11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8fe56b9e6SYuval Mintz #include <asm/byteorder.h> 9fe56b9e6SYuval Mintz #include <linux/delay.h> 10fe56b9e6SYuval Mintz #include <linux/errno.h> 11fe56b9e6SYuval Mintz #include <linux/kernel.h> 12fe56b9e6SYuval Mintz #include <linux/slab.h> 135529bad9STomer Tayar #include <linux/spinlock.h> 14fe56b9e6SYuval Mintz #include <linux/string.h> 150fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 16fe56b9e6SYuval Mintz #include "qed.h" 17cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 1839651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 19fe56b9e6SYuval Mintz #include "qed_hsi.h" 20ee824f4bSOmkar Kulkarni #include "qed_mfw_hsi.h" 21fe56b9e6SYuval Mintz #include "qed_hw.h" 22fe56b9e6SYuval Mintz #include "qed_mcp.h" 23fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 241408cc1fSYuval Mintz #include "qed_sriov.h" 251408cc1fSYuval Mintz 260500a70dSMichal Kalderon #define GRCBASE_MCP 0xe00000 270500a70dSMichal Kalderon 28eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 31fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 346c95dd8fSPrabhakar Kushwaha qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset)), \ 35fe56b9e6SYuval Mintz _val) 36fe56b9e6SYuval Mintz 37fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 386c95dd8fSPrabhakar Kushwaha qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset))) 39fe56b9e6SYuval Mintz 40fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 41fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 42fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 43fe56b9e6SYuval Mintz 44fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 45fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 46fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 47fe56b9e6SYuval Mintz 48fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 49fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 50fe56b9e6SYuval Mintz 51fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 54fe56b9e6SYuval Mintz { 55fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 56fe56b9e6SYuval Mintz return false; 57fe56b9e6SYuval Mintz return true; 58fe56b9e6SYuval Mintz } 59fe56b9e6SYuval Mintz 601a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 61fe56b9e6SYuval Mintz { 62fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 63fe56b9e6SYuval Mintz PUBLIC_PORT); 64fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 67fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 68fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 69fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 70fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 71fe56b9e6SYuval Mintz } 72fe56b9e6SYuval Mintz 731a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 74fe56b9e6SYuval Mintz { 75fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 76fe56b9e6SYuval Mintz u32 tmp, i; 77fe56b9e6SYuval Mintz 78fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 79fe56b9e6SYuval Mintz return; 80fe56b9e6SYuval Mintz 81fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 82fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 83fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 84fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 85fe56b9e6SYuval Mintz 86fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 87fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 88fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 89fe56b9e6SYuval Mintz } 90fe56b9e6SYuval Mintz } 91fe56b9e6SYuval Mintz 924ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 934ed1eea8STomer Tayar struct list_head list; 944ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 954ed1eea8STomer Tayar u16 expected_seq_num; 964ed1eea8STomer Tayar bool b_is_completed; 974ed1eea8STomer Tayar }; 984ed1eea8STomer Tayar 994ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1004ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1014ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1024ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1034ed1eea8STomer Tayar u16 expected_seq_num) 1044ed1eea8STomer Tayar { 1054ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1064ed1eea8STomer Tayar 1074ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1084ed1eea8STomer Tayar if (!p_cmd_elem) 1094ed1eea8STomer Tayar goto out; 1104ed1eea8STomer Tayar 1114ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1124ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1134ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1144ed1eea8STomer Tayar out: 1154ed1eea8STomer Tayar return p_cmd_elem; 1164ed1eea8STomer Tayar } 1174ed1eea8STomer Tayar 1184ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1194ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1204ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1214ed1eea8STomer Tayar { 1224ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1234ed1eea8STomer Tayar kfree(p_cmd_elem); 1244ed1eea8STomer Tayar } 1254ed1eea8STomer Tayar 1264ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1274ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1284ed1eea8STomer Tayar u16 seq_num) 1294ed1eea8STomer Tayar { 1304ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1314ed1eea8STomer Tayar 1324ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1334ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1344ed1eea8STomer Tayar return p_cmd_elem; 1354ed1eea8STomer Tayar } 1364ed1eea8STomer Tayar 1374ed1eea8STomer Tayar return NULL; 1384ed1eea8STomer Tayar } 1394ed1eea8STomer Tayar 140fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 141fe56b9e6SYuval Mintz { 142fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1444ed1eea8STomer Tayar 145fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 146fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1474ed1eea8STomer Tayar 1484ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1494ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1504ed1eea8STomer Tayar p_tmp, 1514ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1524ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 153fe56b9e6SYuval Mintz } 1544ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1554ed1eea8STomer Tayar } 1564ed1eea8STomer Tayar 157fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1583587cb87STomer Tayar p_hwfn->mcp_info = NULL; 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz return 0; 161fe56b9e6SYuval Mintz } 162fe56b9e6SYuval Mintz 163f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 164f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 165f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 166f00d25f3STomer Tayar 1671a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 168fe56b9e6SYuval Mintz { 169fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 170f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 171f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 172fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 173fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 174fe56b9e6SYuval Mintz 175fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 176f00d25f3STomer Tayar if (!p_info->public_base) { 177f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 178f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 179f00d25f3STomer Tayar return -EINVAL; 180f00d25f3STomer Tayar } 181fe56b9e6SYuval Mintz 182fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 183fe56b9e6SYuval Mintz 184f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 185f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 186f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 187f00d25f3STomer Tayar PUBLIC_MFW_MB)); 188f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 189f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 190f00d25f3STomer Tayar p_info->mfw_mb_addr + 191f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 192f00d25f3STomer Tayar sup_msgs)); 193f00d25f3STomer Tayar 194f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 195f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 196f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 197f00d25f3STomer Tayar * data ready indication. 198f00d25f3STomer Tayar */ 199f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 200f00d25f3STomer Tayar msleep(msec); 201f00d25f3STomer Tayar p_info->mfw_mb_length = 202f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 203f00d25f3STomer Tayar p_info->mfw_mb_addr + 204f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 205f00d25f3STomer Tayar } 206f00d25f3STomer Tayar 207f00d25f3STomer Tayar if (!cnt) { 208f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 209f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 210f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 211f00d25f3STomer Tayar return -EBUSY; 212f00d25f3STomer Tayar } 213f00d25f3STomer Tayar 214fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 215fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 216fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 217fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 218fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 219fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 220fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 221fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 222fe56b9e6SYuval Mintz 223fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 224fe56b9e6SYuval Mintz * the first command 225fe56b9e6SYuval Mintz */ 226fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 227fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 228fe56b9e6SYuval Mintz 229fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 230fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 231fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 232fe56b9e6SYuval Mintz 2334ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 234fe56b9e6SYuval Mintz 235fe56b9e6SYuval Mintz return 0; 236fe56b9e6SYuval Mintz } 237fe56b9e6SYuval Mintz 2381a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 239fe56b9e6SYuval Mintz { 240fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 241fe56b9e6SYuval Mintz u32 size; 242fe56b9e6SYuval Mintz 243fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 24460fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 245fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 246fe56b9e6SYuval Mintz goto err; 247fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 248fe56b9e6SYuval Mintz 2494ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2504ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2514ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2524ed1eea8STomer Tayar 2534ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2544ed1eea8STomer Tayar 255fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 256fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 257fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 258fe56b9e6SYuval Mintz * the MCP is not initialized 259fe56b9e6SYuval Mintz */ 260fe56b9e6SYuval Mintz return 0; 261fe56b9e6SYuval Mintz } 262fe56b9e6SYuval Mintz 263fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 26460fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 26583aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 266eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 267fe56b9e6SYuval Mintz goto err; 268fe56b9e6SYuval Mintz 269fe56b9e6SYuval Mintz return 0; 270fe56b9e6SYuval Mintz 271fe56b9e6SYuval Mintz err: 272fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 273fe56b9e6SYuval Mintz return -ENOMEM; 274fe56b9e6SYuval Mintz } 275fe56b9e6SYuval Mintz 2764ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 2774ed1eea8STomer Tayar struct qed_ptt *p_ptt) 2785529bad9STomer Tayar { 2794ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2805529bad9STomer Tayar 2814ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 2824ed1eea8STomer Tayar * time and now. 2835529bad9STomer Tayar */ 2844ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 2854ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 2864ed1eea8STomer Tayar QED_MSG_SP, 2874ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 2884ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 2895529bad9STomer Tayar 2904ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 2914ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2925529bad9STomer Tayar } 2935529bad9STomer Tayar } 2945529bad9STomer Tayar 2951a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 296fe56b9e6SYuval Mintz { 297eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 298fe56b9e6SYuval Mintz int rc = 0; 299fe56b9e6SYuval Mintz 300b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 301b310974eSTomer Tayar DP_NOTICE(p_hwfn, 302b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 303b310974eSTomer Tayar return -EBUSY; 304b310974eSTomer Tayar } 305b310974eSTomer Tayar 3064ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3074ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3084ed1eea8STomer Tayar 3094ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3105529bad9STomer Tayar 311fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3124ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3134ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3144ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 315fe56b9e6SYuval Mintz 316fe56b9e6SYuval Mintz do { 317fe56b9e6SYuval Mintz /* Wait for MFW response */ 318fe56b9e6SYuval Mintz udelay(delay); 319fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 320fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 321fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 322fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 325fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 326fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 327fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 328fe56b9e6SYuval Mintz } else { 329fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 330fe56b9e6SYuval Mintz rc = -EAGAIN; 331fe56b9e6SYuval Mintz } 332fe56b9e6SYuval Mintz 3334ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3345529bad9STomer Tayar 335fe56b9e6SYuval Mintz return rc; 336fe56b9e6SYuval Mintz } 337fe56b9e6SYuval Mintz 3384ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3394ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 340fe56b9e6SYuval Mintz { 3414ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3424ed1eea8STomer Tayar 3434ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3444ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3454ed1eea8STomer Tayar */ 3464ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3474ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3484ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3494ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3504ed1eea8STomer Tayar } 3514ed1eea8STomer Tayar 3524ed1eea8STomer Tayar return false; 3534ed1eea8STomer Tayar } 3544ed1eea8STomer Tayar 3554ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3564ed1eea8STomer Tayar static int 3574ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3584ed1eea8STomer Tayar { 3594ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3604ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3614ed1eea8STomer Tayar u32 mcp_resp; 3624ed1eea8STomer Tayar u16 seq_num; 3634ed1eea8STomer Tayar 3644ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3654ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3664ed1eea8STomer Tayar 3674ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3684ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3694ed1eea8STomer Tayar return -EAGAIN; 3704ed1eea8STomer Tayar 3714ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3724ed1eea8STomer Tayar if (!p_cmd_elem) { 3734ed1eea8STomer Tayar DP_ERR(p_hwfn, 3744ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3754ed1eea8STomer Tayar seq_num); 3764ed1eea8STomer Tayar return -EINVAL; 3774ed1eea8STomer Tayar } 3784ed1eea8STomer Tayar 3794ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3804ed1eea8STomer Tayar 3814ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3824ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 3834ed1eea8STomer Tayar 3844ed1eea8STomer Tayar /* Get the MFW param */ 3854ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 3864ed1eea8STomer Tayar 3874ed1eea8STomer Tayar /* Get the union data */ 3886c95dd8fSPrabhakar Kushwaha if (p_mb_params->p_data_dst && p_mb_params->data_dst_size) { 3894ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3904ed1eea8STomer Tayar offsetof(struct public_drv_mb, 3914ed1eea8STomer Tayar union_data); 3924ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3932f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 3944ed1eea8STomer Tayar } 3954ed1eea8STomer Tayar 3964ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 3974ed1eea8STomer Tayar 3984ed1eea8STomer Tayar return 0; 3994ed1eea8STomer Tayar } 4004ed1eea8STomer Tayar 4014ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4024ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4034ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4044ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4054ed1eea8STomer Tayar u16 seq_num) 4064ed1eea8STomer Tayar { 4074ed1eea8STomer Tayar union drv_union_data union_data; 4084ed1eea8STomer Tayar u32 union_data_addr; 4094ed1eea8STomer Tayar 4104ed1eea8STomer Tayar /* Set the union data */ 4114ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4124ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4134ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4146c95dd8fSPrabhakar Kushwaha if (p_mb_params->p_data_src && p_mb_params->data_src_size) 4154ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4162f67af8cSTomer Tayar p_mb_params->data_src_size); 4174ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4184ed1eea8STomer Tayar sizeof(union_data)); 4194ed1eea8STomer Tayar 4204ed1eea8STomer Tayar /* Set the drv param */ 4214ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4224ed1eea8STomer Tayar 4234ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4244ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4254ed1eea8STomer Tayar 4264ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4274ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4284ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4294ed1eea8STomer Tayar } 4304ed1eea8STomer Tayar 431b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 432b310974eSTomer Tayar { 433b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 434b310974eSTomer Tayar 435b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 436b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 437b310974eSTomer Tayar } 438b310974eSTomer Tayar 439b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 440b310974eSTomer Tayar struct qed_ptt *p_ptt) 441b310974eSTomer Tayar { 442b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 443b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 444b310974eSTomer Tayar 445b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 446b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 447b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 448b310974eSTomer Tayar udelay(delay); 449b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 450b310974eSTomer Tayar udelay(delay); 451b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 452b310974eSTomer Tayar 453b310974eSTomer Tayar DP_NOTICE(p_hwfn, 454b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 455b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 456b310974eSTomer Tayar } 457b310974eSTomer Tayar 4584ed1eea8STomer Tayar static int 4594ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4604ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4614ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 462eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4634ed1eea8STomer Tayar { 464eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4654ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4664ed1eea8STomer Tayar u16 seq_num; 467fe56b9e6SYuval Mintz int rc = 0; 468fe56b9e6SYuval Mintz 4694ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 470fe56b9e6SYuval Mintz do { 4714ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4724ed1eea8STomer Tayar * pending command is completed during this iteration. 4734ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4744ed1eea8STomer Tayar */ 4754ed1eea8STomer Tayar 4764ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4774ed1eea8STomer Tayar 4784ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4794ed1eea8STomer Tayar break; 4804ed1eea8STomer Tayar 4814ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4824ed1eea8STomer Tayar if (!rc) 4834ed1eea8STomer Tayar break; 4844ed1eea8STomer Tayar else if (rc != -EAGAIN) 4854ed1eea8STomer Tayar goto err; 4864ed1eea8STomer Tayar 4874ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 488eaa50fc5STomer Tayar 489eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 490eaa50fc5STomer Tayar msleep(msecs); 491eaa50fc5STomer Tayar else 492eaa50fc5STomer Tayar udelay(usecs); 4934ed1eea8STomer Tayar } while (++cnt < max_retries); 494fe56b9e6SYuval Mintz 4954ed1eea8STomer Tayar if (cnt >= max_retries) { 4964ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4974ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4984ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4994ed1eea8STomer Tayar return -EAGAIN; 500fe56b9e6SYuval Mintz } 5014ed1eea8STomer Tayar 5024ed1eea8STomer Tayar /* Send the mailbox command */ 5034ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5044ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5054ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 506c8004600SDan Carpenter if (!p_cmd_elem) { 507c8004600SDan Carpenter rc = -ENOMEM; 5084ed1eea8STomer Tayar goto err; 509c8004600SDan Carpenter } 5104ed1eea8STomer Tayar 5114ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5124ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5134ed1eea8STomer Tayar 5144ed1eea8STomer Tayar /* Wait for the MFW response */ 5154ed1eea8STomer Tayar do { 5164ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5174ed1eea8STomer Tayar * command is completed during this iteration. 5184ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5194ed1eea8STomer Tayar */ 5204ed1eea8STomer Tayar 521eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 522eaa50fc5STomer Tayar msleep(msecs); 523eaa50fc5STomer Tayar else 524eaa50fc5STomer Tayar udelay(usecs); 525eaa50fc5STomer Tayar 5264ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5274ed1eea8STomer Tayar 5284ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5294ed1eea8STomer Tayar break; 5304ed1eea8STomer Tayar 5314ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5324ed1eea8STomer Tayar if (!rc) 5334ed1eea8STomer Tayar break; 5344ed1eea8STomer Tayar else if (rc != -EAGAIN) 5354ed1eea8STomer Tayar goto err; 5364ed1eea8STomer Tayar 5374ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5384ed1eea8STomer Tayar } while (++cnt < max_retries); 5394ed1eea8STomer Tayar 5404ed1eea8STomer Tayar if (cnt >= max_retries) { 5414ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5424ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5434ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 544b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5454ed1eea8STomer Tayar 5464ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5474ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5484ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5494ed1eea8STomer Tayar 550b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 551b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 552b310974eSTomer Tayar 5532ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, 5542ec276d5SIgor Russkikh QED_HW_ERR_MFW_RESP_FAIL, NULL); 5554ed1eea8STomer Tayar return -EAGAIN; 5564ed1eea8STomer Tayar } 5574ed1eea8STomer Tayar 5584ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5594ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5604ed1eea8STomer Tayar 5614ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5624ed1eea8STomer Tayar QED_MSG_SP, 5634ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5644ed1eea8STomer Tayar p_mb_params->mcp_resp, 5654ed1eea8STomer Tayar p_mb_params->mcp_param, 566eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5674ed1eea8STomer Tayar 5684ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5694ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5704ed1eea8STomer Tayar 5714ed1eea8STomer Tayar return 0; 5724ed1eea8STomer Tayar 5734ed1eea8STomer Tayar err: 5744ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 575fe56b9e6SYuval Mintz return rc; 576fe56b9e6SYuval Mintz } 577fe56b9e6SYuval Mintz 5785529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 579fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5805529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 581fe56b9e6SYuval Mintz { 5822f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5834ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 584eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 585fe56b9e6SYuval Mintz 586fe56b9e6SYuval Mintz /* MCP not initialized */ 587fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 588fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 589fe56b9e6SYuval Mintz return -EBUSY; 590fe56b9e6SYuval Mintz } 591fe56b9e6SYuval Mintz 592b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 593b310974eSTomer Tayar DP_NOTICE(p_hwfn, 594b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 595b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 596b310974eSTomer Tayar return -EBUSY; 597b310974eSTomer Tayar } 598b310974eSTomer Tayar 5992f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 6002f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6012f67af8cSTomer Tayar DP_ERR(p_hwfn, 6022f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6032f67af8cSTomer Tayar p_mb_params->data_src_size, 6042f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6052f67af8cSTomer Tayar return -EINVAL; 6062f67af8cSTomer Tayar } 6072f67af8cSTomer Tayar 608eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 609eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 610eaa50fc5STomer Tayar usecs *= 1000; 611eaa50fc5STomer Tayar } 612eaa50fc5STomer Tayar 6134ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 614eaa50fc5STomer Tayar usecs); 615fe56b9e6SYuval Mintz } 616fe56b9e6SYuval Mintz 6175529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6185529bad9STomer Tayar struct qed_ptt *p_ptt, 6195529bad9STomer Tayar u32 cmd, 6205529bad9STomer Tayar u32 param, 6215529bad9STomer Tayar u32 *o_mcp_resp, 6225529bad9STomer Tayar u32 *o_mcp_param) 623fe56b9e6SYuval Mintz { 6245529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6255529bad9STomer Tayar int rc; 626fe56b9e6SYuval Mintz 6275529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6285529bad9STomer Tayar mb_params.cmd = cmd; 6295529bad9STomer Tayar mb_params.param = param; 63014d39648SMintz, Yuval 6315529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6325529bad9STomer Tayar if (rc) 6335529bad9STomer Tayar return rc; 6345529bad9STomer Tayar 6355529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6365529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6375529bad9STomer Tayar 6385529bad9STomer Tayar return 0; 639fe56b9e6SYuval Mintz } 640fe56b9e6SYuval Mintz 641bf774d14SYueHaibing static int 642bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 64362e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 64462e4d438SSudarsana Reddy Kalluru u32 cmd, 64562e4d438SSudarsana Reddy Kalluru u32 param, 64662e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 64762e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 64862e4d438SSudarsana Reddy Kalluru { 64962e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 65062e4d438SSudarsana Reddy Kalluru int rc; 65162e4d438SSudarsana Reddy Kalluru 65262e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 65362e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 65462e4d438SSudarsana Reddy Kalluru mb_params.param = param; 65562e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 65662e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 65762e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 65862e4d438SSudarsana Reddy Kalluru if (rc) 65962e4d438SSudarsana Reddy Kalluru return rc; 66062e4d438SSudarsana Reddy Kalluru 66162e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 66262e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 66362e4d438SSudarsana Reddy Kalluru 6645e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6655e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6665e7ba042SDenis Bolotin 66762e4d438SSudarsana Reddy Kalluru return 0; 66862e4d438SSudarsana Reddy Kalluru } 66962e4d438SSudarsana Reddy Kalluru 6704102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6714102426fSTomer Tayar struct qed_ptt *p_ptt, 6724102426fSTomer Tayar u32 cmd, 6734102426fSTomer Tayar u32 param, 6744102426fSTomer Tayar u32 *o_mcp_resp, 6756c95dd8fSPrabhakar Kushwaha u32 *o_mcp_param, 6766c95dd8fSPrabhakar Kushwaha u32 *o_txn_size, u32 *o_buf, bool b_can_sleep) 6774102426fSTomer Tayar { 6784102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6792f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 6804102426fSTomer Tayar int rc; 6814102426fSTomer Tayar 6824102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6834102426fSTomer Tayar mb_params.cmd = cmd; 6844102426fSTomer Tayar mb_params.param = param; 6852f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 6862f67af8cSTomer Tayar 6872f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 6882f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 6896c95dd8fSPrabhakar Kushwaha if (b_can_sleep) 6906c95dd8fSPrabhakar Kushwaha mb_params.flags = QED_MB_FLAG_CAN_SLEEP; 6912f67af8cSTomer Tayar 6924102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6934102426fSTomer Tayar if (rc) 6944102426fSTomer Tayar return rc; 6954102426fSTomer Tayar 6964102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6974102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 6984102426fSTomer Tayar 6994102426fSTomer Tayar *o_txn_size = *o_mcp_param; 7002f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 7014102426fSTomer Tayar 7024102426fSTomer Tayar return 0; 7034102426fSTomer Tayar } 7044102426fSTomer Tayar 7055d24bcf1STomer Tayar static bool 7065d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7075d24bcf1STomer Tayar u8 exist_drv_role, 7085d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 709fe56b9e6SYuval Mintz { 7105d24bcf1STomer Tayar bool can_force_load = false; 7115d24bcf1STomer Tayar 7125d24bcf1STomer Tayar switch (override_force_load) { 7135d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7145d24bcf1STomer Tayar can_force_load = true; 7155d24bcf1STomer Tayar break; 7165d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7175d24bcf1STomer Tayar can_force_load = false; 7185d24bcf1STomer Tayar break; 7195d24bcf1STomer Tayar default: 7205d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7215d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7225d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7235d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7245d24bcf1STomer Tayar break; 7255d24bcf1STomer Tayar } 7265d24bcf1STomer Tayar 7275d24bcf1STomer Tayar return can_force_load; 7285d24bcf1STomer Tayar } 7295d24bcf1STomer Tayar 7305d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7315d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7325d24bcf1STomer Tayar { 7335d24bcf1STomer Tayar u32 resp = 0, param = 0; 734fe56b9e6SYuval Mintz int rc; 735fe56b9e6SYuval Mintz 7365d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7375d24bcf1STomer Tayar &resp, ¶m); 7385d24bcf1STomer Tayar if (rc) 7395d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7405d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 741fe56b9e6SYuval Mintz 742fe56b9e6SYuval Mintz return rc; 743fe56b9e6SYuval Mintz } 744fe56b9e6SYuval Mintz 7455d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7465d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7475d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7485d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7495d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7505d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7515529bad9STomer Tayar 7525d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7535d24bcf1STomer Tayar { 7545d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7555d24bcf1STomer Tayar 7565d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7575d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7585d24bcf1STomer Tayar 7595d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7605d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7615d24bcf1STomer Tayar 7625d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7635d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7645d24bcf1STomer Tayar 7655d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7665d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7675d24bcf1STomer Tayar 7685d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7695d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7705d24bcf1STomer Tayar 7715d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7725d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7735d24bcf1STomer Tayar 7745d24bcf1STomer Tayar return config_bitmap; 7755d24bcf1STomer Tayar } 7765d24bcf1STomer Tayar 7775d24bcf1STomer Tayar struct qed_load_req_in_params { 7785d24bcf1STomer Tayar u8 hsi_ver; 7795d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7805d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7815d24bcf1STomer Tayar u32 drv_ver_0; 7825d24bcf1STomer Tayar u32 drv_ver_1; 7835d24bcf1STomer Tayar u32 fw_ver; 7845d24bcf1STomer Tayar u8 drv_role; 7855d24bcf1STomer Tayar u8 timeout_val; 7865d24bcf1STomer Tayar u8 force_cmd; 7875d24bcf1STomer Tayar bool avoid_eng_reset; 7885d24bcf1STomer Tayar }; 7895d24bcf1STomer Tayar 7905d24bcf1STomer Tayar struct qed_load_req_out_params { 7915d24bcf1STomer Tayar u32 load_code; 7925d24bcf1STomer Tayar u32 exist_drv_ver_0; 7935d24bcf1STomer Tayar u32 exist_drv_ver_1; 7945d24bcf1STomer Tayar u32 exist_fw_ver; 7955d24bcf1STomer Tayar u8 exist_drv_role; 7965d24bcf1STomer Tayar u8 mfw_hsi_ver; 7975d24bcf1STomer Tayar bool drv_exists; 7985d24bcf1STomer Tayar }; 7995d24bcf1STomer Tayar 8005d24bcf1STomer Tayar static int 8015d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8025d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8035d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8045d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8055d24bcf1STomer Tayar { 8065d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8075d24bcf1STomer Tayar struct load_req_stc load_req; 8085d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8095d24bcf1STomer Tayar u32 hsi_ver; 8105d24bcf1STomer Tayar int rc; 8115d24bcf1STomer Tayar 8125d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8135d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8145d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8155d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8165d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8175d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8185d24bcf1STomer Tayar p_in_params->timeout_val); 8195d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8205d24bcf1STomer Tayar p_in_params->force_cmd); 8215d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8225d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8235d24bcf1STomer Tayar 8245d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8255d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8265d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8275d24bcf1STomer Tayar 8285d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8295d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8305d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8315d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8325d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8335d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8345d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 835b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8365d24bcf1STomer Tayar 8375d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8385d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8395d24bcf1STomer Tayar mb_params.param, 8405d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8415d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8425d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8435d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8445d24bcf1STomer Tayar 8455d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8465d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8475d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8485d24bcf1STomer Tayar load_req.drv_ver_0, 8495d24bcf1STomer Tayar load_req.drv_ver_1, 8505d24bcf1STomer Tayar load_req.fw_ver, 8515d24bcf1STomer Tayar load_req.misc0, 8525d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8535d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8545d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8555d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8565d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8575d24bcf1STomer Tayar } 8585d24bcf1STomer Tayar 8595d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8605d24bcf1STomer Tayar if (rc) { 8615d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8625d24bcf1STomer Tayar return rc; 8635d24bcf1STomer Tayar } 8645d24bcf1STomer Tayar 8655d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8665d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8675d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8685d24bcf1STomer Tayar 8695d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8705d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8715d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8725d24bcf1STomer Tayar QED_MSG_SP, 8735d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8745d24bcf1STomer Tayar load_rsp.drv_ver_0, 8755d24bcf1STomer Tayar load_rsp.drv_ver_1, 8765d24bcf1STomer Tayar load_rsp.fw_ver, 8775d24bcf1STomer Tayar load_rsp.misc0, 8785d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8795d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8805d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8815d24bcf1STomer Tayar 8825d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 8835d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 8845d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 8855d24bcf1STomer Tayar p_out_params->exist_drv_role = 8865d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 8875d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 8885d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 8895d24bcf1STomer Tayar p_out_params->drv_exists = 8905d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 8915d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 8925d24bcf1STomer Tayar } 8935d24bcf1STomer Tayar 8945d24bcf1STomer Tayar return 0; 8955d24bcf1STomer Tayar } 8965d24bcf1STomer Tayar 8975d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 8985d24bcf1STomer Tayar enum qed_drv_role drv_role, 8995d24bcf1STomer Tayar u8 *p_mfw_drv_role) 9005d24bcf1STomer Tayar { 9015d24bcf1STomer Tayar switch (drv_role) { 9025d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 9035d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9045d24bcf1STomer Tayar break; 9055d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9065d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9075d24bcf1STomer Tayar break; 9085d24bcf1STomer Tayar default: 9095d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9105d24bcf1STomer Tayar return -EINVAL; 9115d24bcf1STomer Tayar } 9125d24bcf1STomer Tayar 9135d24bcf1STomer Tayar return 0; 9145d24bcf1STomer Tayar } 9155d24bcf1STomer Tayar 9165d24bcf1STomer Tayar enum qed_load_req_force { 9175d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9185d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9195d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9205d24bcf1STomer Tayar }; 9215d24bcf1STomer Tayar 9225d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9235d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9245d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9255d24bcf1STomer Tayar { 9265d24bcf1STomer Tayar switch (force_cmd) { 9275d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9285d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9295d24bcf1STomer Tayar break; 9305d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9315d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9325d24bcf1STomer Tayar break; 9335d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9345d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9355d24bcf1STomer Tayar break; 9365d24bcf1STomer Tayar } 9375d24bcf1STomer Tayar } 9385d24bcf1STomer Tayar 9395d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9405d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9415d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9425d24bcf1STomer Tayar { 9435d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9445d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9455d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9465d24bcf1STomer Tayar int rc; 9475d24bcf1STomer Tayar 9485d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9495d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9505d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9515d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9525d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9535d24bcf1STomer Tayar if (rc) 9545d24bcf1STomer Tayar return rc; 9555d24bcf1STomer Tayar 9565d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9575d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9585d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9595d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9605d24bcf1STomer Tayar 9615d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9625d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9635d24bcf1STomer Tayar 9645d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9655d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9665d24bcf1STomer Tayar if (rc) 9675d24bcf1STomer Tayar return rc; 9685d24bcf1STomer Tayar 9695d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9705d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9715d24bcf1STomer Tayar * - MFW responds that a force load request is required 972fe56b9e6SYuval Mintz */ 9735d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9745d24bcf1STomer Tayar DP_INFO(p_hwfn, 9755d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9765d24bcf1STomer Tayar 9775d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9785d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9795d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9805d24bcf1STomer Tayar if (rc) 9815d24bcf1STomer Tayar return rc; 9825d24bcf1STomer Tayar } else if (out_params.load_code == 9835d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 9845d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 9855d24bcf1STomer Tayar out_params.exist_drv_role, 9865d24bcf1STomer Tayar p_params->override_force_load)) { 9875d24bcf1STomer Tayar DP_INFO(p_hwfn, 9885d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 9895d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9905d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9915d24bcf1STomer Tayar out_params.exist_drv_role, 9925d24bcf1STomer Tayar out_params.exist_fw_ver, 9935d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9945d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9955d24bcf1STomer Tayar 9965d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9975d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9985d24bcf1STomer Tayar &mfw_force_cmd); 9995d24bcf1STomer Tayar 10005d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 10015d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10025d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10035d24bcf1STomer Tayar &out_params); 10045d24bcf1STomer Tayar if (rc) 10055d24bcf1STomer Tayar return rc; 10065d24bcf1STomer Tayar } else { 10075d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10085d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10095d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10105d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10115d24bcf1STomer Tayar out_params.exist_drv_role, 10125d24bcf1STomer Tayar out_params.exist_fw_ver, 10135d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10145d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10155d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10165d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10175d24bcf1STomer Tayar 10185d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1019fe56b9e6SYuval Mintz return -EBUSY; 1020fe56b9e6SYuval Mintz } 10215d24bcf1STomer Tayar } 10225d24bcf1STomer Tayar 10235d24bcf1STomer Tayar /* Now handle the other types of responses. 10245d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10255d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10265d24bcf1STomer Tayar */ 10275d24bcf1STomer Tayar switch (out_params.load_code) { 10285d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10295d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10305d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10315d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10325d24bcf1STomer Tayar out_params.drv_exists) { 10335d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10345d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10355d24bcf1STomer Tayar */ 10365d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10375d24bcf1STomer Tayar "PF is already loaded\n"); 10385d24bcf1STomer Tayar return -EINVAL; 10395d24bcf1STomer Tayar } 10405d24bcf1STomer Tayar break; 10415d24bcf1STomer Tayar default: 10425d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10435d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10445d24bcf1STomer Tayar out_params.load_code); 10455d24bcf1STomer Tayar return -EBUSY; 10465d24bcf1STomer Tayar } 10475d24bcf1STomer Tayar 10485d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1049fe56b9e6SYuval Mintz 1050fe56b9e6SYuval Mintz return 0; 1051fe56b9e6SYuval Mintz } 1052fe56b9e6SYuval Mintz 1053666db486STomer Tayar int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1054666db486STomer Tayar { 1055666db486STomer Tayar u32 resp = 0, param = 0; 1056666db486STomer Tayar int rc; 1057666db486STomer Tayar 1058666db486STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp, 1059666db486STomer Tayar ¶m); 1060666db486STomer Tayar if (rc) { 1061666db486STomer Tayar DP_NOTICE(p_hwfn, 1062666db486STomer Tayar "Failed to send a LOAD_DONE command, rc = %d\n", rc); 1063666db486STomer Tayar return rc; 1064666db486STomer Tayar } 1065666db486STomer Tayar 1066666db486STomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1067666db486STomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1068666db486STomer Tayar DP_NOTICE(p_hwfn, 1069666db486STomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1070666db486STomer Tayar 1071666db486STomer Tayar return 0; 1072666db486STomer Tayar } 1073666db486STomer Tayar 10741226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10751226337aSTomer Tayar { 1076eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1077eaa50fc5STomer Tayar u32 wol_param; 10781226337aSTomer Tayar 10791226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 10801226337aSTomer Tayar case QED_OV_WOL_DISABLED: 10811226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 10821226337aSTomer Tayar break; 10831226337aSTomer Tayar case QED_OV_WOL_ENABLED: 10841226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 10851226337aSTomer Tayar break; 10861226337aSTomer Tayar default: 10871226337aSTomer Tayar DP_NOTICE(p_hwfn, 10881226337aSTomer Tayar "Unknown WoL configuration %02x\n", 10891226337aSTomer Tayar p_hwfn->cdev->wol_config); 1090df561f66SGustavo A. R. Silva fallthrough; 10911226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 10921226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 10931226337aSTomer Tayar } 10941226337aSTomer Tayar 1095eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1096eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1097eaa50fc5STomer Tayar mb_params.param = wol_param; 1098b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1099eaa50fc5STomer Tayar 1100eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11011226337aSTomer Tayar } 11021226337aSTomer Tayar 11031226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11041226337aSTomer Tayar { 11051226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11061226337aSTomer Tayar struct mcp_mac wol_mac; 11071226337aSTomer Tayar 11081226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11091226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11101226337aSTomer Tayar 11111226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11121226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11131226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11141226337aSTomer Tayar 11151226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11161226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11171226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11181226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11191226337aSTomer Tayar 11201226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11211226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11221226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11231226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11241226337aSTomer Tayar 11251226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11261226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11271226337aSTomer Tayar } 11281226337aSTomer Tayar 11291226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11301226337aSTomer Tayar } 11311226337aSTomer Tayar 11320b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11330b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11340b55e27dSYuval Mintz { 11350b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11360b55e27dSYuval Mintz PUBLIC_PATH); 11370b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11380b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11390b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11400b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11410b55e27dSYuval Mintz int i; 11420b55e27dSYuval Mintz 11430b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11440b55e27dSYuval Mintz QED_MSG_SP, 11450b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11460b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11470b55e27dSYuval Mintz 11480b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11490b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11500b55e27dSYuval Mintz path_addr + 11510b55e27dSYuval Mintz offsetof(struct public_path, 11520b55e27dSYuval Mintz mcp_vf_disabled) + 11530b55e27dSYuval Mintz sizeof(u32) * i); 11540b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11550b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11560b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11570b55e27dSYuval Mintz } 11580b55e27dSYuval Mintz 11590b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11600b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11610b55e27dSYuval Mintz } 11620b55e27dSYuval Mintz 11630b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11640b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11650b55e27dSYuval Mintz { 11660b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11670b55e27dSYuval Mintz PUBLIC_FUNC); 11680b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11690b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11700b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11710b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11720b55e27dSYuval Mintz int rc; 11730b55e27dSYuval Mintz int i; 11740b55e27dSYuval Mintz 11750b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11760b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11770b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 11780b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 11790b55e27dSYuval Mintz 11800b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 11810b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 11822f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 11832f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 11840b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11850b55e27dSYuval Mintz if (rc) { 11860b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 11870b55e27dSYuval Mintz return -EBUSY; 11880b55e27dSYuval Mintz } 11890b55e27dSYuval Mintz 11900b55e27dSYuval Mintz /* Clear the ACK bits */ 11910b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11920b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 11930b55e27dSYuval Mintz func_addr + 11940b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 11950b55e27dSYuval Mintz i * sizeof(u32), 0); 11960b55e27dSYuval Mintz 11970b55e27dSYuval Mintz return rc; 11980b55e27dSYuval Mintz } 11990b55e27dSYuval Mintz 1200334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1201334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1202334c03b5SZvi Nachmani { 1203334c03b5SZvi Nachmani u32 transceiver_state; 1204334c03b5SZvi Nachmani 1205334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1206334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1207334c03b5SZvi Nachmani offsetof(struct public_port, 1208334c03b5SZvi Nachmani transceiver_data)); 1209334c03b5SZvi Nachmani 1210334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1211334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1212334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1213334c03b5SZvi Nachmani transceiver_state, 1214334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12151a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1216334c03b5SZvi Nachmani 1217334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1218351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1219334c03b5SZvi Nachmani 1220351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1221334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1222334c03b5SZvi Nachmani else 1223334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1224334c03b5SZvi Nachmani } 1225334c03b5SZvi Nachmani 1226645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1227645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1228645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1229645874e5SSudarsana Reddy Kalluru { 1230645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1231645874e5SSudarsana Reddy Kalluru 1232645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1233645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1234645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1235645874e5SSudarsana Reddy Kalluru p_ptt, 1236645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1237645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1238645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1239645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1240645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1241645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1242645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1243645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1244645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1245645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1246645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1247645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1248645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1249645874e5SSudarsana Reddy Kalluru } 1250645874e5SSudarsana Reddy Kalluru 1251e40a826aSSudarsana Reddy Kalluru static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1252e40a826aSSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1253e40a826aSSudarsana Reddy Kalluru struct public_func *p_data, int pfid) 1254e40a826aSSudarsana Reddy Kalluru { 1255e40a826aSSudarsana Reddy Kalluru u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1256e40a826aSSudarsana Reddy Kalluru PUBLIC_FUNC); 1257e40a826aSSudarsana Reddy Kalluru u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1258e40a826aSSudarsana Reddy Kalluru u32 func_addr; 1259e40a826aSSudarsana Reddy Kalluru u32 i, size; 1260e40a826aSSudarsana Reddy Kalluru 1261e40a826aSSudarsana Reddy Kalluru func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1262e40a826aSSudarsana Reddy Kalluru memset(p_data, 0, sizeof(*p_data)); 1263e40a826aSSudarsana Reddy Kalluru 1264e40a826aSSudarsana Reddy Kalluru size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1265e40a826aSSudarsana Reddy Kalluru for (i = 0; i < size / sizeof(u32); i++) 1266e40a826aSSudarsana Reddy Kalluru ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1267e40a826aSSudarsana Reddy Kalluru func_addr + (i << 2)); 1268e40a826aSSudarsana Reddy Kalluru return size; 1269e40a826aSSudarsana Reddy Kalluru } 1270e40a826aSSudarsana Reddy Kalluru 1271e40a826aSSudarsana Reddy Kalluru static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1272e40a826aSSudarsana Reddy Kalluru struct public_func *p_shmem_info) 1273e40a826aSSudarsana Reddy Kalluru { 1274e40a826aSSudarsana Reddy Kalluru struct qed_mcp_function_info *p_info; 1275e40a826aSSudarsana Reddy Kalluru 1276e40a826aSSudarsana Reddy Kalluru p_info = &p_hwfn->mcp_info->func_info; 1277e40a826aSSudarsana Reddy Kalluru 1278e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1279e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MIN_BW); 1280e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1281e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1282e40a826aSSudarsana Reddy Kalluru "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1283e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min); 1284e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = 1; 1285e40a826aSSudarsana Reddy Kalluru } 1286e40a826aSSudarsana Reddy Kalluru 1287e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1288e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MAX_BW); 1289e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1290e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1291e40a826aSSudarsana Reddy Kalluru "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1292e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max); 1293e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = 100; 1294e40a826aSSudarsana Reddy Kalluru } 1295e40a826aSSudarsana Reddy Kalluru } 1296e40a826aSSudarsana Reddy Kalluru 1297cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 12981a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1299cc875c2eSYuval Mintz { 1300cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1301a64b02d5SManish Chopra u8 max_bw, min_bw; 1302cc875c2eSYuval Mintz u32 status = 0; 1303cc875c2eSYuval Mintz 130465ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 130565ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 130665ed2ffdSMintz, Yuval 1307cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1308cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1309cc875c2eSYuval Mintz if (!b_reset) { 1310cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1311cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1312cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1313cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1314cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1315cc875c2eSYuval Mintz status, 1316cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 13171a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1318cc875c2eSYuval Mintz } else { 1319cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1320cc875c2eSYuval Mintz "Resetting link indications\n"); 132165ed2ffdSMintz, Yuval goto out; 1322cc875c2eSYuval Mintz } 1323cc875c2eSYuval Mintz 1324e40a826aSSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) { 1325e40a826aSSudarsana Reddy Kalluru /* Link indication with modern MFW arrives as per-PF 1326e40a826aSSudarsana Reddy Kalluru * indication. 1327e40a826aSSudarsana Reddy Kalluru */ 1328e40a826aSSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & 1329e40a826aSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1330e40a826aSSudarsana Reddy Kalluru struct public_func shmem_info; 1331e40a826aSSudarsana Reddy Kalluru 1332e40a826aSSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1333e40a826aSSudarsana Reddy Kalluru MCP_PF_ID(p_hwfn)); 1334e40a826aSSudarsana Reddy Kalluru p_link->link_up = !!(shmem_info.status & 1335e40a826aSSudarsana Reddy Kalluru FUNC_STATUS_VIRTUAL_LINK_UP); 1336e40a826aSSudarsana Reddy Kalluru qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1337e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1338e40a826aSSudarsana Reddy Kalluru "Virtual link_up = %d\n", p_link->link_up); 1339e40a826aSSudarsana Reddy Kalluru } else { 1340cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1341e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1342e40a826aSSudarsana Reddy Kalluru "Physical link_up = %d\n", p_link->link_up); 1343e40a826aSSudarsana Reddy Kalluru } 1344e40a826aSSudarsana Reddy Kalluru } else { 1345fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1346e40a826aSSudarsana Reddy Kalluru } 1347cc875c2eSYuval Mintz 1348cc875c2eSYuval Mintz p_link->full_duplex = true; 1349cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1350cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1351cc875c2eSYuval Mintz p_link->speed = 100000; 1352cc875c2eSYuval Mintz break; 1353cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1354cc875c2eSYuval Mintz p_link->speed = 50000; 1355cc875c2eSYuval Mintz break; 1356cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1357cc875c2eSYuval Mintz p_link->speed = 40000; 1358cc875c2eSYuval Mintz break; 1359cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1360cc875c2eSYuval Mintz p_link->speed = 25000; 1361cc875c2eSYuval Mintz break; 1362cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1363cc875c2eSYuval Mintz p_link->speed = 20000; 1364cc875c2eSYuval Mintz break; 1365cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1366cc875c2eSYuval Mintz p_link->speed = 10000; 1367cc875c2eSYuval Mintz break; 1368cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1369cc875c2eSYuval Mintz p_link->full_duplex = false; 1370df561f66SGustavo A. R. Silva fallthrough; 1371cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1372cc875c2eSYuval Mintz p_link->speed = 1000; 1373cc875c2eSYuval Mintz break; 1374cc875c2eSYuval Mintz default: 1375cc875c2eSYuval Mintz p_link->speed = 0; 137658874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1377cc875c2eSYuval Mintz } 1378cc875c2eSYuval Mintz 13794b01e519SManish Chopra if (p_link->link_up && p_link->speed) 13804b01e519SManish Chopra p_link->line_speed = p_link->speed; 13814b01e519SManish Chopra else 13824b01e519SManish Chopra p_link->line_speed = 0; 13834b01e519SManish Chopra 13844b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1385a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 13864b01e519SManish Chopra 1387a64b02d5SManish Chopra /* Max bandwidth configuration */ 13884b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1389cc875c2eSYuval Mintz 1390a64b02d5SManish Chopra /* Min bandwidth configuration */ 1391a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 13926f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 13936f437d43SMintz, Yuval p_link->min_pf_rate); 1394a64b02d5SManish Chopra 1395cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1396cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1397cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1398cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1399cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1400cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1401cc875c2eSYuval Mintz 1402cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1403cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1404cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1405cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1406cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1407cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1408cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1409cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1410cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1411cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1412cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1413cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1414cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1415054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1416054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1417054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1418cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1419cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1420cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1421cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1422cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1423cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1424cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1425cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1426cc875c2eSYuval Mintz 1427cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1428cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1429cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1430cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1431cc875c2eSYuval Mintz 1432cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1433cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1434cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1435cc875c2eSYuval Mintz break; 1436cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1437cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1438cc875c2eSYuval Mintz break; 1439cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1440cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1441cc875c2eSYuval Mintz break; 1442cc875c2eSYuval Mintz default: 1443cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1444cc875c2eSYuval Mintz } 1445cc875c2eSYuval Mintz 1446cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1447cc875c2eSYuval Mintz 1448645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1449645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1450645874e5SSudarsana Reddy Kalluru 1451ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1452ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1453ae7e6937SAlexander Lobakin switch (status & LINK_STATUS_FEC_MODE_MASK) { 1454ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_NONE: 1455ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_NONE; 1456ae7e6937SAlexander Lobakin break; 1457ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_FIRECODE_CL74: 1458ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_FIRECODE; 1459ae7e6937SAlexander Lobakin break; 1460ae7e6937SAlexander Lobakin case LINK_STATUS_FEC_MODE_RS_CL91: 1461ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_RS; 1462ae7e6937SAlexander Lobakin break; 1463ae7e6937SAlexander Lobakin default: 1464ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_AUTO; 1465ae7e6937SAlexander Lobakin } 1466ae7e6937SAlexander Lobakin } else { 1467ae7e6937SAlexander Lobakin p_link->fec_active = QED_FEC_MODE_UNSUPPORTED; 1468ae7e6937SAlexander Lobakin } 1469ae7e6937SAlexander Lobakin 1470706d0891SRahul Verma qed_link_update(p_hwfn, p_ptt); 147165ed2ffdSMintz, Yuval out: 147265ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1473cc875c2eSYuval Mintz } 1474cc875c2eSYuval Mintz 1475351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1476cc875c2eSYuval Mintz { 1477cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 14785529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 14792f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1480ae7e6937SAlexander Lobakin u32 cmd, fec_bit = 0; 148199785a87SAlexander Lobakin u32 val, ext_speed; 1482cc875c2eSYuval Mintz int rc = 0; 1483cc875c2eSYuval Mintz 1484cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 14852f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1486cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1487cc875c2eSYuval Mintz if (!params->speed.autoneg) 14882f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 14892f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 14902f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 14912f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 14922f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 14932f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 14944ad95a93SSudarsana Reddy Kalluru 14954ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 14964ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 14974ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 14984ad95a93SSudarsana Reddy Kalluru * still work. 14994ad95a93SSudarsana Reddy Kalluru */ 15004ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 15014ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1502645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1503645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1504645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1505645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1506645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1507645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1508645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1509645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1510645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1511645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1512645874e5SSudarsana Reddy Kalluru } 1513cc875c2eSYuval Mintz 1514ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 1515ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 1516ae7e6937SAlexander Lobakin if (params->fec & QED_FEC_MODE_NONE) 1517ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_NONE; 1518ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_FIRECODE) 1519ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_FIRECODE; 1520ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_RS) 1521ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_RS; 1522ae7e6937SAlexander Lobakin else if (params->fec & QED_FEC_MODE_AUTO) 1523ae7e6937SAlexander Lobakin fec_bit |= FEC_FORCE_MODE_AUTO; 1524ae7e6937SAlexander Lobakin 1525ae7e6937SAlexander Lobakin SET_MFW_FIELD(phy_cfg.fec_mode, FEC_FORCE_MODE, fec_bit); 1526ae7e6937SAlexander Lobakin } 1527ae7e6937SAlexander Lobakin 152899785a87SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 152999785a87SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) { 153099785a87SAlexander Lobakin ext_speed = 0; 153199785a87SAlexander Lobakin if (params->ext_speed.autoneg) 1532f2a74107SPrabhakar Kushwaha ext_speed |= ETH_EXT_SPEED_NONE; 153399785a87SAlexander Lobakin 153499785a87SAlexander Lobakin val = params->ext_speed.forced_speed; 153599785a87SAlexander Lobakin if (val & QED_EXT_SPEED_1G) 153699785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_1G; 153799785a87SAlexander Lobakin if (val & QED_EXT_SPEED_10G) 153899785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_10G; 153999785a87SAlexander Lobakin if (val & QED_EXT_SPEED_25G) 154099785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_25G; 154199785a87SAlexander Lobakin if (val & QED_EXT_SPEED_40G) 154299785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_40G; 154399785a87SAlexander Lobakin if (val & QED_EXT_SPEED_50G_R) 154499785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_50G_BASE_R; 154599785a87SAlexander Lobakin if (val & QED_EXT_SPEED_50G_R2) 154699785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_50G_BASE_R2; 154799785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_R2) 154899785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_R2; 154999785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_R4) 155099785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_R4; 155199785a87SAlexander Lobakin if (val & QED_EXT_SPEED_100G_P4) 155299785a87SAlexander Lobakin ext_speed |= ETH_EXT_SPEED_100G_BASE_P4; 155399785a87SAlexander Lobakin 155499785a87SAlexander Lobakin SET_MFW_FIELD(phy_cfg.extended_speed, ETH_EXT_SPEED, 155599785a87SAlexander Lobakin ext_speed); 155699785a87SAlexander Lobakin 155799785a87SAlexander Lobakin ext_speed = 0; 155899785a87SAlexander Lobakin 155999785a87SAlexander Lobakin val = params->ext_speed.advertised_speeds; 156099785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_1G) 156199785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_1G; 156299785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_10G) 156399785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_10G; 156499785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_25G) 156599785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_25G; 156699785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_40G) 156799785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_40G; 156899785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_50G_R) 156999785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R; 157099785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_50G_R2) 157199785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_50G_BASE_R2; 157299785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_R2) 157399785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R2; 157499785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_R4) 157599785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_R4; 157699785a87SAlexander Lobakin if (val & QED_EXT_SPEED_MASK_100G_P4) 157799785a87SAlexander Lobakin ext_speed |= ETH_EXT_ADV_SPEED_100G_BASE_P4; 157899785a87SAlexander Lobakin 157999785a87SAlexander Lobakin phy_cfg.extended_speed |= ext_speed; 158099785a87SAlexander Lobakin 158199785a87SAlexander Lobakin SET_MFW_FIELD(phy_cfg.fec_mode, FEC_EXTENDED_MODE, 158299785a87SAlexander Lobakin params->ext_fec_mode); 158399785a87SAlexander Lobakin } 158499785a87SAlexander Lobakin 1585fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1586fc916ff2SSudarsana Reddy Kalluru 1587cc875c2eSYuval Mintz if (b_up) { 1588cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 158999785a87SAlexander Lobakin "Configuring Link: Speed 0x%08x, Pause 0x%08x, Adv. Speed 0x%08x, Loopback 0x%08x, FEC 0x%08x, Ext. Speed 0x%08x\n", 1590ae7e6937SAlexander Lobakin phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed, 159199785a87SAlexander Lobakin phy_cfg.loopback_mode, phy_cfg.fec_mode, 159299785a87SAlexander Lobakin phy_cfg.extended_speed); 1593cc875c2eSYuval Mintz } else { 159499785a87SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, "Resetting link\n"); 1595cc875c2eSYuval Mintz } 1596cc875c2eSYuval Mintz 15975529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 15985529bad9STomer Tayar mb_params.cmd = cmd; 15992f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 16002f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 16015529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1602cc875c2eSYuval Mintz 1603cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1604cc875c2eSYuval Mintz if (rc) { 1605cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1606cc875c2eSYuval Mintz return rc; 1607cc875c2eSYuval Mintz } 1608cc875c2eSYuval Mintz 160965ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 161065ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 161165ed2ffdSMintz, Yuval * an attention. 161265ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 161365ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 161465ed2ffdSMintz, Yuval */ 161565ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1616cc875c2eSYuval Mintz 1617cc875c2eSYuval Mintz return 0; 1618cc875c2eSYuval Mintz } 1619cc875c2eSYuval Mintz 162064515dc8STomer Tayar u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn, 162164515dc8STomer Tayar struct qed_ptt *p_ptt) 162264515dc8STomer Tayar { 162364515dc8STomer Tayar u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt; 162464515dc8STomer Tayar 162564515dc8STomer Tayar if (IS_VF(p_hwfn->cdev)) 162664515dc8STomer Tayar return -EINVAL; 162764515dc8STomer Tayar 162864515dc8STomer Tayar path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 162964515dc8STomer Tayar PUBLIC_PATH); 163064515dc8STomer Tayar path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr); 163164515dc8STomer Tayar path_addr = SECTION_ADDR(path_offsize, QED_PATH_ID(p_hwfn)); 163264515dc8STomer Tayar 163364515dc8STomer Tayar proc_kill_cnt = qed_rd(p_hwfn, p_ptt, 163464515dc8STomer Tayar path_addr + 163564515dc8STomer Tayar offsetof(struct public_path, process_kill)) & 163664515dc8STomer Tayar PROCESS_KILL_COUNTER_MASK; 163764515dc8STomer Tayar 163864515dc8STomer Tayar return proc_kill_cnt; 163964515dc8STomer Tayar } 164064515dc8STomer Tayar 164164515dc8STomer Tayar static void qed_mcp_handle_process_kill(struct qed_hwfn *p_hwfn, 164264515dc8STomer Tayar struct qed_ptt *p_ptt) 164364515dc8STomer Tayar { 164464515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 164564515dc8STomer Tayar u32 proc_kill_cnt; 164664515dc8STomer Tayar 164764515dc8STomer Tayar /* Prevent possible attentions/interrupts during the recovery handling 164864515dc8STomer Tayar * and till its load phase, during which they will be re-enabled. 164964515dc8STomer Tayar */ 165064515dc8STomer Tayar qed_int_igu_disable_int(p_hwfn, p_ptt); 165164515dc8STomer Tayar 165264515dc8STomer Tayar DP_NOTICE(p_hwfn, "Received a process kill indication\n"); 165364515dc8STomer Tayar 165464515dc8STomer Tayar /* The following operations should be done once, and thus in CMT mode 165564515dc8STomer Tayar * are carried out by only the first HW function. 165664515dc8STomer Tayar */ 165764515dc8STomer Tayar if (p_hwfn != QED_LEADING_HWFN(cdev)) 165864515dc8STomer Tayar return; 165964515dc8STomer Tayar 166064515dc8STomer Tayar if (cdev->recov_in_prog) { 166164515dc8STomer Tayar DP_NOTICE(p_hwfn, 166264515dc8STomer Tayar "Ignoring the indication since a recovery process is already in progress\n"); 166364515dc8STomer Tayar return; 166464515dc8STomer Tayar } 166564515dc8STomer Tayar 166664515dc8STomer Tayar cdev->recov_in_prog = true; 166764515dc8STomer Tayar 166864515dc8STomer Tayar proc_kill_cnt = qed_get_process_kill_counter(p_hwfn, p_ptt); 166964515dc8STomer Tayar DP_NOTICE(p_hwfn, "Process kill counter: %d\n", proc_kill_cnt); 167064515dc8STomer Tayar 167164515dc8STomer Tayar qed_schedule_recovery_handler(p_hwfn); 167264515dc8STomer Tayar } 167364515dc8STomer Tayar 16746c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 16756c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 16766c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 16776c754246SSudarsana Reddy Kalluru { 16786c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 16796c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 16806c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 16816c754246SSudarsana Reddy Kalluru u32 hsi_param; 16826c754246SSudarsana Reddy Kalluru 16836c754246SSudarsana Reddy Kalluru switch (type) { 16846c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 16856c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 16866c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 16876c754246SSudarsana Reddy Kalluru break; 16886c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 16896c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 16906c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 16916c754246SSudarsana Reddy Kalluru break; 16926c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 16936c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 16946c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 16956c754246SSudarsana Reddy Kalluru break; 16966c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 16976c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 16986c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 16996c754246SSudarsana Reddy Kalluru break; 17006c754246SSudarsana Reddy Kalluru default: 17016c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 17026c754246SSudarsana Reddy Kalluru return; 17036c754246SSudarsana Reddy Kalluru } 17046c754246SSudarsana Reddy Kalluru 17056c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 17066c754246SSudarsana Reddy Kalluru 17076c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 17086c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 17096c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 17102f67af8cSTomer Tayar mb_params.p_data_src = &stats; 17112f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 17126c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 17136c754246SSudarsana Reddy Kalluru } 17146c754246SSudarsana Reddy Kalluru 17151a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17164b01e519SManish Chopra { 17174b01e519SManish Chopra struct qed_mcp_function_info *p_info; 17184b01e519SManish Chopra struct public_func shmem_info; 17194b01e519SManish Chopra u32 resp = 0, param = 0; 17204b01e519SManish Chopra 17211a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 17224b01e519SManish Chopra 17234b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 17244b01e519SManish Chopra 17254b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 17264b01e519SManish Chopra 1727a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 17284b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 17294b01e519SManish Chopra 17304b01e519SManish Chopra /* Acknowledge the MFW */ 17314b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 17324b01e519SManish Chopra ¶m); 17334b01e519SManish Chopra } 17344b01e519SManish Chopra 17352a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17362a351fd9SMintz, Yuval { 17372a351fd9SMintz, Yuval struct public_func shmem_info; 17382a351fd9SMintz, Yuval u32 resp = 0, param = 0; 17392a351fd9SMintz, Yuval 17402a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 17412a351fd9SMintz, Yuval 17422a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 17432a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 17442a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 17457e3e375cSSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 17467e3e375cSSudarsana Reddy Kalluru if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 17477e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 17487e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 17497e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 17507e3e375cSSudarsana Reddy Kalluru 17517e3e375cSSudarsana Reddy Kalluru /* Configure DB to add external vlan to EDPM packets */ 17527e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 17537e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 17547e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 17557e3e375cSSudarsana Reddy Kalluru } else { 17567e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 17577e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 17587e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 17597e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 17607e3e375cSSudarsana Reddy Kalluru } 17617e3e375cSSudarsana Reddy Kalluru 17622a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 17632a351fd9SMintz, Yuval } 17642a351fd9SMintz, Yuval 17657e3e375cSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 17667e3e375cSSudarsana Reddy Kalluru p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 17677e3e375cSSudarsana Reddy Kalluru 17682a351fd9SMintz, Yuval /* Acknowledge the MFW */ 17692a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 17702a351fd9SMintz, Yuval &resp, ¶m); 17712a351fd9SMintz, Yuval } 17722a351fd9SMintz, Yuval 17733e99c211SIgor Russkikh static void qed_mcp_handle_fan_failure(struct qed_hwfn *p_hwfn, 17743e99c211SIgor Russkikh struct qed_ptt *p_ptt) 17753e99c211SIgor Russkikh { 17763e99c211SIgor Russkikh /* A single notification should be sent to upper driver in CMT mode */ 17773e99c211SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 17783e99c211SIgor Russkikh return; 17793e99c211SIgor Russkikh 17803e99c211SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_FAN_FAIL, 17813e99c211SIgor Russkikh "Fan failure was detected on the network interface card and it's going to be shut down.\n"); 17823e99c211SIgor Russkikh } 17833e99c211SIgor Russkikh 1784ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params { 1785ebf64bf4SIgor Russkikh u32 cmd; 1786ebf64bf4SIgor Russkikh void *p_data_src; 1787ebf64bf4SIgor Russkikh u8 data_src_size; 1788ebf64bf4SIgor Russkikh void *p_data_dst; 1789ebf64bf4SIgor Russkikh u8 data_dst_size; 1790ebf64bf4SIgor Russkikh u32 mcp_resp; 1791ebf64bf4SIgor Russkikh }; 1792ebf64bf4SIgor Russkikh 1793ebf64bf4SIgor Russkikh static int 1794ebf64bf4SIgor Russkikh qed_mcp_mdump_cmd(struct qed_hwfn *p_hwfn, 1795ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1796ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params *p_mdump_cmd_params) 1797ebf64bf4SIgor Russkikh { 1798ebf64bf4SIgor Russkikh struct qed_mcp_mb_params mb_params; 1799ebf64bf4SIgor Russkikh int rc; 1800ebf64bf4SIgor Russkikh 1801ebf64bf4SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 1802ebf64bf4SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD; 1803ebf64bf4SIgor Russkikh mb_params.param = p_mdump_cmd_params->cmd; 1804ebf64bf4SIgor Russkikh mb_params.p_data_src = p_mdump_cmd_params->p_data_src; 1805ebf64bf4SIgor Russkikh mb_params.data_src_size = p_mdump_cmd_params->data_src_size; 1806ebf64bf4SIgor Russkikh mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst; 1807ebf64bf4SIgor Russkikh mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size; 1808ebf64bf4SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1809ebf64bf4SIgor Russkikh if (rc) 1810ebf64bf4SIgor Russkikh return rc; 1811ebf64bf4SIgor Russkikh 1812ebf64bf4SIgor Russkikh p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp; 1813ebf64bf4SIgor Russkikh 1814ebf64bf4SIgor Russkikh if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) { 1815ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1816ebf64bf4SIgor Russkikh "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n", 1817ebf64bf4SIgor Russkikh p_mdump_cmd_params->cmd); 1818ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1819ebf64bf4SIgor Russkikh } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 1820ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1821ebf64bf4SIgor Russkikh "The mdump command is not supported by the MFW\n"); 1822ebf64bf4SIgor Russkikh rc = -EOPNOTSUPP; 1823ebf64bf4SIgor Russkikh } 1824ebf64bf4SIgor Russkikh 1825ebf64bf4SIgor Russkikh return rc; 1826ebf64bf4SIgor Russkikh } 1827ebf64bf4SIgor Russkikh 1828ebf64bf4SIgor Russkikh static int qed_mcp_mdump_ack(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1829ebf64bf4SIgor Russkikh { 1830ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1831ebf64bf4SIgor Russkikh 1832ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1833ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK; 1834ebf64bf4SIgor Russkikh 1835ebf64bf4SIgor Russkikh return qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1836ebf64bf4SIgor Russkikh } 1837ebf64bf4SIgor Russkikh 1838ebf64bf4SIgor Russkikh int 1839ebf64bf4SIgor Russkikh qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn, 1840ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt, 1841ebf64bf4SIgor Russkikh struct mdump_retain_data_stc *p_mdump_retain) 1842ebf64bf4SIgor Russkikh { 1843ebf64bf4SIgor Russkikh struct qed_mdump_cmd_params mdump_cmd_params; 1844ebf64bf4SIgor Russkikh int rc; 1845ebf64bf4SIgor Russkikh 1846ebf64bf4SIgor Russkikh memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params)); 1847ebf64bf4SIgor Russkikh mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN; 1848ebf64bf4SIgor Russkikh mdump_cmd_params.p_data_dst = p_mdump_retain; 1849ebf64bf4SIgor Russkikh mdump_cmd_params.data_dst_size = sizeof(*p_mdump_retain); 1850ebf64bf4SIgor Russkikh 1851ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params); 1852ebf64bf4SIgor Russkikh if (rc) 1853ebf64bf4SIgor Russkikh return rc; 1854ebf64bf4SIgor Russkikh 1855ebf64bf4SIgor Russkikh if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) { 1856ebf64bf4SIgor Russkikh DP_INFO(p_hwfn, 1857ebf64bf4SIgor Russkikh "Failed to get the mdump retained data [mcp_resp 0x%x]\n", 1858ebf64bf4SIgor Russkikh mdump_cmd_params.mcp_resp); 1859ebf64bf4SIgor Russkikh return -EINVAL; 1860ebf64bf4SIgor Russkikh } 1861ebf64bf4SIgor Russkikh 1862ebf64bf4SIgor Russkikh return 0; 1863ebf64bf4SIgor Russkikh } 1864ebf64bf4SIgor Russkikh 1865ebf64bf4SIgor Russkikh static void qed_mcp_handle_critical_error(struct qed_hwfn *p_hwfn, 1866ebf64bf4SIgor Russkikh struct qed_ptt *p_ptt) 1867ebf64bf4SIgor Russkikh { 1868ebf64bf4SIgor Russkikh struct mdump_retain_data_stc mdump_retain; 1869ebf64bf4SIgor Russkikh int rc; 1870ebf64bf4SIgor Russkikh 1871ebf64bf4SIgor Russkikh /* In CMT mode - no need for more than a single acknowledgment to the 1872ebf64bf4SIgor Russkikh * MFW, and no more than a single notification to the upper driver. 1873ebf64bf4SIgor Russkikh */ 1874ebf64bf4SIgor Russkikh if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev)) 1875ebf64bf4SIgor Russkikh return; 1876ebf64bf4SIgor Russkikh 1877ebf64bf4SIgor Russkikh rc = qed_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain); 1878ebf64bf4SIgor Russkikh if (rc == 0 && mdump_retain.valid) 1879ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1880ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n", 1881ebf64bf4SIgor Russkikh mdump_retain.epoch, 1882ebf64bf4SIgor Russkikh mdump_retain.pf, mdump_retain.status); 1883ebf64bf4SIgor Russkikh else 1884ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1885ebf64bf4SIgor Russkikh "The MFW notified that a critical error occurred in the device\n"); 1886ebf64bf4SIgor Russkikh 1887ebf64bf4SIgor Russkikh DP_NOTICE(p_hwfn, 1888ebf64bf4SIgor Russkikh "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n"); 1889ebf64bf4SIgor Russkikh qed_mcp_mdump_ack(p_hwfn, p_ptt); 1890ebf64bf4SIgor Russkikh 1891ebf64bf4SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_HW_ATTN, NULL); 1892ebf64bf4SIgor Russkikh } 1893ebf64bf4SIgor Russkikh 1894cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1895cac6f691SSudarsana Reddy Kalluru { 1896cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1897cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1898cac6f691SSudarsana Reddy Kalluru 1899cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1900cac6f691SSudarsana Reddy Kalluru return; 1901cac6f691SSudarsana Reddy Kalluru 1902cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1903cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1904cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1905cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1906cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1907cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1908ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1909ec036eb9SSudarsana Reddy Kalluru "Incorrect UFP Channel type %d port_id 0x%02x\n", 1910ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1911cac6f691SSudarsana Reddy Kalluru 1912cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1913cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1914cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1915cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1916cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1917cac6f691SSudarsana Reddy Kalluru } else { 1918cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1919ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1920ec036eb9SSudarsana Reddy Kalluru "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1921ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1922cac6f691SSudarsana Reddy Kalluru } 1923cac6f691SSudarsana Reddy Kalluru 1924cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1925b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1926b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1927cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1928b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1929cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1930cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1931cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1932cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1933cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1934cac6f691SSudarsana Reddy Kalluru } else { 1935cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1936ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1937ec036eb9SSudarsana Reddy Kalluru "Unknown Host priority control %d port_id 0x%02x\n", 1938ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1939cac6f691SSudarsana Reddy Kalluru } 1940cac6f691SSudarsana Reddy Kalluru 1941cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1942ec036eb9SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1943ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1944ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1945cac6f691SSudarsana Reddy Kalluru } 1946cac6f691SSudarsana Reddy Kalluru 1947cac6f691SSudarsana Reddy Kalluru static int 1948cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1949cac6f691SSudarsana Reddy Kalluru { 1950cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1951cac6f691SSudarsana Reddy Kalluru 1952cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1953cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1954c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1955c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1956cac6f691SSudarsana Reddy Kalluru 1957cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1958cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1959cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1960cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1961cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1962cac6f691SSudarsana Reddy Kalluru } else { 1963cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1964cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1965cac6f691SSudarsana Reddy Kalluru } 1966cac6f691SSudarsana Reddy Kalluru 1967cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1968cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1969cac6f691SSudarsana Reddy Kalluru 1970cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1971cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1972cac6f691SSudarsana Reddy Kalluru 1973cac6f691SSudarsana Reddy Kalluru return 0; 1974cac6f691SSudarsana Reddy Kalluru } 1975cac6f691SSudarsana Reddy Kalluru 1976cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1977cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1978cc875c2eSYuval Mintz { 1979cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1980cc875c2eSYuval Mintz int rc = 0; 1981cc875c2eSYuval Mintz bool found = false; 1982cc875c2eSYuval Mintz u16 i; 1983cc875c2eSYuval Mintz 1984cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1985cc875c2eSYuval Mintz 1986cc875c2eSYuval Mintz /* Read Messages from MFW */ 1987cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1988cc875c2eSYuval Mintz 1989cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1990cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1991cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1992cc875c2eSYuval Mintz continue; 1993cc875c2eSYuval Mintz 1994cc875c2eSYuval Mintz found = true; 1995cc875c2eSYuval Mintz 1996cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1997cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1998cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1999cc875c2eSYuval Mintz 2000cc875c2eSYuval Mintz switch (i) { 2001cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 2002cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 2003cc875c2eSYuval Mintz break; 20040b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 20050b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 20060b55e27dSYuval Mintz break; 200739651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 200839651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 200939651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 201039651abdSSudarsana Reddy Kalluru break; 201139651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 201239651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 201339651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 201439651abdSSudarsana Reddy Kalluru break; 201539651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 201639651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 201739651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 201839651abdSSudarsana Reddy Kalluru break; 2019cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 2020cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 2021cac6f691SSudarsana Reddy Kalluru break; 2022334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 2023334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 2024334c03b5SZvi Nachmani break; 202564515dc8STomer Tayar case MFW_DRV_MSG_ERROR_RECOVERY: 202664515dc8STomer Tayar qed_mcp_handle_process_kill(p_hwfn, p_ptt); 202764515dc8STomer Tayar break; 20286c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 20296c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 20306c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 20316c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 20326c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 20336c754246SSudarsana Reddy Kalluru break; 20344b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 20354b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 20364b01e519SManish Chopra break; 20372a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 20382a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 20392a351fd9SMintz, Yuval break; 20403e99c211SIgor Russkikh case MFW_DRV_MSG_FAILURE_DETECTED: 20413e99c211SIgor Russkikh qed_mcp_handle_fan_failure(p_hwfn, p_ptt); 20423e99c211SIgor Russkikh break; 2043ebf64bf4SIgor Russkikh case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED: 2044ebf64bf4SIgor Russkikh qed_mcp_handle_critical_error(p_hwfn, p_ptt); 2045ebf64bf4SIgor Russkikh break; 204659ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 204759ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 20482a351fd9SMintz, Yuval break; 2049cc875c2eSYuval Mintz default: 205039815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 2051cc875c2eSYuval Mintz rc = -EINVAL; 2052cc875c2eSYuval Mintz } 2053cc875c2eSYuval Mintz } 2054cc875c2eSYuval Mintz 2055cc875c2eSYuval Mintz /* ACK everything */ 2056cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 2057cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 2058cc875c2eSYuval Mintz 2059cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 2060cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 2061cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 2062cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 2063cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 2064cc875c2eSYuval Mintz (__force u32)val); 2065cc875c2eSYuval Mintz } 2066cc875c2eSYuval Mintz 2067cc875c2eSYuval Mintz if (!found) { 2068cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 2069cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 2070cc875c2eSYuval Mintz rc = -EINVAL; 2071cc875c2eSYuval Mintz } 2072cc875c2eSYuval Mintz 2073cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 2074cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 2075cc875c2eSYuval Mintz 2076cc875c2eSYuval Mintz return rc; 2077cc875c2eSYuval Mintz } 2078cc875c2eSYuval Mintz 20791408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 20801408cc1fSYuval Mintz struct qed_ptt *p_ptt, 20811408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 2082fe56b9e6SYuval Mintz { 20836c95dd8fSPrabhakar Kushwaha u32 global_offsize, public_base; 2084fe56b9e6SYuval Mintz 20851408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 20861408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 20871408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 20881408cc1fSYuval Mintz 20891408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 20901408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 20911408cc1fSYuval Mintz return 0; 20921408cc1fSYuval Mintz } else { 20931408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 20941408cc1fSYuval Mintz QED_MSG_IOV, 20951408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 20961408cc1fSYuval Mintz return -EINVAL; 20971408cc1fSYuval Mintz } 20981408cc1fSYuval Mintz } 2099fe56b9e6SYuval Mintz 21006c95dd8fSPrabhakar Kushwaha public_base = p_hwfn->mcp_info->public_base; 2101fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 21026c95dd8fSPrabhakar Kushwaha SECTION_OFFSIZE_ADDR(public_base, 2103fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 21041408cc1fSYuval Mintz *p_mfw_ver = 21051408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 21061408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 21071408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 2108fe56b9e6SYuval Mintz 21096c95dd8fSPrabhakar Kushwaha if (p_running_bundle_id) { 21101408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 21111408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 21121408cc1fSYuval Mintz offsetof(struct public_global, 21131408cc1fSYuval Mintz running_bundle_id)); 21141408cc1fSYuval Mintz } 2115fe56b9e6SYuval Mintz 2116fe56b9e6SYuval Mintz return 0; 2117fe56b9e6SYuval Mintz } 2118fe56b9e6SYuval Mintz 2119ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 2120ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 2121ae33666aSTomer Tayar { 2122ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 2123ae33666aSTomer Tayar 2124ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 2125ae33666aSTomer Tayar return -EINVAL; 2126ae33666aSTomer Tayar 2127ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 2128ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2129ae33666aSTomer Tayar if (!nvm_cfg_addr) { 2130ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2131ae33666aSTomer Tayar return -EINVAL; 2132ae33666aSTomer Tayar } 2133ae33666aSTomer Tayar 2134ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 2135ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2136ae33666aSTomer Tayar 2137ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2138ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 2139ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 2140ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 2141ae33666aSTomer Tayar mbi_ver_addr) & 2142ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 2143ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 2144ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 2145ae33666aSTomer Tayar 2146ae33666aSTomer Tayar return 0; 2147ae33666aSTomer Tayar } 2148ae33666aSTomer Tayar 2149706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 2150706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *p_media_type) 2151cc875c2eSYuval Mintz { 2152c56a8be7SRahul Verma *p_media_type = MEDIA_UNSPECIFIED; 2153c56a8be7SRahul Verma 2154706d0891SRahul Verma if (IS_VF(p_hwfn->cdev)) 21551408cc1fSYuval Mintz return -EINVAL; 21561408cc1fSYuval Mintz 2157cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 2158cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2159cc875c2eSYuval Mintz return -EBUSY; 2160cc875c2eSYuval Mintz } 2161cc875c2eSYuval Mintz 2162706d0891SRahul Verma if (!p_ptt) { 2163cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 2164706d0891SRahul Verma return -EINVAL; 2165706d0891SRahul Verma } 2166cc875c2eSYuval Mintz 2167706d0891SRahul Verma *p_media_type = qed_rd(p_hwfn, p_ptt, 2168706d0891SRahul Verma p_hwfn->mcp_info->port_addr + 2169706d0891SRahul Verma offsetof(struct public_port, 2170706d0891SRahul Verma media_type)); 2171cc875c2eSYuval Mintz 2172cc875c2eSYuval Mintz return 0; 2173cc875c2eSYuval Mintz } 2174cc875c2eSYuval Mintz 2175c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 2176c56a8be7SRahul Verma struct qed_ptt *p_ptt, 2177c56a8be7SRahul Verma u32 *p_transceiver_state, 2178c56a8be7SRahul Verma u32 *p_transceiver_type) 2179c56a8be7SRahul Verma { 2180c56a8be7SRahul Verma u32 transceiver_info; 2181c56a8be7SRahul Verma 218268203a67SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 218368203a67SRahul Verma *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 218468203a67SRahul Verma 2185c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2186c56a8be7SRahul Verma return -EINVAL; 2187c56a8be7SRahul Verma 2188c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2189c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2190c56a8be7SRahul Verma return -EBUSY; 2191c56a8be7SRahul Verma } 2192c56a8be7SRahul Verma 2193c56a8be7SRahul Verma transceiver_info = qed_rd(p_hwfn, p_ptt, 2194c56a8be7SRahul Verma p_hwfn->mcp_info->port_addr + 2195c56a8be7SRahul Verma offsetof(struct public_port, 2196c56a8be7SRahul Verma transceiver_data)); 2197c56a8be7SRahul Verma 2198c56a8be7SRahul Verma *p_transceiver_state = (transceiver_info & 2199c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_MASK) >> 2200c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_OFFSET; 2201c56a8be7SRahul Verma 2202c56a8be7SRahul Verma if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 2203c56a8be7SRahul Verma *p_transceiver_type = (transceiver_info & 2204c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_MASK) >> 2205c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_OFFSET; 2206c56a8be7SRahul Verma else 2207c56a8be7SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 2208c56a8be7SRahul Verma 2209c56a8be7SRahul Verma return 0; 2210c56a8be7SRahul Verma } 22116c95dd8fSPrabhakar Kushwaha 2212c56a8be7SRahul Verma static bool qed_is_transceiver_ready(u32 transceiver_state, 2213c56a8be7SRahul Verma u32 transceiver_type) 2214c56a8be7SRahul Verma { 2215c56a8be7SRahul Verma if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 2216c56a8be7SRahul Verma ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 2217c56a8be7SRahul Verma (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 2218c56a8be7SRahul Verma return true; 2219c56a8be7SRahul Verma 2220c56a8be7SRahul Verma return false; 2221c56a8be7SRahul Verma } 2222c56a8be7SRahul Verma 2223c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 2224c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask) 2225c56a8be7SRahul Verma { 2226c56a8be7SRahul Verma u32 transceiver_type, transceiver_state; 222792619210SArnd Bergmann int ret; 2228c56a8be7SRahul Verma 222992619210SArnd Bergmann ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 2230c56a8be7SRahul Verma &transceiver_type); 223192619210SArnd Bergmann if (ret) 223292619210SArnd Bergmann return ret; 2233c56a8be7SRahul Verma 2234c56a8be7SRahul Verma if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 2235c56a8be7SRahul Verma false) 2236c56a8be7SRahul Verma return -EINVAL; 2237c56a8be7SRahul Verma 2238c56a8be7SRahul Verma switch (transceiver_type) { 2239c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_LX: 2240c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_SX: 2241c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_PCC: 2242c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_ACC: 2243c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1000BASET: 2244c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2245c56a8be7SRahul Verma break; 2246c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_SR: 2247c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LR: 2248c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LRM: 2249c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ER: 2250c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_PCC: 2251c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ACC: 2252c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x10G: 2253c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2254c56a8be7SRahul Verma break; 2255c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_LR4: 2256c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_SR4: 2257c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2258c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2259c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2260c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2261c56a8be7SRahul Verma break; 2262c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_AOC: 2263c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_SR4: 2264c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_LR4: 2265c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ER4: 2266c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ACC: 2267c56a8be7SRahul Verma *p_speed_mask = 2268c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2269c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2270c56a8be7SRahul Verma break; 2271c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_SR: 2272c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_LR: 2273c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_AOC: 2274c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2275c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2276c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2277c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2278c56a8be7SRahul Verma break; 2279c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2280c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2281c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2282c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2283c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2284c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2285c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2286c56a8be7SRahul Verma break; 22879228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR: 22889228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR: 22899228b7c1SAlexander Lobakin *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 22909228b7c1SAlexander Lobakin NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 22919228b7c1SAlexander Lobakin break; 2292c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_CR4: 2293c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2294c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2295c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2296c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2297c56a8be7SRahul Verma break; 2298c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_CR4: 2299c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2300c56a8be7SRahul Verma *p_speed_mask = 2301c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2302c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2303c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2304c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2305c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2306c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2307c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2308c56a8be7SRahul Verma break; 2309c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2310c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2311c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2312c56a8be7SRahul Verma *p_speed_mask = 2313c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2314c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2315c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2316c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2317c56a8be7SRahul Verma break; 2318c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_XLPPI: 2319c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2320c56a8be7SRahul Verma break; 2321c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_BASET: 23229228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR: 23239228b7c1SAlexander Lobakin case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR: 2324c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2325c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2326c56a8be7SRahul Verma break; 2327c56a8be7SRahul Verma default: 23281107a674SColin Ian King DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2329c56a8be7SRahul Verma transceiver_type); 2330c56a8be7SRahul Verma *p_speed_mask = 0xff; 2331c56a8be7SRahul Verma break; 2332c56a8be7SRahul Verma } 2333c56a8be7SRahul Verma 2334c56a8be7SRahul Verma return 0; 2335c56a8be7SRahul Verma } 2336c56a8be7SRahul Verma 2337c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2338c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config) 2339c56a8be7SRahul Verma { 2340c56a8be7SRahul Verma u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2341c56a8be7SRahul Verma 2342c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2343c56a8be7SRahul Verma return -EINVAL; 2344c56a8be7SRahul Verma 2345c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2346c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2347c56a8be7SRahul Verma return -EBUSY; 2348c56a8be7SRahul Verma } 2349c56a8be7SRahul Verma if (!p_ptt) { 2350c56a8be7SRahul Verma *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2351c56a8be7SRahul Verma return -EINVAL; 2352c56a8be7SRahul Verma } 2353c56a8be7SRahul Verma 2354c56a8be7SRahul Verma nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2355c56a8be7SRahul Verma nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2356c56a8be7SRahul Verma port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2357c56a8be7SRahul Verma offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2358c56a8be7SRahul Verma *p_board_config = qed_rd(p_hwfn, p_ptt, 2359c56a8be7SRahul Verma port_cfg_addr + 2360c56a8be7SRahul Verma offsetof(struct nvm_cfg1_port, 2361c56a8be7SRahul Verma board_cfg)); 2362c56a8be7SRahul Verma 2363c56a8be7SRahul Verma return 0; 2364c56a8be7SRahul Verma } 2365c56a8be7SRahul Verma 23666927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 23676927e826SMintz, Yuval static void 23686927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 23696927e826SMintz, Yuval enum qed_pci_personality *p_proto) 23706927e826SMintz, Yuval { 23716927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 23726927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 23736927e826SMintz, Yuval */ 23746927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 23756927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 23766927e826SMintz, Yuval else 23776927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 23786927e826SMintz, Yuval 23796927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 23806927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 23816927e826SMintz, Yuval (u32)*p_proto); 23826927e826SMintz, Yuval } 23836927e826SMintz, Yuval 23846927e826SMintz, Yuval static int 23856927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 23866927e826SMintz, Yuval struct qed_ptt *p_ptt, 23876927e826SMintz, Yuval enum qed_pci_personality *p_proto) 23886927e826SMintz, Yuval { 23896927e826SMintz, Yuval u32 resp = 0, param = 0; 23906927e826SMintz, Yuval int rc; 23916927e826SMintz, Yuval 23926927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 23936927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 23946927e826SMintz, Yuval if (rc) 23956927e826SMintz, Yuval return rc; 23966927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 23976927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 23986927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 23996927e826SMintz, Yuval resp); 24006927e826SMintz, Yuval return -EINVAL; 24016927e826SMintz, Yuval } 24026927e826SMintz, Yuval 24036927e826SMintz, Yuval switch (param) { 24046927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 24056927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 24066927e826SMintz, Yuval break; 24076927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 24086927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 24096927e826SMintz, Yuval break; 24106927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2411e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 2412e0a8f9deSMichal Kalderon break; 2413e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2414e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 2415e0a8f9deSMichal Kalderon break; 24166927e826SMintz, Yuval default: 24176927e826SMintz, Yuval DP_NOTICE(p_hwfn, 24186927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 24196927e826SMintz, Yuval param); 24206927e826SMintz, Yuval return -EINVAL; 24216927e826SMintz, Yuval } 24226927e826SMintz, Yuval 24236927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 24246927e826SMintz, Yuval NETIF_MSG_IFUP, 24256927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 24266927e826SMintz, Yuval (u32)*p_proto, resp, param); 24276927e826SMintz, Yuval return 0; 24286927e826SMintz, Yuval } 24296927e826SMintz, Yuval 2430fe56b9e6SYuval Mintz static int 2431fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2432fe56b9e6SYuval Mintz struct public_func *p_info, 24336927e826SMintz, Yuval struct qed_ptt *p_ptt, 2434fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 2435fe56b9e6SYuval Mintz { 2436fe56b9e6SYuval Mintz int rc = 0; 2437fe56b9e6SYuval Mintz 2438fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2439fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 24401fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 24411fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 24421fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 24436927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2444fe56b9e6SYuval Mintz break; 2445c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 2446c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 2447c5ac9319SYuval Mintz break; 24481e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 24491e128c81SArun Easi *p_proto = QED_PCI_FCOE; 24501e128c81SArun Easi break; 2451c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 2452c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 2453df561f66SGustavo A. R. Silva fallthrough; 2454fe56b9e6SYuval Mintz default: 2455fe56b9e6SYuval Mintz rc = -EINVAL; 2456fe56b9e6SYuval Mintz } 2457fe56b9e6SYuval Mintz 2458fe56b9e6SYuval Mintz return rc; 2459fe56b9e6SYuval Mintz } 2460fe56b9e6SYuval Mintz 2461fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2462fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2463fe56b9e6SYuval Mintz { 2464fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 2465fe56b9e6SYuval Mintz struct public_func shmem_info; 2466fe56b9e6SYuval Mintz 24671a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2468fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 2469fe56b9e6SYuval Mintz 2470fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 2471fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2472fe56b9e6SYuval Mintz 24736927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 24746927e826SMintz, Yuval &info->protocol)) { 2475fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 2476fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2477fe56b9e6SYuval Mintz return -EINVAL; 2478fe56b9e6SYuval Mintz } 2479fe56b9e6SYuval Mintz 24804b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2481fe56b9e6SYuval Mintz 2482fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 2483fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2484fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 2485fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2486fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2487fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2488fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 248914d39648SMintz, Yuval 249014d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 249114d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2492fe56b9e6SYuval Mintz } else { 2493fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2494fe56b9e6SYuval Mintz } 2495fe56b9e6SYuval Mintz 249657796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 249757796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 249857796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 249957796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2500fe56b9e6SYuval Mintz 2501fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2502fe56b9e6SYuval Mintz 25030fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 25040fefbfbaSSudarsana Kalluru 250514d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 250614d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 250714d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 250814d39648SMintz, Yuval u32 resp = 0, param = 0; 250914d39648SMintz, Yuval int rc; 251014d39648SMintz, Yuval 251114d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 251214d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 251314d39648SMintz, Yuval if (rc) 251414d39648SMintz, Yuval return rc; 251514d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 251614d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 251714d39648SMintz, Yuval } 251814d39648SMintz, Yuval 2519fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 2520b03c3bacSAndy Shevchenko "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %pM wwn port %llx node %llx ovlan %04x wol %02x\n", 2521fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2522fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2523b03c3bacSAndy Shevchenko info->mac, 252414d39648SMintz, Yuval info->wwn_port, info->wwn_node, 252514d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2526fe56b9e6SYuval Mintz 2527fe56b9e6SYuval Mintz return 0; 2528fe56b9e6SYuval Mintz } 2529fe56b9e6SYuval Mintz 2530cc875c2eSYuval Mintz struct qed_mcp_link_params 2531cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2532cc875c2eSYuval Mintz { 2533cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2534cc875c2eSYuval Mintz return NULL; 2535cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2536cc875c2eSYuval Mintz } 2537cc875c2eSYuval Mintz 2538cc875c2eSYuval Mintz struct qed_mcp_link_state 2539cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2540cc875c2eSYuval Mintz { 2541cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2542cc875c2eSYuval Mintz return NULL; 2543cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2544cc875c2eSYuval Mintz } 2545cc875c2eSYuval Mintz 2546cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2547cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2548cc875c2eSYuval Mintz { 2549cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2550cc875c2eSYuval Mintz return NULL; 2551cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2552cc875c2eSYuval Mintz } 2553cc875c2eSYuval Mintz 25541a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2555fe56b9e6SYuval Mintz { 2556fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2557fe56b9e6SYuval Mintz int rc; 2558fe56b9e6SYuval Mintz 2559fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 25601a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2561fe56b9e6SYuval Mintz 2562fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 25638f60bafeSYuval Mintz msleep(1020); 2564fe56b9e6SYuval Mintz 2565fe56b9e6SYuval Mintz return rc; 2566fe56b9e6SYuval Mintz } 2567fe56b9e6SYuval Mintz 2568cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 25691a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2570cee4d264SManish Chopra { 2571cee4d264SManish Chopra u32 flash_size; 2572cee4d264SManish Chopra 25731408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 25741408cc1fSYuval Mintz return -EINVAL; 25751408cc1fSYuval Mintz 2576cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2577cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2578cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2579cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2580cee4d264SManish Chopra 2581cee4d264SManish Chopra *p_flash_size = flash_size; 2582cee4d264SManish Chopra 2583cee4d264SManish Chopra return 0; 2584cee4d264SManish Chopra } 2585cee4d264SManish Chopra 258664515dc8STomer Tayar int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 258764515dc8STomer Tayar { 258864515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 258964515dc8STomer Tayar 259064515dc8STomer Tayar if (cdev->recov_in_prog) { 259164515dc8STomer Tayar DP_NOTICE(p_hwfn, 259264515dc8STomer Tayar "Avoid triggering a recovery since such a process is already in progress\n"); 259364515dc8STomer Tayar return -EAGAIN; 259464515dc8STomer Tayar } 259564515dc8STomer Tayar 259664515dc8STomer Tayar DP_NOTICE(p_hwfn, "Triggering a recovery process\n"); 259764515dc8STomer Tayar qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1); 259864515dc8STomer Tayar 259964515dc8STomer Tayar return 0; 260064515dc8STomer Tayar } 260164515dc8STomer Tayar 260264515dc8STomer Tayar #define QED_RECOVERY_PROLOG_SLEEP_MS 100 260364515dc8STomer Tayar 260464515dc8STomer Tayar int qed_recovery_prolog(struct qed_dev *cdev) 260564515dc8STomer Tayar { 260664515dc8STomer Tayar struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 260764515dc8STomer Tayar struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 260864515dc8STomer Tayar int rc; 260964515dc8STomer Tayar 261064515dc8STomer Tayar /* Allow ongoing PCIe transactions to complete */ 261164515dc8STomer Tayar msleep(QED_RECOVERY_PROLOG_SLEEP_MS); 261264515dc8STomer Tayar 261364515dc8STomer Tayar /* Clear the PF's internal FID_enable in the PXP */ 261464515dc8STomer Tayar rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 261564515dc8STomer Tayar if (rc) 261664515dc8STomer Tayar DP_NOTICE(p_hwfn, 261764515dc8STomer Tayar "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 261864515dc8STomer Tayar rc); 261964515dc8STomer Tayar 262064515dc8STomer Tayar return rc; 262164515dc8STomer Tayar } 262264515dc8STomer Tayar 262388072fd4SMintz, Yuval static int 262488072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 26251408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 26261408cc1fSYuval Mintz { 26271408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 26281408cc1fSYuval Mintz int rc; 26291408cc1fSYuval Mintz 26301408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 26311408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 26321408cc1fSYuval Mintz return 0; 26331408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 26341408cc1fSYuval Mintz 26351408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 26361408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 26371408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 26381408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 26391408cc1fSYuval Mintz 26401408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 26411408cc1fSYuval Mintz &resp, &rc_param); 26421408cc1fSYuval Mintz 26431408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 26441408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 26451408cc1fSYuval Mintz rc = -EINVAL; 26461408cc1fSYuval Mintz } else { 26471408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 26481408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 26491408cc1fSYuval Mintz num, vf_id); 26501408cc1fSYuval Mintz } 26511408cc1fSYuval Mintz 26521408cc1fSYuval Mintz return rc; 26531408cc1fSYuval Mintz } 26541408cc1fSYuval Mintz 265588072fd4SMintz, Yuval static int 265688072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 265788072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 265888072fd4SMintz, Yuval { 265988072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 266088072fd4SMintz, Yuval int rc; 266188072fd4SMintz, Yuval 266288072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 266388072fd4SMintz, Yuval param, &resp, &rc_param); 266488072fd4SMintz, Yuval 266588072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 266688072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 266788072fd4SMintz, Yuval rc = -EINVAL; 266888072fd4SMintz, Yuval } else { 266988072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 267088072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 267188072fd4SMintz, Yuval } 267288072fd4SMintz, Yuval 267388072fd4SMintz, Yuval return rc; 267488072fd4SMintz, Yuval } 267588072fd4SMintz, Yuval 267688072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 267788072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 267888072fd4SMintz, Yuval { 267988072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 268088072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 268188072fd4SMintz, Yuval else 268288072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 268388072fd4SMintz, Yuval } 268488072fd4SMintz, Yuval 2685fe56b9e6SYuval Mintz int 2686fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2687fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2688fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2689fe56b9e6SYuval Mintz { 26905529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 26912f67af8cSTomer Tayar struct drv_version_stc drv_version; 26925529bad9STomer Tayar __be32 val; 26935529bad9STomer Tayar u32 i; 26945529bad9STomer Tayar int rc; 2695fe56b9e6SYuval Mintz 26962f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 26972f67af8cSTomer Tayar drv_version.version = p_ver->version; 269867a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 269967a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 27002f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2701fe56b9e6SYuval Mintz } 2702fe56b9e6SYuval Mintz 27035529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 27045529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 27052f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 27062f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 27075529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 27085529bad9STomer Tayar if (rc) 2709fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2710fe56b9e6SYuval Mintz 27115529bad9STomer Tayar return rc; 2712fe56b9e6SYuval Mintz } 271391420b83SSudarsana Kalluru 271476271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 271576271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 271676271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 271776271809STomer Tayar 27184102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27194102426fSTomer Tayar { 272076271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 27214102426fSTomer Tayar int rc; 27224102426fSTomer Tayar 27234102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 27244102426fSTomer Tayar ¶m); 272576271809STomer Tayar if (rc) { 27264102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 27274102426fSTomer Tayar return rc; 27284102426fSTomer Tayar } 27294102426fSTomer Tayar 273076271809STomer Tayar do { 273176271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 273276271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 273376271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 273476271809STomer Tayar break; 273576271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 273676271809STomer Tayar 273776271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 273876271809STomer Tayar DP_NOTICE(p_hwfn, 273976271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 274076271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 274176271809STomer Tayar return -EBUSY; 274276271809STomer Tayar } 274376271809STomer Tayar 2744b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2745b310974eSTomer Tayar 274676271809STomer Tayar return 0; 274776271809STomer Tayar } 274876271809STomer Tayar 274976271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 275076271809STomer Tayar 27514102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27524102426fSTomer Tayar { 275376271809STomer Tayar u32 cpu_mode, cpu_state; 27544102426fSTomer Tayar 27554102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 27564102426fSTomer Tayar 27574102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 275876271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 275976271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 276076271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 276176271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 27624102426fSTomer Tayar 276376271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 276476271809STomer Tayar DP_NOTICE(p_hwfn, 276576271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 276676271809STomer Tayar cpu_mode, cpu_state); 276776271809STomer Tayar return -EBUSY; 276876271809STomer Tayar } 276976271809STomer Tayar 2770b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2771b310974eSTomer Tayar 277276271809STomer Tayar return 0; 27734102426fSTomer Tayar } 27744102426fSTomer Tayar 27750fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 27760fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 27770fefbfbaSSudarsana Kalluru enum qed_ov_client client) 27780fefbfbaSSudarsana Kalluru { 27790fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 27800fefbfbaSSudarsana Kalluru u32 drv_mb_param; 27810fefbfbaSSudarsana Kalluru int rc; 27820fefbfbaSSudarsana Kalluru 27830fefbfbaSSudarsana Kalluru switch (client) { 27840fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 27850fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 27860fefbfbaSSudarsana Kalluru break; 27870fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 27880fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 27890fefbfbaSSudarsana Kalluru break; 27900fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 27910fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 27920fefbfbaSSudarsana Kalluru break; 27930fefbfbaSSudarsana Kalluru default: 27940fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 27950fefbfbaSSudarsana Kalluru return -EINVAL; 27960fefbfbaSSudarsana Kalluru } 27970fefbfbaSSudarsana Kalluru 27980fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 27990fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28000fefbfbaSSudarsana Kalluru if (rc) 28010fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 28020fefbfbaSSudarsana Kalluru 28030fefbfbaSSudarsana Kalluru return rc; 28040fefbfbaSSudarsana Kalluru } 28050fefbfbaSSudarsana Kalluru 28060fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 28070fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 28080fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 28090fefbfbaSSudarsana Kalluru { 28100fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28110fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28120fefbfbaSSudarsana Kalluru int rc; 28130fefbfbaSSudarsana Kalluru 28140fefbfbaSSudarsana Kalluru switch (drv_state) { 28150fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 28160fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 28170fefbfbaSSudarsana Kalluru break; 28180fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 28190fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 28200fefbfbaSSudarsana Kalluru break; 28210fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 28220fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 28230fefbfbaSSudarsana Kalluru break; 28240fefbfbaSSudarsana Kalluru default: 28250fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 28260fefbfbaSSudarsana Kalluru return -EINVAL; 28270fefbfbaSSudarsana Kalluru } 28280fefbfbaSSudarsana Kalluru 28290fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 28300fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28310fefbfbaSSudarsana Kalluru if (rc) 28320fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 28330fefbfbaSSudarsana Kalluru 28340fefbfbaSSudarsana Kalluru return rc; 28350fefbfbaSSudarsana Kalluru } 28360fefbfbaSSudarsana Kalluru 28370fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 28380fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 28390fefbfbaSSudarsana Kalluru { 28400fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28410fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28420fefbfbaSSudarsana Kalluru int rc; 28430fefbfbaSSudarsana Kalluru 28440fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 28450fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 28460fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 28470fefbfbaSSudarsana Kalluru if (rc) 28480fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 28490fefbfbaSSudarsana Kalluru 28500fefbfbaSSudarsana Kalluru return rc; 28510fefbfbaSSudarsana Kalluru } 28520fefbfbaSSudarsana Kalluru 28530fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 285476660757SJakub Kicinski struct qed_ptt *p_ptt, const u8 *mac) 28550fefbfbaSSudarsana Kalluru { 28560fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 285717991002SMintz, Yuval u32 mfw_mac[2]; 28580fefbfbaSSudarsana Kalluru int rc; 28590fefbfbaSSudarsana Kalluru 28600fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 28610fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 28620fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 28630fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 28640fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 28652f67af8cSTomer Tayar 286617991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 286717991002SMintz, Yuval * in 32-bit granularity. 286817991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 286917991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 287017991002SMintz, Yuval */ 287117991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 287217991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 287317991002SMintz, Yuval 287417991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 287517991002SMintz, Yuval mb_params.data_src_size = 8; 28760fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 28770fefbfbaSSudarsana Kalluru if (rc) 28780fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 28790fefbfbaSSudarsana Kalluru 288014d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 288114d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 288214d39648SMintz, Yuval 28830fefbfbaSSudarsana Kalluru return rc; 28840fefbfbaSSudarsana Kalluru } 28850fefbfbaSSudarsana Kalluru 28860fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 28870fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 28880fefbfbaSSudarsana Kalluru { 28890fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 28900fefbfbaSSudarsana Kalluru u32 drv_mb_param; 28910fefbfbaSSudarsana Kalluru int rc; 28920fefbfbaSSudarsana Kalluru 289314d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 289414d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 289514d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 289614d39648SMintz, Yuval return -EINVAL; 289714d39648SMintz, Yuval } 289814d39648SMintz, Yuval 28990fefbfbaSSudarsana Kalluru switch (wol) { 29000fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 29010fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 29020fefbfbaSSudarsana Kalluru break; 29030fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 29040fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 29050fefbfbaSSudarsana Kalluru break; 29060fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 29070fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 29080fefbfbaSSudarsana Kalluru break; 29090fefbfbaSSudarsana Kalluru default: 29100fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 29110fefbfbaSSudarsana Kalluru return -EINVAL; 29120fefbfbaSSudarsana Kalluru } 29130fefbfbaSSudarsana Kalluru 29140fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 29150fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 29160fefbfbaSSudarsana Kalluru if (rc) 29170fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 29180fefbfbaSSudarsana Kalluru 291914d39648SMintz, Yuval /* Store the WoL update for a future unload */ 292014d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 292114d39648SMintz, Yuval 29220fefbfbaSSudarsana Kalluru return rc; 29230fefbfbaSSudarsana Kalluru } 29240fefbfbaSSudarsana Kalluru 29250fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 29260fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 29270fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 29280fefbfbaSSudarsana Kalluru { 29290fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 29300fefbfbaSSudarsana Kalluru u32 drv_mb_param; 29310fefbfbaSSudarsana Kalluru int rc; 29320fefbfbaSSudarsana Kalluru 29330fefbfbaSSudarsana Kalluru switch (eswitch) { 29340fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 29350fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 29360fefbfbaSSudarsana Kalluru break; 29370fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 29380fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 29390fefbfbaSSudarsana Kalluru break; 29400fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 29410fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 29420fefbfbaSSudarsana Kalluru break; 29430fefbfbaSSudarsana Kalluru default: 29440fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 29450fefbfbaSSudarsana Kalluru return -EINVAL; 29460fefbfbaSSudarsana Kalluru } 29470fefbfbaSSudarsana Kalluru 29480fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 29490fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 29500fefbfbaSSudarsana Kalluru if (rc) 29510fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 29520fefbfbaSSudarsana Kalluru 29530fefbfbaSSudarsana Kalluru return rc; 29540fefbfbaSSudarsana Kalluru } 29550fefbfbaSSudarsana Kalluru 29561a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 29571a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 295891420b83SSudarsana Kalluru { 295991420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 296091420b83SSudarsana Kalluru int rc; 296191420b83SSudarsana Kalluru 296291420b83SSudarsana Kalluru switch (mode) { 296391420b83SSudarsana Kalluru case QED_LED_MODE_ON: 296491420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 296591420b83SSudarsana Kalluru break; 296691420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 296791420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 296891420b83SSudarsana Kalluru break; 296991420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 297091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 297191420b83SSudarsana Kalluru break; 297291420b83SSudarsana Kalluru default: 297391420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 297491420b83SSudarsana Kalluru return -EINVAL; 297591420b83SSudarsana Kalluru } 297691420b83SSudarsana Kalluru 297791420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 297891420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 297991420b83SSudarsana Kalluru 298091420b83SSudarsana Kalluru return rc; 298191420b83SSudarsana Kalluru } 298203dc76caSSudarsana Reddy Kalluru 29834102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 29844102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 29854102426fSTomer Tayar { 29864102426fSTomer Tayar u32 resp = 0, param = 0; 29874102426fSTomer Tayar int rc; 29884102426fSTomer Tayar 29894102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 29904102426fSTomer Tayar mask_parities, &resp, ¶m); 29914102426fSTomer Tayar 29924102426fSTomer Tayar if (rc) { 29934102426fSTomer Tayar DP_ERR(p_hwfn, 29944102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 29954102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 29964102426fSTomer Tayar DP_ERR(p_hwfn, 29974102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 29984102426fSTomer Tayar rc = -EINVAL; 29994102426fSTomer Tayar } 30004102426fSTomer Tayar 30014102426fSTomer Tayar return rc; 30024102426fSTomer Tayar } 30034102426fSTomer Tayar 30047a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 30057a4b21b7SMintz, Yuval { 30067a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 30077a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 30087a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 30097a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 30107a4b21b7SMintz, Yuval int rc = 0; 30117a4b21b7SMintz, Yuval 30127a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 30137a4b21b7SMintz, Yuval if (!p_ptt) 30147a4b21b7SMintz, Yuval return -EBUSY; 30157a4b21b7SMintz, Yuval 30167a4b21b7SMintz, Yuval while (bytes_left > 0) { 30177a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 30187a4b21b7SMintz, Yuval 30197a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 30207a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 30217a4b21b7SMintz, Yuval addr + offset + 30227a4b21b7SMintz, Yuval (bytes_to_copy << 3023da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 30247a4b21b7SMintz, Yuval &resp, &resp_param, 30257a4b21b7SMintz, Yuval &read_len, 30266c95dd8fSPrabhakar Kushwaha (u32 *)(p_buf + offset), false); 30277a4b21b7SMintz, Yuval 30287a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 30297a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 30307a4b21b7SMintz, Yuval break; 30317a4b21b7SMintz, Yuval } 30327a4b21b7SMintz, Yuval 30337a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 30346c95dd8fSPrabhakar Kushwaha * isn't preemptible. Sleep a bit to prevent CPU hogging. 30357a4b21b7SMintz, Yuval */ 30367a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 30377a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 30387a4b21b7SMintz, Yuval usleep_range(1000, 2000); 30397a4b21b7SMintz, Yuval 30407a4b21b7SMintz, Yuval offset += read_len; 30417a4b21b7SMintz, Yuval bytes_left -= read_len; 30427a4b21b7SMintz, Yuval } 30437a4b21b7SMintz, Yuval 30447a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 30457a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 30467a4b21b7SMintz, Yuval 30477a4b21b7SMintz, Yuval return rc; 30487a4b21b7SMintz, Yuval } 30497a4b21b7SMintz, Yuval 305062e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 305162e4d438SSudarsana Reddy Kalluru { 305262e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 305362e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 305462e4d438SSudarsana Reddy Kalluru 305562e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 305662e4d438SSudarsana Reddy Kalluru if (!p_ptt) 305762e4d438SSudarsana Reddy Kalluru return -EBUSY; 305862e4d438SSudarsana Reddy Kalluru 305962e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 306062e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 306162e4d438SSudarsana Reddy Kalluru 306262e4d438SSudarsana Reddy Kalluru return 0; 306362e4d438SSudarsana Reddy Kalluru } 306462e4d438SSudarsana Reddy Kalluru 306562e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 306662e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 306762e4d438SSudarsana Reddy Kalluru { 306862e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 306962e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 307062e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 307162e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 307262e4d438SSudarsana Reddy Kalluru 307362e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 307462e4d438SSudarsana Reddy Kalluru if (!p_ptt) 307562e4d438SSudarsana Reddy Kalluru return -EBUSY; 307662e4d438SSudarsana Reddy Kalluru 307762e4d438SSudarsana Reddy Kalluru switch (cmd) { 3078057d2b19SSudarsana Reddy Kalluru case QED_PUT_FILE_BEGIN: 3079057d2b19SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 3080057d2b19SSudarsana Reddy Kalluru break; 308162e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 308262e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 308362e4d438SSudarsana Reddy Kalluru break; 308462e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 308562e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 308662e4d438SSudarsana Reddy Kalluru break; 308762e4d438SSudarsana Reddy Kalluru default: 308862e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 308962e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 309062e4d438SSudarsana Reddy Kalluru goto out; 309162e4d438SSudarsana Reddy Kalluru } 309262e4d438SSudarsana Reddy Kalluru 309362e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 3094057d2b19SSudarsana Reddy Kalluru while (buf_idx < len) { 3095057d2b19SSudarsana Reddy Kalluru if (cmd == QED_PUT_FILE_BEGIN) 3096057d2b19SSudarsana Reddy Kalluru nvm_offset = addr; 3097057d2b19SSudarsana Reddy Kalluru else 3098057d2b19SSudarsana Reddy Kalluru nvm_offset = ((buf_size << 3099057d2b19SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 3100057d2b19SSudarsana Reddy Kalluru buf_idx; 310162e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 310262e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 310362e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 310462e4d438SSudarsana Reddy Kalluru if (rc) { 310562e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 310662e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 310762e4d438SSudarsana Reddy Kalluru break; 310862e4d438SSudarsana Reddy Kalluru } 310962e4d438SSudarsana Reddy Kalluru 311062e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 311162e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 311262e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 311362e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 311462e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 311562e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 311662e4d438SSudarsana Reddy Kalluru break; 311762e4d438SSudarsana Reddy Kalluru } 311862e4d438SSudarsana Reddy Kalluru 311962e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 312062e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 312162e4d438SSudarsana Reddy Kalluru */ 312262e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 312362e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 312462e4d438SSudarsana Reddy Kalluru 3125057d2b19SSudarsana Reddy Kalluru /* For MBI upgrade, MFW response includes the next buffer offset 3126057d2b19SSudarsana Reddy Kalluru * to be delivered to MFW. 3127057d2b19SSudarsana Reddy Kalluru */ 3128057d2b19SSudarsana Reddy Kalluru if (param && cmd == QED_PUT_FILE_DATA) { 31296c95dd8fSPrabhakar Kushwaha buf_idx = 31306c95dd8fSPrabhakar Kushwaha QED_MFW_GET_FIELD(param, 3131057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 31326c95dd8fSPrabhakar Kushwaha buf_size = 31336c95dd8fSPrabhakar Kushwaha QED_MFW_GET_FIELD(param, 3134057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 3135057d2b19SSudarsana Reddy Kalluru } else { 313662e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 3137057d2b19SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), 3138057d2b19SSudarsana Reddy Kalluru MCP_DRV_NVM_BUF_LEN); 3139057d2b19SSudarsana Reddy Kalluru } 314062e4d438SSudarsana Reddy Kalluru } 314162e4d438SSudarsana Reddy Kalluru 314262e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 314362e4d438SSudarsana Reddy Kalluru out: 314462e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 314562e4d438SSudarsana Reddy Kalluru 314662e4d438SSudarsana Reddy Kalluru return rc; 314762e4d438SSudarsana Reddy Kalluru } 314862e4d438SSudarsana Reddy Kalluru 3149b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3150b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 3151b51dab46SSudarsana Reddy Kalluru { 3152b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 3153b51dab46SSudarsana Reddy Kalluru u32 resp, param; 3154b51dab46SSudarsana Reddy Kalluru int rc; 3155b51dab46SSudarsana Reddy Kalluru 3156b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 3157b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 3158b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 3159b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 3160b51dab46SSudarsana Reddy Kalluru 3161b51dab46SSudarsana Reddy Kalluru addr = offset; 3162b51dab46SSudarsana Reddy Kalluru offset = 0; 3163b51dab46SSudarsana Reddy Kalluru bytes_left = len; 3164b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 3165b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 3166b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 3167b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 3168b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 3169b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 3170b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 3171b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 3172b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 3173b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 3174b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 3175b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 3176b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 3177b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 31786c95dd8fSPrabhakar Kushwaha (u32 *)(p_buf + offset), true); 3179b51dab46SSudarsana Reddy Kalluru if (rc) { 3180b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 3181b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 3182b51dab46SSudarsana Reddy Kalluru rc); 3183b51dab46SSudarsana Reddy Kalluru return rc; 3184b51dab46SSudarsana Reddy Kalluru } 3185b51dab46SSudarsana Reddy Kalluru 3186b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 3187b51dab46SSudarsana Reddy Kalluru return -ENODEV; 3188b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 3189b51dab46SSudarsana Reddy Kalluru return -EINVAL; 3190b51dab46SSudarsana Reddy Kalluru 3191b51dab46SSudarsana Reddy Kalluru offset += buf_size; 3192b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 3193b51dab46SSudarsana Reddy Kalluru } 3194b51dab46SSudarsana Reddy Kalluru 3195b51dab46SSudarsana Reddy Kalluru return 0; 3196b51dab46SSudarsana Reddy Kalluru } 3197b51dab46SSudarsana Reddy Kalluru 319803dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319903dc76caSSudarsana Reddy Kalluru { 320003dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 320103dc76caSSudarsana Reddy Kalluru int rc = 0; 320203dc76caSSudarsana Reddy Kalluru 320303dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 320403dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 320503dc76caSSudarsana Reddy Kalluru 320603dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 320703dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 320803dc76caSSudarsana Reddy Kalluru 320903dc76caSSudarsana Reddy Kalluru if (rc) 321003dc76caSSudarsana Reddy Kalluru return rc; 321103dc76caSSudarsana Reddy Kalluru 321203dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 321303dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 321403dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 321503dc76caSSudarsana Reddy Kalluru 321603dc76caSSudarsana Reddy Kalluru return rc; 321703dc76caSSudarsana Reddy Kalluru } 321803dc76caSSudarsana Reddy Kalluru 321903dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 322003dc76caSSudarsana Reddy Kalluru { 322103dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 322203dc76caSSudarsana Reddy Kalluru int rc = 0; 322303dc76caSSudarsana Reddy Kalluru 322403dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 322503dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 322603dc76caSSudarsana Reddy Kalluru 322703dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 322803dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 322903dc76caSSudarsana Reddy Kalluru 323003dc76caSSudarsana Reddy Kalluru if (rc) 323103dc76caSSudarsana Reddy Kalluru return rc; 323203dc76caSSudarsana Reddy Kalluru 323303dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 323403dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 323503dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 323603dc76caSSudarsana Reddy Kalluru 323703dc76caSSudarsana Reddy Kalluru return rc; 323803dc76caSSudarsana Reddy Kalluru } 32397a4b21b7SMintz, Yuval 324043645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 32417a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 32427a4b21b7SMintz, Yuval u32 *num_images) 32437a4b21b7SMintz, Yuval { 32447a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 32457a4b21b7SMintz, Yuval int rc = 0; 32467a4b21b7SMintz, Yuval 32477a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 32487a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 32497a4b21b7SMintz, Yuval 32507a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 32517a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 32527a4b21b7SMintz, Yuval if (rc) 32537a4b21b7SMintz, Yuval return rc; 32547a4b21b7SMintz, Yuval 32557a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 32567a4b21b7SMintz, Yuval rc = -EINVAL; 32577a4b21b7SMintz, Yuval 32587a4b21b7SMintz, Yuval return rc; 32597a4b21b7SMintz, Yuval } 32607a4b21b7SMintz, Yuval 326143645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 32627a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 32637a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 32647a4b21b7SMintz, Yuval u32 image_index) 32657a4b21b7SMintz, Yuval { 32667a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 32677a4b21b7SMintz, Yuval int rc; 32687a4b21b7SMintz, Yuval 32697a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 32707a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 32717a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 32727a4b21b7SMintz, Yuval 32737a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 32747a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 32757a4b21b7SMintz, Yuval &resp, &resp_param, 32767a4b21b7SMintz, Yuval &buf_size, 32776c95dd8fSPrabhakar Kushwaha (u32 *)p_image_att, false); 32787a4b21b7SMintz, Yuval if (rc) 32797a4b21b7SMintz, Yuval return rc; 32807a4b21b7SMintz, Yuval 32817a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 32827a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 32837a4b21b7SMintz, Yuval rc = -EINVAL; 32847a4b21b7SMintz, Yuval 32857a4b21b7SMintz, Yuval return rc; 32867a4b21b7SMintz, Yuval } 32872edbff8dSTomer Tayar 328843645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 328943645ce0SSudarsana Reddy Kalluru { 32905e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 329143645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 329243645ce0SSudarsana Reddy Kalluru int rc; 329343645ce0SSudarsana Reddy Kalluru u32 i; 329443645ce0SSudarsana Reddy Kalluru 32955e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 32965e7ba042SDenis Bolotin return 0; 32975e7ba042SDenis Bolotin 329843645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 329943645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 330043645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 330143645ce0SSudarsana Reddy Kalluru return -EBUSY; 330243645ce0SSudarsana Reddy Kalluru } 330343645ce0SSudarsana Reddy Kalluru 330443645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 33055e7ba042SDenis Bolotin nvm_info.num_images = 0; 330643645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 33075e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 330843645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 330943645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 331043645ce0SSudarsana Reddy Kalluru goto out; 33115e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 331243645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 331343645ce0SSudarsana Reddy Kalluru goto err0; 331443645ce0SSudarsana Reddy Kalluru } 331543645ce0SSudarsana Reddy Kalluru 33165e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 331743645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 331843645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 33195e7ba042SDenis Bolotin if (!nvm_info.image_att) { 332043645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 332143645ce0SSudarsana Reddy Kalluru goto err0; 332243645ce0SSudarsana Reddy Kalluru } 332343645ce0SSudarsana Reddy Kalluru 332443645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 33255e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 332643645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 33275e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 332843645ce0SSudarsana Reddy Kalluru if (rc) { 332943645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 333043645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 333143645ce0SSudarsana Reddy Kalluru goto err1; 333243645ce0SSudarsana Reddy Kalluru } 333343645ce0SSudarsana Reddy Kalluru 333443645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 33355e7ba042SDenis Bolotin nvm_info.image_att[i].len); 333643645ce0SSudarsana Reddy Kalluru } 333743645ce0SSudarsana Reddy Kalluru out: 33385e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 33395e7ba042SDenis Bolotin if (nvm_info.num_images) { 33405e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 33415e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 33425e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 33435e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 33445e7ba042SDenis Bolotin } 33455e7ba042SDenis Bolotin 334643645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 334743645ce0SSudarsana Reddy Kalluru return 0; 334843645ce0SSudarsana Reddy Kalluru 334943645ce0SSudarsana Reddy Kalluru err1: 33505e7ba042SDenis Bolotin kfree(nvm_info.image_att); 335143645ce0SSudarsana Reddy Kalluru err0: 335243645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 335343645ce0SSudarsana Reddy Kalluru return rc; 335443645ce0SSudarsana Reddy Kalluru } 335543645ce0SSudarsana Reddy Kalluru 335613cf8aabSSudarsana Reddy Kalluru void qed_mcp_nvm_info_free(struct qed_hwfn *p_hwfn) 335713cf8aabSSudarsana Reddy Kalluru { 335813cf8aabSSudarsana Reddy Kalluru kfree(p_hwfn->nvm_info.image_att); 335913cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.image_att = NULL; 336013cf8aabSSudarsana Reddy Kalluru p_hwfn->nvm_info.valid = false; 336113cf8aabSSudarsana Reddy Kalluru } 336213cf8aabSSudarsana Reddy Kalluru 33631ac4329aSDenis Bolotin int 336420675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 336520675b37SMintz, Yuval enum qed_nvm_images image_id, 336620675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 336720675b37SMintz, Yuval { 336820675b37SMintz, Yuval enum nvm_image_type type; 336920e100f5SShai Malin int rc; 337043645ce0SSudarsana Reddy Kalluru u32 i; 337120675b37SMintz, Yuval 337220675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 337320675b37SMintz, Yuval switch (image_id) { 337420675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 337520675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 337620675b37SMintz, Yuval break; 337720675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 337820675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 337920675b37SMintz, Yuval break; 33808a52bbabSMichal Kalderon case QED_NVM_IMAGE_MDUMP: 33818a52bbabSMichal Kalderon type = NVM_TYPE_MDUMP; 33828a52bbabSMichal Kalderon break; 33831ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 33841ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 33851ac4329aSDenis Bolotin break; 33861ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 33871ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 33881ac4329aSDenis Bolotin break; 33891ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 3390f2a74107SPrabhakar Kushwaha type = NVM_TYPE_NVM_META; 33911ac4329aSDenis Bolotin break; 339220675b37SMintz, Yuval default: 339320675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 339420675b37SMintz, Yuval image_id); 339520675b37SMintz, Yuval return -EINVAL; 339620675b37SMintz, Yuval } 339720675b37SMintz, Yuval 339820e100f5SShai Malin rc = qed_mcp_nvm_info_populate(p_hwfn); 339920e100f5SShai Malin if (rc) 340020e100f5SShai Malin return rc; 340120e100f5SShai Malin 340243645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 340343645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 340420675b37SMintz, Yuval break; 340543645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 340620675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 340720675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 340820675b37SMintz, Yuval image_id); 340943645ce0SSudarsana Reddy Kalluru return -ENOENT; 341020675b37SMintz, Yuval } 341120675b37SMintz, Yuval 341243645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 341343645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 341420675b37SMintz, Yuval 341520675b37SMintz, Yuval return 0; 341620675b37SMintz, Yuval } 341720675b37SMintz, Yuval 341820675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 341920675b37SMintz, Yuval enum qed_nvm_images image_id, 342020675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 342120675b37SMintz, Yuval { 342220675b37SMintz, Yuval struct qed_nvm_image_att image_att; 342320675b37SMintz, Yuval int rc; 342420675b37SMintz, Yuval 342520675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 342620675b37SMintz, Yuval 3427b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 342820675b37SMintz, Yuval if (rc) 342920675b37SMintz, Yuval return rc; 343020675b37SMintz, Yuval 343120675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 343220675b37SMintz, Yuval if (image_att.length <= 4) { 343320675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 343420675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 343520675b37SMintz, Yuval image_id, image_att.length); 343620675b37SMintz, Yuval return -EINVAL; 343720675b37SMintz, Yuval } 343820675b37SMintz, Yuval 343920675b37SMintz, Yuval if (image_att.length > buffer_len) { 344020675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 344120675b37SMintz, Yuval QED_MSG_STORAGE, 344220675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 344320675b37SMintz, Yuval image_id, image_att.length, buffer_len); 344420675b37SMintz, Yuval return -ENOMEM; 344520675b37SMintz, Yuval } 344620675b37SMintz, Yuval 344720675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 344820675b37SMintz, Yuval p_buffer, image_att.length); 344920675b37SMintz, Yuval } 345020675b37SMintz, Yuval 34519c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 34529c8517c4STomer Tayar { 34539c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 34549c8517c4STomer Tayar 34559c8517c4STomer Tayar switch (res_id) { 34569c8517c4STomer Tayar case QED_SB: 34579c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 34589c8517c4STomer Tayar break; 34599c8517c4STomer Tayar case QED_L2_QUEUE: 34609c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 34619c8517c4STomer Tayar break; 34629c8517c4STomer Tayar case QED_VPORT: 34639c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 34649c8517c4STomer Tayar break; 34659c8517c4STomer Tayar case QED_RSS_ENG: 34669c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 34679c8517c4STomer Tayar break; 34689c8517c4STomer Tayar case QED_PQ: 34699c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 34709c8517c4STomer Tayar break; 34719c8517c4STomer Tayar case QED_RL: 34729c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 34739c8517c4STomer Tayar break; 34749c8517c4STomer Tayar case QED_MAC: 34759c8517c4STomer Tayar case QED_VLAN: 34769c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 34779c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 34789c8517c4STomer Tayar break; 34799c8517c4STomer Tayar case QED_ILT: 34809c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 34819c8517c4STomer Tayar break; 3482997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 34839c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 34849c8517c4STomer Tayar break; 3485997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3486997af5dfSMichal Kalderon mfw_res_id = RESOURCE_LL2_CQS_E; 3487997af5dfSMichal Kalderon break; 34889c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 34899c8517c4STomer Tayar case QED_CMDQS_CQS: 34909c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 34919c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 34929c8517c4STomer Tayar break; 34939c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 34949c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 34959c8517c4STomer Tayar break; 34969c8517c4STomer Tayar case QED_BDQ: 34979c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 34989c8517c4STomer Tayar break; 34999c8517c4STomer Tayar default: 35009c8517c4STomer Tayar break; 35019c8517c4STomer Tayar } 35029c8517c4STomer Tayar 35039c8517c4STomer Tayar return mfw_res_id; 35049c8517c4STomer Tayar } 35059c8517c4STomer Tayar 35069c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 35072edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 35082edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 35092edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 35102edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 35112edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 35122edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 35139c8517c4STomer Tayar 35149c8517c4STomer Tayar struct qed_resc_alloc_in_params { 35159c8517c4STomer Tayar u32 cmd; 35169c8517c4STomer Tayar enum qed_resources res_id; 35179c8517c4STomer Tayar u32 resc_max_val; 35189c8517c4STomer Tayar }; 35199c8517c4STomer Tayar 35209c8517c4STomer Tayar struct qed_resc_alloc_out_params { 35219c8517c4STomer Tayar u32 mcp_resp; 35229c8517c4STomer Tayar u32 mcp_param; 35239c8517c4STomer Tayar u32 resc_num; 35249c8517c4STomer Tayar u32 resc_start; 35259c8517c4STomer Tayar u32 vf_resc_num; 35269c8517c4STomer Tayar u32 vf_resc_start; 35279c8517c4STomer Tayar u32 flags; 35289c8517c4STomer Tayar }; 35299c8517c4STomer Tayar 35309c8517c4STomer Tayar static int 35319c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 35322edbff8dSTomer Tayar struct qed_ptt *p_ptt, 35339c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 35349c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 35352edbff8dSTomer Tayar { 35362edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 35379c8517c4STomer Tayar struct resource_info mfw_resc_info; 35382edbff8dSTomer Tayar int rc; 35392edbff8dSTomer Tayar 35409c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3541bb480242SMintz, Yuval 35429c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 35439c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 35449c8517c4STomer Tayar DP_ERR(p_hwfn, 35459c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 35469c8517c4STomer Tayar p_in_params->res_id, 35479c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 35489c8517c4STomer Tayar return -EINVAL; 35499c8517c4STomer Tayar } 35509c8517c4STomer Tayar 35519c8517c4STomer Tayar switch (p_in_params->cmd) { 35529c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 35539c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 3554df561f66SGustavo A. R. Silva fallthrough; 35559c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 35569c8517c4STomer Tayar break; 35579c8517c4STomer Tayar default: 35589c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 35599c8517c4STomer Tayar p_in_params->cmd); 35609c8517c4STomer Tayar return -EINVAL; 35619c8517c4STomer Tayar } 35629c8517c4STomer Tayar 35639c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 35649c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 35659c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 35669c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 35679c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 35689c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 35699c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 35709c8517c4STomer Tayar 35719c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 35729c8517c4STomer Tayar QED_MSG_SP, 35739c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 35749c8517c4STomer Tayar p_in_params->cmd, 35759c8517c4STomer Tayar p_in_params->res_id, 35769c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 35779c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 35789c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 35799c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 35809c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 35819c8517c4STomer Tayar p_in_params->resc_max_val); 35829c8517c4STomer Tayar 35832edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 35842edbff8dSTomer Tayar if (rc) 35852edbff8dSTomer Tayar return rc; 35862edbff8dSTomer Tayar 35879c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 35889c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 35899c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 35909c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 35919c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 35929c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 35939c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 35942edbff8dSTomer Tayar 35952edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 35962edbff8dSTomer Tayar QED_MSG_SP, 35979c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 35989c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 35999c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 36009c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 36019c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 36029c8517c4STomer Tayar p_out_params->resc_num, 36039c8517c4STomer Tayar p_out_params->resc_start, 36049c8517c4STomer Tayar p_out_params->vf_resc_num, 36059c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 36069c8517c4STomer Tayar 36079c8517c4STomer Tayar return 0; 36089c8517c4STomer Tayar } 36099c8517c4STomer Tayar 36109c8517c4STomer Tayar int 36119c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 36129c8517c4STomer Tayar struct qed_ptt *p_ptt, 36139c8517c4STomer Tayar enum qed_resources res_id, 36149c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 36159c8517c4STomer Tayar { 36169c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 36179c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 36189c8517c4STomer Tayar int rc; 36199c8517c4STomer Tayar 36209c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 36219c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 36229c8517c4STomer Tayar in_params.res_id = res_id; 36239c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 36249c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 36259c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 36269c8517c4STomer Tayar &out_params); 36279c8517c4STomer Tayar if (rc) 36289c8517c4STomer Tayar return rc; 36299c8517c4STomer Tayar 36309c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 36319c8517c4STomer Tayar 36329c8517c4STomer Tayar return 0; 36339c8517c4STomer Tayar } 36349c8517c4STomer Tayar 36359c8517c4STomer Tayar int 36369c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 36379c8517c4STomer Tayar struct qed_ptt *p_ptt, 36389c8517c4STomer Tayar enum qed_resources res_id, 36399c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 36409c8517c4STomer Tayar { 36419c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 36429c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 36439c8517c4STomer Tayar int rc; 36449c8517c4STomer Tayar 36459c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 36469c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 36479c8517c4STomer Tayar in_params.res_id = res_id; 36489c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 36499c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 36509c8517c4STomer Tayar &out_params); 36519c8517c4STomer Tayar if (rc) 36529c8517c4STomer Tayar return rc; 36539c8517c4STomer Tayar 36549c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 36559c8517c4STomer Tayar 36569c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 36579c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 36589c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 36599c8517c4STomer Tayar } 36602edbff8dSTomer Tayar 36612edbff8dSTomer Tayar return 0; 36622edbff8dSTomer Tayar } 366318a69e36SMintz, Yuval 366418a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 366518a69e36SMintz, Yuval { 366618a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 366718a69e36SMintz, Yuval 366818a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 366918a69e36SMintz, Yuval &mcp_resp, &mcp_param); 367018a69e36SMintz, Yuval } 367195691c9cSTomer Tayar 367295691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 367395691c9cSTomer Tayar struct qed_ptt *p_ptt, 367495691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 367595691c9cSTomer Tayar { 367695691c9cSTomer Tayar int rc; 367795691c9cSTomer Tayar 367895691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 367995691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 368095691c9cSTomer Tayar if (rc) 368195691c9cSTomer Tayar return rc; 368295691c9cSTomer Tayar 368395691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 368495691c9cSTomer Tayar DP_INFO(p_hwfn, 368595691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 368695691c9cSTomer Tayar return -EINVAL; 368795691c9cSTomer Tayar } 368895691c9cSTomer Tayar 368995691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 369095691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 369195691c9cSTomer Tayar 369295691c9cSTomer Tayar DP_NOTICE(p_hwfn, 369395691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 369495691c9cSTomer Tayar param, opcode); 369595691c9cSTomer Tayar return -EINVAL; 369695691c9cSTomer Tayar } 369795691c9cSTomer Tayar 369895691c9cSTomer Tayar return rc; 369995691c9cSTomer Tayar } 370095691c9cSTomer Tayar 3701bf774d14SYueHaibing static int 370295691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 370395691c9cSTomer Tayar struct qed_ptt *p_ptt, 370495691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 370595691c9cSTomer Tayar { 370695691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 370795691c9cSTomer Tayar u8 opcode; 370895691c9cSTomer Tayar int rc; 370995691c9cSTomer Tayar 371095691c9cSTomer Tayar switch (p_params->timeout) { 371195691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 371295691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 371395691c9cSTomer Tayar p_params->timeout = 0; 371495691c9cSTomer Tayar break; 371595691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 371695691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 371795691c9cSTomer Tayar p_params->timeout = 0; 371895691c9cSTomer Tayar break; 371995691c9cSTomer Tayar default: 372095691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 372195691c9cSTomer Tayar break; 372295691c9cSTomer Tayar } 372395691c9cSTomer Tayar 372495691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 372595691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 372695691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 372795691c9cSTomer Tayar 372895691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 372995691c9cSTomer Tayar QED_MSG_SP, 373095691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 373195691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 373295691c9cSTomer Tayar 373395691c9cSTomer Tayar /* Attempt to acquire the resource */ 373495691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 373595691c9cSTomer Tayar if (rc) 373695691c9cSTomer Tayar return rc; 373795691c9cSTomer Tayar 373895691c9cSTomer Tayar /* Analyze the response */ 373995691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 374095691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 374195691c9cSTomer Tayar 374295691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 374395691c9cSTomer Tayar QED_MSG_SP, 374495691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 374595691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 374695691c9cSTomer Tayar 374795691c9cSTomer Tayar switch (opcode) { 374895691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 374995691c9cSTomer Tayar p_params->b_granted = true; 375095691c9cSTomer Tayar break; 375195691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 375295691c9cSTomer Tayar p_params->b_granted = false; 375395691c9cSTomer Tayar break; 375495691c9cSTomer Tayar default: 375595691c9cSTomer Tayar DP_NOTICE(p_hwfn, 375695691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 375795691c9cSTomer Tayar mcp_param, opcode); 375895691c9cSTomer Tayar return -EINVAL; 375995691c9cSTomer Tayar } 376095691c9cSTomer Tayar 376195691c9cSTomer Tayar return 0; 376295691c9cSTomer Tayar } 376395691c9cSTomer Tayar 376495691c9cSTomer Tayar int 376595691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 376695691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 376795691c9cSTomer Tayar { 376895691c9cSTomer Tayar u32 retry_cnt = 0; 376995691c9cSTomer Tayar int rc; 377095691c9cSTomer Tayar 377195691c9cSTomer Tayar do { 377295691c9cSTomer Tayar /* No need for an interval before the first iteration */ 377395691c9cSTomer Tayar if (retry_cnt) { 377495691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 377595691c9cSTomer Tayar u16 retry_interval_in_ms = 377695691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 377795691c9cSTomer Tayar 1000); 377895691c9cSTomer Tayar 377995691c9cSTomer Tayar msleep(retry_interval_in_ms); 378095691c9cSTomer Tayar } else { 378195691c9cSTomer Tayar udelay(p_params->retry_interval); 378295691c9cSTomer Tayar } 378395691c9cSTomer Tayar } 378495691c9cSTomer Tayar 378595691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 378695691c9cSTomer Tayar if (rc) 378795691c9cSTomer Tayar return rc; 378895691c9cSTomer Tayar 378995691c9cSTomer Tayar if (p_params->b_granted) 379095691c9cSTomer Tayar break; 379195691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 379295691c9cSTomer Tayar 379395691c9cSTomer Tayar return 0; 379495691c9cSTomer Tayar } 379595691c9cSTomer Tayar 379695691c9cSTomer Tayar int 379795691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 379895691c9cSTomer Tayar struct qed_ptt *p_ptt, 379995691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 380095691c9cSTomer Tayar { 380195691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 380295691c9cSTomer Tayar u8 opcode; 380395691c9cSTomer Tayar int rc; 380495691c9cSTomer Tayar 380595691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 380695691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 380795691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 380895691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 380995691c9cSTomer Tayar 381095691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 381195691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 381295691c9cSTomer Tayar param, opcode, p_params->resource); 381395691c9cSTomer Tayar 381495691c9cSTomer Tayar /* Attempt to release the resource */ 381595691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 381695691c9cSTomer Tayar if (rc) 381795691c9cSTomer Tayar return rc; 381895691c9cSTomer Tayar 381995691c9cSTomer Tayar /* Analyze the response */ 382095691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 382195691c9cSTomer Tayar 382295691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 382395691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 382495691c9cSTomer Tayar mcp_param, opcode); 382595691c9cSTomer Tayar 382695691c9cSTomer Tayar switch (opcode) { 382795691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 382895691c9cSTomer Tayar DP_INFO(p_hwfn, 382995691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 383095691c9cSTomer Tayar p_params->resource); 3831df561f66SGustavo A. R. Silva fallthrough; 383295691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 383395691c9cSTomer Tayar p_params->b_released = true; 383495691c9cSTomer Tayar break; 383595691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 383695691c9cSTomer Tayar p_params->b_released = false; 383795691c9cSTomer Tayar break; 383895691c9cSTomer Tayar default: 383995691c9cSTomer Tayar DP_NOTICE(p_hwfn, 384095691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 384195691c9cSTomer Tayar mcp_param, opcode); 384295691c9cSTomer Tayar return -EINVAL; 384395691c9cSTomer Tayar } 384495691c9cSTomer Tayar 384595691c9cSTomer Tayar return 0; 384695691c9cSTomer Tayar } 3847f470f22cSsudarsana.kalluru@cavium.com 3848f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3849f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3850f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3851f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3852f470f22cSsudarsana.kalluru@cavium.com { 3853f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3854f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3855f470f22cSsudarsana.kalluru@cavium.com 3856f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3857f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3858f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3859f470f22cSsudarsana.kalluru@cavium.com */ 3860f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3861f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3862f470f22cSsudarsana.kalluru@cavium.com } else { 3863f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3864f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3865f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3866f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3867f470f22cSsudarsana.kalluru@cavium.com } 3868f470f22cSsudarsana.kalluru@cavium.com 3869f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3870f470f22cSsudarsana.kalluru@cavium.com } 3871f470f22cSsudarsana.kalluru@cavium.com 3872f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3873f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3874f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3875f470f22cSsudarsana.kalluru@cavium.com } 3876f470f22cSsudarsana.kalluru@cavium.com } 3877645874e5SSudarsana Reddy Kalluru 3878df9c716dSSudarsana Reddy Kalluru bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn) 3879df9c716dSSudarsana Reddy Kalluru { 3880df9c716dSSudarsana Reddy Kalluru return !!(p_hwfn->mcp_info->capabilities & 3881df9c716dSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ); 3882df9c716dSSudarsana Reddy Kalluru } 3883df9c716dSSudarsana Reddy Kalluru 3884645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3885645874e5SSudarsana Reddy Kalluru { 3886645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3887645874e5SSudarsana Reddy Kalluru int rc; 3888645874e5SSudarsana Reddy Kalluru 3889645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3890645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3891645874e5SSudarsana Reddy Kalluru if (!rc) 3892645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3893645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3894645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3895645874e5SSudarsana Reddy Kalluru 3896645874e5SSudarsana Reddy Kalluru return rc; 3897645874e5SSudarsana Reddy Kalluru } 3898645874e5SSudarsana Reddy Kalluru 3899645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3900645874e5SSudarsana Reddy Kalluru { 3901645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3902645874e5SSudarsana Reddy Kalluru 3903e40a826aSSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3904ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK | 3905ae7e6937SAlexander Lobakin DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL; 3906645874e5SSudarsana Reddy Kalluru 3907645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3908645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3909645874e5SSudarsana Reddy Kalluru } 391079284adeSMichal Kalderon 391179284adeSMichal Kalderon int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 391279284adeSMichal Kalderon { 391379284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 391479284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 391579284adeSMichal Kalderon u8 fir_valid, l2_valid; 391679284adeSMichal Kalderon int rc; 391779284adeSMichal Kalderon 391879284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG; 391979284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 392079284adeSMichal Kalderon if (rc) 392179284adeSMichal Kalderon return rc; 392279284adeSMichal Kalderon 392379284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 392479284adeSMichal Kalderon DP_INFO(p_hwfn, 392579284adeSMichal Kalderon "The get_engine_config command is unsupported by the MFW\n"); 392679284adeSMichal Kalderon return -EOPNOTSUPP; 392779284adeSMichal Kalderon } 392879284adeSMichal Kalderon 392979284adeSMichal Kalderon fir_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 393079284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID); 393179284adeSMichal Kalderon if (fir_valid) 393279284adeSMichal Kalderon cdev->fir_affin = 393379284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 393479284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE); 393579284adeSMichal Kalderon 393679284adeSMichal Kalderon l2_valid = QED_MFW_GET_FIELD(mb_params.mcp_param, 393779284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID); 393879284adeSMichal Kalderon if (l2_valid) 393979284adeSMichal Kalderon cdev->l2_affin_hint = 394079284adeSMichal Kalderon QED_MFW_GET_FIELD(mb_params.mcp_param, 394179284adeSMichal Kalderon FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE); 394279284adeSMichal Kalderon 394379284adeSMichal Kalderon DP_INFO(p_hwfn, 394479284adeSMichal Kalderon "Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n", 394579284adeSMichal Kalderon fir_valid, cdev->fir_affin, l2_valid, cdev->l2_affin_hint); 394679284adeSMichal Kalderon 394779284adeSMichal Kalderon return 0; 394879284adeSMichal Kalderon } 394979284adeSMichal Kalderon 395079284adeSMichal Kalderon int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 395179284adeSMichal Kalderon { 395279284adeSMichal Kalderon struct qed_mcp_mb_params mb_params = {0}; 395379284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 395479284adeSMichal Kalderon int rc; 395579284adeSMichal Kalderon 395679284adeSMichal Kalderon mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP; 395779284adeSMichal Kalderon rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 395879284adeSMichal Kalderon if (rc) 395979284adeSMichal Kalderon return rc; 396079284adeSMichal Kalderon 396179284adeSMichal Kalderon if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 396279284adeSMichal Kalderon DP_INFO(p_hwfn, 396379284adeSMichal Kalderon "The get_ppfid_bitmap command is unsupported by the MFW\n"); 396479284adeSMichal Kalderon return -EOPNOTSUPP; 396579284adeSMichal Kalderon } 396679284adeSMichal Kalderon 396779284adeSMichal Kalderon cdev->ppfid_bitmap = QED_MFW_GET_FIELD(mb_params.mcp_param, 396879284adeSMichal Kalderon FW_MB_PARAM_PPFID_BITMAP); 396979284adeSMichal Kalderon 397079284adeSMichal Kalderon DP_VERBOSE(p_hwfn, QED_MSG_SP, "PPFID bitmap 0x%hhx\n", 397179284adeSMichal Kalderon cdev->ppfid_bitmap); 397279284adeSMichal Kalderon 397379284adeSMichal Kalderon return 0; 397479284adeSMichal Kalderon } 397538eabdf0SSudarsana Reddy Kalluru 39762d4c8495SSudarsana Reddy Kalluru int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 39772d4c8495SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 39782d4c8495SSudarsana Reddy Kalluru u32 *p_len) 39792d4c8495SSudarsana Reddy Kalluru { 39802d4c8495SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 39812d4c8495SSudarsana Reddy Kalluru int rc; 39822d4c8495SSudarsana Reddy Kalluru 39832d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 39842d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 39852d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39862d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 39872d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 39882d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39892d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 39902d4c8495SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 39912d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39922d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 39932d4c8495SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 39942d4c8495SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 39952d4c8495SSudarsana Reddy Kalluru entity_id); 39962d4c8495SSudarsana Reddy Kalluru } 39972d4c8495SSudarsana Reddy Kalluru 39982d4c8495SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 39992d4c8495SSudarsana Reddy Kalluru DRV_MSG_CODE_GET_NVM_CFG_OPTION, 40006c95dd8fSPrabhakar Kushwaha mb_param, &resp, ¶m, p_len, 40016c95dd8fSPrabhakar Kushwaha (u32 *)p_buf, false); 40022d4c8495SSudarsana Reddy Kalluru 40032d4c8495SSudarsana Reddy Kalluru return rc; 40042d4c8495SSudarsana Reddy Kalluru } 40052d4c8495SSudarsana Reddy Kalluru 400638eabdf0SSudarsana Reddy Kalluru int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 400738eabdf0SSudarsana Reddy Kalluru u16 option_id, u8 entity_id, u16 flags, u8 *p_buf, 400838eabdf0SSudarsana Reddy Kalluru u32 len) 400938eabdf0SSudarsana Reddy Kalluru { 401038eabdf0SSudarsana Reddy Kalluru u32 mb_param = 0, resp, param; 401138eabdf0SSudarsana Reddy Kalluru 401238eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id); 401338eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ALL) 401438eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 401538eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1); 401638eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_INIT) 401738eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 401838eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1); 401938eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_COMMIT) 402038eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 402138eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1); 402238eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_FREE) 402338eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 402438eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1); 402538eabdf0SSudarsana Reddy Kalluru if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) { 402638eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 402738eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1); 402838eabdf0SSudarsana Reddy Kalluru QED_MFW_SET_FIELD(mb_param, 402938eabdf0SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID, 403038eabdf0SSudarsana Reddy Kalluru entity_id); 403138eabdf0SSudarsana Reddy Kalluru } 403238eabdf0SSudarsana Reddy Kalluru 403338eabdf0SSudarsana Reddy Kalluru return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, 403438eabdf0SSudarsana Reddy Kalluru DRV_MSG_CODE_SET_NVM_CFG_OPTION, 403538eabdf0SSudarsana Reddy Kalluru mb_param, &resp, ¶m, len, (u32 *)p_buf); 403638eabdf0SSudarsana Reddy Kalluru } 4037d8d6c5a7SIgor Russkikh 4038d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_SIZE MCP_DRV_NVM_BUF_LEN 4039d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_HEADER_SIZE sizeof(u32) 4040d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE \ 4041d8d6c5a7SIgor Russkikh (QED_MCP_DBG_DATA_MAX_SIZE - QED_MCP_DBG_DATA_MAX_HEADER_SIZE) 4042d8d6c5a7SIgor Russkikh 4043d8d6c5a7SIgor Russkikh static int 4044d8d6c5a7SIgor Russkikh __qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 4045d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u8 size) 4046d8d6c5a7SIgor Russkikh { 4047d8d6c5a7SIgor Russkikh struct qed_mcp_mb_params mb_params; 4048d8d6c5a7SIgor Russkikh int rc; 4049d8d6c5a7SIgor Russkikh 4050d8d6c5a7SIgor Russkikh if (size > QED_MCP_DBG_DATA_MAX_SIZE) { 4051d8d6c5a7SIgor Russkikh DP_ERR(p_hwfn, 4052d8d6c5a7SIgor Russkikh "Debug data size is %d while it should not exceed %d\n", 4053d8d6c5a7SIgor Russkikh size, QED_MCP_DBG_DATA_MAX_SIZE); 4054d8d6c5a7SIgor Russkikh return -EINVAL; 4055d8d6c5a7SIgor Russkikh } 4056d8d6c5a7SIgor Russkikh 4057d8d6c5a7SIgor Russkikh memset(&mb_params, 0, sizeof(mb_params)); 4058d8d6c5a7SIgor Russkikh mb_params.cmd = DRV_MSG_CODE_DEBUG_DATA_SEND; 4059d8d6c5a7SIgor Russkikh SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE, size); 4060d8d6c5a7SIgor Russkikh mb_params.p_data_src = p_buf; 4061d8d6c5a7SIgor Russkikh mb_params.data_src_size = size; 4062d8d6c5a7SIgor Russkikh rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 4063d8d6c5a7SIgor Russkikh if (rc) 4064d8d6c5a7SIgor Russkikh return rc; 4065d8d6c5a7SIgor Russkikh 4066d8d6c5a7SIgor Russkikh if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 4067d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, 4068d8d6c5a7SIgor Russkikh "The DEBUG_DATA_SEND command is unsupported by the MFW\n"); 4069d8d6c5a7SIgor Russkikh return -EOPNOTSUPP; 4070d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp == (u32)FW_MSG_CODE_DEBUG_NOT_ENABLED) { 4071d8d6c5a7SIgor Russkikh DP_INFO(p_hwfn, "The DEBUG_DATA_SEND command is not enabled\n"); 4072d8d6c5a7SIgor Russkikh return -EBUSY; 4073d8d6c5a7SIgor Russkikh } else if (mb_params.mcp_resp != (u32)FW_MSG_CODE_DEBUG_DATA_SEND_OK) { 4074d8d6c5a7SIgor Russkikh DP_NOTICE(p_hwfn, 4075d8d6c5a7SIgor Russkikh "Failed to send debug data to the MFW [resp 0x%08x]\n", 4076d8d6c5a7SIgor Russkikh mb_params.mcp_resp); 4077d8d6c5a7SIgor Russkikh return -EINVAL; 4078d8d6c5a7SIgor Russkikh } 4079d8d6c5a7SIgor Russkikh 4080d8d6c5a7SIgor Russkikh return 0; 4081d8d6c5a7SIgor Russkikh } 4082d8d6c5a7SIgor Russkikh 4083d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type { 4084d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, 4085d8d6c5a7SIgor Russkikh }; 4086d8d6c5a7SIgor Russkikh 4087d8d6c5a7SIgor Russkikh /* Header format: [31:28] PFID, [27:20] flags, [19:12] type, [11:0] S/N */ 4088d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_OFFSET 0 4089d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_SN_MASK 0x00000fff 4090d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_OFFSET 12 4091d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_TYPE_MASK 0x000ff000 4092d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_OFFSET 20 4093d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_MASK 0x0ff00000 4094d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_OFFSET 28 4095d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_PF_MASK 0xf0000000 4096d8d6c5a7SIgor Russkikh 4097d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_FIRST 0x1 4098d8d6c5a7SIgor Russkikh #define QED_MCP_DBG_DATA_HDR_FLAGS_LAST 0x2 4099d8d6c5a7SIgor Russkikh 4100d8d6c5a7SIgor Russkikh static int 4101d8d6c5a7SIgor Russkikh qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn, 4102d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, 4103d8d6c5a7SIgor Russkikh enum qed_mcp_dbg_data_type type, u8 *p_buf, u32 size) 4104d8d6c5a7SIgor Russkikh { 4105d8d6c5a7SIgor Russkikh u8 raw_data[QED_MCP_DBG_DATA_MAX_SIZE], *p_tmp_buf = p_buf; 4106d8d6c5a7SIgor Russkikh u32 tmp_size = size, *p_header, *p_payload; 4107d8d6c5a7SIgor Russkikh u8 flags = 0; 4108d8d6c5a7SIgor Russkikh u16 seq; 4109d8d6c5a7SIgor Russkikh int rc; 4110d8d6c5a7SIgor Russkikh 4111d8d6c5a7SIgor Russkikh p_header = (u32 *)raw_data; 4112d8d6c5a7SIgor Russkikh p_payload = (u32 *)(raw_data + QED_MCP_DBG_DATA_MAX_HEADER_SIZE); 4113d8d6c5a7SIgor Russkikh 4114d8d6c5a7SIgor Russkikh seq = (u16)atomic_inc_return(&p_hwfn->mcp_info->dbg_data_seq); 4115d8d6c5a7SIgor Russkikh 4116d8d6c5a7SIgor Russkikh /* First chunk is marked as 'first' */ 4117d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4118d8d6c5a7SIgor Russkikh 4119d8d6c5a7SIgor Russkikh *p_header = 0; 4120d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_SN, seq); 4121d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_TYPE, type); 4122d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4123d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_PF, p_hwfn->abs_pf_id); 4124d8d6c5a7SIgor Russkikh 4125d8d6c5a7SIgor Russkikh while (tmp_size > QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE) { 4126d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE); 4127d8d6c5a7SIgor Russkikh rc = __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4128d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_MAX_SIZE); 4129d8d6c5a7SIgor Russkikh if (rc) 4130d8d6c5a7SIgor Russkikh return rc; 4131d8d6c5a7SIgor Russkikh 4132d8d6c5a7SIgor Russkikh /* Clear the 'first' marking after sending the first chunk */ 4133d8d6c5a7SIgor Russkikh if (p_tmp_buf == p_buf) { 4134d8d6c5a7SIgor Russkikh flags &= ~QED_MCP_DBG_DATA_HDR_FLAGS_FIRST; 4135d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, 4136d8d6c5a7SIgor Russkikh flags); 4137d8d6c5a7SIgor Russkikh } 4138d8d6c5a7SIgor Russkikh 4139d8d6c5a7SIgor Russkikh p_tmp_buf += QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4140d8d6c5a7SIgor Russkikh tmp_size -= QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE; 4141d8d6c5a7SIgor Russkikh } 4142d8d6c5a7SIgor Russkikh 4143d8d6c5a7SIgor Russkikh /* Last chunk is marked as 'last' */ 4144d8d6c5a7SIgor Russkikh flags |= QED_MCP_DBG_DATA_HDR_FLAGS_LAST; 4145d8d6c5a7SIgor Russkikh SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags); 4146d8d6c5a7SIgor Russkikh memcpy(p_payload, p_tmp_buf, tmp_size); 4147d8d6c5a7SIgor Russkikh 4148d8d6c5a7SIgor Russkikh /* Casting the left size to u8 is ok since at this point it is <= 32 */ 4149d8d6c5a7SIgor Russkikh return __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data, 4150d8d6c5a7SIgor Russkikh (u8)(QED_MCP_DBG_DATA_MAX_HEADER_SIZE + 4151d8d6c5a7SIgor Russkikh tmp_size)); 4152d8d6c5a7SIgor Russkikh } 4153d8d6c5a7SIgor Russkikh 4154d8d6c5a7SIgor Russkikh int 4155d8d6c5a7SIgor Russkikh qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn, 4156d8d6c5a7SIgor Russkikh struct qed_ptt *p_ptt, u8 *p_buf, u32 size) 4157d8d6c5a7SIgor Russkikh { 4158d8d6c5a7SIgor Russkikh return qed_mcp_send_debug_data(p_hwfn, p_ptt, 4159d8d6c5a7SIgor Russkikh QED_MCP_DBG_DATA_TYPE_RAW, p_buf, size); 4160d8d6c5a7SIgor Russkikh } 4161*823163baSManish Chopra 4162*823163baSManish Chopra bool qed_mcp_is_esl_supported(struct qed_hwfn *p_hwfn) 4163*823163baSManish Chopra { 4164*823163baSManish Chopra return !!(p_hwfn->mcp_info->capabilities & 4165*823163baSManish Chopra FW_MB_PARAM_FEATURE_SUPPORT_ENHANCED_SYS_LCK); 4166*823163baSManish Chopra } 4167*823163baSManish Chopra 4168*823163baSManish Chopra int qed_mcp_get_esl_status(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool *active) 4169*823163baSManish Chopra { 4170*823163baSManish Chopra u32 resp = 0, param = 0; 4171*823163baSManish Chopra int rc; 4172*823163baSManish Chopra 4173*823163baSManish Chopra rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MANAGEMENT_STATUS, 0, &resp, ¶m); 4174*823163baSManish Chopra if (rc) { 4175*823163baSManish Chopra DP_NOTICE(p_hwfn, "Failed to send ESL command, rc = %d\n", rc); 4176*823163baSManish Chopra return rc; 4177*823163baSManish Chopra } 4178*823163baSManish Chopra 4179*823163baSManish Chopra *active = !!(param & FW_MB_PARAM_MANAGEMENT_STATUS_LOCKDOWN_ENABLED); 4180*823163baSManish Chopra 4181*823163baSManish Chopra return 0; 4182*823163baSManish Chopra } 4183