1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 43cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 4439651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 45fe56b9e6SYuval Mintz #include "qed_hsi.h" 46fe56b9e6SYuval Mintz #include "qed_hw.h" 47fe56b9e6SYuval Mintz #include "qed_mcp.h" 48fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 491408cc1fSYuval Mintz #include "qed_sriov.h" 501408cc1fSYuval Mintz 51eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58fe56b9e6SYuval Mintz _val) 59fe56b9e6SYuval Mintz 60fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62fe56b9e6SYuval Mintz 63fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 66fe56b9e6SYuval Mintz 67fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 70fe56b9e6SYuval Mintz 71fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77fe56b9e6SYuval Mintz { 78fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79fe56b9e6SYuval Mintz return false; 80fe56b9e6SYuval Mintz return true; 81fe56b9e6SYuval Mintz } 82fe56b9e6SYuval Mintz 831a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84fe56b9e6SYuval Mintz { 85fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86fe56b9e6SYuval Mintz PUBLIC_PORT); 87fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 91fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 92fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 93fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94fe56b9e6SYuval Mintz } 95fe56b9e6SYuval Mintz 961a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97fe56b9e6SYuval Mintz { 98fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99fe56b9e6SYuval Mintz u32 tmp, i; 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 102fe56b9e6SYuval Mintz return; 103fe56b9e6SYuval Mintz 104fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 105fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 106fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 107fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 108fe56b9e6SYuval Mintz 109fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 110fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz } 114fe56b9e6SYuval Mintz 1154ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1164ed1eea8STomer Tayar struct list_head list; 1174ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1184ed1eea8STomer Tayar u16 expected_seq_num; 1194ed1eea8STomer Tayar bool b_is_completed; 1204ed1eea8STomer Tayar }; 1214ed1eea8STomer Tayar 1224ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1234ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1244ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1254ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1264ed1eea8STomer Tayar u16 expected_seq_num) 1274ed1eea8STomer Tayar { 1284ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1294ed1eea8STomer Tayar 1304ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1314ed1eea8STomer Tayar if (!p_cmd_elem) 1324ed1eea8STomer Tayar goto out; 1334ed1eea8STomer Tayar 1344ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1354ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1364ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1374ed1eea8STomer Tayar out: 1384ed1eea8STomer Tayar return p_cmd_elem; 1394ed1eea8STomer Tayar } 1404ed1eea8STomer Tayar 1414ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1424ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1444ed1eea8STomer Tayar { 1454ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1464ed1eea8STomer Tayar kfree(p_cmd_elem); 1474ed1eea8STomer Tayar } 1484ed1eea8STomer Tayar 1494ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1504ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1514ed1eea8STomer Tayar u16 seq_num) 1524ed1eea8STomer Tayar { 1534ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1544ed1eea8STomer Tayar 1554ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1564ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1574ed1eea8STomer Tayar return p_cmd_elem; 1584ed1eea8STomer Tayar } 1594ed1eea8STomer Tayar 1604ed1eea8STomer Tayar return NULL; 1614ed1eea8STomer Tayar } 1624ed1eea8STomer Tayar 163fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 164fe56b9e6SYuval Mintz { 165fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1664ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1674ed1eea8STomer Tayar 168fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 169fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1704ed1eea8STomer Tayar 1714ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1724ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1734ed1eea8STomer Tayar p_tmp, 1744ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1754ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176fe56b9e6SYuval Mintz } 1774ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1784ed1eea8STomer Tayar } 1794ed1eea8STomer Tayar 180fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1813587cb87STomer Tayar p_hwfn->mcp_info = NULL; 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz return 0; 184fe56b9e6SYuval Mintz } 185fe56b9e6SYuval Mintz 186f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 187f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 188f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 189f00d25f3STomer Tayar 1901a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 191fe56b9e6SYuval Mintz { 192fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 193f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 194f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 195fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 196fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 199f00d25f3STomer Tayar if (!p_info->public_base) { 200f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 201f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 202f00d25f3STomer Tayar return -EINVAL; 203f00d25f3STomer Tayar } 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 206fe56b9e6SYuval Mintz 207f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 208f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 210f00d25f3STomer Tayar PUBLIC_MFW_MB)); 211f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 213f00d25f3STomer Tayar p_info->mfw_mb_addr + 214f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 215f00d25f3STomer Tayar sup_msgs)); 216f00d25f3STomer Tayar 217f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 218f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 219f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 220f00d25f3STomer Tayar * data ready indication. 221f00d25f3STomer Tayar */ 222f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 223f00d25f3STomer Tayar msleep(msec); 224f00d25f3STomer Tayar p_info->mfw_mb_length = 225f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 226f00d25f3STomer Tayar p_info->mfw_mb_addr + 227f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 228f00d25f3STomer Tayar } 229f00d25f3STomer Tayar 230f00d25f3STomer Tayar if (!cnt) { 231f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 232f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 233f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 234f00d25f3STomer Tayar return -EBUSY; 235f00d25f3STomer Tayar } 236f00d25f3STomer Tayar 237fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 238fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 239fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 240fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 241fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 242fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 243fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 244fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 245fe56b9e6SYuval Mintz 246fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 247fe56b9e6SYuval Mintz * the first command 248fe56b9e6SYuval Mintz */ 249fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 250fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 253fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 254fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 255fe56b9e6SYuval Mintz 2564ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 257fe56b9e6SYuval Mintz 258fe56b9e6SYuval Mintz return 0; 259fe56b9e6SYuval Mintz } 260fe56b9e6SYuval Mintz 2611a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 262fe56b9e6SYuval Mintz { 263fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 264fe56b9e6SYuval Mintz u32 size; 265fe56b9e6SYuval Mintz 266fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 26760fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 268fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 269fe56b9e6SYuval Mintz goto err; 270fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 271fe56b9e6SYuval Mintz 2724ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2734ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2744ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2754ed1eea8STomer Tayar 2764ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2774ed1eea8STomer Tayar 278fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 279fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 280fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 281fe56b9e6SYuval Mintz * the MCP is not initialized 282fe56b9e6SYuval Mintz */ 283fe56b9e6SYuval Mintz return 0; 284fe56b9e6SYuval Mintz } 285fe56b9e6SYuval Mintz 286fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 28760fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 28883aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 289eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 290fe56b9e6SYuval Mintz goto err; 291fe56b9e6SYuval Mintz 292fe56b9e6SYuval Mintz return 0; 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz err: 295fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 296fe56b9e6SYuval Mintz return -ENOMEM; 297fe56b9e6SYuval Mintz } 298fe56b9e6SYuval Mintz 2994ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 3004ed1eea8STomer Tayar struct qed_ptt *p_ptt) 3015529bad9STomer Tayar { 3024ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3035529bad9STomer Tayar 3044ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 3054ed1eea8STomer Tayar * time and now. 3065529bad9STomer Tayar */ 3074ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 3084ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 3094ed1eea8STomer Tayar QED_MSG_SP, 3104ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 3114ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 3125529bad9STomer Tayar 3134ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 3144ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 3155529bad9STomer Tayar } 3165529bad9STomer Tayar } 3175529bad9STomer Tayar 3181a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319fe56b9e6SYuval Mintz { 320eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 321fe56b9e6SYuval Mintz int rc = 0; 322fe56b9e6SYuval Mintz 323b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 324b310974eSTomer Tayar DP_NOTICE(p_hwfn, 325b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 326b310974eSTomer Tayar return -EBUSY; 327b310974eSTomer Tayar } 328b310974eSTomer Tayar 3294ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3304ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3314ed1eea8STomer Tayar 3324ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3335529bad9STomer Tayar 334fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3354ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3364ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3374ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 338fe56b9e6SYuval Mintz 339fe56b9e6SYuval Mintz do { 340fe56b9e6SYuval Mintz /* Wait for MFW response */ 341fe56b9e6SYuval Mintz udelay(delay); 342fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 343fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 344fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 345fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 346fe56b9e6SYuval Mintz 347fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 348fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 349fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 350fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 351fe56b9e6SYuval Mintz } else { 352fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 353fe56b9e6SYuval Mintz rc = -EAGAIN; 354fe56b9e6SYuval Mintz } 355fe56b9e6SYuval Mintz 3564ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3575529bad9STomer Tayar 358fe56b9e6SYuval Mintz return rc; 359fe56b9e6SYuval Mintz } 360fe56b9e6SYuval Mintz 3614ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3624ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 363fe56b9e6SYuval Mintz { 3644ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3654ed1eea8STomer Tayar 3664ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3674ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3684ed1eea8STomer Tayar */ 3694ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3704ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3714ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3724ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3734ed1eea8STomer Tayar } 3744ed1eea8STomer Tayar 3754ed1eea8STomer Tayar return false; 3764ed1eea8STomer Tayar } 3774ed1eea8STomer Tayar 3784ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3794ed1eea8STomer Tayar static int 3804ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3814ed1eea8STomer Tayar { 3824ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3834ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3844ed1eea8STomer Tayar u32 mcp_resp; 3854ed1eea8STomer Tayar u16 seq_num; 3864ed1eea8STomer Tayar 3874ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3884ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3894ed1eea8STomer Tayar 3904ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3914ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3924ed1eea8STomer Tayar return -EAGAIN; 3934ed1eea8STomer Tayar 3944ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3954ed1eea8STomer Tayar if (!p_cmd_elem) { 3964ed1eea8STomer Tayar DP_ERR(p_hwfn, 3974ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3984ed1eea8STomer Tayar seq_num); 3994ed1eea8STomer Tayar return -EINVAL; 4004ed1eea8STomer Tayar } 4014ed1eea8STomer Tayar 4024ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 4034ed1eea8STomer Tayar 4044ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 4054ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 4064ed1eea8STomer Tayar 4074ed1eea8STomer Tayar /* Get the MFW param */ 4084ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 4094ed1eea8STomer Tayar 4104ed1eea8STomer Tayar /* Get the union data */ 4112f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 4124ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4134ed1eea8STomer Tayar offsetof(struct public_drv_mb, 4144ed1eea8STomer Tayar union_data); 4154ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 4162f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 4174ed1eea8STomer Tayar } 4184ed1eea8STomer Tayar 4194ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 4204ed1eea8STomer Tayar 4214ed1eea8STomer Tayar return 0; 4224ed1eea8STomer Tayar } 4234ed1eea8STomer Tayar 4244ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4254ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4264ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4274ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4284ed1eea8STomer Tayar u16 seq_num) 4294ed1eea8STomer Tayar { 4304ed1eea8STomer Tayar union drv_union_data union_data; 4314ed1eea8STomer Tayar u32 union_data_addr; 4324ed1eea8STomer Tayar 4334ed1eea8STomer Tayar /* Set the union data */ 4344ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4354ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4364ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4372f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 4384ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4392f67af8cSTomer Tayar p_mb_params->data_src_size); 4404ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4414ed1eea8STomer Tayar sizeof(union_data)); 4424ed1eea8STomer Tayar 4434ed1eea8STomer Tayar /* Set the drv param */ 4444ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4454ed1eea8STomer Tayar 4464ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4474ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4484ed1eea8STomer Tayar 4494ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4504ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4514ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4524ed1eea8STomer Tayar } 4534ed1eea8STomer Tayar 454b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 455b310974eSTomer Tayar { 456b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 457b310974eSTomer Tayar 458b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 459b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 460b310974eSTomer Tayar } 461b310974eSTomer Tayar 462b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 463b310974eSTomer Tayar struct qed_ptt *p_ptt) 464b310974eSTomer Tayar { 465b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 466b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 467b310974eSTomer Tayar 468b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 469b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 470b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 471b310974eSTomer Tayar udelay(delay); 472b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 473b310974eSTomer Tayar udelay(delay); 474b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 475b310974eSTomer Tayar 476b310974eSTomer Tayar DP_NOTICE(p_hwfn, 477b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 478b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 479b310974eSTomer Tayar } 480b310974eSTomer Tayar 4814ed1eea8STomer Tayar static int 4824ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4834ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4844ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 485eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4864ed1eea8STomer Tayar { 487eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4884ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4894ed1eea8STomer Tayar u16 seq_num; 490fe56b9e6SYuval Mintz int rc = 0; 491fe56b9e6SYuval Mintz 4924ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 493fe56b9e6SYuval Mintz do { 4944ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4954ed1eea8STomer Tayar * pending command is completed during this iteration. 4964ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4974ed1eea8STomer Tayar */ 4984ed1eea8STomer Tayar 4994ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 5024ed1eea8STomer Tayar break; 5034ed1eea8STomer Tayar 5044ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5054ed1eea8STomer Tayar if (!rc) 5064ed1eea8STomer Tayar break; 5074ed1eea8STomer Tayar else if (rc != -EAGAIN) 5084ed1eea8STomer Tayar goto err; 5094ed1eea8STomer Tayar 5104ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 511eaa50fc5STomer Tayar 512eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 513eaa50fc5STomer Tayar msleep(msecs); 514eaa50fc5STomer Tayar else 515eaa50fc5STomer Tayar udelay(usecs); 5164ed1eea8STomer Tayar } while (++cnt < max_retries); 517fe56b9e6SYuval Mintz 5184ed1eea8STomer Tayar if (cnt >= max_retries) { 5194ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5204ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 5214ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 5224ed1eea8STomer Tayar return -EAGAIN; 523fe56b9e6SYuval Mintz } 5244ed1eea8STomer Tayar 5254ed1eea8STomer Tayar /* Send the mailbox command */ 5264ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5274ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5284ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 529c8004600SDan Carpenter if (!p_cmd_elem) { 530c8004600SDan Carpenter rc = -ENOMEM; 5314ed1eea8STomer Tayar goto err; 532c8004600SDan Carpenter } 5334ed1eea8STomer Tayar 5344ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5354ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5364ed1eea8STomer Tayar 5374ed1eea8STomer Tayar /* Wait for the MFW response */ 5384ed1eea8STomer Tayar do { 5394ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5404ed1eea8STomer Tayar * command is completed during this iteration. 5414ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5424ed1eea8STomer Tayar */ 5434ed1eea8STomer Tayar 544eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 545eaa50fc5STomer Tayar msleep(msecs); 546eaa50fc5STomer Tayar else 547eaa50fc5STomer Tayar udelay(usecs); 548eaa50fc5STomer Tayar 5494ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5504ed1eea8STomer Tayar 5514ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5524ed1eea8STomer Tayar break; 5534ed1eea8STomer Tayar 5544ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5554ed1eea8STomer Tayar if (!rc) 5564ed1eea8STomer Tayar break; 5574ed1eea8STomer Tayar else if (rc != -EAGAIN) 5584ed1eea8STomer Tayar goto err; 5594ed1eea8STomer Tayar 5604ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5614ed1eea8STomer Tayar } while (++cnt < max_retries); 5624ed1eea8STomer Tayar 5634ed1eea8STomer Tayar if (cnt >= max_retries) { 5644ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5654ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5664ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 567b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5684ed1eea8STomer Tayar 5694ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5704ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5714ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5724ed1eea8STomer Tayar 573b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 574b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 575b310974eSTomer Tayar 5764ed1eea8STomer Tayar return -EAGAIN; 5774ed1eea8STomer Tayar } 5784ed1eea8STomer Tayar 5794ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5804ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5814ed1eea8STomer Tayar 5824ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5834ed1eea8STomer Tayar QED_MSG_SP, 5844ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5854ed1eea8STomer Tayar p_mb_params->mcp_resp, 5864ed1eea8STomer Tayar p_mb_params->mcp_param, 587eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5884ed1eea8STomer Tayar 5894ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5904ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5914ed1eea8STomer Tayar 5924ed1eea8STomer Tayar return 0; 5934ed1eea8STomer Tayar 5944ed1eea8STomer Tayar err: 5954ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 596fe56b9e6SYuval Mintz return rc; 597fe56b9e6SYuval Mintz } 598fe56b9e6SYuval Mintz 5995529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 600fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 6015529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 602fe56b9e6SYuval Mintz { 6032f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 6044ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 605eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 606fe56b9e6SYuval Mintz 607fe56b9e6SYuval Mintz /* MCP not initialized */ 608fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 609fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 610fe56b9e6SYuval Mintz return -EBUSY; 611fe56b9e6SYuval Mintz } 612fe56b9e6SYuval Mintz 613b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 614b310974eSTomer Tayar DP_NOTICE(p_hwfn, 615b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 616b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 617b310974eSTomer Tayar return -EBUSY; 618b310974eSTomer Tayar } 619b310974eSTomer Tayar 6202f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 6212f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6222f67af8cSTomer Tayar DP_ERR(p_hwfn, 6232f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6242f67af8cSTomer Tayar p_mb_params->data_src_size, 6252f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6262f67af8cSTomer Tayar return -EINVAL; 6272f67af8cSTomer Tayar } 6282f67af8cSTomer Tayar 629eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 630eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 631eaa50fc5STomer Tayar usecs *= 1000; 632eaa50fc5STomer Tayar } 633eaa50fc5STomer Tayar 6344ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 635eaa50fc5STomer Tayar usecs); 636fe56b9e6SYuval Mintz } 637fe56b9e6SYuval Mintz 6385529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6395529bad9STomer Tayar struct qed_ptt *p_ptt, 6405529bad9STomer Tayar u32 cmd, 6415529bad9STomer Tayar u32 param, 6425529bad9STomer Tayar u32 *o_mcp_resp, 6435529bad9STomer Tayar u32 *o_mcp_param) 644fe56b9e6SYuval Mintz { 6455529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6465529bad9STomer Tayar int rc; 647fe56b9e6SYuval Mintz 6485529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6495529bad9STomer Tayar mb_params.cmd = cmd; 6505529bad9STomer Tayar mb_params.param = param; 65114d39648SMintz, Yuval 6525529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6535529bad9STomer Tayar if (rc) 6545529bad9STomer Tayar return rc; 6555529bad9STomer Tayar 6565529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6575529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6585529bad9STomer Tayar 6595529bad9STomer Tayar return 0; 660fe56b9e6SYuval Mintz } 661fe56b9e6SYuval Mintz 662bf774d14SYueHaibing static int 663bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 66462e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 66562e4d438SSudarsana Reddy Kalluru u32 cmd, 66662e4d438SSudarsana Reddy Kalluru u32 param, 66762e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 66862e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 66962e4d438SSudarsana Reddy Kalluru { 67062e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 67162e4d438SSudarsana Reddy Kalluru int rc; 67262e4d438SSudarsana Reddy Kalluru 67362e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 67462e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 67562e4d438SSudarsana Reddy Kalluru mb_params.param = param; 67662e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 67762e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 67862e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 67962e4d438SSudarsana Reddy Kalluru if (rc) 68062e4d438SSudarsana Reddy Kalluru return rc; 68162e4d438SSudarsana Reddy Kalluru 68262e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 68362e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 68462e4d438SSudarsana Reddy Kalluru 6855e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6865e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6875e7ba042SDenis Bolotin 68862e4d438SSudarsana Reddy Kalluru return 0; 68962e4d438SSudarsana Reddy Kalluru } 69062e4d438SSudarsana Reddy Kalluru 6914102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6924102426fSTomer Tayar struct qed_ptt *p_ptt, 6934102426fSTomer Tayar u32 cmd, 6944102426fSTomer Tayar u32 param, 6954102426fSTomer Tayar u32 *o_mcp_resp, 6964102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6974102426fSTomer Tayar { 6984102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6992f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 7004102426fSTomer Tayar int rc; 7014102426fSTomer Tayar 7024102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7034102426fSTomer Tayar mb_params.cmd = cmd; 7044102426fSTomer Tayar mb_params.param = param; 7052f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 7062f67af8cSTomer Tayar 7072f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 7082f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 7092f67af8cSTomer Tayar 7104102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7114102426fSTomer Tayar if (rc) 7124102426fSTomer Tayar return rc; 7134102426fSTomer Tayar 7144102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 7154102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 7164102426fSTomer Tayar 7174102426fSTomer Tayar *o_txn_size = *o_mcp_param; 7182f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 7194102426fSTomer Tayar 7204102426fSTomer Tayar return 0; 7214102426fSTomer Tayar } 7224102426fSTomer Tayar 7235d24bcf1STomer Tayar static bool 7245d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7255d24bcf1STomer Tayar u8 exist_drv_role, 7265d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 727fe56b9e6SYuval Mintz { 7285d24bcf1STomer Tayar bool can_force_load = false; 7295d24bcf1STomer Tayar 7305d24bcf1STomer Tayar switch (override_force_load) { 7315d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7325d24bcf1STomer Tayar can_force_load = true; 7335d24bcf1STomer Tayar break; 7345d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7355d24bcf1STomer Tayar can_force_load = false; 7365d24bcf1STomer Tayar break; 7375d24bcf1STomer Tayar default: 7385d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7395d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7405d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7415d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7425d24bcf1STomer Tayar break; 7435d24bcf1STomer Tayar } 7445d24bcf1STomer Tayar 7455d24bcf1STomer Tayar return can_force_load; 7465d24bcf1STomer Tayar } 7475d24bcf1STomer Tayar 7485d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7495d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7505d24bcf1STomer Tayar { 7515d24bcf1STomer Tayar u32 resp = 0, param = 0; 752fe56b9e6SYuval Mintz int rc; 753fe56b9e6SYuval Mintz 7545d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7555d24bcf1STomer Tayar &resp, ¶m); 7565d24bcf1STomer Tayar if (rc) 7575d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7585d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 759fe56b9e6SYuval Mintz 760fe56b9e6SYuval Mintz return rc; 761fe56b9e6SYuval Mintz } 762fe56b9e6SYuval Mintz 7635d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7645d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7655d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7665d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7675d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7685d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7695529bad9STomer Tayar 7705d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7715d24bcf1STomer Tayar { 7725d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7735d24bcf1STomer Tayar 7745d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7755d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7765d24bcf1STomer Tayar 7775d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7785d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7795d24bcf1STomer Tayar 7805d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7815d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7825d24bcf1STomer Tayar 7835d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7845d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7855d24bcf1STomer Tayar 7865d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7875d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7885d24bcf1STomer Tayar 7895d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7905d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7915d24bcf1STomer Tayar 7925d24bcf1STomer Tayar return config_bitmap; 7935d24bcf1STomer Tayar } 7945d24bcf1STomer Tayar 7955d24bcf1STomer Tayar struct qed_load_req_in_params { 7965d24bcf1STomer Tayar u8 hsi_ver; 7975d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7985d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7995d24bcf1STomer Tayar u32 drv_ver_0; 8005d24bcf1STomer Tayar u32 drv_ver_1; 8015d24bcf1STomer Tayar u32 fw_ver; 8025d24bcf1STomer Tayar u8 drv_role; 8035d24bcf1STomer Tayar u8 timeout_val; 8045d24bcf1STomer Tayar u8 force_cmd; 8055d24bcf1STomer Tayar bool avoid_eng_reset; 8065d24bcf1STomer Tayar }; 8075d24bcf1STomer Tayar 8085d24bcf1STomer Tayar struct qed_load_req_out_params { 8095d24bcf1STomer Tayar u32 load_code; 8105d24bcf1STomer Tayar u32 exist_drv_ver_0; 8115d24bcf1STomer Tayar u32 exist_drv_ver_1; 8125d24bcf1STomer Tayar u32 exist_fw_ver; 8135d24bcf1STomer Tayar u8 exist_drv_role; 8145d24bcf1STomer Tayar u8 mfw_hsi_ver; 8155d24bcf1STomer Tayar bool drv_exists; 8165d24bcf1STomer Tayar }; 8175d24bcf1STomer Tayar 8185d24bcf1STomer Tayar static int 8195d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8205d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8215d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8225d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8235d24bcf1STomer Tayar { 8245d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8255d24bcf1STomer Tayar struct load_req_stc load_req; 8265d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8275d24bcf1STomer Tayar u32 hsi_ver; 8285d24bcf1STomer Tayar int rc; 8295d24bcf1STomer Tayar 8305d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8315d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8325d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8335d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8345d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8355d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8365d24bcf1STomer Tayar p_in_params->timeout_val); 8375d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8385d24bcf1STomer Tayar p_in_params->force_cmd); 8395d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8405d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8415d24bcf1STomer Tayar 8425d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8435d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8445d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8455d24bcf1STomer Tayar 8465d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8475d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8485d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8495d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8505d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8515d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8525d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 853b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8545d24bcf1STomer Tayar 8555d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8565d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8575d24bcf1STomer Tayar mb_params.param, 8585d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8595d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8605d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8615d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8625d24bcf1STomer Tayar 8635d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8645d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8655d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8665d24bcf1STomer Tayar load_req.drv_ver_0, 8675d24bcf1STomer Tayar load_req.drv_ver_1, 8685d24bcf1STomer Tayar load_req.fw_ver, 8695d24bcf1STomer Tayar load_req.misc0, 8705d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8715d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8725d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8735d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8745d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8755d24bcf1STomer Tayar } 8765d24bcf1STomer Tayar 8775d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8785d24bcf1STomer Tayar if (rc) { 8795d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8805d24bcf1STomer Tayar return rc; 8815d24bcf1STomer Tayar } 8825d24bcf1STomer Tayar 8835d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8845d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8855d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8865d24bcf1STomer Tayar 8875d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8885d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8895d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8905d24bcf1STomer Tayar QED_MSG_SP, 8915d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8925d24bcf1STomer Tayar load_rsp.drv_ver_0, 8935d24bcf1STomer Tayar load_rsp.drv_ver_1, 8945d24bcf1STomer Tayar load_rsp.fw_ver, 8955d24bcf1STomer Tayar load_rsp.misc0, 8965d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8975d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8985d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8995d24bcf1STomer Tayar 9005d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 9015d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 9025d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 9035d24bcf1STomer Tayar p_out_params->exist_drv_role = 9045d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 9055d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 9065d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 9075d24bcf1STomer Tayar p_out_params->drv_exists = 9085d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 9095d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 9105d24bcf1STomer Tayar } 9115d24bcf1STomer Tayar 9125d24bcf1STomer Tayar return 0; 9135d24bcf1STomer Tayar } 9145d24bcf1STomer Tayar 9155d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 9165d24bcf1STomer Tayar enum qed_drv_role drv_role, 9175d24bcf1STomer Tayar u8 *p_mfw_drv_role) 9185d24bcf1STomer Tayar { 9195d24bcf1STomer Tayar switch (drv_role) { 9205d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 9215d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9225d24bcf1STomer Tayar break; 9235d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9245d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9255d24bcf1STomer Tayar break; 9265d24bcf1STomer Tayar default: 9275d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9285d24bcf1STomer Tayar return -EINVAL; 9295d24bcf1STomer Tayar } 9305d24bcf1STomer Tayar 9315d24bcf1STomer Tayar return 0; 9325d24bcf1STomer Tayar } 9335d24bcf1STomer Tayar 9345d24bcf1STomer Tayar enum qed_load_req_force { 9355d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9365d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9375d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9385d24bcf1STomer Tayar }; 9395d24bcf1STomer Tayar 9405d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9415d24bcf1STomer Tayar 9425d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9435d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9445d24bcf1STomer Tayar { 9455d24bcf1STomer Tayar switch (force_cmd) { 9465d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9475d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9485d24bcf1STomer Tayar break; 9495d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9505d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9515d24bcf1STomer Tayar break; 9525d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9535d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9545d24bcf1STomer Tayar break; 9555d24bcf1STomer Tayar } 9565d24bcf1STomer Tayar } 9575d24bcf1STomer Tayar 9585d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9595d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9605d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9615d24bcf1STomer Tayar { 9625d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9635d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9645d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9655d24bcf1STomer Tayar int rc; 9665d24bcf1STomer Tayar 9675d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9685d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9695d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 9705d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9715d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9725d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9735d24bcf1STomer Tayar if (rc) 9745d24bcf1STomer Tayar return rc; 9755d24bcf1STomer Tayar 9765d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9775d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9785d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9795d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9805d24bcf1STomer Tayar 9815d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9825d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9835d24bcf1STomer Tayar 9845d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9855d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9865d24bcf1STomer Tayar if (rc) 9875d24bcf1STomer Tayar return rc; 9885d24bcf1STomer Tayar 9895d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9905d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9915d24bcf1STomer Tayar * - MFW responds that a force load request is required 992fe56b9e6SYuval Mintz */ 9935d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9945d24bcf1STomer Tayar DP_INFO(p_hwfn, 9955d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9965d24bcf1STomer Tayar 9975d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9985d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9995d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 10005d24bcf1STomer Tayar if (rc) 10015d24bcf1STomer Tayar return rc; 10025d24bcf1STomer Tayar } else if (out_params.load_code == 10035d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 10045d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 10055d24bcf1STomer Tayar out_params.exist_drv_role, 10065d24bcf1STomer Tayar p_params->override_force_load)) { 10075d24bcf1STomer Tayar DP_INFO(p_hwfn, 10085d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 10095d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10105d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10115d24bcf1STomer Tayar out_params.exist_drv_role, 10125d24bcf1STomer Tayar out_params.exist_fw_ver, 10135d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10145d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10155d24bcf1STomer Tayar 10165d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 10175d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 10185d24bcf1STomer Tayar &mfw_force_cmd); 10195d24bcf1STomer Tayar 10205d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 10215d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10225d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10235d24bcf1STomer Tayar &out_params); 10245d24bcf1STomer Tayar if (rc) 10255d24bcf1STomer Tayar return rc; 10265d24bcf1STomer Tayar } else { 10275d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10285d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10295d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10305d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10315d24bcf1STomer Tayar out_params.exist_drv_role, 10325d24bcf1STomer Tayar out_params.exist_fw_ver, 10335d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10345d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10355d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10365d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10375d24bcf1STomer Tayar 10385d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1039fe56b9e6SYuval Mintz return -EBUSY; 1040fe56b9e6SYuval Mintz } 10415d24bcf1STomer Tayar } 10425d24bcf1STomer Tayar 10435d24bcf1STomer Tayar /* Now handle the other types of responses. 10445d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10455d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10465d24bcf1STomer Tayar */ 10475d24bcf1STomer Tayar switch (out_params.load_code) { 10485d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10495d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10505d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10515d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10525d24bcf1STomer Tayar out_params.drv_exists) { 10535d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10545d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10555d24bcf1STomer Tayar */ 10565d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10575d24bcf1STomer Tayar "PF is already loaded\n"); 10585d24bcf1STomer Tayar return -EINVAL; 10595d24bcf1STomer Tayar } 10605d24bcf1STomer Tayar break; 10615d24bcf1STomer Tayar default: 10625d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10635d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10645d24bcf1STomer Tayar out_params.load_code); 10655d24bcf1STomer Tayar return -EBUSY; 10665d24bcf1STomer Tayar } 10675d24bcf1STomer Tayar 10685d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1069fe56b9e6SYuval Mintz 1070fe56b9e6SYuval Mintz return 0; 1071fe56b9e6SYuval Mintz } 1072fe56b9e6SYuval Mintz 1073666db486STomer Tayar int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1074666db486STomer Tayar { 1075666db486STomer Tayar u32 resp = 0, param = 0; 1076666db486STomer Tayar int rc; 1077666db486STomer Tayar 1078666db486STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp, 1079666db486STomer Tayar ¶m); 1080666db486STomer Tayar if (rc) { 1081666db486STomer Tayar DP_NOTICE(p_hwfn, 1082666db486STomer Tayar "Failed to send a LOAD_DONE command, rc = %d\n", rc); 1083666db486STomer Tayar return rc; 1084666db486STomer Tayar } 1085666db486STomer Tayar 1086666db486STomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1087666db486STomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1088666db486STomer Tayar DP_NOTICE(p_hwfn, 1089666db486STomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1090666db486STomer Tayar 1091666db486STomer Tayar return 0; 1092666db486STomer Tayar } 1093666db486STomer Tayar 10941226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10951226337aSTomer Tayar { 1096eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1097eaa50fc5STomer Tayar u32 wol_param; 10981226337aSTomer Tayar 10991226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 11001226337aSTomer Tayar case QED_OV_WOL_DISABLED: 11011226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 11021226337aSTomer Tayar break; 11031226337aSTomer Tayar case QED_OV_WOL_ENABLED: 11041226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 11051226337aSTomer Tayar break; 11061226337aSTomer Tayar default: 11071226337aSTomer Tayar DP_NOTICE(p_hwfn, 11081226337aSTomer Tayar "Unknown WoL configuration %02x\n", 11091226337aSTomer Tayar p_hwfn->cdev->wol_config); 11101226337aSTomer Tayar /* Fallthrough */ 11111226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 11121226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 11131226337aSTomer Tayar } 11141226337aSTomer Tayar 1115eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1116eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1117eaa50fc5STomer Tayar mb_params.param = wol_param; 1118b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1119eaa50fc5STomer Tayar 1120eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11211226337aSTomer Tayar } 11221226337aSTomer Tayar 11231226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11241226337aSTomer Tayar { 11251226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11261226337aSTomer Tayar struct mcp_mac wol_mac; 11271226337aSTomer Tayar 11281226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11291226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11301226337aSTomer Tayar 11311226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11321226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11331226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11341226337aSTomer Tayar 11351226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11361226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11371226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11381226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11391226337aSTomer Tayar 11401226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11411226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11421226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11431226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11441226337aSTomer Tayar 11451226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11461226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11471226337aSTomer Tayar } 11481226337aSTomer Tayar 11491226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11501226337aSTomer Tayar } 11511226337aSTomer Tayar 11520b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11530b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11540b55e27dSYuval Mintz { 11550b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11560b55e27dSYuval Mintz PUBLIC_PATH); 11570b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11580b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11590b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11600b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11610b55e27dSYuval Mintz int i; 11620b55e27dSYuval Mintz 11630b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11640b55e27dSYuval Mintz QED_MSG_SP, 11650b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11660b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11670b55e27dSYuval Mintz 11680b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11690b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11700b55e27dSYuval Mintz path_addr + 11710b55e27dSYuval Mintz offsetof(struct public_path, 11720b55e27dSYuval Mintz mcp_vf_disabled) + 11730b55e27dSYuval Mintz sizeof(u32) * i); 11740b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11750b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11760b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11770b55e27dSYuval Mintz } 11780b55e27dSYuval Mintz 11790b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11800b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11810b55e27dSYuval Mintz } 11820b55e27dSYuval Mintz 11830b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11840b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11850b55e27dSYuval Mintz { 11860b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11870b55e27dSYuval Mintz PUBLIC_FUNC); 11880b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11890b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11900b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11910b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11920b55e27dSYuval Mintz int rc; 11930b55e27dSYuval Mintz int i; 11940b55e27dSYuval Mintz 11950b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11960b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11970b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 11980b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 11990b55e27dSYuval Mintz 12000b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 12010b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 12022f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 12032f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 12040b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 12050b55e27dSYuval Mintz if (rc) { 12060b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 12070b55e27dSYuval Mintz return -EBUSY; 12080b55e27dSYuval Mintz } 12090b55e27dSYuval Mintz 12100b55e27dSYuval Mintz /* Clear the ACK bits */ 12110b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 12120b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 12130b55e27dSYuval Mintz func_addr + 12140b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 12150b55e27dSYuval Mintz i * sizeof(u32), 0); 12160b55e27dSYuval Mintz 12170b55e27dSYuval Mintz return rc; 12180b55e27dSYuval Mintz } 12190b55e27dSYuval Mintz 1220334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1221334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1222334c03b5SZvi Nachmani { 1223334c03b5SZvi Nachmani u32 transceiver_state; 1224334c03b5SZvi Nachmani 1225334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1226334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1227334c03b5SZvi Nachmani offsetof(struct public_port, 1228334c03b5SZvi Nachmani transceiver_data)); 1229334c03b5SZvi Nachmani 1230334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1231334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1232334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1233334c03b5SZvi Nachmani transceiver_state, 1234334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12351a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1236334c03b5SZvi Nachmani 1237334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1238351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1239334c03b5SZvi Nachmani 1240351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1241334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1242334c03b5SZvi Nachmani else 1243334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1244334c03b5SZvi Nachmani } 1245334c03b5SZvi Nachmani 1246645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1247645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1248645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1249645874e5SSudarsana Reddy Kalluru { 1250645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1251645874e5SSudarsana Reddy Kalluru 1252645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1253645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1254645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1255645874e5SSudarsana Reddy Kalluru p_ptt, 1256645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1257645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1258645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1259645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1260645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1261645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1262645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1263645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1264645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1265645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1266645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1267645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1268645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1269645874e5SSudarsana Reddy Kalluru } 1270645874e5SSudarsana Reddy Kalluru 1271e40a826aSSudarsana Reddy Kalluru static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1272e40a826aSSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1273e40a826aSSudarsana Reddy Kalluru struct public_func *p_data, int pfid) 1274e40a826aSSudarsana Reddy Kalluru { 1275e40a826aSSudarsana Reddy Kalluru u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1276e40a826aSSudarsana Reddy Kalluru PUBLIC_FUNC); 1277e40a826aSSudarsana Reddy Kalluru u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1278e40a826aSSudarsana Reddy Kalluru u32 func_addr; 1279e40a826aSSudarsana Reddy Kalluru u32 i, size; 1280e40a826aSSudarsana Reddy Kalluru 1281e40a826aSSudarsana Reddy Kalluru func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1282e40a826aSSudarsana Reddy Kalluru memset(p_data, 0, sizeof(*p_data)); 1283e40a826aSSudarsana Reddy Kalluru 1284e40a826aSSudarsana Reddy Kalluru size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1285e40a826aSSudarsana Reddy Kalluru for (i = 0; i < size / sizeof(u32); i++) 1286e40a826aSSudarsana Reddy Kalluru ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1287e40a826aSSudarsana Reddy Kalluru func_addr + (i << 2)); 1288e40a826aSSudarsana Reddy Kalluru return size; 1289e40a826aSSudarsana Reddy Kalluru } 1290e40a826aSSudarsana Reddy Kalluru 1291e40a826aSSudarsana Reddy Kalluru static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1292e40a826aSSudarsana Reddy Kalluru struct public_func *p_shmem_info) 1293e40a826aSSudarsana Reddy Kalluru { 1294e40a826aSSudarsana Reddy Kalluru struct qed_mcp_function_info *p_info; 1295e40a826aSSudarsana Reddy Kalluru 1296e40a826aSSudarsana Reddy Kalluru p_info = &p_hwfn->mcp_info->func_info; 1297e40a826aSSudarsana Reddy Kalluru 1298e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1299e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MIN_BW); 1300e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1301e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1302e40a826aSSudarsana Reddy Kalluru "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1303e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min); 1304e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = 1; 1305e40a826aSSudarsana Reddy Kalluru } 1306e40a826aSSudarsana Reddy Kalluru 1307e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1308e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MAX_BW); 1309e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1310e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1311e40a826aSSudarsana Reddy Kalluru "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1312e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max); 1313e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = 100; 1314e40a826aSSudarsana Reddy Kalluru } 1315e40a826aSSudarsana Reddy Kalluru } 1316e40a826aSSudarsana Reddy Kalluru 1317cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 13181a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1319cc875c2eSYuval Mintz { 1320cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1321a64b02d5SManish Chopra u8 max_bw, min_bw; 1322cc875c2eSYuval Mintz u32 status = 0; 1323cc875c2eSYuval Mintz 132465ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 132565ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 132665ed2ffdSMintz, Yuval 1327cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1328cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1329cc875c2eSYuval Mintz if (!b_reset) { 1330cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1331cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1332cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1333cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1334cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1335cc875c2eSYuval Mintz status, 1336cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 13371a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1338cc875c2eSYuval Mintz } else { 1339cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1340cc875c2eSYuval Mintz "Resetting link indications\n"); 134165ed2ffdSMintz, Yuval goto out; 1342cc875c2eSYuval Mintz } 1343cc875c2eSYuval Mintz 1344e40a826aSSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) { 1345e40a826aSSudarsana Reddy Kalluru /* Link indication with modern MFW arrives as per-PF 1346e40a826aSSudarsana Reddy Kalluru * indication. 1347e40a826aSSudarsana Reddy Kalluru */ 1348e40a826aSSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & 1349e40a826aSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1350e40a826aSSudarsana Reddy Kalluru struct public_func shmem_info; 1351e40a826aSSudarsana Reddy Kalluru 1352e40a826aSSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1353e40a826aSSudarsana Reddy Kalluru MCP_PF_ID(p_hwfn)); 1354e40a826aSSudarsana Reddy Kalluru p_link->link_up = !!(shmem_info.status & 1355e40a826aSSudarsana Reddy Kalluru FUNC_STATUS_VIRTUAL_LINK_UP); 1356e40a826aSSudarsana Reddy Kalluru qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1357e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1358e40a826aSSudarsana Reddy Kalluru "Virtual link_up = %d\n", p_link->link_up); 1359e40a826aSSudarsana Reddy Kalluru } else { 1360cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1361e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1362e40a826aSSudarsana Reddy Kalluru "Physical link_up = %d\n", p_link->link_up); 1363e40a826aSSudarsana Reddy Kalluru } 1364e40a826aSSudarsana Reddy Kalluru } else { 1365fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1366e40a826aSSudarsana Reddy Kalluru } 1367cc875c2eSYuval Mintz 1368cc875c2eSYuval Mintz p_link->full_duplex = true; 1369cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1370cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1371cc875c2eSYuval Mintz p_link->speed = 100000; 1372cc875c2eSYuval Mintz break; 1373cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1374cc875c2eSYuval Mintz p_link->speed = 50000; 1375cc875c2eSYuval Mintz break; 1376cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1377cc875c2eSYuval Mintz p_link->speed = 40000; 1378cc875c2eSYuval Mintz break; 1379cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1380cc875c2eSYuval Mintz p_link->speed = 25000; 1381cc875c2eSYuval Mintz break; 1382cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1383cc875c2eSYuval Mintz p_link->speed = 20000; 1384cc875c2eSYuval Mintz break; 1385cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1386cc875c2eSYuval Mintz p_link->speed = 10000; 1387cc875c2eSYuval Mintz break; 1388cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1389cc875c2eSYuval Mintz p_link->full_duplex = false; 1390cc875c2eSYuval Mintz /* Fall-through */ 1391cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1392cc875c2eSYuval Mintz p_link->speed = 1000; 1393cc875c2eSYuval Mintz break; 1394cc875c2eSYuval Mintz default: 1395cc875c2eSYuval Mintz p_link->speed = 0; 139658874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1397cc875c2eSYuval Mintz } 1398cc875c2eSYuval Mintz 13994b01e519SManish Chopra if (p_link->link_up && p_link->speed) 14004b01e519SManish Chopra p_link->line_speed = p_link->speed; 14014b01e519SManish Chopra else 14024b01e519SManish Chopra p_link->line_speed = 0; 14034b01e519SManish Chopra 14044b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1405a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 14064b01e519SManish Chopra 1407a64b02d5SManish Chopra /* Max bandwidth configuration */ 14084b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1409cc875c2eSYuval Mintz 1410a64b02d5SManish Chopra /* Min bandwidth configuration */ 1411a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 14126f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 14136f437d43SMintz, Yuval p_link->min_pf_rate); 1414a64b02d5SManish Chopra 1415cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1416cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1417cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1418cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1419cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1420cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1421cc875c2eSYuval Mintz 1422cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1423cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1424cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1425cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1426cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1427cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1428cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1429cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1430cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1431cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1432cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1433cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1434cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1435054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1436054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1437054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1438cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1439cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1440cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1441cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1442cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1443cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1444cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1445cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1446cc875c2eSYuval Mintz 1447cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1448cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1449cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1450cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1451cc875c2eSYuval Mintz 1452cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1453cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1454cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1455cc875c2eSYuval Mintz break; 1456cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1457cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1458cc875c2eSYuval Mintz break; 1459cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1460cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1461cc875c2eSYuval Mintz break; 1462cc875c2eSYuval Mintz default: 1463cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1464cc875c2eSYuval Mintz } 1465cc875c2eSYuval Mintz 1466cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1467cc875c2eSYuval Mintz 1468645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1469645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1470645874e5SSudarsana Reddy Kalluru 1471706d0891SRahul Verma qed_link_update(p_hwfn, p_ptt); 147265ed2ffdSMintz, Yuval out: 147365ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1474cc875c2eSYuval Mintz } 1475cc875c2eSYuval Mintz 1476351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1477cc875c2eSYuval Mintz { 1478cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 14795529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 14802f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1481cc875c2eSYuval Mintz int rc = 0; 14825529bad9STomer Tayar u32 cmd; 1483cc875c2eSYuval Mintz 1484cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 14852f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1486cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1487cc875c2eSYuval Mintz if (!params->speed.autoneg) 14882f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 14892f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 14902f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 14912f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 14922f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 14932f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 14944ad95a93SSudarsana Reddy Kalluru 14954ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 14964ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 14974ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 14984ad95a93SSudarsana Reddy Kalluru * still work. 14994ad95a93SSudarsana Reddy Kalluru */ 15004ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 15014ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1502645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1503645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1504645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1505645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1506645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1507645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1508645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1509645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1510645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1511645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1512645874e5SSudarsana Reddy Kalluru } 1513cc875c2eSYuval Mintz 1514fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1515fc916ff2SSudarsana Reddy Kalluru 1516cc875c2eSYuval Mintz if (b_up) { 1517cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1518cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 15192f67af8cSTomer Tayar phy_cfg.speed, 15202f67af8cSTomer Tayar phy_cfg.pause, 15212f67af8cSTomer Tayar phy_cfg.adv_speed, 15222f67af8cSTomer Tayar phy_cfg.loopback_mode, 15232f67af8cSTomer Tayar phy_cfg.feature_config_flags); 1524cc875c2eSYuval Mintz } else { 1525cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1526cc875c2eSYuval Mintz "Resetting link\n"); 1527cc875c2eSYuval Mintz } 1528cc875c2eSYuval Mintz 15295529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 15305529bad9STomer Tayar mb_params.cmd = cmd; 15312f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 15322f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 15335529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1534cc875c2eSYuval Mintz 1535cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1536cc875c2eSYuval Mintz if (rc) { 1537cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1538cc875c2eSYuval Mintz return rc; 1539cc875c2eSYuval Mintz } 1540cc875c2eSYuval Mintz 154165ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 154265ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 154365ed2ffdSMintz, Yuval * an attention. 154465ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 154565ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 154665ed2ffdSMintz, Yuval */ 154765ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1548cc875c2eSYuval Mintz 1549cc875c2eSYuval Mintz return 0; 1550cc875c2eSYuval Mintz } 1551cc875c2eSYuval Mintz 15526c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 15536c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 15546c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 15556c754246SSudarsana Reddy Kalluru { 15566c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 15576c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 15586c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 15596c754246SSudarsana Reddy Kalluru u32 hsi_param; 15606c754246SSudarsana Reddy Kalluru 15616c754246SSudarsana Reddy Kalluru switch (type) { 15626c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 15636c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 15646c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 15656c754246SSudarsana Reddy Kalluru break; 15666c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 15676c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 15686c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 15696c754246SSudarsana Reddy Kalluru break; 15706c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 15716c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 15726c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 15736c754246SSudarsana Reddy Kalluru break; 15746c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 15756c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 15766c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 15776c754246SSudarsana Reddy Kalluru break; 15786c754246SSudarsana Reddy Kalluru default: 15796c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 15806c754246SSudarsana Reddy Kalluru return; 15816c754246SSudarsana Reddy Kalluru } 15826c754246SSudarsana Reddy Kalluru 15836c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 15846c754246SSudarsana Reddy Kalluru 15856c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 15866c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 15876c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 15882f67af8cSTomer Tayar mb_params.p_data_src = &stats; 15892f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 15906c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 15916c754246SSudarsana Reddy Kalluru } 15926c754246SSudarsana Reddy Kalluru 15931a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15944b01e519SManish Chopra { 15954b01e519SManish Chopra struct qed_mcp_function_info *p_info; 15964b01e519SManish Chopra struct public_func shmem_info; 15974b01e519SManish Chopra u32 resp = 0, param = 0; 15984b01e519SManish Chopra 15991a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 16004b01e519SManish Chopra 16014b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 16024b01e519SManish Chopra 16034b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 16044b01e519SManish Chopra 1605a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 16064b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 16074b01e519SManish Chopra 16084b01e519SManish Chopra /* Acknowledge the MFW */ 16094b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 16104b01e519SManish Chopra ¶m); 16114b01e519SManish Chopra } 16124b01e519SManish Chopra 16132a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 16142a351fd9SMintz, Yuval { 16152a351fd9SMintz, Yuval struct public_func shmem_info; 16162a351fd9SMintz, Yuval u32 resp = 0, param = 0; 16172a351fd9SMintz, Yuval 16182a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 16192a351fd9SMintz, Yuval 16202a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 16212a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 16222a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 16237e3e375cSSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 16247e3e375cSSudarsana Reddy Kalluru if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 16257e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 16267e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16277e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 16287e3e375cSSudarsana Reddy Kalluru 16297e3e375cSSudarsana Reddy Kalluru /* Configure DB to add external vlan to EDPM packets */ 16307e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 16317e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 16327e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16337e3e375cSSudarsana Reddy Kalluru } else { 16347e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 16357e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 16367e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 16377e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 16387e3e375cSSudarsana Reddy Kalluru } 16397e3e375cSSudarsana Reddy Kalluru 16402a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 16412a351fd9SMintz, Yuval } 16422a351fd9SMintz, Yuval 16437e3e375cSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 16447e3e375cSSudarsana Reddy Kalluru p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 16457e3e375cSSudarsana Reddy Kalluru 16462a351fd9SMintz, Yuval /* Acknowledge the MFW */ 16472a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 16482a351fd9SMintz, Yuval &resp, ¶m); 16492a351fd9SMintz, Yuval } 16502a351fd9SMintz, Yuval 1651cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1652cac6f691SSudarsana Reddy Kalluru { 1653cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1654cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1655cac6f691SSudarsana Reddy Kalluru 1656cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1657cac6f691SSudarsana Reddy Kalluru return; 1658cac6f691SSudarsana Reddy Kalluru 1659cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1660cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1661cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1662cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1663cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1664cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1665ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1666ec036eb9SSudarsana Reddy Kalluru "Incorrect UFP Channel type %d port_id 0x%02x\n", 1667ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1668cac6f691SSudarsana Reddy Kalluru 1669cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1670cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1671cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1672cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1673cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1674cac6f691SSudarsana Reddy Kalluru } else { 1675cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1676ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1677ec036eb9SSudarsana Reddy Kalluru "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1678ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1679cac6f691SSudarsana Reddy Kalluru } 1680cac6f691SSudarsana Reddy Kalluru 1681cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1682b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1683b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1684cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1685b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1686cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1687cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1688cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1689cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1690cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1691cac6f691SSudarsana Reddy Kalluru } else { 1692cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1693ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1694ec036eb9SSudarsana Reddy Kalluru "Unknown Host priority control %d port_id 0x%02x\n", 1695ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1696cac6f691SSudarsana Reddy Kalluru } 1697cac6f691SSudarsana Reddy Kalluru 1698cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1699ec036eb9SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1700ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1701ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1702cac6f691SSudarsana Reddy Kalluru } 1703cac6f691SSudarsana Reddy Kalluru 1704cac6f691SSudarsana Reddy Kalluru static int 1705cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1706cac6f691SSudarsana Reddy Kalluru { 1707cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1708cac6f691SSudarsana Reddy Kalluru 1709cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1710cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1711c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1712c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1713cac6f691SSudarsana Reddy Kalluru 1714cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1715cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1716cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1717cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1718cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1719cac6f691SSudarsana Reddy Kalluru } else { 1720cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1721cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1722cac6f691SSudarsana Reddy Kalluru } 1723cac6f691SSudarsana Reddy Kalluru 1724cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1725cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1726cac6f691SSudarsana Reddy Kalluru 1727cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1728cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1729cac6f691SSudarsana Reddy Kalluru 1730cac6f691SSudarsana Reddy Kalluru return 0; 1731cac6f691SSudarsana Reddy Kalluru } 1732cac6f691SSudarsana Reddy Kalluru 1733cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1734cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1735cc875c2eSYuval Mintz { 1736cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1737cc875c2eSYuval Mintz int rc = 0; 1738cc875c2eSYuval Mintz bool found = false; 1739cc875c2eSYuval Mintz u16 i; 1740cc875c2eSYuval Mintz 1741cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1742cc875c2eSYuval Mintz 1743cc875c2eSYuval Mintz /* Read Messages from MFW */ 1744cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1745cc875c2eSYuval Mintz 1746cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1747cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1748cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1749cc875c2eSYuval Mintz continue; 1750cc875c2eSYuval Mintz 1751cc875c2eSYuval Mintz found = true; 1752cc875c2eSYuval Mintz 1753cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1754cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1755cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1756cc875c2eSYuval Mintz 1757cc875c2eSYuval Mintz switch (i) { 1758cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1759cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1760cc875c2eSYuval Mintz break; 17610b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 17620b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 17630b55e27dSYuval Mintz break; 176439651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 176539651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 176639651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 176739651abdSSudarsana Reddy Kalluru break; 176839651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 176939651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 177039651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 177139651abdSSudarsana Reddy Kalluru break; 177239651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 177339651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 177439651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 177539651abdSSudarsana Reddy Kalluru break; 1776cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 1777cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1778cac6f691SSudarsana Reddy Kalluru break; 1779334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1780334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1781334c03b5SZvi Nachmani break; 17826c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 17836c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 17846c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 17856c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 17866c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 17876c754246SSudarsana Reddy Kalluru break; 17884b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 17894b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 17904b01e519SManish Chopra break; 17912a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 17922a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 17932a351fd9SMintz, Yuval break; 179459ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 179559ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 17962a351fd9SMintz, Yuval break; 1797cc875c2eSYuval Mintz default: 179839815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1799cc875c2eSYuval Mintz rc = -EINVAL; 1800cc875c2eSYuval Mintz } 1801cc875c2eSYuval Mintz } 1802cc875c2eSYuval Mintz 1803cc875c2eSYuval Mintz /* ACK everything */ 1804cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1805cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1806cc875c2eSYuval Mintz 1807cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1808cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1809cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1810cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1811cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1812cc875c2eSYuval Mintz (__force u32)val); 1813cc875c2eSYuval Mintz } 1814cc875c2eSYuval Mintz 1815cc875c2eSYuval Mintz if (!found) { 1816cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1817cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1818cc875c2eSYuval Mintz rc = -EINVAL; 1819cc875c2eSYuval Mintz } 1820cc875c2eSYuval Mintz 1821cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1822cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1823cc875c2eSYuval Mintz 1824cc875c2eSYuval Mintz return rc; 1825cc875c2eSYuval Mintz } 1826cc875c2eSYuval Mintz 18271408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 18281408cc1fSYuval Mintz struct qed_ptt *p_ptt, 18291408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1830fe56b9e6SYuval Mintz { 1831fe56b9e6SYuval Mintz u32 global_offsize; 1832fe56b9e6SYuval Mintz 18331408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 18341408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 18351408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 18361408cc1fSYuval Mintz 18371408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 18381408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 18391408cc1fSYuval Mintz return 0; 18401408cc1fSYuval Mintz } else { 18411408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 18421408cc1fSYuval Mintz QED_MSG_IOV, 18431408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 18441408cc1fSYuval Mintz return -EINVAL; 18451408cc1fSYuval Mintz } 18461408cc1fSYuval Mintz } 1847fe56b9e6SYuval Mintz 1848fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 18491408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 18501408cc1fSYuval Mintz mcp_info->public_base, 1851fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 18521408cc1fSYuval Mintz *p_mfw_ver = 18531408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 18541408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 18551408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1856fe56b9e6SYuval Mintz 18571408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 18581408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 18591408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 18601408cc1fSYuval Mintz offsetof(struct public_global, 18611408cc1fSYuval Mintz running_bundle_id)); 18621408cc1fSYuval Mintz } 1863fe56b9e6SYuval Mintz 1864fe56b9e6SYuval Mintz return 0; 1865fe56b9e6SYuval Mintz } 1866fe56b9e6SYuval Mintz 1867ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1868ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1869ae33666aSTomer Tayar { 1870ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1871ae33666aSTomer Tayar 1872ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 1873ae33666aSTomer Tayar return -EINVAL; 1874ae33666aSTomer Tayar 1875ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 1876ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1877ae33666aSTomer Tayar if (!nvm_cfg_addr) { 1878ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1879ae33666aSTomer Tayar return -EINVAL; 1880ae33666aSTomer Tayar } 1881ae33666aSTomer Tayar 1882ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 1883ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1884ae33666aSTomer Tayar 1885ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1886ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 1887ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 1888ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1889ae33666aSTomer Tayar mbi_ver_addr) & 1890ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1891ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1892ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1893ae33666aSTomer Tayar 1894ae33666aSTomer Tayar return 0; 1895ae33666aSTomer Tayar } 1896ae33666aSTomer Tayar 1897706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 1898706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *p_media_type) 1899cc875c2eSYuval Mintz { 1900c56a8be7SRahul Verma *p_media_type = MEDIA_UNSPECIFIED; 1901c56a8be7SRahul Verma 1902706d0891SRahul Verma if (IS_VF(p_hwfn->cdev)) 19031408cc1fSYuval Mintz return -EINVAL; 19041408cc1fSYuval Mintz 1905cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1906cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1907cc875c2eSYuval Mintz return -EBUSY; 1908cc875c2eSYuval Mintz } 1909cc875c2eSYuval Mintz 1910706d0891SRahul Verma if (!p_ptt) { 1911cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1912706d0891SRahul Verma return -EINVAL; 1913706d0891SRahul Verma } 1914cc875c2eSYuval Mintz 1915706d0891SRahul Verma *p_media_type = qed_rd(p_hwfn, p_ptt, 1916706d0891SRahul Verma p_hwfn->mcp_info->port_addr + 1917706d0891SRahul Verma offsetof(struct public_port, 1918706d0891SRahul Verma media_type)); 1919cc875c2eSYuval Mintz 1920cc875c2eSYuval Mintz return 0; 1921cc875c2eSYuval Mintz } 1922cc875c2eSYuval Mintz 1923c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 1924c56a8be7SRahul Verma struct qed_ptt *p_ptt, 1925c56a8be7SRahul Verma u32 *p_transceiver_state, 1926c56a8be7SRahul Verma u32 *p_transceiver_type) 1927c56a8be7SRahul Verma { 1928c56a8be7SRahul Verma u32 transceiver_info; 1929c56a8be7SRahul Verma 193068203a67SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 193168203a67SRahul Verma *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 193268203a67SRahul Verma 1933c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 1934c56a8be7SRahul Verma return -EINVAL; 1935c56a8be7SRahul Verma 1936c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 1937c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1938c56a8be7SRahul Verma return -EBUSY; 1939c56a8be7SRahul Verma } 1940c56a8be7SRahul Verma 1941c56a8be7SRahul Verma transceiver_info = qed_rd(p_hwfn, p_ptt, 1942c56a8be7SRahul Verma p_hwfn->mcp_info->port_addr + 1943c56a8be7SRahul Verma offsetof(struct public_port, 1944c56a8be7SRahul Verma transceiver_data)); 1945c56a8be7SRahul Verma 1946c56a8be7SRahul Verma *p_transceiver_state = (transceiver_info & 1947c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_MASK) >> 1948c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_OFFSET; 1949c56a8be7SRahul Verma 1950c56a8be7SRahul Verma if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1951c56a8be7SRahul Verma *p_transceiver_type = (transceiver_info & 1952c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_MASK) >> 1953c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_OFFSET; 1954c56a8be7SRahul Verma else 1955c56a8be7SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 1956c56a8be7SRahul Verma 1957c56a8be7SRahul Verma return 0; 1958c56a8be7SRahul Verma } 1959c56a8be7SRahul Verma static bool qed_is_transceiver_ready(u32 transceiver_state, 1960c56a8be7SRahul Verma u32 transceiver_type) 1961c56a8be7SRahul Verma { 1962c56a8be7SRahul Verma if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 1963c56a8be7SRahul Verma ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 1964c56a8be7SRahul Verma (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 1965c56a8be7SRahul Verma return true; 1966c56a8be7SRahul Verma 1967c56a8be7SRahul Verma return false; 1968c56a8be7SRahul Verma } 1969c56a8be7SRahul Verma 1970c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 1971c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask) 1972c56a8be7SRahul Verma { 1973c56a8be7SRahul Verma u32 transceiver_type, transceiver_state; 197492619210SArnd Bergmann int ret; 1975c56a8be7SRahul Verma 197692619210SArnd Bergmann ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 1977c56a8be7SRahul Verma &transceiver_type); 197892619210SArnd Bergmann if (ret) 197992619210SArnd Bergmann return ret; 1980c56a8be7SRahul Verma 1981c56a8be7SRahul Verma if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 1982c56a8be7SRahul Verma false) 1983c56a8be7SRahul Verma return -EINVAL; 1984c56a8be7SRahul Verma 1985c56a8be7SRahul Verma switch (transceiver_type) { 1986c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_LX: 1987c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_SX: 1988c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_PCC: 1989c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_ACC: 1990c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1000BASET: 1991c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1992c56a8be7SRahul Verma break; 1993c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_SR: 1994c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LR: 1995c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LRM: 1996c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ER: 1997c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_PCC: 1998c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ACC: 1999c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x10G: 2000c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2001c56a8be7SRahul Verma break; 2002c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_LR4: 2003c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_SR4: 2004c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2005c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2006c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2007c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2008c56a8be7SRahul Verma break; 2009c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_AOC: 2010c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_SR4: 2011c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_LR4: 2012c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ER4: 2013c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ACC: 2014c56a8be7SRahul Verma *p_speed_mask = 2015c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2016c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2017c56a8be7SRahul Verma break; 2018c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_SR: 2019c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_LR: 2020c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_AOC: 2021c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2022c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2023c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2024c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2025c56a8be7SRahul Verma break; 2026c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2027c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2028c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2029c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2030c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2031c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2032c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2033c56a8be7SRahul Verma break; 2034c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_CR4: 2035c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2036c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2037c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2038c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2039c56a8be7SRahul Verma break; 2040c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_CR4: 2041c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2042c56a8be7SRahul Verma *p_speed_mask = 2043c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2044c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2045c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2046c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2047c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2048c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2049c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2050c56a8be7SRahul Verma break; 2051c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2052c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2053c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2054c56a8be7SRahul Verma *p_speed_mask = 2055c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2056c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2057c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2058c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2059c56a8be7SRahul Verma break; 2060c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_XLPPI: 2061c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2062c56a8be7SRahul Verma break; 2063c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_BASET: 2064c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2065c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2066c56a8be7SRahul Verma break; 2067c56a8be7SRahul Verma default: 20681107a674SColin Ian King DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2069c56a8be7SRahul Verma transceiver_type); 2070c56a8be7SRahul Verma *p_speed_mask = 0xff; 2071c56a8be7SRahul Verma break; 2072c56a8be7SRahul Verma } 2073c56a8be7SRahul Verma 2074c56a8be7SRahul Verma return 0; 2075c56a8be7SRahul Verma } 2076c56a8be7SRahul Verma 2077c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2078c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config) 2079c56a8be7SRahul Verma { 2080c56a8be7SRahul Verma u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2081c56a8be7SRahul Verma 2082c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2083c56a8be7SRahul Verma return -EINVAL; 2084c56a8be7SRahul Verma 2085c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2086c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2087c56a8be7SRahul Verma return -EBUSY; 2088c56a8be7SRahul Verma } 2089c56a8be7SRahul Verma if (!p_ptt) { 2090c56a8be7SRahul Verma *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2091c56a8be7SRahul Verma return -EINVAL; 2092c56a8be7SRahul Verma } 2093c56a8be7SRahul Verma 2094c56a8be7SRahul Verma nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2095c56a8be7SRahul Verma nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2096c56a8be7SRahul Verma port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2097c56a8be7SRahul Verma offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2098c56a8be7SRahul Verma *p_board_config = qed_rd(p_hwfn, p_ptt, 2099c56a8be7SRahul Verma port_cfg_addr + 2100c56a8be7SRahul Verma offsetof(struct nvm_cfg1_port, 2101c56a8be7SRahul Verma board_cfg)); 2102c56a8be7SRahul Verma 2103c56a8be7SRahul Verma return 0; 2104c56a8be7SRahul Verma } 2105c56a8be7SRahul Verma 21066927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 21076927e826SMintz, Yuval static void 21086927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 21096927e826SMintz, Yuval enum qed_pci_personality *p_proto) 21106927e826SMintz, Yuval { 21116927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 21126927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 21136927e826SMintz, Yuval */ 21146927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 21156927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 21166927e826SMintz, Yuval else 21176927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 21186927e826SMintz, Yuval 21196927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 21206927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 21216927e826SMintz, Yuval (u32) *p_proto); 21226927e826SMintz, Yuval } 21236927e826SMintz, Yuval 21246927e826SMintz, Yuval static int 21256927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 21266927e826SMintz, Yuval struct qed_ptt *p_ptt, 21276927e826SMintz, Yuval enum qed_pci_personality *p_proto) 21286927e826SMintz, Yuval { 21296927e826SMintz, Yuval u32 resp = 0, param = 0; 21306927e826SMintz, Yuval int rc; 21316927e826SMintz, Yuval 21326927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 21336927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 21346927e826SMintz, Yuval if (rc) 21356927e826SMintz, Yuval return rc; 21366927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 21376927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 21386927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 21396927e826SMintz, Yuval resp); 21406927e826SMintz, Yuval return -EINVAL; 21416927e826SMintz, Yuval } 21426927e826SMintz, Yuval 21436927e826SMintz, Yuval switch (param) { 21446927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 21456927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 21466927e826SMintz, Yuval break; 21476927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 21486927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 21496927e826SMintz, Yuval break; 21506927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2151e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 2152e0a8f9deSMichal Kalderon break; 2153e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2154e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 2155e0a8f9deSMichal Kalderon break; 21566927e826SMintz, Yuval default: 21576927e826SMintz, Yuval DP_NOTICE(p_hwfn, 21586927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 21596927e826SMintz, Yuval param); 21606927e826SMintz, Yuval return -EINVAL; 21616927e826SMintz, Yuval } 21626927e826SMintz, Yuval 21636927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 21646927e826SMintz, Yuval NETIF_MSG_IFUP, 21656927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 21666927e826SMintz, Yuval (u32) *p_proto, resp, param); 21676927e826SMintz, Yuval return 0; 21686927e826SMintz, Yuval } 21696927e826SMintz, Yuval 2170fe56b9e6SYuval Mintz static int 2171fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2172fe56b9e6SYuval Mintz struct public_func *p_info, 21736927e826SMintz, Yuval struct qed_ptt *p_ptt, 2174fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 2175fe56b9e6SYuval Mintz { 2176fe56b9e6SYuval Mintz int rc = 0; 2177fe56b9e6SYuval Mintz 2178fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2179fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 21801fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 21811fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 21821fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 21836927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2184fe56b9e6SYuval Mintz break; 2185c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 2186c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 2187c5ac9319SYuval Mintz break; 21881e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 21891e128c81SArun Easi *p_proto = QED_PCI_FCOE; 21901e128c81SArun Easi break; 2191c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 2192c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 21936927e826SMintz, Yuval /* Fallthrough */ 2194fe56b9e6SYuval Mintz default: 2195fe56b9e6SYuval Mintz rc = -EINVAL; 2196fe56b9e6SYuval Mintz } 2197fe56b9e6SYuval Mintz 2198fe56b9e6SYuval Mintz return rc; 2199fe56b9e6SYuval Mintz } 2200fe56b9e6SYuval Mintz 2201fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2202fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2203fe56b9e6SYuval Mintz { 2204fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 2205fe56b9e6SYuval Mintz struct public_func shmem_info; 2206fe56b9e6SYuval Mintz 22071a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2208fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 2209fe56b9e6SYuval Mintz 2210fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 2211fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2212fe56b9e6SYuval Mintz 22136927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 22146927e826SMintz, Yuval &info->protocol)) { 2215fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 2216fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2217fe56b9e6SYuval Mintz return -EINVAL; 2218fe56b9e6SYuval Mintz } 2219fe56b9e6SYuval Mintz 22204b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2221fe56b9e6SYuval Mintz 2222fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 2223fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2224fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 2225fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2226fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2227fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2228fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 222914d39648SMintz, Yuval 223014d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 223114d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2232fe56b9e6SYuval Mintz } else { 2233fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2234fe56b9e6SYuval Mintz } 2235fe56b9e6SYuval Mintz 223657796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 223757796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 223857796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 223957796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2240fe56b9e6SYuval Mintz 2241fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2242fe56b9e6SYuval Mintz 22430fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 22440fefbfbaSSudarsana Kalluru 224514d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 224614d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 224714d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 224814d39648SMintz, Yuval u32 resp = 0, param = 0; 224914d39648SMintz, Yuval int rc; 225014d39648SMintz, Yuval 225114d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 225214d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 225314d39648SMintz, Yuval if (rc) 225414d39648SMintz, Yuval return rc; 225514d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 225614d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 225714d39648SMintz, Yuval } 225814d39648SMintz, Yuval 2259fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 226014d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 2261fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2262fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2263fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 2264fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 226514d39648SMintz, Yuval info->wwn_port, info->wwn_node, 226614d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2267fe56b9e6SYuval Mintz 2268fe56b9e6SYuval Mintz return 0; 2269fe56b9e6SYuval Mintz } 2270fe56b9e6SYuval Mintz 2271cc875c2eSYuval Mintz struct qed_mcp_link_params 2272cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2273cc875c2eSYuval Mintz { 2274cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2275cc875c2eSYuval Mintz return NULL; 2276cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2277cc875c2eSYuval Mintz } 2278cc875c2eSYuval Mintz 2279cc875c2eSYuval Mintz struct qed_mcp_link_state 2280cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2281cc875c2eSYuval Mintz { 2282cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2283cc875c2eSYuval Mintz return NULL; 2284cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2285cc875c2eSYuval Mintz } 2286cc875c2eSYuval Mintz 2287cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2288cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2289cc875c2eSYuval Mintz { 2290cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2291cc875c2eSYuval Mintz return NULL; 2292cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2293cc875c2eSYuval Mintz } 2294cc875c2eSYuval Mintz 22951a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2296fe56b9e6SYuval Mintz { 2297fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2298fe56b9e6SYuval Mintz int rc; 2299fe56b9e6SYuval Mintz 2300fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 23011a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2302fe56b9e6SYuval Mintz 2303fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 23048f60bafeSYuval Mintz msleep(1020); 2305fe56b9e6SYuval Mintz 2306fe56b9e6SYuval Mintz return rc; 2307fe56b9e6SYuval Mintz } 2308fe56b9e6SYuval Mintz 2309cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 23101a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2311cee4d264SManish Chopra { 2312cee4d264SManish Chopra u32 flash_size; 2313cee4d264SManish Chopra 23141408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 23151408cc1fSYuval Mintz return -EINVAL; 23161408cc1fSYuval Mintz 2317cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2318cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2319cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2320cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2321cee4d264SManish Chopra 2322cee4d264SManish Chopra *p_flash_size = flash_size; 2323cee4d264SManish Chopra 2324cee4d264SManish Chopra return 0; 2325cee4d264SManish Chopra } 2326cee4d264SManish Chopra 232788072fd4SMintz, Yuval static int 232888072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 23291408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 23301408cc1fSYuval Mintz { 23311408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 23321408cc1fSYuval Mintz int rc; 23331408cc1fSYuval Mintz 23341408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 23351408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 23361408cc1fSYuval Mintz return 0; 23371408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 23381408cc1fSYuval Mintz 23391408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 23401408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 23411408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 23421408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 23431408cc1fSYuval Mintz 23441408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 23451408cc1fSYuval Mintz &resp, &rc_param); 23461408cc1fSYuval Mintz 23471408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 23481408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 23491408cc1fSYuval Mintz rc = -EINVAL; 23501408cc1fSYuval Mintz } else { 23511408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 23521408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 23531408cc1fSYuval Mintz num, vf_id); 23541408cc1fSYuval Mintz } 23551408cc1fSYuval Mintz 23561408cc1fSYuval Mintz return rc; 23571408cc1fSYuval Mintz } 23581408cc1fSYuval Mintz 235988072fd4SMintz, Yuval static int 236088072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 236188072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 236288072fd4SMintz, Yuval { 236388072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 236488072fd4SMintz, Yuval int rc; 236588072fd4SMintz, Yuval 236688072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 236788072fd4SMintz, Yuval param, &resp, &rc_param); 236888072fd4SMintz, Yuval 236988072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 237088072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 237188072fd4SMintz, Yuval rc = -EINVAL; 237288072fd4SMintz, Yuval } else { 237388072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 237488072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 237588072fd4SMintz, Yuval } 237688072fd4SMintz, Yuval 237788072fd4SMintz, Yuval return rc; 237888072fd4SMintz, Yuval } 237988072fd4SMintz, Yuval 238088072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 238188072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 238288072fd4SMintz, Yuval { 238388072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 238488072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 238588072fd4SMintz, Yuval else 238688072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 238788072fd4SMintz, Yuval } 238888072fd4SMintz, Yuval 2389fe56b9e6SYuval Mintz int 2390fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2391fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2392fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2393fe56b9e6SYuval Mintz { 23945529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 23952f67af8cSTomer Tayar struct drv_version_stc drv_version; 23965529bad9STomer Tayar __be32 val; 23975529bad9STomer Tayar u32 i; 23985529bad9STomer Tayar int rc; 2399fe56b9e6SYuval Mintz 24002f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 24012f67af8cSTomer Tayar drv_version.version = p_ver->version; 240267a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 240367a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 24042f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2405fe56b9e6SYuval Mintz } 2406fe56b9e6SYuval Mintz 24075529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 24085529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 24092f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 24102f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 24115529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 24125529bad9STomer Tayar if (rc) 2413fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2414fe56b9e6SYuval Mintz 24155529bad9STomer Tayar return rc; 2416fe56b9e6SYuval Mintz } 241791420b83SSudarsana Kalluru 241876271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 241976271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 242076271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 242176271809STomer Tayar 24224102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 24234102426fSTomer Tayar { 242476271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 24254102426fSTomer Tayar int rc; 24264102426fSTomer Tayar 24274102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 24284102426fSTomer Tayar ¶m); 242976271809STomer Tayar if (rc) { 24304102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 24314102426fSTomer Tayar return rc; 24324102426fSTomer Tayar } 24334102426fSTomer Tayar 243476271809STomer Tayar do { 243576271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 243676271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 243776271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 243876271809STomer Tayar break; 243976271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 244076271809STomer Tayar 244176271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 244276271809STomer Tayar DP_NOTICE(p_hwfn, 244376271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 244476271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 244576271809STomer Tayar return -EBUSY; 244676271809STomer Tayar } 244776271809STomer Tayar 2448b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2449b310974eSTomer Tayar 245076271809STomer Tayar return 0; 245176271809STomer Tayar } 245276271809STomer Tayar 245376271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 245476271809STomer Tayar 24554102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 24564102426fSTomer Tayar { 245776271809STomer Tayar u32 cpu_mode, cpu_state; 24584102426fSTomer Tayar 24594102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 24604102426fSTomer Tayar 24614102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 246276271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 246376271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 246476271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 246576271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 24664102426fSTomer Tayar 246776271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 246876271809STomer Tayar DP_NOTICE(p_hwfn, 246976271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 247076271809STomer Tayar cpu_mode, cpu_state); 247176271809STomer Tayar return -EBUSY; 247276271809STomer Tayar } 247376271809STomer Tayar 2474b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2475b310974eSTomer Tayar 247676271809STomer Tayar return 0; 24774102426fSTomer Tayar } 24784102426fSTomer Tayar 24790fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 24800fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 24810fefbfbaSSudarsana Kalluru enum qed_ov_client client) 24820fefbfbaSSudarsana Kalluru { 24830fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 24840fefbfbaSSudarsana Kalluru u32 drv_mb_param; 24850fefbfbaSSudarsana Kalluru int rc; 24860fefbfbaSSudarsana Kalluru 24870fefbfbaSSudarsana Kalluru switch (client) { 24880fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 24890fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 24900fefbfbaSSudarsana Kalluru break; 24910fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 24920fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 24930fefbfbaSSudarsana Kalluru break; 24940fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 24950fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 24960fefbfbaSSudarsana Kalluru break; 24970fefbfbaSSudarsana Kalluru default: 24980fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 24990fefbfbaSSudarsana Kalluru return -EINVAL; 25000fefbfbaSSudarsana Kalluru } 25010fefbfbaSSudarsana Kalluru 25020fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 25030fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 25040fefbfbaSSudarsana Kalluru if (rc) 25050fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 25060fefbfbaSSudarsana Kalluru 25070fefbfbaSSudarsana Kalluru return rc; 25080fefbfbaSSudarsana Kalluru } 25090fefbfbaSSudarsana Kalluru 25100fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 25110fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 25120fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 25130fefbfbaSSudarsana Kalluru { 25140fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 25150fefbfbaSSudarsana Kalluru u32 drv_mb_param; 25160fefbfbaSSudarsana Kalluru int rc; 25170fefbfbaSSudarsana Kalluru 25180fefbfbaSSudarsana Kalluru switch (drv_state) { 25190fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 25200fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 25210fefbfbaSSudarsana Kalluru break; 25220fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 25230fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 25240fefbfbaSSudarsana Kalluru break; 25250fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 25260fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 25270fefbfbaSSudarsana Kalluru break; 25280fefbfbaSSudarsana Kalluru default: 25290fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 25300fefbfbaSSudarsana Kalluru return -EINVAL; 25310fefbfbaSSudarsana Kalluru } 25320fefbfbaSSudarsana Kalluru 25330fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 25340fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 25350fefbfbaSSudarsana Kalluru if (rc) 25360fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 25370fefbfbaSSudarsana Kalluru 25380fefbfbaSSudarsana Kalluru return rc; 25390fefbfbaSSudarsana Kalluru } 25400fefbfbaSSudarsana Kalluru 25410fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 25420fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 25430fefbfbaSSudarsana Kalluru { 25440fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 25450fefbfbaSSudarsana Kalluru u32 drv_mb_param; 25460fefbfbaSSudarsana Kalluru int rc; 25470fefbfbaSSudarsana Kalluru 25480fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 25490fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 25500fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 25510fefbfbaSSudarsana Kalluru if (rc) 25520fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 25530fefbfbaSSudarsana Kalluru 25540fefbfbaSSudarsana Kalluru return rc; 25550fefbfbaSSudarsana Kalluru } 25560fefbfbaSSudarsana Kalluru 25570fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 25580fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 25590fefbfbaSSudarsana Kalluru { 25600fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 256117991002SMintz, Yuval u32 mfw_mac[2]; 25620fefbfbaSSudarsana Kalluru int rc; 25630fefbfbaSSudarsana Kalluru 25640fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 25650fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 25660fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 25670fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 25680fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 25692f67af8cSTomer Tayar 257017991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 257117991002SMintz, Yuval * in 32-bit granularity. 257217991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 257317991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 257417991002SMintz, Yuval */ 257517991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 257617991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 257717991002SMintz, Yuval 257817991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 257917991002SMintz, Yuval mb_params.data_src_size = 8; 25800fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 25810fefbfbaSSudarsana Kalluru if (rc) 25820fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 25830fefbfbaSSudarsana Kalluru 258414d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 258514d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 258614d39648SMintz, Yuval 25870fefbfbaSSudarsana Kalluru return rc; 25880fefbfbaSSudarsana Kalluru } 25890fefbfbaSSudarsana Kalluru 25900fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 25910fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 25920fefbfbaSSudarsana Kalluru { 25930fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 25940fefbfbaSSudarsana Kalluru u32 drv_mb_param; 25950fefbfbaSSudarsana Kalluru int rc; 25960fefbfbaSSudarsana Kalluru 259714d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 259814d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 259914d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 260014d39648SMintz, Yuval return -EINVAL; 260114d39648SMintz, Yuval } 260214d39648SMintz, Yuval 26030fefbfbaSSudarsana Kalluru switch (wol) { 26040fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 26050fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 26060fefbfbaSSudarsana Kalluru break; 26070fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 26080fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 26090fefbfbaSSudarsana Kalluru break; 26100fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 26110fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 26120fefbfbaSSudarsana Kalluru break; 26130fefbfbaSSudarsana Kalluru default: 26140fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 26150fefbfbaSSudarsana Kalluru return -EINVAL; 26160fefbfbaSSudarsana Kalluru } 26170fefbfbaSSudarsana Kalluru 26180fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 26190fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 26200fefbfbaSSudarsana Kalluru if (rc) 26210fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 26220fefbfbaSSudarsana Kalluru 262314d39648SMintz, Yuval /* Store the WoL update for a future unload */ 262414d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 262514d39648SMintz, Yuval 26260fefbfbaSSudarsana Kalluru return rc; 26270fefbfbaSSudarsana Kalluru } 26280fefbfbaSSudarsana Kalluru 26290fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 26300fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 26310fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 26320fefbfbaSSudarsana Kalluru { 26330fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 26340fefbfbaSSudarsana Kalluru u32 drv_mb_param; 26350fefbfbaSSudarsana Kalluru int rc; 26360fefbfbaSSudarsana Kalluru 26370fefbfbaSSudarsana Kalluru switch (eswitch) { 26380fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 26390fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 26400fefbfbaSSudarsana Kalluru break; 26410fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 26420fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 26430fefbfbaSSudarsana Kalluru break; 26440fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 26450fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 26460fefbfbaSSudarsana Kalluru break; 26470fefbfbaSSudarsana Kalluru default: 26480fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 26490fefbfbaSSudarsana Kalluru return -EINVAL; 26500fefbfbaSSudarsana Kalluru } 26510fefbfbaSSudarsana Kalluru 26520fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 26530fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 26540fefbfbaSSudarsana Kalluru if (rc) 26550fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 26560fefbfbaSSudarsana Kalluru 26570fefbfbaSSudarsana Kalluru return rc; 26580fefbfbaSSudarsana Kalluru } 26590fefbfbaSSudarsana Kalluru 26601a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 26611a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 266291420b83SSudarsana Kalluru { 266391420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 266491420b83SSudarsana Kalluru int rc; 266591420b83SSudarsana Kalluru 266691420b83SSudarsana Kalluru switch (mode) { 266791420b83SSudarsana Kalluru case QED_LED_MODE_ON: 266891420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 266991420b83SSudarsana Kalluru break; 267091420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 267191420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 267291420b83SSudarsana Kalluru break; 267391420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 267491420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 267591420b83SSudarsana Kalluru break; 267691420b83SSudarsana Kalluru default: 267791420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 267891420b83SSudarsana Kalluru return -EINVAL; 267991420b83SSudarsana Kalluru } 268091420b83SSudarsana Kalluru 268191420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 268291420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 268391420b83SSudarsana Kalluru 268491420b83SSudarsana Kalluru return rc; 268591420b83SSudarsana Kalluru } 268603dc76caSSudarsana Reddy Kalluru 26874102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 26884102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 26894102426fSTomer Tayar { 26904102426fSTomer Tayar u32 resp = 0, param = 0; 26914102426fSTomer Tayar int rc; 26924102426fSTomer Tayar 26934102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 26944102426fSTomer Tayar mask_parities, &resp, ¶m); 26954102426fSTomer Tayar 26964102426fSTomer Tayar if (rc) { 26974102426fSTomer Tayar DP_ERR(p_hwfn, 26984102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 26994102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 27004102426fSTomer Tayar DP_ERR(p_hwfn, 27014102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 27024102426fSTomer Tayar rc = -EINVAL; 27034102426fSTomer Tayar } 27044102426fSTomer Tayar 27054102426fSTomer Tayar return rc; 27064102426fSTomer Tayar } 27074102426fSTomer Tayar 27087a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 27097a4b21b7SMintz, Yuval { 27107a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 27117a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 27127a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 27137a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 27147a4b21b7SMintz, Yuval int rc = 0; 27157a4b21b7SMintz, Yuval 27167a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 27177a4b21b7SMintz, Yuval if (!p_ptt) 27187a4b21b7SMintz, Yuval return -EBUSY; 27197a4b21b7SMintz, Yuval 27207a4b21b7SMintz, Yuval while (bytes_left > 0) { 27217a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 27227a4b21b7SMintz, Yuval 27237a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 27247a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 27257a4b21b7SMintz, Yuval addr + offset + 27267a4b21b7SMintz, Yuval (bytes_to_copy << 2727da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 27287a4b21b7SMintz, Yuval &resp, &resp_param, 27297a4b21b7SMintz, Yuval &read_len, 27307a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 27317a4b21b7SMintz, Yuval 27327a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 27337a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 27347a4b21b7SMintz, Yuval break; 27357a4b21b7SMintz, Yuval } 27367a4b21b7SMintz, Yuval 27377a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 27387a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 27397a4b21b7SMintz, Yuval */ 27407a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 27417a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 27427a4b21b7SMintz, Yuval usleep_range(1000, 2000); 27437a4b21b7SMintz, Yuval 27447a4b21b7SMintz, Yuval offset += read_len; 27457a4b21b7SMintz, Yuval bytes_left -= read_len; 27467a4b21b7SMintz, Yuval } 27477a4b21b7SMintz, Yuval 27487a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 27497a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 27507a4b21b7SMintz, Yuval 27517a4b21b7SMintz, Yuval return rc; 27527a4b21b7SMintz, Yuval } 27537a4b21b7SMintz, Yuval 275462e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 275562e4d438SSudarsana Reddy Kalluru { 275662e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 275762e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 275862e4d438SSudarsana Reddy Kalluru 275962e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 276062e4d438SSudarsana Reddy Kalluru if (!p_ptt) 276162e4d438SSudarsana Reddy Kalluru return -EBUSY; 276262e4d438SSudarsana Reddy Kalluru 276362e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 276462e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 276562e4d438SSudarsana Reddy Kalluru 276662e4d438SSudarsana Reddy Kalluru return 0; 276762e4d438SSudarsana Reddy Kalluru } 276862e4d438SSudarsana Reddy Kalluru 276962e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 277062e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 277162e4d438SSudarsana Reddy Kalluru { 277262e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 277362e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 277462e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 277562e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 277662e4d438SSudarsana Reddy Kalluru 277762e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 277862e4d438SSudarsana Reddy Kalluru if (!p_ptt) 277962e4d438SSudarsana Reddy Kalluru return -EBUSY; 278062e4d438SSudarsana Reddy Kalluru 278162e4d438SSudarsana Reddy Kalluru switch (cmd) { 2782057d2b19SSudarsana Reddy Kalluru case QED_PUT_FILE_BEGIN: 2783057d2b19SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 2784057d2b19SSudarsana Reddy Kalluru break; 278562e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 278662e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 278762e4d438SSudarsana Reddy Kalluru break; 278862e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 278962e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 279062e4d438SSudarsana Reddy Kalluru break; 279162e4d438SSudarsana Reddy Kalluru default: 279262e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 279362e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 279462e4d438SSudarsana Reddy Kalluru goto out; 279562e4d438SSudarsana Reddy Kalluru } 279662e4d438SSudarsana Reddy Kalluru 279762e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 2798057d2b19SSudarsana Reddy Kalluru while (buf_idx < len) { 2799057d2b19SSudarsana Reddy Kalluru if (cmd == QED_PUT_FILE_BEGIN) 2800057d2b19SSudarsana Reddy Kalluru nvm_offset = addr; 2801057d2b19SSudarsana Reddy Kalluru else 2802057d2b19SSudarsana Reddy Kalluru nvm_offset = ((buf_size << 2803057d2b19SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 2804057d2b19SSudarsana Reddy Kalluru buf_idx; 280562e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 280662e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 280762e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 280862e4d438SSudarsana Reddy Kalluru if (rc) { 280962e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 281062e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 281162e4d438SSudarsana Reddy Kalluru break; 281262e4d438SSudarsana Reddy Kalluru } 281362e4d438SSudarsana Reddy Kalluru 281462e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 281562e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 281662e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 281762e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 281862e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 281962e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 282062e4d438SSudarsana Reddy Kalluru break; 282162e4d438SSudarsana Reddy Kalluru } 282262e4d438SSudarsana Reddy Kalluru 282362e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 282462e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 282562e4d438SSudarsana Reddy Kalluru */ 282662e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 282762e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 282862e4d438SSudarsana Reddy Kalluru 2829057d2b19SSudarsana Reddy Kalluru /* For MBI upgrade, MFW response includes the next buffer offset 2830057d2b19SSudarsana Reddy Kalluru * to be delivered to MFW. 2831057d2b19SSudarsana Reddy Kalluru */ 2832057d2b19SSudarsana Reddy Kalluru if (param && cmd == QED_PUT_FILE_DATA) { 2833057d2b19SSudarsana Reddy Kalluru buf_idx = QED_MFW_GET_FIELD(param, 2834057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 2835057d2b19SSudarsana Reddy Kalluru buf_size = QED_MFW_GET_FIELD(param, 2836057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 2837057d2b19SSudarsana Reddy Kalluru } else { 283862e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 2839057d2b19SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), 2840057d2b19SSudarsana Reddy Kalluru MCP_DRV_NVM_BUF_LEN); 2841057d2b19SSudarsana Reddy Kalluru } 284262e4d438SSudarsana Reddy Kalluru } 284362e4d438SSudarsana Reddy Kalluru 284462e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 284562e4d438SSudarsana Reddy Kalluru out: 284662e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 284762e4d438SSudarsana Reddy Kalluru 284862e4d438SSudarsana Reddy Kalluru return rc; 284962e4d438SSudarsana Reddy Kalluru } 285062e4d438SSudarsana Reddy Kalluru 2851b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2852b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2853b51dab46SSudarsana Reddy Kalluru { 2854b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2855b51dab46SSudarsana Reddy Kalluru u32 resp, param; 2856b51dab46SSudarsana Reddy Kalluru int rc; 2857b51dab46SSudarsana Reddy Kalluru 2858b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2859b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2860b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2861b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2862b51dab46SSudarsana Reddy Kalluru 2863b51dab46SSudarsana Reddy Kalluru addr = offset; 2864b51dab46SSudarsana Reddy Kalluru offset = 0; 2865b51dab46SSudarsana Reddy Kalluru bytes_left = len; 2866b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 2867b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 2868b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 2869b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2870b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2871b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 2872b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2873b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2874b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 2875b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2876b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2877b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2878b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 2879b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 2880b51dab46SSudarsana Reddy Kalluru (u32 *)(p_buf + offset)); 2881b51dab46SSudarsana Reddy Kalluru if (rc) { 2882b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 2883b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2884b51dab46SSudarsana Reddy Kalluru rc); 2885b51dab46SSudarsana Reddy Kalluru return rc; 2886b51dab46SSudarsana Reddy Kalluru } 2887b51dab46SSudarsana Reddy Kalluru 2888b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2889b51dab46SSudarsana Reddy Kalluru return -ENODEV; 2890b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2891b51dab46SSudarsana Reddy Kalluru return -EINVAL; 2892b51dab46SSudarsana Reddy Kalluru 2893b51dab46SSudarsana Reddy Kalluru offset += buf_size; 2894b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 2895b51dab46SSudarsana Reddy Kalluru } 2896b51dab46SSudarsana Reddy Kalluru 2897b51dab46SSudarsana Reddy Kalluru return 0; 2898b51dab46SSudarsana Reddy Kalluru } 2899b51dab46SSudarsana Reddy Kalluru 290003dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 290103dc76caSSudarsana Reddy Kalluru { 290203dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 290303dc76caSSudarsana Reddy Kalluru int rc = 0; 290403dc76caSSudarsana Reddy Kalluru 290503dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 290603dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 290703dc76caSSudarsana Reddy Kalluru 290803dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 290903dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 291003dc76caSSudarsana Reddy Kalluru 291103dc76caSSudarsana Reddy Kalluru if (rc) 291203dc76caSSudarsana Reddy Kalluru return rc; 291303dc76caSSudarsana Reddy Kalluru 291403dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 291503dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 291603dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 291703dc76caSSudarsana Reddy Kalluru 291803dc76caSSudarsana Reddy Kalluru return rc; 291903dc76caSSudarsana Reddy Kalluru } 292003dc76caSSudarsana Reddy Kalluru 292103dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 292203dc76caSSudarsana Reddy Kalluru { 292303dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 292403dc76caSSudarsana Reddy Kalluru int rc = 0; 292503dc76caSSudarsana Reddy Kalluru 292603dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 292703dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 292803dc76caSSudarsana Reddy Kalluru 292903dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 293003dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 293103dc76caSSudarsana Reddy Kalluru 293203dc76caSSudarsana Reddy Kalluru if (rc) 293303dc76caSSudarsana Reddy Kalluru return rc; 293403dc76caSSudarsana Reddy Kalluru 293503dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 293603dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 293703dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 293803dc76caSSudarsana Reddy Kalluru 293903dc76caSSudarsana Reddy Kalluru return rc; 294003dc76caSSudarsana Reddy Kalluru } 29417a4b21b7SMintz, Yuval 294243645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 29437a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 29447a4b21b7SMintz, Yuval u32 *num_images) 29457a4b21b7SMintz, Yuval { 29467a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 29477a4b21b7SMintz, Yuval int rc = 0; 29487a4b21b7SMintz, Yuval 29497a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 29507a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 29517a4b21b7SMintz, Yuval 29527a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 29537a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 29547a4b21b7SMintz, Yuval if (rc) 29557a4b21b7SMintz, Yuval return rc; 29567a4b21b7SMintz, Yuval 29577a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 29587a4b21b7SMintz, Yuval rc = -EINVAL; 29597a4b21b7SMintz, Yuval 29607a4b21b7SMintz, Yuval return rc; 29617a4b21b7SMintz, Yuval } 29627a4b21b7SMintz, Yuval 296343645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 29647a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 29657a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 29667a4b21b7SMintz, Yuval u32 image_index) 29677a4b21b7SMintz, Yuval { 29687a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 29697a4b21b7SMintz, Yuval int rc; 29707a4b21b7SMintz, Yuval 29717a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 29727a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 29737a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 29747a4b21b7SMintz, Yuval 29757a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 29767a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 29777a4b21b7SMintz, Yuval &resp, &resp_param, 29787a4b21b7SMintz, Yuval &buf_size, 29797a4b21b7SMintz, Yuval (u32 *)p_image_att); 29807a4b21b7SMintz, Yuval if (rc) 29817a4b21b7SMintz, Yuval return rc; 29827a4b21b7SMintz, Yuval 29837a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 29847a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 29857a4b21b7SMintz, Yuval rc = -EINVAL; 29867a4b21b7SMintz, Yuval 29877a4b21b7SMintz, Yuval return rc; 29887a4b21b7SMintz, Yuval } 29892edbff8dSTomer Tayar 299043645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 299143645ce0SSudarsana Reddy Kalluru { 29925e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 299343645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 299443645ce0SSudarsana Reddy Kalluru int rc; 299543645ce0SSudarsana Reddy Kalluru u32 i; 299643645ce0SSudarsana Reddy Kalluru 29975e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 29985e7ba042SDenis Bolotin return 0; 29995e7ba042SDenis Bolotin 300043645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 300143645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 300243645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 300343645ce0SSudarsana Reddy Kalluru return -EBUSY; 300443645ce0SSudarsana Reddy Kalluru } 300543645ce0SSudarsana Reddy Kalluru 300643645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 30075e7ba042SDenis Bolotin nvm_info.num_images = 0; 300843645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 30095e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 301043645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 301143645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 301243645ce0SSudarsana Reddy Kalluru goto out; 30135e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 301443645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 301543645ce0SSudarsana Reddy Kalluru goto err0; 301643645ce0SSudarsana Reddy Kalluru } 301743645ce0SSudarsana Reddy Kalluru 30185e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 301943645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 302043645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 30215e7ba042SDenis Bolotin if (!nvm_info.image_att) { 302243645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 302343645ce0SSudarsana Reddy Kalluru goto err0; 302443645ce0SSudarsana Reddy Kalluru } 302543645ce0SSudarsana Reddy Kalluru 302643645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 30275e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 302843645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 30295e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 303043645ce0SSudarsana Reddy Kalluru if (rc) { 303143645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 303243645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 303343645ce0SSudarsana Reddy Kalluru goto err1; 303443645ce0SSudarsana Reddy Kalluru } 303543645ce0SSudarsana Reddy Kalluru 303643645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 30375e7ba042SDenis Bolotin nvm_info.image_att[i].len); 303843645ce0SSudarsana Reddy Kalluru } 303943645ce0SSudarsana Reddy Kalluru out: 30405e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 30415e7ba042SDenis Bolotin if (nvm_info.num_images) { 30425e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 30435e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 30445e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 30455e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 30465e7ba042SDenis Bolotin } 30475e7ba042SDenis Bolotin 304843645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 304943645ce0SSudarsana Reddy Kalluru return 0; 305043645ce0SSudarsana Reddy Kalluru 305143645ce0SSudarsana Reddy Kalluru err1: 30525e7ba042SDenis Bolotin kfree(nvm_info.image_att); 305343645ce0SSudarsana Reddy Kalluru err0: 305443645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 305543645ce0SSudarsana Reddy Kalluru return rc; 305643645ce0SSudarsana Reddy Kalluru } 305743645ce0SSudarsana Reddy Kalluru 30581ac4329aSDenis Bolotin int 305920675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 306020675b37SMintz, Yuval enum qed_nvm_images image_id, 306120675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 306220675b37SMintz, Yuval { 306320675b37SMintz, Yuval enum nvm_image_type type; 306443645ce0SSudarsana Reddy Kalluru u32 i; 306520675b37SMintz, Yuval 306620675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 306720675b37SMintz, Yuval switch (image_id) { 306820675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 306920675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 307020675b37SMintz, Yuval break; 307120675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 307220675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 307320675b37SMintz, Yuval break; 30741ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 30751ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 30761ac4329aSDenis Bolotin break; 30771ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 30781ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 30791ac4329aSDenis Bolotin break; 30801ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 30811ac4329aSDenis Bolotin type = NVM_TYPE_META; 30821ac4329aSDenis Bolotin break; 308320675b37SMintz, Yuval default: 308420675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 308520675b37SMintz, Yuval image_id); 308620675b37SMintz, Yuval return -EINVAL; 308720675b37SMintz, Yuval } 308820675b37SMintz, Yuval 30895e7ba042SDenis Bolotin qed_mcp_nvm_info_populate(p_hwfn); 309043645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 309143645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 309220675b37SMintz, Yuval break; 309343645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 309420675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 309520675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 309620675b37SMintz, Yuval image_id); 309743645ce0SSudarsana Reddy Kalluru return -ENOENT; 309820675b37SMintz, Yuval } 309920675b37SMintz, Yuval 310043645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 310143645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 310220675b37SMintz, Yuval 310320675b37SMintz, Yuval return 0; 310420675b37SMintz, Yuval } 310520675b37SMintz, Yuval 310620675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 310720675b37SMintz, Yuval enum qed_nvm_images image_id, 310820675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 310920675b37SMintz, Yuval { 311020675b37SMintz, Yuval struct qed_nvm_image_att image_att; 311120675b37SMintz, Yuval int rc; 311220675b37SMintz, Yuval 311320675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 311420675b37SMintz, Yuval 3115b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 311620675b37SMintz, Yuval if (rc) 311720675b37SMintz, Yuval return rc; 311820675b37SMintz, Yuval 311920675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 312020675b37SMintz, Yuval if (image_att.length <= 4) { 312120675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 312220675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 312320675b37SMintz, Yuval image_id, image_att.length); 312420675b37SMintz, Yuval return -EINVAL; 312520675b37SMintz, Yuval } 312620675b37SMintz, Yuval 312720675b37SMintz, Yuval if (image_att.length > buffer_len) { 312820675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 312920675b37SMintz, Yuval QED_MSG_STORAGE, 313020675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 313120675b37SMintz, Yuval image_id, image_att.length, buffer_len); 313220675b37SMintz, Yuval return -ENOMEM; 313320675b37SMintz, Yuval } 313420675b37SMintz, Yuval 313520675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 313620675b37SMintz, Yuval p_buffer, image_att.length); 313720675b37SMintz, Yuval } 313820675b37SMintz, Yuval 31399c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 31409c8517c4STomer Tayar { 31419c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 31429c8517c4STomer Tayar 31439c8517c4STomer Tayar switch (res_id) { 31449c8517c4STomer Tayar case QED_SB: 31459c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 31469c8517c4STomer Tayar break; 31479c8517c4STomer Tayar case QED_L2_QUEUE: 31489c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 31499c8517c4STomer Tayar break; 31509c8517c4STomer Tayar case QED_VPORT: 31519c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 31529c8517c4STomer Tayar break; 31539c8517c4STomer Tayar case QED_RSS_ENG: 31549c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 31559c8517c4STomer Tayar break; 31569c8517c4STomer Tayar case QED_PQ: 31579c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 31589c8517c4STomer Tayar break; 31599c8517c4STomer Tayar case QED_RL: 31609c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 31619c8517c4STomer Tayar break; 31629c8517c4STomer Tayar case QED_MAC: 31639c8517c4STomer Tayar case QED_VLAN: 31649c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 31659c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 31669c8517c4STomer Tayar break; 31679c8517c4STomer Tayar case QED_ILT: 31689c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 31699c8517c4STomer Tayar break; 31709c8517c4STomer Tayar case QED_LL2_QUEUE: 31719c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 31729c8517c4STomer Tayar break; 31739c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 31749c8517c4STomer Tayar case QED_CMDQS_CQS: 31759c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 31769c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 31779c8517c4STomer Tayar break; 31789c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 31799c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 31809c8517c4STomer Tayar break; 31819c8517c4STomer Tayar case QED_BDQ: 31829c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 31839c8517c4STomer Tayar break; 31849c8517c4STomer Tayar default: 31859c8517c4STomer Tayar break; 31869c8517c4STomer Tayar } 31879c8517c4STomer Tayar 31889c8517c4STomer Tayar return mfw_res_id; 31899c8517c4STomer Tayar } 31909c8517c4STomer Tayar 31919c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 31922edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 31932edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 31942edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 31952edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 31962edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 31972edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 31989c8517c4STomer Tayar 31999c8517c4STomer Tayar struct qed_resc_alloc_in_params { 32009c8517c4STomer Tayar u32 cmd; 32019c8517c4STomer Tayar enum qed_resources res_id; 32029c8517c4STomer Tayar u32 resc_max_val; 32039c8517c4STomer Tayar }; 32049c8517c4STomer Tayar 32059c8517c4STomer Tayar struct qed_resc_alloc_out_params { 32069c8517c4STomer Tayar u32 mcp_resp; 32079c8517c4STomer Tayar u32 mcp_param; 32089c8517c4STomer Tayar u32 resc_num; 32099c8517c4STomer Tayar u32 resc_start; 32109c8517c4STomer Tayar u32 vf_resc_num; 32119c8517c4STomer Tayar u32 vf_resc_start; 32129c8517c4STomer Tayar u32 flags; 32139c8517c4STomer Tayar }; 32149c8517c4STomer Tayar 32159c8517c4STomer Tayar static int 32169c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 32172edbff8dSTomer Tayar struct qed_ptt *p_ptt, 32189c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 32199c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 32202edbff8dSTomer Tayar { 32212edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 32229c8517c4STomer Tayar struct resource_info mfw_resc_info; 32232edbff8dSTomer Tayar int rc; 32242edbff8dSTomer Tayar 32259c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3226bb480242SMintz, Yuval 32279c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 32289c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 32299c8517c4STomer Tayar DP_ERR(p_hwfn, 32309c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 32319c8517c4STomer Tayar p_in_params->res_id, 32329c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 32339c8517c4STomer Tayar return -EINVAL; 32349c8517c4STomer Tayar } 32359c8517c4STomer Tayar 32369c8517c4STomer Tayar switch (p_in_params->cmd) { 32379c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 32389c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 32399c8517c4STomer Tayar /* Fallthrough */ 32409c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 32419c8517c4STomer Tayar break; 32429c8517c4STomer Tayar default: 32439c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 32449c8517c4STomer Tayar p_in_params->cmd); 32459c8517c4STomer Tayar return -EINVAL; 32469c8517c4STomer Tayar } 32479c8517c4STomer Tayar 32489c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 32499c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 32509c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 32519c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 32529c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 32539c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 32549c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 32559c8517c4STomer Tayar 32569c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 32579c8517c4STomer Tayar QED_MSG_SP, 32589c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 32599c8517c4STomer Tayar p_in_params->cmd, 32609c8517c4STomer Tayar p_in_params->res_id, 32619c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 32629c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 32639c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 32649c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 32659c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 32669c8517c4STomer Tayar p_in_params->resc_max_val); 32679c8517c4STomer Tayar 32682edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 32692edbff8dSTomer Tayar if (rc) 32702edbff8dSTomer Tayar return rc; 32712edbff8dSTomer Tayar 32729c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 32739c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 32749c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 32759c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 32769c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 32779c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 32789c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 32792edbff8dSTomer Tayar 32802edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 32812edbff8dSTomer Tayar QED_MSG_SP, 32829c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 32839c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 32849c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 32859c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 32869c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 32879c8517c4STomer Tayar p_out_params->resc_num, 32889c8517c4STomer Tayar p_out_params->resc_start, 32899c8517c4STomer Tayar p_out_params->vf_resc_num, 32909c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 32919c8517c4STomer Tayar 32929c8517c4STomer Tayar return 0; 32939c8517c4STomer Tayar } 32949c8517c4STomer Tayar 32959c8517c4STomer Tayar int 32969c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 32979c8517c4STomer Tayar struct qed_ptt *p_ptt, 32989c8517c4STomer Tayar enum qed_resources res_id, 32999c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 33009c8517c4STomer Tayar { 33019c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 33029c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 33039c8517c4STomer Tayar int rc; 33049c8517c4STomer Tayar 33059c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 33069c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 33079c8517c4STomer Tayar in_params.res_id = res_id; 33089c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 33099c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 33109c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 33119c8517c4STomer Tayar &out_params); 33129c8517c4STomer Tayar if (rc) 33139c8517c4STomer Tayar return rc; 33149c8517c4STomer Tayar 33159c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 33169c8517c4STomer Tayar 33179c8517c4STomer Tayar return 0; 33189c8517c4STomer Tayar } 33199c8517c4STomer Tayar 33209c8517c4STomer Tayar int 33219c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 33229c8517c4STomer Tayar struct qed_ptt *p_ptt, 33239c8517c4STomer Tayar enum qed_resources res_id, 33249c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 33259c8517c4STomer Tayar { 33269c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 33279c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 33289c8517c4STomer Tayar int rc; 33299c8517c4STomer Tayar 33309c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 33319c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 33329c8517c4STomer Tayar in_params.res_id = res_id; 33339c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 33349c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 33359c8517c4STomer Tayar &out_params); 33369c8517c4STomer Tayar if (rc) 33379c8517c4STomer Tayar return rc; 33389c8517c4STomer Tayar 33399c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 33409c8517c4STomer Tayar 33419c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 33429c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 33439c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 33449c8517c4STomer Tayar } 33452edbff8dSTomer Tayar 33462edbff8dSTomer Tayar return 0; 33472edbff8dSTomer Tayar } 334818a69e36SMintz, Yuval 334918a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 335018a69e36SMintz, Yuval { 335118a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 335218a69e36SMintz, Yuval 335318a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 335418a69e36SMintz, Yuval &mcp_resp, &mcp_param); 335518a69e36SMintz, Yuval } 335695691c9cSTomer Tayar 335795691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 335895691c9cSTomer Tayar struct qed_ptt *p_ptt, 335995691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 336095691c9cSTomer Tayar { 336195691c9cSTomer Tayar int rc; 336295691c9cSTomer Tayar 336395691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 336495691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 336595691c9cSTomer Tayar if (rc) 336695691c9cSTomer Tayar return rc; 336795691c9cSTomer Tayar 336895691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 336995691c9cSTomer Tayar DP_INFO(p_hwfn, 337095691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 337195691c9cSTomer Tayar return -EINVAL; 337295691c9cSTomer Tayar } 337395691c9cSTomer Tayar 337495691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 337595691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 337695691c9cSTomer Tayar 337795691c9cSTomer Tayar DP_NOTICE(p_hwfn, 337895691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 337995691c9cSTomer Tayar param, opcode); 338095691c9cSTomer Tayar return -EINVAL; 338195691c9cSTomer Tayar } 338295691c9cSTomer Tayar 338395691c9cSTomer Tayar return rc; 338495691c9cSTomer Tayar } 338595691c9cSTomer Tayar 3386bf774d14SYueHaibing static int 338795691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 338895691c9cSTomer Tayar struct qed_ptt *p_ptt, 338995691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 339095691c9cSTomer Tayar { 339195691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 339295691c9cSTomer Tayar u8 opcode; 339395691c9cSTomer Tayar int rc; 339495691c9cSTomer Tayar 339595691c9cSTomer Tayar switch (p_params->timeout) { 339695691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 339795691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 339895691c9cSTomer Tayar p_params->timeout = 0; 339995691c9cSTomer Tayar break; 340095691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 340195691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 340295691c9cSTomer Tayar p_params->timeout = 0; 340395691c9cSTomer Tayar break; 340495691c9cSTomer Tayar default: 340595691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 340695691c9cSTomer Tayar break; 340795691c9cSTomer Tayar } 340895691c9cSTomer Tayar 340995691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 341095691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 341195691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 341295691c9cSTomer Tayar 341395691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 341495691c9cSTomer Tayar QED_MSG_SP, 341595691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 341695691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 341795691c9cSTomer Tayar 341895691c9cSTomer Tayar /* Attempt to acquire the resource */ 341995691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 342095691c9cSTomer Tayar if (rc) 342195691c9cSTomer Tayar return rc; 342295691c9cSTomer Tayar 342395691c9cSTomer Tayar /* Analyze the response */ 342495691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 342595691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 342695691c9cSTomer Tayar 342795691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 342895691c9cSTomer Tayar QED_MSG_SP, 342995691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 343095691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 343195691c9cSTomer Tayar 343295691c9cSTomer Tayar switch (opcode) { 343395691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 343495691c9cSTomer Tayar p_params->b_granted = true; 343595691c9cSTomer Tayar break; 343695691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 343795691c9cSTomer Tayar p_params->b_granted = false; 343895691c9cSTomer Tayar break; 343995691c9cSTomer Tayar default: 344095691c9cSTomer Tayar DP_NOTICE(p_hwfn, 344195691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 344295691c9cSTomer Tayar mcp_param, opcode); 344395691c9cSTomer Tayar return -EINVAL; 344495691c9cSTomer Tayar } 344595691c9cSTomer Tayar 344695691c9cSTomer Tayar return 0; 344795691c9cSTomer Tayar } 344895691c9cSTomer Tayar 344995691c9cSTomer Tayar int 345095691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 345195691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 345295691c9cSTomer Tayar { 345395691c9cSTomer Tayar u32 retry_cnt = 0; 345495691c9cSTomer Tayar int rc; 345595691c9cSTomer Tayar 345695691c9cSTomer Tayar do { 345795691c9cSTomer Tayar /* No need for an interval before the first iteration */ 345895691c9cSTomer Tayar if (retry_cnt) { 345995691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 346095691c9cSTomer Tayar u16 retry_interval_in_ms = 346195691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 346295691c9cSTomer Tayar 1000); 346395691c9cSTomer Tayar 346495691c9cSTomer Tayar msleep(retry_interval_in_ms); 346595691c9cSTomer Tayar } else { 346695691c9cSTomer Tayar udelay(p_params->retry_interval); 346795691c9cSTomer Tayar } 346895691c9cSTomer Tayar } 346995691c9cSTomer Tayar 347095691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 347195691c9cSTomer Tayar if (rc) 347295691c9cSTomer Tayar return rc; 347395691c9cSTomer Tayar 347495691c9cSTomer Tayar if (p_params->b_granted) 347595691c9cSTomer Tayar break; 347695691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 347795691c9cSTomer Tayar 347895691c9cSTomer Tayar return 0; 347995691c9cSTomer Tayar } 348095691c9cSTomer Tayar 348195691c9cSTomer Tayar int 348295691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 348395691c9cSTomer Tayar struct qed_ptt *p_ptt, 348495691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 348595691c9cSTomer Tayar { 348695691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 348795691c9cSTomer Tayar u8 opcode; 348895691c9cSTomer Tayar int rc; 348995691c9cSTomer Tayar 349095691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 349195691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 349295691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 349395691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 349495691c9cSTomer Tayar 349595691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 349695691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 349795691c9cSTomer Tayar param, opcode, p_params->resource); 349895691c9cSTomer Tayar 349995691c9cSTomer Tayar /* Attempt to release the resource */ 350095691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 350195691c9cSTomer Tayar if (rc) 350295691c9cSTomer Tayar return rc; 350395691c9cSTomer Tayar 350495691c9cSTomer Tayar /* Analyze the response */ 350595691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 350695691c9cSTomer Tayar 350795691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 350895691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 350995691c9cSTomer Tayar mcp_param, opcode); 351095691c9cSTomer Tayar 351195691c9cSTomer Tayar switch (opcode) { 351295691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 351395691c9cSTomer Tayar DP_INFO(p_hwfn, 351495691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 351595691c9cSTomer Tayar p_params->resource); 351695691c9cSTomer Tayar /* Fallthrough */ 351795691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 351895691c9cSTomer Tayar p_params->b_released = true; 351995691c9cSTomer Tayar break; 352095691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 352195691c9cSTomer Tayar p_params->b_released = false; 352295691c9cSTomer Tayar break; 352395691c9cSTomer Tayar default: 352495691c9cSTomer Tayar DP_NOTICE(p_hwfn, 352595691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 352695691c9cSTomer Tayar mcp_param, opcode); 352795691c9cSTomer Tayar return -EINVAL; 352895691c9cSTomer Tayar } 352995691c9cSTomer Tayar 353095691c9cSTomer Tayar return 0; 353195691c9cSTomer Tayar } 3532f470f22cSsudarsana.kalluru@cavium.com 3533f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3534f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3535f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3536f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3537f470f22cSsudarsana.kalluru@cavium.com { 3538f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3539f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3540f470f22cSsudarsana.kalluru@cavium.com 3541f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3542f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3543f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3544f470f22cSsudarsana.kalluru@cavium.com */ 3545f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3546f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3547f470f22cSsudarsana.kalluru@cavium.com } else { 3548f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3549f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3550f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3551f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3552f470f22cSsudarsana.kalluru@cavium.com } 3553f470f22cSsudarsana.kalluru@cavium.com 3554f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3555f470f22cSsudarsana.kalluru@cavium.com } 3556f470f22cSsudarsana.kalluru@cavium.com 3557f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3558f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3559f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3560f470f22cSsudarsana.kalluru@cavium.com } 3561f470f22cSsudarsana.kalluru@cavium.com } 3562645874e5SSudarsana Reddy Kalluru 3563645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3564645874e5SSudarsana Reddy Kalluru { 3565645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3566645874e5SSudarsana Reddy Kalluru int rc; 3567645874e5SSudarsana Reddy Kalluru 3568645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3569645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3570645874e5SSudarsana Reddy Kalluru if (!rc) 3571645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3572645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3573645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3574645874e5SSudarsana Reddy Kalluru 3575645874e5SSudarsana Reddy Kalluru return rc; 3576645874e5SSudarsana Reddy Kalluru } 3577645874e5SSudarsana Reddy Kalluru 3578645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3579645874e5SSudarsana Reddy Kalluru { 3580645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3581645874e5SSudarsana Reddy Kalluru 3582e40a826aSSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3583e40a826aSSudarsana Reddy Kalluru DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK; 3584645874e5SSudarsana Reddy Kalluru 3585645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3586645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3587645874e5SSudarsana Reddy Kalluru } 3588