1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 4339651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 44fe56b9e6SYuval Mintz #include "qed_hsi.h" 45fe56b9e6SYuval Mintz #include "qed_hw.h" 46fe56b9e6SYuval Mintz #include "qed_mcp.h" 47fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 481408cc1fSYuval Mintz #include "qed_sriov.h" 491408cc1fSYuval Mintz 50fe56b9e6SYuval Mintz #define CHIP_MCP_RESP_ITER_US 10 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 53fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 56fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 57fe56b9e6SYuval Mintz _val) 58fe56b9e6SYuval Mintz 59fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 60fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 61fe56b9e6SYuval Mintz 62fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 63fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 64fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 67fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 68fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 69fe56b9e6SYuval Mintz 70fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 71fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 72fe56b9e6SYuval Mintz 73fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 74fe56b9e6SYuval Mintz 75fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 76fe56b9e6SYuval Mintz { 77fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 78fe56b9e6SYuval Mintz return false; 79fe56b9e6SYuval Mintz return true; 80fe56b9e6SYuval Mintz } 81fe56b9e6SYuval Mintz 821a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 83fe56b9e6SYuval Mintz { 84fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 85fe56b9e6SYuval Mintz PUBLIC_PORT); 86fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 89fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 90fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 91fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 92fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 93fe56b9e6SYuval Mintz } 94fe56b9e6SYuval Mintz 951a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 96fe56b9e6SYuval Mintz { 97fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 98fe56b9e6SYuval Mintz u32 tmp, i; 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 101fe56b9e6SYuval Mintz return; 102fe56b9e6SYuval Mintz 103fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 104fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 105fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 106fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 107fe56b9e6SYuval Mintz 108fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 109fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 110fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 111fe56b9e6SYuval Mintz } 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz 1144ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1154ed1eea8STomer Tayar struct list_head list; 1164ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1174ed1eea8STomer Tayar u16 expected_seq_num; 1184ed1eea8STomer Tayar bool b_is_completed; 1194ed1eea8STomer Tayar }; 1204ed1eea8STomer Tayar 1214ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1224ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1234ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1244ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1254ed1eea8STomer Tayar u16 expected_seq_num) 1264ed1eea8STomer Tayar { 1274ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1284ed1eea8STomer Tayar 1294ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1304ed1eea8STomer Tayar if (!p_cmd_elem) 1314ed1eea8STomer Tayar goto out; 1324ed1eea8STomer Tayar 1334ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1344ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1354ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1364ed1eea8STomer Tayar out: 1374ed1eea8STomer Tayar return p_cmd_elem; 1384ed1eea8STomer Tayar } 1394ed1eea8STomer Tayar 1404ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1414ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1424ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1434ed1eea8STomer Tayar { 1444ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1454ed1eea8STomer Tayar kfree(p_cmd_elem); 1464ed1eea8STomer Tayar } 1474ed1eea8STomer Tayar 1484ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1494ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1504ed1eea8STomer Tayar u16 seq_num) 1514ed1eea8STomer Tayar { 1524ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1534ed1eea8STomer Tayar 1544ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1554ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1564ed1eea8STomer Tayar return p_cmd_elem; 1574ed1eea8STomer Tayar } 1584ed1eea8STomer Tayar 1594ed1eea8STomer Tayar return NULL; 1604ed1eea8STomer Tayar } 1614ed1eea8STomer Tayar 162fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 163fe56b9e6SYuval Mintz { 164fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1654ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1664ed1eea8STomer Tayar 167fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 168fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1694ed1eea8STomer Tayar 1704ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1714ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1724ed1eea8STomer Tayar p_tmp, 1734ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1744ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 175fe56b9e6SYuval Mintz } 1764ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1774ed1eea8STomer Tayar } 1784ed1eea8STomer Tayar 179fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1803587cb87STomer Tayar p_hwfn->mcp_info = NULL; 181fe56b9e6SYuval Mintz 182fe56b9e6SYuval Mintz return 0; 183fe56b9e6SYuval Mintz } 184fe56b9e6SYuval Mintz 1851a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 186fe56b9e6SYuval Mintz { 187fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 188fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 189fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 190fe56b9e6SYuval Mintz 191fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 192fe56b9e6SYuval Mintz if (!p_info->public_base) 193fe56b9e6SYuval Mintz return 0; 194fe56b9e6SYuval Mintz 195fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 196fe56b9e6SYuval Mintz 197fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 198fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 199fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 200fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 201fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 202fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 203fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 204fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 205fe56b9e6SYuval Mintz 206fe56b9e6SYuval Mintz /* Set the MFW MB address */ 207fe56b9e6SYuval Mintz mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 208fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 209fe56b9e6SYuval Mintz PUBLIC_MFW_MB)); 210fe56b9e6SYuval Mintz p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 211fe56b9e6SYuval Mintz p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 212fe56b9e6SYuval Mintz 213fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 214fe56b9e6SYuval Mintz * the first command 215fe56b9e6SYuval Mintz */ 216fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 217fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 218fe56b9e6SYuval Mintz 219fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 220fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 221fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 222fe56b9e6SYuval Mintz 2234ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 224fe56b9e6SYuval Mintz 225fe56b9e6SYuval Mintz return 0; 226fe56b9e6SYuval Mintz } 227fe56b9e6SYuval Mintz 2281a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 229fe56b9e6SYuval Mintz { 230fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 231fe56b9e6SYuval Mintz u32 size; 232fe56b9e6SYuval Mintz 233fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 23460fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 235fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 236fe56b9e6SYuval Mintz goto err; 237fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 238fe56b9e6SYuval Mintz 2394ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2404ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2414ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2424ed1eea8STomer Tayar 2434ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2444ed1eea8STomer Tayar 245fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 246fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 247fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 248fe56b9e6SYuval Mintz * the MCP is not initialized 249fe56b9e6SYuval Mintz */ 250fe56b9e6SYuval Mintz return 0; 251fe56b9e6SYuval Mintz } 252fe56b9e6SYuval Mintz 253fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 25460fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 25583aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 256eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 257fe56b9e6SYuval Mintz goto err; 258fe56b9e6SYuval Mintz 259fe56b9e6SYuval Mintz return 0; 260fe56b9e6SYuval Mintz 261fe56b9e6SYuval Mintz err: 262fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 263fe56b9e6SYuval Mintz return -ENOMEM; 264fe56b9e6SYuval Mintz } 265fe56b9e6SYuval Mintz 2664ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 2674ed1eea8STomer Tayar struct qed_ptt *p_ptt) 2685529bad9STomer Tayar { 2694ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2705529bad9STomer Tayar 2714ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 2724ed1eea8STomer Tayar * time and now. 2735529bad9STomer Tayar */ 2744ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 2754ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 2764ed1eea8STomer Tayar QED_MSG_SP, 2774ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 2784ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 2795529bad9STomer Tayar 2804ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 2814ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2825529bad9STomer Tayar } 2835529bad9STomer Tayar } 2845529bad9STomer Tayar 2851a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 286fe56b9e6SYuval Mintz { 2874ed1eea8STomer Tayar u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0; 288fe56b9e6SYuval Mintz int rc = 0; 289fe56b9e6SYuval Mintz 2904ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 2914ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 2924ed1eea8STomer Tayar 2934ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2945529bad9STomer Tayar 295fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 2964ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 2974ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 2984ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 299fe56b9e6SYuval Mintz 300fe56b9e6SYuval Mintz do { 301fe56b9e6SYuval Mintz /* Wait for MFW response */ 302fe56b9e6SYuval Mintz udelay(delay); 303fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 304fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 305fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 306fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 307fe56b9e6SYuval Mintz 308fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 309fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 310fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 311fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 312fe56b9e6SYuval Mintz } else { 313fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 314fe56b9e6SYuval Mintz rc = -EAGAIN; 315fe56b9e6SYuval Mintz } 316fe56b9e6SYuval Mintz 3174ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3185529bad9STomer Tayar 319fe56b9e6SYuval Mintz return rc; 320fe56b9e6SYuval Mintz } 321fe56b9e6SYuval Mintz 3224ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3234ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 324fe56b9e6SYuval Mintz { 3254ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3264ed1eea8STomer Tayar 3274ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3284ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3294ed1eea8STomer Tayar */ 3304ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3314ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3324ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3334ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3344ed1eea8STomer Tayar } 3354ed1eea8STomer Tayar 3364ed1eea8STomer Tayar return false; 3374ed1eea8STomer Tayar } 3384ed1eea8STomer Tayar 3394ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3404ed1eea8STomer Tayar static int 3414ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3424ed1eea8STomer Tayar { 3434ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3444ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3454ed1eea8STomer Tayar u32 mcp_resp; 3464ed1eea8STomer Tayar u16 seq_num; 3474ed1eea8STomer Tayar 3484ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3494ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3504ed1eea8STomer Tayar 3514ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3524ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3534ed1eea8STomer Tayar return -EAGAIN; 3544ed1eea8STomer Tayar 3554ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3564ed1eea8STomer Tayar if (!p_cmd_elem) { 3574ed1eea8STomer Tayar DP_ERR(p_hwfn, 3584ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3594ed1eea8STomer Tayar seq_num); 3604ed1eea8STomer Tayar return -EINVAL; 3614ed1eea8STomer Tayar } 3624ed1eea8STomer Tayar 3634ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3644ed1eea8STomer Tayar 3654ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3664ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 3674ed1eea8STomer Tayar 3684ed1eea8STomer Tayar /* Get the MFW param */ 3694ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 3704ed1eea8STomer Tayar 3714ed1eea8STomer Tayar /* Get the union data */ 3722f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 3734ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3744ed1eea8STomer Tayar offsetof(struct public_drv_mb, 3754ed1eea8STomer Tayar union_data); 3764ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3772f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 3784ed1eea8STomer Tayar } 3794ed1eea8STomer Tayar 3804ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 3814ed1eea8STomer Tayar 3824ed1eea8STomer Tayar return 0; 3834ed1eea8STomer Tayar } 3844ed1eea8STomer Tayar 3854ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3864ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 3874ed1eea8STomer Tayar struct qed_ptt *p_ptt, 3884ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 3894ed1eea8STomer Tayar u16 seq_num) 3904ed1eea8STomer Tayar { 3914ed1eea8STomer Tayar union drv_union_data union_data; 3924ed1eea8STomer Tayar u32 union_data_addr; 3934ed1eea8STomer Tayar 3944ed1eea8STomer Tayar /* Set the union data */ 3954ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3964ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 3974ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 3982f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 3994ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4002f67af8cSTomer Tayar p_mb_params->data_src_size); 4014ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4024ed1eea8STomer Tayar sizeof(union_data)); 4034ed1eea8STomer Tayar 4044ed1eea8STomer Tayar /* Set the drv param */ 4054ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4064ed1eea8STomer Tayar 4074ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4084ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4094ed1eea8STomer Tayar 4104ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4114ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4124ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4134ed1eea8STomer Tayar } 4144ed1eea8STomer Tayar 4154ed1eea8STomer Tayar static int 4164ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4174ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4184ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4194ed1eea8STomer Tayar u32 max_retries, u32 delay) 4204ed1eea8STomer Tayar { 4214ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4224ed1eea8STomer Tayar u32 cnt = 0; 4234ed1eea8STomer Tayar u16 seq_num; 424fe56b9e6SYuval Mintz int rc = 0; 425fe56b9e6SYuval Mintz 4264ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 427fe56b9e6SYuval Mintz do { 4284ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4294ed1eea8STomer Tayar * pending command is completed during this iteration. 4304ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4314ed1eea8STomer Tayar */ 4324ed1eea8STomer Tayar 4334ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4344ed1eea8STomer Tayar 4354ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4364ed1eea8STomer Tayar break; 4374ed1eea8STomer Tayar 4384ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4394ed1eea8STomer Tayar if (!rc) 4404ed1eea8STomer Tayar break; 4414ed1eea8STomer Tayar else if (rc != -EAGAIN) 4424ed1eea8STomer Tayar goto err; 4434ed1eea8STomer Tayar 4444ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 445fe56b9e6SYuval Mintz udelay(delay); 4464ed1eea8STomer Tayar } while (++cnt < max_retries); 447fe56b9e6SYuval Mintz 4484ed1eea8STomer Tayar if (cnt >= max_retries) { 4494ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4504ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4514ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4524ed1eea8STomer Tayar return -EAGAIN; 453fe56b9e6SYuval Mintz } 4544ed1eea8STomer Tayar 4554ed1eea8STomer Tayar /* Send the mailbox command */ 4564ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 4574ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 4584ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 459c8004600SDan Carpenter if (!p_cmd_elem) { 460c8004600SDan Carpenter rc = -ENOMEM; 4614ed1eea8STomer Tayar goto err; 462c8004600SDan Carpenter } 4634ed1eea8STomer Tayar 4644ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 4654ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4664ed1eea8STomer Tayar 4674ed1eea8STomer Tayar /* Wait for the MFW response */ 4684ed1eea8STomer Tayar do { 4694ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 4704ed1eea8STomer Tayar * command is completed during this iteration. 4714ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 4724ed1eea8STomer Tayar */ 4734ed1eea8STomer Tayar 4744ed1eea8STomer Tayar udelay(delay); 4754ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4764ed1eea8STomer Tayar 4774ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 4784ed1eea8STomer Tayar break; 4794ed1eea8STomer Tayar 4804ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4814ed1eea8STomer Tayar if (!rc) 4824ed1eea8STomer Tayar break; 4834ed1eea8STomer Tayar else if (rc != -EAGAIN) 4844ed1eea8STomer Tayar goto err; 4854ed1eea8STomer Tayar 4864ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4874ed1eea8STomer Tayar } while (++cnt < max_retries); 4884ed1eea8STomer Tayar 4894ed1eea8STomer Tayar if (cnt >= max_retries) { 4904ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4914ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 4924ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4934ed1eea8STomer Tayar 4944ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4954ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 4964ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4974ed1eea8STomer Tayar 4984ed1eea8STomer Tayar return -EAGAIN; 4994ed1eea8STomer Tayar } 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5024ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5034ed1eea8STomer Tayar 5044ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5054ed1eea8STomer Tayar QED_MSG_SP, 5064ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5074ed1eea8STomer Tayar p_mb_params->mcp_resp, 5084ed1eea8STomer Tayar p_mb_params->mcp_param, 5094ed1eea8STomer Tayar (cnt * delay) / 1000, (cnt * delay) % 1000); 5104ed1eea8STomer Tayar 5114ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5124ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5134ed1eea8STomer Tayar 5144ed1eea8STomer Tayar return 0; 5154ed1eea8STomer Tayar 5164ed1eea8STomer Tayar err: 5174ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 518fe56b9e6SYuval Mintz return rc; 519fe56b9e6SYuval Mintz } 520fe56b9e6SYuval Mintz 5215529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 522fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5235529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 524fe56b9e6SYuval Mintz { 5252f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5264ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 5274ed1eea8STomer Tayar u32 delay = CHIP_MCP_RESP_ITER_US; 528fe56b9e6SYuval Mintz 529fe56b9e6SYuval Mintz /* MCP not initialized */ 530fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 531fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 532fe56b9e6SYuval Mintz return -EBUSY; 533fe56b9e6SYuval Mintz } 534fe56b9e6SYuval Mintz 5352f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 5362f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 5372f67af8cSTomer Tayar DP_ERR(p_hwfn, 5382f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 5392f67af8cSTomer Tayar p_mb_params->data_src_size, 5402f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 5412f67af8cSTomer Tayar return -EINVAL; 5422f67af8cSTomer Tayar } 5432f67af8cSTomer Tayar 5444ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 5454ed1eea8STomer Tayar delay); 546fe56b9e6SYuval Mintz } 547fe56b9e6SYuval Mintz 5485529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 5495529bad9STomer Tayar struct qed_ptt *p_ptt, 5505529bad9STomer Tayar u32 cmd, 5515529bad9STomer Tayar u32 param, 5525529bad9STomer Tayar u32 *o_mcp_resp, 5535529bad9STomer Tayar u32 *o_mcp_param) 554fe56b9e6SYuval Mintz { 5555529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 5565529bad9STomer Tayar int rc; 557fe56b9e6SYuval Mintz 5585529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 5595529bad9STomer Tayar mb_params.cmd = cmd; 5605529bad9STomer Tayar mb_params.param = param; 56114d39648SMintz, Yuval 5625529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 5635529bad9STomer Tayar if (rc) 5645529bad9STomer Tayar return rc; 5655529bad9STomer Tayar 5665529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 5675529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 5685529bad9STomer Tayar 5695529bad9STomer Tayar return 0; 570fe56b9e6SYuval Mintz } 571fe56b9e6SYuval Mintz 57262e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 57362e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 57462e4d438SSudarsana Reddy Kalluru u32 cmd, 57562e4d438SSudarsana Reddy Kalluru u32 param, 57662e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 57762e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 57862e4d438SSudarsana Reddy Kalluru { 57962e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 58062e4d438SSudarsana Reddy Kalluru int rc; 58162e4d438SSudarsana Reddy Kalluru 58262e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 58362e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 58462e4d438SSudarsana Reddy Kalluru mb_params.param = param; 58562e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 58662e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 58762e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 58862e4d438SSudarsana Reddy Kalluru if (rc) 58962e4d438SSudarsana Reddy Kalluru return rc; 59062e4d438SSudarsana Reddy Kalluru 59162e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 59262e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 59362e4d438SSudarsana Reddy Kalluru 59462e4d438SSudarsana Reddy Kalluru return 0; 59562e4d438SSudarsana Reddy Kalluru } 59662e4d438SSudarsana Reddy Kalluru 5974102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 5984102426fSTomer Tayar struct qed_ptt *p_ptt, 5994102426fSTomer Tayar u32 cmd, 6004102426fSTomer Tayar u32 param, 6014102426fSTomer Tayar u32 *o_mcp_resp, 6024102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6034102426fSTomer Tayar { 6044102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6052f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 6064102426fSTomer Tayar int rc; 6074102426fSTomer Tayar 6084102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6094102426fSTomer Tayar mb_params.cmd = cmd; 6104102426fSTomer Tayar mb_params.param = param; 6112f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 6122f67af8cSTomer Tayar 6132f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 6142f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 6152f67af8cSTomer Tayar 6164102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6174102426fSTomer Tayar if (rc) 6184102426fSTomer Tayar return rc; 6194102426fSTomer Tayar 6204102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6214102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 6224102426fSTomer Tayar 6234102426fSTomer Tayar *o_txn_size = *o_mcp_param; 6242f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 6254102426fSTomer Tayar 6264102426fSTomer Tayar return 0; 6274102426fSTomer Tayar } 6284102426fSTomer Tayar 6295d24bcf1STomer Tayar static bool 6305d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 6315d24bcf1STomer Tayar u8 exist_drv_role, 6325d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 633fe56b9e6SYuval Mintz { 6345d24bcf1STomer Tayar bool can_force_load = false; 6355d24bcf1STomer Tayar 6365d24bcf1STomer Tayar switch (override_force_load) { 6375d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 6385d24bcf1STomer Tayar can_force_load = true; 6395d24bcf1STomer Tayar break; 6405d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 6415d24bcf1STomer Tayar can_force_load = false; 6425d24bcf1STomer Tayar break; 6435d24bcf1STomer Tayar default: 6445d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 6455d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 6465d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 6475d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 6485d24bcf1STomer Tayar break; 6495d24bcf1STomer Tayar } 6505d24bcf1STomer Tayar 6515d24bcf1STomer Tayar return can_force_load; 6525d24bcf1STomer Tayar } 6535d24bcf1STomer Tayar 6545d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 6555d24bcf1STomer Tayar struct qed_ptt *p_ptt) 6565d24bcf1STomer Tayar { 6575d24bcf1STomer Tayar u32 resp = 0, param = 0; 658fe56b9e6SYuval Mintz int rc; 659fe56b9e6SYuval Mintz 6605d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 6615d24bcf1STomer Tayar &resp, ¶m); 6625d24bcf1STomer Tayar if (rc) 6635d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 6645d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 665fe56b9e6SYuval Mintz 666fe56b9e6SYuval Mintz return rc; 667fe56b9e6SYuval Mintz } 668fe56b9e6SYuval Mintz 6695d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 6705d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 6715d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 6725d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 6735d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 6745d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 6755529bad9STomer Tayar 6765d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 6775d24bcf1STomer Tayar { 6785d24bcf1STomer Tayar u32 config_bitmap = 0x0; 6795d24bcf1STomer Tayar 6805d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 6815d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 6825d24bcf1STomer Tayar 6835d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 6845d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 6855d24bcf1STomer Tayar 6865d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 6875d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 6885d24bcf1STomer Tayar 6895d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 6905d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 6915d24bcf1STomer Tayar 6925d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 6935d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 6945d24bcf1STomer Tayar 6955d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 6965d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 6975d24bcf1STomer Tayar 6985d24bcf1STomer Tayar return config_bitmap; 6995d24bcf1STomer Tayar } 7005d24bcf1STomer Tayar 7015d24bcf1STomer Tayar struct qed_load_req_in_params { 7025d24bcf1STomer Tayar u8 hsi_ver; 7035d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7045d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7055d24bcf1STomer Tayar u32 drv_ver_0; 7065d24bcf1STomer Tayar u32 drv_ver_1; 7075d24bcf1STomer Tayar u32 fw_ver; 7085d24bcf1STomer Tayar u8 drv_role; 7095d24bcf1STomer Tayar u8 timeout_val; 7105d24bcf1STomer Tayar u8 force_cmd; 7115d24bcf1STomer Tayar bool avoid_eng_reset; 7125d24bcf1STomer Tayar }; 7135d24bcf1STomer Tayar 7145d24bcf1STomer Tayar struct qed_load_req_out_params { 7155d24bcf1STomer Tayar u32 load_code; 7165d24bcf1STomer Tayar u32 exist_drv_ver_0; 7175d24bcf1STomer Tayar u32 exist_drv_ver_1; 7185d24bcf1STomer Tayar u32 exist_fw_ver; 7195d24bcf1STomer Tayar u8 exist_drv_role; 7205d24bcf1STomer Tayar u8 mfw_hsi_ver; 7215d24bcf1STomer Tayar bool drv_exists; 7225d24bcf1STomer Tayar }; 7235d24bcf1STomer Tayar 7245d24bcf1STomer Tayar static int 7255d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 7265d24bcf1STomer Tayar struct qed_ptt *p_ptt, 7275d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 7285d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 7295d24bcf1STomer Tayar { 7305d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 7315d24bcf1STomer Tayar struct load_req_stc load_req; 7325d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 7335d24bcf1STomer Tayar u32 hsi_ver; 7345d24bcf1STomer Tayar int rc; 7355d24bcf1STomer Tayar 7365d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 7375d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 7385d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 7395d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 7405d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 7415d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 7425d24bcf1STomer Tayar p_in_params->timeout_val); 7435d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 7445d24bcf1STomer Tayar p_in_params->force_cmd); 7455d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 7465d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 7475d24bcf1STomer Tayar 7485d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 7495d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 7505d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 7515d24bcf1STomer Tayar 7525d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7535d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 7545d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 7555d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 7565d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 7575d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 7585d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 7595d24bcf1STomer Tayar 7605d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 7615d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 7625d24bcf1STomer Tayar mb_params.param, 7635d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 7645d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 7655d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 7665d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 7675d24bcf1STomer Tayar 7685d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 7695d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 7705d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 7715d24bcf1STomer Tayar load_req.drv_ver_0, 7725d24bcf1STomer Tayar load_req.drv_ver_1, 7735d24bcf1STomer Tayar load_req.fw_ver, 7745d24bcf1STomer Tayar load_req.misc0, 7755d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 7765d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 7775d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 7785d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 7795d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 7805d24bcf1STomer Tayar } 7815d24bcf1STomer Tayar 7825d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7835d24bcf1STomer Tayar if (rc) { 7845d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 7855d24bcf1STomer Tayar return rc; 7865d24bcf1STomer Tayar } 7875d24bcf1STomer Tayar 7885d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 7895d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 7905d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 7915d24bcf1STomer Tayar 7925d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 7935d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 7945d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 7955d24bcf1STomer Tayar QED_MSG_SP, 7965d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 7975d24bcf1STomer Tayar load_rsp.drv_ver_0, 7985d24bcf1STomer Tayar load_rsp.drv_ver_1, 7995d24bcf1STomer Tayar load_rsp.fw_ver, 8005d24bcf1STomer Tayar load_rsp.misc0, 8015d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8025d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8035d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8045d24bcf1STomer Tayar 8055d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 8065d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 8075d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 8085d24bcf1STomer Tayar p_out_params->exist_drv_role = 8095d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 8105d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 8115d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 8125d24bcf1STomer Tayar p_out_params->drv_exists = 8135d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 8145d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 8155d24bcf1STomer Tayar } 8165d24bcf1STomer Tayar 8175d24bcf1STomer Tayar return 0; 8185d24bcf1STomer Tayar } 8195d24bcf1STomer Tayar 8205d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 8215d24bcf1STomer Tayar enum qed_drv_role drv_role, 8225d24bcf1STomer Tayar u8 *p_mfw_drv_role) 8235d24bcf1STomer Tayar { 8245d24bcf1STomer Tayar switch (drv_role) { 8255d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 8265d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 8275d24bcf1STomer Tayar break; 8285d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 8295d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 8305d24bcf1STomer Tayar break; 8315d24bcf1STomer Tayar default: 8325d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 8335d24bcf1STomer Tayar return -EINVAL; 8345d24bcf1STomer Tayar } 8355d24bcf1STomer Tayar 8365d24bcf1STomer Tayar return 0; 8375d24bcf1STomer Tayar } 8385d24bcf1STomer Tayar 8395d24bcf1STomer Tayar enum qed_load_req_force { 8405d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 8415d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 8425d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 8435d24bcf1STomer Tayar }; 8445d24bcf1STomer Tayar 8455d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 8465d24bcf1STomer Tayar 8475d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 8485d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 8495d24bcf1STomer Tayar { 8505d24bcf1STomer Tayar switch (force_cmd) { 8515d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 8525d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 8535d24bcf1STomer Tayar break; 8545d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 8555d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 8565d24bcf1STomer Tayar break; 8575d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 8585d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 8595d24bcf1STomer Tayar break; 8605d24bcf1STomer Tayar } 8615d24bcf1STomer Tayar } 8625d24bcf1STomer Tayar 8635d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8645d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8655d24bcf1STomer Tayar struct qed_load_req_params *p_params) 8665d24bcf1STomer Tayar { 8675d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 8685d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 8695d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 8705d24bcf1STomer Tayar int rc; 8715d24bcf1STomer Tayar 8725d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 8735d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 8745d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 8755d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 8765d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 8775d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 8785d24bcf1STomer Tayar if (rc) 8795d24bcf1STomer Tayar return rc; 8805d24bcf1STomer Tayar 8815d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 8825d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 8835d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 8845d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 8855d24bcf1STomer Tayar 8865d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 8875d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 8885d24bcf1STomer Tayar 8895d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 8905d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 8915d24bcf1STomer Tayar if (rc) 8925d24bcf1STomer Tayar return rc; 8935d24bcf1STomer Tayar 8945d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 8955d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 8965d24bcf1STomer Tayar * - MFW responds that a force load request is required 897fe56b9e6SYuval Mintz */ 8985d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8995d24bcf1STomer Tayar DP_INFO(p_hwfn, 9005d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9015d24bcf1STomer Tayar 9025d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9035d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9045d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9055d24bcf1STomer Tayar if (rc) 9065d24bcf1STomer Tayar return rc; 9075d24bcf1STomer Tayar } else if (out_params.load_code == 9085d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 9095d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 9105d24bcf1STomer Tayar out_params.exist_drv_role, 9115d24bcf1STomer Tayar p_params->override_force_load)) { 9125d24bcf1STomer Tayar DP_INFO(p_hwfn, 9135d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 9145d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9155d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9165d24bcf1STomer Tayar out_params.exist_drv_role, 9175d24bcf1STomer Tayar out_params.exist_fw_ver, 9185d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9195d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9205d24bcf1STomer Tayar 9215d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9225d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9235d24bcf1STomer Tayar &mfw_force_cmd); 9245d24bcf1STomer Tayar 9255d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9265d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9275d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 9285d24bcf1STomer Tayar &out_params); 9295d24bcf1STomer Tayar if (rc) 9305d24bcf1STomer Tayar return rc; 9315d24bcf1STomer Tayar } else { 9325d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9335d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 9345d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 9355d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 9365d24bcf1STomer Tayar out_params.exist_drv_role, 9375d24bcf1STomer Tayar out_params.exist_fw_ver, 9385d24bcf1STomer Tayar out_params.exist_drv_ver_0, 9395d24bcf1STomer Tayar out_params.exist_drv_ver_1); 9405d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9415d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 9425d24bcf1STomer Tayar 9435d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 944fe56b9e6SYuval Mintz return -EBUSY; 945fe56b9e6SYuval Mintz } 9465d24bcf1STomer Tayar } 9475d24bcf1STomer Tayar 9485d24bcf1STomer Tayar /* Now handle the other types of responses. 9495d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 9505d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 9515d24bcf1STomer Tayar */ 9525d24bcf1STomer Tayar switch (out_params.load_code) { 9535d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 9545d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 9555d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 9565d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 9575d24bcf1STomer Tayar out_params.drv_exists) { 9585d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 9595d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 9605d24bcf1STomer Tayar */ 9615d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9625d24bcf1STomer Tayar "PF is already loaded\n"); 9635d24bcf1STomer Tayar return -EINVAL; 9645d24bcf1STomer Tayar } 9655d24bcf1STomer Tayar break; 9665d24bcf1STomer Tayar default: 9675d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 9685d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 9695d24bcf1STomer Tayar out_params.load_code); 9705d24bcf1STomer Tayar return -EBUSY; 9715d24bcf1STomer Tayar } 9725d24bcf1STomer Tayar 9735d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 974fe56b9e6SYuval Mintz 975fe56b9e6SYuval Mintz return 0; 976fe56b9e6SYuval Mintz } 977fe56b9e6SYuval Mintz 9781226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 9791226337aSTomer Tayar { 9801226337aSTomer Tayar u32 wol_param, mcp_resp, mcp_param; 9811226337aSTomer Tayar 9821226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 9831226337aSTomer Tayar case QED_OV_WOL_DISABLED: 9841226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 9851226337aSTomer Tayar break; 9861226337aSTomer Tayar case QED_OV_WOL_ENABLED: 9871226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 9881226337aSTomer Tayar break; 9891226337aSTomer Tayar default: 9901226337aSTomer Tayar DP_NOTICE(p_hwfn, 9911226337aSTomer Tayar "Unknown WoL configuration %02x\n", 9921226337aSTomer Tayar p_hwfn->cdev->wol_config); 9931226337aSTomer Tayar /* Fallthrough */ 9941226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 9951226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 9961226337aSTomer Tayar } 9971226337aSTomer Tayar 9981226337aSTomer Tayar return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param, 9991226337aSTomer Tayar &mcp_resp, &mcp_param); 10001226337aSTomer Tayar } 10011226337aSTomer Tayar 10021226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10031226337aSTomer Tayar { 10041226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 10051226337aSTomer Tayar struct mcp_mac wol_mac; 10061226337aSTomer Tayar 10071226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 10081226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 10091226337aSTomer Tayar 10101226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 10111226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 10121226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 10131226337aSTomer Tayar 10141226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 10151226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 10161226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 10171226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 10181226337aSTomer Tayar 10191226337aSTomer Tayar DP_VERBOSE(p_hwfn, 10201226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 10211226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 10221226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 10231226337aSTomer Tayar 10241226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 10251226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 10261226337aSTomer Tayar } 10271226337aSTomer Tayar 10281226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10291226337aSTomer Tayar } 10301226337aSTomer Tayar 10310b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 10320b55e27dSYuval Mintz struct qed_ptt *p_ptt) 10330b55e27dSYuval Mintz { 10340b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 10350b55e27dSYuval Mintz PUBLIC_PATH); 10360b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 10370b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 10380b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 10390b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 10400b55e27dSYuval Mintz int i; 10410b55e27dSYuval Mintz 10420b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 10430b55e27dSYuval Mintz QED_MSG_SP, 10440b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 10450b55e27dSYuval Mintz mfw_path_offsize, path_addr); 10460b55e27dSYuval Mintz 10470b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 10480b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 10490b55e27dSYuval Mintz path_addr + 10500b55e27dSYuval Mintz offsetof(struct public_path, 10510b55e27dSYuval Mintz mcp_vf_disabled) + 10520b55e27dSYuval Mintz sizeof(u32) * i); 10530b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 10540b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 10550b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 10560b55e27dSYuval Mintz } 10570b55e27dSYuval Mintz 10580b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 10590b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 10600b55e27dSYuval Mintz } 10610b55e27dSYuval Mintz 10620b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 10630b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 10640b55e27dSYuval Mintz { 10650b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 10660b55e27dSYuval Mintz PUBLIC_FUNC); 10670b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 10680b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 10690b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 10700b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 10710b55e27dSYuval Mintz int rc; 10720b55e27dSYuval Mintz int i; 10730b55e27dSYuval Mintz 10740b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 10750b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 10760b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 10770b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 10780b55e27dSYuval Mintz 10790b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 10800b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 10812f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 10822f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 10830b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10840b55e27dSYuval Mintz if (rc) { 10850b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 10860b55e27dSYuval Mintz return -EBUSY; 10870b55e27dSYuval Mintz } 10880b55e27dSYuval Mintz 10890b55e27dSYuval Mintz /* Clear the ACK bits */ 10900b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 10910b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 10920b55e27dSYuval Mintz func_addr + 10930b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 10940b55e27dSYuval Mintz i * sizeof(u32), 0); 10950b55e27dSYuval Mintz 10960b55e27dSYuval Mintz return rc; 10970b55e27dSYuval Mintz } 10980b55e27dSYuval Mintz 1099334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1100334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1101334c03b5SZvi Nachmani { 1102334c03b5SZvi Nachmani u32 transceiver_state; 1103334c03b5SZvi Nachmani 1104334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1105334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1106334c03b5SZvi Nachmani offsetof(struct public_port, 1107334c03b5SZvi Nachmani transceiver_data)); 1108334c03b5SZvi Nachmani 1109334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1110334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1111334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1112334c03b5SZvi Nachmani transceiver_state, 1113334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 11141a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1115334c03b5SZvi Nachmani 1116334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1117351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1118334c03b5SZvi Nachmani 1119351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1120334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1121334c03b5SZvi Nachmani else 1122334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1123334c03b5SZvi Nachmani } 1124334c03b5SZvi Nachmani 1125645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1126645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1127645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1128645874e5SSudarsana Reddy Kalluru { 1129645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1130645874e5SSudarsana Reddy Kalluru 1131645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1132645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1133645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1134645874e5SSudarsana Reddy Kalluru p_ptt, 1135645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1136645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1137645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1138645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1139645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1140645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1141645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1142645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1143645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1144645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1145645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1146645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1147645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1148645874e5SSudarsana Reddy Kalluru } 1149645874e5SSudarsana Reddy Kalluru 1150cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 11511a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1152cc875c2eSYuval Mintz { 1153cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1154a64b02d5SManish Chopra u8 max_bw, min_bw; 1155cc875c2eSYuval Mintz u32 status = 0; 1156cc875c2eSYuval Mintz 115765ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 115865ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 115965ed2ffdSMintz, Yuval 1160cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1161cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1162cc875c2eSYuval Mintz if (!b_reset) { 1163cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1164cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1165cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1166cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1167cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1168cc875c2eSYuval Mintz status, 1169cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 11701a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1171cc875c2eSYuval Mintz } else { 1172cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1173cc875c2eSYuval Mintz "Resetting link indications\n"); 117465ed2ffdSMintz, Yuval goto out; 1175cc875c2eSYuval Mintz } 1176cc875c2eSYuval Mintz 1177fc916ff2SSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) 1178cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1179fc916ff2SSudarsana Reddy Kalluru else 1180fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1181cc875c2eSYuval Mintz 1182cc875c2eSYuval Mintz p_link->full_duplex = true; 1183cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1184cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1185cc875c2eSYuval Mintz p_link->speed = 100000; 1186cc875c2eSYuval Mintz break; 1187cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1188cc875c2eSYuval Mintz p_link->speed = 50000; 1189cc875c2eSYuval Mintz break; 1190cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1191cc875c2eSYuval Mintz p_link->speed = 40000; 1192cc875c2eSYuval Mintz break; 1193cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1194cc875c2eSYuval Mintz p_link->speed = 25000; 1195cc875c2eSYuval Mintz break; 1196cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1197cc875c2eSYuval Mintz p_link->speed = 20000; 1198cc875c2eSYuval Mintz break; 1199cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1200cc875c2eSYuval Mintz p_link->speed = 10000; 1201cc875c2eSYuval Mintz break; 1202cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1203cc875c2eSYuval Mintz p_link->full_duplex = false; 1204cc875c2eSYuval Mintz /* Fall-through */ 1205cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1206cc875c2eSYuval Mintz p_link->speed = 1000; 1207cc875c2eSYuval Mintz break; 1208cc875c2eSYuval Mintz default: 1209cc875c2eSYuval Mintz p_link->speed = 0; 1210cc875c2eSYuval Mintz } 1211cc875c2eSYuval Mintz 12124b01e519SManish Chopra if (p_link->link_up && p_link->speed) 12134b01e519SManish Chopra p_link->line_speed = p_link->speed; 12144b01e519SManish Chopra else 12154b01e519SManish Chopra p_link->line_speed = 0; 12164b01e519SManish Chopra 12174b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1218a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 12194b01e519SManish Chopra 1220a64b02d5SManish Chopra /* Max bandwidth configuration */ 12214b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1222cc875c2eSYuval Mintz 1223a64b02d5SManish Chopra /* Min bandwidth configuration */ 1224a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 12256f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 12266f437d43SMintz, Yuval p_link->min_pf_rate); 1227a64b02d5SManish Chopra 1228cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1229cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1230cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1231cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1232cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1233cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1234cc875c2eSYuval Mintz 1235cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1236cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1237cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1238cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1239cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1240cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1241cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1242cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1243cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1244cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1245cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1246cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1247cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1248054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1249054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1250054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1251cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1252cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1253cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1254cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1255cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1256cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1257cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1258cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1259cc875c2eSYuval Mintz 1260cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1261cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1262cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1263cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1264cc875c2eSYuval Mintz 1265cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1266cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1267cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1268cc875c2eSYuval Mintz break; 1269cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1270cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1271cc875c2eSYuval Mintz break; 1272cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1273cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1274cc875c2eSYuval Mintz break; 1275cc875c2eSYuval Mintz default: 1276cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1277cc875c2eSYuval Mintz } 1278cc875c2eSYuval Mintz 1279cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1280cc875c2eSYuval Mintz 1281645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1282645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1283645874e5SSudarsana Reddy Kalluru 1284cc875c2eSYuval Mintz qed_link_update(p_hwfn); 128565ed2ffdSMintz, Yuval out: 128665ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1287cc875c2eSYuval Mintz } 1288cc875c2eSYuval Mintz 1289351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1290cc875c2eSYuval Mintz { 1291cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 12925529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 12932f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1294cc875c2eSYuval Mintz int rc = 0; 12955529bad9STomer Tayar u32 cmd; 1296cc875c2eSYuval Mintz 1297cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 12982f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1299cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1300cc875c2eSYuval Mintz if (!params->speed.autoneg) 13012f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 13022f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 13032f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 13042f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 13052f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 13062f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 1307645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 1308645874e5SSudarsana Reddy Kalluru if (params->eee.enable) 1309645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1310645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1311645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1312645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1313645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1314645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1315645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1316645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1317645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1318645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1319645874e5SSudarsana Reddy Kalluru } 1320cc875c2eSYuval Mintz 1321fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1322fc916ff2SSudarsana Reddy Kalluru 1323cc875c2eSYuval Mintz if (b_up) { 1324cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1325cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 13262f67af8cSTomer Tayar phy_cfg.speed, 13272f67af8cSTomer Tayar phy_cfg.pause, 13282f67af8cSTomer Tayar phy_cfg.adv_speed, 13292f67af8cSTomer Tayar phy_cfg.loopback_mode, 13302f67af8cSTomer Tayar phy_cfg.feature_config_flags); 1331cc875c2eSYuval Mintz } else { 1332cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1333cc875c2eSYuval Mintz "Resetting link\n"); 1334cc875c2eSYuval Mintz } 1335cc875c2eSYuval Mintz 13365529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 13375529bad9STomer Tayar mb_params.cmd = cmd; 13382f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 13392f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 13405529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1341cc875c2eSYuval Mintz 1342cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1343cc875c2eSYuval Mintz if (rc) { 1344cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1345cc875c2eSYuval Mintz return rc; 1346cc875c2eSYuval Mintz } 1347cc875c2eSYuval Mintz 134865ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 134965ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 135065ed2ffdSMintz, Yuval * an attention. 135165ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 135265ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 135365ed2ffdSMintz, Yuval */ 135465ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1355cc875c2eSYuval Mintz 1356cc875c2eSYuval Mintz return 0; 1357cc875c2eSYuval Mintz } 1358cc875c2eSYuval Mintz 13596c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 13606c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 13616c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 13626c754246SSudarsana Reddy Kalluru { 13636c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 13646c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 13656c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 13666c754246SSudarsana Reddy Kalluru u32 hsi_param; 13676c754246SSudarsana Reddy Kalluru 13686c754246SSudarsana Reddy Kalluru switch (type) { 13696c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 13706c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 13716c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 13726c754246SSudarsana Reddy Kalluru break; 13736c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 13746c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 13756c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 13766c754246SSudarsana Reddy Kalluru break; 13776c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 13786c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 13796c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 13806c754246SSudarsana Reddy Kalluru break; 13816c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 13826c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 13836c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 13846c754246SSudarsana Reddy Kalluru break; 13856c754246SSudarsana Reddy Kalluru default: 13866c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 13876c754246SSudarsana Reddy Kalluru return; 13886c754246SSudarsana Reddy Kalluru } 13896c754246SSudarsana Reddy Kalluru 13906c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 13916c754246SSudarsana Reddy Kalluru 13926c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 13936c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 13946c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 13952f67af8cSTomer Tayar mb_params.p_data_src = &stats; 13962f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 13976c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 13986c754246SSudarsana Reddy Kalluru } 13996c754246SSudarsana Reddy Kalluru 14004b01e519SManish Chopra static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 14014b01e519SManish Chopra struct public_func *p_shmem_info) 14024b01e519SManish Chopra { 14034b01e519SManish Chopra struct qed_mcp_function_info *p_info; 14044b01e519SManish Chopra 14054b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 14064b01e519SManish Chopra 14074b01e519SManish Chopra p_info->bandwidth_min = (p_shmem_info->config & 14084b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_MASK) >> 14094b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_SHIFT; 14104b01e519SManish Chopra if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 14114b01e519SManish Chopra DP_INFO(p_hwfn, 14124b01e519SManish Chopra "bandwidth minimum out of bounds [%02x]. Set to 1\n", 14134b01e519SManish Chopra p_info->bandwidth_min); 14144b01e519SManish Chopra p_info->bandwidth_min = 1; 14154b01e519SManish Chopra } 14164b01e519SManish Chopra 14174b01e519SManish Chopra p_info->bandwidth_max = (p_shmem_info->config & 14184b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_MASK) >> 14194b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_SHIFT; 14204b01e519SManish Chopra if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 14214b01e519SManish Chopra DP_INFO(p_hwfn, 14224b01e519SManish Chopra "bandwidth maximum out of bounds [%02x]. Set to 100\n", 14234b01e519SManish Chopra p_info->bandwidth_max); 14244b01e519SManish Chopra p_info->bandwidth_max = 100; 14254b01e519SManish Chopra } 14264b01e519SManish Chopra } 14274b01e519SManish Chopra 14284b01e519SManish Chopra static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 14294b01e519SManish Chopra struct qed_ptt *p_ptt, 14301a635e48SYuval Mintz struct public_func *p_data, int pfid) 14314b01e519SManish Chopra { 14324b01e519SManish Chopra u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 14334b01e519SManish Chopra PUBLIC_FUNC); 14344b01e519SManish Chopra u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 14354b01e519SManish Chopra u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 14364b01e519SManish Chopra u32 i, size; 14374b01e519SManish Chopra 14384b01e519SManish Chopra memset(p_data, 0, sizeof(*p_data)); 14394b01e519SManish Chopra 14401a635e48SYuval Mintz size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 14414b01e519SManish Chopra for (i = 0; i < size / sizeof(u32); i++) 14424b01e519SManish Chopra ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 14434b01e519SManish Chopra func_addr + (i << 2)); 14444b01e519SManish Chopra return size; 14454b01e519SManish Chopra } 14464b01e519SManish Chopra 14471a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 14484b01e519SManish Chopra { 14494b01e519SManish Chopra struct qed_mcp_function_info *p_info; 14504b01e519SManish Chopra struct public_func shmem_info; 14514b01e519SManish Chopra u32 resp = 0, param = 0; 14524b01e519SManish Chopra 14531a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 14544b01e519SManish Chopra 14554b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 14564b01e519SManish Chopra 14574b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 14584b01e519SManish Chopra 1459a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 14604b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 14614b01e519SManish Chopra 14624b01e519SManish Chopra /* Acknowledge the MFW */ 14634b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 14644b01e519SManish Chopra ¶m); 14654b01e519SManish Chopra } 14664b01e519SManish Chopra 14672a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 14682a351fd9SMintz, Yuval { 14692a351fd9SMintz, Yuval struct public_func shmem_info; 14702a351fd9SMintz, Yuval u32 resp = 0, param = 0; 14712a351fd9SMintz, Yuval 14722a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 14732a351fd9SMintz, Yuval 14742a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 14752a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 14762a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 14772a351fd9SMintz, Yuval if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) && 14782a351fd9SMintz, Yuval (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) { 14792a351fd9SMintz, Yuval qed_wr(p_hwfn, p_ptt, 14802a351fd9SMintz, Yuval NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan); 14812a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 14822a351fd9SMintz, Yuval } 14832a351fd9SMintz, Yuval 14842a351fd9SMintz, Yuval /* Acknowledge the MFW */ 14852a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 14862a351fd9SMintz, Yuval &resp, ¶m); 14872a351fd9SMintz, Yuval } 14882a351fd9SMintz, Yuval 1489cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1490cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1491cc875c2eSYuval Mintz { 1492cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1493cc875c2eSYuval Mintz int rc = 0; 1494cc875c2eSYuval Mintz bool found = false; 1495cc875c2eSYuval Mintz u16 i; 1496cc875c2eSYuval Mintz 1497cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1498cc875c2eSYuval Mintz 1499cc875c2eSYuval Mintz /* Read Messages from MFW */ 1500cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1501cc875c2eSYuval Mintz 1502cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1503cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1504cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1505cc875c2eSYuval Mintz continue; 1506cc875c2eSYuval Mintz 1507cc875c2eSYuval Mintz found = true; 1508cc875c2eSYuval Mintz 1509cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1510cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1511cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1512cc875c2eSYuval Mintz 1513cc875c2eSYuval Mintz switch (i) { 1514cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1515cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1516cc875c2eSYuval Mintz break; 15170b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 15180b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 15190b55e27dSYuval Mintz break; 152039651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 152139651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 152239651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 152339651abdSSudarsana Reddy Kalluru break; 152439651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 152539651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 152639651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 152739651abdSSudarsana Reddy Kalluru break; 152839651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 152939651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 153039651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 153139651abdSSudarsana Reddy Kalluru break; 1532334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1533334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1534334c03b5SZvi Nachmani break; 15356c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 15366c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 15376c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 15386c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 15396c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 15406c754246SSudarsana Reddy Kalluru break; 15414b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 15424b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 15434b01e519SManish Chopra break; 15442a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 15452a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 15462a351fd9SMintz, Yuval break; 15472a351fd9SMintz, Yuval break; 1548cc875c2eSYuval Mintz default: 154939815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1550cc875c2eSYuval Mintz rc = -EINVAL; 1551cc875c2eSYuval Mintz } 1552cc875c2eSYuval Mintz } 1553cc875c2eSYuval Mintz 1554cc875c2eSYuval Mintz /* ACK everything */ 1555cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1556cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1557cc875c2eSYuval Mintz 1558cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1559cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1560cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1561cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1562cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1563cc875c2eSYuval Mintz (__force u32)val); 1564cc875c2eSYuval Mintz } 1565cc875c2eSYuval Mintz 1566cc875c2eSYuval Mintz if (!found) { 1567cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1568cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1569cc875c2eSYuval Mintz rc = -EINVAL; 1570cc875c2eSYuval Mintz } 1571cc875c2eSYuval Mintz 1572cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1573cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1574cc875c2eSYuval Mintz 1575cc875c2eSYuval Mintz return rc; 1576cc875c2eSYuval Mintz } 1577cc875c2eSYuval Mintz 15781408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 15791408cc1fSYuval Mintz struct qed_ptt *p_ptt, 15801408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1581fe56b9e6SYuval Mintz { 1582fe56b9e6SYuval Mintz u32 global_offsize; 1583fe56b9e6SYuval Mintz 15841408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 15851408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 15861408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 15871408cc1fSYuval Mintz 15881408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 15891408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 15901408cc1fSYuval Mintz return 0; 15911408cc1fSYuval Mintz } else { 15921408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 15931408cc1fSYuval Mintz QED_MSG_IOV, 15941408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 15951408cc1fSYuval Mintz return -EINVAL; 15961408cc1fSYuval Mintz } 15971408cc1fSYuval Mintz } 1598fe56b9e6SYuval Mintz 1599fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 16001408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 16011408cc1fSYuval Mintz mcp_info->public_base, 1602fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 16031408cc1fSYuval Mintz *p_mfw_ver = 16041408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 16051408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 16061408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1607fe56b9e6SYuval Mintz 16081408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 16091408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 16101408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 16111408cc1fSYuval Mintz offsetof(struct public_global, 16121408cc1fSYuval Mintz running_bundle_id)); 16131408cc1fSYuval Mintz } 1614fe56b9e6SYuval Mintz 1615fe56b9e6SYuval Mintz return 0; 1616fe56b9e6SYuval Mintz } 1617fe56b9e6SYuval Mintz 1618ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1619ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1620ae33666aSTomer Tayar { 1621ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1622ae33666aSTomer Tayar 1623ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 1624ae33666aSTomer Tayar return -EINVAL; 1625ae33666aSTomer Tayar 1626ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 1627ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1628ae33666aSTomer Tayar if (!nvm_cfg_addr) { 1629ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1630ae33666aSTomer Tayar return -EINVAL; 1631ae33666aSTomer Tayar } 1632ae33666aSTomer Tayar 1633ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 1634ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1635ae33666aSTomer Tayar 1636ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1637ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 1638ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 1639ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1640ae33666aSTomer Tayar mbi_ver_addr) & 1641ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1642ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1643ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1644ae33666aSTomer Tayar 1645ae33666aSTomer Tayar return 0; 1646ae33666aSTomer Tayar } 1647ae33666aSTomer Tayar 16481a635e48SYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1649cc875c2eSYuval Mintz { 1650cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1651cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 1652cc875c2eSYuval Mintz 16531408cc1fSYuval Mintz if (IS_VF(cdev)) 16541408cc1fSYuval Mintz return -EINVAL; 16551408cc1fSYuval Mintz 1656cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1657cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1658cc875c2eSYuval Mintz return -EBUSY; 1659cc875c2eSYuval Mintz } 1660cc875c2eSYuval Mintz 1661cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1662cc875c2eSYuval Mintz 1663cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 1664cc875c2eSYuval Mintz if (!p_ptt) 1665cc875c2eSYuval Mintz return -EBUSY; 1666cc875c2eSYuval Mintz 1667cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1668cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 1669cc875c2eSYuval Mintz 1670cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 1671cc875c2eSYuval Mintz 1672cc875c2eSYuval Mintz return 0; 1673cc875c2eSYuval Mintz } 1674cc875c2eSYuval Mintz 16756927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 16766927e826SMintz, Yuval static void 16776927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 16786927e826SMintz, Yuval enum qed_pci_personality *p_proto) 16796927e826SMintz, Yuval { 16806927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 16816927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 16826927e826SMintz, Yuval */ 16836927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 16846927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 16856927e826SMintz, Yuval else 16866927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 16876927e826SMintz, Yuval 16886927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 16896927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 16906927e826SMintz, Yuval (u32) *p_proto); 16916927e826SMintz, Yuval } 16926927e826SMintz, Yuval 16936927e826SMintz, Yuval static int 16946927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 16956927e826SMintz, Yuval struct qed_ptt *p_ptt, 16966927e826SMintz, Yuval enum qed_pci_personality *p_proto) 16976927e826SMintz, Yuval { 16986927e826SMintz, Yuval u32 resp = 0, param = 0; 16996927e826SMintz, Yuval int rc; 17006927e826SMintz, Yuval 17016927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 17026927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 17036927e826SMintz, Yuval if (rc) 17046927e826SMintz, Yuval return rc; 17056927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 17066927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 17076927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 17086927e826SMintz, Yuval resp); 17096927e826SMintz, Yuval return -EINVAL; 17106927e826SMintz, Yuval } 17116927e826SMintz, Yuval 17126927e826SMintz, Yuval switch (param) { 17136927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 17146927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 17156927e826SMintz, Yuval break; 17166927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 17176927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 17186927e826SMintz, Yuval break; 17196927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 1720e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 1721e0a8f9deSMichal Kalderon break; 1722e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 1723e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 1724e0a8f9deSMichal Kalderon break; 17256927e826SMintz, Yuval default: 17266927e826SMintz, Yuval DP_NOTICE(p_hwfn, 17276927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 17286927e826SMintz, Yuval param); 17296927e826SMintz, Yuval return -EINVAL; 17306927e826SMintz, Yuval } 17316927e826SMintz, Yuval 17326927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 17336927e826SMintz, Yuval NETIF_MSG_IFUP, 17346927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 17356927e826SMintz, Yuval (u32) *p_proto, resp, param); 17366927e826SMintz, Yuval return 0; 17376927e826SMintz, Yuval } 17386927e826SMintz, Yuval 1739fe56b9e6SYuval Mintz static int 1740fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1741fe56b9e6SYuval Mintz struct public_func *p_info, 17426927e826SMintz, Yuval struct qed_ptt *p_ptt, 1743fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 1744fe56b9e6SYuval Mintz { 1745fe56b9e6SYuval Mintz int rc = 0; 1746fe56b9e6SYuval Mintz 1747fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1748fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 17491fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 17501fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 17511fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 17526927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1753fe56b9e6SYuval Mintz break; 1754c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 1755c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 1756c5ac9319SYuval Mintz break; 17571e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 17581e128c81SArun Easi *p_proto = QED_PCI_FCOE; 17591e128c81SArun Easi break; 1760c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 1761c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 17626927e826SMintz, Yuval /* Fallthrough */ 1763fe56b9e6SYuval Mintz default: 1764fe56b9e6SYuval Mintz rc = -EINVAL; 1765fe56b9e6SYuval Mintz } 1766fe56b9e6SYuval Mintz 1767fe56b9e6SYuval Mintz return rc; 1768fe56b9e6SYuval Mintz } 1769fe56b9e6SYuval Mintz 1770fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1771fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1772fe56b9e6SYuval Mintz { 1773fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 1774fe56b9e6SYuval Mintz struct public_func shmem_info; 1775fe56b9e6SYuval Mintz 17761a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1777fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 1778fe56b9e6SYuval Mintz 1779fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 1780fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1781fe56b9e6SYuval Mintz 17826927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 17836927e826SMintz, Yuval &info->protocol)) { 1784fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 1785fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1786fe56b9e6SYuval Mintz return -EINVAL; 1787fe56b9e6SYuval Mintz } 1788fe56b9e6SYuval Mintz 17894b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1790fe56b9e6SYuval Mintz 1791fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 1792fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1793fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 1794fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1795fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1796fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1797fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 179814d39648SMintz, Yuval 179914d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 180014d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1801fe56b9e6SYuval Mintz } else { 1802fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1803fe56b9e6SYuval Mintz } 1804fe56b9e6SYuval Mintz 180557796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 180657796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 180757796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 180857796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 1809fe56b9e6SYuval Mintz 1810fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1811fe56b9e6SYuval Mintz 18120fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 18130fefbfbaSSudarsana Kalluru 181414d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 181514d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 181614d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 181714d39648SMintz, Yuval u32 resp = 0, param = 0; 181814d39648SMintz, Yuval int rc; 181914d39648SMintz, Yuval 182014d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 182114d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 182214d39648SMintz, Yuval if (rc) 182314d39648SMintz, Yuval return rc; 182414d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 182514d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 182614d39648SMintz, Yuval } 182714d39648SMintz, Yuval 1828fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 182914d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1830fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 1831fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 1832fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 1833fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 183414d39648SMintz, Yuval info->wwn_port, info->wwn_node, 183514d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1836fe56b9e6SYuval Mintz 1837fe56b9e6SYuval Mintz return 0; 1838fe56b9e6SYuval Mintz } 1839fe56b9e6SYuval Mintz 1840cc875c2eSYuval Mintz struct qed_mcp_link_params 1841cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1842cc875c2eSYuval Mintz { 1843cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1844cc875c2eSYuval Mintz return NULL; 1845cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 1846cc875c2eSYuval Mintz } 1847cc875c2eSYuval Mintz 1848cc875c2eSYuval Mintz struct qed_mcp_link_state 1849cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1850cc875c2eSYuval Mintz { 1851cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1852cc875c2eSYuval Mintz return NULL; 1853cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 1854cc875c2eSYuval Mintz } 1855cc875c2eSYuval Mintz 1856cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 1857cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1858cc875c2eSYuval Mintz { 1859cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1860cc875c2eSYuval Mintz return NULL; 1861cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 1862cc875c2eSYuval Mintz } 1863cc875c2eSYuval Mintz 18641a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1865fe56b9e6SYuval Mintz { 1866fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 1867fe56b9e6SYuval Mintz int rc; 1868fe56b9e6SYuval Mintz 1869fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 18701a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1871fe56b9e6SYuval Mintz 1872fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 18738f60bafeSYuval Mintz msleep(1020); 1874fe56b9e6SYuval Mintz 1875fe56b9e6SYuval Mintz return rc; 1876fe56b9e6SYuval Mintz } 1877fe56b9e6SYuval Mintz 1878cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 18791a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 1880cee4d264SManish Chopra { 1881cee4d264SManish Chopra u32 flash_size; 1882cee4d264SManish Chopra 18831408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 18841408cc1fSYuval Mintz return -EINVAL; 18851408cc1fSYuval Mintz 1886cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1887cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1888cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1889cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1890cee4d264SManish Chopra 1891cee4d264SManish Chopra *p_flash_size = flash_size; 1892cee4d264SManish Chopra 1893cee4d264SManish Chopra return 0; 1894cee4d264SManish Chopra } 1895cee4d264SManish Chopra 189688072fd4SMintz, Yuval static int 189788072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 18981408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 18991408cc1fSYuval Mintz { 19001408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 19011408cc1fSYuval Mintz int rc; 19021408cc1fSYuval Mintz 19031408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 19041408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 19051408cc1fSYuval Mintz return 0; 19061408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 19071408cc1fSYuval Mintz 19081408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 19091408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 19101408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 19111408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 19121408cc1fSYuval Mintz 19131408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 19141408cc1fSYuval Mintz &resp, &rc_param); 19151408cc1fSYuval Mintz 19161408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 19171408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 19181408cc1fSYuval Mintz rc = -EINVAL; 19191408cc1fSYuval Mintz } else { 19201408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 19211408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 19221408cc1fSYuval Mintz num, vf_id); 19231408cc1fSYuval Mintz } 19241408cc1fSYuval Mintz 19251408cc1fSYuval Mintz return rc; 19261408cc1fSYuval Mintz } 19271408cc1fSYuval Mintz 192888072fd4SMintz, Yuval static int 192988072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 193088072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 193188072fd4SMintz, Yuval { 193288072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 193388072fd4SMintz, Yuval int rc; 193488072fd4SMintz, Yuval 193588072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 193688072fd4SMintz, Yuval param, &resp, &rc_param); 193788072fd4SMintz, Yuval 193888072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 193988072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 194088072fd4SMintz, Yuval rc = -EINVAL; 194188072fd4SMintz, Yuval } else { 194288072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 194388072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 194488072fd4SMintz, Yuval } 194588072fd4SMintz, Yuval 194688072fd4SMintz, Yuval return rc; 194788072fd4SMintz, Yuval } 194888072fd4SMintz, Yuval 194988072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 195088072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 195188072fd4SMintz, Yuval { 195288072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 195388072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 195488072fd4SMintz, Yuval else 195588072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 195688072fd4SMintz, Yuval } 195788072fd4SMintz, Yuval 1958fe56b9e6SYuval Mintz int 1959fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 1960fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1961fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 1962fe56b9e6SYuval Mintz { 19635529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 19642f67af8cSTomer Tayar struct drv_version_stc drv_version; 19655529bad9STomer Tayar __be32 val; 19665529bad9STomer Tayar u32 i; 19675529bad9STomer Tayar int rc; 1968fe56b9e6SYuval Mintz 19692f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 19702f67af8cSTomer Tayar drv_version.version = p_ver->version; 197167a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 197267a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 19732f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 1974fe56b9e6SYuval Mintz } 1975fe56b9e6SYuval Mintz 19765529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 19775529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 19782f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 19792f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 19805529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 19815529bad9STomer Tayar if (rc) 1982fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1983fe56b9e6SYuval Mintz 19845529bad9STomer Tayar return rc; 1985fe56b9e6SYuval Mintz } 198691420b83SSudarsana Kalluru 19874102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 19884102426fSTomer Tayar { 19894102426fSTomer Tayar u32 resp = 0, param = 0; 19904102426fSTomer Tayar int rc; 19914102426fSTomer Tayar 19924102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 19934102426fSTomer Tayar ¶m); 19944102426fSTomer Tayar if (rc) 19954102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 19964102426fSTomer Tayar 19974102426fSTomer Tayar return rc; 19984102426fSTomer Tayar } 19994102426fSTomer Tayar 20004102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 20014102426fSTomer Tayar { 20024102426fSTomer Tayar u32 value, cpu_mode; 20034102426fSTomer Tayar 20044102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 20054102426fSTomer Tayar 20064102426fSTomer Tayar value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 20074102426fSTomer Tayar value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 20084102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 20094102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 20104102426fSTomer Tayar 20114102426fSTomer Tayar return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 20124102426fSTomer Tayar } 20134102426fSTomer Tayar 20140fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 20150fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 20160fefbfbaSSudarsana Kalluru enum qed_ov_client client) 20170fefbfbaSSudarsana Kalluru { 20180fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 20190fefbfbaSSudarsana Kalluru u32 drv_mb_param; 20200fefbfbaSSudarsana Kalluru int rc; 20210fefbfbaSSudarsana Kalluru 20220fefbfbaSSudarsana Kalluru switch (client) { 20230fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 20240fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 20250fefbfbaSSudarsana Kalluru break; 20260fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 20270fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 20280fefbfbaSSudarsana Kalluru break; 20290fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 20300fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 20310fefbfbaSSudarsana Kalluru break; 20320fefbfbaSSudarsana Kalluru default: 20330fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 20340fefbfbaSSudarsana Kalluru return -EINVAL; 20350fefbfbaSSudarsana Kalluru } 20360fefbfbaSSudarsana Kalluru 20370fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 20380fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 20390fefbfbaSSudarsana Kalluru if (rc) 20400fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 20410fefbfbaSSudarsana Kalluru 20420fefbfbaSSudarsana Kalluru return rc; 20430fefbfbaSSudarsana Kalluru } 20440fefbfbaSSudarsana Kalluru 20450fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 20460fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 20470fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 20480fefbfbaSSudarsana Kalluru { 20490fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 20500fefbfbaSSudarsana Kalluru u32 drv_mb_param; 20510fefbfbaSSudarsana Kalluru int rc; 20520fefbfbaSSudarsana Kalluru 20530fefbfbaSSudarsana Kalluru switch (drv_state) { 20540fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 20550fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 20560fefbfbaSSudarsana Kalluru break; 20570fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 20580fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 20590fefbfbaSSudarsana Kalluru break; 20600fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 20610fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 20620fefbfbaSSudarsana Kalluru break; 20630fefbfbaSSudarsana Kalluru default: 20640fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 20650fefbfbaSSudarsana Kalluru return -EINVAL; 20660fefbfbaSSudarsana Kalluru } 20670fefbfbaSSudarsana Kalluru 20680fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 20690fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 20700fefbfbaSSudarsana Kalluru if (rc) 20710fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 20720fefbfbaSSudarsana Kalluru 20730fefbfbaSSudarsana Kalluru return rc; 20740fefbfbaSSudarsana Kalluru } 20750fefbfbaSSudarsana Kalluru 20760fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 20770fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 20780fefbfbaSSudarsana Kalluru { 20790fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 20800fefbfbaSSudarsana Kalluru u32 drv_mb_param; 20810fefbfbaSSudarsana Kalluru int rc; 20820fefbfbaSSudarsana Kalluru 20830fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 20840fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 20850fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 20860fefbfbaSSudarsana Kalluru if (rc) 20870fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 20880fefbfbaSSudarsana Kalluru 20890fefbfbaSSudarsana Kalluru return rc; 20900fefbfbaSSudarsana Kalluru } 20910fefbfbaSSudarsana Kalluru 20920fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 20930fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 20940fefbfbaSSudarsana Kalluru { 20950fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 209617991002SMintz, Yuval u32 mfw_mac[2]; 20970fefbfbaSSudarsana Kalluru int rc; 20980fefbfbaSSudarsana Kalluru 20990fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 21000fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 21010fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 21020fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 21030fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 21042f67af8cSTomer Tayar 210517991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 210617991002SMintz, Yuval * in 32-bit granularity. 210717991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 210817991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 210917991002SMintz, Yuval */ 211017991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 211117991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 211217991002SMintz, Yuval 211317991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 211417991002SMintz, Yuval mb_params.data_src_size = 8; 21150fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 21160fefbfbaSSudarsana Kalluru if (rc) 21170fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 21180fefbfbaSSudarsana Kalluru 211914d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 212014d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 212114d39648SMintz, Yuval 21220fefbfbaSSudarsana Kalluru return rc; 21230fefbfbaSSudarsana Kalluru } 21240fefbfbaSSudarsana Kalluru 21250fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 21260fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 21270fefbfbaSSudarsana Kalluru { 21280fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 21290fefbfbaSSudarsana Kalluru u32 drv_mb_param; 21300fefbfbaSSudarsana Kalluru int rc; 21310fefbfbaSSudarsana Kalluru 213214d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 213314d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 213414d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 213514d39648SMintz, Yuval return -EINVAL; 213614d39648SMintz, Yuval } 213714d39648SMintz, Yuval 21380fefbfbaSSudarsana Kalluru switch (wol) { 21390fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 21400fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 21410fefbfbaSSudarsana Kalluru break; 21420fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 21430fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 21440fefbfbaSSudarsana Kalluru break; 21450fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 21460fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 21470fefbfbaSSudarsana Kalluru break; 21480fefbfbaSSudarsana Kalluru default: 21490fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 21500fefbfbaSSudarsana Kalluru return -EINVAL; 21510fefbfbaSSudarsana Kalluru } 21520fefbfbaSSudarsana Kalluru 21530fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 21540fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 21550fefbfbaSSudarsana Kalluru if (rc) 21560fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 21570fefbfbaSSudarsana Kalluru 215814d39648SMintz, Yuval /* Store the WoL update for a future unload */ 215914d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 216014d39648SMintz, Yuval 21610fefbfbaSSudarsana Kalluru return rc; 21620fefbfbaSSudarsana Kalluru } 21630fefbfbaSSudarsana Kalluru 21640fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 21650fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 21660fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 21670fefbfbaSSudarsana Kalluru { 21680fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 21690fefbfbaSSudarsana Kalluru u32 drv_mb_param; 21700fefbfbaSSudarsana Kalluru int rc; 21710fefbfbaSSudarsana Kalluru 21720fefbfbaSSudarsana Kalluru switch (eswitch) { 21730fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 21740fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 21750fefbfbaSSudarsana Kalluru break; 21760fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 21770fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 21780fefbfbaSSudarsana Kalluru break; 21790fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 21800fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 21810fefbfbaSSudarsana Kalluru break; 21820fefbfbaSSudarsana Kalluru default: 21830fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 21840fefbfbaSSudarsana Kalluru return -EINVAL; 21850fefbfbaSSudarsana Kalluru } 21860fefbfbaSSudarsana Kalluru 21870fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 21880fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 21890fefbfbaSSudarsana Kalluru if (rc) 21900fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 21910fefbfbaSSudarsana Kalluru 21920fefbfbaSSudarsana Kalluru return rc; 21930fefbfbaSSudarsana Kalluru } 21940fefbfbaSSudarsana Kalluru 21951a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 21961a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 219791420b83SSudarsana Kalluru { 219891420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 219991420b83SSudarsana Kalluru int rc; 220091420b83SSudarsana Kalluru 220191420b83SSudarsana Kalluru switch (mode) { 220291420b83SSudarsana Kalluru case QED_LED_MODE_ON: 220391420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 220491420b83SSudarsana Kalluru break; 220591420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 220691420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 220791420b83SSudarsana Kalluru break; 220891420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 220991420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 221091420b83SSudarsana Kalluru break; 221191420b83SSudarsana Kalluru default: 221291420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 221391420b83SSudarsana Kalluru return -EINVAL; 221491420b83SSudarsana Kalluru } 221591420b83SSudarsana Kalluru 221691420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 221791420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 221891420b83SSudarsana Kalluru 221991420b83SSudarsana Kalluru return rc; 222091420b83SSudarsana Kalluru } 222103dc76caSSudarsana Reddy Kalluru 22224102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 22234102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 22244102426fSTomer Tayar { 22254102426fSTomer Tayar u32 resp = 0, param = 0; 22264102426fSTomer Tayar int rc; 22274102426fSTomer Tayar 22284102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 22294102426fSTomer Tayar mask_parities, &resp, ¶m); 22304102426fSTomer Tayar 22314102426fSTomer Tayar if (rc) { 22324102426fSTomer Tayar DP_ERR(p_hwfn, 22334102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 22344102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 22354102426fSTomer Tayar DP_ERR(p_hwfn, 22364102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 22374102426fSTomer Tayar rc = -EINVAL; 22384102426fSTomer Tayar } 22394102426fSTomer Tayar 22404102426fSTomer Tayar return rc; 22414102426fSTomer Tayar } 22424102426fSTomer Tayar 22437a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 22447a4b21b7SMintz, Yuval { 22457a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 22467a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 22477a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 22487a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 22497a4b21b7SMintz, Yuval int rc = 0; 22507a4b21b7SMintz, Yuval 22517a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 22527a4b21b7SMintz, Yuval if (!p_ptt) 22537a4b21b7SMintz, Yuval return -EBUSY; 22547a4b21b7SMintz, Yuval 22557a4b21b7SMintz, Yuval while (bytes_left > 0) { 22567a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 22577a4b21b7SMintz, Yuval 22587a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 22597a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 22607a4b21b7SMintz, Yuval addr + offset + 22617a4b21b7SMintz, Yuval (bytes_to_copy << 2262da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 22637a4b21b7SMintz, Yuval &resp, &resp_param, 22647a4b21b7SMintz, Yuval &read_len, 22657a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 22667a4b21b7SMintz, Yuval 22677a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 22687a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 22697a4b21b7SMintz, Yuval break; 22707a4b21b7SMintz, Yuval } 22717a4b21b7SMintz, Yuval 22727a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 22737a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 22747a4b21b7SMintz, Yuval */ 22757a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 22767a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 22777a4b21b7SMintz, Yuval usleep_range(1000, 2000); 22787a4b21b7SMintz, Yuval 22797a4b21b7SMintz, Yuval offset += read_len; 22807a4b21b7SMintz, Yuval bytes_left -= read_len; 22817a4b21b7SMintz, Yuval } 22827a4b21b7SMintz, Yuval 22837a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 22847a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 22857a4b21b7SMintz, Yuval 22867a4b21b7SMintz, Yuval return rc; 22877a4b21b7SMintz, Yuval } 22887a4b21b7SMintz, Yuval 228962e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 229062e4d438SSudarsana Reddy Kalluru { 229162e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 229262e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 229362e4d438SSudarsana Reddy Kalluru 229462e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 229562e4d438SSudarsana Reddy Kalluru if (!p_ptt) 229662e4d438SSudarsana Reddy Kalluru return -EBUSY; 229762e4d438SSudarsana Reddy Kalluru 229862e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 229962e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 230062e4d438SSudarsana Reddy Kalluru 230162e4d438SSudarsana Reddy Kalluru return 0; 230262e4d438SSudarsana Reddy Kalluru } 230362e4d438SSudarsana Reddy Kalluru 230462e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr) 230562e4d438SSudarsana Reddy Kalluru { 230662e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 230762e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 230862e4d438SSudarsana Reddy Kalluru u32 resp, param; 230962e4d438SSudarsana Reddy Kalluru int rc; 231062e4d438SSudarsana Reddy Kalluru 231162e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 231262e4d438SSudarsana Reddy Kalluru if (!p_ptt) 231362e4d438SSudarsana Reddy Kalluru return -EBUSY; 231462e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr, 231562e4d438SSudarsana Reddy Kalluru &resp, ¶m); 231662e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 231762e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 231862e4d438SSudarsana Reddy Kalluru 231962e4d438SSudarsana Reddy Kalluru return rc; 232062e4d438SSudarsana Reddy Kalluru } 232162e4d438SSudarsana Reddy Kalluru 232262e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 232362e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 232462e4d438SSudarsana Reddy Kalluru { 232562e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 232662e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 232762e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 232862e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 232962e4d438SSudarsana Reddy Kalluru 233062e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 233162e4d438SSudarsana Reddy Kalluru if (!p_ptt) 233262e4d438SSudarsana Reddy Kalluru return -EBUSY; 233362e4d438SSudarsana Reddy Kalluru 233462e4d438SSudarsana Reddy Kalluru switch (cmd) { 233562e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 233662e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 233762e4d438SSudarsana Reddy Kalluru break; 233862e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 233962e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 234062e4d438SSudarsana Reddy Kalluru break; 234162e4d438SSudarsana Reddy Kalluru default: 234262e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 234362e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 234462e4d438SSudarsana Reddy Kalluru goto out; 234562e4d438SSudarsana Reddy Kalluru } 234662e4d438SSudarsana Reddy Kalluru 234762e4d438SSudarsana Reddy Kalluru while (buf_idx < len) { 234862e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 234962e4d438SSudarsana Reddy Kalluru nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) | 235062e4d438SSudarsana Reddy Kalluru addr) + buf_idx; 235162e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 235262e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 235362e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 235462e4d438SSudarsana Reddy Kalluru if (rc) { 235562e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 235662e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 235762e4d438SSudarsana Reddy Kalluru break; 235862e4d438SSudarsana Reddy Kalluru } 235962e4d438SSudarsana Reddy Kalluru 236062e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 236162e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 236262e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 236362e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 236462e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 236562e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 236662e4d438SSudarsana Reddy Kalluru break; 236762e4d438SSudarsana Reddy Kalluru } 236862e4d438SSudarsana Reddy Kalluru 236962e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 237062e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 237162e4d438SSudarsana Reddy Kalluru */ 237262e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 237362e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 237462e4d438SSudarsana Reddy Kalluru 237562e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 237662e4d438SSudarsana Reddy Kalluru } 237762e4d438SSudarsana Reddy Kalluru 237862e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 237962e4d438SSudarsana Reddy Kalluru out: 238062e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 238162e4d438SSudarsana Reddy Kalluru 238262e4d438SSudarsana Reddy Kalluru return rc; 238362e4d438SSudarsana Reddy Kalluru } 238462e4d438SSudarsana Reddy Kalluru 238503dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 238603dc76caSSudarsana Reddy Kalluru { 238703dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 238803dc76caSSudarsana Reddy Kalluru int rc = 0; 238903dc76caSSudarsana Reddy Kalluru 239003dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 239103dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 239203dc76caSSudarsana Reddy Kalluru 239303dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 239403dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 239503dc76caSSudarsana Reddy Kalluru 239603dc76caSSudarsana Reddy Kalluru if (rc) 239703dc76caSSudarsana Reddy Kalluru return rc; 239803dc76caSSudarsana Reddy Kalluru 239903dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 240003dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 240103dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 240203dc76caSSudarsana Reddy Kalluru 240303dc76caSSudarsana Reddy Kalluru return rc; 240403dc76caSSudarsana Reddy Kalluru } 240503dc76caSSudarsana Reddy Kalluru 240603dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 240703dc76caSSudarsana Reddy Kalluru { 240803dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 240903dc76caSSudarsana Reddy Kalluru int rc = 0; 241003dc76caSSudarsana Reddy Kalluru 241103dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 241203dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 241303dc76caSSudarsana Reddy Kalluru 241403dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 241503dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 241603dc76caSSudarsana Reddy Kalluru 241703dc76caSSudarsana Reddy Kalluru if (rc) 241803dc76caSSudarsana Reddy Kalluru return rc; 241903dc76caSSudarsana Reddy Kalluru 242003dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 242103dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 242203dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 242303dc76caSSudarsana Reddy Kalluru 242403dc76caSSudarsana Reddy Kalluru return rc; 242503dc76caSSudarsana Reddy Kalluru } 24267a4b21b7SMintz, Yuval 242743645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 24287a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 24297a4b21b7SMintz, Yuval u32 *num_images) 24307a4b21b7SMintz, Yuval { 24317a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 24327a4b21b7SMintz, Yuval int rc = 0; 24337a4b21b7SMintz, Yuval 24347a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 24357a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 24367a4b21b7SMintz, Yuval 24377a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 24387a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 24397a4b21b7SMintz, Yuval if (rc) 24407a4b21b7SMintz, Yuval return rc; 24417a4b21b7SMintz, Yuval 24427a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 24437a4b21b7SMintz, Yuval rc = -EINVAL; 24447a4b21b7SMintz, Yuval 24457a4b21b7SMintz, Yuval return rc; 24467a4b21b7SMintz, Yuval } 24477a4b21b7SMintz, Yuval 244843645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 24497a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 24507a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 24517a4b21b7SMintz, Yuval u32 image_index) 24527a4b21b7SMintz, Yuval { 24537a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 24547a4b21b7SMintz, Yuval int rc; 24557a4b21b7SMintz, Yuval 24567a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 24577a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 24587a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 24597a4b21b7SMintz, Yuval 24607a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 24617a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 24627a4b21b7SMintz, Yuval &resp, &resp_param, 24637a4b21b7SMintz, Yuval &buf_size, 24647a4b21b7SMintz, Yuval (u32 *)p_image_att); 24657a4b21b7SMintz, Yuval if (rc) 24667a4b21b7SMintz, Yuval return rc; 24677a4b21b7SMintz, Yuval 24687a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 24697a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 24707a4b21b7SMintz, Yuval rc = -EINVAL; 24717a4b21b7SMintz, Yuval 24727a4b21b7SMintz, Yuval return rc; 24737a4b21b7SMintz, Yuval } 24742edbff8dSTomer Tayar 247543645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 247643645ce0SSudarsana Reddy Kalluru { 247743645ce0SSudarsana Reddy Kalluru struct qed_nvm_image_info *nvm_info = &p_hwfn->nvm_info; 247843645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 247943645ce0SSudarsana Reddy Kalluru int rc; 248043645ce0SSudarsana Reddy Kalluru u32 i; 248143645ce0SSudarsana Reddy Kalluru 248243645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 248343645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 248443645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 248543645ce0SSudarsana Reddy Kalluru return -EBUSY; 248643645ce0SSudarsana Reddy Kalluru } 248743645ce0SSudarsana Reddy Kalluru 248843645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 248943645ce0SSudarsana Reddy Kalluru nvm_info->num_images = 0; 249043645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 249143645ce0SSudarsana Reddy Kalluru p_ptt, &nvm_info->num_images); 249243645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 249343645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 249443645ce0SSudarsana Reddy Kalluru goto out; 249543645ce0SSudarsana Reddy Kalluru } else if (rc || !nvm_info->num_images) { 249643645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 249743645ce0SSudarsana Reddy Kalluru goto err0; 249843645ce0SSudarsana Reddy Kalluru } 249943645ce0SSudarsana Reddy Kalluru 250043645ce0SSudarsana Reddy Kalluru nvm_info->image_att = kmalloc(nvm_info->num_images * 250143645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 250243645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 250343645ce0SSudarsana Reddy Kalluru if (!nvm_info->image_att) { 250443645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 250543645ce0SSudarsana Reddy Kalluru goto err0; 250643645ce0SSudarsana Reddy Kalluru } 250743645ce0SSudarsana Reddy Kalluru 250843645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 250943645ce0SSudarsana Reddy Kalluru for (i = 0; i < nvm_info->num_images; i++) { 251043645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 251143645ce0SSudarsana Reddy Kalluru &nvm_info->image_att[i], i); 251243645ce0SSudarsana Reddy Kalluru if (rc) { 251343645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 251443645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 251543645ce0SSudarsana Reddy Kalluru goto err1; 251643645ce0SSudarsana Reddy Kalluru } 251743645ce0SSudarsana Reddy Kalluru 251843645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 251943645ce0SSudarsana Reddy Kalluru nvm_info->image_att[i].len); 252043645ce0SSudarsana Reddy Kalluru } 252143645ce0SSudarsana Reddy Kalluru out: 252243645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 252343645ce0SSudarsana Reddy Kalluru return 0; 252443645ce0SSudarsana Reddy Kalluru 252543645ce0SSudarsana Reddy Kalluru err1: 252643645ce0SSudarsana Reddy Kalluru kfree(nvm_info->image_att); 252743645ce0SSudarsana Reddy Kalluru err0: 252843645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 252943645ce0SSudarsana Reddy Kalluru return rc; 253043645ce0SSudarsana Reddy Kalluru } 253143645ce0SSudarsana Reddy Kalluru 25321ac4329aSDenis Bolotin int 253320675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 253420675b37SMintz, Yuval enum qed_nvm_images image_id, 253520675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 253620675b37SMintz, Yuval { 253720675b37SMintz, Yuval enum nvm_image_type type; 253843645ce0SSudarsana Reddy Kalluru u32 i; 253920675b37SMintz, Yuval 254020675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 254120675b37SMintz, Yuval switch (image_id) { 254220675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 254320675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 254420675b37SMintz, Yuval break; 254520675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 254620675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 254720675b37SMintz, Yuval break; 25481ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 25491ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 25501ac4329aSDenis Bolotin break; 25511ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 25521ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 25531ac4329aSDenis Bolotin break; 25541ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 25551ac4329aSDenis Bolotin type = NVM_TYPE_META; 25561ac4329aSDenis Bolotin break; 255720675b37SMintz, Yuval default: 255820675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 255920675b37SMintz, Yuval image_id); 256020675b37SMintz, Yuval return -EINVAL; 256120675b37SMintz, Yuval } 256220675b37SMintz, Yuval 256343645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 256443645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 256520675b37SMintz, Yuval break; 256643645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 256720675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 256820675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 256920675b37SMintz, Yuval image_id); 257043645ce0SSudarsana Reddy Kalluru return -ENOENT; 257120675b37SMintz, Yuval } 257220675b37SMintz, Yuval 257343645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 257443645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 257520675b37SMintz, Yuval 257620675b37SMintz, Yuval return 0; 257720675b37SMintz, Yuval } 257820675b37SMintz, Yuval 257920675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 258020675b37SMintz, Yuval enum qed_nvm_images image_id, 258120675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 258220675b37SMintz, Yuval { 258320675b37SMintz, Yuval struct qed_nvm_image_att image_att; 258420675b37SMintz, Yuval int rc; 258520675b37SMintz, Yuval 258620675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 258720675b37SMintz, Yuval 2588b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 258920675b37SMintz, Yuval if (rc) 259020675b37SMintz, Yuval return rc; 259120675b37SMintz, Yuval 259220675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 259320675b37SMintz, Yuval if (image_att.length <= 4) { 259420675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 259520675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 259620675b37SMintz, Yuval image_id, image_att.length); 259720675b37SMintz, Yuval return -EINVAL; 259820675b37SMintz, Yuval } 259920675b37SMintz, Yuval 260020675b37SMintz, Yuval if (image_att.length > buffer_len) { 260120675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 260220675b37SMintz, Yuval QED_MSG_STORAGE, 260320675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 260420675b37SMintz, Yuval image_id, image_att.length, buffer_len); 260520675b37SMintz, Yuval return -ENOMEM; 260620675b37SMintz, Yuval } 260720675b37SMintz, Yuval 260820675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 260920675b37SMintz, Yuval p_buffer, image_att.length); 261020675b37SMintz, Yuval } 261120675b37SMintz, Yuval 26129c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 26139c8517c4STomer Tayar { 26149c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 26159c8517c4STomer Tayar 26169c8517c4STomer Tayar switch (res_id) { 26179c8517c4STomer Tayar case QED_SB: 26189c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 26199c8517c4STomer Tayar break; 26209c8517c4STomer Tayar case QED_L2_QUEUE: 26219c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 26229c8517c4STomer Tayar break; 26239c8517c4STomer Tayar case QED_VPORT: 26249c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 26259c8517c4STomer Tayar break; 26269c8517c4STomer Tayar case QED_RSS_ENG: 26279c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 26289c8517c4STomer Tayar break; 26299c8517c4STomer Tayar case QED_PQ: 26309c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 26319c8517c4STomer Tayar break; 26329c8517c4STomer Tayar case QED_RL: 26339c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 26349c8517c4STomer Tayar break; 26359c8517c4STomer Tayar case QED_MAC: 26369c8517c4STomer Tayar case QED_VLAN: 26379c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 26389c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 26399c8517c4STomer Tayar break; 26409c8517c4STomer Tayar case QED_ILT: 26419c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 26429c8517c4STomer Tayar break; 26439c8517c4STomer Tayar case QED_LL2_QUEUE: 26449c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 26459c8517c4STomer Tayar break; 26469c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 26479c8517c4STomer Tayar case QED_CMDQS_CQS: 26489c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 26499c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 26509c8517c4STomer Tayar break; 26519c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 26529c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 26539c8517c4STomer Tayar break; 26549c8517c4STomer Tayar case QED_BDQ: 26559c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 26569c8517c4STomer Tayar break; 26579c8517c4STomer Tayar default: 26589c8517c4STomer Tayar break; 26599c8517c4STomer Tayar } 26609c8517c4STomer Tayar 26619c8517c4STomer Tayar return mfw_res_id; 26629c8517c4STomer Tayar } 26639c8517c4STomer Tayar 26649c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 26652edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 26662edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 26672edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 26682edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 26692edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 26702edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 26719c8517c4STomer Tayar 26729c8517c4STomer Tayar struct qed_resc_alloc_in_params { 26739c8517c4STomer Tayar u32 cmd; 26749c8517c4STomer Tayar enum qed_resources res_id; 26759c8517c4STomer Tayar u32 resc_max_val; 26769c8517c4STomer Tayar }; 26779c8517c4STomer Tayar 26789c8517c4STomer Tayar struct qed_resc_alloc_out_params { 26799c8517c4STomer Tayar u32 mcp_resp; 26809c8517c4STomer Tayar u32 mcp_param; 26819c8517c4STomer Tayar u32 resc_num; 26829c8517c4STomer Tayar u32 resc_start; 26839c8517c4STomer Tayar u32 vf_resc_num; 26849c8517c4STomer Tayar u32 vf_resc_start; 26859c8517c4STomer Tayar u32 flags; 26869c8517c4STomer Tayar }; 26879c8517c4STomer Tayar 26889c8517c4STomer Tayar static int 26899c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 26902edbff8dSTomer Tayar struct qed_ptt *p_ptt, 26919c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 26929c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 26932edbff8dSTomer Tayar { 26942edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 26959c8517c4STomer Tayar struct resource_info mfw_resc_info; 26962edbff8dSTomer Tayar int rc; 26972edbff8dSTomer Tayar 26989c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 2699bb480242SMintz, Yuval 27009c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 27019c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 27029c8517c4STomer Tayar DP_ERR(p_hwfn, 27039c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 27049c8517c4STomer Tayar p_in_params->res_id, 27059c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 27069c8517c4STomer Tayar return -EINVAL; 27079c8517c4STomer Tayar } 27089c8517c4STomer Tayar 27099c8517c4STomer Tayar switch (p_in_params->cmd) { 27109c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 27119c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 27129c8517c4STomer Tayar /* Fallthrough */ 27139c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 27149c8517c4STomer Tayar break; 27159c8517c4STomer Tayar default: 27169c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 27179c8517c4STomer Tayar p_in_params->cmd); 27189c8517c4STomer Tayar return -EINVAL; 27199c8517c4STomer Tayar } 27209c8517c4STomer Tayar 27219c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 27229c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 27239c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 27249c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 27259c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 27269c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 27279c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 27289c8517c4STomer Tayar 27299c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 27309c8517c4STomer Tayar QED_MSG_SP, 27319c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 27329c8517c4STomer Tayar p_in_params->cmd, 27339c8517c4STomer Tayar p_in_params->res_id, 27349c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 27359c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 27369c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 27379c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 27389c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 27399c8517c4STomer Tayar p_in_params->resc_max_val); 27409c8517c4STomer Tayar 27412edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 27422edbff8dSTomer Tayar if (rc) 27432edbff8dSTomer Tayar return rc; 27442edbff8dSTomer Tayar 27459c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 27469c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 27479c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 27489c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 27499c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 27509c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 27519c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 27522edbff8dSTomer Tayar 27532edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 27542edbff8dSTomer Tayar QED_MSG_SP, 27559c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 27569c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 27579c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 27589c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 27599c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 27609c8517c4STomer Tayar p_out_params->resc_num, 27619c8517c4STomer Tayar p_out_params->resc_start, 27629c8517c4STomer Tayar p_out_params->vf_resc_num, 27639c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 27649c8517c4STomer Tayar 27659c8517c4STomer Tayar return 0; 27669c8517c4STomer Tayar } 27679c8517c4STomer Tayar 27689c8517c4STomer Tayar int 27699c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 27709c8517c4STomer Tayar struct qed_ptt *p_ptt, 27719c8517c4STomer Tayar enum qed_resources res_id, 27729c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 27739c8517c4STomer Tayar { 27749c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 27759c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 27769c8517c4STomer Tayar int rc; 27779c8517c4STomer Tayar 27789c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 27799c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 27809c8517c4STomer Tayar in_params.res_id = res_id; 27819c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 27829c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 27839c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 27849c8517c4STomer Tayar &out_params); 27859c8517c4STomer Tayar if (rc) 27869c8517c4STomer Tayar return rc; 27879c8517c4STomer Tayar 27889c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 27899c8517c4STomer Tayar 27909c8517c4STomer Tayar return 0; 27919c8517c4STomer Tayar } 27929c8517c4STomer Tayar 27939c8517c4STomer Tayar int 27949c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 27959c8517c4STomer Tayar struct qed_ptt *p_ptt, 27969c8517c4STomer Tayar enum qed_resources res_id, 27979c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 27989c8517c4STomer Tayar { 27999c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 28009c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 28019c8517c4STomer Tayar int rc; 28029c8517c4STomer Tayar 28039c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 28049c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 28059c8517c4STomer Tayar in_params.res_id = res_id; 28069c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 28079c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 28089c8517c4STomer Tayar &out_params); 28099c8517c4STomer Tayar if (rc) 28109c8517c4STomer Tayar return rc; 28119c8517c4STomer Tayar 28129c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 28139c8517c4STomer Tayar 28149c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 28159c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 28169c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 28179c8517c4STomer Tayar } 28182edbff8dSTomer Tayar 28192edbff8dSTomer Tayar return 0; 28202edbff8dSTomer Tayar } 282118a69e36SMintz, Yuval 282218a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 282318a69e36SMintz, Yuval { 282418a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 282518a69e36SMintz, Yuval 282618a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 282718a69e36SMintz, Yuval &mcp_resp, &mcp_param); 282818a69e36SMintz, Yuval } 282995691c9cSTomer Tayar 283095691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 283195691c9cSTomer Tayar struct qed_ptt *p_ptt, 283295691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 283395691c9cSTomer Tayar { 283495691c9cSTomer Tayar int rc; 283595691c9cSTomer Tayar 283695691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 283795691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 283895691c9cSTomer Tayar if (rc) 283995691c9cSTomer Tayar return rc; 284095691c9cSTomer Tayar 284195691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 284295691c9cSTomer Tayar DP_INFO(p_hwfn, 284395691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 284495691c9cSTomer Tayar return -EINVAL; 284595691c9cSTomer Tayar } 284695691c9cSTomer Tayar 284795691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 284895691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 284995691c9cSTomer Tayar 285095691c9cSTomer Tayar DP_NOTICE(p_hwfn, 285195691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 285295691c9cSTomer Tayar param, opcode); 285395691c9cSTomer Tayar return -EINVAL; 285495691c9cSTomer Tayar } 285595691c9cSTomer Tayar 285695691c9cSTomer Tayar return rc; 285795691c9cSTomer Tayar } 285895691c9cSTomer Tayar 285995691c9cSTomer Tayar int 286095691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 286195691c9cSTomer Tayar struct qed_ptt *p_ptt, 286295691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 286395691c9cSTomer Tayar { 286495691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 286595691c9cSTomer Tayar u8 opcode; 286695691c9cSTomer Tayar int rc; 286795691c9cSTomer Tayar 286895691c9cSTomer Tayar switch (p_params->timeout) { 286995691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 287095691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 287195691c9cSTomer Tayar p_params->timeout = 0; 287295691c9cSTomer Tayar break; 287395691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 287495691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 287595691c9cSTomer Tayar p_params->timeout = 0; 287695691c9cSTomer Tayar break; 287795691c9cSTomer Tayar default: 287895691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 287995691c9cSTomer Tayar break; 288095691c9cSTomer Tayar } 288195691c9cSTomer Tayar 288295691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 288395691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 288495691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 288595691c9cSTomer Tayar 288695691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 288795691c9cSTomer Tayar QED_MSG_SP, 288895691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 288995691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 289095691c9cSTomer Tayar 289195691c9cSTomer Tayar /* Attempt to acquire the resource */ 289295691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 289395691c9cSTomer Tayar if (rc) 289495691c9cSTomer Tayar return rc; 289595691c9cSTomer Tayar 289695691c9cSTomer Tayar /* Analyze the response */ 289795691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 289895691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 289995691c9cSTomer Tayar 290095691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 290195691c9cSTomer Tayar QED_MSG_SP, 290295691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 290395691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 290495691c9cSTomer Tayar 290595691c9cSTomer Tayar switch (opcode) { 290695691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 290795691c9cSTomer Tayar p_params->b_granted = true; 290895691c9cSTomer Tayar break; 290995691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 291095691c9cSTomer Tayar p_params->b_granted = false; 291195691c9cSTomer Tayar break; 291295691c9cSTomer Tayar default: 291395691c9cSTomer Tayar DP_NOTICE(p_hwfn, 291495691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 291595691c9cSTomer Tayar mcp_param, opcode); 291695691c9cSTomer Tayar return -EINVAL; 291795691c9cSTomer Tayar } 291895691c9cSTomer Tayar 291995691c9cSTomer Tayar return 0; 292095691c9cSTomer Tayar } 292195691c9cSTomer Tayar 292295691c9cSTomer Tayar int 292395691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 292495691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 292595691c9cSTomer Tayar { 292695691c9cSTomer Tayar u32 retry_cnt = 0; 292795691c9cSTomer Tayar int rc; 292895691c9cSTomer Tayar 292995691c9cSTomer Tayar do { 293095691c9cSTomer Tayar /* No need for an interval before the first iteration */ 293195691c9cSTomer Tayar if (retry_cnt) { 293295691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 293395691c9cSTomer Tayar u16 retry_interval_in_ms = 293495691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 293595691c9cSTomer Tayar 1000); 293695691c9cSTomer Tayar 293795691c9cSTomer Tayar msleep(retry_interval_in_ms); 293895691c9cSTomer Tayar } else { 293995691c9cSTomer Tayar udelay(p_params->retry_interval); 294095691c9cSTomer Tayar } 294195691c9cSTomer Tayar } 294295691c9cSTomer Tayar 294395691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 294495691c9cSTomer Tayar if (rc) 294595691c9cSTomer Tayar return rc; 294695691c9cSTomer Tayar 294795691c9cSTomer Tayar if (p_params->b_granted) 294895691c9cSTomer Tayar break; 294995691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 295095691c9cSTomer Tayar 295195691c9cSTomer Tayar return 0; 295295691c9cSTomer Tayar } 295395691c9cSTomer Tayar 295495691c9cSTomer Tayar int 295595691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 295695691c9cSTomer Tayar struct qed_ptt *p_ptt, 295795691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 295895691c9cSTomer Tayar { 295995691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 296095691c9cSTomer Tayar u8 opcode; 296195691c9cSTomer Tayar int rc; 296295691c9cSTomer Tayar 296395691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 296495691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 296595691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 296695691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 296795691c9cSTomer Tayar 296895691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 296995691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 297095691c9cSTomer Tayar param, opcode, p_params->resource); 297195691c9cSTomer Tayar 297295691c9cSTomer Tayar /* Attempt to release the resource */ 297395691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 297495691c9cSTomer Tayar if (rc) 297595691c9cSTomer Tayar return rc; 297695691c9cSTomer Tayar 297795691c9cSTomer Tayar /* Analyze the response */ 297895691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 297995691c9cSTomer Tayar 298095691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 298195691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 298295691c9cSTomer Tayar mcp_param, opcode); 298395691c9cSTomer Tayar 298495691c9cSTomer Tayar switch (opcode) { 298595691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 298695691c9cSTomer Tayar DP_INFO(p_hwfn, 298795691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 298895691c9cSTomer Tayar p_params->resource); 298995691c9cSTomer Tayar /* Fallthrough */ 299095691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 299195691c9cSTomer Tayar p_params->b_released = true; 299295691c9cSTomer Tayar break; 299395691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 299495691c9cSTomer Tayar p_params->b_released = false; 299595691c9cSTomer Tayar break; 299695691c9cSTomer Tayar default: 299795691c9cSTomer Tayar DP_NOTICE(p_hwfn, 299895691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 299995691c9cSTomer Tayar mcp_param, opcode); 300095691c9cSTomer Tayar return -EINVAL; 300195691c9cSTomer Tayar } 300295691c9cSTomer Tayar 300395691c9cSTomer Tayar return 0; 300495691c9cSTomer Tayar } 3005f470f22cSsudarsana.kalluru@cavium.com 3006f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3007f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3008f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3009f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3010f470f22cSsudarsana.kalluru@cavium.com { 3011f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3012f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3013f470f22cSsudarsana.kalluru@cavium.com 3014f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3015f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3016f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3017f470f22cSsudarsana.kalluru@cavium.com */ 3018f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3019f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3020f470f22cSsudarsana.kalluru@cavium.com } else { 3021f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3022f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3023f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3024f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3025f470f22cSsudarsana.kalluru@cavium.com } 3026f470f22cSsudarsana.kalluru@cavium.com 3027f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3028f470f22cSsudarsana.kalluru@cavium.com } 3029f470f22cSsudarsana.kalluru@cavium.com 3030f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3031f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3032f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3033f470f22cSsudarsana.kalluru@cavium.com } 3034f470f22cSsudarsana.kalluru@cavium.com } 3035645874e5SSudarsana Reddy Kalluru 3036645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3037645874e5SSudarsana Reddy Kalluru { 3038645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3039645874e5SSudarsana Reddy Kalluru int rc; 3040645874e5SSudarsana Reddy Kalluru 3041645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3042645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3043645874e5SSudarsana Reddy Kalluru if (!rc) 3044645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3045645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3046645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3047645874e5SSudarsana Reddy Kalluru 3048645874e5SSudarsana Reddy Kalluru return rc; 3049645874e5SSudarsana Reddy Kalluru } 3050645874e5SSudarsana Reddy Kalluru 3051645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3052645874e5SSudarsana Reddy Kalluru { 3053645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3054645874e5SSudarsana Reddy Kalluru 3055645874e5SSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE; 3056645874e5SSudarsana Reddy Kalluru 3057645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3058645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3059645874e5SSudarsana Reddy Kalluru } 3060