1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/delay.h> 12fe56b9e6SYuval Mintz #include <linux/errno.h> 13fe56b9e6SYuval Mintz #include <linux/kernel.h> 14fe56b9e6SYuval Mintz #include <linux/slab.h> 155529bad9STomer Tayar #include <linux/spinlock.h> 16fe56b9e6SYuval Mintz #include <linux/string.h> 170fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 18fe56b9e6SYuval Mintz #include "qed.h" 1939651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 20fe56b9e6SYuval Mintz #include "qed_hsi.h" 21fe56b9e6SYuval Mintz #include "qed_hw.h" 22fe56b9e6SYuval Mintz #include "qed_mcp.h" 23fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 241408cc1fSYuval Mintz #include "qed_sriov.h" 251408cc1fSYuval Mintz 26fe56b9e6SYuval Mintz #define CHIP_MCP_RESP_ITER_US 10 27fe56b9e6SYuval Mintz 28fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 29fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 30fe56b9e6SYuval Mintz 31fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 32fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 33fe56b9e6SYuval Mintz _val) 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 36fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 39fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 40fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 41fe56b9e6SYuval Mintz 42fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 43fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 44fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 45fe56b9e6SYuval Mintz 46fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 47fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 48fe56b9e6SYuval Mintz 49fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 50fe56b9e6SYuval Mintz 51fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 52fe56b9e6SYuval Mintz { 53fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 54fe56b9e6SYuval Mintz return false; 55fe56b9e6SYuval Mintz return true; 56fe56b9e6SYuval Mintz } 57fe56b9e6SYuval Mintz 581a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 59fe56b9e6SYuval Mintz { 60fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 61fe56b9e6SYuval Mintz PUBLIC_PORT); 62fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 65fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 66fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 67fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 68fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 69fe56b9e6SYuval Mintz } 70fe56b9e6SYuval Mintz 711a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 72fe56b9e6SYuval Mintz { 73fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 74fe56b9e6SYuval Mintz u32 tmp, i; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 77fe56b9e6SYuval Mintz return; 78fe56b9e6SYuval Mintz 79fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 80fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 81fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 82fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 83fe56b9e6SYuval Mintz 84fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 85fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 86fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 87fe56b9e6SYuval Mintz } 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz 90fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 91fe56b9e6SYuval Mintz { 92fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 93fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 94fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 95fe56b9e6SYuval Mintz } 96fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 97fe56b9e6SYuval Mintz 98fe56b9e6SYuval Mintz return 0; 99fe56b9e6SYuval Mintz } 100fe56b9e6SYuval Mintz 1011a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 102fe56b9e6SYuval Mintz { 103fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 104fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 105fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 108fe56b9e6SYuval Mintz if (!p_info->public_base) 109fe56b9e6SYuval Mintz return 0; 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 112fe56b9e6SYuval Mintz 113fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 114fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 115fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 116fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 117fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 118fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 119fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 120fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 121fe56b9e6SYuval Mintz 122fe56b9e6SYuval Mintz /* Set the MFW MB address */ 123fe56b9e6SYuval Mintz mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 124fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 125fe56b9e6SYuval Mintz PUBLIC_MFW_MB)); 126fe56b9e6SYuval Mintz p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 127fe56b9e6SYuval Mintz p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 128fe56b9e6SYuval Mintz 129fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 130fe56b9e6SYuval Mintz * the first command 131fe56b9e6SYuval Mintz */ 132fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 133fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 136fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 137fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 138fe56b9e6SYuval Mintz 139fe56b9e6SYuval Mintz p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 140fe56b9e6SYuval Mintz 141fe56b9e6SYuval Mintz return 0; 142fe56b9e6SYuval Mintz } 143fe56b9e6SYuval Mintz 1441a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 145fe56b9e6SYuval Mintz { 146fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 147fe56b9e6SYuval Mintz u32 size; 148fe56b9e6SYuval Mintz 149fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 15060fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 151fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 152fe56b9e6SYuval Mintz goto err; 153fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 154fe56b9e6SYuval Mintz 155fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 156fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 157fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 158fe56b9e6SYuval Mintz * the MCP is not initialized 159fe56b9e6SYuval Mintz */ 160fe56b9e6SYuval Mintz return 0; 161fe56b9e6SYuval Mintz } 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 16460fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 16583aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 166fe56b9e6SYuval Mintz if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr) 167fe56b9e6SYuval Mintz goto err; 168fe56b9e6SYuval Mintz 1695529bad9STomer Tayar /* Initialize the MFW spinlock */ 1705529bad9STomer Tayar spin_lock_init(&p_info->lock); 171fe56b9e6SYuval Mintz 172fe56b9e6SYuval Mintz return 0; 173fe56b9e6SYuval Mintz 174fe56b9e6SYuval Mintz err: 175fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 176fe56b9e6SYuval Mintz return -ENOMEM; 177fe56b9e6SYuval Mintz } 178fe56b9e6SYuval Mintz 1795529bad9STomer Tayar /* Locks the MFW mailbox of a PF to ensure a single access. 1805529bad9STomer Tayar * The lock is achieved in most cases by holding a spinlock, causing other 1815529bad9STomer Tayar * threads to wait till a previous access is done. 1825529bad9STomer Tayar * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single 1835529bad9STomer Tayar * access is achieved by setting a blocking flag, which will fail other 1845529bad9STomer Tayar * competing contexts to send their mailboxes. 1855529bad9STomer Tayar */ 1861a635e48SYuval Mintz static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn, u32 cmd) 1875529bad9STomer Tayar { 1885529bad9STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->lock); 1895529bad9STomer Tayar 1905529bad9STomer Tayar /* The spinlock shouldn't be acquired when the mailbox command is 1915529bad9STomer Tayar * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel 1925529bad9STomer Tayar * pending [UN]LOAD_REQ command of another PF together with a spinlock 1935529bad9STomer Tayar * (i.e. interrupts are disabled) - can lead to a deadlock. 1945529bad9STomer Tayar * It is assumed that for a single PF, no other mailbox commands can be 1955529bad9STomer Tayar * sent from another context while sending LOAD_REQ, and that any 1965529bad9STomer Tayar * parallel commands to UNLOAD_REQ can be cancelled. 1975529bad9STomer Tayar */ 1985529bad9STomer Tayar if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE) 1995529bad9STomer Tayar p_hwfn->mcp_info->block_mb_sending = false; 2005529bad9STomer Tayar 2015529bad9STomer Tayar if (p_hwfn->mcp_info->block_mb_sending) { 2025529bad9STomer Tayar DP_NOTICE(p_hwfn, 2035529bad9STomer Tayar "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n", 2045529bad9STomer Tayar cmd); 2055529bad9STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->lock); 2065529bad9STomer Tayar return -EBUSY; 2075529bad9STomer Tayar } 2085529bad9STomer Tayar 2095529bad9STomer Tayar if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) { 2105529bad9STomer Tayar p_hwfn->mcp_info->block_mb_sending = true; 2115529bad9STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->lock); 2125529bad9STomer Tayar } 2135529bad9STomer Tayar 2145529bad9STomer Tayar return 0; 2155529bad9STomer Tayar } 2165529bad9STomer Tayar 2171a635e48SYuval Mintz static void qed_mcp_mb_unlock(struct qed_hwfn *p_hwfn, u32 cmd) 2185529bad9STomer Tayar { 2195529bad9STomer Tayar if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ) 2205529bad9STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->lock); 2215529bad9STomer Tayar } 2225529bad9STomer Tayar 2231a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 224fe56b9e6SYuval Mintz { 225fe56b9e6SYuval Mintz u32 seq = ++p_hwfn->mcp_info->drv_mb_seq; 226fe56b9e6SYuval Mintz u8 delay = CHIP_MCP_RESP_ITER_US; 227fe56b9e6SYuval Mintz u32 org_mcp_reset_seq, cnt = 0; 228fe56b9e6SYuval Mintz int rc = 0; 229fe56b9e6SYuval Mintz 2305529bad9STomer Tayar /* Ensure that only a single thread is accessing the mailbox at a 2315529bad9STomer Tayar * certain time. 2325529bad9STomer Tayar */ 2335529bad9STomer Tayar rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 2345529bad9STomer Tayar if (rc != 0) 2355529bad9STomer Tayar return rc; 2365529bad9STomer Tayar 237fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 238fe56b9e6SYuval Mintz org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 239fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, 240fe56b9e6SYuval Mintz (DRV_MSG_CODE_MCP_RESET | seq)); 241fe56b9e6SYuval Mintz 242fe56b9e6SYuval Mintz do { 243fe56b9e6SYuval Mintz /* Wait for MFW response */ 244fe56b9e6SYuval Mintz udelay(delay); 245fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 246fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 247fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 248fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 249fe56b9e6SYuval Mintz 250fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 251fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 252fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 253fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 254fe56b9e6SYuval Mintz } else { 255fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 256fe56b9e6SYuval Mintz rc = -EAGAIN; 257fe56b9e6SYuval Mintz } 258fe56b9e6SYuval Mintz 2595529bad9STomer Tayar qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 2605529bad9STomer Tayar 261fe56b9e6SYuval Mintz return rc; 262fe56b9e6SYuval Mintz } 263fe56b9e6SYuval Mintz 264fe56b9e6SYuval Mintz static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn, 265fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 266fe56b9e6SYuval Mintz u32 cmd, 267fe56b9e6SYuval Mintz u32 param, 268fe56b9e6SYuval Mintz u32 *o_mcp_resp, 269fe56b9e6SYuval Mintz u32 *o_mcp_param) 270fe56b9e6SYuval Mintz { 271fe56b9e6SYuval Mintz u8 delay = CHIP_MCP_RESP_ITER_US; 272fe56b9e6SYuval Mintz u32 seq, cnt = 1, actual_mb_seq; 273fe56b9e6SYuval Mintz int rc = 0; 274fe56b9e6SYuval Mintz 275fe56b9e6SYuval Mintz /* Get actual driver mailbox sequence */ 276fe56b9e6SYuval Mintz actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 277fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 278fe56b9e6SYuval Mintz 279fe56b9e6SYuval Mintz /* Use MCP history register to check if MCP reset occurred between 280fe56b9e6SYuval Mintz * init time and now. 281fe56b9e6SYuval Mintz */ 282fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->mcp_hist != 283fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 284fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n"); 285fe56b9e6SYuval Mintz qed_load_mcp_offsets(p_hwfn, p_ptt); 286fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 287fe56b9e6SYuval Mintz } 288fe56b9e6SYuval Mintz seq = ++p_hwfn->mcp_info->drv_mb_seq; 289fe56b9e6SYuval Mintz 290fe56b9e6SYuval Mintz /* Set drv param */ 291fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param); 292fe56b9e6SYuval Mintz 293fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 294fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq)); 295fe56b9e6SYuval Mintz 296fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 297fe56b9e6SYuval Mintz "wrote command (%x) to MFW MB param 0x%08x\n", 298fe56b9e6SYuval Mintz (cmd | seq), param); 299fe56b9e6SYuval Mintz 300fe56b9e6SYuval Mintz do { 301fe56b9e6SYuval Mintz /* Wait for MFW response */ 302fe56b9e6SYuval Mintz udelay(delay); 303fe56b9e6SYuval Mintz *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 304fe56b9e6SYuval Mintz 305fe56b9e6SYuval Mintz /* Give the FW up to 5 second (500*10ms) */ 306fe56b9e6SYuval Mintz } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) && 307fe56b9e6SYuval Mintz (cnt++ < QED_DRV_MB_MAX_RETRIES)); 308fe56b9e6SYuval Mintz 309fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 310fe56b9e6SYuval Mintz "[after %d ms] read (%x) seq is (%x) from FW MB\n", 311fe56b9e6SYuval Mintz cnt * delay, *o_mcp_resp, seq); 312fe56b9e6SYuval Mintz 313fe56b9e6SYuval Mintz /* Is this a reply to our command? */ 314fe56b9e6SYuval Mintz if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) { 315fe56b9e6SYuval Mintz *o_mcp_resp &= FW_MSG_CODE_MASK; 316fe56b9e6SYuval Mintz /* Get the MCP param */ 317fe56b9e6SYuval Mintz *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 318fe56b9e6SYuval Mintz } else { 319fe56b9e6SYuval Mintz /* FW BUG! */ 320525ef5c0SYuval Mintz DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n", 321525ef5c0SYuval Mintz cmd, param); 322fe56b9e6SYuval Mintz *o_mcp_resp = 0; 323fe56b9e6SYuval Mintz rc = -EAGAIN; 324fe56b9e6SYuval Mintz } 325fe56b9e6SYuval Mintz return rc; 326fe56b9e6SYuval Mintz } 327fe56b9e6SYuval Mintz 3285529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 329fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 3305529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 331fe56b9e6SYuval Mintz { 3325529bad9STomer Tayar u32 union_data_addr; 33314d39648SMintz, Yuval 3345529bad9STomer Tayar int rc; 335fe56b9e6SYuval Mintz 336fe56b9e6SYuval Mintz /* MCP not initialized */ 337fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 338fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 339fe56b9e6SYuval Mintz return -EBUSY; 340fe56b9e6SYuval Mintz } 341fe56b9e6SYuval Mintz 3425529bad9STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3435529bad9STomer Tayar offsetof(struct public_drv_mb, union_data); 3445529bad9STomer Tayar 3455529bad9STomer Tayar /* Ensure that only a single thread is accessing the mailbox at a 3465529bad9STomer Tayar * certain time. 347fe56b9e6SYuval Mintz */ 3485529bad9STomer Tayar rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd); 3495529bad9STomer Tayar if (rc) 3505529bad9STomer Tayar return rc; 3515529bad9STomer Tayar 3525529bad9STomer Tayar if (p_mb_params->p_data_src != NULL) 3535529bad9STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, 3545529bad9STomer Tayar p_mb_params->p_data_src, 3555529bad9STomer Tayar sizeof(*p_mb_params->p_data_src)); 3565529bad9STomer Tayar 3575529bad9STomer Tayar rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd, 3585529bad9STomer Tayar p_mb_params->param, &p_mb_params->mcp_resp, 3595529bad9STomer Tayar &p_mb_params->mcp_param); 3605529bad9STomer Tayar 3615529bad9STomer Tayar if (p_mb_params->p_data_dst != NULL) 3625529bad9STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3635529bad9STomer Tayar union_data_addr, 3645529bad9STomer Tayar sizeof(*p_mb_params->p_data_dst)); 3655529bad9STomer Tayar 3665529bad9STomer Tayar qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd); 367fe56b9e6SYuval Mintz 368fe56b9e6SYuval Mintz return rc; 369fe56b9e6SYuval Mintz } 370fe56b9e6SYuval Mintz 3715529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 3725529bad9STomer Tayar struct qed_ptt *p_ptt, 3735529bad9STomer Tayar u32 cmd, 3745529bad9STomer Tayar u32 param, 3755529bad9STomer Tayar u32 *o_mcp_resp, 3765529bad9STomer Tayar u32 *o_mcp_param) 377fe56b9e6SYuval Mintz { 3785529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 37914d39648SMintz, Yuval union drv_union_data data_src; 3805529bad9STomer Tayar int rc; 381fe56b9e6SYuval Mintz 3825529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 38314d39648SMintz, Yuval memset(&data_src, 0, sizeof(data_src)); 3845529bad9STomer Tayar mb_params.cmd = cmd; 3855529bad9STomer Tayar mb_params.param = param; 38614d39648SMintz, Yuval 38714d39648SMintz, Yuval /* In case of UNLOAD_DONE, set the primary MAC */ 38814d39648SMintz, Yuval if ((cmd == DRV_MSG_CODE_UNLOAD_DONE) && 38914d39648SMintz, Yuval (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED)) { 39014d39648SMintz, Yuval u8 *p_mac = p_hwfn->cdev->wol_mac; 39114d39648SMintz, Yuval 39214d39648SMintz, Yuval data_src.wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 39314d39648SMintz, Yuval data_src.wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 39414d39648SMintz, Yuval p_mac[4] << 8 | p_mac[5]; 39514d39648SMintz, Yuval 39614d39648SMintz, Yuval DP_VERBOSE(p_hwfn, 39714d39648SMintz, Yuval (QED_MSG_SP | NETIF_MSG_IFDOWN), 39814d39648SMintz, Yuval "Setting WoL MAC: %pM --> [%08x,%08x]\n", 39914d39648SMintz, Yuval p_mac, data_src.wol_mac.mac_upper, 40014d39648SMintz, Yuval data_src.wol_mac.mac_lower); 40114d39648SMintz, Yuval 40214d39648SMintz, Yuval mb_params.p_data_src = &data_src; 40314d39648SMintz, Yuval } 40414d39648SMintz, Yuval 4055529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 4065529bad9STomer Tayar if (rc) 4075529bad9STomer Tayar return rc; 4085529bad9STomer Tayar 4095529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 4105529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 4115529bad9STomer Tayar 4125529bad9STomer Tayar return 0; 413fe56b9e6SYuval Mintz } 414fe56b9e6SYuval Mintz 4154102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 4164102426fSTomer Tayar struct qed_ptt *p_ptt, 4174102426fSTomer Tayar u32 cmd, 4184102426fSTomer Tayar u32 param, 4194102426fSTomer Tayar u32 *o_mcp_resp, 4204102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 4214102426fSTomer Tayar { 4224102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 4234102426fSTomer Tayar union drv_union_data union_data; 4244102426fSTomer Tayar int rc; 4254102426fSTomer Tayar 4264102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 4274102426fSTomer Tayar mb_params.cmd = cmd; 4284102426fSTomer Tayar mb_params.param = param; 4294102426fSTomer Tayar mb_params.p_data_dst = &union_data; 4304102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 4314102426fSTomer Tayar if (rc) 4324102426fSTomer Tayar return rc; 4334102426fSTomer Tayar 4344102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 4354102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 4364102426fSTomer Tayar 4374102426fSTomer Tayar *o_txn_size = *o_mcp_param; 4384102426fSTomer Tayar memcpy(o_buf, &union_data.raw_data, *o_txn_size); 4394102426fSTomer Tayar 4404102426fSTomer Tayar return 0; 4414102426fSTomer Tayar } 4424102426fSTomer Tayar 443fe56b9e6SYuval Mintz int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 4441a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_load_code) 445fe56b9e6SYuval Mintz { 446fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 4475529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 4485529bad9STomer Tayar union drv_union_data union_data; 449fe56b9e6SYuval Mintz int rc; 450fe56b9e6SYuval Mintz 4515529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 452fe56b9e6SYuval Mintz /* Load Request */ 4535529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 4545529bad9STomer Tayar mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT | 4555529bad9STomer Tayar cdev->drv_type; 4565529bad9STomer Tayar memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE); 4575529bad9STomer Tayar mb_params.p_data_src = &union_data; 4585529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 459fe56b9e6SYuval Mintz 460fe56b9e6SYuval Mintz /* if mcp fails to respond we must abort */ 461fe56b9e6SYuval Mintz if (rc) { 462fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 463fe56b9e6SYuval Mintz return rc; 464fe56b9e6SYuval Mintz } 465fe56b9e6SYuval Mintz 4665529bad9STomer Tayar *p_load_code = mb_params.mcp_resp; 4675529bad9STomer Tayar 468fe56b9e6SYuval Mintz /* If MFW refused (e.g. other port is in diagnostic mode) we 469fe56b9e6SYuval Mintz * must abort. This can happen in the following cases: 470fe56b9e6SYuval Mintz * - Other port is in diagnostic mode 471fe56b9e6SYuval Mintz * - Previously loaded function on the engine is not compliant with 472fe56b9e6SYuval Mintz * the requester. 473fe56b9e6SYuval Mintz * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION. 474fe56b9e6SYuval Mintz * - 475fe56b9e6SYuval Mintz */ 476fe56b9e6SYuval Mintz if (!(*p_load_code) || 477fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) || 478fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) || 479fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) { 480fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP refused load request, aborting\n"); 481fe56b9e6SYuval Mintz return -EBUSY; 482fe56b9e6SYuval Mintz } 483fe56b9e6SYuval Mintz 484fe56b9e6SYuval Mintz return 0; 485fe56b9e6SYuval Mintz } 486fe56b9e6SYuval Mintz 4870b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 4880b55e27dSYuval Mintz struct qed_ptt *p_ptt) 4890b55e27dSYuval Mintz { 4900b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 4910b55e27dSYuval Mintz PUBLIC_PATH); 4920b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 4930b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 4940b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 4950b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 4960b55e27dSYuval Mintz int i; 4970b55e27dSYuval Mintz 4980b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 4990b55e27dSYuval Mintz QED_MSG_SP, 5000b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 5010b55e27dSYuval Mintz mfw_path_offsize, path_addr); 5020b55e27dSYuval Mintz 5030b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 5040b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 5050b55e27dSYuval Mintz path_addr + 5060b55e27dSYuval Mintz offsetof(struct public_path, 5070b55e27dSYuval Mintz mcp_vf_disabled) + 5080b55e27dSYuval Mintz sizeof(u32) * i); 5090b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 5100b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 5110b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 5120b55e27dSYuval Mintz } 5130b55e27dSYuval Mintz 5140b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 5150b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 5160b55e27dSYuval Mintz } 5170b55e27dSYuval Mintz 5180b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 5190b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 5200b55e27dSYuval Mintz { 5210b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 5220b55e27dSYuval Mintz PUBLIC_FUNC); 5230b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 5240b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 5250b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 5260b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 5270b55e27dSYuval Mintz union drv_union_data union_data; 5280b55e27dSYuval Mintz int rc; 5290b55e27dSYuval Mintz int i; 5300b55e27dSYuval Mintz 5310b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 5320b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 5330b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 5340b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 5350b55e27dSYuval Mintz 5360b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 5370b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 5380b55e27dSYuval Mintz memcpy(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8); 5390b55e27dSYuval Mintz mb_params.p_data_src = &union_data; 5400b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 5410b55e27dSYuval Mintz if (rc) { 5420b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 5430b55e27dSYuval Mintz return -EBUSY; 5440b55e27dSYuval Mintz } 5450b55e27dSYuval Mintz 5460b55e27dSYuval Mintz /* Clear the ACK bits */ 5470b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 5480b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 5490b55e27dSYuval Mintz func_addr + 5500b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 5510b55e27dSYuval Mintz i * sizeof(u32), 0); 5520b55e27dSYuval Mintz 5530b55e27dSYuval Mintz return rc; 5540b55e27dSYuval Mintz } 5550b55e27dSYuval Mintz 556334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 557334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 558334c03b5SZvi Nachmani { 559334c03b5SZvi Nachmani u32 transceiver_state; 560334c03b5SZvi Nachmani 561334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 562334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 563334c03b5SZvi Nachmani offsetof(struct public_port, 564334c03b5SZvi Nachmani transceiver_data)); 565334c03b5SZvi Nachmani 566334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 567334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 568334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 569334c03b5SZvi Nachmani transceiver_state, 570334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 5711a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 572334c03b5SZvi Nachmani 573334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 574351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 575334c03b5SZvi Nachmani 576351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 577334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 578334c03b5SZvi Nachmani else 579334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 580334c03b5SZvi Nachmani } 581334c03b5SZvi Nachmani 582cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 5831a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 584cc875c2eSYuval Mintz { 585cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 586a64b02d5SManish Chopra u8 max_bw, min_bw; 587cc875c2eSYuval Mintz u32 status = 0; 588cc875c2eSYuval Mintz 589cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 590cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 591cc875c2eSYuval Mintz if (!b_reset) { 592cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 593cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 594cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 595cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 596cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 597cc875c2eSYuval Mintz status, 598cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 5991a635e48SYuval Mintz offsetof(struct public_port, link_status))); 600cc875c2eSYuval Mintz } else { 601cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 602cc875c2eSYuval Mintz "Resetting link indications\n"); 603cc875c2eSYuval Mintz return; 604cc875c2eSYuval Mintz } 605cc875c2eSYuval Mintz 606fc916ff2SSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) 607cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 608fc916ff2SSudarsana Reddy Kalluru else 609fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 610cc875c2eSYuval Mintz 611cc875c2eSYuval Mintz p_link->full_duplex = true; 612cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 613cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 614cc875c2eSYuval Mintz p_link->speed = 100000; 615cc875c2eSYuval Mintz break; 616cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 617cc875c2eSYuval Mintz p_link->speed = 50000; 618cc875c2eSYuval Mintz break; 619cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 620cc875c2eSYuval Mintz p_link->speed = 40000; 621cc875c2eSYuval Mintz break; 622cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 623cc875c2eSYuval Mintz p_link->speed = 25000; 624cc875c2eSYuval Mintz break; 625cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 626cc875c2eSYuval Mintz p_link->speed = 20000; 627cc875c2eSYuval Mintz break; 628cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 629cc875c2eSYuval Mintz p_link->speed = 10000; 630cc875c2eSYuval Mintz break; 631cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 632cc875c2eSYuval Mintz p_link->full_duplex = false; 633cc875c2eSYuval Mintz /* Fall-through */ 634cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 635cc875c2eSYuval Mintz p_link->speed = 1000; 636cc875c2eSYuval Mintz break; 637cc875c2eSYuval Mintz default: 638cc875c2eSYuval Mintz p_link->speed = 0; 639cc875c2eSYuval Mintz } 640cc875c2eSYuval Mintz 6414b01e519SManish Chopra if (p_link->link_up && p_link->speed) 6424b01e519SManish Chopra p_link->line_speed = p_link->speed; 6434b01e519SManish Chopra else 6444b01e519SManish Chopra p_link->line_speed = 0; 6454b01e519SManish Chopra 6464b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 647a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 6484b01e519SManish Chopra 649a64b02d5SManish Chopra /* Max bandwidth configuration */ 6504b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 651cc875c2eSYuval Mintz 652a64b02d5SManish Chopra /* Min bandwidth configuration */ 653a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 654a64b02d5SManish Chopra qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate); 655a64b02d5SManish Chopra 656cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 657cc875c2eSYuval Mintz p_link->an_complete = !!(status & 658cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 659cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 660cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 661cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 662cc875c2eSYuval Mintz 663cc875c2eSYuval Mintz p_link->partner_adv_speed |= 664cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 665cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 666cc875c2eSYuval Mintz p_link->partner_adv_speed |= 667cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 668cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 669cc875c2eSYuval Mintz p_link->partner_adv_speed |= 670cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 671cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 672cc875c2eSYuval Mintz p_link->partner_adv_speed |= 673cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 674cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 675cc875c2eSYuval Mintz p_link->partner_adv_speed |= 676054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 677054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 678054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 679cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 680cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 681cc875c2eSYuval Mintz p_link->partner_adv_speed |= 682cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 683cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 684cc875c2eSYuval Mintz p_link->partner_adv_speed |= 685cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 686cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 687cc875c2eSYuval Mintz 688cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 689cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 690cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 691cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 692cc875c2eSYuval Mintz 693cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 694cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 695cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 696cc875c2eSYuval Mintz break; 697cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 698cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 699cc875c2eSYuval Mintz break; 700cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 701cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 702cc875c2eSYuval Mintz break; 703cc875c2eSYuval Mintz default: 704cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 705cc875c2eSYuval Mintz } 706cc875c2eSYuval Mintz 707cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 708cc875c2eSYuval Mintz 709cc875c2eSYuval Mintz qed_link_update(p_hwfn); 710cc875c2eSYuval Mintz } 711cc875c2eSYuval Mintz 712351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 713cc875c2eSYuval Mintz { 714cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 7155529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 7165529bad9STomer Tayar union drv_union_data union_data; 717351a4dedSYuval Mintz struct eth_phy_cfg *phy_cfg; 718cc875c2eSYuval Mintz int rc = 0; 7195529bad9STomer Tayar u32 cmd; 720cc875c2eSYuval Mintz 721cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 7225529bad9STomer Tayar phy_cfg = &union_data.drv_phy_cfg; 7235529bad9STomer Tayar memset(phy_cfg, 0, sizeof(*phy_cfg)); 724cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 725cc875c2eSYuval Mintz if (!params->speed.autoneg) 7265529bad9STomer Tayar phy_cfg->speed = params->speed.forced_speed; 727351a4dedSYuval Mintz phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 728351a4dedSYuval Mintz phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 729351a4dedSYuval Mintz phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 7305529bad9STomer Tayar phy_cfg->adv_speed = params->speed.advertised_speeds; 7315529bad9STomer Tayar phy_cfg->loopback_mode = params->loopback_mode; 732cc875c2eSYuval Mintz 733fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 734fc916ff2SSudarsana Reddy Kalluru 735cc875c2eSYuval Mintz if (b_up) { 736cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 737cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 7385529bad9STomer Tayar phy_cfg->speed, 7395529bad9STomer Tayar phy_cfg->pause, 7405529bad9STomer Tayar phy_cfg->adv_speed, 7415529bad9STomer Tayar phy_cfg->loopback_mode, 7425529bad9STomer Tayar phy_cfg->feature_config_flags); 743cc875c2eSYuval Mintz } else { 744cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 745cc875c2eSYuval Mintz "Resetting link\n"); 746cc875c2eSYuval Mintz } 747cc875c2eSYuval Mintz 7485529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7495529bad9STomer Tayar mb_params.cmd = cmd; 7505529bad9STomer Tayar mb_params.p_data_src = &union_data; 7515529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 752cc875c2eSYuval Mintz 753cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 754cc875c2eSYuval Mintz if (rc) { 755cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 756cc875c2eSYuval Mintz return rc; 757cc875c2eSYuval Mintz } 758cc875c2eSYuval Mintz 759cc875c2eSYuval Mintz /* Reset the link status if needed */ 760cc875c2eSYuval Mintz if (!b_up) 761cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, true); 762cc875c2eSYuval Mintz 763cc875c2eSYuval Mintz return 0; 764cc875c2eSYuval Mintz } 765cc875c2eSYuval Mintz 7666c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 7676c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 7686c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 7696c754246SSudarsana Reddy Kalluru { 7706c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 7716c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 7726c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 7736c754246SSudarsana Reddy Kalluru union drv_union_data union_data; 7746c754246SSudarsana Reddy Kalluru u32 hsi_param; 7756c754246SSudarsana Reddy Kalluru 7766c754246SSudarsana Reddy Kalluru switch (type) { 7776c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 7786c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 7796c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 7806c754246SSudarsana Reddy Kalluru break; 7816c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 7826c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 7836c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 7846c754246SSudarsana Reddy Kalluru break; 7856c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 7866c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 7876c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 7886c754246SSudarsana Reddy Kalluru break; 7896c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 7906c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 7916c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 7926c754246SSudarsana Reddy Kalluru break; 7936c754246SSudarsana Reddy Kalluru default: 7946c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 7956c754246SSudarsana Reddy Kalluru return; 7966c754246SSudarsana Reddy Kalluru } 7976c754246SSudarsana Reddy Kalluru 7986c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 7996c754246SSudarsana Reddy Kalluru 8006c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 8016c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 8026c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 8036c754246SSudarsana Reddy Kalluru memcpy(&union_data, &stats, sizeof(stats)); 8046c754246SSudarsana Reddy Kalluru mb_params.p_data_src = &union_data; 8056c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8066c754246SSudarsana Reddy Kalluru } 8076c754246SSudarsana Reddy Kalluru 8084b01e519SManish Chopra static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 8094b01e519SManish Chopra struct public_func *p_shmem_info) 8104b01e519SManish Chopra { 8114b01e519SManish Chopra struct qed_mcp_function_info *p_info; 8124b01e519SManish Chopra 8134b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 8144b01e519SManish Chopra 8154b01e519SManish Chopra p_info->bandwidth_min = (p_shmem_info->config & 8164b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_MASK) >> 8174b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_SHIFT; 8184b01e519SManish Chopra if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 8194b01e519SManish Chopra DP_INFO(p_hwfn, 8204b01e519SManish Chopra "bandwidth minimum out of bounds [%02x]. Set to 1\n", 8214b01e519SManish Chopra p_info->bandwidth_min); 8224b01e519SManish Chopra p_info->bandwidth_min = 1; 8234b01e519SManish Chopra } 8244b01e519SManish Chopra 8254b01e519SManish Chopra p_info->bandwidth_max = (p_shmem_info->config & 8264b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_MASK) >> 8274b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_SHIFT; 8284b01e519SManish Chopra if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 8294b01e519SManish Chopra DP_INFO(p_hwfn, 8304b01e519SManish Chopra "bandwidth maximum out of bounds [%02x]. Set to 100\n", 8314b01e519SManish Chopra p_info->bandwidth_max); 8324b01e519SManish Chopra p_info->bandwidth_max = 100; 8334b01e519SManish Chopra } 8344b01e519SManish Chopra } 8354b01e519SManish Chopra 8364b01e519SManish Chopra static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 8374b01e519SManish Chopra struct qed_ptt *p_ptt, 8381a635e48SYuval Mintz struct public_func *p_data, int pfid) 8394b01e519SManish Chopra { 8404b01e519SManish Chopra u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 8414b01e519SManish Chopra PUBLIC_FUNC); 8424b01e519SManish Chopra u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 8434b01e519SManish Chopra u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 8444b01e519SManish Chopra u32 i, size; 8454b01e519SManish Chopra 8464b01e519SManish Chopra memset(p_data, 0, sizeof(*p_data)); 8474b01e519SManish Chopra 8481a635e48SYuval Mintz size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 8494b01e519SManish Chopra for (i = 0; i < size / sizeof(u32); i++) 8504b01e519SManish Chopra ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 8514b01e519SManish Chopra func_addr + (i << 2)); 8524b01e519SManish Chopra return size; 8534b01e519SManish Chopra } 8544b01e519SManish Chopra 8551a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 8564b01e519SManish Chopra { 8574b01e519SManish Chopra struct qed_mcp_function_info *p_info; 8584b01e519SManish Chopra struct public_func shmem_info; 8594b01e519SManish Chopra u32 resp = 0, param = 0; 8604b01e519SManish Chopra 8611a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 8624b01e519SManish Chopra 8634b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 8644b01e519SManish Chopra 8654b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 8664b01e519SManish Chopra 867a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 8684b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 8694b01e519SManish Chopra 8704b01e519SManish Chopra /* Acknowledge the MFW */ 8714b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 8724b01e519SManish Chopra ¶m); 8734b01e519SManish Chopra } 8744b01e519SManish Chopra 875cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 876cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 877cc875c2eSYuval Mintz { 878cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 879cc875c2eSYuval Mintz int rc = 0; 880cc875c2eSYuval Mintz bool found = false; 881cc875c2eSYuval Mintz u16 i; 882cc875c2eSYuval Mintz 883cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 884cc875c2eSYuval Mintz 885cc875c2eSYuval Mintz /* Read Messages from MFW */ 886cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 887cc875c2eSYuval Mintz 888cc875c2eSYuval Mintz /* Compare current messages to old ones */ 889cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 890cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 891cc875c2eSYuval Mintz continue; 892cc875c2eSYuval Mintz 893cc875c2eSYuval Mintz found = true; 894cc875c2eSYuval Mintz 895cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 896cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 897cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 898cc875c2eSYuval Mintz 899cc875c2eSYuval Mintz switch (i) { 900cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 901cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 902cc875c2eSYuval Mintz break; 9030b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 9040b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 9050b55e27dSYuval Mintz break; 90639651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 90739651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 90839651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 90939651abdSSudarsana Reddy Kalluru break; 91039651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 91139651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 91239651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 91339651abdSSudarsana Reddy Kalluru break; 91439651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 91539651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 91639651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 91739651abdSSudarsana Reddy Kalluru break; 918334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 919334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 920334c03b5SZvi Nachmani break; 9216c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 9226c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 9236c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 9246c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 9256c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 9266c754246SSudarsana Reddy Kalluru break; 9274b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 9284b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 9294b01e519SManish Chopra break; 930cc875c2eSYuval Mintz default: 931cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i); 932cc875c2eSYuval Mintz rc = -EINVAL; 933cc875c2eSYuval Mintz } 934cc875c2eSYuval Mintz } 935cc875c2eSYuval Mintz 936cc875c2eSYuval Mintz /* ACK everything */ 937cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 938cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 939cc875c2eSYuval Mintz 940cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 941cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 942cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 943cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 944cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 945cc875c2eSYuval Mintz (__force u32)val); 946cc875c2eSYuval Mintz } 947cc875c2eSYuval Mintz 948cc875c2eSYuval Mintz if (!found) { 949cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 950cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 951cc875c2eSYuval Mintz rc = -EINVAL; 952cc875c2eSYuval Mintz } 953cc875c2eSYuval Mintz 954cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 955cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 956cc875c2eSYuval Mintz 957cc875c2eSYuval Mintz return rc; 958cc875c2eSYuval Mintz } 959cc875c2eSYuval Mintz 9601408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 9611408cc1fSYuval Mintz struct qed_ptt *p_ptt, 9621408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 963fe56b9e6SYuval Mintz { 964fe56b9e6SYuval Mintz u32 global_offsize; 965fe56b9e6SYuval Mintz 9661408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 9671408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 9681408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 9691408cc1fSYuval Mintz 9701408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 9711408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 9721408cc1fSYuval Mintz return 0; 9731408cc1fSYuval Mintz } else { 9741408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 9751408cc1fSYuval Mintz QED_MSG_IOV, 9761408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 9771408cc1fSYuval Mintz return -EINVAL; 9781408cc1fSYuval Mintz } 9791408cc1fSYuval Mintz } 980fe56b9e6SYuval Mintz 981fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 9821408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 9831408cc1fSYuval Mintz mcp_info->public_base, 984fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 9851408cc1fSYuval Mintz *p_mfw_ver = 9861408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 9871408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 9881408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 989fe56b9e6SYuval Mintz 9901408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 9911408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 9921408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 9931408cc1fSYuval Mintz offsetof(struct public_global, 9941408cc1fSYuval Mintz running_bundle_id)); 9951408cc1fSYuval Mintz } 996fe56b9e6SYuval Mintz 997fe56b9e6SYuval Mintz return 0; 998fe56b9e6SYuval Mintz } 999fe56b9e6SYuval Mintz 10001a635e48SYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1001cc875c2eSYuval Mintz { 1002cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1003cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 1004cc875c2eSYuval Mintz 10051408cc1fSYuval Mintz if (IS_VF(cdev)) 10061408cc1fSYuval Mintz return -EINVAL; 10071408cc1fSYuval Mintz 1008cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1009cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1010cc875c2eSYuval Mintz return -EBUSY; 1011cc875c2eSYuval Mintz } 1012cc875c2eSYuval Mintz 1013cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1014cc875c2eSYuval Mintz 1015cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 1016cc875c2eSYuval Mintz if (!p_ptt) 1017cc875c2eSYuval Mintz return -EBUSY; 1018cc875c2eSYuval Mintz 1019cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1020cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 1021cc875c2eSYuval Mintz 1022cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 1023cc875c2eSYuval Mintz 1024cc875c2eSYuval Mintz return 0; 1025cc875c2eSYuval Mintz } 1026cc875c2eSYuval Mintz 1027fe56b9e6SYuval Mintz static int 1028fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1029fe56b9e6SYuval Mintz struct public_func *p_info, 1030fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 1031fe56b9e6SYuval Mintz { 1032fe56b9e6SYuval Mintz int rc = 0; 1033fe56b9e6SYuval Mintz 1034fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1035fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 1036c5ac9319SYuval Mintz if (test_bit(QED_DEV_CAP_ROCE, 1037c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities)) 1038c5ac9319SYuval Mintz *p_proto = QED_PCI_ETH_ROCE; 1039c5ac9319SYuval Mintz else 1040fe56b9e6SYuval Mintz *p_proto = QED_PCI_ETH; 1041fe56b9e6SYuval Mintz break; 1042c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 1043c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 1044c5ac9319SYuval Mintz break; 1045c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 1046c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 1047c5ac9319SYuval Mintz rc = -EINVAL; 1048c5ac9319SYuval Mintz break; 1049fe56b9e6SYuval Mintz default: 1050fe56b9e6SYuval Mintz rc = -EINVAL; 1051fe56b9e6SYuval Mintz } 1052fe56b9e6SYuval Mintz 1053fe56b9e6SYuval Mintz return rc; 1054fe56b9e6SYuval Mintz } 1055fe56b9e6SYuval Mintz 1056fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1057fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1058fe56b9e6SYuval Mintz { 1059fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 1060fe56b9e6SYuval Mintz struct public_func shmem_info; 1061fe56b9e6SYuval Mintz 10621a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1063fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 1064fe56b9e6SYuval Mintz 1065fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 1066fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1067fe56b9e6SYuval Mintz 10681a635e48SYuval Mintz if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) { 1069fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 1070fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1071fe56b9e6SYuval Mintz return -EINVAL; 1072fe56b9e6SYuval Mintz } 1073fe56b9e6SYuval Mintz 10744b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1075fe56b9e6SYuval Mintz 1076fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 1077fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1078fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 1079fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1080fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1081fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1082fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 108314d39648SMintz, Yuval 108414d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 108514d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1086fe56b9e6SYuval Mintz } else { 1087fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1088fe56b9e6SYuval Mintz } 1089fe56b9e6SYuval Mintz 1090fe56b9e6SYuval Mintz info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper | 1091fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32); 1092fe56b9e6SYuval Mintz info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper | 1093fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32); 1094fe56b9e6SYuval Mintz 1095fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1096fe56b9e6SYuval Mintz 10970fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 10980fefbfbaSSudarsana Kalluru 109914d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 110014d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 110114d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 110214d39648SMintz, Yuval u32 resp = 0, param = 0; 110314d39648SMintz, Yuval int rc; 110414d39648SMintz, Yuval 110514d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 110614d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 110714d39648SMintz, Yuval if (rc) 110814d39648SMintz, Yuval return rc; 110914d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 111014d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 111114d39648SMintz, Yuval } 111214d39648SMintz, Yuval 1113fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 111414d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1115fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 1116fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 1117fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 1118fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 111914d39648SMintz, Yuval info->wwn_port, info->wwn_node, 112014d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1121fe56b9e6SYuval Mintz 1122fe56b9e6SYuval Mintz return 0; 1123fe56b9e6SYuval Mintz } 1124fe56b9e6SYuval Mintz 1125cc875c2eSYuval Mintz struct qed_mcp_link_params 1126cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1127cc875c2eSYuval Mintz { 1128cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1129cc875c2eSYuval Mintz return NULL; 1130cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 1131cc875c2eSYuval Mintz } 1132cc875c2eSYuval Mintz 1133cc875c2eSYuval Mintz struct qed_mcp_link_state 1134cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1135cc875c2eSYuval Mintz { 1136cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1137cc875c2eSYuval Mintz return NULL; 1138cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 1139cc875c2eSYuval Mintz } 1140cc875c2eSYuval Mintz 1141cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 1142cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1143cc875c2eSYuval Mintz { 1144cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1145cc875c2eSYuval Mintz return NULL; 1146cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 1147cc875c2eSYuval Mintz } 1148cc875c2eSYuval Mintz 11491a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1150fe56b9e6SYuval Mintz { 1151fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 1152fe56b9e6SYuval Mintz int rc; 1153fe56b9e6SYuval Mintz 1154fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 11551a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1156fe56b9e6SYuval Mintz 1157fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 11588f60bafeSYuval Mintz msleep(1020); 1159fe56b9e6SYuval Mintz 1160fe56b9e6SYuval Mintz return rc; 1161fe56b9e6SYuval Mintz } 1162fe56b9e6SYuval Mintz 1163cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 11641a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 1165cee4d264SManish Chopra { 1166cee4d264SManish Chopra u32 flash_size; 1167cee4d264SManish Chopra 11681408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 11691408cc1fSYuval Mintz return -EINVAL; 11701408cc1fSYuval Mintz 1171cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1172cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1173cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1174cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1175cee4d264SManish Chopra 1176cee4d264SManish Chopra *p_flash_size = flash_size; 1177cee4d264SManish Chopra 1178cee4d264SManish Chopra return 0; 1179cee4d264SManish Chopra } 1180cee4d264SManish Chopra 11811408cc1fSYuval Mintz int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 11821408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 11831408cc1fSYuval Mintz { 11841408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 11851408cc1fSYuval Mintz int rc; 11861408cc1fSYuval Mintz 11871408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 11881408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 11891408cc1fSYuval Mintz return 0; 11901408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 11911408cc1fSYuval Mintz 11921408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 11931408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 11941408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 11951408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 11961408cc1fSYuval Mintz 11971408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 11981408cc1fSYuval Mintz &resp, &rc_param); 11991408cc1fSYuval Mintz 12001408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 12011408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 12021408cc1fSYuval Mintz rc = -EINVAL; 12031408cc1fSYuval Mintz } else { 12041408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 12051408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 12061408cc1fSYuval Mintz num, vf_id); 12071408cc1fSYuval Mintz } 12081408cc1fSYuval Mintz 12091408cc1fSYuval Mintz return rc; 12101408cc1fSYuval Mintz } 12111408cc1fSYuval Mintz 1212fe56b9e6SYuval Mintz int 1213fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 1214fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1215fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 1216fe56b9e6SYuval Mintz { 12175529bad9STomer Tayar struct drv_version_stc *p_drv_version; 12185529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 12195529bad9STomer Tayar union drv_union_data union_data; 12205529bad9STomer Tayar __be32 val; 12215529bad9STomer Tayar u32 i; 12225529bad9STomer Tayar int rc; 1223fe56b9e6SYuval Mintz 12245529bad9STomer Tayar p_drv_version = &union_data.drv_version; 12255529bad9STomer Tayar p_drv_version->version = p_ver->version; 12264b01e519SManish Chopra 122767a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 122867a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 12294b01e519SManish Chopra *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val; 1230fe56b9e6SYuval Mintz } 1231fe56b9e6SYuval Mintz 12325529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 12335529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 12345529bad9STomer Tayar mb_params.p_data_src = &union_data; 12355529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 12365529bad9STomer Tayar if (rc) 1237fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1238fe56b9e6SYuval Mintz 12395529bad9STomer Tayar return rc; 1240fe56b9e6SYuval Mintz } 124191420b83SSudarsana Kalluru 12424102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 12434102426fSTomer Tayar { 12444102426fSTomer Tayar u32 resp = 0, param = 0; 12454102426fSTomer Tayar int rc; 12464102426fSTomer Tayar 12474102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 12484102426fSTomer Tayar ¶m); 12494102426fSTomer Tayar if (rc) 12504102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 12514102426fSTomer Tayar 12524102426fSTomer Tayar return rc; 12534102426fSTomer Tayar } 12544102426fSTomer Tayar 12554102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 12564102426fSTomer Tayar { 12574102426fSTomer Tayar u32 value, cpu_mode; 12584102426fSTomer Tayar 12594102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 12604102426fSTomer Tayar 12614102426fSTomer Tayar value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 12624102426fSTomer Tayar value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 12634102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 12644102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 12654102426fSTomer Tayar 12664102426fSTomer Tayar return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 12674102426fSTomer Tayar } 12684102426fSTomer Tayar 12690fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 12700fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 12710fefbfbaSSudarsana Kalluru enum qed_ov_client client) 12720fefbfbaSSudarsana Kalluru { 12730fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 12740fefbfbaSSudarsana Kalluru u32 drv_mb_param; 12750fefbfbaSSudarsana Kalluru int rc; 12760fefbfbaSSudarsana Kalluru 12770fefbfbaSSudarsana Kalluru switch (client) { 12780fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 12790fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 12800fefbfbaSSudarsana Kalluru break; 12810fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 12820fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 12830fefbfbaSSudarsana Kalluru break; 12840fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 12850fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 12860fefbfbaSSudarsana Kalluru break; 12870fefbfbaSSudarsana Kalluru default: 12880fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 12890fefbfbaSSudarsana Kalluru return -EINVAL; 12900fefbfbaSSudarsana Kalluru } 12910fefbfbaSSudarsana Kalluru 12920fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 12930fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 12940fefbfbaSSudarsana Kalluru if (rc) 12950fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 12960fefbfbaSSudarsana Kalluru 12970fefbfbaSSudarsana Kalluru return rc; 12980fefbfbaSSudarsana Kalluru } 12990fefbfbaSSudarsana Kalluru 13000fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 13010fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 13020fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 13030fefbfbaSSudarsana Kalluru { 13040fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 13050fefbfbaSSudarsana Kalluru u32 drv_mb_param; 13060fefbfbaSSudarsana Kalluru int rc; 13070fefbfbaSSudarsana Kalluru 13080fefbfbaSSudarsana Kalluru switch (drv_state) { 13090fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 13100fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 13110fefbfbaSSudarsana Kalluru break; 13120fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 13130fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 13140fefbfbaSSudarsana Kalluru break; 13150fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 13160fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 13170fefbfbaSSudarsana Kalluru break; 13180fefbfbaSSudarsana Kalluru default: 13190fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 13200fefbfbaSSudarsana Kalluru return -EINVAL; 13210fefbfbaSSudarsana Kalluru } 13220fefbfbaSSudarsana Kalluru 13230fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 13240fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 13250fefbfbaSSudarsana Kalluru if (rc) 13260fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 13270fefbfbaSSudarsana Kalluru 13280fefbfbaSSudarsana Kalluru return rc; 13290fefbfbaSSudarsana Kalluru } 13300fefbfbaSSudarsana Kalluru 13310fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 13320fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 13330fefbfbaSSudarsana Kalluru { 13340fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 13350fefbfbaSSudarsana Kalluru u32 drv_mb_param; 13360fefbfbaSSudarsana Kalluru int rc; 13370fefbfbaSSudarsana Kalluru 13380fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 13390fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 13400fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 13410fefbfbaSSudarsana Kalluru if (rc) 13420fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 13430fefbfbaSSudarsana Kalluru 13440fefbfbaSSudarsana Kalluru return rc; 13450fefbfbaSSudarsana Kalluru } 13460fefbfbaSSudarsana Kalluru 13470fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 13480fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 13490fefbfbaSSudarsana Kalluru { 13500fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 13510fefbfbaSSudarsana Kalluru union drv_union_data union_data; 13520fefbfbaSSudarsana Kalluru int rc; 13530fefbfbaSSudarsana Kalluru 13540fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 13550fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 13560fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 13570fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 13580fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 13590fefbfbaSSudarsana Kalluru ether_addr_copy(&union_data.raw_data[0], mac); 13600fefbfbaSSudarsana Kalluru mb_params.p_data_src = &union_data; 13610fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 13620fefbfbaSSudarsana Kalluru if (rc) 13630fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 13640fefbfbaSSudarsana Kalluru 136514d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 136614d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 136714d39648SMintz, Yuval 13680fefbfbaSSudarsana Kalluru return rc; 13690fefbfbaSSudarsana Kalluru } 13700fefbfbaSSudarsana Kalluru 13710fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 13720fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 13730fefbfbaSSudarsana Kalluru { 13740fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 13750fefbfbaSSudarsana Kalluru u32 drv_mb_param; 13760fefbfbaSSudarsana Kalluru int rc; 13770fefbfbaSSudarsana Kalluru 137814d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 137914d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 138014d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 138114d39648SMintz, Yuval return -EINVAL; 138214d39648SMintz, Yuval } 138314d39648SMintz, Yuval 13840fefbfbaSSudarsana Kalluru switch (wol) { 13850fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 13860fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 13870fefbfbaSSudarsana Kalluru break; 13880fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 13890fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 13900fefbfbaSSudarsana Kalluru break; 13910fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 13920fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 13930fefbfbaSSudarsana Kalluru break; 13940fefbfbaSSudarsana Kalluru default: 13950fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 13960fefbfbaSSudarsana Kalluru return -EINVAL; 13970fefbfbaSSudarsana Kalluru } 13980fefbfbaSSudarsana Kalluru 13990fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 14000fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 14010fefbfbaSSudarsana Kalluru if (rc) 14020fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 14030fefbfbaSSudarsana Kalluru 140414d39648SMintz, Yuval /* Store the WoL update for a future unload */ 140514d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 140614d39648SMintz, Yuval 14070fefbfbaSSudarsana Kalluru return rc; 14080fefbfbaSSudarsana Kalluru } 14090fefbfbaSSudarsana Kalluru 14100fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 14110fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 14120fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 14130fefbfbaSSudarsana Kalluru { 14140fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 14150fefbfbaSSudarsana Kalluru u32 drv_mb_param; 14160fefbfbaSSudarsana Kalluru int rc; 14170fefbfbaSSudarsana Kalluru 14180fefbfbaSSudarsana Kalluru switch (eswitch) { 14190fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 14200fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 14210fefbfbaSSudarsana Kalluru break; 14220fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 14230fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 14240fefbfbaSSudarsana Kalluru break; 14250fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 14260fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 14270fefbfbaSSudarsana Kalluru break; 14280fefbfbaSSudarsana Kalluru default: 14290fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 14300fefbfbaSSudarsana Kalluru return -EINVAL; 14310fefbfbaSSudarsana Kalluru } 14320fefbfbaSSudarsana Kalluru 14330fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 14340fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 14350fefbfbaSSudarsana Kalluru if (rc) 14360fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 14370fefbfbaSSudarsana Kalluru 14380fefbfbaSSudarsana Kalluru return rc; 14390fefbfbaSSudarsana Kalluru } 14400fefbfbaSSudarsana Kalluru 14411a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 14421a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 144391420b83SSudarsana Kalluru { 144491420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 144591420b83SSudarsana Kalluru int rc; 144691420b83SSudarsana Kalluru 144791420b83SSudarsana Kalluru switch (mode) { 144891420b83SSudarsana Kalluru case QED_LED_MODE_ON: 144991420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 145091420b83SSudarsana Kalluru break; 145191420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 145291420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 145391420b83SSudarsana Kalluru break; 145491420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 145591420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 145691420b83SSudarsana Kalluru break; 145791420b83SSudarsana Kalluru default: 145891420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 145991420b83SSudarsana Kalluru return -EINVAL; 146091420b83SSudarsana Kalluru } 146191420b83SSudarsana Kalluru 146291420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 146391420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 146491420b83SSudarsana Kalluru 146591420b83SSudarsana Kalluru return rc; 146691420b83SSudarsana Kalluru } 146703dc76caSSudarsana Reddy Kalluru 14684102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 14694102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 14704102426fSTomer Tayar { 14714102426fSTomer Tayar u32 resp = 0, param = 0; 14724102426fSTomer Tayar int rc; 14734102426fSTomer Tayar 14744102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 14754102426fSTomer Tayar mask_parities, &resp, ¶m); 14764102426fSTomer Tayar 14774102426fSTomer Tayar if (rc) { 14784102426fSTomer Tayar DP_ERR(p_hwfn, 14794102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 14804102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 14814102426fSTomer Tayar DP_ERR(p_hwfn, 14824102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 14834102426fSTomer Tayar rc = -EINVAL; 14844102426fSTomer Tayar } 14854102426fSTomer Tayar 14864102426fSTomer Tayar return rc; 14874102426fSTomer Tayar } 14884102426fSTomer Tayar 14897a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 14907a4b21b7SMintz, Yuval { 14917a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 14927a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 14937a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 14947a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 14957a4b21b7SMintz, Yuval int rc = 0; 14967a4b21b7SMintz, Yuval 14977a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 14987a4b21b7SMintz, Yuval if (!p_ptt) 14997a4b21b7SMintz, Yuval return -EBUSY; 15007a4b21b7SMintz, Yuval 15017a4b21b7SMintz, Yuval while (bytes_left > 0) { 15027a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 15037a4b21b7SMintz, Yuval 15047a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 15057a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 15067a4b21b7SMintz, Yuval addr + offset + 15077a4b21b7SMintz, Yuval (bytes_to_copy << 15087a4b21b7SMintz, Yuval DRV_MB_PARAM_NVM_LEN_SHIFT), 15097a4b21b7SMintz, Yuval &resp, &resp_param, 15107a4b21b7SMintz, Yuval &read_len, 15117a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 15127a4b21b7SMintz, Yuval 15137a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 15147a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 15157a4b21b7SMintz, Yuval break; 15167a4b21b7SMintz, Yuval } 15177a4b21b7SMintz, Yuval 15187a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 15197a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 15207a4b21b7SMintz, Yuval */ 15217a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 15227a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 15237a4b21b7SMintz, Yuval usleep_range(1000, 2000); 15247a4b21b7SMintz, Yuval 15257a4b21b7SMintz, Yuval offset += read_len; 15267a4b21b7SMintz, Yuval bytes_left -= read_len; 15277a4b21b7SMintz, Yuval } 15287a4b21b7SMintz, Yuval 15297a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 15307a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 15317a4b21b7SMintz, Yuval 15327a4b21b7SMintz, Yuval return rc; 15337a4b21b7SMintz, Yuval } 15347a4b21b7SMintz, Yuval 153503dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 153603dc76caSSudarsana Reddy Kalluru { 153703dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 153803dc76caSSudarsana Reddy Kalluru int rc = 0; 153903dc76caSSudarsana Reddy Kalluru 154003dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 154103dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 154203dc76caSSudarsana Reddy Kalluru 154303dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 154403dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 154503dc76caSSudarsana Reddy Kalluru 154603dc76caSSudarsana Reddy Kalluru if (rc) 154703dc76caSSudarsana Reddy Kalluru return rc; 154803dc76caSSudarsana Reddy Kalluru 154903dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 155003dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 155103dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 155203dc76caSSudarsana Reddy Kalluru 155303dc76caSSudarsana Reddy Kalluru return rc; 155403dc76caSSudarsana Reddy Kalluru } 155503dc76caSSudarsana Reddy Kalluru 155603dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 155703dc76caSSudarsana Reddy Kalluru { 155803dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 155903dc76caSSudarsana Reddy Kalluru int rc = 0; 156003dc76caSSudarsana Reddy Kalluru 156103dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 156203dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 156303dc76caSSudarsana Reddy Kalluru 156403dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 156503dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 156603dc76caSSudarsana Reddy Kalluru 156703dc76caSSudarsana Reddy Kalluru if (rc) 156803dc76caSSudarsana Reddy Kalluru return rc; 156903dc76caSSudarsana Reddy Kalluru 157003dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 157103dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 157203dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 157303dc76caSSudarsana Reddy Kalluru 157403dc76caSSudarsana Reddy Kalluru return rc; 157503dc76caSSudarsana Reddy Kalluru } 15767a4b21b7SMintz, Yuval 15777a4b21b7SMintz, Yuval int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn, 15787a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 15797a4b21b7SMintz, Yuval u32 *num_images) 15807a4b21b7SMintz, Yuval { 15817a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 15827a4b21b7SMintz, Yuval int rc = 0; 15837a4b21b7SMintz, Yuval 15847a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 15857a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 15867a4b21b7SMintz, Yuval 15877a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 15887a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 15897a4b21b7SMintz, Yuval if (rc) 15907a4b21b7SMintz, Yuval return rc; 15917a4b21b7SMintz, Yuval 15927a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 15937a4b21b7SMintz, Yuval rc = -EINVAL; 15947a4b21b7SMintz, Yuval 15957a4b21b7SMintz, Yuval return rc; 15967a4b21b7SMintz, Yuval } 15977a4b21b7SMintz, Yuval 15987a4b21b7SMintz, Yuval int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn, 15997a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 16007a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 16017a4b21b7SMintz, Yuval u32 image_index) 16027a4b21b7SMintz, Yuval { 16037a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 16047a4b21b7SMintz, Yuval int rc; 16057a4b21b7SMintz, Yuval 16067a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 16077a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 16087a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 16097a4b21b7SMintz, Yuval 16107a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 16117a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 16127a4b21b7SMintz, Yuval &resp, &resp_param, 16137a4b21b7SMintz, Yuval &buf_size, 16147a4b21b7SMintz, Yuval (u32 *)p_image_att); 16157a4b21b7SMintz, Yuval if (rc) 16167a4b21b7SMintz, Yuval return rc; 16177a4b21b7SMintz, Yuval 16187a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 16197a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 16207a4b21b7SMintz, Yuval rc = -EINVAL; 16217a4b21b7SMintz, Yuval 16227a4b21b7SMintz, Yuval return rc; 16237a4b21b7SMintz, Yuval } 1624