1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 4339651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 44fe56b9e6SYuval Mintz #include "qed_hsi.h" 45fe56b9e6SYuval Mintz #include "qed_hw.h" 46fe56b9e6SYuval Mintz #include "qed_mcp.h" 47fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 481408cc1fSYuval Mintz #include "qed_sriov.h" 491408cc1fSYuval Mintz 50fe56b9e6SYuval Mintz #define CHIP_MCP_RESP_ITER_US 10 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 53fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 56fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 57fe56b9e6SYuval Mintz _val) 58fe56b9e6SYuval Mintz 59fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 60fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 61fe56b9e6SYuval Mintz 62fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 63fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 64fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 67fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 68fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 69fe56b9e6SYuval Mintz 70fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 71fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 72fe56b9e6SYuval Mintz 73fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 74fe56b9e6SYuval Mintz 75fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 76fe56b9e6SYuval Mintz { 77fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 78fe56b9e6SYuval Mintz return false; 79fe56b9e6SYuval Mintz return true; 80fe56b9e6SYuval Mintz } 81fe56b9e6SYuval Mintz 821a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 83fe56b9e6SYuval Mintz { 84fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 85fe56b9e6SYuval Mintz PUBLIC_PORT); 86fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 89fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 90fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 91fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 92fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 93fe56b9e6SYuval Mintz } 94fe56b9e6SYuval Mintz 951a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 96fe56b9e6SYuval Mintz { 97fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 98fe56b9e6SYuval Mintz u32 tmp, i; 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 101fe56b9e6SYuval Mintz return; 102fe56b9e6SYuval Mintz 103fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 104fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 105fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 106fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 107fe56b9e6SYuval Mintz 108fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 109fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 110fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 111fe56b9e6SYuval Mintz } 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz 1144ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1154ed1eea8STomer Tayar struct list_head list; 1164ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1174ed1eea8STomer Tayar u16 expected_seq_num; 1184ed1eea8STomer Tayar bool b_is_completed; 1194ed1eea8STomer Tayar }; 1204ed1eea8STomer Tayar 1214ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1224ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1234ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1244ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1254ed1eea8STomer Tayar u16 expected_seq_num) 1264ed1eea8STomer Tayar { 1274ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1284ed1eea8STomer Tayar 1294ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1304ed1eea8STomer Tayar if (!p_cmd_elem) 1314ed1eea8STomer Tayar goto out; 1324ed1eea8STomer Tayar 1334ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1344ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1354ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1364ed1eea8STomer Tayar out: 1374ed1eea8STomer Tayar return p_cmd_elem; 1384ed1eea8STomer Tayar } 1394ed1eea8STomer Tayar 1404ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1414ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1424ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1434ed1eea8STomer Tayar { 1444ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1454ed1eea8STomer Tayar kfree(p_cmd_elem); 1464ed1eea8STomer Tayar } 1474ed1eea8STomer Tayar 1484ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1494ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1504ed1eea8STomer Tayar u16 seq_num) 1514ed1eea8STomer Tayar { 1524ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1534ed1eea8STomer Tayar 1544ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1554ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1564ed1eea8STomer Tayar return p_cmd_elem; 1574ed1eea8STomer Tayar } 1584ed1eea8STomer Tayar 1594ed1eea8STomer Tayar return NULL; 1604ed1eea8STomer Tayar } 1614ed1eea8STomer Tayar 162fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 163fe56b9e6SYuval Mintz { 164fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1654ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1664ed1eea8STomer Tayar 167fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 168fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1694ed1eea8STomer Tayar 1704ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1714ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1724ed1eea8STomer Tayar p_tmp, 1734ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1744ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 175fe56b9e6SYuval Mintz } 1764ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1774ed1eea8STomer Tayar } 1784ed1eea8STomer Tayar 179fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz return 0; 182fe56b9e6SYuval Mintz } 183fe56b9e6SYuval Mintz 1841a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 185fe56b9e6SYuval Mintz { 186fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 187fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 188fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 191fe56b9e6SYuval Mintz if (!p_info->public_base) 192fe56b9e6SYuval Mintz return 0; 193fe56b9e6SYuval Mintz 194fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 195fe56b9e6SYuval Mintz 196fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 197fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 198fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 199fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 200fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 201fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 202fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 203fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz /* Set the MFW MB address */ 206fe56b9e6SYuval Mintz mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 207fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 208fe56b9e6SYuval Mintz PUBLIC_MFW_MB)); 209fe56b9e6SYuval Mintz p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 210fe56b9e6SYuval Mintz p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 211fe56b9e6SYuval Mintz 212fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 213fe56b9e6SYuval Mintz * the first command 214fe56b9e6SYuval Mintz */ 215fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 216fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 217fe56b9e6SYuval Mintz 218fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 219fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 220fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 221fe56b9e6SYuval Mintz 2224ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 223fe56b9e6SYuval Mintz 224fe56b9e6SYuval Mintz return 0; 225fe56b9e6SYuval Mintz } 226fe56b9e6SYuval Mintz 2271a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 228fe56b9e6SYuval Mintz { 229fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 230fe56b9e6SYuval Mintz u32 size; 231fe56b9e6SYuval Mintz 232fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 23360fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 234fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 235fe56b9e6SYuval Mintz goto err; 236fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 237fe56b9e6SYuval Mintz 2384ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2394ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2404ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2414ed1eea8STomer Tayar 2424ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2434ed1eea8STomer Tayar 244fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 245fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 246fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 247fe56b9e6SYuval Mintz * the MCP is not initialized 248fe56b9e6SYuval Mintz */ 249fe56b9e6SYuval Mintz return 0; 250fe56b9e6SYuval Mintz } 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 25360fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 25483aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 255fe56b9e6SYuval Mintz if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr) 256fe56b9e6SYuval Mintz goto err; 257fe56b9e6SYuval Mintz 258fe56b9e6SYuval Mintz return 0; 259fe56b9e6SYuval Mintz 260fe56b9e6SYuval Mintz err: 261fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 262fe56b9e6SYuval Mintz return -ENOMEM; 263fe56b9e6SYuval Mintz } 264fe56b9e6SYuval Mintz 2654ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 2664ed1eea8STomer Tayar struct qed_ptt *p_ptt) 2675529bad9STomer Tayar { 2684ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2695529bad9STomer Tayar 2704ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 2714ed1eea8STomer Tayar * time and now. 2725529bad9STomer Tayar */ 2734ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 2744ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 2754ed1eea8STomer Tayar QED_MSG_SP, 2764ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 2774ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 2785529bad9STomer Tayar 2794ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 2804ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2815529bad9STomer Tayar } 2825529bad9STomer Tayar } 2835529bad9STomer Tayar 2841a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 285fe56b9e6SYuval Mintz { 2864ed1eea8STomer Tayar u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0; 287fe56b9e6SYuval Mintz int rc = 0; 288fe56b9e6SYuval Mintz 2894ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 2904ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 2914ed1eea8STomer Tayar 2924ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 2935529bad9STomer Tayar 294fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 2954ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 2964ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 2974ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 298fe56b9e6SYuval Mintz 299fe56b9e6SYuval Mintz do { 300fe56b9e6SYuval Mintz /* Wait for MFW response */ 301fe56b9e6SYuval Mintz udelay(delay); 302fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 303fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 304fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 305fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 306fe56b9e6SYuval Mintz 307fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 308fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 309fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 310fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 311fe56b9e6SYuval Mintz } else { 312fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 313fe56b9e6SYuval Mintz rc = -EAGAIN; 314fe56b9e6SYuval Mintz } 315fe56b9e6SYuval Mintz 3164ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3175529bad9STomer Tayar 318fe56b9e6SYuval Mintz return rc; 319fe56b9e6SYuval Mintz } 320fe56b9e6SYuval Mintz 3214ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3224ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 323fe56b9e6SYuval Mintz { 3244ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3254ed1eea8STomer Tayar 3264ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3274ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3284ed1eea8STomer Tayar */ 3294ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3304ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3314ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3324ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3334ed1eea8STomer Tayar } 3344ed1eea8STomer Tayar 3354ed1eea8STomer Tayar return false; 3364ed1eea8STomer Tayar } 3374ed1eea8STomer Tayar 3384ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3394ed1eea8STomer Tayar static int 3404ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3414ed1eea8STomer Tayar { 3424ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3444ed1eea8STomer Tayar u32 mcp_resp; 3454ed1eea8STomer Tayar u16 seq_num; 3464ed1eea8STomer Tayar 3474ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3484ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3494ed1eea8STomer Tayar 3504ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3514ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3524ed1eea8STomer Tayar return -EAGAIN; 3534ed1eea8STomer Tayar 3544ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3554ed1eea8STomer Tayar if (!p_cmd_elem) { 3564ed1eea8STomer Tayar DP_ERR(p_hwfn, 3574ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3584ed1eea8STomer Tayar seq_num); 3594ed1eea8STomer Tayar return -EINVAL; 3604ed1eea8STomer Tayar } 3614ed1eea8STomer Tayar 3624ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 3634ed1eea8STomer Tayar 3644ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 3654ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 3664ed1eea8STomer Tayar 3674ed1eea8STomer Tayar /* Get the MFW param */ 3684ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 3694ed1eea8STomer Tayar 3704ed1eea8STomer Tayar /* Get the union data */ 3712f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 3724ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3734ed1eea8STomer Tayar offsetof(struct public_drv_mb, 3744ed1eea8STomer Tayar union_data); 3754ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3762f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 3774ed1eea8STomer Tayar } 3784ed1eea8STomer Tayar 3794ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 3804ed1eea8STomer Tayar 3814ed1eea8STomer Tayar return 0; 3824ed1eea8STomer Tayar } 3834ed1eea8STomer Tayar 3844ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3854ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 3864ed1eea8STomer Tayar struct qed_ptt *p_ptt, 3874ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 3884ed1eea8STomer Tayar u16 seq_num) 3894ed1eea8STomer Tayar { 3904ed1eea8STomer Tayar union drv_union_data union_data; 3914ed1eea8STomer Tayar u32 union_data_addr; 3924ed1eea8STomer Tayar 3934ed1eea8STomer Tayar /* Set the union data */ 3944ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3954ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 3964ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 3972f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 3984ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 3992f67af8cSTomer Tayar p_mb_params->data_src_size); 4004ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4014ed1eea8STomer Tayar sizeof(union_data)); 4024ed1eea8STomer Tayar 4034ed1eea8STomer Tayar /* Set the drv param */ 4044ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4054ed1eea8STomer Tayar 4064ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4074ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4084ed1eea8STomer Tayar 4094ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4104ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4114ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4124ed1eea8STomer Tayar } 4134ed1eea8STomer Tayar 4144ed1eea8STomer Tayar static int 4154ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4164ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4174ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4184ed1eea8STomer Tayar u32 max_retries, u32 delay) 4194ed1eea8STomer Tayar { 4204ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4214ed1eea8STomer Tayar u32 cnt = 0; 4224ed1eea8STomer Tayar u16 seq_num; 423fe56b9e6SYuval Mintz int rc = 0; 424fe56b9e6SYuval Mintz 4254ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 426fe56b9e6SYuval Mintz do { 4274ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4284ed1eea8STomer Tayar * pending command is completed during this iteration. 4294ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4304ed1eea8STomer Tayar */ 4314ed1eea8STomer Tayar 4324ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4334ed1eea8STomer Tayar 4344ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 4354ed1eea8STomer Tayar break; 4364ed1eea8STomer Tayar 4374ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4384ed1eea8STomer Tayar if (!rc) 4394ed1eea8STomer Tayar break; 4404ed1eea8STomer Tayar else if (rc != -EAGAIN) 4414ed1eea8STomer Tayar goto err; 4424ed1eea8STomer Tayar 4434ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 444fe56b9e6SYuval Mintz udelay(delay); 4454ed1eea8STomer Tayar } while (++cnt < max_retries); 446fe56b9e6SYuval Mintz 4474ed1eea8STomer Tayar if (cnt >= max_retries) { 4484ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4494ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 4504ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4514ed1eea8STomer Tayar return -EAGAIN; 452fe56b9e6SYuval Mintz } 4534ed1eea8STomer Tayar 4544ed1eea8STomer Tayar /* Send the mailbox command */ 4554ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 4564ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 4574ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 4584ed1eea8STomer Tayar if (!p_cmd_elem) 4594ed1eea8STomer Tayar goto err; 4604ed1eea8STomer Tayar 4614ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 4624ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4634ed1eea8STomer Tayar 4644ed1eea8STomer Tayar /* Wait for the MFW response */ 4654ed1eea8STomer Tayar do { 4664ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 4674ed1eea8STomer Tayar * command is completed during this iteration. 4684ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 4694ed1eea8STomer Tayar */ 4704ed1eea8STomer Tayar 4714ed1eea8STomer Tayar udelay(delay); 4724ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4734ed1eea8STomer Tayar 4744ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 4754ed1eea8STomer Tayar break; 4764ed1eea8STomer Tayar 4774ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 4784ed1eea8STomer Tayar if (!rc) 4794ed1eea8STomer Tayar break; 4804ed1eea8STomer Tayar else if (rc != -EAGAIN) 4814ed1eea8STomer Tayar goto err; 4824ed1eea8STomer Tayar 4834ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4844ed1eea8STomer Tayar } while (++cnt < max_retries); 4854ed1eea8STomer Tayar 4864ed1eea8STomer Tayar if (cnt >= max_retries) { 4874ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 4884ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 4894ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 4904ed1eea8STomer Tayar 4914ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 4924ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 4934ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 4944ed1eea8STomer Tayar 4954ed1eea8STomer Tayar return -EAGAIN; 4964ed1eea8STomer Tayar } 4974ed1eea8STomer Tayar 4984ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 4994ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5024ed1eea8STomer Tayar QED_MSG_SP, 5034ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5044ed1eea8STomer Tayar p_mb_params->mcp_resp, 5054ed1eea8STomer Tayar p_mb_params->mcp_param, 5064ed1eea8STomer Tayar (cnt * delay) / 1000, (cnt * delay) % 1000); 5074ed1eea8STomer Tayar 5084ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5094ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5104ed1eea8STomer Tayar 5114ed1eea8STomer Tayar return 0; 5124ed1eea8STomer Tayar 5134ed1eea8STomer Tayar err: 5144ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 515fe56b9e6SYuval Mintz return rc; 516fe56b9e6SYuval Mintz } 517fe56b9e6SYuval Mintz 5185529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 519fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 5205529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 521fe56b9e6SYuval Mintz { 5222f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 5234ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 5244ed1eea8STomer Tayar u32 delay = CHIP_MCP_RESP_ITER_US; 525fe56b9e6SYuval Mintz 526fe56b9e6SYuval Mintz /* MCP not initialized */ 527fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 528fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 529fe56b9e6SYuval Mintz return -EBUSY; 530fe56b9e6SYuval Mintz } 531fe56b9e6SYuval Mintz 5322f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 5332f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 5342f67af8cSTomer Tayar DP_ERR(p_hwfn, 5352f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 5362f67af8cSTomer Tayar p_mb_params->data_src_size, 5372f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 5382f67af8cSTomer Tayar return -EINVAL; 5392f67af8cSTomer Tayar } 5402f67af8cSTomer Tayar 5414ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 5424ed1eea8STomer Tayar delay); 543fe56b9e6SYuval Mintz } 544fe56b9e6SYuval Mintz 5455529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 5465529bad9STomer Tayar struct qed_ptt *p_ptt, 5475529bad9STomer Tayar u32 cmd, 5485529bad9STomer Tayar u32 param, 5495529bad9STomer Tayar u32 *o_mcp_resp, 5505529bad9STomer Tayar u32 *o_mcp_param) 551fe56b9e6SYuval Mintz { 5525529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 5535529bad9STomer Tayar int rc; 554fe56b9e6SYuval Mintz 5555529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 5565529bad9STomer Tayar mb_params.cmd = cmd; 5575529bad9STomer Tayar mb_params.param = param; 55814d39648SMintz, Yuval 5595529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 5605529bad9STomer Tayar if (rc) 5615529bad9STomer Tayar return rc; 5625529bad9STomer Tayar 5635529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 5645529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 5655529bad9STomer Tayar 5665529bad9STomer Tayar return 0; 567fe56b9e6SYuval Mintz } 568fe56b9e6SYuval Mintz 5694102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 5704102426fSTomer Tayar struct qed_ptt *p_ptt, 5714102426fSTomer Tayar u32 cmd, 5724102426fSTomer Tayar u32 param, 5734102426fSTomer Tayar u32 *o_mcp_resp, 5744102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 5754102426fSTomer Tayar { 5764102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 5772f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 5784102426fSTomer Tayar int rc; 5794102426fSTomer Tayar 5804102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 5814102426fSTomer Tayar mb_params.cmd = cmd; 5824102426fSTomer Tayar mb_params.param = param; 5832f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 5842f67af8cSTomer Tayar 5852f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 5862f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 5872f67af8cSTomer Tayar 5884102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 5894102426fSTomer Tayar if (rc) 5904102426fSTomer Tayar return rc; 5914102426fSTomer Tayar 5924102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 5934102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 5944102426fSTomer Tayar 5954102426fSTomer Tayar *o_txn_size = *o_mcp_param; 5962f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 5974102426fSTomer Tayar 5984102426fSTomer Tayar return 0; 5994102426fSTomer Tayar } 6004102426fSTomer Tayar 601fe56b9e6SYuval Mintz int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 6021a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_load_code) 603fe56b9e6SYuval Mintz { 604fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 6055529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6065529bad9STomer Tayar union drv_union_data union_data; 607fe56b9e6SYuval Mintz int rc; 608fe56b9e6SYuval Mintz 6095529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 610fe56b9e6SYuval Mintz /* Load Request */ 6115529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 6125529bad9STomer Tayar mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT | 6135529bad9STomer Tayar cdev->drv_type; 6145529bad9STomer Tayar memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE); 6155529bad9STomer Tayar mb_params.p_data_src = &union_data; 6162f67af8cSTomer Tayar mb_params.data_src_size = sizeof(union_data.ver_str); 6175529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 618fe56b9e6SYuval Mintz 619fe56b9e6SYuval Mintz /* if mcp fails to respond we must abort */ 620fe56b9e6SYuval Mintz if (rc) { 621fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 622fe56b9e6SYuval Mintz return rc; 623fe56b9e6SYuval Mintz } 624fe56b9e6SYuval Mintz 6255529bad9STomer Tayar *p_load_code = mb_params.mcp_resp; 6265529bad9STomer Tayar 627fe56b9e6SYuval Mintz /* If MFW refused (e.g. other port is in diagnostic mode) we 628fe56b9e6SYuval Mintz * must abort. This can happen in the following cases: 629fe56b9e6SYuval Mintz * - Other port is in diagnostic mode 630fe56b9e6SYuval Mintz * - Previously loaded function on the engine is not compliant with 631fe56b9e6SYuval Mintz * the requester. 632fe56b9e6SYuval Mintz * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION. 633fe56b9e6SYuval Mintz * - 634fe56b9e6SYuval Mintz */ 635fe56b9e6SYuval Mintz if (!(*p_load_code) || 636fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) || 637fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) || 638fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) { 639fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP refused load request, aborting\n"); 640fe56b9e6SYuval Mintz return -EBUSY; 641fe56b9e6SYuval Mintz } 642fe56b9e6SYuval Mintz 643fe56b9e6SYuval Mintz return 0; 644fe56b9e6SYuval Mintz } 645fe56b9e6SYuval Mintz 6461226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 6471226337aSTomer Tayar { 6481226337aSTomer Tayar u32 wol_param, mcp_resp, mcp_param; 6491226337aSTomer Tayar 6501226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 6511226337aSTomer Tayar case QED_OV_WOL_DISABLED: 6521226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 6531226337aSTomer Tayar break; 6541226337aSTomer Tayar case QED_OV_WOL_ENABLED: 6551226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 6561226337aSTomer Tayar break; 6571226337aSTomer Tayar default: 6581226337aSTomer Tayar DP_NOTICE(p_hwfn, 6591226337aSTomer Tayar "Unknown WoL configuration %02x\n", 6601226337aSTomer Tayar p_hwfn->cdev->wol_config); 6611226337aSTomer Tayar /* Fallthrough */ 6621226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 6631226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 6641226337aSTomer Tayar } 6651226337aSTomer Tayar 6661226337aSTomer Tayar return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param, 6671226337aSTomer Tayar &mcp_resp, &mcp_param); 6681226337aSTomer Tayar } 6691226337aSTomer Tayar 6701226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 6711226337aSTomer Tayar { 6721226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 6731226337aSTomer Tayar struct mcp_mac wol_mac; 6741226337aSTomer Tayar 6751226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6761226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 6771226337aSTomer Tayar 6781226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 6791226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 6801226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 6811226337aSTomer Tayar 6821226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 6831226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 6841226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 6851226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 6861226337aSTomer Tayar 6871226337aSTomer Tayar DP_VERBOSE(p_hwfn, 6881226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 6891226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 6901226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 6911226337aSTomer Tayar 6921226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 6931226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 6941226337aSTomer Tayar } 6951226337aSTomer Tayar 6961226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6971226337aSTomer Tayar } 6981226337aSTomer Tayar 6990b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 7000b55e27dSYuval Mintz struct qed_ptt *p_ptt) 7010b55e27dSYuval Mintz { 7020b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 7030b55e27dSYuval Mintz PUBLIC_PATH); 7040b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 7050b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 7060b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 7070b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 7080b55e27dSYuval Mintz int i; 7090b55e27dSYuval Mintz 7100b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 7110b55e27dSYuval Mintz QED_MSG_SP, 7120b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 7130b55e27dSYuval Mintz mfw_path_offsize, path_addr); 7140b55e27dSYuval Mintz 7150b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 7160b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 7170b55e27dSYuval Mintz path_addr + 7180b55e27dSYuval Mintz offsetof(struct public_path, 7190b55e27dSYuval Mintz mcp_vf_disabled) + 7200b55e27dSYuval Mintz sizeof(u32) * i); 7210b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 7220b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 7230b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 7240b55e27dSYuval Mintz } 7250b55e27dSYuval Mintz 7260b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 7270b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 7280b55e27dSYuval Mintz } 7290b55e27dSYuval Mintz 7300b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 7310b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 7320b55e27dSYuval Mintz { 7330b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 7340b55e27dSYuval Mintz PUBLIC_FUNC); 7350b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 7360b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 7370b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 7380b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 7390b55e27dSYuval Mintz int rc; 7400b55e27dSYuval Mintz int i; 7410b55e27dSYuval Mintz 7420b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 7430b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 7440b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 7450b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 7460b55e27dSYuval Mintz 7470b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 7480b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 7492f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 7502f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 7510b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7520b55e27dSYuval Mintz if (rc) { 7530b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 7540b55e27dSYuval Mintz return -EBUSY; 7550b55e27dSYuval Mintz } 7560b55e27dSYuval Mintz 7570b55e27dSYuval Mintz /* Clear the ACK bits */ 7580b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 7590b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 7600b55e27dSYuval Mintz func_addr + 7610b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 7620b55e27dSYuval Mintz i * sizeof(u32), 0); 7630b55e27dSYuval Mintz 7640b55e27dSYuval Mintz return rc; 7650b55e27dSYuval Mintz } 7660b55e27dSYuval Mintz 767334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 768334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 769334c03b5SZvi Nachmani { 770334c03b5SZvi Nachmani u32 transceiver_state; 771334c03b5SZvi Nachmani 772334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 773334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 774334c03b5SZvi Nachmani offsetof(struct public_port, 775334c03b5SZvi Nachmani transceiver_data)); 776334c03b5SZvi Nachmani 777334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 778334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 779334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 780334c03b5SZvi Nachmani transceiver_state, 781334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 7821a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 783334c03b5SZvi Nachmani 784334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 785351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 786334c03b5SZvi Nachmani 787351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 788334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 789334c03b5SZvi Nachmani else 790334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 791334c03b5SZvi Nachmani } 792334c03b5SZvi Nachmani 793cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 7941a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 795cc875c2eSYuval Mintz { 796cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 797a64b02d5SManish Chopra u8 max_bw, min_bw; 798cc875c2eSYuval Mintz u32 status = 0; 799cc875c2eSYuval Mintz 80065ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 80165ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 80265ed2ffdSMintz, Yuval 803cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 804cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 805cc875c2eSYuval Mintz if (!b_reset) { 806cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 807cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 808cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 809cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 810cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 811cc875c2eSYuval Mintz status, 812cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 8131a635e48SYuval Mintz offsetof(struct public_port, link_status))); 814cc875c2eSYuval Mintz } else { 815cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 816cc875c2eSYuval Mintz "Resetting link indications\n"); 81765ed2ffdSMintz, Yuval goto out; 818cc875c2eSYuval Mintz } 819cc875c2eSYuval Mintz 820fc916ff2SSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) 821cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 822fc916ff2SSudarsana Reddy Kalluru else 823fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 824cc875c2eSYuval Mintz 825cc875c2eSYuval Mintz p_link->full_duplex = true; 826cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 827cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 828cc875c2eSYuval Mintz p_link->speed = 100000; 829cc875c2eSYuval Mintz break; 830cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 831cc875c2eSYuval Mintz p_link->speed = 50000; 832cc875c2eSYuval Mintz break; 833cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 834cc875c2eSYuval Mintz p_link->speed = 40000; 835cc875c2eSYuval Mintz break; 836cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 837cc875c2eSYuval Mintz p_link->speed = 25000; 838cc875c2eSYuval Mintz break; 839cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 840cc875c2eSYuval Mintz p_link->speed = 20000; 841cc875c2eSYuval Mintz break; 842cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 843cc875c2eSYuval Mintz p_link->speed = 10000; 844cc875c2eSYuval Mintz break; 845cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 846cc875c2eSYuval Mintz p_link->full_duplex = false; 847cc875c2eSYuval Mintz /* Fall-through */ 848cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 849cc875c2eSYuval Mintz p_link->speed = 1000; 850cc875c2eSYuval Mintz break; 851cc875c2eSYuval Mintz default: 852cc875c2eSYuval Mintz p_link->speed = 0; 853cc875c2eSYuval Mintz } 854cc875c2eSYuval Mintz 8554b01e519SManish Chopra if (p_link->link_up && p_link->speed) 8564b01e519SManish Chopra p_link->line_speed = p_link->speed; 8574b01e519SManish Chopra else 8584b01e519SManish Chopra p_link->line_speed = 0; 8594b01e519SManish Chopra 8604b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 861a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 8624b01e519SManish Chopra 863a64b02d5SManish Chopra /* Max bandwidth configuration */ 8644b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 865cc875c2eSYuval Mintz 866a64b02d5SManish Chopra /* Min bandwidth configuration */ 867a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 8686f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 8696f437d43SMintz, Yuval p_link->min_pf_rate); 870a64b02d5SManish Chopra 871cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 872cc875c2eSYuval Mintz p_link->an_complete = !!(status & 873cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 874cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 875cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 876cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 877cc875c2eSYuval Mintz 878cc875c2eSYuval Mintz p_link->partner_adv_speed |= 879cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 880cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 881cc875c2eSYuval Mintz p_link->partner_adv_speed |= 882cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 883cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 884cc875c2eSYuval Mintz p_link->partner_adv_speed |= 885cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 886cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 887cc875c2eSYuval Mintz p_link->partner_adv_speed |= 888cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 889cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 890cc875c2eSYuval Mintz p_link->partner_adv_speed |= 891054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 892054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 893054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 894cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 895cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 896cc875c2eSYuval Mintz p_link->partner_adv_speed |= 897cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 898cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 899cc875c2eSYuval Mintz p_link->partner_adv_speed |= 900cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 901cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 902cc875c2eSYuval Mintz 903cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 904cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 905cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 906cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 907cc875c2eSYuval Mintz 908cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 909cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 910cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 911cc875c2eSYuval Mintz break; 912cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 913cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 914cc875c2eSYuval Mintz break; 915cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 916cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 917cc875c2eSYuval Mintz break; 918cc875c2eSYuval Mintz default: 919cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 920cc875c2eSYuval Mintz } 921cc875c2eSYuval Mintz 922cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 923cc875c2eSYuval Mintz 924cc875c2eSYuval Mintz qed_link_update(p_hwfn); 92565ed2ffdSMintz, Yuval out: 92665ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 927cc875c2eSYuval Mintz } 928cc875c2eSYuval Mintz 929351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 930cc875c2eSYuval Mintz { 931cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 9325529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 9332f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 934cc875c2eSYuval Mintz int rc = 0; 9355529bad9STomer Tayar u32 cmd; 936cc875c2eSYuval Mintz 937cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 9382f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 939cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 940cc875c2eSYuval Mintz if (!params->speed.autoneg) 9412f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 9422f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 9432f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 9442f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 9452f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 9462f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 947cc875c2eSYuval Mintz 948fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 949fc916ff2SSudarsana Reddy Kalluru 950cc875c2eSYuval Mintz if (b_up) { 951cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 952cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 9532f67af8cSTomer Tayar phy_cfg.speed, 9542f67af8cSTomer Tayar phy_cfg.pause, 9552f67af8cSTomer Tayar phy_cfg.adv_speed, 9562f67af8cSTomer Tayar phy_cfg.loopback_mode, 9572f67af8cSTomer Tayar phy_cfg.feature_config_flags); 958cc875c2eSYuval Mintz } else { 959cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 960cc875c2eSYuval Mintz "Resetting link\n"); 961cc875c2eSYuval Mintz } 962cc875c2eSYuval Mintz 9635529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 9645529bad9STomer Tayar mb_params.cmd = cmd; 9652f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 9662f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 9675529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 968cc875c2eSYuval Mintz 969cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 970cc875c2eSYuval Mintz if (rc) { 971cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 972cc875c2eSYuval Mintz return rc; 973cc875c2eSYuval Mintz } 974cc875c2eSYuval Mintz 97565ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 97665ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 97765ed2ffdSMintz, Yuval * an attention. 97865ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 97965ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 98065ed2ffdSMintz, Yuval */ 98165ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 982cc875c2eSYuval Mintz 983cc875c2eSYuval Mintz return 0; 984cc875c2eSYuval Mintz } 985cc875c2eSYuval Mintz 9866c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 9876c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 9886c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 9896c754246SSudarsana Reddy Kalluru { 9906c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 9916c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 9926c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 9936c754246SSudarsana Reddy Kalluru u32 hsi_param; 9946c754246SSudarsana Reddy Kalluru 9956c754246SSudarsana Reddy Kalluru switch (type) { 9966c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 9976c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 9986c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 9996c754246SSudarsana Reddy Kalluru break; 10006c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 10016c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 10026c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 10036c754246SSudarsana Reddy Kalluru break; 10046c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 10056c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 10066c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 10076c754246SSudarsana Reddy Kalluru break; 10086c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 10096c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 10106c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 10116c754246SSudarsana Reddy Kalluru break; 10126c754246SSudarsana Reddy Kalluru default: 10136c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 10146c754246SSudarsana Reddy Kalluru return; 10156c754246SSudarsana Reddy Kalluru } 10166c754246SSudarsana Reddy Kalluru 10176c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 10186c754246SSudarsana Reddy Kalluru 10196c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 10206c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 10216c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 10222f67af8cSTomer Tayar mb_params.p_data_src = &stats; 10232f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 10246c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 10256c754246SSudarsana Reddy Kalluru } 10266c754246SSudarsana Reddy Kalluru 10274b01e519SManish Chopra static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 10284b01e519SManish Chopra struct public_func *p_shmem_info) 10294b01e519SManish Chopra { 10304b01e519SManish Chopra struct qed_mcp_function_info *p_info; 10314b01e519SManish Chopra 10324b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 10334b01e519SManish Chopra 10344b01e519SManish Chopra p_info->bandwidth_min = (p_shmem_info->config & 10354b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_MASK) >> 10364b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_SHIFT; 10374b01e519SManish Chopra if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 10384b01e519SManish Chopra DP_INFO(p_hwfn, 10394b01e519SManish Chopra "bandwidth minimum out of bounds [%02x]. Set to 1\n", 10404b01e519SManish Chopra p_info->bandwidth_min); 10414b01e519SManish Chopra p_info->bandwidth_min = 1; 10424b01e519SManish Chopra } 10434b01e519SManish Chopra 10444b01e519SManish Chopra p_info->bandwidth_max = (p_shmem_info->config & 10454b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_MASK) >> 10464b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_SHIFT; 10474b01e519SManish Chopra if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 10484b01e519SManish Chopra DP_INFO(p_hwfn, 10494b01e519SManish Chopra "bandwidth maximum out of bounds [%02x]. Set to 100\n", 10504b01e519SManish Chopra p_info->bandwidth_max); 10514b01e519SManish Chopra p_info->bandwidth_max = 100; 10524b01e519SManish Chopra } 10534b01e519SManish Chopra } 10544b01e519SManish Chopra 10554b01e519SManish Chopra static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 10564b01e519SManish Chopra struct qed_ptt *p_ptt, 10571a635e48SYuval Mintz struct public_func *p_data, int pfid) 10584b01e519SManish Chopra { 10594b01e519SManish Chopra u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 10604b01e519SManish Chopra PUBLIC_FUNC); 10614b01e519SManish Chopra u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 10624b01e519SManish Chopra u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 10634b01e519SManish Chopra u32 i, size; 10644b01e519SManish Chopra 10654b01e519SManish Chopra memset(p_data, 0, sizeof(*p_data)); 10664b01e519SManish Chopra 10671a635e48SYuval Mintz size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 10684b01e519SManish Chopra for (i = 0; i < size / sizeof(u32); i++) 10694b01e519SManish Chopra ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 10704b01e519SManish Chopra func_addr + (i << 2)); 10714b01e519SManish Chopra return size; 10724b01e519SManish Chopra } 10734b01e519SManish Chopra 10741a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10754b01e519SManish Chopra { 10764b01e519SManish Chopra struct qed_mcp_function_info *p_info; 10774b01e519SManish Chopra struct public_func shmem_info; 10784b01e519SManish Chopra u32 resp = 0, param = 0; 10794b01e519SManish Chopra 10801a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 10814b01e519SManish Chopra 10824b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 10834b01e519SManish Chopra 10844b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 10854b01e519SManish Chopra 1086a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 10874b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 10884b01e519SManish Chopra 10894b01e519SManish Chopra /* Acknowledge the MFW */ 10904b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 10914b01e519SManish Chopra ¶m); 10924b01e519SManish Chopra } 10934b01e519SManish Chopra 1094cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1095cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1096cc875c2eSYuval Mintz { 1097cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1098cc875c2eSYuval Mintz int rc = 0; 1099cc875c2eSYuval Mintz bool found = false; 1100cc875c2eSYuval Mintz u16 i; 1101cc875c2eSYuval Mintz 1102cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1103cc875c2eSYuval Mintz 1104cc875c2eSYuval Mintz /* Read Messages from MFW */ 1105cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1106cc875c2eSYuval Mintz 1107cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1108cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1109cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1110cc875c2eSYuval Mintz continue; 1111cc875c2eSYuval Mintz 1112cc875c2eSYuval Mintz found = true; 1113cc875c2eSYuval Mintz 1114cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1115cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1116cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1117cc875c2eSYuval Mintz 1118cc875c2eSYuval Mintz switch (i) { 1119cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1120cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1121cc875c2eSYuval Mintz break; 11220b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 11230b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 11240b55e27dSYuval Mintz break; 112539651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 112639651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 112739651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 112839651abdSSudarsana Reddy Kalluru break; 112939651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 113039651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 113139651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 113239651abdSSudarsana Reddy Kalluru break; 113339651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 113439651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 113539651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 113639651abdSSudarsana Reddy Kalluru break; 1137334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1138334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1139334c03b5SZvi Nachmani break; 11406c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 11416c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 11426c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 11436c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 11446c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 11456c754246SSudarsana Reddy Kalluru break; 11464b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 11474b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 11484b01e519SManish Chopra break; 1149cc875c2eSYuval Mintz default: 115039815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1151cc875c2eSYuval Mintz rc = -EINVAL; 1152cc875c2eSYuval Mintz } 1153cc875c2eSYuval Mintz } 1154cc875c2eSYuval Mintz 1155cc875c2eSYuval Mintz /* ACK everything */ 1156cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1157cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1158cc875c2eSYuval Mintz 1159cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1160cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1161cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1162cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1163cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1164cc875c2eSYuval Mintz (__force u32)val); 1165cc875c2eSYuval Mintz } 1166cc875c2eSYuval Mintz 1167cc875c2eSYuval Mintz if (!found) { 1168cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1169cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1170cc875c2eSYuval Mintz rc = -EINVAL; 1171cc875c2eSYuval Mintz } 1172cc875c2eSYuval Mintz 1173cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1174cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1175cc875c2eSYuval Mintz 1176cc875c2eSYuval Mintz return rc; 1177cc875c2eSYuval Mintz } 1178cc875c2eSYuval Mintz 11791408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 11801408cc1fSYuval Mintz struct qed_ptt *p_ptt, 11811408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1182fe56b9e6SYuval Mintz { 1183fe56b9e6SYuval Mintz u32 global_offsize; 1184fe56b9e6SYuval Mintz 11851408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 11861408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 11871408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 11881408cc1fSYuval Mintz 11891408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 11901408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 11911408cc1fSYuval Mintz return 0; 11921408cc1fSYuval Mintz } else { 11931408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 11941408cc1fSYuval Mintz QED_MSG_IOV, 11951408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 11961408cc1fSYuval Mintz return -EINVAL; 11971408cc1fSYuval Mintz } 11981408cc1fSYuval Mintz } 1199fe56b9e6SYuval Mintz 1200fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 12011408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 12021408cc1fSYuval Mintz mcp_info->public_base, 1203fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 12041408cc1fSYuval Mintz *p_mfw_ver = 12051408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 12061408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 12071408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1208fe56b9e6SYuval Mintz 12091408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 12101408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 12111408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 12121408cc1fSYuval Mintz offsetof(struct public_global, 12131408cc1fSYuval Mintz running_bundle_id)); 12141408cc1fSYuval Mintz } 1215fe56b9e6SYuval Mintz 1216fe56b9e6SYuval Mintz return 0; 1217fe56b9e6SYuval Mintz } 1218fe56b9e6SYuval Mintz 12191a635e48SYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 1220cc875c2eSYuval Mintz { 1221cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 1222cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 1223cc875c2eSYuval Mintz 12241408cc1fSYuval Mintz if (IS_VF(cdev)) 12251408cc1fSYuval Mintz return -EINVAL; 12261408cc1fSYuval Mintz 1227cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1228cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1229cc875c2eSYuval Mintz return -EBUSY; 1230cc875c2eSYuval Mintz } 1231cc875c2eSYuval Mintz 1232cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1233cc875c2eSYuval Mintz 1234cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 1235cc875c2eSYuval Mintz if (!p_ptt) 1236cc875c2eSYuval Mintz return -EBUSY; 1237cc875c2eSYuval Mintz 1238cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1239cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 1240cc875c2eSYuval Mintz 1241cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 1242cc875c2eSYuval Mintz 1243cc875c2eSYuval Mintz return 0; 1244cc875c2eSYuval Mintz } 1245cc875c2eSYuval Mintz 12466927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 12476927e826SMintz, Yuval static void 12486927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 12496927e826SMintz, Yuval enum qed_pci_personality *p_proto) 12506927e826SMintz, Yuval { 12516927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 12526927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 12536927e826SMintz, Yuval */ 12546927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 12556927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 12566927e826SMintz, Yuval else 12576927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 12586927e826SMintz, Yuval 12596927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 12606927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 12616927e826SMintz, Yuval (u32) *p_proto); 12626927e826SMintz, Yuval } 12636927e826SMintz, Yuval 12646927e826SMintz, Yuval static int 12656927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 12666927e826SMintz, Yuval struct qed_ptt *p_ptt, 12676927e826SMintz, Yuval enum qed_pci_personality *p_proto) 12686927e826SMintz, Yuval { 12696927e826SMintz, Yuval u32 resp = 0, param = 0; 12706927e826SMintz, Yuval int rc; 12716927e826SMintz, Yuval 12726927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 12736927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 12746927e826SMintz, Yuval if (rc) 12756927e826SMintz, Yuval return rc; 12766927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 12776927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 12786927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 12796927e826SMintz, Yuval resp); 12806927e826SMintz, Yuval return -EINVAL; 12816927e826SMintz, Yuval } 12826927e826SMintz, Yuval 12836927e826SMintz, Yuval switch (param) { 12846927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 12856927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 12866927e826SMintz, Yuval break; 12876927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 12886927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 12896927e826SMintz, Yuval break; 12906927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_BOTH: 12916927e826SMintz, Yuval DP_NOTICE(p_hwfn, 12926927e826SMintz, Yuval "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n"); 12936927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 12946927e826SMintz, Yuval break; 12956927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 12966927e826SMintz, Yuval default: 12976927e826SMintz, Yuval DP_NOTICE(p_hwfn, 12986927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 12996927e826SMintz, Yuval param); 13006927e826SMintz, Yuval return -EINVAL; 13016927e826SMintz, Yuval } 13026927e826SMintz, Yuval 13036927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 13046927e826SMintz, Yuval NETIF_MSG_IFUP, 13056927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 13066927e826SMintz, Yuval (u32) *p_proto, resp, param); 13076927e826SMintz, Yuval return 0; 13086927e826SMintz, Yuval } 13096927e826SMintz, Yuval 1310fe56b9e6SYuval Mintz static int 1311fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1312fe56b9e6SYuval Mintz struct public_func *p_info, 13136927e826SMintz, Yuval struct qed_ptt *p_ptt, 1314fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 1315fe56b9e6SYuval Mintz { 1316fe56b9e6SYuval Mintz int rc = 0; 1317fe56b9e6SYuval Mintz 1318fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1319fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 13201fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 13211fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 13221fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 13236927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 1324fe56b9e6SYuval Mintz break; 1325c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 1326c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 1327c5ac9319SYuval Mintz break; 13281e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 13291e128c81SArun Easi *p_proto = QED_PCI_FCOE; 13301e128c81SArun Easi break; 1331c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 1332c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 13336927e826SMintz, Yuval /* Fallthrough */ 1334fe56b9e6SYuval Mintz default: 1335fe56b9e6SYuval Mintz rc = -EINVAL; 1336fe56b9e6SYuval Mintz } 1337fe56b9e6SYuval Mintz 1338fe56b9e6SYuval Mintz return rc; 1339fe56b9e6SYuval Mintz } 1340fe56b9e6SYuval Mintz 1341fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1342fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1343fe56b9e6SYuval Mintz { 1344fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 1345fe56b9e6SYuval Mintz struct public_func shmem_info; 1346fe56b9e6SYuval Mintz 13471a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1348fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 1349fe56b9e6SYuval Mintz 1350fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 1351fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1352fe56b9e6SYuval Mintz 13536927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 13546927e826SMintz, Yuval &info->protocol)) { 1355fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 1356fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1357fe56b9e6SYuval Mintz return -EINVAL; 1358fe56b9e6SYuval Mintz } 1359fe56b9e6SYuval Mintz 13604b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1361fe56b9e6SYuval Mintz 1362fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 1363fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1364fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 1365fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1366fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1367fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1368fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 136914d39648SMintz, Yuval 137014d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 137114d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 1372fe56b9e6SYuval Mintz } else { 1373fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1374fe56b9e6SYuval Mintz } 1375fe56b9e6SYuval Mintz 1376fe56b9e6SYuval Mintz info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper | 1377fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32); 1378fe56b9e6SYuval Mintz info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper | 1379fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32); 1380fe56b9e6SYuval Mintz 1381fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1382fe56b9e6SYuval Mintz 13830fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 13840fefbfbaSSudarsana Kalluru 138514d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 138614d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 138714d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 138814d39648SMintz, Yuval u32 resp = 0, param = 0; 138914d39648SMintz, Yuval int rc; 139014d39648SMintz, Yuval 139114d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 139214d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 139314d39648SMintz, Yuval if (rc) 139414d39648SMintz, Yuval return rc; 139514d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 139614d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 139714d39648SMintz, Yuval } 139814d39648SMintz, Yuval 1399fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 140014d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 1401fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 1402fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 1403fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 1404fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 140514d39648SMintz, Yuval info->wwn_port, info->wwn_node, 140614d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 1407fe56b9e6SYuval Mintz 1408fe56b9e6SYuval Mintz return 0; 1409fe56b9e6SYuval Mintz } 1410fe56b9e6SYuval Mintz 1411cc875c2eSYuval Mintz struct qed_mcp_link_params 1412cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1413cc875c2eSYuval Mintz { 1414cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1415cc875c2eSYuval Mintz return NULL; 1416cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 1417cc875c2eSYuval Mintz } 1418cc875c2eSYuval Mintz 1419cc875c2eSYuval Mintz struct qed_mcp_link_state 1420cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1421cc875c2eSYuval Mintz { 1422cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1423cc875c2eSYuval Mintz return NULL; 1424cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 1425cc875c2eSYuval Mintz } 1426cc875c2eSYuval Mintz 1427cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 1428cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1429cc875c2eSYuval Mintz { 1430cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1431cc875c2eSYuval Mintz return NULL; 1432cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 1433cc875c2eSYuval Mintz } 1434cc875c2eSYuval Mintz 14351a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1436fe56b9e6SYuval Mintz { 1437fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 1438fe56b9e6SYuval Mintz int rc; 1439fe56b9e6SYuval Mintz 1440fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 14411a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1442fe56b9e6SYuval Mintz 1443fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 14448f60bafeSYuval Mintz msleep(1020); 1445fe56b9e6SYuval Mintz 1446fe56b9e6SYuval Mintz return rc; 1447fe56b9e6SYuval Mintz } 1448fe56b9e6SYuval Mintz 1449cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 14501a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 1451cee4d264SManish Chopra { 1452cee4d264SManish Chopra u32 flash_size; 1453cee4d264SManish Chopra 14541408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 14551408cc1fSYuval Mintz return -EINVAL; 14561408cc1fSYuval Mintz 1457cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1458cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1459cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1460cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1461cee4d264SManish Chopra 1462cee4d264SManish Chopra *p_flash_size = flash_size; 1463cee4d264SManish Chopra 1464cee4d264SManish Chopra return 0; 1465cee4d264SManish Chopra } 1466cee4d264SManish Chopra 14671408cc1fSYuval Mintz int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 14681408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 14691408cc1fSYuval Mintz { 14701408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 14711408cc1fSYuval Mintz int rc; 14721408cc1fSYuval Mintz 14731408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 14741408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 14751408cc1fSYuval Mintz return 0; 14761408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 14771408cc1fSYuval Mintz 14781408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 14791408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 14801408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 14811408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 14821408cc1fSYuval Mintz 14831408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 14841408cc1fSYuval Mintz &resp, &rc_param); 14851408cc1fSYuval Mintz 14861408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 14871408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 14881408cc1fSYuval Mintz rc = -EINVAL; 14891408cc1fSYuval Mintz } else { 14901408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 14911408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 14921408cc1fSYuval Mintz num, vf_id); 14931408cc1fSYuval Mintz } 14941408cc1fSYuval Mintz 14951408cc1fSYuval Mintz return rc; 14961408cc1fSYuval Mintz } 14971408cc1fSYuval Mintz 1498fe56b9e6SYuval Mintz int 1499fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 1500fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1501fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 1502fe56b9e6SYuval Mintz { 15035529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 15042f67af8cSTomer Tayar struct drv_version_stc drv_version; 15055529bad9STomer Tayar __be32 val; 15065529bad9STomer Tayar u32 i; 15075529bad9STomer Tayar int rc; 1508fe56b9e6SYuval Mintz 15092f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 15102f67af8cSTomer Tayar drv_version.version = p_ver->version; 151167a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 151267a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 15132f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 1514fe56b9e6SYuval Mintz } 1515fe56b9e6SYuval Mintz 15165529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 15175529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 15182f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 15192f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 15205529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 15215529bad9STomer Tayar if (rc) 1522fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1523fe56b9e6SYuval Mintz 15245529bad9STomer Tayar return rc; 1525fe56b9e6SYuval Mintz } 152691420b83SSudarsana Kalluru 15274102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15284102426fSTomer Tayar { 15294102426fSTomer Tayar u32 resp = 0, param = 0; 15304102426fSTomer Tayar int rc; 15314102426fSTomer Tayar 15324102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 15334102426fSTomer Tayar ¶m); 15344102426fSTomer Tayar if (rc) 15354102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 15364102426fSTomer Tayar 15374102426fSTomer Tayar return rc; 15384102426fSTomer Tayar } 15394102426fSTomer Tayar 15404102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15414102426fSTomer Tayar { 15424102426fSTomer Tayar u32 value, cpu_mode; 15434102426fSTomer Tayar 15444102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 15454102426fSTomer Tayar 15464102426fSTomer Tayar value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 15474102426fSTomer Tayar value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 15484102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 15494102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 15504102426fSTomer Tayar 15514102426fSTomer Tayar return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 15524102426fSTomer Tayar } 15534102426fSTomer Tayar 15540fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 15550fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 15560fefbfbaSSudarsana Kalluru enum qed_ov_client client) 15570fefbfbaSSudarsana Kalluru { 15580fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 15590fefbfbaSSudarsana Kalluru u32 drv_mb_param; 15600fefbfbaSSudarsana Kalluru int rc; 15610fefbfbaSSudarsana Kalluru 15620fefbfbaSSudarsana Kalluru switch (client) { 15630fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 15640fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 15650fefbfbaSSudarsana Kalluru break; 15660fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 15670fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 15680fefbfbaSSudarsana Kalluru break; 15690fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 15700fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 15710fefbfbaSSudarsana Kalluru break; 15720fefbfbaSSudarsana Kalluru default: 15730fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 15740fefbfbaSSudarsana Kalluru return -EINVAL; 15750fefbfbaSSudarsana Kalluru } 15760fefbfbaSSudarsana Kalluru 15770fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 15780fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 15790fefbfbaSSudarsana Kalluru if (rc) 15800fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 15810fefbfbaSSudarsana Kalluru 15820fefbfbaSSudarsana Kalluru return rc; 15830fefbfbaSSudarsana Kalluru } 15840fefbfbaSSudarsana Kalluru 15850fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 15860fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 15870fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 15880fefbfbaSSudarsana Kalluru { 15890fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 15900fefbfbaSSudarsana Kalluru u32 drv_mb_param; 15910fefbfbaSSudarsana Kalluru int rc; 15920fefbfbaSSudarsana Kalluru 15930fefbfbaSSudarsana Kalluru switch (drv_state) { 15940fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 15950fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 15960fefbfbaSSudarsana Kalluru break; 15970fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 15980fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 15990fefbfbaSSudarsana Kalluru break; 16000fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 16010fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 16020fefbfbaSSudarsana Kalluru break; 16030fefbfbaSSudarsana Kalluru default: 16040fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 16050fefbfbaSSudarsana Kalluru return -EINVAL; 16060fefbfbaSSudarsana Kalluru } 16070fefbfbaSSudarsana Kalluru 16080fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 16090fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 16100fefbfbaSSudarsana Kalluru if (rc) 16110fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 16120fefbfbaSSudarsana Kalluru 16130fefbfbaSSudarsana Kalluru return rc; 16140fefbfbaSSudarsana Kalluru } 16150fefbfbaSSudarsana Kalluru 16160fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 16170fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 16180fefbfbaSSudarsana Kalluru { 16190fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 16200fefbfbaSSudarsana Kalluru u32 drv_mb_param; 16210fefbfbaSSudarsana Kalluru int rc; 16220fefbfbaSSudarsana Kalluru 16230fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 16240fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 16250fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 16260fefbfbaSSudarsana Kalluru if (rc) 16270fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 16280fefbfbaSSudarsana Kalluru 16290fefbfbaSSudarsana Kalluru return rc; 16300fefbfbaSSudarsana Kalluru } 16310fefbfbaSSudarsana Kalluru 16320fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 16330fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 16340fefbfbaSSudarsana Kalluru { 16350fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 163617991002SMintz, Yuval u32 mfw_mac[2]; 16370fefbfbaSSudarsana Kalluru int rc; 16380fefbfbaSSudarsana Kalluru 16390fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 16400fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 16410fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 16420fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 16430fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 16442f67af8cSTomer Tayar 164517991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 164617991002SMintz, Yuval * in 32-bit granularity. 164717991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 164817991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 164917991002SMintz, Yuval */ 165017991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 165117991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 165217991002SMintz, Yuval 165317991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 165417991002SMintz, Yuval mb_params.data_src_size = 8; 16550fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 16560fefbfbaSSudarsana Kalluru if (rc) 16570fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 16580fefbfbaSSudarsana Kalluru 165914d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 166014d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 166114d39648SMintz, Yuval 16620fefbfbaSSudarsana Kalluru return rc; 16630fefbfbaSSudarsana Kalluru } 16640fefbfbaSSudarsana Kalluru 16650fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 16660fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 16670fefbfbaSSudarsana Kalluru { 16680fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 16690fefbfbaSSudarsana Kalluru u32 drv_mb_param; 16700fefbfbaSSudarsana Kalluru int rc; 16710fefbfbaSSudarsana Kalluru 167214d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 167314d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 167414d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 167514d39648SMintz, Yuval return -EINVAL; 167614d39648SMintz, Yuval } 167714d39648SMintz, Yuval 16780fefbfbaSSudarsana Kalluru switch (wol) { 16790fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 16800fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 16810fefbfbaSSudarsana Kalluru break; 16820fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 16830fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 16840fefbfbaSSudarsana Kalluru break; 16850fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 16860fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 16870fefbfbaSSudarsana Kalluru break; 16880fefbfbaSSudarsana Kalluru default: 16890fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 16900fefbfbaSSudarsana Kalluru return -EINVAL; 16910fefbfbaSSudarsana Kalluru } 16920fefbfbaSSudarsana Kalluru 16930fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 16940fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 16950fefbfbaSSudarsana Kalluru if (rc) 16960fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 16970fefbfbaSSudarsana Kalluru 169814d39648SMintz, Yuval /* Store the WoL update for a future unload */ 169914d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 170014d39648SMintz, Yuval 17010fefbfbaSSudarsana Kalluru return rc; 17020fefbfbaSSudarsana Kalluru } 17030fefbfbaSSudarsana Kalluru 17040fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 17050fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 17060fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 17070fefbfbaSSudarsana Kalluru { 17080fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 17090fefbfbaSSudarsana Kalluru u32 drv_mb_param; 17100fefbfbaSSudarsana Kalluru int rc; 17110fefbfbaSSudarsana Kalluru 17120fefbfbaSSudarsana Kalluru switch (eswitch) { 17130fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 17140fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 17150fefbfbaSSudarsana Kalluru break; 17160fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 17170fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 17180fefbfbaSSudarsana Kalluru break; 17190fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 17200fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 17210fefbfbaSSudarsana Kalluru break; 17220fefbfbaSSudarsana Kalluru default: 17230fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 17240fefbfbaSSudarsana Kalluru return -EINVAL; 17250fefbfbaSSudarsana Kalluru } 17260fefbfbaSSudarsana Kalluru 17270fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 17280fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 17290fefbfbaSSudarsana Kalluru if (rc) 17300fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 17310fefbfbaSSudarsana Kalluru 17320fefbfbaSSudarsana Kalluru return rc; 17330fefbfbaSSudarsana Kalluru } 17340fefbfbaSSudarsana Kalluru 17351a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 17361a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 173791420b83SSudarsana Kalluru { 173891420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 173991420b83SSudarsana Kalluru int rc; 174091420b83SSudarsana Kalluru 174191420b83SSudarsana Kalluru switch (mode) { 174291420b83SSudarsana Kalluru case QED_LED_MODE_ON: 174391420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 174491420b83SSudarsana Kalluru break; 174591420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 174691420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 174791420b83SSudarsana Kalluru break; 174891420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 174991420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 175091420b83SSudarsana Kalluru break; 175191420b83SSudarsana Kalluru default: 175291420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 175391420b83SSudarsana Kalluru return -EINVAL; 175491420b83SSudarsana Kalluru } 175591420b83SSudarsana Kalluru 175691420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 175791420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 175891420b83SSudarsana Kalluru 175991420b83SSudarsana Kalluru return rc; 176091420b83SSudarsana Kalluru } 176103dc76caSSudarsana Reddy Kalluru 17624102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 17634102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 17644102426fSTomer Tayar { 17654102426fSTomer Tayar u32 resp = 0, param = 0; 17664102426fSTomer Tayar int rc; 17674102426fSTomer Tayar 17684102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 17694102426fSTomer Tayar mask_parities, &resp, ¶m); 17704102426fSTomer Tayar 17714102426fSTomer Tayar if (rc) { 17724102426fSTomer Tayar DP_ERR(p_hwfn, 17734102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 17744102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 17754102426fSTomer Tayar DP_ERR(p_hwfn, 17764102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 17774102426fSTomer Tayar rc = -EINVAL; 17784102426fSTomer Tayar } 17794102426fSTomer Tayar 17804102426fSTomer Tayar return rc; 17814102426fSTomer Tayar } 17824102426fSTomer Tayar 17837a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 17847a4b21b7SMintz, Yuval { 17857a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 17867a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 17877a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 17887a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 17897a4b21b7SMintz, Yuval int rc = 0; 17907a4b21b7SMintz, Yuval 17917a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 17927a4b21b7SMintz, Yuval if (!p_ptt) 17937a4b21b7SMintz, Yuval return -EBUSY; 17947a4b21b7SMintz, Yuval 17957a4b21b7SMintz, Yuval while (bytes_left > 0) { 17967a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 17977a4b21b7SMintz, Yuval 17987a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 17997a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 18007a4b21b7SMintz, Yuval addr + offset + 18017a4b21b7SMintz, Yuval (bytes_to_copy << 18027a4b21b7SMintz, Yuval DRV_MB_PARAM_NVM_LEN_SHIFT), 18037a4b21b7SMintz, Yuval &resp, &resp_param, 18047a4b21b7SMintz, Yuval &read_len, 18057a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 18067a4b21b7SMintz, Yuval 18077a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 18087a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 18097a4b21b7SMintz, Yuval break; 18107a4b21b7SMintz, Yuval } 18117a4b21b7SMintz, Yuval 18127a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 18137a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 18147a4b21b7SMintz, Yuval */ 18157a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 18167a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 18177a4b21b7SMintz, Yuval usleep_range(1000, 2000); 18187a4b21b7SMintz, Yuval 18197a4b21b7SMintz, Yuval offset += read_len; 18207a4b21b7SMintz, Yuval bytes_left -= read_len; 18217a4b21b7SMintz, Yuval } 18227a4b21b7SMintz, Yuval 18237a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 18247a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 18257a4b21b7SMintz, Yuval 18267a4b21b7SMintz, Yuval return rc; 18277a4b21b7SMintz, Yuval } 18287a4b21b7SMintz, Yuval 182903dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 183003dc76caSSudarsana Reddy Kalluru { 183103dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 183203dc76caSSudarsana Reddy Kalluru int rc = 0; 183303dc76caSSudarsana Reddy Kalluru 183403dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 183503dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 183603dc76caSSudarsana Reddy Kalluru 183703dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 183803dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 183903dc76caSSudarsana Reddy Kalluru 184003dc76caSSudarsana Reddy Kalluru if (rc) 184103dc76caSSudarsana Reddy Kalluru return rc; 184203dc76caSSudarsana Reddy Kalluru 184303dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 184403dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 184503dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 184603dc76caSSudarsana Reddy Kalluru 184703dc76caSSudarsana Reddy Kalluru return rc; 184803dc76caSSudarsana Reddy Kalluru } 184903dc76caSSudarsana Reddy Kalluru 185003dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 185103dc76caSSudarsana Reddy Kalluru { 185203dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 185303dc76caSSudarsana Reddy Kalluru int rc = 0; 185403dc76caSSudarsana Reddy Kalluru 185503dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 185603dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 185703dc76caSSudarsana Reddy Kalluru 185803dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 185903dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 186003dc76caSSudarsana Reddy Kalluru 186103dc76caSSudarsana Reddy Kalluru if (rc) 186203dc76caSSudarsana Reddy Kalluru return rc; 186303dc76caSSudarsana Reddy Kalluru 186403dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 186503dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 186603dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 186703dc76caSSudarsana Reddy Kalluru 186803dc76caSSudarsana Reddy Kalluru return rc; 186903dc76caSSudarsana Reddy Kalluru } 18707a4b21b7SMintz, Yuval 18717a4b21b7SMintz, Yuval int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn, 18727a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 18737a4b21b7SMintz, Yuval u32 *num_images) 18747a4b21b7SMintz, Yuval { 18757a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 18767a4b21b7SMintz, Yuval int rc = 0; 18777a4b21b7SMintz, Yuval 18787a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 18797a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 18807a4b21b7SMintz, Yuval 18817a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 18827a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 18837a4b21b7SMintz, Yuval if (rc) 18847a4b21b7SMintz, Yuval return rc; 18857a4b21b7SMintz, Yuval 18867a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 18877a4b21b7SMintz, Yuval rc = -EINVAL; 18887a4b21b7SMintz, Yuval 18897a4b21b7SMintz, Yuval return rc; 18907a4b21b7SMintz, Yuval } 18917a4b21b7SMintz, Yuval 18927a4b21b7SMintz, Yuval int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn, 18937a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 18947a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 18957a4b21b7SMintz, Yuval u32 image_index) 18967a4b21b7SMintz, Yuval { 18977a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 18987a4b21b7SMintz, Yuval int rc; 18997a4b21b7SMintz, Yuval 19007a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 19017a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 19027a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 19037a4b21b7SMintz, Yuval 19047a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 19057a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 19067a4b21b7SMintz, Yuval &resp, &resp_param, 19077a4b21b7SMintz, Yuval &buf_size, 19087a4b21b7SMintz, Yuval (u32 *)p_image_att); 19097a4b21b7SMintz, Yuval if (rc) 19107a4b21b7SMintz, Yuval return rc; 19117a4b21b7SMintz, Yuval 19127a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 19137a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 19147a4b21b7SMintz, Yuval rc = -EINVAL; 19157a4b21b7SMintz, Yuval 19167a4b21b7SMintz, Yuval return rc; 19177a4b21b7SMintz, Yuval } 19182edbff8dSTomer Tayar 19192edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 1 19202edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 19212edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 19222edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 19232edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 19242edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 19252edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 19262edbff8dSTomer Tayar int qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 19272edbff8dSTomer Tayar struct qed_ptt *p_ptt, 19282edbff8dSTomer Tayar struct resource_info *p_resc_info, 19292edbff8dSTomer Tayar u32 *p_mcp_resp, u32 *p_mcp_param) 19302edbff8dSTomer Tayar { 19312edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 19322edbff8dSTomer Tayar int rc; 19332edbff8dSTomer Tayar 19342edbff8dSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 19352edbff8dSTomer Tayar mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 19362edbff8dSTomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 1937bb480242SMintz, Yuval 19382f67af8cSTomer Tayar mb_params.p_data_src = p_resc_info; 19392f67af8cSTomer Tayar mb_params.data_src_size = sizeof(*p_resc_info); 19402f67af8cSTomer Tayar mb_params.p_data_dst = p_resc_info; 19412f67af8cSTomer Tayar mb_params.data_dst_size = sizeof(*p_resc_info); 19422edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 19432edbff8dSTomer Tayar if (rc) 19442edbff8dSTomer Tayar return rc; 19452edbff8dSTomer Tayar 1946bb480242SMintz, Yuval /* Copy the data back */ 19472edbff8dSTomer Tayar *p_mcp_resp = mb_params.mcp_resp; 19482edbff8dSTomer Tayar *p_mcp_param = mb_params.mcp_param; 19492edbff8dSTomer Tayar 19502edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 19512edbff8dSTomer Tayar QED_MSG_SP, 19522edbff8dSTomer Tayar "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x, offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n", 19532edbff8dSTomer Tayar *p_mcp_param, 19542edbff8dSTomer Tayar p_resc_info->res_id, 19552edbff8dSTomer Tayar p_resc_info->size, 19562edbff8dSTomer Tayar p_resc_info->offset, 19572edbff8dSTomer Tayar p_resc_info->vf_size, 19582edbff8dSTomer Tayar p_resc_info->vf_offset, p_resc_info->flags); 19592edbff8dSTomer Tayar 19602edbff8dSTomer Tayar return 0; 19612edbff8dSTomer Tayar } 1962