1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/delay.h> 12fe56b9e6SYuval Mintz #include <linux/errno.h> 13fe56b9e6SYuval Mintz #include <linux/kernel.h> 14fe56b9e6SYuval Mintz #include <linux/slab.h> 155529bad9STomer Tayar #include <linux/spinlock.h> 16fe56b9e6SYuval Mintz #include <linux/string.h> 170fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 18fe56b9e6SYuval Mintz #include "qed.h" 1939651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 20fe56b9e6SYuval Mintz #include "qed_hsi.h" 21fe56b9e6SYuval Mintz #include "qed_hw.h" 22fe56b9e6SYuval Mintz #include "qed_mcp.h" 23fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 241408cc1fSYuval Mintz #include "qed_sriov.h" 251408cc1fSYuval Mintz 26fe56b9e6SYuval Mintz #define CHIP_MCP_RESP_ITER_US 10 27fe56b9e6SYuval Mintz 28fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 29fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 30fe56b9e6SYuval Mintz 31fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 32fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 33fe56b9e6SYuval Mintz _val) 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 36fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 39fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 40fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 41fe56b9e6SYuval Mintz 42fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 43fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 44fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 45fe56b9e6SYuval Mintz 46fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 47fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 48fe56b9e6SYuval Mintz 49fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 50fe56b9e6SYuval Mintz 51fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 52fe56b9e6SYuval Mintz { 53fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 54fe56b9e6SYuval Mintz return false; 55fe56b9e6SYuval Mintz return true; 56fe56b9e6SYuval Mintz } 57fe56b9e6SYuval Mintz 581a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 59fe56b9e6SYuval Mintz { 60fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 61fe56b9e6SYuval Mintz PUBLIC_PORT); 62fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 65fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 66fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 67fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 68fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 69fe56b9e6SYuval Mintz } 70fe56b9e6SYuval Mintz 711a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 72fe56b9e6SYuval Mintz { 73fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 74fe56b9e6SYuval Mintz u32 tmp, i; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 77fe56b9e6SYuval Mintz return; 78fe56b9e6SYuval Mintz 79fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 80fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 81fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 82fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 83fe56b9e6SYuval Mintz 84fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 85fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 86fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 87fe56b9e6SYuval Mintz } 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz 90fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 91fe56b9e6SYuval Mintz { 92fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 93fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 94fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 95fe56b9e6SYuval Mintz } 96fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 97fe56b9e6SYuval Mintz 98fe56b9e6SYuval Mintz return 0; 99fe56b9e6SYuval Mintz } 100fe56b9e6SYuval Mintz 1011a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 102fe56b9e6SYuval Mintz { 103fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 104fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 105fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 108fe56b9e6SYuval Mintz if (!p_info->public_base) 109fe56b9e6SYuval Mintz return 0; 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 112fe56b9e6SYuval Mintz 113fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 114fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 115fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 116fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 117fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 118fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 119fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 120fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 121fe56b9e6SYuval Mintz 122fe56b9e6SYuval Mintz /* Set the MFW MB address */ 123fe56b9e6SYuval Mintz mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 124fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 125fe56b9e6SYuval Mintz PUBLIC_MFW_MB)); 126fe56b9e6SYuval Mintz p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 127fe56b9e6SYuval Mintz p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); 128fe56b9e6SYuval Mintz 129fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 130fe56b9e6SYuval Mintz * the first command 131fe56b9e6SYuval Mintz */ 132fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 133fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 136fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 137fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 138fe56b9e6SYuval Mintz 139fe56b9e6SYuval Mintz p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 140fe56b9e6SYuval Mintz 141fe56b9e6SYuval Mintz return 0; 142fe56b9e6SYuval Mintz } 143fe56b9e6SYuval Mintz 1441a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 145fe56b9e6SYuval Mintz { 146fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 147fe56b9e6SYuval Mintz u32 size; 148fe56b9e6SYuval Mintz 149fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 15060fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 151fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 152fe56b9e6SYuval Mintz goto err; 153fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 154fe56b9e6SYuval Mintz 155fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 156fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 157fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 158fe56b9e6SYuval Mintz * the MCP is not initialized 159fe56b9e6SYuval Mintz */ 160fe56b9e6SYuval Mintz return 0; 161fe56b9e6SYuval Mintz } 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 16460fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 16583aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 166fe56b9e6SYuval Mintz if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr) 167fe56b9e6SYuval Mintz goto err; 168fe56b9e6SYuval Mintz 1695529bad9STomer Tayar /* Initialize the MFW spinlock */ 1705529bad9STomer Tayar spin_lock_init(&p_info->lock); 171fe56b9e6SYuval Mintz 172fe56b9e6SYuval Mintz return 0; 173fe56b9e6SYuval Mintz 174fe56b9e6SYuval Mintz err: 175fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 176fe56b9e6SYuval Mintz return -ENOMEM; 177fe56b9e6SYuval Mintz } 178fe56b9e6SYuval Mintz 1795529bad9STomer Tayar /* Locks the MFW mailbox of a PF to ensure a single access. 1805529bad9STomer Tayar * The lock is achieved in most cases by holding a spinlock, causing other 1815529bad9STomer Tayar * threads to wait till a previous access is done. 1825529bad9STomer Tayar * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single 1835529bad9STomer Tayar * access is achieved by setting a blocking flag, which will fail other 1845529bad9STomer Tayar * competing contexts to send their mailboxes. 1855529bad9STomer Tayar */ 1861a635e48SYuval Mintz static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn, u32 cmd) 1875529bad9STomer Tayar { 1885529bad9STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->lock); 1895529bad9STomer Tayar 1905529bad9STomer Tayar /* The spinlock shouldn't be acquired when the mailbox command is 1915529bad9STomer Tayar * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel 1925529bad9STomer Tayar * pending [UN]LOAD_REQ command of another PF together with a spinlock 1935529bad9STomer Tayar * (i.e. interrupts are disabled) - can lead to a deadlock. 1945529bad9STomer Tayar * It is assumed that for a single PF, no other mailbox commands can be 1955529bad9STomer Tayar * sent from another context while sending LOAD_REQ, and that any 1965529bad9STomer Tayar * parallel commands to UNLOAD_REQ can be cancelled. 1975529bad9STomer Tayar */ 1985529bad9STomer Tayar if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE) 1995529bad9STomer Tayar p_hwfn->mcp_info->block_mb_sending = false; 2005529bad9STomer Tayar 2015529bad9STomer Tayar if (p_hwfn->mcp_info->block_mb_sending) { 2025529bad9STomer Tayar DP_NOTICE(p_hwfn, 2035529bad9STomer Tayar "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n", 2045529bad9STomer Tayar cmd); 2055529bad9STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->lock); 2065529bad9STomer Tayar return -EBUSY; 2075529bad9STomer Tayar } 2085529bad9STomer Tayar 2095529bad9STomer Tayar if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) { 2105529bad9STomer Tayar p_hwfn->mcp_info->block_mb_sending = true; 2115529bad9STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->lock); 2125529bad9STomer Tayar } 2135529bad9STomer Tayar 2145529bad9STomer Tayar return 0; 2155529bad9STomer Tayar } 2165529bad9STomer Tayar 2171a635e48SYuval Mintz static void qed_mcp_mb_unlock(struct qed_hwfn *p_hwfn, u32 cmd) 2185529bad9STomer Tayar { 2195529bad9STomer Tayar if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ) 2205529bad9STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->lock); 2215529bad9STomer Tayar } 2225529bad9STomer Tayar 2231a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 224fe56b9e6SYuval Mintz { 225fe56b9e6SYuval Mintz u32 seq = ++p_hwfn->mcp_info->drv_mb_seq; 226fe56b9e6SYuval Mintz u8 delay = CHIP_MCP_RESP_ITER_US; 227fe56b9e6SYuval Mintz u32 org_mcp_reset_seq, cnt = 0; 228fe56b9e6SYuval Mintz int rc = 0; 229fe56b9e6SYuval Mintz 2305529bad9STomer Tayar /* Ensure that only a single thread is accessing the mailbox at a 2315529bad9STomer Tayar * certain time. 2325529bad9STomer Tayar */ 2335529bad9STomer Tayar rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 2345529bad9STomer Tayar if (rc != 0) 2355529bad9STomer Tayar return rc; 2365529bad9STomer Tayar 237fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 238fe56b9e6SYuval Mintz org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 239fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, 240fe56b9e6SYuval Mintz (DRV_MSG_CODE_MCP_RESET | seq)); 241fe56b9e6SYuval Mintz 242fe56b9e6SYuval Mintz do { 243fe56b9e6SYuval Mintz /* Wait for MFW response */ 244fe56b9e6SYuval Mintz udelay(delay); 245fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 246fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 247fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 248fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 249fe56b9e6SYuval Mintz 250fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 251fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 252fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 253fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 254fe56b9e6SYuval Mintz } else { 255fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 256fe56b9e6SYuval Mintz rc = -EAGAIN; 257fe56b9e6SYuval Mintz } 258fe56b9e6SYuval Mintz 2595529bad9STomer Tayar qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET); 2605529bad9STomer Tayar 261fe56b9e6SYuval Mintz return rc; 262fe56b9e6SYuval Mintz } 263fe56b9e6SYuval Mintz 264fe56b9e6SYuval Mintz static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn, 265fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 266fe56b9e6SYuval Mintz u32 cmd, 267fe56b9e6SYuval Mintz u32 param, 268fe56b9e6SYuval Mintz u32 *o_mcp_resp, 269fe56b9e6SYuval Mintz u32 *o_mcp_param) 270fe56b9e6SYuval Mintz { 271fe56b9e6SYuval Mintz u8 delay = CHIP_MCP_RESP_ITER_US; 272fe56b9e6SYuval Mintz u32 seq, cnt = 1, actual_mb_seq; 273fe56b9e6SYuval Mintz int rc = 0; 274fe56b9e6SYuval Mintz 275fe56b9e6SYuval Mintz /* Get actual driver mailbox sequence */ 276fe56b9e6SYuval Mintz actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 277fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 278fe56b9e6SYuval Mintz 279fe56b9e6SYuval Mintz /* Use MCP history register to check if MCP reset occurred between 280fe56b9e6SYuval Mintz * init time and now. 281fe56b9e6SYuval Mintz */ 282fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->mcp_hist != 283fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 284fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n"); 285fe56b9e6SYuval Mintz qed_load_mcp_offsets(p_hwfn, p_ptt); 286fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 287fe56b9e6SYuval Mintz } 288fe56b9e6SYuval Mintz seq = ++p_hwfn->mcp_info->drv_mb_seq; 289fe56b9e6SYuval Mintz 290fe56b9e6SYuval Mintz /* Set drv param */ 291fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param); 292fe56b9e6SYuval Mintz 293fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 294fe56b9e6SYuval Mintz DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq)); 295fe56b9e6SYuval Mintz 296fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 297fe56b9e6SYuval Mintz "wrote command (%x) to MFW MB param 0x%08x\n", 298fe56b9e6SYuval Mintz (cmd | seq), param); 299fe56b9e6SYuval Mintz 300fe56b9e6SYuval Mintz do { 301fe56b9e6SYuval Mintz /* Wait for MFW response */ 302fe56b9e6SYuval Mintz udelay(delay); 303fe56b9e6SYuval Mintz *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 304fe56b9e6SYuval Mintz 305fe56b9e6SYuval Mintz /* Give the FW up to 5 second (500*10ms) */ 306fe56b9e6SYuval Mintz } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) && 307fe56b9e6SYuval Mintz (cnt++ < QED_DRV_MB_MAX_RETRIES)); 308fe56b9e6SYuval Mintz 309fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 310fe56b9e6SYuval Mintz "[after %d ms] read (%x) seq is (%x) from FW MB\n", 311fe56b9e6SYuval Mintz cnt * delay, *o_mcp_resp, seq); 312fe56b9e6SYuval Mintz 313fe56b9e6SYuval Mintz /* Is this a reply to our command? */ 314fe56b9e6SYuval Mintz if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) { 315fe56b9e6SYuval Mintz *o_mcp_resp &= FW_MSG_CODE_MASK; 316fe56b9e6SYuval Mintz /* Get the MCP param */ 317fe56b9e6SYuval Mintz *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 318fe56b9e6SYuval Mintz } else { 319fe56b9e6SYuval Mintz /* FW BUG! */ 320525ef5c0SYuval Mintz DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n", 321525ef5c0SYuval Mintz cmd, param); 322fe56b9e6SYuval Mintz *o_mcp_resp = 0; 323fe56b9e6SYuval Mintz rc = -EAGAIN; 324fe56b9e6SYuval Mintz } 325fe56b9e6SYuval Mintz return rc; 326fe56b9e6SYuval Mintz } 327fe56b9e6SYuval Mintz 3285529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 329fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 3305529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 331fe56b9e6SYuval Mintz { 3325529bad9STomer Tayar u32 union_data_addr; 3335529bad9STomer Tayar int rc; 334fe56b9e6SYuval Mintz 335fe56b9e6SYuval Mintz /* MCP not initialized */ 336fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 337fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 338fe56b9e6SYuval Mintz return -EBUSY; 339fe56b9e6SYuval Mintz } 340fe56b9e6SYuval Mintz 3415529bad9STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 3425529bad9STomer Tayar offsetof(struct public_drv_mb, union_data); 3435529bad9STomer Tayar 3445529bad9STomer Tayar /* Ensure that only a single thread is accessing the mailbox at a 3455529bad9STomer Tayar * certain time. 346fe56b9e6SYuval Mintz */ 3475529bad9STomer Tayar rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd); 3485529bad9STomer Tayar if (rc) 3495529bad9STomer Tayar return rc; 3505529bad9STomer Tayar 3515529bad9STomer Tayar if (p_mb_params->p_data_src != NULL) 3525529bad9STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, 3535529bad9STomer Tayar p_mb_params->p_data_src, 3545529bad9STomer Tayar sizeof(*p_mb_params->p_data_src)); 3555529bad9STomer Tayar 3565529bad9STomer Tayar rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd, 3575529bad9STomer Tayar p_mb_params->param, &p_mb_params->mcp_resp, 3585529bad9STomer Tayar &p_mb_params->mcp_param); 3595529bad9STomer Tayar 3605529bad9STomer Tayar if (p_mb_params->p_data_dst != NULL) 3615529bad9STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 3625529bad9STomer Tayar union_data_addr, 3635529bad9STomer Tayar sizeof(*p_mb_params->p_data_dst)); 3645529bad9STomer Tayar 3655529bad9STomer Tayar qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd); 366fe56b9e6SYuval Mintz 367fe56b9e6SYuval Mintz return rc; 368fe56b9e6SYuval Mintz } 369fe56b9e6SYuval Mintz 3705529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 3715529bad9STomer Tayar struct qed_ptt *p_ptt, 3725529bad9STomer Tayar u32 cmd, 3735529bad9STomer Tayar u32 param, 3745529bad9STomer Tayar u32 *o_mcp_resp, 3755529bad9STomer Tayar u32 *o_mcp_param) 376fe56b9e6SYuval Mintz { 3775529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 3785529bad9STomer Tayar int rc; 379fe56b9e6SYuval Mintz 3805529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 3815529bad9STomer Tayar mb_params.cmd = cmd; 3825529bad9STomer Tayar mb_params.param = param; 3835529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 3845529bad9STomer Tayar if (rc) 3855529bad9STomer Tayar return rc; 3865529bad9STomer Tayar 3875529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 3885529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 3895529bad9STomer Tayar 3905529bad9STomer Tayar return 0; 391fe56b9e6SYuval Mintz } 392fe56b9e6SYuval Mintz 3934102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 3944102426fSTomer Tayar struct qed_ptt *p_ptt, 3954102426fSTomer Tayar u32 cmd, 3964102426fSTomer Tayar u32 param, 3974102426fSTomer Tayar u32 *o_mcp_resp, 3984102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 3994102426fSTomer Tayar { 4004102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 4014102426fSTomer Tayar union drv_union_data union_data; 4024102426fSTomer Tayar int rc; 4034102426fSTomer Tayar 4044102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 4054102426fSTomer Tayar mb_params.cmd = cmd; 4064102426fSTomer Tayar mb_params.param = param; 4074102426fSTomer Tayar mb_params.p_data_dst = &union_data; 4084102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 4094102426fSTomer Tayar if (rc) 4104102426fSTomer Tayar return rc; 4114102426fSTomer Tayar 4124102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 4134102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 4144102426fSTomer Tayar 4154102426fSTomer Tayar *o_txn_size = *o_mcp_param; 4164102426fSTomer Tayar memcpy(o_buf, &union_data.raw_data, *o_txn_size); 4174102426fSTomer Tayar 4184102426fSTomer Tayar return 0; 4194102426fSTomer Tayar } 4204102426fSTomer Tayar 421fe56b9e6SYuval Mintz int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 4221a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_load_code) 423fe56b9e6SYuval Mintz { 424fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 4255529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 4265529bad9STomer Tayar union drv_union_data union_data; 427fe56b9e6SYuval Mintz int rc; 428fe56b9e6SYuval Mintz 4295529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 430fe56b9e6SYuval Mintz /* Load Request */ 4315529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 4325529bad9STomer Tayar mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT | 4335529bad9STomer Tayar cdev->drv_type; 4345529bad9STomer Tayar memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE); 4355529bad9STomer Tayar mb_params.p_data_src = &union_data; 4365529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 437fe56b9e6SYuval Mintz 438fe56b9e6SYuval Mintz /* if mcp fails to respond we must abort */ 439fe56b9e6SYuval Mintz if (rc) { 440fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 441fe56b9e6SYuval Mintz return rc; 442fe56b9e6SYuval Mintz } 443fe56b9e6SYuval Mintz 4445529bad9STomer Tayar *p_load_code = mb_params.mcp_resp; 4455529bad9STomer Tayar 446fe56b9e6SYuval Mintz /* If MFW refused (e.g. other port is in diagnostic mode) we 447fe56b9e6SYuval Mintz * must abort. This can happen in the following cases: 448fe56b9e6SYuval Mintz * - Other port is in diagnostic mode 449fe56b9e6SYuval Mintz * - Previously loaded function on the engine is not compliant with 450fe56b9e6SYuval Mintz * the requester. 451fe56b9e6SYuval Mintz * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION. 452fe56b9e6SYuval Mintz * - 453fe56b9e6SYuval Mintz */ 454fe56b9e6SYuval Mintz if (!(*p_load_code) || 455fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) || 456fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) || 457fe56b9e6SYuval Mintz ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) { 458fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP refused load request, aborting\n"); 459fe56b9e6SYuval Mintz return -EBUSY; 460fe56b9e6SYuval Mintz } 461fe56b9e6SYuval Mintz 462fe56b9e6SYuval Mintz return 0; 463fe56b9e6SYuval Mintz } 464fe56b9e6SYuval Mintz 4650b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 4660b55e27dSYuval Mintz struct qed_ptt *p_ptt) 4670b55e27dSYuval Mintz { 4680b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 4690b55e27dSYuval Mintz PUBLIC_PATH); 4700b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 4710b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 4720b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 4730b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 4740b55e27dSYuval Mintz int i; 4750b55e27dSYuval Mintz 4760b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 4770b55e27dSYuval Mintz QED_MSG_SP, 4780b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 4790b55e27dSYuval Mintz mfw_path_offsize, path_addr); 4800b55e27dSYuval Mintz 4810b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 4820b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 4830b55e27dSYuval Mintz path_addr + 4840b55e27dSYuval Mintz offsetof(struct public_path, 4850b55e27dSYuval Mintz mcp_vf_disabled) + 4860b55e27dSYuval Mintz sizeof(u32) * i); 4870b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 4880b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 4890b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 4900b55e27dSYuval Mintz } 4910b55e27dSYuval Mintz 4920b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 4930b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 4940b55e27dSYuval Mintz } 4950b55e27dSYuval Mintz 4960b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 4970b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 4980b55e27dSYuval Mintz { 4990b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 5000b55e27dSYuval Mintz PUBLIC_FUNC); 5010b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 5020b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 5030b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 5040b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 5050b55e27dSYuval Mintz union drv_union_data union_data; 5060b55e27dSYuval Mintz int rc; 5070b55e27dSYuval Mintz int i; 5080b55e27dSYuval Mintz 5090b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 5100b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 5110b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 5120b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 5130b55e27dSYuval Mintz 5140b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 5150b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 5160b55e27dSYuval Mintz memcpy(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8); 5170b55e27dSYuval Mintz mb_params.p_data_src = &union_data; 5180b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 5190b55e27dSYuval Mintz if (rc) { 5200b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 5210b55e27dSYuval Mintz return -EBUSY; 5220b55e27dSYuval Mintz } 5230b55e27dSYuval Mintz 5240b55e27dSYuval Mintz /* Clear the ACK bits */ 5250b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 5260b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 5270b55e27dSYuval Mintz func_addr + 5280b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 5290b55e27dSYuval Mintz i * sizeof(u32), 0); 5300b55e27dSYuval Mintz 5310b55e27dSYuval Mintz return rc; 5320b55e27dSYuval Mintz } 5330b55e27dSYuval Mintz 534334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 535334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 536334c03b5SZvi Nachmani { 537334c03b5SZvi Nachmani u32 transceiver_state; 538334c03b5SZvi Nachmani 539334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 540334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 541334c03b5SZvi Nachmani offsetof(struct public_port, 542334c03b5SZvi Nachmani transceiver_data)); 543334c03b5SZvi Nachmani 544334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 545334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 546334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 547334c03b5SZvi Nachmani transceiver_state, 548334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 5491a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 550334c03b5SZvi Nachmani 551334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 552351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 553334c03b5SZvi Nachmani 554351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 555334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 556334c03b5SZvi Nachmani else 557334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 558334c03b5SZvi Nachmani } 559334c03b5SZvi Nachmani 560cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 5611a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 562cc875c2eSYuval Mintz { 563cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 564a64b02d5SManish Chopra u8 max_bw, min_bw; 565cc875c2eSYuval Mintz u32 status = 0; 566cc875c2eSYuval Mintz 567cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 568cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 569cc875c2eSYuval Mintz if (!b_reset) { 570cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 571cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 572cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 573cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 574cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 575cc875c2eSYuval Mintz status, 576cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 5771a635e48SYuval Mintz offsetof(struct public_port, link_status))); 578cc875c2eSYuval Mintz } else { 579cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 580cc875c2eSYuval Mintz "Resetting link indications\n"); 581cc875c2eSYuval Mintz return; 582cc875c2eSYuval Mintz } 583cc875c2eSYuval Mintz 584fc916ff2SSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) 585cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 586fc916ff2SSudarsana Reddy Kalluru else 587fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 588cc875c2eSYuval Mintz 589cc875c2eSYuval Mintz p_link->full_duplex = true; 590cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 591cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 592cc875c2eSYuval Mintz p_link->speed = 100000; 593cc875c2eSYuval Mintz break; 594cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 595cc875c2eSYuval Mintz p_link->speed = 50000; 596cc875c2eSYuval Mintz break; 597cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 598cc875c2eSYuval Mintz p_link->speed = 40000; 599cc875c2eSYuval Mintz break; 600cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 601cc875c2eSYuval Mintz p_link->speed = 25000; 602cc875c2eSYuval Mintz break; 603cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 604cc875c2eSYuval Mintz p_link->speed = 20000; 605cc875c2eSYuval Mintz break; 606cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 607cc875c2eSYuval Mintz p_link->speed = 10000; 608cc875c2eSYuval Mintz break; 609cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 610cc875c2eSYuval Mintz p_link->full_duplex = false; 611cc875c2eSYuval Mintz /* Fall-through */ 612cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 613cc875c2eSYuval Mintz p_link->speed = 1000; 614cc875c2eSYuval Mintz break; 615cc875c2eSYuval Mintz default: 616cc875c2eSYuval Mintz p_link->speed = 0; 617cc875c2eSYuval Mintz } 618cc875c2eSYuval Mintz 6194b01e519SManish Chopra if (p_link->link_up && p_link->speed) 6204b01e519SManish Chopra p_link->line_speed = p_link->speed; 6214b01e519SManish Chopra else 6224b01e519SManish Chopra p_link->line_speed = 0; 6234b01e519SManish Chopra 6244b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 625a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 6264b01e519SManish Chopra 627a64b02d5SManish Chopra /* Max bandwidth configuration */ 6284b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 629cc875c2eSYuval Mintz 630a64b02d5SManish Chopra /* Min bandwidth configuration */ 631a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 632a64b02d5SManish Chopra qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate); 633a64b02d5SManish Chopra 634cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 635cc875c2eSYuval Mintz p_link->an_complete = !!(status & 636cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 637cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 638cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 639cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 640cc875c2eSYuval Mintz 641cc875c2eSYuval Mintz p_link->partner_adv_speed |= 642cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 643cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 644cc875c2eSYuval Mintz p_link->partner_adv_speed |= 645cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 646cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 647cc875c2eSYuval Mintz p_link->partner_adv_speed |= 648cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 649cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 650cc875c2eSYuval Mintz p_link->partner_adv_speed |= 651cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 652cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 653cc875c2eSYuval Mintz p_link->partner_adv_speed |= 654054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 655054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 656054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 657cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 658cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 659cc875c2eSYuval Mintz p_link->partner_adv_speed |= 660cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 661cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 662cc875c2eSYuval Mintz p_link->partner_adv_speed |= 663cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 664cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 665cc875c2eSYuval Mintz 666cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 667cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 668cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 669cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 670cc875c2eSYuval Mintz 671cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 672cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 673cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 674cc875c2eSYuval Mintz break; 675cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 676cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 677cc875c2eSYuval Mintz break; 678cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 679cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 680cc875c2eSYuval Mintz break; 681cc875c2eSYuval Mintz default: 682cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 683cc875c2eSYuval Mintz } 684cc875c2eSYuval Mintz 685cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 686cc875c2eSYuval Mintz 687cc875c2eSYuval Mintz qed_link_update(p_hwfn); 688cc875c2eSYuval Mintz } 689cc875c2eSYuval Mintz 690351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 691cc875c2eSYuval Mintz { 692cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 6935529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6945529bad9STomer Tayar union drv_union_data union_data; 695351a4dedSYuval Mintz struct eth_phy_cfg *phy_cfg; 696cc875c2eSYuval Mintz int rc = 0; 6975529bad9STomer Tayar u32 cmd; 698cc875c2eSYuval Mintz 699cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 7005529bad9STomer Tayar phy_cfg = &union_data.drv_phy_cfg; 7015529bad9STomer Tayar memset(phy_cfg, 0, sizeof(*phy_cfg)); 702cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 703cc875c2eSYuval Mintz if (!params->speed.autoneg) 7045529bad9STomer Tayar phy_cfg->speed = params->speed.forced_speed; 705351a4dedSYuval Mintz phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 706351a4dedSYuval Mintz phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 707351a4dedSYuval Mintz phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 7085529bad9STomer Tayar phy_cfg->adv_speed = params->speed.advertised_speeds; 7095529bad9STomer Tayar phy_cfg->loopback_mode = params->loopback_mode; 710cc875c2eSYuval Mintz 711fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 712fc916ff2SSudarsana Reddy Kalluru 713cc875c2eSYuval Mintz if (b_up) { 714cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 715cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 7165529bad9STomer Tayar phy_cfg->speed, 7175529bad9STomer Tayar phy_cfg->pause, 7185529bad9STomer Tayar phy_cfg->adv_speed, 7195529bad9STomer Tayar phy_cfg->loopback_mode, 7205529bad9STomer Tayar phy_cfg->feature_config_flags); 721cc875c2eSYuval Mintz } else { 722cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 723cc875c2eSYuval Mintz "Resetting link\n"); 724cc875c2eSYuval Mintz } 725cc875c2eSYuval Mintz 7265529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7275529bad9STomer Tayar mb_params.cmd = cmd; 7285529bad9STomer Tayar mb_params.p_data_src = &union_data; 7295529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 730cc875c2eSYuval Mintz 731cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 732cc875c2eSYuval Mintz if (rc) { 733cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 734cc875c2eSYuval Mintz return rc; 735cc875c2eSYuval Mintz } 736cc875c2eSYuval Mintz 737cc875c2eSYuval Mintz /* Reset the link status if needed */ 738cc875c2eSYuval Mintz if (!b_up) 739cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, true); 740cc875c2eSYuval Mintz 741cc875c2eSYuval Mintz return 0; 742cc875c2eSYuval Mintz } 743cc875c2eSYuval Mintz 7446c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 7456c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 7466c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 7476c754246SSudarsana Reddy Kalluru { 7486c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 7496c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 7506c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 7516c754246SSudarsana Reddy Kalluru union drv_union_data union_data; 7526c754246SSudarsana Reddy Kalluru u32 hsi_param; 7536c754246SSudarsana Reddy Kalluru 7546c754246SSudarsana Reddy Kalluru switch (type) { 7556c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 7566c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 7576c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 7586c754246SSudarsana Reddy Kalluru break; 7596c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 7606c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 7616c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 7626c754246SSudarsana Reddy Kalluru break; 7636c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 7646c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 7656c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 7666c754246SSudarsana Reddy Kalluru break; 7676c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 7686c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 7696c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 7706c754246SSudarsana Reddy Kalluru break; 7716c754246SSudarsana Reddy Kalluru default: 7726c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 7736c754246SSudarsana Reddy Kalluru return; 7746c754246SSudarsana Reddy Kalluru } 7756c754246SSudarsana Reddy Kalluru 7766c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 7776c754246SSudarsana Reddy Kalluru 7786c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 7796c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 7806c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 7816c754246SSudarsana Reddy Kalluru memcpy(&union_data, &stats, sizeof(stats)); 7826c754246SSudarsana Reddy Kalluru mb_params.p_data_src = &union_data; 7836c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7846c754246SSudarsana Reddy Kalluru } 7856c754246SSudarsana Reddy Kalluru 7864b01e519SManish Chopra static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 7874b01e519SManish Chopra struct public_func *p_shmem_info) 7884b01e519SManish Chopra { 7894b01e519SManish Chopra struct qed_mcp_function_info *p_info; 7904b01e519SManish Chopra 7914b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 7924b01e519SManish Chopra 7934b01e519SManish Chopra p_info->bandwidth_min = (p_shmem_info->config & 7944b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_MASK) >> 7954b01e519SManish Chopra FUNC_MF_CFG_MIN_BW_SHIFT; 7964b01e519SManish Chopra if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 7974b01e519SManish Chopra DP_INFO(p_hwfn, 7984b01e519SManish Chopra "bandwidth minimum out of bounds [%02x]. Set to 1\n", 7994b01e519SManish Chopra p_info->bandwidth_min); 8004b01e519SManish Chopra p_info->bandwidth_min = 1; 8014b01e519SManish Chopra } 8024b01e519SManish Chopra 8034b01e519SManish Chopra p_info->bandwidth_max = (p_shmem_info->config & 8044b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_MASK) >> 8054b01e519SManish Chopra FUNC_MF_CFG_MAX_BW_SHIFT; 8064b01e519SManish Chopra if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 8074b01e519SManish Chopra DP_INFO(p_hwfn, 8084b01e519SManish Chopra "bandwidth maximum out of bounds [%02x]. Set to 100\n", 8094b01e519SManish Chopra p_info->bandwidth_max); 8104b01e519SManish Chopra p_info->bandwidth_max = 100; 8114b01e519SManish Chopra } 8124b01e519SManish Chopra } 8134b01e519SManish Chopra 8144b01e519SManish Chopra static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 8154b01e519SManish Chopra struct qed_ptt *p_ptt, 8161a635e48SYuval Mintz struct public_func *p_data, int pfid) 8174b01e519SManish Chopra { 8184b01e519SManish Chopra u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 8194b01e519SManish Chopra PUBLIC_FUNC); 8204b01e519SManish Chopra u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 8214b01e519SManish Chopra u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 8224b01e519SManish Chopra u32 i, size; 8234b01e519SManish Chopra 8244b01e519SManish Chopra memset(p_data, 0, sizeof(*p_data)); 8254b01e519SManish Chopra 8261a635e48SYuval Mintz size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 8274b01e519SManish Chopra for (i = 0; i < size / sizeof(u32); i++) 8284b01e519SManish Chopra ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 8294b01e519SManish Chopra func_addr + (i << 2)); 8304b01e519SManish Chopra return size; 8314b01e519SManish Chopra } 8324b01e519SManish Chopra 8331a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 8344b01e519SManish Chopra { 8354b01e519SManish Chopra struct qed_mcp_function_info *p_info; 8364b01e519SManish Chopra struct public_func shmem_info; 8374b01e519SManish Chopra u32 resp = 0, param = 0; 8384b01e519SManish Chopra 8391a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 8404b01e519SManish Chopra 8414b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 8424b01e519SManish Chopra 8434b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 8444b01e519SManish Chopra 845a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 8464b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 8474b01e519SManish Chopra 8484b01e519SManish Chopra /* Acknowledge the MFW */ 8494b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 8504b01e519SManish Chopra ¶m); 8514b01e519SManish Chopra } 8524b01e519SManish Chopra 853cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 854cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 855cc875c2eSYuval Mintz { 856cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 857cc875c2eSYuval Mintz int rc = 0; 858cc875c2eSYuval Mintz bool found = false; 859cc875c2eSYuval Mintz u16 i; 860cc875c2eSYuval Mintz 861cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 862cc875c2eSYuval Mintz 863cc875c2eSYuval Mintz /* Read Messages from MFW */ 864cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 865cc875c2eSYuval Mintz 866cc875c2eSYuval Mintz /* Compare current messages to old ones */ 867cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 868cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 869cc875c2eSYuval Mintz continue; 870cc875c2eSYuval Mintz 871cc875c2eSYuval Mintz found = true; 872cc875c2eSYuval Mintz 873cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 874cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 875cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 876cc875c2eSYuval Mintz 877cc875c2eSYuval Mintz switch (i) { 878cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 879cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 880cc875c2eSYuval Mintz break; 8810b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 8820b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 8830b55e27dSYuval Mintz break; 88439651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 88539651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 88639651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 88739651abdSSudarsana Reddy Kalluru break; 88839651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 88939651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 89039651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 89139651abdSSudarsana Reddy Kalluru break; 89239651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 89339651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 89439651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 89539651abdSSudarsana Reddy Kalluru break; 896334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 897334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 898334c03b5SZvi Nachmani break; 8996c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 9006c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 9016c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 9026c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 9036c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 9046c754246SSudarsana Reddy Kalluru break; 9054b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 9064b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 9074b01e519SManish Chopra break; 908cc875c2eSYuval Mintz default: 909cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i); 910cc875c2eSYuval Mintz rc = -EINVAL; 911cc875c2eSYuval Mintz } 912cc875c2eSYuval Mintz } 913cc875c2eSYuval Mintz 914cc875c2eSYuval Mintz /* ACK everything */ 915cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 916cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 917cc875c2eSYuval Mintz 918cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 919cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 920cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 921cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 922cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 923cc875c2eSYuval Mintz (__force u32)val); 924cc875c2eSYuval Mintz } 925cc875c2eSYuval Mintz 926cc875c2eSYuval Mintz if (!found) { 927cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 928cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 929cc875c2eSYuval Mintz rc = -EINVAL; 930cc875c2eSYuval Mintz } 931cc875c2eSYuval Mintz 932cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 933cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 934cc875c2eSYuval Mintz 935cc875c2eSYuval Mintz return rc; 936cc875c2eSYuval Mintz } 937cc875c2eSYuval Mintz 9381408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 9391408cc1fSYuval Mintz struct qed_ptt *p_ptt, 9401408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 941fe56b9e6SYuval Mintz { 942fe56b9e6SYuval Mintz u32 global_offsize; 943fe56b9e6SYuval Mintz 9441408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 9451408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 9461408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 9471408cc1fSYuval Mintz 9481408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 9491408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 9501408cc1fSYuval Mintz return 0; 9511408cc1fSYuval Mintz } else { 9521408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 9531408cc1fSYuval Mintz QED_MSG_IOV, 9541408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 9551408cc1fSYuval Mintz return -EINVAL; 9561408cc1fSYuval Mintz } 9571408cc1fSYuval Mintz } 958fe56b9e6SYuval Mintz 959fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 9601408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 9611408cc1fSYuval Mintz mcp_info->public_base, 962fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 9631408cc1fSYuval Mintz *p_mfw_ver = 9641408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 9651408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 9661408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 967fe56b9e6SYuval Mintz 9681408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 9691408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 9701408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 9711408cc1fSYuval Mintz offsetof(struct public_global, 9721408cc1fSYuval Mintz running_bundle_id)); 9731408cc1fSYuval Mintz } 974fe56b9e6SYuval Mintz 975fe56b9e6SYuval Mintz return 0; 976fe56b9e6SYuval Mintz } 977fe56b9e6SYuval Mintz 9781a635e48SYuval Mintz int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) 979cc875c2eSYuval Mintz { 980cc875c2eSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; 981cc875c2eSYuval Mintz struct qed_ptt *p_ptt; 982cc875c2eSYuval Mintz 9831408cc1fSYuval Mintz if (IS_VF(cdev)) 9841408cc1fSYuval Mintz return -EINVAL; 9851408cc1fSYuval Mintz 986cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 987cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 988cc875c2eSYuval Mintz return -EBUSY; 989cc875c2eSYuval Mintz } 990cc875c2eSYuval Mintz 991cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 992cc875c2eSYuval Mintz 993cc875c2eSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 994cc875c2eSYuval Mintz if (!p_ptt) 995cc875c2eSYuval Mintz return -EBUSY; 996cc875c2eSYuval Mintz 997cc875c2eSYuval Mintz *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 998cc875c2eSYuval Mintz offsetof(struct public_port, media_type)); 999cc875c2eSYuval Mintz 1000cc875c2eSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 1001cc875c2eSYuval Mintz 1002cc875c2eSYuval Mintz return 0; 1003cc875c2eSYuval Mintz } 1004cc875c2eSYuval Mintz 1005fe56b9e6SYuval Mintz static int 1006fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 1007fe56b9e6SYuval Mintz struct public_func *p_info, 1008fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 1009fe56b9e6SYuval Mintz { 1010fe56b9e6SYuval Mintz int rc = 0; 1011fe56b9e6SYuval Mintz 1012fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 1013fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 1014c5ac9319SYuval Mintz if (test_bit(QED_DEV_CAP_ROCE, 1015c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities)) 1016c5ac9319SYuval Mintz *p_proto = QED_PCI_ETH_ROCE; 1017c5ac9319SYuval Mintz else 1018fe56b9e6SYuval Mintz *p_proto = QED_PCI_ETH; 1019fe56b9e6SYuval Mintz break; 1020c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 1021c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 1022c5ac9319SYuval Mintz break; 1023c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 1024c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 1025c5ac9319SYuval Mintz rc = -EINVAL; 1026c5ac9319SYuval Mintz break; 1027fe56b9e6SYuval Mintz default: 1028fe56b9e6SYuval Mintz rc = -EINVAL; 1029fe56b9e6SYuval Mintz } 1030fe56b9e6SYuval Mintz 1031fe56b9e6SYuval Mintz return rc; 1032fe56b9e6SYuval Mintz } 1033fe56b9e6SYuval Mintz 1034fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 1035fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1036fe56b9e6SYuval Mintz { 1037fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 1038fe56b9e6SYuval Mintz struct public_func shmem_info; 1039fe56b9e6SYuval Mintz 10401a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1041fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 1042fe56b9e6SYuval Mintz 1043fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 1044fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 1045fe56b9e6SYuval Mintz 10461a635e48SYuval Mintz if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) { 1047fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 1048fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 1049fe56b9e6SYuval Mintz return -EINVAL; 1050fe56b9e6SYuval Mintz } 1051fe56b9e6SYuval Mintz 10524b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1053fe56b9e6SYuval Mintz 1054fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 1055fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 1056fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 1057fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 1058fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 1059fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 1060fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 1061fe56b9e6SYuval Mintz } else { 1062fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 1063fe56b9e6SYuval Mintz } 1064fe56b9e6SYuval Mintz 1065fe56b9e6SYuval Mintz info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper | 1066fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32); 1067fe56b9e6SYuval Mintz info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper | 1068fe56b9e6SYuval Mintz (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32); 1069fe56b9e6SYuval Mintz 1070fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 1071fe56b9e6SYuval Mintz 10720fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 10730fefbfbaSSudarsana Kalluru 1074fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 1075fe56b9e6SYuval Mintz "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x\n", 1076fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 1077fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 1078fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 1079fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 1080fe56b9e6SYuval Mintz info->wwn_port, info->wwn_node, info->ovlan); 1081fe56b9e6SYuval Mintz 1082fe56b9e6SYuval Mintz return 0; 1083fe56b9e6SYuval Mintz } 1084fe56b9e6SYuval Mintz 1085cc875c2eSYuval Mintz struct qed_mcp_link_params 1086cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 1087cc875c2eSYuval Mintz { 1088cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1089cc875c2eSYuval Mintz return NULL; 1090cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 1091cc875c2eSYuval Mintz } 1092cc875c2eSYuval Mintz 1093cc875c2eSYuval Mintz struct qed_mcp_link_state 1094cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 1095cc875c2eSYuval Mintz { 1096cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1097cc875c2eSYuval Mintz return NULL; 1098cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 1099cc875c2eSYuval Mintz } 1100cc875c2eSYuval Mintz 1101cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 1102cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 1103cc875c2eSYuval Mintz { 1104cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 1105cc875c2eSYuval Mintz return NULL; 1106cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 1107cc875c2eSYuval Mintz } 1108cc875c2eSYuval Mintz 11091a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1110fe56b9e6SYuval Mintz { 1111fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 1112fe56b9e6SYuval Mintz int rc; 1113fe56b9e6SYuval Mintz 1114fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 11151a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 1116fe56b9e6SYuval Mintz 1117fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 11188f60bafeSYuval Mintz msleep(1020); 1119fe56b9e6SYuval Mintz 1120fe56b9e6SYuval Mintz return rc; 1121fe56b9e6SYuval Mintz } 1122fe56b9e6SYuval Mintz 1123cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 11241a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 1125cee4d264SManish Chopra { 1126cee4d264SManish Chopra u32 flash_size; 1127cee4d264SManish Chopra 11281408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 11291408cc1fSYuval Mintz return -EINVAL; 11301408cc1fSYuval Mintz 1131cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 1132cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 1133cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 1134cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 1135cee4d264SManish Chopra 1136cee4d264SManish Chopra *p_flash_size = flash_size; 1137cee4d264SManish Chopra 1138cee4d264SManish Chopra return 0; 1139cee4d264SManish Chopra } 1140cee4d264SManish Chopra 11411408cc1fSYuval Mintz int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 11421408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 11431408cc1fSYuval Mintz { 11441408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 11451408cc1fSYuval Mintz int rc; 11461408cc1fSYuval Mintz 11471408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 11481408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 11491408cc1fSYuval Mintz return 0; 11501408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 11511408cc1fSYuval Mintz 11521408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 11531408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 11541408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 11551408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 11561408cc1fSYuval Mintz 11571408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 11581408cc1fSYuval Mintz &resp, &rc_param); 11591408cc1fSYuval Mintz 11601408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 11611408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 11621408cc1fSYuval Mintz rc = -EINVAL; 11631408cc1fSYuval Mintz } else { 11641408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 11651408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 11661408cc1fSYuval Mintz num, vf_id); 11671408cc1fSYuval Mintz } 11681408cc1fSYuval Mintz 11691408cc1fSYuval Mintz return rc; 11701408cc1fSYuval Mintz } 11711408cc1fSYuval Mintz 1172fe56b9e6SYuval Mintz int 1173fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 1174fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1175fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 1176fe56b9e6SYuval Mintz { 11775529bad9STomer Tayar struct drv_version_stc *p_drv_version; 11785529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 11795529bad9STomer Tayar union drv_union_data union_data; 11805529bad9STomer Tayar __be32 val; 11815529bad9STomer Tayar u32 i; 11825529bad9STomer Tayar int rc; 1183fe56b9e6SYuval Mintz 11845529bad9STomer Tayar p_drv_version = &union_data.drv_version; 11855529bad9STomer Tayar p_drv_version->version = p_ver->version; 11864b01e519SManish Chopra 118767a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 118867a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 11894b01e519SManish Chopra *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val; 1190fe56b9e6SYuval Mintz } 1191fe56b9e6SYuval Mintz 11925529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11935529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 11945529bad9STomer Tayar mb_params.p_data_src = &union_data; 11955529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11965529bad9STomer Tayar if (rc) 1197fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1198fe56b9e6SYuval Mintz 11995529bad9STomer Tayar return rc; 1200fe56b9e6SYuval Mintz } 120191420b83SSudarsana Kalluru 12024102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 12034102426fSTomer Tayar { 12044102426fSTomer Tayar u32 resp = 0, param = 0; 12054102426fSTomer Tayar int rc; 12064102426fSTomer Tayar 12074102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 12084102426fSTomer Tayar ¶m); 12094102426fSTomer Tayar if (rc) 12104102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 12114102426fSTomer Tayar 12124102426fSTomer Tayar return rc; 12134102426fSTomer Tayar } 12144102426fSTomer Tayar 12154102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 12164102426fSTomer Tayar { 12174102426fSTomer Tayar u32 value, cpu_mode; 12184102426fSTomer Tayar 12194102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 12204102426fSTomer Tayar 12214102426fSTomer Tayar value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 12224102426fSTomer Tayar value &= ~MCP_REG_CPU_MODE_SOFT_HALT; 12234102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); 12244102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 12254102426fSTomer Tayar 12264102426fSTomer Tayar return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; 12274102426fSTomer Tayar } 12284102426fSTomer Tayar 12290fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 12300fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 12310fefbfbaSSudarsana Kalluru enum qed_ov_client client) 12320fefbfbaSSudarsana Kalluru { 12330fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 12340fefbfbaSSudarsana Kalluru u32 drv_mb_param; 12350fefbfbaSSudarsana Kalluru int rc; 12360fefbfbaSSudarsana Kalluru 12370fefbfbaSSudarsana Kalluru switch (client) { 12380fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 12390fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 12400fefbfbaSSudarsana Kalluru break; 12410fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 12420fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 12430fefbfbaSSudarsana Kalluru break; 12440fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 12450fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 12460fefbfbaSSudarsana Kalluru break; 12470fefbfbaSSudarsana Kalluru default: 12480fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 12490fefbfbaSSudarsana Kalluru return -EINVAL; 12500fefbfbaSSudarsana Kalluru } 12510fefbfbaSSudarsana Kalluru 12520fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 12530fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 12540fefbfbaSSudarsana Kalluru if (rc) 12550fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 12560fefbfbaSSudarsana Kalluru 12570fefbfbaSSudarsana Kalluru return rc; 12580fefbfbaSSudarsana Kalluru } 12590fefbfbaSSudarsana Kalluru 12600fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 12610fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 12620fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 12630fefbfbaSSudarsana Kalluru { 12640fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 12650fefbfbaSSudarsana Kalluru u32 drv_mb_param; 12660fefbfbaSSudarsana Kalluru int rc; 12670fefbfbaSSudarsana Kalluru 12680fefbfbaSSudarsana Kalluru switch (drv_state) { 12690fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 12700fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 12710fefbfbaSSudarsana Kalluru break; 12720fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 12730fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 12740fefbfbaSSudarsana Kalluru break; 12750fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 12760fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 12770fefbfbaSSudarsana Kalluru break; 12780fefbfbaSSudarsana Kalluru default: 12790fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 12800fefbfbaSSudarsana Kalluru return -EINVAL; 12810fefbfbaSSudarsana Kalluru } 12820fefbfbaSSudarsana Kalluru 12830fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 12840fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 12850fefbfbaSSudarsana Kalluru if (rc) 12860fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 12870fefbfbaSSudarsana Kalluru 12880fefbfbaSSudarsana Kalluru return rc; 12890fefbfbaSSudarsana Kalluru } 12900fefbfbaSSudarsana Kalluru 12910fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 12920fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 12930fefbfbaSSudarsana Kalluru { 12940fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 12950fefbfbaSSudarsana Kalluru u32 drv_mb_param; 12960fefbfbaSSudarsana Kalluru int rc; 12970fefbfbaSSudarsana Kalluru 12980fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 12990fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 13000fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 13010fefbfbaSSudarsana Kalluru if (rc) 13020fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 13030fefbfbaSSudarsana Kalluru 13040fefbfbaSSudarsana Kalluru return rc; 13050fefbfbaSSudarsana Kalluru } 13060fefbfbaSSudarsana Kalluru 13070fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 13080fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 13090fefbfbaSSudarsana Kalluru { 13100fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 13110fefbfbaSSudarsana Kalluru union drv_union_data union_data; 13120fefbfbaSSudarsana Kalluru int rc; 13130fefbfbaSSudarsana Kalluru 13140fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 13150fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 13160fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 13170fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 13180fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 13190fefbfbaSSudarsana Kalluru ether_addr_copy(&union_data.raw_data[0], mac); 13200fefbfbaSSudarsana Kalluru mb_params.p_data_src = &union_data; 13210fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 13220fefbfbaSSudarsana Kalluru if (rc) 13230fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 13240fefbfbaSSudarsana Kalluru 13250fefbfbaSSudarsana Kalluru return rc; 13260fefbfbaSSudarsana Kalluru } 13270fefbfbaSSudarsana Kalluru 13280fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 13290fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 13300fefbfbaSSudarsana Kalluru { 13310fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 13320fefbfbaSSudarsana Kalluru u32 drv_mb_param; 13330fefbfbaSSudarsana Kalluru int rc; 13340fefbfbaSSudarsana Kalluru 13350fefbfbaSSudarsana Kalluru switch (wol) { 13360fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 13370fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 13380fefbfbaSSudarsana Kalluru break; 13390fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 13400fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 13410fefbfbaSSudarsana Kalluru break; 13420fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 13430fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 13440fefbfbaSSudarsana Kalluru break; 13450fefbfbaSSudarsana Kalluru default: 13460fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 13470fefbfbaSSudarsana Kalluru return -EINVAL; 13480fefbfbaSSudarsana Kalluru } 13490fefbfbaSSudarsana Kalluru 13500fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 13510fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 13520fefbfbaSSudarsana Kalluru if (rc) 13530fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 13540fefbfbaSSudarsana Kalluru 13550fefbfbaSSudarsana Kalluru return rc; 13560fefbfbaSSudarsana Kalluru } 13570fefbfbaSSudarsana Kalluru 13580fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 13590fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 13600fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 13610fefbfbaSSudarsana Kalluru { 13620fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 13630fefbfbaSSudarsana Kalluru u32 drv_mb_param; 13640fefbfbaSSudarsana Kalluru int rc; 13650fefbfbaSSudarsana Kalluru 13660fefbfbaSSudarsana Kalluru switch (eswitch) { 13670fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 13680fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 13690fefbfbaSSudarsana Kalluru break; 13700fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 13710fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 13720fefbfbaSSudarsana Kalluru break; 13730fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 13740fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 13750fefbfbaSSudarsana Kalluru break; 13760fefbfbaSSudarsana Kalluru default: 13770fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 13780fefbfbaSSudarsana Kalluru return -EINVAL; 13790fefbfbaSSudarsana Kalluru } 13800fefbfbaSSudarsana Kalluru 13810fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 13820fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 13830fefbfbaSSudarsana Kalluru if (rc) 13840fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 13850fefbfbaSSudarsana Kalluru 13860fefbfbaSSudarsana Kalluru return rc; 13870fefbfbaSSudarsana Kalluru } 13880fefbfbaSSudarsana Kalluru 13891a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 13901a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 139191420b83SSudarsana Kalluru { 139291420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 139391420b83SSudarsana Kalluru int rc; 139491420b83SSudarsana Kalluru 139591420b83SSudarsana Kalluru switch (mode) { 139691420b83SSudarsana Kalluru case QED_LED_MODE_ON: 139791420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 139891420b83SSudarsana Kalluru break; 139991420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 140091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 140191420b83SSudarsana Kalluru break; 140291420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 140391420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 140491420b83SSudarsana Kalluru break; 140591420b83SSudarsana Kalluru default: 140691420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 140791420b83SSudarsana Kalluru return -EINVAL; 140891420b83SSudarsana Kalluru } 140991420b83SSudarsana Kalluru 141091420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 141191420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 141291420b83SSudarsana Kalluru 141391420b83SSudarsana Kalluru return rc; 141491420b83SSudarsana Kalluru } 141503dc76caSSudarsana Reddy Kalluru 14164102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 14174102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 14184102426fSTomer Tayar { 14194102426fSTomer Tayar u32 resp = 0, param = 0; 14204102426fSTomer Tayar int rc; 14214102426fSTomer Tayar 14224102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 14234102426fSTomer Tayar mask_parities, &resp, ¶m); 14244102426fSTomer Tayar 14254102426fSTomer Tayar if (rc) { 14264102426fSTomer Tayar DP_ERR(p_hwfn, 14274102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 14284102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 14294102426fSTomer Tayar DP_ERR(p_hwfn, 14304102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 14314102426fSTomer Tayar rc = -EINVAL; 14324102426fSTomer Tayar } 14334102426fSTomer Tayar 14344102426fSTomer Tayar return rc; 14354102426fSTomer Tayar } 14364102426fSTomer Tayar 143703dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 143803dc76caSSudarsana Reddy Kalluru { 143903dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 144003dc76caSSudarsana Reddy Kalluru int rc = 0; 144103dc76caSSudarsana Reddy Kalluru 144203dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 144303dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 144403dc76caSSudarsana Reddy Kalluru 144503dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 144603dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 144703dc76caSSudarsana Reddy Kalluru 144803dc76caSSudarsana Reddy Kalluru if (rc) 144903dc76caSSudarsana Reddy Kalluru return rc; 145003dc76caSSudarsana Reddy Kalluru 145103dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 145203dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 145303dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 145403dc76caSSudarsana Reddy Kalluru 145503dc76caSSudarsana Reddy Kalluru return rc; 145603dc76caSSudarsana Reddy Kalluru } 145703dc76caSSudarsana Reddy Kalluru 145803dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 145903dc76caSSudarsana Reddy Kalluru { 146003dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 146103dc76caSSudarsana Reddy Kalluru int rc = 0; 146203dc76caSSudarsana Reddy Kalluru 146303dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 146403dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 146503dc76caSSudarsana Reddy Kalluru 146603dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 146703dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 146803dc76caSSudarsana Reddy Kalluru 146903dc76caSSudarsana Reddy Kalluru if (rc) 147003dc76caSSudarsana Reddy Kalluru return rc; 147103dc76caSSudarsana Reddy Kalluru 147203dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 147303dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 147403dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 147503dc76caSSudarsana Reddy Kalluru 147603dc76caSSudarsana Reddy Kalluru return rc; 147703dc76caSSudarsana Reddy Kalluru } 1478