1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 395529bad9STomer Tayar #include <linux/spinlock.h> 40fe56b9e6SYuval Mintz #include <linux/string.h> 410fefbfbaSSudarsana Kalluru #include <linux/etherdevice.h> 42fe56b9e6SYuval Mintz #include "qed.h" 43cac6f691SSudarsana Reddy Kalluru #include "qed_cxt.h" 4439651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 45fe56b9e6SYuval Mintz #include "qed_hsi.h" 46fe56b9e6SYuval Mintz #include "qed_hw.h" 47fe56b9e6SYuval Mintz #include "qed_mcp.h" 48fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 491408cc1fSYuval Mintz #include "qed_sriov.h" 501408cc1fSYuval Mintz 51eaa50fc5STomer Tayar #define QED_MCP_RESP_ITER_US 10 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ 54fe56b9e6SYuval Mintz #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ 57fe56b9e6SYuval Mintz qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ 58fe56b9e6SYuval Mintz _val) 59fe56b9e6SYuval Mintz 60fe56b9e6SYuval Mintz #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ 61fe56b9e6SYuval Mintz qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) 62fe56b9e6SYuval Mintz 63fe56b9e6SYuval Mintz #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ 64fe56b9e6SYuval Mintz DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ 65fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field), _val) 66fe56b9e6SYuval Mintz 67fe56b9e6SYuval Mintz #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ 68fe56b9e6SYuval Mintz DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ 69fe56b9e6SYuval Mintz offsetof(struct public_drv_mb, _field)) 70fe56b9e6SYuval Mintz 71fe56b9e6SYuval Mintz #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ 72fe56b9e6SYuval Mintz DRV_ID_PDA_COMP_VER_SHIFT) 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz #define MCP_BYTES_PER_MBIT_SHIFT 17 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) 77fe56b9e6SYuval Mintz { 78fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) 79fe56b9e6SYuval Mintz return false; 80fe56b9e6SYuval Mintz return true; 81fe56b9e6SYuval Mintz } 82fe56b9e6SYuval Mintz 831a635e48SYuval Mintz void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84fe56b9e6SYuval Mintz { 85fe56b9e6SYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 86fe56b9e6SYuval Mintz PUBLIC_PORT); 87fe56b9e6SYuval Mintz u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, 90fe56b9e6SYuval Mintz MFW_PORT(p_hwfn)); 91fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 92fe56b9e6SYuval Mintz "port_addr = 0x%x, port_id 0x%02x\n", 93fe56b9e6SYuval Mintz p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); 94fe56b9e6SYuval Mintz } 95fe56b9e6SYuval Mintz 961a635e48SYuval Mintz void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 97fe56b9e6SYuval Mintz { 98fe56b9e6SYuval Mintz u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); 99fe56b9e6SYuval Mintz u32 tmp, i; 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info->public_base) 102fe56b9e6SYuval Mintz return; 103fe56b9e6SYuval Mintz 104fe56b9e6SYuval Mintz for (i = 0; i < length; i++) { 105fe56b9e6SYuval Mintz tmp = qed_rd(p_hwfn, p_ptt, 106fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_addr + 107fe56b9e6SYuval Mintz (i << 2) + sizeof(u32)); 108fe56b9e6SYuval Mintz 109fe56b9e6SYuval Mintz /* The MB data is actually BE; Need to force it to cpu */ 110fe56b9e6SYuval Mintz ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = 111fe56b9e6SYuval Mintz be32_to_cpu((__force __be32)tmp); 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz } 114fe56b9e6SYuval Mintz 1154ed1eea8STomer Tayar struct qed_mcp_cmd_elem { 1164ed1eea8STomer Tayar struct list_head list; 1174ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 1184ed1eea8STomer Tayar u16 expected_seq_num; 1194ed1eea8STomer Tayar bool b_is_completed; 1204ed1eea8STomer Tayar }; 1214ed1eea8STomer Tayar 1224ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1234ed1eea8STomer Tayar static struct qed_mcp_cmd_elem * 1244ed1eea8STomer Tayar qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, 1254ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 1264ed1eea8STomer Tayar u16 expected_seq_num) 1274ed1eea8STomer Tayar { 1284ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1294ed1eea8STomer Tayar 1304ed1eea8STomer Tayar p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); 1314ed1eea8STomer Tayar if (!p_cmd_elem) 1324ed1eea8STomer Tayar goto out; 1334ed1eea8STomer Tayar 1344ed1eea8STomer Tayar p_cmd_elem->p_mb_params = p_mb_params; 1354ed1eea8STomer Tayar p_cmd_elem->expected_seq_num = expected_seq_num; 1364ed1eea8STomer Tayar list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); 1374ed1eea8STomer Tayar out: 1384ed1eea8STomer Tayar return p_cmd_elem; 1394ed1eea8STomer Tayar } 1404ed1eea8STomer Tayar 1414ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1424ed1eea8STomer Tayar static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, 1434ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem) 1444ed1eea8STomer Tayar { 1454ed1eea8STomer Tayar list_del(&p_cmd_elem->list); 1464ed1eea8STomer Tayar kfree(p_cmd_elem); 1474ed1eea8STomer Tayar } 1484ed1eea8STomer Tayar 1494ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 1504ed1eea8STomer Tayar static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, 1514ed1eea8STomer Tayar u16 seq_num) 1524ed1eea8STomer Tayar { 1534ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem = NULL; 1544ed1eea8STomer Tayar 1554ed1eea8STomer Tayar list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { 1564ed1eea8STomer Tayar if (p_cmd_elem->expected_seq_num == seq_num) 1574ed1eea8STomer Tayar return p_cmd_elem; 1584ed1eea8STomer Tayar } 1594ed1eea8STomer Tayar 1604ed1eea8STomer Tayar return NULL; 1614ed1eea8STomer Tayar } 1624ed1eea8STomer Tayar 163fe56b9e6SYuval Mintz int qed_mcp_free(struct qed_hwfn *p_hwfn) 164fe56b9e6SYuval Mintz { 165fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1664ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; 1674ed1eea8STomer Tayar 168fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_cur); 169fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info->mfw_mb_shadow); 1704ed1eea8STomer Tayar 1714ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 1724ed1eea8STomer Tayar list_for_each_entry_safe(p_cmd_elem, 1734ed1eea8STomer Tayar p_tmp, 1744ed1eea8STomer Tayar &p_hwfn->mcp_info->cmd_list, list) { 1754ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 176fe56b9e6SYuval Mintz } 1774ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 1784ed1eea8STomer Tayar } 1794ed1eea8STomer Tayar 180fe56b9e6SYuval Mintz kfree(p_hwfn->mcp_info); 1813587cb87STomer Tayar p_hwfn->mcp_info = NULL; 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz return 0; 184fe56b9e6SYuval Mintz } 185fe56b9e6SYuval Mintz 186f00d25f3STomer Tayar /* Maximum of 1 sec to wait for the SHMEM ready indication */ 187f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_MAX_RETRIES 20 188f00d25f3STomer Tayar #define QED_MCP_SHMEM_RDY_ITER_MS 50 189f00d25f3STomer Tayar 1901a635e48SYuval Mintz static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 191fe56b9e6SYuval Mintz { 192fe56b9e6SYuval Mintz struct qed_mcp_info *p_info = p_hwfn->mcp_info; 193f00d25f3STomer Tayar u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES; 194f00d25f3STomer Tayar u8 msec = QED_MCP_SHMEM_RDY_ITER_MS; 195fe56b9e6SYuval Mintz u32 drv_mb_offsize, mfw_mb_offsize; 196fe56b9e6SYuval Mintz u32 mcp_pf_id = MCP_PF_ID(p_hwfn); 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); 199f00d25f3STomer Tayar if (!p_info->public_base) { 200f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 201f00d25f3STomer Tayar "The address of the MCP scratch-pad is not configured\n"); 202f00d25f3STomer Tayar return -EINVAL; 203f00d25f3STomer Tayar } 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz p_info->public_base |= GRCBASE_MCP; 206fe56b9e6SYuval Mintz 207f00d25f3STomer Tayar /* Get the MFW MB address and number of supported messages */ 208f00d25f3STomer Tayar mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, 209f00d25f3STomer Tayar SECTION_OFFSIZE_ADDR(p_info->public_base, 210f00d25f3STomer Tayar PUBLIC_MFW_MB)); 211f00d25f3STomer Tayar p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); 212f00d25f3STomer Tayar p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, 213f00d25f3STomer Tayar p_info->mfw_mb_addr + 214f00d25f3STomer Tayar offsetof(struct public_mfw_mb, 215f00d25f3STomer Tayar sup_msgs)); 216f00d25f3STomer Tayar 217f00d25f3STomer Tayar /* The driver can notify that there was an MCP reset, and might read the 218f00d25f3STomer Tayar * SHMEM values before the MFW has completed initializing them. 219f00d25f3STomer Tayar * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a 220f00d25f3STomer Tayar * data ready indication. 221f00d25f3STomer Tayar */ 222f00d25f3STomer Tayar while (!p_info->mfw_mb_length && --cnt) { 223f00d25f3STomer Tayar msleep(msec); 224f00d25f3STomer Tayar p_info->mfw_mb_length = 225f00d25f3STomer Tayar (u16)qed_rd(p_hwfn, p_ptt, 226f00d25f3STomer Tayar p_info->mfw_mb_addr + 227f00d25f3STomer Tayar offsetof(struct public_mfw_mb, sup_msgs)); 228f00d25f3STomer Tayar } 229f00d25f3STomer Tayar 230f00d25f3STomer Tayar if (!cnt) { 231f00d25f3STomer Tayar DP_NOTICE(p_hwfn, 232f00d25f3STomer Tayar "Failed to get the SHMEM ready notification after %d msec\n", 233f00d25f3STomer Tayar QED_MCP_SHMEM_RDY_MAX_RETRIES * msec); 234f00d25f3STomer Tayar return -EBUSY; 235f00d25f3STomer Tayar } 236f00d25f3STomer Tayar 237fe56b9e6SYuval Mintz /* Calculate the driver and MFW mailbox address */ 238fe56b9e6SYuval Mintz drv_mb_offsize = qed_rd(p_hwfn, p_ptt, 239fe56b9e6SYuval Mintz SECTION_OFFSIZE_ADDR(p_info->public_base, 240fe56b9e6SYuval Mintz PUBLIC_DRV_MB)); 241fe56b9e6SYuval Mintz p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); 242fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 243fe56b9e6SYuval Mintz "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", 244fe56b9e6SYuval Mintz drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); 245fe56b9e6SYuval Mintz 246fe56b9e6SYuval Mintz /* Get the current driver mailbox sequence before sending 247fe56b9e6SYuval Mintz * the first command 248fe56b9e6SYuval Mintz */ 249fe56b9e6SYuval Mintz p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & 250fe56b9e6SYuval Mintz DRV_MSG_SEQ_NUMBER_MASK; 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz /* Get current FW pulse sequence */ 253fe56b9e6SYuval Mintz p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & 254fe56b9e6SYuval Mintz DRV_PULSE_SEQ_MASK; 255fe56b9e6SYuval Mintz 2564ed1eea8STomer Tayar p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 257fe56b9e6SYuval Mintz 258fe56b9e6SYuval Mintz return 0; 259fe56b9e6SYuval Mintz } 260fe56b9e6SYuval Mintz 2611a635e48SYuval Mintz int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 262fe56b9e6SYuval Mintz { 263fe56b9e6SYuval Mintz struct qed_mcp_info *p_info; 264fe56b9e6SYuval Mintz u32 size; 265fe56b9e6SYuval Mintz 266fe56b9e6SYuval Mintz /* Allocate mcp_info structure */ 26760fffb3bSYuval Mintz p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); 268fe56b9e6SYuval Mintz if (!p_hwfn->mcp_info) 269fe56b9e6SYuval Mintz goto err; 270fe56b9e6SYuval Mintz p_info = p_hwfn->mcp_info; 271fe56b9e6SYuval Mintz 2724ed1eea8STomer Tayar /* Initialize the MFW spinlock */ 2734ed1eea8STomer Tayar spin_lock_init(&p_info->cmd_lock); 2744ed1eea8STomer Tayar spin_lock_init(&p_info->link_lock); 2754ed1eea8STomer Tayar 2764ed1eea8STomer Tayar INIT_LIST_HEAD(&p_info->cmd_list); 2774ed1eea8STomer Tayar 278fe56b9e6SYuval Mintz if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { 279fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MCP is not initialized\n"); 280fe56b9e6SYuval Mintz /* Do not free mcp_info here, since public_base indicate that 281fe56b9e6SYuval Mintz * the MCP is not initialized 282fe56b9e6SYuval Mintz */ 283fe56b9e6SYuval Mintz return 0; 284fe56b9e6SYuval Mintz } 285fe56b9e6SYuval Mintz 286fe56b9e6SYuval Mintz size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); 28760fffb3bSYuval Mintz p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); 28883aeb933SYuval Mintz p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); 289eb2a6b80SChristophe Jaillet if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) 290fe56b9e6SYuval Mintz goto err; 291fe56b9e6SYuval Mintz 292fe56b9e6SYuval Mintz return 0; 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz err: 295fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 296fe56b9e6SYuval Mintz return -ENOMEM; 297fe56b9e6SYuval Mintz } 298fe56b9e6SYuval Mintz 2994ed1eea8STomer Tayar static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, 3004ed1eea8STomer Tayar struct qed_ptt *p_ptt) 3015529bad9STomer Tayar { 3024ed1eea8STomer Tayar u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3035529bad9STomer Tayar 3044ed1eea8STomer Tayar /* Use MCP history register to check if MCP reset occurred between init 3054ed1eea8STomer Tayar * time and now. 3065529bad9STomer Tayar */ 3074ed1eea8STomer Tayar if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { 3084ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 3094ed1eea8STomer Tayar QED_MSG_SP, 3104ed1eea8STomer Tayar "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", 3114ed1eea8STomer Tayar p_hwfn->mcp_info->mcp_hist, generic_por_0); 3125529bad9STomer Tayar 3134ed1eea8STomer Tayar qed_load_mcp_offsets(p_hwfn, p_ptt); 3144ed1eea8STomer Tayar qed_mcp_cmd_port_init(p_hwfn, p_ptt); 3155529bad9STomer Tayar } 3165529bad9STomer Tayar } 3175529bad9STomer Tayar 3181a635e48SYuval Mintz int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 319fe56b9e6SYuval Mintz { 320eaa50fc5STomer Tayar u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0; 321fe56b9e6SYuval Mintz int rc = 0; 322fe56b9e6SYuval Mintz 323b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 324b310974eSTomer Tayar DP_NOTICE(p_hwfn, 325b310974eSTomer Tayar "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n"); 326b310974eSTomer Tayar return -EBUSY; 327b310974eSTomer Tayar } 328b310974eSTomer Tayar 3294ed1eea8STomer Tayar /* Ensure that only a single thread is accessing the mailbox */ 3304ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 3314ed1eea8STomer Tayar 3324ed1eea8STomer Tayar org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); 3335529bad9STomer Tayar 334fe56b9e6SYuval Mintz /* Set drv command along with the updated sequence */ 3354ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 3364ed1eea8STomer Tayar seq = ++p_hwfn->mcp_info->drv_mb_seq; 3374ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); 338fe56b9e6SYuval Mintz 339fe56b9e6SYuval Mintz do { 340fe56b9e6SYuval Mintz /* Wait for MFW response */ 341fe56b9e6SYuval Mintz udelay(delay); 342fe56b9e6SYuval Mintz /* Give the FW up to 500 second (50*1000*10usec) */ 343fe56b9e6SYuval Mintz } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, 344fe56b9e6SYuval Mintz MISCS_REG_GENERIC_POR_0)) && 345fe56b9e6SYuval Mintz (cnt++ < QED_MCP_RESET_RETRIES)); 346fe56b9e6SYuval Mintz 347fe56b9e6SYuval Mintz if (org_mcp_reset_seq != 348fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { 349fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 350fe56b9e6SYuval Mintz "MCP was reset after %d usec\n", cnt * delay); 351fe56b9e6SYuval Mintz } else { 352fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Failed to reset MCP\n"); 353fe56b9e6SYuval Mintz rc = -EAGAIN; 354fe56b9e6SYuval Mintz } 355fe56b9e6SYuval Mintz 3564ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 3575529bad9STomer Tayar 358fe56b9e6SYuval Mintz return rc; 359fe56b9e6SYuval Mintz } 360fe56b9e6SYuval Mintz 3614ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3624ed1eea8STomer Tayar static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) 363fe56b9e6SYuval Mintz { 3644ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3654ed1eea8STomer Tayar 3664ed1eea8STomer Tayar /* There is at most one pending command at a certain time, and if it 3674ed1eea8STomer Tayar * exists - it is placed at the HEAD of the list. 3684ed1eea8STomer Tayar */ 3694ed1eea8STomer Tayar if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { 3704ed1eea8STomer Tayar p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, 3714ed1eea8STomer Tayar struct qed_mcp_cmd_elem, list); 3724ed1eea8STomer Tayar return !p_cmd_elem->b_is_completed; 3734ed1eea8STomer Tayar } 3744ed1eea8STomer Tayar 3754ed1eea8STomer Tayar return false; 3764ed1eea8STomer Tayar } 3774ed1eea8STomer Tayar 3784ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 3794ed1eea8STomer Tayar static int 3804ed1eea8STomer Tayar qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3814ed1eea8STomer Tayar { 3824ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params; 3834ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 3844ed1eea8STomer Tayar u32 mcp_resp; 3854ed1eea8STomer Tayar u16 seq_num; 3864ed1eea8STomer Tayar 3874ed1eea8STomer Tayar mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); 3884ed1eea8STomer Tayar seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); 3894ed1eea8STomer Tayar 3904ed1eea8STomer Tayar /* Return if no new non-handled response has been received */ 3914ed1eea8STomer Tayar if (seq_num != p_hwfn->mcp_info->drv_mb_seq) 3924ed1eea8STomer Tayar return -EAGAIN; 3934ed1eea8STomer Tayar 3944ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); 3954ed1eea8STomer Tayar if (!p_cmd_elem) { 3964ed1eea8STomer Tayar DP_ERR(p_hwfn, 3974ed1eea8STomer Tayar "Failed to find a pending mailbox cmd that expects sequence number %d\n", 3984ed1eea8STomer Tayar seq_num); 3994ed1eea8STomer Tayar return -EINVAL; 4004ed1eea8STomer Tayar } 4014ed1eea8STomer Tayar 4024ed1eea8STomer Tayar p_mb_params = p_cmd_elem->p_mb_params; 4034ed1eea8STomer Tayar 4044ed1eea8STomer Tayar /* Get the MFW response along with the sequence number */ 4054ed1eea8STomer Tayar p_mb_params->mcp_resp = mcp_resp; 4064ed1eea8STomer Tayar 4074ed1eea8STomer Tayar /* Get the MFW param */ 4084ed1eea8STomer Tayar p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); 4094ed1eea8STomer Tayar 4104ed1eea8STomer Tayar /* Get the union data */ 4112f67af8cSTomer Tayar if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { 4124ed1eea8STomer Tayar u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4134ed1eea8STomer Tayar offsetof(struct public_drv_mb, 4144ed1eea8STomer Tayar union_data); 4154ed1eea8STomer Tayar qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, 4162f67af8cSTomer Tayar union_data_addr, p_mb_params->data_dst_size); 4174ed1eea8STomer Tayar } 4184ed1eea8STomer Tayar 4194ed1eea8STomer Tayar p_cmd_elem->b_is_completed = true; 4204ed1eea8STomer Tayar 4214ed1eea8STomer Tayar return 0; 4224ed1eea8STomer Tayar } 4234ed1eea8STomer Tayar 4244ed1eea8STomer Tayar /* Must be called while cmd_lock is acquired */ 4254ed1eea8STomer Tayar static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4264ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4274ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 4284ed1eea8STomer Tayar u16 seq_num) 4294ed1eea8STomer Tayar { 4304ed1eea8STomer Tayar union drv_union_data union_data; 4314ed1eea8STomer Tayar u32 union_data_addr; 4324ed1eea8STomer Tayar 4334ed1eea8STomer Tayar /* Set the union data */ 4344ed1eea8STomer Tayar union_data_addr = p_hwfn->mcp_info->drv_mb_addr + 4354ed1eea8STomer Tayar offsetof(struct public_drv_mb, union_data); 4364ed1eea8STomer Tayar memset(&union_data, 0, sizeof(union_data)); 4372f67af8cSTomer Tayar if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) 4384ed1eea8STomer Tayar memcpy(&union_data, p_mb_params->p_data_src, 4392f67af8cSTomer Tayar p_mb_params->data_src_size); 4404ed1eea8STomer Tayar qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, 4414ed1eea8STomer Tayar sizeof(union_data)); 4424ed1eea8STomer Tayar 4434ed1eea8STomer Tayar /* Set the drv param */ 4444ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); 4454ed1eea8STomer Tayar 4464ed1eea8STomer Tayar /* Set the drv command along with the sequence number */ 4474ed1eea8STomer Tayar DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); 4484ed1eea8STomer Tayar 4494ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 4504ed1eea8STomer Tayar "MFW mailbox: command 0x%08x param 0x%08x\n", 4514ed1eea8STomer Tayar (p_mb_params->cmd | seq_num), p_mb_params->param); 4524ed1eea8STomer Tayar } 4534ed1eea8STomer Tayar 454b310974eSTomer Tayar static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd) 455b310974eSTomer Tayar { 456b310974eSTomer Tayar p_hwfn->mcp_info->b_block_cmd = block_cmd; 457b310974eSTomer Tayar 458b310974eSTomer Tayar DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n", 459b310974eSTomer Tayar block_cmd ? "Block" : "Unblock"); 460b310974eSTomer Tayar } 461b310974eSTomer Tayar 462b310974eSTomer Tayar static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn, 463b310974eSTomer Tayar struct qed_ptt *p_ptt) 464b310974eSTomer Tayar { 465b310974eSTomer Tayar u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2; 466b310974eSTomer Tayar u32 delay = QED_MCP_RESP_ITER_US; 467b310974eSTomer Tayar 468b310974eSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 469b310974eSTomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 470b310974eSTomer Tayar cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 471b310974eSTomer Tayar udelay(delay); 472b310974eSTomer Tayar cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 473b310974eSTomer Tayar udelay(delay); 474b310974eSTomer Tayar cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER); 475b310974eSTomer Tayar 476b310974eSTomer Tayar DP_NOTICE(p_hwfn, 477b310974eSTomer Tayar "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n", 478b310974eSTomer Tayar cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2); 479b310974eSTomer Tayar } 480b310974eSTomer Tayar 4814ed1eea8STomer Tayar static int 4824ed1eea8STomer Tayar _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 4834ed1eea8STomer Tayar struct qed_ptt *p_ptt, 4844ed1eea8STomer Tayar struct qed_mcp_mb_params *p_mb_params, 485eaa50fc5STomer Tayar u32 max_retries, u32 usecs) 4864ed1eea8STomer Tayar { 487eaa50fc5STomer Tayar u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000); 4884ed1eea8STomer Tayar struct qed_mcp_cmd_elem *p_cmd_elem; 4894ed1eea8STomer Tayar u16 seq_num; 490fe56b9e6SYuval Mintz int rc = 0; 491fe56b9e6SYuval Mintz 4924ed1eea8STomer Tayar /* Wait until the mailbox is non-occupied */ 493fe56b9e6SYuval Mintz do { 4944ed1eea8STomer Tayar /* Exit the loop if there is no pending command, or if the 4954ed1eea8STomer Tayar * pending command is completed during this iteration. 4964ed1eea8STomer Tayar * The spinlock stays locked until the command is sent. 4974ed1eea8STomer Tayar */ 4984ed1eea8STomer Tayar 4994ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5004ed1eea8STomer Tayar 5014ed1eea8STomer Tayar if (!qed_mcp_has_pending_cmd(p_hwfn)) 5024ed1eea8STomer Tayar break; 5034ed1eea8STomer Tayar 5044ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5054ed1eea8STomer Tayar if (!rc) 5064ed1eea8STomer Tayar break; 5074ed1eea8STomer Tayar else if (rc != -EAGAIN) 5084ed1eea8STomer Tayar goto err; 5094ed1eea8STomer Tayar 5104ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 511eaa50fc5STomer Tayar 512eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 513eaa50fc5STomer Tayar msleep(msecs); 514eaa50fc5STomer Tayar else 515eaa50fc5STomer Tayar udelay(usecs); 5164ed1eea8STomer Tayar } while (++cnt < max_retries); 517fe56b9e6SYuval Mintz 5184ed1eea8STomer Tayar if (cnt >= max_retries) { 5194ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5204ed1eea8STomer Tayar "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", 5214ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 5224ed1eea8STomer Tayar return -EAGAIN; 523fe56b9e6SYuval Mintz } 5244ed1eea8STomer Tayar 5254ed1eea8STomer Tayar /* Send the mailbox command */ 5264ed1eea8STomer Tayar qed_mcp_reread_offsets(p_hwfn, p_ptt); 5274ed1eea8STomer Tayar seq_num = ++p_hwfn->mcp_info->drv_mb_seq; 5284ed1eea8STomer Tayar p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); 529c8004600SDan Carpenter if (!p_cmd_elem) { 530c8004600SDan Carpenter rc = -ENOMEM; 5314ed1eea8STomer Tayar goto err; 532c8004600SDan Carpenter } 5334ed1eea8STomer Tayar 5344ed1eea8STomer Tayar __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); 5354ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5364ed1eea8STomer Tayar 5374ed1eea8STomer Tayar /* Wait for the MFW response */ 5384ed1eea8STomer Tayar do { 5394ed1eea8STomer Tayar /* Exit the loop if the command is already completed, or if the 5404ed1eea8STomer Tayar * command is completed during this iteration. 5414ed1eea8STomer Tayar * The spinlock stays locked until the list element is removed. 5424ed1eea8STomer Tayar */ 5434ed1eea8STomer Tayar 544eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) 545eaa50fc5STomer Tayar msleep(msecs); 546eaa50fc5STomer Tayar else 547eaa50fc5STomer Tayar udelay(usecs); 548eaa50fc5STomer Tayar 5494ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5504ed1eea8STomer Tayar 5514ed1eea8STomer Tayar if (p_cmd_elem->b_is_completed) 5524ed1eea8STomer Tayar break; 5534ed1eea8STomer Tayar 5544ed1eea8STomer Tayar rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); 5554ed1eea8STomer Tayar if (!rc) 5564ed1eea8STomer Tayar break; 5574ed1eea8STomer Tayar else if (rc != -EAGAIN) 5584ed1eea8STomer Tayar goto err; 5594ed1eea8STomer Tayar 5604ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5614ed1eea8STomer Tayar } while (++cnt < max_retries); 5624ed1eea8STomer Tayar 5634ed1eea8STomer Tayar if (cnt >= max_retries) { 5644ed1eea8STomer Tayar DP_NOTICE(p_hwfn, 5654ed1eea8STomer Tayar "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", 5664ed1eea8STomer Tayar p_mb_params->cmd, p_mb_params->param); 567b310974eSTomer Tayar qed_mcp_print_cpu_info(p_hwfn, p_ptt); 5684ed1eea8STomer Tayar 5694ed1eea8STomer Tayar spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); 5704ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5714ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5724ed1eea8STomer Tayar 573b310974eSTomer Tayar if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK)) 574b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 575b310974eSTomer Tayar 5764ed1eea8STomer Tayar return -EAGAIN; 5774ed1eea8STomer Tayar } 5784ed1eea8STomer Tayar 5794ed1eea8STomer Tayar qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); 5804ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 5814ed1eea8STomer Tayar 5824ed1eea8STomer Tayar DP_VERBOSE(p_hwfn, 5834ed1eea8STomer Tayar QED_MSG_SP, 5844ed1eea8STomer Tayar "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", 5854ed1eea8STomer Tayar p_mb_params->mcp_resp, 5864ed1eea8STomer Tayar p_mb_params->mcp_param, 587eaa50fc5STomer Tayar (cnt * usecs) / 1000, (cnt * usecs) % 1000); 5884ed1eea8STomer Tayar 5894ed1eea8STomer Tayar /* Clear the sequence number from the MFW response */ 5904ed1eea8STomer Tayar p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; 5914ed1eea8STomer Tayar 5924ed1eea8STomer Tayar return 0; 5934ed1eea8STomer Tayar 5944ed1eea8STomer Tayar err: 5954ed1eea8STomer Tayar spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); 596fe56b9e6SYuval Mintz return rc; 597fe56b9e6SYuval Mintz } 598fe56b9e6SYuval Mintz 5995529bad9STomer Tayar static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, 600fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 6015529bad9STomer Tayar struct qed_mcp_mb_params *p_mb_params) 602fe56b9e6SYuval Mintz { 6032f67af8cSTomer Tayar size_t union_data_size = sizeof(union drv_union_data); 6044ed1eea8STomer Tayar u32 max_retries = QED_DRV_MB_MAX_RETRIES; 605eaa50fc5STomer Tayar u32 usecs = QED_MCP_RESP_ITER_US; 606fe56b9e6SYuval Mintz 607fe56b9e6SYuval Mintz /* MCP not initialized */ 608fe56b9e6SYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 609fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 610fe56b9e6SYuval Mintz return -EBUSY; 611fe56b9e6SYuval Mintz } 612fe56b9e6SYuval Mintz 613b310974eSTomer Tayar if (p_hwfn->mcp_info->b_block_cmd) { 614b310974eSTomer Tayar DP_NOTICE(p_hwfn, 615b310974eSTomer Tayar "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n", 616b310974eSTomer Tayar p_mb_params->cmd, p_mb_params->param); 617b310974eSTomer Tayar return -EBUSY; 618b310974eSTomer Tayar } 619b310974eSTomer Tayar 6202f67af8cSTomer Tayar if (p_mb_params->data_src_size > union_data_size || 6212f67af8cSTomer Tayar p_mb_params->data_dst_size > union_data_size) { 6222f67af8cSTomer Tayar DP_ERR(p_hwfn, 6232f67af8cSTomer Tayar "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", 6242f67af8cSTomer Tayar p_mb_params->data_src_size, 6252f67af8cSTomer Tayar p_mb_params->data_dst_size, union_data_size); 6262f67af8cSTomer Tayar return -EINVAL; 6272f67af8cSTomer Tayar } 6282f67af8cSTomer Tayar 629eaa50fc5STomer Tayar if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) { 630eaa50fc5STomer Tayar max_retries = DIV_ROUND_UP(max_retries, 1000); 631eaa50fc5STomer Tayar usecs *= 1000; 632eaa50fc5STomer Tayar } 633eaa50fc5STomer Tayar 6344ed1eea8STomer Tayar return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, 635eaa50fc5STomer Tayar usecs); 636fe56b9e6SYuval Mintz } 637fe56b9e6SYuval Mintz 6385529bad9STomer Tayar int qed_mcp_cmd(struct qed_hwfn *p_hwfn, 6395529bad9STomer Tayar struct qed_ptt *p_ptt, 6405529bad9STomer Tayar u32 cmd, 6415529bad9STomer Tayar u32 param, 6425529bad9STomer Tayar u32 *o_mcp_resp, 6435529bad9STomer Tayar u32 *o_mcp_param) 644fe56b9e6SYuval Mintz { 6455529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 6465529bad9STomer Tayar int rc; 647fe56b9e6SYuval Mintz 6485529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 6495529bad9STomer Tayar mb_params.cmd = cmd; 6505529bad9STomer Tayar mb_params.param = param; 65114d39648SMintz, Yuval 6525529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 6535529bad9STomer Tayar if (rc) 6545529bad9STomer Tayar return rc; 6555529bad9STomer Tayar 6565529bad9STomer Tayar *o_mcp_resp = mb_params.mcp_resp; 6575529bad9STomer Tayar *o_mcp_param = mb_params.mcp_param; 6585529bad9STomer Tayar 6595529bad9STomer Tayar return 0; 660fe56b9e6SYuval Mintz } 661fe56b9e6SYuval Mintz 662bf774d14SYueHaibing static int 663bf774d14SYueHaibing qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn, 66462e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 66562e4d438SSudarsana Reddy Kalluru u32 cmd, 66662e4d438SSudarsana Reddy Kalluru u32 param, 66762e4d438SSudarsana Reddy Kalluru u32 *o_mcp_resp, 66862e4d438SSudarsana Reddy Kalluru u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf) 66962e4d438SSudarsana Reddy Kalluru { 67062e4d438SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 67162e4d438SSudarsana Reddy Kalluru int rc; 67262e4d438SSudarsana Reddy Kalluru 67362e4d438SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 67462e4d438SSudarsana Reddy Kalluru mb_params.cmd = cmd; 67562e4d438SSudarsana Reddy Kalluru mb_params.param = param; 67662e4d438SSudarsana Reddy Kalluru mb_params.p_data_src = i_buf; 67762e4d438SSudarsana Reddy Kalluru mb_params.data_src_size = (u8)i_txn_size; 67862e4d438SSudarsana Reddy Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 67962e4d438SSudarsana Reddy Kalluru if (rc) 68062e4d438SSudarsana Reddy Kalluru return rc; 68162e4d438SSudarsana Reddy Kalluru 68262e4d438SSudarsana Reddy Kalluru *o_mcp_resp = mb_params.mcp_resp; 68362e4d438SSudarsana Reddy Kalluru *o_mcp_param = mb_params.mcp_param; 68462e4d438SSudarsana Reddy Kalluru 6855e7ba042SDenis Bolotin /* nvm_info needs to be updated */ 6865e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = false; 6875e7ba042SDenis Bolotin 68862e4d438SSudarsana Reddy Kalluru return 0; 68962e4d438SSudarsana Reddy Kalluru } 69062e4d438SSudarsana Reddy Kalluru 6914102426fSTomer Tayar int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, 6924102426fSTomer Tayar struct qed_ptt *p_ptt, 6934102426fSTomer Tayar u32 cmd, 6944102426fSTomer Tayar u32 param, 6954102426fSTomer Tayar u32 *o_mcp_resp, 6964102426fSTomer Tayar u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) 6974102426fSTomer Tayar { 6984102426fSTomer Tayar struct qed_mcp_mb_params mb_params; 6992f67af8cSTomer Tayar u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 7004102426fSTomer Tayar int rc; 7014102426fSTomer Tayar 7024102426fSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 7034102426fSTomer Tayar mb_params.cmd = cmd; 7044102426fSTomer Tayar mb_params.param = param; 7052f67af8cSTomer Tayar mb_params.p_data_dst = raw_data; 7062f67af8cSTomer Tayar 7072f67af8cSTomer Tayar /* Use the maximal value since the actual one is part of the response */ 7082f67af8cSTomer Tayar mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; 7092f67af8cSTomer Tayar 7104102426fSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 7114102426fSTomer Tayar if (rc) 7124102426fSTomer Tayar return rc; 7134102426fSTomer Tayar 7144102426fSTomer Tayar *o_mcp_resp = mb_params.mcp_resp; 7154102426fSTomer Tayar *o_mcp_param = mb_params.mcp_param; 7164102426fSTomer Tayar 7174102426fSTomer Tayar *o_txn_size = *o_mcp_param; 7182f67af8cSTomer Tayar memcpy(o_buf, raw_data, *o_txn_size); 7194102426fSTomer Tayar 7204102426fSTomer Tayar return 0; 7214102426fSTomer Tayar } 7224102426fSTomer Tayar 7235d24bcf1STomer Tayar static bool 7245d24bcf1STomer Tayar qed_mcp_can_force_load(u8 drv_role, 7255d24bcf1STomer Tayar u8 exist_drv_role, 7265d24bcf1STomer Tayar enum qed_override_force_load override_force_load) 727fe56b9e6SYuval Mintz { 7285d24bcf1STomer Tayar bool can_force_load = false; 7295d24bcf1STomer Tayar 7305d24bcf1STomer Tayar switch (override_force_load) { 7315d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_ALWAYS: 7325d24bcf1STomer Tayar can_force_load = true; 7335d24bcf1STomer Tayar break; 7345d24bcf1STomer Tayar case QED_OVERRIDE_FORCE_LOAD_NEVER: 7355d24bcf1STomer Tayar can_force_load = false; 7365d24bcf1STomer Tayar break; 7375d24bcf1STomer Tayar default: 7385d24bcf1STomer Tayar can_force_load = (drv_role == DRV_ROLE_OS && 7395d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_PREBOOT) || 7405d24bcf1STomer Tayar (drv_role == DRV_ROLE_KDUMP && 7415d24bcf1STomer Tayar exist_drv_role == DRV_ROLE_OS); 7425d24bcf1STomer Tayar break; 7435d24bcf1STomer Tayar } 7445d24bcf1STomer Tayar 7455d24bcf1STomer Tayar return can_force_load; 7465d24bcf1STomer Tayar } 7475d24bcf1STomer Tayar 7485d24bcf1STomer Tayar static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, 7495d24bcf1STomer Tayar struct qed_ptt *p_ptt) 7505d24bcf1STomer Tayar { 7515d24bcf1STomer Tayar u32 resp = 0, param = 0; 752fe56b9e6SYuval Mintz int rc; 753fe56b9e6SYuval Mintz 7545d24bcf1STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, 7555d24bcf1STomer Tayar &resp, ¶m); 7565d24bcf1STomer Tayar if (rc) 7575d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 7585d24bcf1STomer Tayar "Failed to send cancel load request, rc = %d\n", rc); 759fe56b9e6SYuval Mintz 760fe56b9e6SYuval Mintz return rc; 761fe56b9e6SYuval Mintz } 762fe56b9e6SYuval Mintz 7635d24bcf1STomer Tayar #define CONFIG_QEDE_BITMAP_IDX BIT(0) 7645d24bcf1STomer Tayar #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) 7655d24bcf1STomer Tayar #define CONFIG_QEDR_BITMAP_IDX BIT(2) 7665d24bcf1STomer Tayar #define CONFIG_QEDF_BITMAP_IDX BIT(4) 7675d24bcf1STomer Tayar #define CONFIG_QEDI_BITMAP_IDX BIT(5) 7685d24bcf1STomer Tayar #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) 7695529bad9STomer Tayar 7705d24bcf1STomer Tayar static u32 qed_get_config_bitmap(void) 7715d24bcf1STomer Tayar { 7725d24bcf1STomer Tayar u32 config_bitmap = 0x0; 7735d24bcf1STomer Tayar 7745d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QEDE)) 7755d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDE_BITMAP_IDX; 7765d24bcf1STomer Tayar 7775d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_SRIOV)) 7785d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; 7795d24bcf1STomer Tayar 7805d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_RDMA)) 7815d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDR_BITMAP_IDX; 7825d24bcf1STomer Tayar 7835d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_FCOE)) 7845d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDF_BITMAP_IDX; 7855d24bcf1STomer Tayar 7865d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_ISCSI)) 7875d24bcf1STomer Tayar config_bitmap |= CONFIG_QEDI_BITMAP_IDX; 7885d24bcf1STomer Tayar 7895d24bcf1STomer Tayar if (IS_ENABLED(CONFIG_QED_LL2)) 7905d24bcf1STomer Tayar config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; 7915d24bcf1STomer Tayar 7925d24bcf1STomer Tayar return config_bitmap; 7935d24bcf1STomer Tayar } 7945d24bcf1STomer Tayar 7955d24bcf1STomer Tayar struct qed_load_req_in_params { 7965d24bcf1STomer Tayar u8 hsi_ver; 7975d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 7985d24bcf1STomer Tayar #define QED_LOAD_REQ_HSI_VER_1 1 7995d24bcf1STomer Tayar u32 drv_ver_0; 8005d24bcf1STomer Tayar u32 drv_ver_1; 8015d24bcf1STomer Tayar u32 fw_ver; 8025d24bcf1STomer Tayar u8 drv_role; 8035d24bcf1STomer Tayar u8 timeout_val; 8045d24bcf1STomer Tayar u8 force_cmd; 8055d24bcf1STomer Tayar bool avoid_eng_reset; 8065d24bcf1STomer Tayar }; 8075d24bcf1STomer Tayar 8085d24bcf1STomer Tayar struct qed_load_req_out_params { 8095d24bcf1STomer Tayar u32 load_code; 8105d24bcf1STomer Tayar u32 exist_drv_ver_0; 8115d24bcf1STomer Tayar u32 exist_drv_ver_1; 8125d24bcf1STomer Tayar u32 exist_fw_ver; 8135d24bcf1STomer Tayar u8 exist_drv_role; 8145d24bcf1STomer Tayar u8 mfw_hsi_ver; 8155d24bcf1STomer Tayar bool drv_exists; 8165d24bcf1STomer Tayar }; 8175d24bcf1STomer Tayar 8185d24bcf1STomer Tayar static int 8195d24bcf1STomer Tayar __qed_mcp_load_req(struct qed_hwfn *p_hwfn, 8205d24bcf1STomer Tayar struct qed_ptt *p_ptt, 8215d24bcf1STomer Tayar struct qed_load_req_in_params *p_in_params, 8225d24bcf1STomer Tayar struct qed_load_req_out_params *p_out_params) 8235d24bcf1STomer Tayar { 8245d24bcf1STomer Tayar struct qed_mcp_mb_params mb_params; 8255d24bcf1STomer Tayar struct load_req_stc load_req; 8265d24bcf1STomer Tayar struct load_rsp_stc load_rsp; 8275d24bcf1STomer Tayar u32 hsi_ver; 8285d24bcf1STomer Tayar int rc; 8295d24bcf1STomer Tayar 8305d24bcf1STomer Tayar memset(&load_req, 0, sizeof(load_req)); 8315d24bcf1STomer Tayar load_req.drv_ver_0 = p_in_params->drv_ver_0; 8325d24bcf1STomer Tayar load_req.drv_ver_1 = p_in_params->drv_ver_1; 8335d24bcf1STomer Tayar load_req.fw_ver = p_in_params->fw_ver; 8345d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); 8355d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, 8365d24bcf1STomer Tayar p_in_params->timeout_val); 8375d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, 8385d24bcf1STomer Tayar p_in_params->force_cmd); 8395d24bcf1STomer Tayar QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, 8405d24bcf1STomer Tayar p_in_params->avoid_eng_reset); 8415d24bcf1STomer Tayar 8425d24bcf1STomer Tayar hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? 8435d24bcf1STomer Tayar DRV_ID_MCP_HSI_VER_CURRENT : 8445d24bcf1STomer Tayar (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); 8455d24bcf1STomer Tayar 8465d24bcf1STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 8475d24bcf1STomer Tayar mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; 8485d24bcf1STomer Tayar mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; 8495d24bcf1STomer Tayar mb_params.p_data_src = &load_req; 8505d24bcf1STomer Tayar mb_params.data_src_size = sizeof(load_req); 8515d24bcf1STomer Tayar mb_params.p_data_dst = &load_rsp; 8525d24bcf1STomer Tayar mb_params.data_dst_size = sizeof(load_rsp); 853b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 8545d24bcf1STomer Tayar 8555d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8565d24bcf1STomer Tayar "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", 8575d24bcf1STomer Tayar mb_params.param, 8585d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), 8595d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), 8605d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), 8615d24bcf1STomer Tayar QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); 8625d24bcf1STomer Tayar 8635d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { 8645d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8655d24bcf1STomer Tayar "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", 8665d24bcf1STomer Tayar load_req.drv_ver_0, 8675d24bcf1STomer Tayar load_req.drv_ver_1, 8685d24bcf1STomer Tayar load_req.fw_ver, 8695d24bcf1STomer Tayar load_req.misc0, 8705d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), 8715d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, 8725d24bcf1STomer Tayar LOAD_REQ_LOCK_TO), 8735d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), 8745d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); 8755d24bcf1STomer Tayar } 8765d24bcf1STomer Tayar 8775d24bcf1STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 8785d24bcf1STomer Tayar if (rc) { 8795d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); 8805d24bcf1STomer Tayar return rc; 8815d24bcf1STomer Tayar } 8825d24bcf1STomer Tayar 8835d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 8845d24bcf1STomer Tayar "Load Response: resp 0x%08x\n", mb_params.mcp_resp); 8855d24bcf1STomer Tayar p_out_params->load_code = mb_params.mcp_resp; 8865d24bcf1STomer Tayar 8875d24bcf1STomer Tayar if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 8885d24bcf1STomer Tayar p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 8895d24bcf1STomer Tayar DP_VERBOSE(p_hwfn, 8905d24bcf1STomer Tayar QED_MSG_SP, 8915d24bcf1STomer Tayar "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", 8925d24bcf1STomer Tayar load_rsp.drv_ver_0, 8935d24bcf1STomer Tayar load_rsp.drv_ver_1, 8945d24bcf1STomer Tayar load_rsp.fw_ver, 8955d24bcf1STomer Tayar load_rsp.misc0, 8965d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), 8975d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), 8985d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); 8995d24bcf1STomer Tayar 9005d24bcf1STomer Tayar p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; 9015d24bcf1STomer Tayar p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; 9025d24bcf1STomer Tayar p_out_params->exist_fw_ver = load_rsp.fw_ver; 9035d24bcf1STomer Tayar p_out_params->exist_drv_role = 9045d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); 9055d24bcf1STomer Tayar p_out_params->mfw_hsi_ver = 9065d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); 9075d24bcf1STomer Tayar p_out_params->drv_exists = 9085d24bcf1STomer Tayar QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & 9095d24bcf1STomer Tayar LOAD_RSP_FLAGS0_DRV_EXISTS; 9105d24bcf1STomer Tayar } 9115d24bcf1STomer Tayar 9125d24bcf1STomer Tayar return 0; 9135d24bcf1STomer Tayar } 9145d24bcf1STomer Tayar 9155d24bcf1STomer Tayar static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, 9165d24bcf1STomer Tayar enum qed_drv_role drv_role, 9175d24bcf1STomer Tayar u8 *p_mfw_drv_role) 9185d24bcf1STomer Tayar { 9195d24bcf1STomer Tayar switch (drv_role) { 9205d24bcf1STomer Tayar case QED_DRV_ROLE_OS: 9215d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_OS; 9225d24bcf1STomer Tayar break; 9235d24bcf1STomer Tayar case QED_DRV_ROLE_KDUMP: 9245d24bcf1STomer Tayar *p_mfw_drv_role = DRV_ROLE_KDUMP; 9255d24bcf1STomer Tayar break; 9265d24bcf1STomer Tayar default: 9275d24bcf1STomer Tayar DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); 9285d24bcf1STomer Tayar return -EINVAL; 9295d24bcf1STomer Tayar } 9305d24bcf1STomer Tayar 9315d24bcf1STomer Tayar return 0; 9325d24bcf1STomer Tayar } 9335d24bcf1STomer Tayar 9345d24bcf1STomer Tayar enum qed_load_req_force { 9355d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, 9365d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_PF, 9375d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 9385d24bcf1STomer Tayar }; 9395d24bcf1STomer Tayar 9405d24bcf1STomer Tayar static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, 9415d24bcf1STomer Tayar 9425d24bcf1STomer Tayar enum qed_load_req_force force_cmd, 9435d24bcf1STomer Tayar u8 *p_mfw_force_cmd) 9445d24bcf1STomer Tayar { 9455d24bcf1STomer Tayar switch (force_cmd) { 9465d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_NONE: 9475d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; 9485d24bcf1STomer Tayar break; 9495d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_PF: 9505d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; 9515d24bcf1STomer Tayar break; 9525d24bcf1STomer Tayar case QED_LOAD_REQ_FORCE_ALL: 9535d24bcf1STomer Tayar *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; 9545d24bcf1STomer Tayar break; 9555d24bcf1STomer Tayar } 9565d24bcf1STomer Tayar } 9575d24bcf1STomer Tayar 9585d24bcf1STomer Tayar int qed_mcp_load_req(struct qed_hwfn *p_hwfn, 9595d24bcf1STomer Tayar struct qed_ptt *p_ptt, 9605d24bcf1STomer Tayar struct qed_load_req_params *p_params) 9615d24bcf1STomer Tayar { 9625d24bcf1STomer Tayar struct qed_load_req_out_params out_params; 9635d24bcf1STomer Tayar struct qed_load_req_in_params in_params; 9645d24bcf1STomer Tayar u8 mfw_drv_role, mfw_force_cmd; 9655d24bcf1STomer Tayar int rc; 9665d24bcf1STomer Tayar 9675d24bcf1STomer Tayar memset(&in_params, 0, sizeof(in_params)); 9685d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; 9695d24bcf1STomer Tayar in_params.drv_ver_0 = QED_VERSION; 9705d24bcf1STomer Tayar in_params.drv_ver_1 = qed_get_config_bitmap(); 9715d24bcf1STomer Tayar in_params.fw_ver = STORM_FW_VERSION; 9725d24bcf1STomer Tayar rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); 9735d24bcf1STomer Tayar if (rc) 9745d24bcf1STomer Tayar return rc; 9755d24bcf1STomer Tayar 9765d24bcf1STomer Tayar in_params.drv_role = mfw_drv_role; 9775d24bcf1STomer Tayar in_params.timeout_val = p_params->timeout_val; 9785d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 9795d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); 9805d24bcf1STomer Tayar 9815d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 9825d24bcf1STomer Tayar in_params.avoid_eng_reset = p_params->avoid_eng_reset; 9835d24bcf1STomer Tayar 9845d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9855d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 9865d24bcf1STomer Tayar if (rc) 9875d24bcf1STomer Tayar return rc; 9885d24bcf1STomer Tayar 9895d24bcf1STomer Tayar /* First handle cases where another load request should/might be sent: 9905d24bcf1STomer Tayar * - MFW expects the old interface [HSI version = 1] 9915d24bcf1STomer Tayar * - MFW responds that a force load request is required 992fe56b9e6SYuval Mintz */ 9935d24bcf1STomer Tayar if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { 9945d24bcf1STomer Tayar DP_INFO(p_hwfn, 9955d24bcf1STomer Tayar "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); 9965d24bcf1STomer Tayar 9975d24bcf1STomer Tayar in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; 9985d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 9995d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); 10005d24bcf1STomer Tayar if (rc) 10015d24bcf1STomer Tayar return rc; 10025d24bcf1STomer Tayar } else if (out_params.load_code == 10035d24bcf1STomer Tayar FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { 10045d24bcf1STomer Tayar if (qed_mcp_can_force_load(in_params.drv_role, 10055d24bcf1STomer Tayar out_params.exist_drv_role, 10065d24bcf1STomer Tayar p_params->override_force_load)) { 10075d24bcf1STomer Tayar DP_INFO(p_hwfn, 10085d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", 10095d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10105d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10115d24bcf1STomer Tayar out_params.exist_drv_role, 10125d24bcf1STomer Tayar out_params.exist_fw_ver, 10135d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10145d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10155d24bcf1STomer Tayar 10165d24bcf1STomer Tayar qed_get_mfw_force_cmd(p_hwfn, 10175d24bcf1STomer Tayar QED_LOAD_REQ_FORCE_ALL, 10185d24bcf1STomer Tayar &mfw_force_cmd); 10195d24bcf1STomer Tayar 10205d24bcf1STomer Tayar in_params.force_cmd = mfw_force_cmd; 10215d24bcf1STomer Tayar memset(&out_params, 0, sizeof(out_params)); 10225d24bcf1STomer Tayar rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, 10235d24bcf1STomer Tayar &out_params); 10245d24bcf1STomer Tayar if (rc) 10255d24bcf1STomer Tayar return rc; 10265d24bcf1STomer Tayar } else { 10275d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10285d24bcf1STomer Tayar "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", 10295d24bcf1STomer Tayar in_params.drv_role, in_params.fw_ver, 10305d24bcf1STomer Tayar in_params.drv_ver_0, in_params.drv_ver_1, 10315d24bcf1STomer Tayar out_params.exist_drv_role, 10325d24bcf1STomer Tayar out_params.exist_fw_ver, 10335d24bcf1STomer Tayar out_params.exist_drv_ver_0, 10345d24bcf1STomer Tayar out_params.exist_drv_ver_1); 10355d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10365d24bcf1STomer Tayar "Avoid sending a force load request to prevent disruption of active PFs\n"); 10375d24bcf1STomer Tayar 10385d24bcf1STomer Tayar qed_mcp_cancel_load_req(p_hwfn, p_ptt); 1039fe56b9e6SYuval Mintz return -EBUSY; 1040fe56b9e6SYuval Mintz } 10415d24bcf1STomer Tayar } 10425d24bcf1STomer Tayar 10435d24bcf1STomer Tayar /* Now handle the other types of responses. 10445d24bcf1STomer Tayar * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not 10455d24bcf1STomer Tayar * expected here after the additional revised load requests were sent. 10465d24bcf1STomer Tayar */ 10475d24bcf1STomer Tayar switch (out_params.load_code) { 10485d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_ENGINE: 10495d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_PORT: 10505d24bcf1STomer Tayar case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10515d24bcf1STomer Tayar if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && 10525d24bcf1STomer Tayar out_params.drv_exists) { 10535d24bcf1STomer Tayar /* The role and fw/driver version match, but the PF is 10545d24bcf1STomer Tayar * already loaded and has not been unloaded gracefully. 10555d24bcf1STomer Tayar */ 10565d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10575d24bcf1STomer Tayar "PF is already loaded\n"); 10585d24bcf1STomer Tayar return -EINVAL; 10595d24bcf1STomer Tayar } 10605d24bcf1STomer Tayar break; 10615d24bcf1STomer Tayar default: 10625d24bcf1STomer Tayar DP_NOTICE(p_hwfn, 10635d24bcf1STomer Tayar "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", 10645d24bcf1STomer Tayar out_params.load_code); 10655d24bcf1STomer Tayar return -EBUSY; 10665d24bcf1STomer Tayar } 10675d24bcf1STomer Tayar 10685d24bcf1STomer Tayar p_params->load_code = out_params.load_code; 1069fe56b9e6SYuval Mintz 1070fe56b9e6SYuval Mintz return 0; 1071fe56b9e6SYuval Mintz } 1072fe56b9e6SYuval Mintz 10731226337aSTomer Tayar int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 10741226337aSTomer Tayar { 1075eaa50fc5STomer Tayar struct qed_mcp_mb_params mb_params; 1076eaa50fc5STomer Tayar u32 wol_param; 10771226337aSTomer Tayar 10781226337aSTomer Tayar switch (p_hwfn->cdev->wol_config) { 10791226337aSTomer Tayar case QED_OV_WOL_DISABLED: 10801226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 10811226337aSTomer Tayar break; 10821226337aSTomer Tayar case QED_OV_WOL_ENABLED: 10831226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 10841226337aSTomer Tayar break; 10851226337aSTomer Tayar default: 10861226337aSTomer Tayar DP_NOTICE(p_hwfn, 10871226337aSTomer Tayar "Unknown WoL configuration %02x\n", 10881226337aSTomer Tayar p_hwfn->cdev->wol_config); 10891226337aSTomer Tayar /* Fallthrough */ 10901226337aSTomer Tayar case QED_OV_WOL_DEFAULT: 10911226337aSTomer Tayar wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 10921226337aSTomer Tayar } 10931226337aSTomer Tayar 1094eaa50fc5STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 1095eaa50fc5STomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ; 1096eaa50fc5STomer Tayar mb_params.param = wol_param; 1097b310974eSTomer Tayar mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK; 1098eaa50fc5STomer Tayar 1099eaa50fc5STomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11001226337aSTomer Tayar } 11011226337aSTomer Tayar 11021226337aSTomer Tayar int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 11031226337aSTomer Tayar { 11041226337aSTomer Tayar struct qed_mcp_mb_params mb_params; 11051226337aSTomer Tayar struct mcp_mac wol_mac; 11061226337aSTomer Tayar 11071226337aSTomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 11081226337aSTomer Tayar mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; 11091226337aSTomer Tayar 11101226337aSTomer Tayar /* Set the primary MAC if WoL is enabled */ 11111226337aSTomer Tayar if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { 11121226337aSTomer Tayar u8 *p_mac = p_hwfn->cdev->wol_mac; 11131226337aSTomer Tayar 11141226337aSTomer Tayar memset(&wol_mac, 0, sizeof(wol_mac)); 11151226337aSTomer Tayar wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; 11161226337aSTomer Tayar wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | 11171226337aSTomer Tayar p_mac[4] << 8 | p_mac[5]; 11181226337aSTomer Tayar 11191226337aSTomer Tayar DP_VERBOSE(p_hwfn, 11201226337aSTomer Tayar (QED_MSG_SP | NETIF_MSG_IFDOWN), 11211226337aSTomer Tayar "Setting WoL MAC: %pM --> [%08x,%08x]\n", 11221226337aSTomer Tayar p_mac, wol_mac.mac_upper, wol_mac.mac_lower); 11231226337aSTomer Tayar 11241226337aSTomer Tayar mb_params.p_data_src = &wol_mac; 11251226337aSTomer Tayar mb_params.data_src_size = sizeof(wol_mac); 11261226337aSTomer Tayar } 11271226337aSTomer Tayar 11281226337aSTomer Tayar return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11291226337aSTomer Tayar } 11301226337aSTomer Tayar 11310b55e27dSYuval Mintz static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, 11320b55e27dSYuval Mintz struct qed_ptt *p_ptt) 11330b55e27dSYuval Mintz { 11340b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11350b55e27dSYuval Mintz PUBLIC_PATH); 11360b55e27dSYuval Mintz u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 11370b55e27dSYuval Mintz u32 path_addr = SECTION_ADDR(mfw_path_offsize, 11380b55e27dSYuval Mintz QED_PATH_ID(p_hwfn)); 11390b55e27dSYuval Mintz u32 disabled_vfs[VF_MAX_STATIC / 32]; 11400b55e27dSYuval Mintz int i; 11410b55e27dSYuval Mintz 11420b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, 11430b55e27dSYuval Mintz QED_MSG_SP, 11440b55e27dSYuval Mintz "Reading Disabled VF information from [offset %08x], path_addr %08x\n", 11450b55e27dSYuval Mintz mfw_path_offsize, path_addr); 11460b55e27dSYuval Mintz 11470b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) { 11480b55e27dSYuval Mintz disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, 11490b55e27dSYuval Mintz path_addr + 11500b55e27dSYuval Mintz offsetof(struct public_path, 11510b55e27dSYuval Mintz mcp_vf_disabled) + 11520b55e27dSYuval Mintz sizeof(u32) * i); 11530b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11540b55e27dSYuval Mintz "FLR-ed VFs [%08x,...,%08x] - %08x\n", 11550b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); 11560b55e27dSYuval Mintz } 11570b55e27dSYuval Mintz 11580b55e27dSYuval Mintz if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) 11590b55e27dSYuval Mintz qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); 11600b55e27dSYuval Mintz } 11610b55e27dSYuval Mintz 11620b55e27dSYuval Mintz int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, 11630b55e27dSYuval Mintz struct qed_ptt *p_ptt, u32 *vfs_to_ack) 11640b55e27dSYuval Mintz { 11650b55e27dSYuval Mintz u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 11660b55e27dSYuval Mintz PUBLIC_FUNC); 11670b55e27dSYuval Mintz u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); 11680b55e27dSYuval Mintz u32 func_addr = SECTION_ADDR(mfw_func_offsize, 11690b55e27dSYuval Mintz MCP_PF_ID(p_hwfn)); 11700b55e27dSYuval Mintz struct qed_mcp_mb_params mb_params; 11710b55e27dSYuval Mintz int rc; 11720b55e27dSYuval Mintz int i; 11730b55e27dSYuval Mintz 11740b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11750b55e27dSYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), 11760b55e27dSYuval Mintz "Acking VFs [%08x,...,%08x] - %08x\n", 11770b55e27dSYuval Mintz i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); 11780b55e27dSYuval Mintz 11790b55e27dSYuval Mintz memset(&mb_params, 0, sizeof(mb_params)); 11800b55e27dSYuval Mintz mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; 11812f67af8cSTomer Tayar mb_params.p_data_src = vfs_to_ack; 11822f67af8cSTomer Tayar mb_params.data_src_size = VF_MAX_STATIC / 8; 11830b55e27dSYuval Mintz rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 11840b55e27dSYuval Mintz if (rc) { 11850b55e27dSYuval Mintz DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); 11860b55e27dSYuval Mintz return -EBUSY; 11870b55e27dSYuval Mintz } 11880b55e27dSYuval Mintz 11890b55e27dSYuval Mintz /* Clear the ACK bits */ 11900b55e27dSYuval Mintz for (i = 0; i < (VF_MAX_STATIC / 32); i++) 11910b55e27dSYuval Mintz qed_wr(p_hwfn, p_ptt, 11920b55e27dSYuval Mintz func_addr + 11930b55e27dSYuval Mintz offsetof(struct public_func, drv_ack_vf_disabled) + 11940b55e27dSYuval Mintz i * sizeof(u32), 0); 11950b55e27dSYuval Mintz 11960b55e27dSYuval Mintz return rc; 11970b55e27dSYuval Mintz } 11980b55e27dSYuval Mintz 1199334c03b5SZvi Nachmani static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, 1200334c03b5SZvi Nachmani struct qed_ptt *p_ptt) 1201334c03b5SZvi Nachmani { 1202334c03b5SZvi Nachmani u32 transceiver_state; 1203334c03b5SZvi Nachmani 1204334c03b5SZvi Nachmani transceiver_state = qed_rd(p_hwfn, p_ptt, 1205334c03b5SZvi Nachmani p_hwfn->mcp_info->port_addr + 1206334c03b5SZvi Nachmani offsetof(struct public_port, 1207334c03b5SZvi Nachmani transceiver_data)); 1208334c03b5SZvi Nachmani 1209334c03b5SZvi Nachmani DP_VERBOSE(p_hwfn, 1210334c03b5SZvi Nachmani (NETIF_MSG_HW | QED_MSG_SP), 1211334c03b5SZvi Nachmani "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", 1212334c03b5SZvi Nachmani transceiver_state, 1213334c03b5SZvi Nachmani (u32)(p_hwfn->mcp_info->port_addr + 12141a635e48SYuval Mintz offsetof(struct public_port, transceiver_data))); 1215334c03b5SZvi Nachmani 1216334c03b5SZvi Nachmani transceiver_state = GET_FIELD(transceiver_state, 1217351a4dedSYuval Mintz ETH_TRANSCEIVER_STATE); 1218334c03b5SZvi Nachmani 1219351a4dedSYuval Mintz if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1220334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is present.\n"); 1221334c03b5SZvi Nachmani else 1222334c03b5SZvi Nachmani DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); 1223334c03b5SZvi Nachmani } 1224334c03b5SZvi Nachmani 1225645874e5SSudarsana Reddy Kalluru static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn, 1226645874e5SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1227645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_state *p_link) 1228645874e5SSudarsana Reddy Kalluru { 1229645874e5SSudarsana Reddy Kalluru u32 eee_status, val; 1230645874e5SSudarsana Reddy Kalluru 1231645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps = 0; 1232645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps = 0; 1233645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, 1234645874e5SSudarsana Reddy Kalluru p_ptt, 1235645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 1236645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 1237645874e5SSudarsana Reddy Kalluru p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT); 1238645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET; 1239645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1240645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_1G_ADV; 1241645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1242645874e5SSudarsana Reddy Kalluru p_link->eee_adv_caps |= QED_EEE_10G_ADV; 1243645874e5SSudarsana Reddy Kalluru val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET; 1244645874e5SSudarsana Reddy Kalluru if (val & EEE_1G_ADV) 1245645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV; 1246645874e5SSudarsana Reddy Kalluru if (val & EEE_10G_ADV) 1247645874e5SSudarsana Reddy Kalluru p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV; 1248645874e5SSudarsana Reddy Kalluru } 1249645874e5SSudarsana Reddy Kalluru 1250e40a826aSSudarsana Reddy Kalluru static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, 1251e40a826aSSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 1252e40a826aSSudarsana Reddy Kalluru struct public_func *p_data, int pfid) 1253e40a826aSSudarsana Reddy Kalluru { 1254e40a826aSSudarsana Reddy Kalluru u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 1255e40a826aSSudarsana Reddy Kalluru PUBLIC_FUNC); 1256e40a826aSSudarsana Reddy Kalluru u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); 1257e40a826aSSudarsana Reddy Kalluru u32 func_addr; 1258e40a826aSSudarsana Reddy Kalluru u32 i, size; 1259e40a826aSSudarsana Reddy Kalluru 1260e40a826aSSudarsana Reddy Kalluru func_addr = SECTION_ADDR(mfw_path_offsize, pfid); 1261e40a826aSSudarsana Reddy Kalluru memset(p_data, 0, sizeof(*p_data)); 1262e40a826aSSudarsana Reddy Kalluru 1263e40a826aSSudarsana Reddy Kalluru size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); 1264e40a826aSSudarsana Reddy Kalluru for (i = 0; i < size / sizeof(u32); i++) 1265e40a826aSSudarsana Reddy Kalluru ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, 1266e40a826aSSudarsana Reddy Kalluru func_addr + (i << 2)); 1267e40a826aSSudarsana Reddy Kalluru return size; 1268e40a826aSSudarsana Reddy Kalluru } 1269e40a826aSSudarsana Reddy Kalluru 1270e40a826aSSudarsana Reddy Kalluru static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, 1271e40a826aSSudarsana Reddy Kalluru struct public_func *p_shmem_info) 1272e40a826aSSudarsana Reddy Kalluru { 1273e40a826aSSudarsana Reddy Kalluru struct qed_mcp_function_info *p_info; 1274e40a826aSSudarsana Reddy Kalluru 1275e40a826aSSudarsana Reddy Kalluru p_info = &p_hwfn->mcp_info->func_info; 1276e40a826aSSudarsana Reddy Kalluru 1277e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config, 1278e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MIN_BW); 1279e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { 1280e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1281e40a826aSSudarsana Reddy Kalluru "bandwidth minimum out of bounds [%02x]. Set to 1\n", 1282e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min); 1283e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_min = 1; 1284e40a826aSSudarsana Reddy Kalluru } 1285e40a826aSSudarsana Reddy Kalluru 1286e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config, 1287e40a826aSSudarsana Reddy Kalluru FUNC_MF_CFG_MAX_BW); 1288e40a826aSSudarsana Reddy Kalluru if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { 1289e40a826aSSudarsana Reddy Kalluru DP_INFO(p_hwfn, 1290e40a826aSSudarsana Reddy Kalluru "bandwidth maximum out of bounds [%02x]. Set to 100\n", 1291e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max); 1292e40a826aSSudarsana Reddy Kalluru p_info->bandwidth_max = 100; 1293e40a826aSSudarsana Reddy Kalluru } 1294e40a826aSSudarsana Reddy Kalluru } 1295e40a826aSSudarsana Reddy Kalluru 1296cc875c2eSYuval Mintz static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, 12971a635e48SYuval Mintz struct qed_ptt *p_ptt, bool b_reset) 1298cc875c2eSYuval Mintz { 1299cc875c2eSYuval Mintz struct qed_mcp_link_state *p_link; 1300a64b02d5SManish Chopra u8 max_bw, min_bw; 1301cc875c2eSYuval Mintz u32 status = 0; 1302cc875c2eSYuval Mintz 130365ed2ffdSMintz, Yuval /* Prevent SW/attentions from doing this at the same time */ 130465ed2ffdSMintz, Yuval spin_lock_bh(&p_hwfn->mcp_info->link_lock); 130565ed2ffdSMintz, Yuval 1306cc875c2eSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 1307cc875c2eSYuval Mintz memset(p_link, 0, sizeof(*p_link)); 1308cc875c2eSYuval Mintz if (!b_reset) { 1309cc875c2eSYuval Mintz status = qed_rd(p_hwfn, p_ptt, 1310cc875c2eSYuval Mintz p_hwfn->mcp_info->port_addr + 1311cc875c2eSYuval Mintz offsetof(struct public_port, link_status)); 1312cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), 1313cc875c2eSYuval Mintz "Received link update [0x%08x] from mfw [Addr 0x%x]\n", 1314cc875c2eSYuval Mintz status, 1315cc875c2eSYuval Mintz (u32)(p_hwfn->mcp_info->port_addr + 13161a635e48SYuval Mintz offsetof(struct public_port, link_status))); 1317cc875c2eSYuval Mintz } else { 1318cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1319cc875c2eSYuval Mintz "Resetting link indications\n"); 132065ed2ffdSMintz, Yuval goto out; 1321cc875c2eSYuval Mintz } 1322cc875c2eSYuval Mintz 1323e40a826aSSudarsana Reddy Kalluru if (p_hwfn->b_drv_link_init) { 1324e40a826aSSudarsana Reddy Kalluru /* Link indication with modern MFW arrives as per-PF 1325e40a826aSSudarsana Reddy Kalluru * indication. 1326e40a826aSSudarsana Reddy Kalluru */ 1327e40a826aSSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & 1328e40a826aSSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_VLINK) { 1329e40a826aSSudarsana Reddy Kalluru struct public_func shmem_info; 1330e40a826aSSudarsana Reddy Kalluru 1331e40a826aSSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, 1332e40a826aSSudarsana Reddy Kalluru MCP_PF_ID(p_hwfn)); 1333e40a826aSSudarsana Reddy Kalluru p_link->link_up = !!(shmem_info.status & 1334e40a826aSSudarsana Reddy Kalluru FUNC_STATUS_VIRTUAL_LINK_UP); 1335e40a826aSSudarsana Reddy Kalluru qed_read_pf_bandwidth(p_hwfn, &shmem_info); 1336e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1337e40a826aSSudarsana Reddy Kalluru "Virtual link_up = %d\n", p_link->link_up); 1338e40a826aSSudarsana Reddy Kalluru } else { 1339cc875c2eSYuval Mintz p_link->link_up = !!(status & LINK_STATUS_LINK_UP); 1340e40a826aSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1341e40a826aSSudarsana Reddy Kalluru "Physical link_up = %d\n", p_link->link_up); 1342e40a826aSSudarsana Reddy Kalluru } 1343e40a826aSSudarsana Reddy Kalluru } else { 1344fc916ff2SSudarsana Reddy Kalluru p_link->link_up = false; 1345e40a826aSSudarsana Reddy Kalluru } 1346cc875c2eSYuval Mintz 1347cc875c2eSYuval Mintz p_link->full_duplex = true; 1348cc875c2eSYuval Mintz switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { 1349cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_100G: 1350cc875c2eSYuval Mintz p_link->speed = 100000; 1351cc875c2eSYuval Mintz break; 1352cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_50G: 1353cc875c2eSYuval Mintz p_link->speed = 50000; 1354cc875c2eSYuval Mintz break; 1355cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_40G: 1356cc875c2eSYuval Mintz p_link->speed = 40000; 1357cc875c2eSYuval Mintz break; 1358cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_25G: 1359cc875c2eSYuval Mintz p_link->speed = 25000; 1360cc875c2eSYuval Mintz break; 1361cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_20G: 1362cc875c2eSYuval Mintz p_link->speed = 20000; 1363cc875c2eSYuval Mintz break; 1364cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_10G: 1365cc875c2eSYuval Mintz p_link->speed = 10000; 1366cc875c2eSYuval Mintz break; 1367cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: 1368cc875c2eSYuval Mintz p_link->full_duplex = false; 1369cc875c2eSYuval Mintz /* Fall-through */ 1370cc875c2eSYuval Mintz case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: 1371cc875c2eSYuval Mintz p_link->speed = 1000; 1372cc875c2eSYuval Mintz break; 1373cc875c2eSYuval Mintz default: 1374cc875c2eSYuval Mintz p_link->speed = 0; 137558874c7bSSudarsana Reddy Kalluru p_link->link_up = 0; 1376cc875c2eSYuval Mintz } 1377cc875c2eSYuval Mintz 13784b01e519SManish Chopra if (p_link->link_up && p_link->speed) 13794b01e519SManish Chopra p_link->line_speed = p_link->speed; 13804b01e519SManish Chopra else 13814b01e519SManish Chopra p_link->line_speed = 0; 13824b01e519SManish Chopra 13834b01e519SManish Chopra max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; 1384a64b02d5SManish Chopra min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; 13854b01e519SManish Chopra 1386a64b02d5SManish Chopra /* Max bandwidth configuration */ 13874b01e519SManish Chopra __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); 1388cc875c2eSYuval Mintz 1389a64b02d5SManish Chopra /* Min bandwidth configuration */ 1390a64b02d5SManish Chopra __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); 13916f437d43SMintz, Yuval qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, 13926f437d43SMintz, Yuval p_link->min_pf_rate); 1393a64b02d5SManish Chopra 1394cc875c2eSYuval Mintz p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); 1395cc875c2eSYuval Mintz p_link->an_complete = !!(status & 1396cc875c2eSYuval Mintz LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); 1397cc875c2eSYuval Mintz p_link->parallel_detection = !!(status & 1398cc875c2eSYuval Mintz LINK_STATUS_PARALLEL_DETECTION_USED); 1399cc875c2eSYuval Mintz p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); 1400cc875c2eSYuval Mintz 1401cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1402cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? 1403cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD : 0; 1404cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1405cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? 1406cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD : 0; 1407cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1408cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? 1409cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G : 0; 1410cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1411cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? 1412cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_20G : 0; 1413cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1414054c67d1SSudarsana Reddy Kalluru (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? 1415054c67d1SSudarsana Reddy Kalluru QED_LINK_PARTNER_SPEED_25G : 0; 1416054c67d1SSudarsana Reddy Kalluru p_link->partner_adv_speed |= 1417cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? 1418cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G : 0; 1419cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1420cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? 1421cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G : 0; 1422cc875c2eSYuval Mintz p_link->partner_adv_speed |= 1423cc875c2eSYuval Mintz (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? 1424cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G : 0; 1425cc875c2eSYuval Mintz 1426cc875c2eSYuval Mintz p_link->partner_tx_flow_ctrl_en = 1427cc875c2eSYuval Mintz !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); 1428cc875c2eSYuval Mintz p_link->partner_rx_flow_ctrl_en = 1429cc875c2eSYuval Mintz !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 1430cc875c2eSYuval Mintz 1431cc875c2eSYuval Mintz switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { 1432cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: 1433cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; 1434cc875c2eSYuval Mintz break; 1435cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: 1436cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; 1437cc875c2eSYuval Mintz break; 1438cc875c2eSYuval Mintz case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: 1439cc875c2eSYuval Mintz p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; 1440cc875c2eSYuval Mintz break; 1441cc875c2eSYuval Mintz default: 1442cc875c2eSYuval Mintz p_link->partner_adv_pause = 0; 1443cc875c2eSYuval Mintz } 1444cc875c2eSYuval Mintz 1445cc875c2eSYuval Mintz p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); 1446cc875c2eSYuval Mintz 1447645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) 1448645874e5SSudarsana Reddy Kalluru qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link); 1449645874e5SSudarsana Reddy Kalluru 1450706d0891SRahul Verma qed_link_update(p_hwfn, p_ptt); 145165ed2ffdSMintz, Yuval out: 145265ed2ffdSMintz, Yuval spin_unlock_bh(&p_hwfn->mcp_info->link_lock); 1453cc875c2eSYuval Mintz } 1454cc875c2eSYuval Mintz 1455351a4dedSYuval Mintz int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) 1456cc875c2eSYuval Mintz { 1457cc875c2eSYuval Mintz struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; 14585529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 14592f67af8cSTomer Tayar struct eth_phy_cfg phy_cfg; 1460cc875c2eSYuval Mintz int rc = 0; 14615529bad9STomer Tayar u32 cmd; 1462cc875c2eSYuval Mintz 1463cc875c2eSYuval Mintz /* Set the shmem configuration according to params */ 14642f67af8cSTomer Tayar memset(&phy_cfg, 0, sizeof(phy_cfg)); 1465cc875c2eSYuval Mintz cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; 1466cc875c2eSYuval Mintz if (!params->speed.autoneg) 14672f67af8cSTomer Tayar phy_cfg.speed = params->speed.forced_speed; 14682f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; 14692f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; 14702f67af8cSTomer Tayar phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; 14712f67af8cSTomer Tayar phy_cfg.adv_speed = params->speed.advertised_speeds; 14722f67af8cSTomer Tayar phy_cfg.loopback_mode = params->loopback_mode; 14734ad95a93SSudarsana Reddy Kalluru 14744ad95a93SSudarsana Reddy Kalluru /* There are MFWs that share this capability regardless of whether 14754ad95a93SSudarsana Reddy Kalluru * this is feasible or not. And given that at the very least adv_caps 14764ad95a93SSudarsana Reddy Kalluru * would be set internally by qed, we want to make sure LFA would 14774ad95a93SSudarsana Reddy Kalluru * still work. 14784ad95a93SSudarsana Reddy Kalluru */ 14794ad95a93SSudarsana Reddy Kalluru if ((p_hwfn->mcp_info->capabilities & 14804ad95a93SSudarsana Reddy Kalluru FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) { 1481645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED; 1482645874e5SSudarsana Reddy Kalluru if (params->eee.tx_lpi_enable) 1483645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_TX_LPI; 1484645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_1G_ADV) 1485645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G; 1486645874e5SSudarsana Reddy Kalluru if (params->eee.adv_caps & QED_EEE_10G_ADV) 1487645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G; 1488645874e5SSudarsana Reddy Kalluru phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer << 1489645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_OFFSET) & 1490645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_MASK; 1491645874e5SSudarsana Reddy Kalluru } 1492cc875c2eSYuval Mintz 1493fc916ff2SSudarsana Reddy Kalluru p_hwfn->b_drv_link_init = b_up; 1494fc916ff2SSudarsana Reddy Kalluru 1495cc875c2eSYuval Mintz if (b_up) { 1496cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1497cc875c2eSYuval Mintz "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", 14982f67af8cSTomer Tayar phy_cfg.speed, 14992f67af8cSTomer Tayar phy_cfg.pause, 15002f67af8cSTomer Tayar phy_cfg.adv_speed, 15012f67af8cSTomer Tayar phy_cfg.loopback_mode, 15022f67af8cSTomer Tayar phy_cfg.feature_config_flags); 1503cc875c2eSYuval Mintz } else { 1504cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1505cc875c2eSYuval Mintz "Resetting link\n"); 1506cc875c2eSYuval Mintz } 1507cc875c2eSYuval Mintz 15085529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 15095529bad9STomer Tayar mb_params.cmd = cmd; 15102f67af8cSTomer Tayar mb_params.p_data_src = &phy_cfg; 15112f67af8cSTomer Tayar mb_params.data_src_size = sizeof(phy_cfg); 15125529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 1513cc875c2eSYuval Mintz 1514cc875c2eSYuval Mintz /* if mcp fails to respond we must abort */ 1515cc875c2eSYuval Mintz if (rc) { 1516cc875c2eSYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 1517cc875c2eSYuval Mintz return rc; 1518cc875c2eSYuval Mintz } 1519cc875c2eSYuval Mintz 152065ed2ffdSMintz, Yuval /* Mimic link-change attention, done for several reasons: 152165ed2ffdSMintz, Yuval * - On reset, there's no guarantee MFW would trigger 152265ed2ffdSMintz, Yuval * an attention. 152365ed2ffdSMintz, Yuval * - On initialization, older MFWs might not indicate link change 152465ed2ffdSMintz, Yuval * during LFA, so we'll never get an UP indication. 152565ed2ffdSMintz, Yuval */ 152665ed2ffdSMintz, Yuval qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); 1527cc875c2eSYuval Mintz 1528cc875c2eSYuval Mintz return 0; 1529cc875c2eSYuval Mintz } 1530cc875c2eSYuval Mintz 15316c754246SSudarsana Reddy Kalluru static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, 15326c754246SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 15336c754246SSudarsana Reddy Kalluru enum MFW_DRV_MSG_TYPE type) 15346c754246SSudarsana Reddy Kalluru { 15356c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type stats_type; 15366c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats stats; 15376c754246SSudarsana Reddy Kalluru struct qed_mcp_mb_params mb_params; 15386c754246SSudarsana Reddy Kalluru u32 hsi_param; 15396c754246SSudarsana Reddy Kalluru 15406c754246SSudarsana Reddy Kalluru switch (type) { 15416c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 15426c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_LAN_STATS; 15436c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; 15446c754246SSudarsana Reddy Kalluru break; 15456c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 15466c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_FCOE_STATS; 15476c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; 15486c754246SSudarsana Reddy Kalluru break; 15496c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 15506c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_ISCSI_STATS; 15516c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; 15526c754246SSudarsana Reddy Kalluru break; 15536c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 15546c754246SSudarsana Reddy Kalluru stats_type = QED_MCP_RDMA_STATS; 15556c754246SSudarsana Reddy Kalluru hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; 15566c754246SSudarsana Reddy Kalluru break; 15576c754246SSudarsana Reddy Kalluru default: 15586c754246SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); 15596c754246SSudarsana Reddy Kalluru return; 15606c754246SSudarsana Reddy Kalluru } 15616c754246SSudarsana Reddy Kalluru 15626c754246SSudarsana Reddy Kalluru qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); 15636c754246SSudarsana Reddy Kalluru 15646c754246SSudarsana Reddy Kalluru memset(&mb_params, 0, sizeof(mb_params)); 15656c754246SSudarsana Reddy Kalluru mb_params.cmd = DRV_MSG_CODE_GET_STATS; 15666c754246SSudarsana Reddy Kalluru mb_params.param = hsi_param; 15672f67af8cSTomer Tayar mb_params.p_data_src = &stats; 15682f67af8cSTomer Tayar mb_params.data_src_size = sizeof(stats); 15696c754246SSudarsana Reddy Kalluru qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 15706c754246SSudarsana Reddy Kalluru } 15716c754246SSudarsana Reddy Kalluru 15721a635e48SYuval Mintz static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15734b01e519SManish Chopra { 15744b01e519SManish Chopra struct qed_mcp_function_info *p_info; 15754b01e519SManish Chopra struct public_func shmem_info; 15764b01e519SManish Chopra u32 resp = 0, param = 0; 15774b01e519SManish Chopra 15781a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 15794b01e519SManish Chopra 15804b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 15814b01e519SManish Chopra 15824b01e519SManish Chopra p_info = &p_hwfn->mcp_info->func_info; 15834b01e519SManish Chopra 1584a64b02d5SManish Chopra qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); 15854b01e519SManish Chopra qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); 15864b01e519SManish Chopra 15874b01e519SManish Chopra /* Acknowledge the MFW */ 15884b01e519SManish Chopra qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, 15894b01e519SManish Chopra ¶m); 15904b01e519SManish Chopra } 15914b01e519SManish Chopra 15922a351fd9SMintz, Yuval static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 15932a351fd9SMintz, Yuval { 15942a351fd9SMintz, Yuval struct public_func shmem_info; 15952a351fd9SMintz, Yuval u32 resp = 0, param = 0; 15962a351fd9SMintz, Yuval 15972a351fd9SMintz, Yuval qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 15982a351fd9SMintz, Yuval 15992a351fd9SMintz, Yuval p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & 16002a351fd9SMintz, Yuval FUNC_MF_CFG_OV_STAG_MASK; 16012a351fd9SMintz, Yuval p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; 16027e3e375cSSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) { 16037e3e375cSSudarsana Reddy Kalluru if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) { 16047e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 16057e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16067e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1); 16077e3e375cSSudarsana Reddy Kalluru 16087e3e375cSSudarsana Reddy Kalluru /* Configure DB to add external vlan to EDPM packets */ 16097e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 16107e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 16117e3e375cSSudarsana Reddy Kalluru p_hwfn->hw_info.ovlan); 16127e3e375cSSudarsana Reddy Kalluru } else { 16137e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0); 16147e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0); 16157e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0); 16167e3e375cSSudarsana Reddy Kalluru qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0); 16177e3e375cSSudarsana Reddy Kalluru } 16187e3e375cSSudarsana Reddy Kalluru 16192a351fd9SMintz, Yuval qed_sp_pf_update_stag(p_hwfn); 16202a351fd9SMintz, Yuval } 16212a351fd9SMintz, Yuval 16227e3e375cSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n", 16237e3e375cSSudarsana Reddy Kalluru p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode); 16247e3e375cSSudarsana Reddy Kalluru 16252a351fd9SMintz, Yuval /* Acknowledge the MFW */ 16262a351fd9SMintz, Yuval qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, 16272a351fd9SMintz, Yuval &resp, ¶m); 16282a351fd9SMintz, Yuval } 16292a351fd9SMintz, Yuval 1630cac6f691SSudarsana Reddy Kalluru void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1631cac6f691SSudarsana Reddy Kalluru { 1632cac6f691SSudarsana Reddy Kalluru struct public_func shmem_info; 1633cac6f691SSudarsana Reddy Kalluru u32 port_cfg, val; 1634cac6f691SSudarsana Reddy Kalluru 1635cac6f691SSudarsana Reddy Kalluru if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) 1636cac6f691SSudarsana Reddy Kalluru return; 1637cac6f691SSudarsana Reddy Kalluru 1638cac6f691SSudarsana Reddy Kalluru memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info)); 1639cac6f691SSudarsana Reddy Kalluru port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 1640cac6f691SSudarsana Reddy Kalluru offsetof(struct public_port, oem_cfg_port)); 1641cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >> 1642cac6f691SSudarsana Reddy Kalluru OEM_CFG_CHANNEL_TYPE_OFFSET; 1643cac6f691SSudarsana Reddy Kalluru if (val != OEM_CFG_CHANNEL_TYPE_STAGGED) 1644ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1645ec036eb9SSudarsana Reddy Kalluru "Incorrect UFP Channel type %d port_id 0x%02x\n", 1646ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1647cac6f691SSudarsana Reddy Kalluru 1648cac6f691SSudarsana Reddy Kalluru val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET; 1649cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_SCHED_TYPE_ETS) { 1650cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS; 1651cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) { 1652cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW; 1653cac6f691SSudarsana Reddy Kalluru } else { 1654cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN; 1655ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1656ec036eb9SSudarsana Reddy Kalluru "Unknown UFP scheduling mode %d port_id 0x%02x\n", 1657ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1658cac6f691SSudarsana Reddy Kalluru } 1659cac6f691SSudarsana Reddy Kalluru 1660cac6f691SSudarsana Reddy Kalluru qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 1661b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >> 1662b5fabb08SSudarsana Reddy Kalluru OEM_CFG_FUNC_TC_OFFSET; 1663cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.tc = (u8)val; 1664b5fabb08SSudarsana Reddy Kalluru val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >> 1665cac6f691SSudarsana Reddy Kalluru OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET; 1666cac6f691SSudarsana Reddy Kalluru if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) { 1667cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC; 1668cac6f691SSudarsana Reddy Kalluru } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) { 1669cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS; 1670cac6f691SSudarsana Reddy Kalluru } else { 1671cac6f691SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN; 1672ec036eb9SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1673ec036eb9SSudarsana Reddy Kalluru "Unknown Host priority control %d port_id 0x%02x\n", 1674ec036eb9SSudarsana Reddy Kalluru val, MFW_PORT(p_hwfn)); 1675cac6f691SSudarsana Reddy Kalluru } 1676cac6f691SSudarsana Reddy Kalluru 1677cac6f691SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 1678ec036eb9SSudarsana Reddy Kalluru "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n", 1679ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc, 1680ec036eb9SSudarsana Reddy Kalluru p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn)); 1681cac6f691SSudarsana Reddy Kalluru } 1682cac6f691SSudarsana Reddy Kalluru 1683cac6f691SSudarsana Reddy Kalluru static int 1684cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1685cac6f691SSudarsana Reddy Kalluru { 1686cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 1687cac6f691SSudarsana Reddy Kalluru 1688cac6f691SSudarsana Reddy Kalluru if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) { 1689cac6f691SSudarsana Reddy Kalluru p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc; 1690c4259ddaSDenis Bolotin qed_hw_info_set_offload_tc(&p_hwfn->hw_info, 1691c4259ddaSDenis Bolotin p_hwfn->ufp_info.tc); 1692cac6f691SSudarsana Reddy Kalluru 1693cac6f691SSudarsana Reddy Kalluru qed_qm_reconf(p_hwfn, p_ptt); 1694cac6f691SSudarsana Reddy Kalluru } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) { 1695cac6f691SSudarsana Reddy Kalluru /* Merge UFP TC with the dcbx TC data */ 1696cac6f691SSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 1697cac6f691SSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 1698cac6f691SSudarsana Reddy Kalluru } else { 1699cac6f691SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n"); 1700cac6f691SSudarsana Reddy Kalluru return -EINVAL; 1701cac6f691SSudarsana Reddy Kalluru } 1702cac6f691SSudarsana Reddy Kalluru 1703cac6f691SSudarsana Reddy Kalluru /* update storm FW with negotiation results */ 1704cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_ufp(p_hwfn); 1705cac6f691SSudarsana Reddy Kalluru 1706cac6f691SSudarsana Reddy Kalluru /* update stag pcp value */ 1707cac6f691SSudarsana Reddy Kalluru qed_sp_pf_update_stag(p_hwfn); 1708cac6f691SSudarsana Reddy Kalluru 1709cac6f691SSudarsana Reddy Kalluru return 0; 1710cac6f691SSudarsana Reddy Kalluru } 1711cac6f691SSudarsana Reddy Kalluru 1712cc875c2eSYuval Mintz int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, 1713cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1714cc875c2eSYuval Mintz { 1715cc875c2eSYuval Mintz struct qed_mcp_info *info = p_hwfn->mcp_info; 1716cc875c2eSYuval Mintz int rc = 0; 1717cc875c2eSYuval Mintz bool found = false; 1718cc875c2eSYuval Mintz u16 i; 1719cc875c2eSYuval Mintz 1720cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); 1721cc875c2eSYuval Mintz 1722cc875c2eSYuval Mintz /* Read Messages from MFW */ 1723cc875c2eSYuval Mintz qed_mcp_read_mb(p_hwfn, p_ptt); 1724cc875c2eSYuval Mintz 1725cc875c2eSYuval Mintz /* Compare current messages to old ones */ 1726cc875c2eSYuval Mintz for (i = 0; i < info->mfw_mb_length; i++) { 1727cc875c2eSYuval Mintz if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) 1728cc875c2eSYuval Mintz continue; 1729cc875c2eSYuval Mintz 1730cc875c2eSYuval Mintz found = true; 1731cc875c2eSYuval Mintz 1732cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1733cc875c2eSYuval Mintz "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", 1734cc875c2eSYuval Mintz i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); 1735cc875c2eSYuval Mintz 1736cc875c2eSYuval Mintz switch (i) { 1737cc875c2eSYuval Mintz case MFW_DRV_MSG_LINK_CHANGE: 1738cc875c2eSYuval Mintz qed_mcp_handle_link_change(p_hwfn, p_ptt, false); 1739cc875c2eSYuval Mintz break; 17400b55e27dSYuval Mintz case MFW_DRV_MSG_VF_DISABLED: 17410b55e27dSYuval Mintz qed_mcp_handle_vf_flr(p_hwfn, p_ptt); 17420b55e27dSYuval Mintz break; 174339651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_LLDP_DATA_UPDATED: 174439651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 174539651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_LLDP_MIB); 174639651abdSSudarsana Reddy Kalluru break; 174739651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: 174839651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 174939651abdSSudarsana Reddy Kalluru QED_DCBX_REMOTE_MIB); 175039651abdSSudarsana Reddy Kalluru break; 175139651abdSSudarsana Reddy Kalluru case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: 175239651abdSSudarsana Reddy Kalluru qed_dcbx_mib_update_event(p_hwfn, p_ptt, 175339651abdSSudarsana Reddy Kalluru QED_DCBX_OPERATIONAL_MIB); 175439651abdSSudarsana Reddy Kalluru break; 1755cac6f691SSudarsana Reddy Kalluru case MFW_DRV_MSG_OEM_CFG_UPDATE: 1756cac6f691SSudarsana Reddy Kalluru qed_mcp_handle_ufp_event(p_hwfn, p_ptt); 1757cac6f691SSudarsana Reddy Kalluru break; 1758334c03b5SZvi Nachmani case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: 1759334c03b5SZvi Nachmani qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); 1760334c03b5SZvi Nachmani break; 17616c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_LAN_STATS: 17626c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_FCOE_STATS: 17636c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_ISCSI_STATS: 17646c754246SSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_RDMA_STATS: 17656c754246SSudarsana Reddy Kalluru qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); 17666c754246SSudarsana Reddy Kalluru break; 17674b01e519SManish Chopra case MFW_DRV_MSG_BW_UPDATE: 17684b01e519SManish Chopra qed_mcp_update_bw(p_hwfn, p_ptt); 17694b01e519SManish Chopra break; 17702a351fd9SMintz, Yuval case MFW_DRV_MSG_S_TAG_UPDATE: 17712a351fd9SMintz, Yuval qed_mcp_update_stag(p_hwfn, p_ptt); 17722a351fd9SMintz, Yuval break; 177359ccf86fSSudarsana Reddy Kalluru case MFW_DRV_MSG_GET_TLV_REQ: 177459ccf86fSSudarsana Reddy Kalluru qed_mfw_tlv_req(p_hwfn); 17752a351fd9SMintz, Yuval break; 1776cc875c2eSYuval Mintz default: 177739815944SMintz, Yuval DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); 1778cc875c2eSYuval Mintz rc = -EINVAL; 1779cc875c2eSYuval Mintz } 1780cc875c2eSYuval Mintz } 1781cc875c2eSYuval Mintz 1782cc875c2eSYuval Mintz /* ACK everything */ 1783cc875c2eSYuval Mintz for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { 1784cc875c2eSYuval Mintz __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); 1785cc875c2eSYuval Mintz 1786cc875c2eSYuval Mintz /* MFW expect answer in BE, so we force write in that format */ 1787cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, 1788cc875c2eSYuval Mintz info->mfw_mb_addr + sizeof(u32) + 1789cc875c2eSYuval Mintz MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * 1790cc875c2eSYuval Mintz sizeof(u32) + i * sizeof(u32), 1791cc875c2eSYuval Mintz (__force u32)val); 1792cc875c2eSYuval Mintz } 1793cc875c2eSYuval Mintz 1794cc875c2eSYuval Mintz if (!found) { 1795cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, 1796cc875c2eSYuval Mintz "Received an MFW message indication but no new message!\n"); 1797cc875c2eSYuval Mintz rc = -EINVAL; 1798cc875c2eSYuval Mintz } 1799cc875c2eSYuval Mintz 1800cc875c2eSYuval Mintz /* Copy the new mfw messages into the shadow */ 1801cc875c2eSYuval Mintz memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); 1802cc875c2eSYuval Mintz 1803cc875c2eSYuval Mintz return rc; 1804cc875c2eSYuval Mintz } 1805cc875c2eSYuval Mintz 18061408cc1fSYuval Mintz int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, 18071408cc1fSYuval Mintz struct qed_ptt *p_ptt, 18081408cc1fSYuval Mintz u32 *p_mfw_ver, u32 *p_running_bundle_id) 1809fe56b9e6SYuval Mintz { 1810fe56b9e6SYuval Mintz u32 global_offsize; 1811fe56b9e6SYuval Mintz 18121408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) { 18131408cc1fSYuval Mintz if (p_hwfn->vf_iov_info) { 18141408cc1fSYuval Mintz struct pfvf_acquire_resp_tlv *p_resp; 18151408cc1fSYuval Mintz 18161408cc1fSYuval Mintz p_resp = &p_hwfn->vf_iov_info->acquire_resp; 18171408cc1fSYuval Mintz *p_mfw_ver = p_resp->pfdev_info.mfw_ver; 18181408cc1fSYuval Mintz return 0; 18191408cc1fSYuval Mintz } else { 18201408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 18211408cc1fSYuval Mintz QED_MSG_IOV, 18221408cc1fSYuval Mintz "VF requested MFW version prior to ACQUIRE\n"); 18231408cc1fSYuval Mintz return -EINVAL; 18241408cc1fSYuval Mintz } 18251408cc1fSYuval Mintz } 1826fe56b9e6SYuval Mintz 1827fe56b9e6SYuval Mintz global_offsize = qed_rd(p_hwfn, p_ptt, 18281408cc1fSYuval Mintz SECTION_OFFSIZE_ADDR(p_hwfn-> 18291408cc1fSYuval Mintz mcp_info->public_base, 1830fe56b9e6SYuval Mintz PUBLIC_GLOBAL)); 18311408cc1fSYuval Mintz *p_mfw_ver = 18321408cc1fSYuval Mintz qed_rd(p_hwfn, p_ptt, 18331408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 18341408cc1fSYuval Mintz 0) + offsetof(struct public_global, mfw_ver)); 1835fe56b9e6SYuval Mintz 18361408cc1fSYuval Mintz if (p_running_bundle_id != NULL) { 18371408cc1fSYuval Mintz *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, 18381408cc1fSYuval Mintz SECTION_ADDR(global_offsize, 0) + 18391408cc1fSYuval Mintz offsetof(struct public_global, 18401408cc1fSYuval Mintz running_bundle_id)); 18411408cc1fSYuval Mintz } 1842fe56b9e6SYuval Mintz 1843fe56b9e6SYuval Mintz return 0; 1844fe56b9e6SYuval Mintz } 1845fe56b9e6SYuval Mintz 1846ae33666aSTomer Tayar int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, 1847ae33666aSTomer Tayar struct qed_ptt *p_ptt, u32 *p_mbi_ver) 1848ae33666aSTomer Tayar { 1849ae33666aSTomer Tayar u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; 1850ae33666aSTomer Tayar 1851ae33666aSTomer Tayar if (IS_VF(p_hwfn->cdev)) 1852ae33666aSTomer Tayar return -EINVAL; 1853ae33666aSTomer Tayar 1854ae33666aSTomer Tayar /* Read the address of the nvm_cfg */ 1855ae33666aSTomer Tayar nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1856ae33666aSTomer Tayar if (!nvm_cfg_addr) { 1857ae33666aSTomer Tayar DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1858ae33666aSTomer Tayar return -EINVAL; 1859ae33666aSTomer Tayar } 1860ae33666aSTomer Tayar 1861ae33666aSTomer Tayar /* Read the offset of nvm_cfg1 */ 1862ae33666aSTomer Tayar nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1863ae33666aSTomer Tayar 1864ae33666aSTomer Tayar mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1865ae33666aSTomer Tayar offsetof(struct nvm_cfg1, glob) + 1866ae33666aSTomer Tayar offsetof(struct nvm_cfg1_glob, mbi_version); 1867ae33666aSTomer Tayar *p_mbi_ver = qed_rd(p_hwfn, p_ptt, 1868ae33666aSTomer Tayar mbi_ver_addr) & 1869ae33666aSTomer Tayar (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | 1870ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_1_MASK | 1871ae33666aSTomer Tayar NVM_CFG1_GLOB_MBI_VERSION_2_MASK); 1872ae33666aSTomer Tayar 1873ae33666aSTomer Tayar return 0; 1874ae33666aSTomer Tayar } 1875ae33666aSTomer Tayar 1876706d0891SRahul Verma int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn, 1877706d0891SRahul Verma struct qed_ptt *p_ptt, u32 *p_media_type) 1878cc875c2eSYuval Mintz { 1879c56a8be7SRahul Verma *p_media_type = MEDIA_UNSPECIFIED; 1880c56a8be7SRahul Verma 1881706d0891SRahul Verma if (IS_VF(p_hwfn->cdev)) 18821408cc1fSYuval Mintz return -EINVAL; 18831408cc1fSYuval Mintz 1884cc875c2eSYuval Mintz if (!qed_mcp_is_init(p_hwfn)) { 1885cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1886cc875c2eSYuval Mintz return -EBUSY; 1887cc875c2eSYuval Mintz } 1888cc875c2eSYuval Mintz 1889706d0891SRahul Verma if (!p_ptt) { 1890cc875c2eSYuval Mintz *p_media_type = MEDIA_UNSPECIFIED; 1891706d0891SRahul Verma return -EINVAL; 1892706d0891SRahul Verma } 1893cc875c2eSYuval Mintz 1894706d0891SRahul Verma *p_media_type = qed_rd(p_hwfn, p_ptt, 1895706d0891SRahul Verma p_hwfn->mcp_info->port_addr + 1896706d0891SRahul Verma offsetof(struct public_port, 1897706d0891SRahul Verma media_type)); 1898cc875c2eSYuval Mintz 1899cc875c2eSYuval Mintz return 0; 1900cc875c2eSYuval Mintz } 1901cc875c2eSYuval Mintz 1902c56a8be7SRahul Verma int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn, 1903c56a8be7SRahul Verma struct qed_ptt *p_ptt, 1904c56a8be7SRahul Verma u32 *p_transceiver_state, 1905c56a8be7SRahul Verma u32 *p_transceiver_type) 1906c56a8be7SRahul Verma { 1907c56a8be7SRahul Verma u32 transceiver_info; 1908c56a8be7SRahul Verma 190968203a67SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE; 191068203a67SRahul Verma *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING; 191168203a67SRahul Verma 1912c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 1913c56a8be7SRahul Verma return -EINVAL; 1914c56a8be7SRahul Verma 1915c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 1916c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 1917c56a8be7SRahul Verma return -EBUSY; 1918c56a8be7SRahul Verma } 1919c56a8be7SRahul Verma 1920c56a8be7SRahul Verma transceiver_info = qed_rd(p_hwfn, p_ptt, 1921c56a8be7SRahul Verma p_hwfn->mcp_info->port_addr + 1922c56a8be7SRahul Verma offsetof(struct public_port, 1923c56a8be7SRahul Verma transceiver_data)); 1924c56a8be7SRahul Verma 1925c56a8be7SRahul Verma *p_transceiver_state = (transceiver_info & 1926c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_MASK) >> 1927c56a8be7SRahul Verma ETH_TRANSCEIVER_STATE_OFFSET; 1928c56a8be7SRahul Verma 1929c56a8be7SRahul Verma if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) 1930c56a8be7SRahul Verma *p_transceiver_type = (transceiver_info & 1931c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_MASK) >> 1932c56a8be7SRahul Verma ETH_TRANSCEIVER_TYPE_OFFSET; 1933c56a8be7SRahul Verma else 1934c56a8be7SRahul Verma *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN; 1935c56a8be7SRahul Verma 1936c56a8be7SRahul Verma return 0; 1937c56a8be7SRahul Verma } 1938c56a8be7SRahul Verma static bool qed_is_transceiver_ready(u32 transceiver_state, 1939c56a8be7SRahul Verma u32 transceiver_type) 1940c56a8be7SRahul Verma { 1941c56a8be7SRahul Verma if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) && 1942c56a8be7SRahul Verma ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) && 1943c56a8be7SRahul Verma (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE)) 1944c56a8be7SRahul Verma return true; 1945c56a8be7SRahul Verma 1946c56a8be7SRahul Verma return false; 1947c56a8be7SRahul Verma } 1948c56a8be7SRahul Verma 1949c56a8be7SRahul Verma int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn, 1950c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_speed_mask) 1951c56a8be7SRahul Verma { 1952c56a8be7SRahul Verma u32 transceiver_type, transceiver_state; 195392619210SArnd Bergmann int ret; 1954c56a8be7SRahul Verma 195592619210SArnd Bergmann ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, 1956c56a8be7SRahul Verma &transceiver_type); 195792619210SArnd Bergmann if (ret) 195892619210SArnd Bergmann return ret; 1959c56a8be7SRahul Verma 1960c56a8be7SRahul Verma if (qed_is_transceiver_ready(transceiver_state, transceiver_type) == 1961c56a8be7SRahul Verma false) 1962c56a8be7SRahul Verma return -EINVAL; 1963c56a8be7SRahul Verma 1964c56a8be7SRahul Verma switch (transceiver_type) { 1965c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_LX: 1966c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_SX: 1967c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_PCC: 1968c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1G_ACC: 1969c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_1000BASET: 1970c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1971c56a8be7SRahul Verma break; 1972c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_SR: 1973c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LR: 1974c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_LRM: 1975c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ER: 1976c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_PCC: 1977c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_ACC: 1978c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x10G: 1979c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1980c56a8be7SRahul Verma break; 1981c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_LR4: 1982c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_SR4: 1983c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 1984c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 1985c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 1986c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1987c56a8be7SRahul Verma break; 1988c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_AOC: 1989c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_SR4: 1990c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_LR4: 1991c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ER4: 1992c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_ACC: 1993c56a8be7SRahul Verma *p_speed_mask = 1994c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 1995c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1996c56a8be7SRahul Verma break; 1997c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_SR: 1998c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_LR: 1999c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_AOC: 2000c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_S: 2001c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_M: 2002c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_ACC_L: 2003c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2004c56a8be7SRahul Verma break; 2005c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_N: 2006c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_S: 2007c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_25G_CA_L: 2008c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_4x25G_CR: 2009c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2010c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2011c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2012c56a8be7SRahul Verma break; 2013c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_40G_CR4: 2014c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2015c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2016c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2017c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2018c56a8be7SRahul Verma break; 2019c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_100G_CR4: 2020c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2021c56a8be7SRahul Verma *p_speed_mask = 2022c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2023c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G | 2024c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2025c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2026c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G | 2027c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2028c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2029c56a8be7SRahul Verma break; 2030c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2031c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2032c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC: 2033c56a8be7SRahul Verma *p_speed_mask = 2034c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G | 2035c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G | 2036c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G | 2037c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2038c56a8be7SRahul Verma break; 2039c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_XLPPI: 2040c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2041c56a8be7SRahul Verma break; 2042c56a8be7SRahul Verma case ETH_TRANSCEIVER_TYPE_10G_BASET: 2043c56a8be7SRahul Verma *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G | 2044c56a8be7SRahul Verma NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2045c56a8be7SRahul Verma break; 2046c56a8be7SRahul Verma default: 20471107a674SColin Ian King DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n", 2048c56a8be7SRahul Verma transceiver_type); 2049c56a8be7SRahul Verma *p_speed_mask = 0xff; 2050c56a8be7SRahul Verma break; 2051c56a8be7SRahul Verma } 2052c56a8be7SRahul Verma 2053c56a8be7SRahul Verma return 0; 2054c56a8be7SRahul Verma } 2055c56a8be7SRahul Verma 2056c56a8be7SRahul Verma int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn, 2057c56a8be7SRahul Verma struct qed_ptt *p_ptt, u32 *p_board_config) 2058c56a8be7SRahul Verma { 2059c56a8be7SRahul Verma u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr; 2060c56a8be7SRahul Verma 2061c56a8be7SRahul Verma if (IS_VF(p_hwfn->cdev)) 2062c56a8be7SRahul Verma return -EINVAL; 2063c56a8be7SRahul Verma 2064c56a8be7SRahul Verma if (!qed_mcp_is_init(p_hwfn)) { 2065c56a8be7SRahul Verma DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); 2066c56a8be7SRahul Verma return -EBUSY; 2067c56a8be7SRahul Verma } 2068c56a8be7SRahul Verma if (!p_ptt) { 2069c56a8be7SRahul Verma *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 2070c56a8be7SRahul Verma return -EINVAL; 2071c56a8be7SRahul Verma } 2072c56a8be7SRahul Verma 2073c56a8be7SRahul Verma nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2074c56a8be7SRahul Verma nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2075c56a8be7SRahul Verma port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2076c56a8be7SRahul Verma offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2077c56a8be7SRahul Verma *p_board_config = qed_rd(p_hwfn, p_ptt, 2078c56a8be7SRahul Verma port_cfg_addr + 2079c56a8be7SRahul Verma offsetof(struct nvm_cfg1_port, 2080c56a8be7SRahul Verma board_cfg)); 2081c56a8be7SRahul Verma 2082c56a8be7SRahul Verma return 0; 2083c56a8be7SRahul Verma } 2084c56a8be7SRahul Verma 20856927e826SMintz, Yuval /* Old MFW has a global configuration for all PFs regarding RDMA support */ 20866927e826SMintz, Yuval static void 20876927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, 20886927e826SMintz, Yuval enum qed_pci_personality *p_proto) 20896927e826SMintz, Yuval { 20906927e826SMintz, Yuval /* There wasn't ever a legacy MFW that published iwarp. 20916927e826SMintz, Yuval * So at this point, this is either plain l2 or RoCE. 20926927e826SMintz, Yuval */ 20936927e826SMintz, Yuval if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) 20946927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 20956927e826SMintz, Yuval else 20966927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 20976927e826SMintz, Yuval 20986927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 20996927e826SMintz, Yuval "According to Legacy capabilities, L2 personality is %08x\n", 21006927e826SMintz, Yuval (u32) *p_proto); 21016927e826SMintz, Yuval } 21026927e826SMintz, Yuval 21036927e826SMintz, Yuval static int 21046927e826SMintz, Yuval qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, 21056927e826SMintz, Yuval struct qed_ptt *p_ptt, 21066927e826SMintz, Yuval enum qed_pci_personality *p_proto) 21076927e826SMintz, Yuval { 21086927e826SMintz, Yuval u32 resp = 0, param = 0; 21096927e826SMintz, Yuval int rc; 21106927e826SMintz, Yuval 21116927e826SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 21126927e826SMintz, Yuval DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); 21136927e826SMintz, Yuval if (rc) 21146927e826SMintz, Yuval return rc; 21156927e826SMintz, Yuval if (resp != FW_MSG_CODE_OK) { 21166927e826SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 21176927e826SMintz, Yuval "MFW lacks support for command; Returns %08x\n", 21186927e826SMintz, Yuval resp); 21196927e826SMintz, Yuval return -EINVAL; 21206927e826SMintz, Yuval } 21216927e826SMintz, Yuval 21226927e826SMintz, Yuval switch (param) { 21236927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_NONE: 21246927e826SMintz, Yuval *p_proto = QED_PCI_ETH; 21256927e826SMintz, Yuval break; 21266927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_ROCE: 21276927e826SMintz, Yuval *p_proto = QED_PCI_ETH_ROCE; 21286927e826SMintz, Yuval break; 21296927e826SMintz, Yuval case FW_MB_PARAM_GET_PF_RDMA_IWARP: 2130e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_IWARP; 2131e0a8f9deSMichal Kalderon break; 2132e0a8f9deSMichal Kalderon case FW_MB_PARAM_GET_PF_RDMA_BOTH: 2133e0a8f9deSMichal Kalderon *p_proto = QED_PCI_ETH_RDMA; 2134e0a8f9deSMichal Kalderon break; 21356927e826SMintz, Yuval default: 21366927e826SMintz, Yuval DP_NOTICE(p_hwfn, 21376927e826SMintz, Yuval "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", 21386927e826SMintz, Yuval param); 21396927e826SMintz, Yuval return -EINVAL; 21406927e826SMintz, Yuval } 21416927e826SMintz, Yuval 21426927e826SMintz, Yuval DP_VERBOSE(p_hwfn, 21436927e826SMintz, Yuval NETIF_MSG_IFUP, 21446927e826SMintz, Yuval "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", 21456927e826SMintz, Yuval (u32) *p_proto, resp, param); 21466927e826SMintz, Yuval return 0; 21476927e826SMintz, Yuval } 21486927e826SMintz, Yuval 2149fe56b9e6SYuval Mintz static int 2150fe56b9e6SYuval Mintz qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, 2151fe56b9e6SYuval Mintz struct public_func *p_info, 21526927e826SMintz, Yuval struct qed_ptt *p_ptt, 2153fe56b9e6SYuval Mintz enum qed_pci_personality *p_proto) 2154fe56b9e6SYuval Mintz { 2155fe56b9e6SYuval Mintz int rc = 0; 2156fe56b9e6SYuval Mintz 2157fe56b9e6SYuval Mintz switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { 2158fe56b9e6SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ETHERNET: 21591fe582ecSRam Amrani if (!IS_ENABLED(CONFIG_QED_RDMA)) 21601fe582ecSRam Amrani *p_proto = QED_PCI_ETH; 21611fe582ecSRam Amrani else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) 21626927e826SMintz, Yuval qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); 2163fe56b9e6SYuval Mintz break; 2164c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ISCSI: 2165c5ac9319SYuval Mintz *p_proto = QED_PCI_ISCSI; 2166c5ac9319SYuval Mintz break; 21671e128c81SArun Easi case FUNC_MF_CFG_PROTOCOL_FCOE: 21681e128c81SArun Easi *p_proto = QED_PCI_FCOE; 21691e128c81SArun Easi break; 2170c5ac9319SYuval Mintz case FUNC_MF_CFG_PROTOCOL_ROCE: 2171c5ac9319SYuval Mintz DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); 21726927e826SMintz, Yuval /* Fallthrough */ 2173fe56b9e6SYuval Mintz default: 2174fe56b9e6SYuval Mintz rc = -EINVAL; 2175fe56b9e6SYuval Mintz } 2176fe56b9e6SYuval Mintz 2177fe56b9e6SYuval Mintz return rc; 2178fe56b9e6SYuval Mintz } 2179fe56b9e6SYuval Mintz 2180fe56b9e6SYuval Mintz int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, 2181fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2182fe56b9e6SYuval Mintz { 2183fe56b9e6SYuval Mintz struct qed_mcp_function_info *info; 2184fe56b9e6SYuval Mintz struct public_func shmem_info; 2185fe56b9e6SYuval Mintz 21861a635e48SYuval Mintz qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); 2187fe56b9e6SYuval Mintz info = &p_hwfn->mcp_info->func_info; 2188fe56b9e6SYuval Mintz 2189fe56b9e6SYuval Mintz info->pause_on_host = (shmem_info.config & 2190fe56b9e6SYuval Mintz FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; 2191fe56b9e6SYuval Mintz 21926927e826SMintz, Yuval if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, 21936927e826SMintz, Yuval &info->protocol)) { 2194fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Unknown personality %08x\n", 2195fe56b9e6SYuval Mintz (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); 2196fe56b9e6SYuval Mintz return -EINVAL; 2197fe56b9e6SYuval Mintz } 2198fe56b9e6SYuval Mintz 21994b01e519SManish Chopra qed_read_pf_bandwidth(p_hwfn, &shmem_info); 2200fe56b9e6SYuval Mintz 2201fe56b9e6SYuval Mintz if (shmem_info.mac_upper || shmem_info.mac_lower) { 2202fe56b9e6SYuval Mintz info->mac[0] = (u8)(shmem_info.mac_upper >> 8); 2203fe56b9e6SYuval Mintz info->mac[1] = (u8)(shmem_info.mac_upper); 2204fe56b9e6SYuval Mintz info->mac[2] = (u8)(shmem_info.mac_lower >> 24); 2205fe56b9e6SYuval Mintz info->mac[3] = (u8)(shmem_info.mac_lower >> 16); 2206fe56b9e6SYuval Mintz info->mac[4] = (u8)(shmem_info.mac_lower >> 8); 2207fe56b9e6SYuval Mintz info->mac[5] = (u8)(shmem_info.mac_lower); 220814d39648SMintz, Yuval 220914d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 221014d39648SMintz, Yuval memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); 2211fe56b9e6SYuval Mintz } else { 2212fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); 2213fe56b9e6SYuval Mintz } 2214fe56b9e6SYuval Mintz 221557796759SMintz, Yuval info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | 221657796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); 221757796759SMintz, Yuval info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | 221857796759SMintz, Yuval (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); 2219fe56b9e6SYuval Mintz 2220fe56b9e6SYuval Mintz info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); 2221fe56b9e6SYuval Mintz 22220fefbfbaSSudarsana Kalluru info->mtu = (u16)shmem_info.mtu_size; 22230fefbfbaSSudarsana Kalluru 222414d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; 222514d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; 222614d39648SMintz, Yuval if (qed_mcp_is_init(p_hwfn)) { 222714d39648SMintz, Yuval u32 resp = 0, param = 0; 222814d39648SMintz, Yuval int rc; 222914d39648SMintz, Yuval 223014d39648SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, 223114d39648SMintz, Yuval DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); 223214d39648SMintz, Yuval if (rc) 223314d39648SMintz, Yuval return rc; 223414d39648SMintz, Yuval if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) 223514d39648SMintz, Yuval p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; 223614d39648SMintz, Yuval } 223714d39648SMintz, Yuval 2238fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), 223914d39648SMintz, Yuval "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", 2240fe56b9e6SYuval Mintz info->pause_on_host, info->protocol, 2241fe56b9e6SYuval Mintz info->bandwidth_min, info->bandwidth_max, 2242fe56b9e6SYuval Mintz info->mac[0], info->mac[1], info->mac[2], 2243fe56b9e6SYuval Mintz info->mac[3], info->mac[4], info->mac[5], 224414d39648SMintz, Yuval info->wwn_port, info->wwn_node, 224514d39648SMintz, Yuval info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); 2246fe56b9e6SYuval Mintz 2247fe56b9e6SYuval Mintz return 0; 2248fe56b9e6SYuval Mintz } 2249fe56b9e6SYuval Mintz 2250cc875c2eSYuval Mintz struct qed_mcp_link_params 2251cc875c2eSYuval Mintz *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) 2252cc875c2eSYuval Mintz { 2253cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2254cc875c2eSYuval Mintz return NULL; 2255cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_input; 2256cc875c2eSYuval Mintz } 2257cc875c2eSYuval Mintz 2258cc875c2eSYuval Mintz struct qed_mcp_link_state 2259cc875c2eSYuval Mintz *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) 2260cc875c2eSYuval Mintz { 2261cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2262cc875c2eSYuval Mintz return NULL; 2263cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_output; 2264cc875c2eSYuval Mintz } 2265cc875c2eSYuval Mintz 2266cc875c2eSYuval Mintz struct qed_mcp_link_capabilities 2267cc875c2eSYuval Mintz *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) 2268cc875c2eSYuval Mintz { 2269cc875c2eSYuval Mintz if (!p_hwfn || !p_hwfn->mcp_info) 2270cc875c2eSYuval Mintz return NULL; 2271cc875c2eSYuval Mintz return &p_hwfn->mcp_info->link_capabilities; 2272cc875c2eSYuval Mintz } 2273cc875c2eSYuval Mintz 22741a635e48SYuval Mintz int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2275fe56b9e6SYuval Mintz { 2276fe56b9e6SYuval Mintz u32 resp = 0, param = 0; 2277fe56b9e6SYuval Mintz int rc; 2278fe56b9e6SYuval Mintz 2279fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, 22801a635e48SYuval Mintz DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); 2281fe56b9e6SYuval Mintz 2282fe56b9e6SYuval Mintz /* Wait for the drain to complete before returning */ 22838f60bafeSYuval Mintz msleep(1020); 2284fe56b9e6SYuval Mintz 2285fe56b9e6SYuval Mintz return rc; 2286fe56b9e6SYuval Mintz } 2287fe56b9e6SYuval Mintz 2288cee4d264SManish Chopra int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, 22891a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 *p_flash_size) 2290cee4d264SManish Chopra { 2291cee4d264SManish Chopra u32 flash_size; 2292cee4d264SManish Chopra 22931408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 22941408cc1fSYuval Mintz return -EINVAL; 22951408cc1fSYuval Mintz 2296cee4d264SManish Chopra flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); 2297cee4d264SManish Chopra flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> 2298cee4d264SManish Chopra MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; 2299cee4d264SManish Chopra flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); 2300cee4d264SManish Chopra 2301cee4d264SManish Chopra *p_flash_size = flash_size; 2302cee4d264SManish Chopra 2303cee4d264SManish Chopra return 0; 2304cee4d264SManish Chopra } 2305cee4d264SManish Chopra 230688072fd4SMintz, Yuval static int 230788072fd4SMintz, Yuval qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, 23081408cc1fSYuval Mintz struct qed_ptt *p_ptt, u8 vf_id, u8 num) 23091408cc1fSYuval Mintz { 23101408cc1fSYuval Mintz u32 resp = 0, param = 0, rc_param = 0; 23111408cc1fSYuval Mintz int rc; 23121408cc1fSYuval Mintz 23131408cc1fSYuval Mintz /* Only Leader can configure MSIX, and need to take CMT into account */ 23141408cc1fSYuval Mintz if (!IS_LEAD_HWFN(p_hwfn)) 23151408cc1fSYuval Mintz return 0; 23161408cc1fSYuval Mintz num *= p_hwfn->cdev->num_hwfns; 23171408cc1fSYuval Mintz 23181408cc1fSYuval Mintz param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & 23191408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; 23201408cc1fSYuval Mintz param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & 23211408cc1fSYuval Mintz DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; 23221408cc1fSYuval Mintz 23231408cc1fSYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, 23241408cc1fSYuval Mintz &resp, &rc_param); 23251408cc1fSYuval Mintz 23261408cc1fSYuval Mintz if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { 23271408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); 23281408cc1fSYuval Mintz rc = -EINVAL; 23291408cc1fSYuval Mintz } else { 23301408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 23311408cc1fSYuval Mintz "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", 23321408cc1fSYuval Mintz num, vf_id); 23331408cc1fSYuval Mintz } 23341408cc1fSYuval Mintz 23351408cc1fSYuval Mintz return rc; 23361408cc1fSYuval Mintz } 23371408cc1fSYuval Mintz 233888072fd4SMintz, Yuval static int 233988072fd4SMintz, Yuval qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, 234088072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 num) 234188072fd4SMintz, Yuval { 234288072fd4SMintz, Yuval u32 resp = 0, param = num, rc_param = 0; 234388072fd4SMintz, Yuval int rc; 234488072fd4SMintz, Yuval 234588072fd4SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, 234688072fd4SMintz, Yuval param, &resp, &rc_param); 234788072fd4SMintz, Yuval 234888072fd4SMintz, Yuval if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { 234988072fd4SMintz, Yuval DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); 235088072fd4SMintz, Yuval rc = -EINVAL; 235188072fd4SMintz, Yuval } else { 235288072fd4SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_IOV, 235388072fd4SMintz, Yuval "Requested 0x%02x MSI-x interrupts for VFs\n", num); 235488072fd4SMintz, Yuval } 235588072fd4SMintz, Yuval 235688072fd4SMintz, Yuval return rc; 235788072fd4SMintz, Yuval } 235888072fd4SMintz, Yuval 235988072fd4SMintz, Yuval int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, 236088072fd4SMintz, Yuval struct qed_ptt *p_ptt, u8 vf_id, u8 num) 236188072fd4SMintz, Yuval { 236288072fd4SMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 236388072fd4SMintz, Yuval return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); 236488072fd4SMintz, Yuval else 236588072fd4SMintz, Yuval return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); 236688072fd4SMintz, Yuval } 236788072fd4SMintz, Yuval 2368fe56b9e6SYuval Mintz int 2369fe56b9e6SYuval Mintz qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, 2370fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2371fe56b9e6SYuval Mintz struct qed_mcp_drv_version *p_ver) 2372fe56b9e6SYuval Mintz { 23735529bad9STomer Tayar struct qed_mcp_mb_params mb_params; 23742f67af8cSTomer Tayar struct drv_version_stc drv_version; 23755529bad9STomer Tayar __be32 val; 23765529bad9STomer Tayar u32 i; 23775529bad9STomer Tayar int rc; 2378fe56b9e6SYuval Mintz 23792f67af8cSTomer Tayar memset(&drv_version, 0, sizeof(drv_version)); 23802f67af8cSTomer Tayar drv_version.version = p_ver->version; 238167a99b70SYuval Mintz for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { 238267a99b70SYuval Mintz val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); 23832f67af8cSTomer Tayar *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; 2384fe56b9e6SYuval Mintz } 2385fe56b9e6SYuval Mintz 23865529bad9STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 23875529bad9STomer Tayar mb_params.cmd = DRV_MSG_CODE_SET_VERSION; 23882f67af8cSTomer Tayar mb_params.p_data_src = &drv_version; 23892f67af8cSTomer Tayar mb_params.data_src_size = sizeof(drv_version); 23905529bad9STomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 23915529bad9STomer Tayar if (rc) 2392fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 2393fe56b9e6SYuval Mintz 23945529bad9STomer Tayar return rc; 2395fe56b9e6SYuval Mintz } 239691420b83SSudarsana Kalluru 239776271809STomer Tayar /* A maximal 100 msec waiting time for the MCP to halt */ 239876271809STomer Tayar #define QED_MCP_HALT_SLEEP_MS 10 239976271809STomer Tayar #define QED_MCP_HALT_MAX_RETRIES 10 240076271809STomer Tayar 24014102426fSTomer Tayar int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 24024102426fSTomer Tayar { 240376271809STomer Tayar u32 resp = 0, param = 0, cpu_state, cnt = 0; 24044102426fSTomer Tayar int rc; 24054102426fSTomer Tayar 24064102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, 24074102426fSTomer Tayar ¶m); 240876271809STomer Tayar if (rc) { 24094102426fSTomer Tayar DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 24104102426fSTomer Tayar return rc; 24114102426fSTomer Tayar } 24124102426fSTomer Tayar 241376271809STomer Tayar do { 241476271809STomer Tayar msleep(QED_MCP_HALT_SLEEP_MS); 241576271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 241676271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) 241776271809STomer Tayar break; 241876271809STomer Tayar } while (++cnt < QED_MCP_HALT_MAX_RETRIES); 241976271809STomer Tayar 242076271809STomer Tayar if (cnt == QED_MCP_HALT_MAX_RETRIES) { 242176271809STomer Tayar DP_NOTICE(p_hwfn, 242276271809STomer Tayar "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 242376271809STomer Tayar qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state); 242476271809STomer Tayar return -EBUSY; 242576271809STomer Tayar } 242676271809STomer Tayar 2427b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, true); 2428b310974eSTomer Tayar 242976271809STomer Tayar return 0; 243076271809STomer Tayar } 243176271809STomer Tayar 243276271809STomer Tayar #define QED_MCP_RESUME_SLEEP_MS 10 243376271809STomer Tayar 24344102426fSTomer Tayar int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 24354102426fSTomer Tayar { 243676271809STomer Tayar u32 cpu_mode, cpu_state; 24374102426fSTomer Tayar 24384102426fSTomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); 24394102426fSTomer Tayar 24404102426fSTomer Tayar cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); 244176271809STomer Tayar cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT; 244276271809STomer Tayar qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode); 244376271809STomer Tayar msleep(QED_MCP_RESUME_SLEEP_MS); 244476271809STomer Tayar cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE); 24454102426fSTomer Tayar 244676271809STomer Tayar if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) { 244776271809STomer Tayar DP_NOTICE(p_hwfn, 244876271809STomer Tayar "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n", 244976271809STomer Tayar cpu_mode, cpu_state); 245076271809STomer Tayar return -EBUSY; 245176271809STomer Tayar } 245276271809STomer Tayar 2453b310974eSTomer Tayar qed_mcp_cmd_set_blocking(p_hwfn, false); 2454b310974eSTomer Tayar 245576271809STomer Tayar return 0; 24564102426fSTomer Tayar } 24574102426fSTomer Tayar 24580fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, 24590fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 24600fefbfbaSSudarsana Kalluru enum qed_ov_client client) 24610fefbfbaSSudarsana Kalluru { 24620fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 24630fefbfbaSSudarsana Kalluru u32 drv_mb_param; 24640fefbfbaSSudarsana Kalluru int rc; 24650fefbfbaSSudarsana Kalluru 24660fefbfbaSSudarsana Kalluru switch (client) { 24670fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_DRV: 24680fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; 24690fefbfbaSSudarsana Kalluru break; 24700fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_USER: 24710fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; 24720fefbfbaSSudarsana Kalluru break; 24730fefbfbaSSudarsana Kalluru case QED_OV_CLIENT_VENDOR_SPEC: 24740fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; 24750fefbfbaSSudarsana Kalluru break; 24760fefbfbaSSudarsana Kalluru default: 24770fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); 24780fefbfbaSSudarsana Kalluru return -EINVAL; 24790fefbfbaSSudarsana Kalluru } 24800fefbfbaSSudarsana Kalluru 24810fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, 24820fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 24830fefbfbaSSudarsana Kalluru if (rc) 24840fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "MCP response failure, aborting\n"); 24850fefbfbaSSudarsana Kalluru 24860fefbfbaSSudarsana Kalluru return rc; 24870fefbfbaSSudarsana Kalluru } 24880fefbfbaSSudarsana Kalluru 24890fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, 24900fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 24910fefbfbaSSudarsana Kalluru enum qed_ov_driver_state drv_state) 24920fefbfbaSSudarsana Kalluru { 24930fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 24940fefbfbaSSudarsana Kalluru u32 drv_mb_param; 24950fefbfbaSSudarsana Kalluru int rc; 24960fefbfbaSSudarsana Kalluru 24970fefbfbaSSudarsana Kalluru switch (drv_state) { 24980fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_NOT_LOADED: 24990fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; 25000fefbfbaSSudarsana Kalluru break; 25010fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_DISABLED: 25020fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; 25030fefbfbaSSudarsana Kalluru break; 25040fefbfbaSSudarsana Kalluru case QED_OV_DRIVER_STATE_ACTIVE: 25050fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; 25060fefbfbaSSudarsana Kalluru break; 25070fefbfbaSSudarsana Kalluru default: 25080fefbfbaSSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); 25090fefbfbaSSudarsana Kalluru return -EINVAL; 25100fefbfbaSSudarsana Kalluru } 25110fefbfbaSSudarsana Kalluru 25120fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, 25130fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 25140fefbfbaSSudarsana Kalluru if (rc) 25150fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send driver state\n"); 25160fefbfbaSSudarsana Kalluru 25170fefbfbaSSudarsana Kalluru return rc; 25180fefbfbaSSudarsana Kalluru } 25190fefbfbaSSudarsana Kalluru 25200fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, 25210fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u16 mtu) 25220fefbfbaSSudarsana Kalluru { 25230fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 25240fefbfbaSSudarsana Kalluru u32 drv_mb_param; 25250fefbfbaSSudarsana Kalluru int rc; 25260fefbfbaSSudarsana Kalluru 25270fefbfbaSSudarsana Kalluru drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; 25280fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, 25290fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 25300fefbfbaSSudarsana Kalluru if (rc) 25310fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); 25320fefbfbaSSudarsana Kalluru 25330fefbfbaSSudarsana Kalluru return rc; 25340fefbfbaSSudarsana Kalluru } 25350fefbfbaSSudarsana Kalluru 25360fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, 25370fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, u8 *mac) 25380fefbfbaSSudarsana Kalluru { 25390fefbfbaSSudarsana Kalluru struct qed_mcp_mb_params mb_params; 254017991002SMintz, Yuval u32 mfw_mac[2]; 25410fefbfbaSSudarsana Kalluru int rc; 25420fefbfbaSSudarsana Kalluru 25430fefbfbaSSudarsana Kalluru memset(&mb_params, 0, sizeof(mb_params)); 25440fefbfbaSSudarsana Kalluru mb_params.cmd = DRV_MSG_CODE_SET_VMAC; 25450fefbfbaSSudarsana Kalluru mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << 25460fefbfbaSSudarsana Kalluru DRV_MSG_CODE_VMAC_TYPE_SHIFT; 25470fefbfbaSSudarsana Kalluru mb_params.param |= MCP_PF_ID(p_hwfn); 25482f67af8cSTomer Tayar 254917991002SMintz, Yuval /* MCP is BE, and on LE platforms PCI would swap access to SHMEM 255017991002SMintz, Yuval * in 32-bit granularity. 255117991002SMintz, Yuval * So the MAC has to be set in native order [and not byte order], 255217991002SMintz, Yuval * otherwise it would be read incorrectly by MFW after swap. 255317991002SMintz, Yuval */ 255417991002SMintz, Yuval mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; 255517991002SMintz, Yuval mfw_mac[1] = mac[4] << 24 | mac[5] << 16; 255617991002SMintz, Yuval 255717991002SMintz, Yuval mb_params.p_data_src = (u8 *)mfw_mac; 255817991002SMintz, Yuval mb_params.data_src_size = 8; 25590fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 25600fefbfbaSSudarsana Kalluru if (rc) 25610fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); 25620fefbfbaSSudarsana Kalluru 256314d39648SMintz, Yuval /* Store primary MAC for later possible WoL */ 256414d39648SMintz, Yuval memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); 256514d39648SMintz, Yuval 25660fefbfbaSSudarsana Kalluru return rc; 25670fefbfbaSSudarsana Kalluru } 25680fefbfbaSSudarsana Kalluru 25690fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, 25700fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, enum qed_ov_wol wol) 25710fefbfbaSSudarsana Kalluru { 25720fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 25730fefbfbaSSudarsana Kalluru u32 drv_mb_param; 25740fefbfbaSSudarsana Kalluru int rc; 25750fefbfbaSSudarsana Kalluru 257614d39648SMintz, Yuval if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { 257714d39648SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_SP, 257814d39648SMintz, Yuval "Can't change WoL configuration when WoL isn't supported\n"); 257914d39648SMintz, Yuval return -EINVAL; 258014d39648SMintz, Yuval } 258114d39648SMintz, Yuval 25820fefbfbaSSudarsana Kalluru switch (wol) { 25830fefbfbaSSudarsana Kalluru case QED_OV_WOL_DEFAULT: 25840fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; 25850fefbfbaSSudarsana Kalluru break; 25860fefbfbaSSudarsana Kalluru case QED_OV_WOL_DISABLED: 25870fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; 25880fefbfbaSSudarsana Kalluru break; 25890fefbfbaSSudarsana Kalluru case QED_OV_WOL_ENABLED: 25900fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; 25910fefbfbaSSudarsana Kalluru break; 25920fefbfbaSSudarsana Kalluru default: 25930fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); 25940fefbfbaSSudarsana Kalluru return -EINVAL; 25950fefbfbaSSudarsana Kalluru } 25960fefbfbaSSudarsana Kalluru 25970fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, 25980fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 25990fefbfbaSSudarsana Kalluru if (rc) 26000fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); 26010fefbfbaSSudarsana Kalluru 260214d39648SMintz, Yuval /* Store the WoL update for a future unload */ 260314d39648SMintz, Yuval p_hwfn->cdev->wol_config = (u8)wol; 260414d39648SMintz, Yuval 26050fefbfbaSSudarsana Kalluru return rc; 26060fefbfbaSSudarsana Kalluru } 26070fefbfbaSSudarsana Kalluru 26080fefbfbaSSudarsana Kalluru int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, 26090fefbfbaSSudarsana Kalluru struct qed_ptt *p_ptt, 26100fefbfbaSSudarsana Kalluru enum qed_ov_eswitch eswitch) 26110fefbfbaSSudarsana Kalluru { 26120fefbfbaSSudarsana Kalluru u32 resp = 0, param = 0; 26130fefbfbaSSudarsana Kalluru u32 drv_mb_param; 26140fefbfbaSSudarsana Kalluru int rc; 26150fefbfbaSSudarsana Kalluru 26160fefbfbaSSudarsana Kalluru switch (eswitch) { 26170fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_NONE: 26180fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; 26190fefbfbaSSudarsana Kalluru break; 26200fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEB: 26210fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; 26220fefbfbaSSudarsana Kalluru break; 26230fefbfbaSSudarsana Kalluru case QED_OV_ESWITCH_VEPA: 26240fefbfbaSSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; 26250fefbfbaSSudarsana Kalluru break; 26260fefbfbaSSudarsana Kalluru default: 26270fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); 26280fefbfbaSSudarsana Kalluru return -EINVAL; 26290fefbfbaSSudarsana Kalluru } 26300fefbfbaSSudarsana Kalluru 26310fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, 26320fefbfbaSSudarsana Kalluru drv_mb_param, &resp, ¶m); 26330fefbfbaSSudarsana Kalluru if (rc) 26340fefbfbaSSudarsana Kalluru DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); 26350fefbfbaSSudarsana Kalluru 26360fefbfbaSSudarsana Kalluru return rc; 26370fefbfbaSSudarsana Kalluru } 26380fefbfbaSSudarsana Kalluru 26391a635e48SYuval Mintz int qed_mcp_set_led(struct qed_hwfn *p_hwfn, 26401a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_led_mode mode) 264191420b83SSudarsana Kalluru { 264291420b83SSudarsana Kalluru u32 resp = 0, param = 0, drv_mb_param; 264391420b83SSudarsana Kalluru int rc; 264491420b83SSudarsana Kalluru 264591420b83SSudarsana Kalluru switch (mode) { 264691420b83SSudarsana Kalluru case QED_LED_MODE_ON: 264791420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; 264891420b83SSudarsana Kalluru break; 264991420b83SSudarsana Kalluru case QED_LED_MODE_OFF: 265091420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; 265191420b83SSudarsana Kalluru break; 265291420b83SSudarsana Kalluru case QED_LED_MODE_RESTORE: 265391420b83SSudarsana Kalluru drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; 265491420b83SSudarsana Kalluru break; 265591420b83SSudarsana Kalluru default: 265691420b83SSudarsana Kalluru DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); 265791420b83SSudarsana Kalluru return -EINVAL; 265891420b83SSudarsana Kalluru } 265991420b83SSudarsana Kalluru 266091420b83SSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, 266191420b83SSudarsana Kalluru drv_mb_param, &resp, ¶m); 266291420b83SSudarsana Kalluru 266391420b83SSudarsana Kalluru return rc; 266491420b83SSudarsana Kalluru } 266503dc76caSSudarsana Reddy Kalluru 26664102426fSTomer Tayar int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, 26674102426fSTomer Tayar struct qed_ptt *p_ptt, u32 mask_parities) 26684102426fSTomer Tayar { 26694102426fSTomer Tayar u32 resp = 0, param = 0; 26704102426fSTomer Tayar int rc; 26714102426fSTomer Tayar 26724102426fSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, 26734102426fSTomer Tayar mask_parities, &resp, ¶m); 26744102426fSTomer Tayar 26754102426fSTomer Tayar if (rc) { 26764102426fSTomer Tayar DP_ERR(p_hwfn, 26774102426fSTomer Tayar "MCP response failure for mask parities, aborting\n"); 26784102426fSTomer Tayar } else if (resp != FW_MSG_CODE_OK) { 26794102426fSTomer Tayar DP_ERR(p_hwfn, 26804102426fSTomer Tayar "MCP did not acknowledge mask parity request. Old MFW?\n"); 26814102426fSTomer Tayar rc = -EINVAL; 26824102426fSTomer Tayar } 26834102426fSTomer Tayar 26844102426fSTomer Tayar return rc; 26854102426fSTomer Tayar } 26864102426fSTomer Tayar 26877a4b21b7SMintz, Yuval int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) 26887a4b21b7SMintz, Yuval { 26897a4b21b7SMintz, Yuval u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; 26907a4b21b7SMintz, Yuval struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 26917a4b21b7SMintz, Yuval u32 resp = 0, resp_param = 0; 26927a4b21b7SMintz, Yuval struct qed_ptt *p_ptt; 26937a4b21b7SMintz, Yuval int rc = 0; 26947a4b21b7SMintz, Yuval 26957a4b21b7SMintz, Yuval p_ptt = qed_ptt_acquire(p_hwfn); 26967a4b21b7SMintz, Yuval if (!p_ptt) 26977a4b21b7SMintz, Yuval return -EBUSY; 26987a4b21b7SMintz, Yuval 26997a4b21b7SMintz, Yuval while (bytes_left > 0) { 27007a4b21b7SMintz, Yuval bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); 27017a4b21b7SMintz, Yuval 27027a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 27037a4b21b7SMintz, Yuval DRV_MSG_CODE_NVM_READ_NVRAM, 27047a4b21b7SMintz, Yuval addr + offset + 27057a4b21b7SMintz, Yuval (bytes_to_copy << 2706da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 27077a4b21b7SMintz, Yuval &resp, &resp_param, 27087a4b21b7SMintz, Yuval &read_len, 27097a4b21b7SMintz, Yuval (u32 *)(p_buf + offset)); 27107a4b21b7SMintz, Yuval 27117a4b21b7SMintz, Yuval if (rc || (resp != FW_MSG_CODE_NVM_OK)) { 27127a4b21b7SMintz, Yuval DP_NOTICE(cdev, "MCP command rc = %d\n", rc); 27137a4b21b7SMintz, Yuval break; 27147a4b21b7SMintz, Yuval } 27157a4b21b7SMintz, Yuval 27167a4b21b7SMintz, Yuval /* This can be a lengthy process, and it's possible scheduler 27177a4b21b7SMintz, Yuval * isn't preemptable. Sleep a bit to prevent CPU hogging. 27187a4b21b7SMintz, Yuval */ 27197a4b21b7SMintz, Yuval if (bytes_left % 0x1000 < 27207a4b21b7SMintz, Yuval (bytes_left - read_len) % 0x1000) 27217a4b21b7SMintz, Yuval usleep_range(1000, 2000); 27227a4b21b7SMintz, Yuval 27237a4b21b7SMintz, Yuval offset += read_len; 27247a4b21b7SMintz, Yuval bytes_left -= read_len; 27257a4b21b7SMintz, Yuval } 27267a4b21b7SMintz, Yuval 27277a4b21b7SMintz, Yuval cdev->mcp_nvm_resp = resp; 27287a4b21b7SMintz, Yuval qed_ptt_release(p_hwfn, p_ptt); 27297a4b21b7SMintz, Yuval 27307a4b21b7SMintz, Yuval return rc; 27317a4b21b7SMintz, Yuval } 27327a4b21b7SMintz, Yuval 273362e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf) 273462e4d438SSudarsana Reddy Kalluru { 273562e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 273662e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 273762e4d438SSudarsana Reddy Kalluru 273862e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 273962e4d438SSudarsana Reddy Kalluru if (!p_ptt) 274062e4d438SSudarsana Reddy Kalluru return -EBUSY; 274162e4d438SSudarsana Reddy Kalluru 274262e4d438SSudarsana Reddy Kalluru memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp)); 274362e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 274462e4d438SSudarsana Reddy Kalluru 274562e4d438SSudarsana Reddy Kalluru return 0; 274662e4d438SSudarsana Reddy Kalluru } 274762e4d438SSudarsana Reddy Kalluru 274862e4d438SSudarsana Reddy Kalluru int qed_mcp_nvm_write(struct qed_dev *cdev, 274962e4d438SSudarsana Reddy Kalluru u32 cmd, u32 addr, u8 *p_buf, u32 len) 275062e4d438SSudarsana Reddy Kalluru { 275162e4d438SSudarsana Reddy Kalluru u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param; 275262e4d438SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 275362e4d438SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 275462e4d438SSudarsana Reddy Kalluru int rc = -EINVAL; 275562e4d438SSudarsana Reddy Kalluru 275662e4d438SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 275762e4d438SSudarsana Reddy Kalluru if (!p_ptt) 275862e4d438SSudarsana Reddy Kalluru return -EBUSY; 275962e4d438SSudarsana Reddy Kalluru 276062e4d438SSudarsana Reddy Kalluru switch (cmd) { 2761057d2b19SSudarsana Reddy Kalluru case QED_PUT_FILE_BEGIN: 2762057d2b19SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN; 2763057d2b19SSudarsana Reddy Kalluru break; 276462e4d438SSudarsana Reddy Kalluru case QED_PUT_FILE_DATA: 276562e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA; 276662e4d438SSudarsana Reddy Kalluru break; 276762e4d438SSudarsana Reddy Kalluru case QED_NVM_WRITE_NVRAM: 276862e4d438SSudarsana Reddy Kalluru nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM; 276962e4d438SSudarsana Reddy Kalluru break; 277062e4d438SSudarsana Reddy Kalluru default: 277162e4d438SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd); 277262e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 277362e4d438SSudarsana Reddy Kalluru goto out; 277462e4d438SSudarsana Reddy Kalluru } 277562e4d438SSudarsana Reddy Kalluru 277662e4d438SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN); 2777057d2b19SSudarsana Reddy Kalluru while (buf_idx < len) { 2778057d2b19SSudarsana Reddy Kalluru if (cmd == QED_PUT_FILE_BEGIN) 2779057d2b19SSudarsana Reddy Kalluru nvm_offset = addr; 2780057d2b19SSudarsana Reddy Kalluru else 2781057d2b19SSudarsana Reddy Kalluru nvm_offset = ((buf_size << 2782057d2b19SSudarsana Reddy Kalluru DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) + 2783057d2b19SSudarsana Reddy Kalluru buf_idx; 278462e4d438SSudarsana Reddy Kalluru rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset, 278562e4d438SSudarsana Reddy Kalluru &resp, ¶m, buf_size, 278662e4d438SSudarsana Reddy Kalluru (u32 *)&p_buf[buf_idx]); 278762e4d438SSudarsana Reddy Kalluru if (rc) { 278862e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc); 278962e4d438SSudarsana Reddy Kalluru resp = FW_MSG_CODE_ERROR; 279062e4d438SSudarsana Reddy Kalluru break; 279162e4d438SSudarsana Reddy Kalluru } 279262e4d438SSudarsana Reddy Kalluru 279362e4d438SSudarsana Reddy Kalluru if (resp != FW_MSG_CODE_OK && 279462e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_OK && 279562e4d438SSudarsana Reddy Kalluru resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) { 279662e4d438SSudarsana Reddy Kalluru DP_NOTICE(cdev, 279762e4d438SSudarsana Reddy Kalluru "nvm write failed, resp = 0x%08x\n", resp); 279862e4d438SSudarsana Reddy Kalluru rc = -EINVAL; 279962e4d438SSudarsana Reddy Kalluru break; 280062e4d438SSudarsana Reddy Kalluru } 280162e4d438SSudarsana Reddy Kalluru 280262e4d438SSudarsana Reddy Kalluru /* This can be a lengthy process, and it's possible scheduler 280362e4d438SSudarsana Reddy Kalluru * isn't pre-emptable. Sleep a bit to prevent CPU hogging. 280462e4d438SSudarsana Reddy Kalluru */ 280562e4d438SSudarsana Reddy Kalluru if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000) 280662e4d438SSudarsana Reddy Kalluru usleep_range(1000, 2000); 280762e4d438SSudarsana Reddy Kalluru 2808057d2b19SSudarsana Reddy Kalluru /* For MBI upgrade, MFW response includes the next buffer offset 2809057d2b19SSudarsana Reddy Kalluru * to be delivered to MFW. 2810057d2b19SSudarsana Reddy Kalluru */ 2811057d2b19SSudarsana Reddy Kalluru if (param && cmd == QED_PUT_FILE_DATA) { 2812057d2b19SSudarsana Reddy Kalluru buf_idx = QED_MFW_GET_FIELD(param, 2813057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET); 2814057d2b19SSudarsana Reddy Kalluru buf_size = QED_MFW_GET_FIELD(param, 2815057d2b19SSudarsana Reddy Kalluru FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE); 2816057d2b19SSudarsana Reddy Kalluru } else { 281762e4d438SSudarsana Reddy Kalluru buf_idx += buf_size; 2818057d2b19SSudarsana Reddy Kalluru buf_size = min_t(u32, (len - buf_idx), 2819057d2b19SSudarsana Reddy Kalluru MCP_DRV_NVM_BUF_LEN); 2820057d2b19SSudarsana Reddy Kalluru } 282162e4d438SSudarsana Reddy Kalluru } 282262e4d438SSudarsana Reddy Kalluru 282362e4d438SSudarsana Reddy Kalluru cdev->mcp_nvm_resp = resp; 282462e4d438SSudarsana Reddy Kalluru out: 282562e4d438SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 282662e4d438SSudarsana Reddy Kalluru 282762e4d438SSudarsana Reddy Kalluru return rc; 282862e4d438SSudarsana Reddy Kalluru } 282962e4d438SSudarsana Reddy Kalluru 2830b51dab46SSudarsana Reddy Kalluru int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2831b51dab46SSudarsana Reddy Kalluru u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf) 2832b51dab46SSudarsana Reddy Kalluru { 2833b51dab46SSudarsana Reddy Kalluru u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0; 2834b51dab46SSudarsana Reddy Kalluru u32 resp, param; 2835b51dab46SSudarsana Reddy Kalluru int rc; 2836b51dab46SSudarsana Reddy Kalluru 2837b51dab46SSudarsana Reddy Kalluru nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) & 2838b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK; 2839b51dab46SSudarsana Reddy Kalluru nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) & 2840b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK; 2841b51dab46SSudarsana Reddy Kalluru 2842b51dab46SSudarsana Reddy Kalluru addr = offset; 2843b51dab46SSudarsana Reddy Kalluru offset = 0; 2844b51dab46SSudarsana Reddy Kalluru bytes_left = len; 2845b51dab46SSudarsana Reddy Kalluru while (bytes_left > 0) { 2846b51dab46SSudarsana Reddy Kalluru bytes_to_copy = min_t(u32, bytes_left, 2847b51dab46SSudarsana Reddy Kalluru MAX_I2C_TRANSACTION_SIZE); 2848b51dab46SSudarsana Reddy Kalluru nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK | 2849b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_PORT_MASK); 2850b51dab46SSudarsana Reddy Kalluru nvm_offset |= ((addr + offset) << 2851b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) & 2852b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK; 2853b51dab46SSudarsana Reddy Kalluru nvm_offset |= (bytes_to_copy << 2854b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) & 2855b51dab46SSudarsana Reddy Kalluru DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK; 2856b51dab46SSudarsana Reddy Kalluru rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 2857b51dab46SSudarsana Reddy Kalluru DRV_MSG_CODE_TRANSCEIVER_READ, 2858b51dab46SSudarsana Reddy Kalluru nvm_offset, &resp, ¶m, &buf_size, 2859b51dab46SSudarsana Reddy Kalluru (u32 *)(p_buf + offset)); 2860b51dab46SSudarsana Reddy Kalluru if (rc) { 2861b51dab46SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 2862b51dab46SSudarsana Reddy Kalluru "Failed to send a transceiver read command to the MFW. rc = %d.\n", 2863b51dab46SSudarsana Reddy Kalluru rc); 2864b51dab46SSudarsana Reddy Kalluru return rc; 2865b51dab46SSudarsana Reddy Kalluru } 2866b51dab46SSudarsana Reddy Kalluru 2867b51dab46SSudarsana Reddy Kalluru if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) 2868b51dab46SSudarsana Reddy Kalluru return -ENODEV; 2869b51dab46SSudarsana Reddy Kalluru else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK) 2870b51dab46SSudarsana Reddy Kalluru return -EINVAL; 2871b51dab46SSudarsana Reddy Kalluru 2872b51dab46SSudarsana Reddy Kalluru offset += buf_size; 2873b51dab46SSudarsana Reddy Kalluru bytes_left -= buf_size; 2874b51dab46SSudarsana Reddy Kalluru } 2875b51dab46SSudarsana Reddy Kalluru 2876b51dab46SSudarsana Reddy Kalluru return 0; 2877b51dab46SSudarsana Reddy Kalluru } 2878b51dab46SSudarsana Reddy Kalluru 287903dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 288003dc76caSSudarsana Reddy Kalluru { 288103dc76caSSudarsana Reddy Kalluru u32 drv_mb_param = 0, rsp, param; 288203dc76caSSudarsana Reddy Kalluru int rc = 0; 288303dc76caSSudarsana Reddy Kalluru 288403dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << 288503dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 288603dc76caSSudarsana Reddy Kalluru 288703dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 288803dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 288903dc76caSSudarsana Reddy Kalluru 289003dc76caSSudarsana Reddy Kalluru if (rc) 289103dc76caSSudarsana Reddy Kalluru return rc; 289203dc76caSSudarsana Reddy Kalluru 289303dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 289403dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 289503dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 289603dc76caSSudarsana Reddy Kalluru 289703dc76caSSudarsana Reddy Kalluru return rc; 289803dc76caSSudarsana Reddy Kalluru } 289903dc76caSSudarsana Reddy Kalluru 290003dc76caSSudarsana Reddy Kalluru int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 290103dc76caSSudarsana Reddy Kalluru { 290203dc76caSSudarsana Reddy Kalluru u32 drv_mb_param, rsp, param; 290303dc76caSSudarsana Reddy Kalluru int rc = 0; 290403dc76caSSudarsana Reddy Kalluru 290503dc76caSSudarsana Reddy Kalluru drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << 290603dc76caSSudarsana Reddy Kalluru DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 290703dc76caSSudarsana Reddy Kalluru 290803dc76caSSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 290903dc76caSSudarsana Reddy Kalluru drv_mb_param, &rsp, ¶m); 291003dc76caSSudarsana Reddy Kalluru 291103dc76caSSudarsana Reddy Kalluru if (rc) 291203dc76caSSudarsana Reddy Kalluru return rc; 291303dc76caSSudarsana Reddy Kalluru 291403dc76caSSudarsana Reddy Kalluru if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 291503dc76caSSudarsana Reddy Kalluru (param != DRV_MB_PARAM_BIST_RC_PASSED)) 291603dc76caSSudarsana Reddy Kalluru rc = -EAGAIN; 291703dc76caSSudarsana Reddy Kalluru 291803dc76caSSudarsana Reddy Kalluru return rc; 291903dc76caSSudarsana Reddy Kalluru } 29207a4b21b7SMintz, Yuval 292143645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn, 29227a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 29237a4b21b7SMintz, Yuval u32 *num_images) 29247a4b21b7SMintz, Yuval { 29257a4b21b7SMintz, Yuval u32 drv_mb_param = 0, rsp; 29267a4b21b7SMintz, Yuval int rc = 0; 29277a4b21b7SMintz, Yuval 29287a4b21b7SMintz, Yuval drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << 29297a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); 29307a4b21b7SMintz, Yuval 29317a4b21b7SMintz, Yuval rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, 29327a4b21b7SMintz, Yuval drv_mb_param, &rsp, num_images); 29337a4b21b7SMintz, Yuval if (rc) 29347a4b21b7SMintz, Yuval return rc; 29357a4b21b7SMintz, Yuval 29367a4b21b7SMintz, Yuval if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) 29377a4b21b7SMintz, Yuval rc = -EINVAL; 29387a4b21b7SMintz, Yuval 29397a4b21b7SMintz, Yuval return rc; 29407a4b21b7SMintz, Yuval } 29417a4b21b7SMintz, Yuval 294243645ce0SSudarsana Reddy Kalluru int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn, 29437a4b21b7SMintz, Yuval struct qed_ptt *p_ptt, 29447a4b21b7SMintz, Yuval struct bist_nvm_image_att *p_image_att, 29457a4b21b7SMintz, Yuval u32 image_index) 29467a4b21b7SMintz, Yuval { 29477a4b21b7SMintz, Yuval u32 buf_size = 0, param, resp = 0, resp_param = 0; 29487a4b21b7SMintz, Yuval int rc; 29497a4b21b7SMintz, Yuval 29507a4b21b7SMintz, Yuval param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << 29517a4b21b7SMintz, Yuval DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; 29527a4b21b7SMintz, Yuval param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; 29537a4b21b7SMintz, Yuval 29547a4b21b7SMintz, Yuval rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 29557a4b21b7SMintz, Yuval DRV_MSG_CODE_BIST_TEST, param, 29567a4b21b7SMintz, Yuval &resp, &resp_param, 29577a4b21b7SMintz, Yuval &buf_size, 29587a4b21b7SMintz, Yuval (u32 *)p_image_att); 29597a4b21b7SMintz, Yuval if (rc) 29607a4b21b7SMintz, Yuval return rc; 29617a4b21b7SMintz, Yuval 29627a4b21b7SMintz, Yuval if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || 29637a4b21b7SMintz, Yuval (p_image_att->return_code != 1)) 29647a4b21b7SMintz, Yuval rc = -EINVAL; 29657a4b21b7SMintz, Yuval 29667a4b21b7SMintz, Yuval return rc; 29677a4b21b7SMintz, Yuval } 29682edbff8dSTomer Tayar 296943645ce0SSudarsana Reddy Kalluru int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) 297043645ce0SSudarsana Reddy Kalluru { 29715e7ba042SDenis Bolotin struct qed_nvm_image_info nvm_info; 297243645ce0SSudarsana Reddy Kalluru struct qed_ptt *p_ptt; 297343645ce0SSudarsana Reddy Kalluru int rc; 297443645ce0SSudarsana Reddy Kalluru u32 i; 297543645ce0SSudarsana Reddy Kalluru 29765e7ba042SDenis Bolotin if (p_hwfn->nvm_info.valid) 29775e7ba042SDenis Bolotin return 0; 29785e7ba042SDenis Bolotin 297943645ce0SSudarsana Reddy Kalluru p_ptt = qed_ptt_acquire(p_hwfn); 298043645ce0SSudarsana Reddy Kalluru if (!p_ptt) { 298143645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "failed to acquire ptt\n"); 298243645ce0SSudarsana Reddy Kalluru return -EBUSY; 298343645ce0SSudarsana Reddy Kalluru } 298443645ce0SSudarsana Reddy Kalluru 298543645ce0SSudarsana Reddy Kalluru /* Acquire from MFW the amount of available images */ 29865e7ba042SDenis Bolotin nvm_info.num_images = 0; 298743645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, 29885e7ba042SDenis Bolotin p_ptt, &nvm_info.num_images); 298943645ce0SSudarsana Reddy Kalluru if (rc == -EOPNOTSUPP) { 299043645ce0SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n"); 299143645ce0SSudarsana Reddy Kalluru goto out; 29925e7ba042SDenis Bolotin } else if (rc || !nvm_info.num_images) { 299343645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Failed getting number of images\n"); 299443645ce0SSudarsana Reddy Kalluru goto err0; 299543645ce0SSudarsana Reddy Kalluru } 299643645ce0SSudarsana Reddy Kalluru 29975e7ba042SDenis Bolotin nvm_info.image_att = kmalloc_array(nvm_info.num_images, 299843645ce0SSudarsana Reddy Kalluru sizeof(struct bist_nvm_image_att), 299943645ce0SSudarsana Reddy Kalluru GFP_KERNEL); 30005e7ba042SDenis Bolotin if (!nvm_info.image_att) { 300143645ce0SSudarsana Reddy Kalluru rc = -ENOMEM; 300243645ce0SSudarsana Reddy Kalluru goto err0; 300343645ce0SSudarsana Reddy Kalluru } 300443645ce0SSudarsana Reddy Kalluru 300543645ce0SSudarsana Reddy Kalluru /* Iterate over images and get their attributes */ 30065e7ba042SDenis Bolotin for (i = 0; i < nvm_info.num_images; i++) { 300743645ce0SSudarsana Reddy Kalluru rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt, 30085e7ba042SDenis Bolotin &nvm_info.image_att[i], i); 300943645ce0SSudarsana Reddy Kalluru if (rc) { 301043645ce0SSudarsana Reddy Kalluru DP_ERR(p_hwfn, 301143645ce0SSudarsana Reddy Kalluru "Failed getting image index %d attributes\n", i); 301243645ce0SSudarsana Reddy Kalluru goto err1; 301343645ce0SSudarsana Reddy Kalluru } 301443645ce0SSudarsana Reddy Kalluru 301543645ce0SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i, 30165e7ba042SDenis Bolotin nvm_info.image_att[i].len); 301743645ce0SSudarsana Reddy Kalluru } 301843645ce0SSudarsana Reddy Kalluru out: 30195e7ba042SDenis Bolotin /* Update hwfn's nvm_info */ 30205e7ba042SDenis Bolotin if (nvm_info.num_images) { 30215e7ba042SDenis Bolotin p_hwfn->nvm_info.num_images = nvm_info.num_images; 30225e7ba042SDenis Bolotin kfree(p_hwfn->nvm_info.image_att); 30235e7ba042SDenis Bolotin p_hwfn->nvm_info.image_att = nvm_info.image_att; 30245e7ba042SDenis Bolotin p_hwfn->nvm_info.valid = true; 30255e7ba042SDenis Bolotin } 30265e7ba042SDenis Bolotin 302743645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 302843645ce0SSudarsana Reddy Kalluru return 0; 302943645ce0SSudarsana Reddy Kalluru 303043645ce0SSudarsana Reddy Kalluru err1: 30315e7ba042SDenis Bolotin kfree(nvm_info.image_att); 303243645ce0SSudarsana Reddy Kalluru err0: 303343645ce0SSudarsana Reddy Kalluru qed_ptt_release(p_hwfn, p_ptt); 303443645ce0SSudarsana Reddy Kalluru return rc; 303543645ce0SSudarsana Reddy Kalluru } 303643645ce0SSudarsana Reddy Kalluru 30371ac4329aSDenis Bolotin int 303820675b37SMintz, Yuval qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, 303920675b37SMintz, Yuval enum qed_nvm_images image_id, 304020675b37SMintz, Yuval struct qed_nvm_image_att *p_image_att) 304120675b37SMintz, Yuval { 304220675b37SMintz, Yuval enum nvm_image_type type; 304343645ce0SSudarsana Reddy Kalluru u32 i; 304420675b37SMintz, Yuval 304520675b37SMintz, Yuval /* Translate image_id into MFW definitions */ 304620675b37SMintz, Yuval switch (image_id) { 304720675b37SMintz, Yuval case QED_NVM_IMAGE_ISCSI_CFG: 304820675b37SMintz, Yuval type = NVM_TYPE_ISCSI_CFG; 304920675b37SMintz, Yuval break; 305020675b37SMintz, Yuval case QED_NVM_IMAGE_FCOE_CFG: 305120675b37SMintz, Yuval type = NVM_TYPE_FCOE_CFG; 305220675b37SMintz, Yuval break; 30531ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_CFG1: 30541ac4329aSDenis Bolotin type = NVM_TYPE_NVM_CFG1; 30551ac4329aSDenis Bolotin break; 30561ac4329aSDenis Bolotin case QED_NVM_IMAGE_DEFAULT_CFG: 30571ac4329aSDenis Bolotin type = NVM_TYPE_DEFAULT_CFG; 30581ac4329aSDenis Bolotin break; 30591ac4329aSDenis Bolotin case QED_NVM_IMAGE_NVM_META: 30601ac4329aSDenis Bolotin type = NVM_TYPE_META; 30611ac4329aSDenis Bolotin break; 306220675b37SMintz, Yuval default: 306320675b37SMintz, Yuval DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", 306420675b37SMintz, Yuval image_id); 306520675b37SMintz, Yuval return -EINVAL; 306620675b37SMintz, Yuval } 306720675b37SMintz, Yuval 30685e7ba042SDenis Bolotin qed_mcp_nvm_info_populate(p_hwfn); 306943645ce0SSudarsana Reddy Kalluru for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 307043645ce0SSudarsana Reddy Kalluru if (type == p_hwfn->nvm_info.image_att[i].image_type) 307120675b37SMintz, Yuval break; 307243645ce0SSudarsana Reddy Kalluru if (i == p_hwfn->nvm_info.num_images) { 307320675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 307420675b37SMintz, Yuval "Failed to find nvram image of type %08x\n", 307520675b37SMintz, Yuval image_id); 307643645ce0SSudarsana Reddy Kalluru return -ENOENT; 307720675b37SMintz, Yuval } 307820675b37SMintz, Yuval 307943645ce0SSudarsana Reddy Kalluru p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 308043645ce0SSudarsana Reddy Kalluru p_image_att->length = p_hwfn->nvm_info.image_att[i].len; 308120675b37SMintz, Yuval 308220675b37SMintz, Yuval return 0; 308320675b37SMintz, Yuval } 308420675b37SMintz, Yuval 308520675b37SMintz, Yuval int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, 308620675b37SMintz, Yuval enum qed_nvm_images image_id, 308720675b37SMintz, Yuval u8 *p_buffer, u32 buffer_len) 308820675b37SMintz, Yuval { 308920675b37SMintz, Yuval struct qed_nvm_image_att image_att; 309020675b37SMintz, Yuval int rc; 309120675b37SMintz, Yuval 309220675b37SMintz, Yuval memset(p_buffer, 0, buffer_len); 309320675b37SMintz, Yuval 3094b60bfdfeSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 309520675b37SMintz, Yuval if (rc) 309620675b37SMintz, Yuval return rc; 309720675b37SMintz, Yuval 309820675b37SMintz, Yuval /* Validate sizes - both the image's and the supplied buffer's */ 309920675b37SMintz, Yuval if (image_att.length <= 4) { 310020675b37SMintz, Yuval DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, 310120675b37SMintz, Yuval "Image [%d] is too small - only %d bytes\n", 310220675b37SMintz, Yuval image_id, image_att.length); 310320675b37SMintz, Yuval return -EINVAL; 310420675b37SMintz, Yuval } 310520675b37SMintz, Yuval 310620675b37SMintz, Yuval if (image_att.length > buffer_len) { 310720675b37SMintz, Yuval DP_VERBOSE(p_hwfn, 310820675b37SMintz, Yuval QED_MSG_STORAGE, 310920675b37SMintz, Yuval "Image [%d] is too big - %08x bytes where only %08x are available\n", 311020675b37SMintz, Yuval image_id, image_att.length, buffer_len); 311120675b37SMintz, Yuval return -ENOMEM; 311220675b37SMintz, Yuval } 311320675b37SMintz, Yuval 311420675b37SMintz, Yuval return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, 311520675b37SMintz, Yuval p_buffer, image_att.length); 311620675b37SMintz, Yuval } 311720675b37SMintz, Yuval 31189c8517c4STomer Tayar static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) 31199c8517c4STomer Tayar { 31209c8517c4STomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 31219c8517c4STomer Tayar 31229c8517c4STomer Tayar switch (res_id) { 31239c8517c4STomer Tayar case QED_SB: 31249c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 31259c8517c4STomer Tayar break; 31269c8517c4STomer Tayar case QED_L2_QUEUE: 31279c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 31289c8517c4STomer Tayar break; 31299c8517c4STomer Tayar case QED_VPORT: 31309c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 31319c8517c4STomer Tayar break; 31329c8517c4STomer Tayar case QED_RSS_ENG: 31339c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 31349c8517c4STomer Tayar break; 31359c8517c4STomer Tayar case QED_PQ: 31369c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 31379c8517c4STomer Tayar break; 31389c8517c4STomer Tayar case QED_RL: 31399c8517c4STomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 31409c8517c4STomer Tayar break; 31419c8517c4STomer Tayar case QED_MAC: 31429c8517c4STomer Tayar case QED_VLAN: 31439c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 31449c8517c4STomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 31459c8517c4STomer Tayar break; 31469c8517c4STomer Tayar case QED_ILT: 31479c8517c4STomer Tayar mfw_res_id = RESOURCE_ILT_E; 31489c8517c4STomer Tayar break; 31499c8517c4STomer Tayar case QED_LL2_QUEUE: 31509c8517c4STomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 31519c8517c4STomer Tayar break; 31529c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 31539c8517c4STomer Tayar case QED_CMDQS_CQS: 31549c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 31559c8517c4STomer Tayar mfw_res_id = RESOURCE_CQS_E; 31569c8517c4STomer Tayar break; 31579c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 31589c8517c4STomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 31599c8517c4STomer Tayar break; 31609c8517c4STomer Tayar case QED_BDQ: 31619c8517c4STomer Tayar mfw_res_id = RESOURCE_BDQ_E; 31629c8517c4STomer Tayar break; 31639c8517c4STomer Tayar default: 31649c8517c4STomer Tayar break; 31659c8517c4STomer Tayar } 31669c8517c4STomer Tayar 31679c8517c4STomer Tayar return mfw_res_id; 31689c8517c4STomer Tayar } 31699c8517c4STomer Tayar 31709c8517c4STomer Tayar #define QED_RESC_ALLOC_VERSION_MAJOR 2 31712edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION_MINOR 0 31722edbff8dSTomer Tayar #define QED_RESC_ALLOC_VERSION \ 31732edbff8dSTomer Tayar ((QED_RESC_ALLOC_VERSION_MAJOR << \ 31742edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ 31752edbff8dSTomer Tayar (QED_RESC_ALLOC_VERSION_MINOR << \ 31762edbff8dSTomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) 31779c8517c4STomer Tayar 31789c8517c4STomer Tayar struct qed_resc_alloc_in_params { 31799c8517c4STomer Tayar u32 cmd; 31809c8517c4STomer Tayar enum qed_resources res_id; 31819c8517c4STomer Tayar u32 resc_max_val; 31829c8517c4STomer Tayar }; 31839c8517c4STomer Tayar 31849c8517c4STomer Tayar struct qed_resc_alloc_out_params { 31859c8517c4STomer Tayar u32 mcp_resp; 31869c8517c4STomer Tayar u32 mcp_param; 31879c8517c4STomer Tayar u32 resc_num; 31889c8517c4STomer Tayar u32 resc_start; 31899c8517c4STomer Tayar u32 vf_resc_num; 31909c8517c4STomer Tayar u32 vf_resc_start; 31919c8517c4STomer Tayar u32 flags; 31929c8517c4STomer Tayar }; 31939c8517c4STomer Tayar 31949c8517c4STomer Tayar static int 31959c8517c4STomer Tayar qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, 31962edbff8dSTomer Tayar struct qed_ptt *p_ptt, 31979c8517c4STomer Tayar struct qed_resc_alloc_in_params *p_in_params, 31989c8517c4STomer Tayar struct qed_resc_alloc_out_params *p_out_params) 31992edbff8dSTomer Tayar { 32002edbff8dSTomer Tayar struct qed_mcp_mb_params mb_params; 32019c8517c4STomer Tayar struct resource_info mfw_resc_info; 32022edbff8dSTomer Tayar int rc; 32032edbff8dSTomer Tayar 32049c8517c4STomer Tayar memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); 3205bb480242SMintz, Yuval 32069c8517c4STomer Tayar mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); 32079c8517c4STomer Tayar if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { 32089c8517c4STomer Tayar DP_ERR(p_hwfn, 32099c8517c4STomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 32109c8517c4STomer Tayar p_in_params->res_id, 32119c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id)); 32129c8517c4STomer Tayar return -EINVAL; 32139c8517c4STomer Tayar } 32149c8517c4STomer Tayar 32159c8517c4STomer Tayar switch (p_in_params->cmd) { 32169c8517c4STomer Tayar case DRV_MSG_SET_RESOURCE_VALUE_MSG: 32179c8517c4STomer Tayar mfw_resc_info.size = p_in_params->resc_max_val; 32189c8517c4STomer Tayar /* Fallthrough */ 32199c8517c4STomer Tayar case DRV_MSG_GET_RESOURCE_ALLOC_MSG: 32209c8517c4STomer Tayar break; 32219c8517c4STomer Tayar default: 32229c8517c4STomer Tayar DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", 32239c8517c4STomer Tayar p_in_params->cmd); 32249c8517c4STomer Tayar return -EINVAL; 32259c8517c4STomer Tayar } 32269c8517c4STomer Tayar 32279c8517c4STomer Tayar memset(&mb_params, 0, sizeof(mb_params)); 32289c8517c4STomer Tayar mb_params.cmd = p_in_params->cmd; 32299c8517c4STomer Tayar mb_params.param = QED_RESC_ALLOC_VERSION; 32309c8517c4STomer Tayar mb_params.p_data_src = &mfw_resc_info; 32319c8517c4STomer Tayar mb_params.data_src_size = sizeof(mfw_resc_info); 32329c8517c4STomer Tayar mb_params.p_data_dst = mb_params.p_data_src; 32339c8517c4STomer Tayar mb_params.data_dst_size = mb_params.data_src_size; 32349c8517c4STomer Tayar 32359c8517c4STomer Tayar DP_VERBOSE(p_hwfn, 32369c8517c4STomer Tayar QED_MSG_SP, 32379c8517c4STomer Tayar "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", 32389c8517c4STomer Tayar p_in_params->cmd, 32399c8517c4STomer Tayar p_in_params->res_id, 32409c8517c4STomer Tayar qed_hw_get_resc_name(p_in_params->res_id), 32419c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 32429c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 32439c8517c4STomer Tayar QED_MFW_GET_FIELD(mb_params.param, 32449c8517c4STomer Tayar DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 32459c8517c4STomer Tayar p_in_params->resc_max_val); 32469c8517c4STomer Tayar 32472edbff8dSTomer Tayar rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); 32482edbff8dSTomer Tayar if (rc) 32492edbff8dSTomer Tayar return rc; 32502edbff8dSTomer Tayar 32519c8517c4STomer Tayar p_out_params->mcp_resp = mb_params.mcp_resp; 32529c8517c4STomer Tayar p_out_params->mcp_param = mb_params.mcp_param; 32539c8517c4STomer Tayar p_out_params->resc_num = mfw_resc_info.size; 32549c8517c4STomer Tayar p_out_params->resc_start = mfw_resc_info.offset; 32559c8517c4STomer Tayar p_out_params->vf_resc_num = mfw_resc_info.vf_size; 32569c8517c4STomer Tayar p_out_params->vf_resc_start = mfw_resc_info.vf_offset; 32579c8517c4STomer Tayar p_out_params->flags = mfw_resc_info.flags; 32582edbff8dSTomer Tayar 32592edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, 32602edbff8dSTomer Tayar QED_MSG_SP, 32619c8517c4STomer Tayar "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", 32629c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 32639c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), 32649c8517c4STomer Tayar QED_MFW_GET_FIELD(p_out_params->mcp_param, 32659c8517c4STomer Tayar FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), 32669c8517c4STomer Tayar p_out_params->resc_num, 32679c8517c4STomer Tayar p_out_params->resc_start, 32689c8517c4STomer Tayar p_out_params->vf_resc_num, 32699c8517c4STomer Tayar p_out_params->vf_resc_start, p_out_params->flags); 32709c8517c4STomer Tayar 32719c8517c4STomer Tayar return 0; 32729c8517c4STomer Tayar } 32739c8517c4STomer Tayar 32749c8517c4STomer Tayar int 32759c8517c4STomer Tayar qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, 32769c8517c4STomer Tayar struct qed_ptt *p_ptt, 32779c8517c4STomer Tayar enum qed_resources res_id, 32789c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 32799c8517c4STomer Tayar { 32809c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 32819c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 32829c8517c4STomer Tayar int rc; 32839c8517c4STomer Tayar 32849c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 32859c8517c4STomer Tayar in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; 32869c8517c4STomer Tayar in_params.res_id = res_id; 32879c8517c4STomer Tayar in_params.resc_max_val = resc_max_val; 32889c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 32899c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 32909c8517c4STomer Tayar &out_params); 32919c8517c4STomer Tayar if (rc) 32929c8517c4STomer Tayar return rc; 32939c8517c4STomer Tayar 32949c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 32959c8517c4STomer Tayar 32969c8517c4STomer Tayar return 0; 32979c8517c4STomer Tayar } 32989c8517c4STomer Tayar 32999c8517c4STomer Tayar int 33009c8517c4STomer Tayar qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, 33019c8517c4STomer Tayar struct qed_ptt *p_ptt, 33029c8517c4STomer Tayar enum qed_resources res_id, 33039c8517c4STomer Tayar u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) 33049c8517c4STomer Tayar { 33059c8517c4STomer Tayar struct qed_resc_alloc_out_params out_params; 33069c8517c4STomer Tayar struct qed_resc_alloc_in_params in_params; 33079c8517c4STomer Tayar int rc; 33089c8517c4STomer Tayar 33099c8517c4STomer Tayar memset(&in_params, 0, sizeof(in_params)); 33109c8517c4STomer Tayar in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; 33119c8517c4STomer Tayar in_params.res_id = res_id; 33129c8517c4STomer Tayar memset(&out_params, 0, sizeof(out_params)); 33139c8517c4STomer Tayar rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, 33149c8517c4STomer Tayar &out_params); 33159c8517c4STomer Tayar if (rc) 33169c8517c4STomer Tayar return rc; 33179c8517c4STomer Tayar 33189c8517c4STomer Tayar *p_mcp_resp = out_params.mcp_resp; 33199c8517c4STomer Tayar 33209c8517c4STomer Tayar if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { 33219c8517c4STomer Tayar *p_resc_num = out_params.resc_num; 33229c8517c4STomer Tayar *p_resc_start = out_params.resc_start; 33239c8517c4STomer Tayar } 33242edbff8dSTomer Tayar 33252edbff8dSTomer Tayar return 0; 33262edbff8dSTomer Tayar } 332718a69e36SMintz, Yuval 332818a69e36SMintz, Yuval int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 332918a69e36SMintz, Yuval { 333018a69e36SMintz, Yuval u32 mcp_resp, mcp_param; 333118a69e36SMintz, Yuval 333218a69e36SMintz, Yuval return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, 333318a69e36SMintz, Yuval &mcp_resp, &mcp_param); 333418a69e36SMintz, Yuval } 333595691c9cSTomer Tayar 333695691c9cSTomer Tayar static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, 333795691c9cSTomer Tayar struct qed_ptt *p_ptt, 333895691c9cSTomer Tayar u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) 333995691c9cSTomer Tayar { 334095691c9cSTomer Tayar int rc; 334195691c9cSTomer Tayar 334295691c9cSTomer Tayar rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, 334395691c9cSTomer Tayar p_mcp_resp, p_mcp_param); 334495691c9cSTomer Tayar if (rc) 334595691c9cSTomer Tayar return rc; 334695691c9cSTomer Tayar 334795691c9cSTomer Tayar if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { 334895691c9cSTomer Tayar DP_INFO(p_hwfn, 334995691c9cSTomer Tayar "The resource command is unsupported by the MFW\n"); 335095691c9cSTomer Tayar return -EINVAL; 335195691c9cSTomer Tayar } 335295691c9cSTomer Tayar 335395691c9cSTomer Tayar if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { 335495691c9cSTomer Tayar u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); 335595691c9cSTomer Tayar 335695691c9cSTomer Tayar DP_NOTICE(p_hwfn, 335795691c9cSTomer Tayar "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", 335895691c9cSTomer Tayar param, opcode); 335995691c9cSTomer Tayar return -EINVAL; 336095691c9cSTomer Tayar } 336195691c9cSTomer Tayar 336295691c9cSTomer Tayar return rc; 336395691c9cSTomer Tayar } 336495691c9cSTomer Tayar 3365bf774d14SYueHaibing static int 336695691c9cSTomer Tayar __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 336795691c9cSTomer Tayar struct qed_ptt *p_ptt, 336895691c9cSTomer Tayar struct qed_resc_lock_params *p_params) 336995691c9cSTomer Tayar { 337095691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 337195691c9cSTomer Tayar u8 opcode; 337295691c9cSTomer Tayar int rc; 337395691c9cSTomer Tayar 337495691c9cSTomer Tayar switch (p_params->timeout) { 337595691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_DEFAULT: 337695691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ; 337795691c9cSTomer Tayar p_params->timeout = 0; 337895691c9cSTomer Tayar break; 337995691c9cSTomer Tayar case QED_MCP_RESC_LOCK_TO_NONE: 338095691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_WO_AGING; 338195691c9cSTomer Tayar p_params->timeout = 0; 338295691c9cSTomer Tayar break; 338395691c9cSTomer Tayar default: 338495691c9cSTomer Tayar opcode = RESOURCE_OPCODE_REQ_W_AGING; 338595691c9cSTomer Tayar break; 338695691c9cSTomer Tayar } 338795691c9cSTomer Tayar 338895691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 338995691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 339095691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); 339195691c9cSTomer Tayar 339295691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 339395691c9cSTomer Tayar QED_MSG_SP, 339495691c9cSTomer Tayar "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", 339595691c9cSTomer Tayar param, p_params->timeout, opcode, p_params->resource); 339695691c9cSTomer Tayar 339795691c9cSTomer Tayar /* Attempt to acquire the resource */ 339895691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 339995691c9cSTomer Tayar if (rc) 340095691c9cSTomer Tayar return rc; 340195691c9cSTomer Tayar 340295691c9cSTomer Tayar /* Analyze the response */ 340395691c9cSTomer Tayar p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); 340495691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 340595691c9cSTomer Tayar 340695691c9cSTomer Tayar DP_VERBOSE(p_hwfn, 340795691c9cSTomer Tayar QED_MSG_SP, 340895691c9cSTomer Tayar "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", 340995691c9cSTomer Tayar mcp_param, opcode, p_params->owner); 341095691c9cSTomer Tayar 341195691c9cSTomer Tayar switch (opcode) { 341295691c9cSTomer Tayar case RESOURCE_OPCODE_GNT: 341395691c9cSTomer Tayar p_params->b_granted = true; 341495691c9cSTomer Tayar break; 341595691c9cSTomer Tayar case RESOURCE_OPCODE_BUSY: 341695691c9cSTomer Tayar p_params->b_granted = false; 341795691c9cSTomer Tayar break; 341895691c9cSTomer Tayar default: 341995691c9cSTomer Tayar DP_NOTICE(p_hwfn, 342095691c9cSTomer Tayar "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", 342195691c9cSTomer Tayar mcp_param, opcode); 342295691c9cSTomer Tayar return -EINVAL; 342395691c9cSTomer Tayar } 342495691c9cSTomer Tayar 342595691c9cSTomer Tayar return 0; 342695691c9cSTomer Tayar } 342795691c9cSTomer Tayar 342895691c9cSTomer Tayar int 342995691c9cSTomer Tayar qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, 343095691c9cSTomer Tayar struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) 343195691c9cSTomer Tayar { 343295691c9cSTomer Tayar u32 retry_cnt = 0; 343395691c9cSTomer Tayar int rc; 343495691c9cSTomer Tayar 343595691c9cSTomer Tayar do { 343695691c9cSTomer Tayar /* No need for an interval before the first iteration */ 343795691c9cSTomer Tayar if (retry_cnt) { 343895691c9cSTomer Tayar if (p_params->sleep_b4_retry) { 343995691c9cSTomer Tayar u16 retry_interval_in_ms = 344095691c9cSTomer Tayar DIV_ROUND_UP(p_params->retry_interval, 344195691c9cSTomer Tayar 1000); 344295691c9cSTomer Tayar 344395691c9cSTomer Tayar msleep(retry_interval_in_ms); 344495691c9cSTomer Tayar } else { 344595691c9cSTomer Tayar udelay(p_params->retry_interval); 344695691c9cSTomer Tayar } 344795691c9cSTomer Tayar } 344895691c9cSTomer Tayar 344995691c9cSTomer Tayar rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); 345095691c9cSTomer Tayar if (rc) 345195691c9cSTomer Tayar return rc; 345295691c9cSTomer Tayar 345395691c9cSTomer Tayar if (p_params->b_granted) 345495691c9cSTomer Tayar break; 345595691c9cSTomer Tayar } while (retry_cnt++ < p_params->retry_num); 345695691c9cSTomer Tayar 345795691c9cSTomer Tayar return 0; 345895691c9cSTomer Tayar } 345995691c9cSTomer Tayar 346095691c9cSTomer Tayar int 346195691c9cSTomer Tayar qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, 346295691c9cSTomer Tayar struct qed_ptt *p_ptt, 346395691c9cSTomer Tayar struct qed_resc_unlock_params *p_params) 346495691c9cSTomer Tayar { 346595691c9cSTomer Tayar u32 param = 0, mcp_resp, mcp_param; 346695691c9cSTomer Tayar u8 opcode; 346795691c9cSTomer Tayar int rc; 346895691c9cSTomer Tayar 346995691c9cSTomer Tayar opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE 347095691c9cSTomer Tayar : RESOURCE_OPCODE_RELEASE; 347195691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); 347295691c9cSTomer Tayar QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); 347395691c9cSTomer Tayar 347495691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 347595691c9cSTomer Tayar "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", 347695691c9cSTomer Tayar param, opcode, p_params->resource); 347795691c9cSTomer Tayar 347895691c9cSTomer Tayar /* Attempt to release the resource */ 347995691c9cSTomer Tayar rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); 348095691c9cSTomer Tayar if (rc) 348195691c9cSTomer Tayar return rc; 348295691c9cSTomer Tayar 348395691c9cSTomer Tayar /* Analyze the response */ 348495691c9cSTomer Tayar opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); 348595691c9cSTomer Tayar 348695691c9cSTomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, 348795691c9cSTomer Tayar "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", 348895691c9cSTomer Tayar mcp_param, opcode); 348995691c9cSTomer Tayar 349095691c9cSTomer Tayar switch (opcode) { 349195691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED_PREVIOUS: 349295691c9cSTomer Tayar DP_INFO(p_hwfn, 349395691c9cSTomer Tayar "Resource unlock request for an already released resource [%d]\n", 349495691c9cSTomer Tayar p_params->resource); 349595691c9cSTomer Tayar /* Fallthrough */ 349695691c9cSTomer Tayar case RESOURCE_OPCODE_RELEASED: 349795691c9cSTomer Tayar p_params->b_released = true; 349895691c9cSTomer Tayar break; 349995691c9cSTomer Tayar case RESOURCE_OPCODE_WRONG_OWNER: 350095691c9cSTomer Tayar p_params->b_released = false; 350195691c9cSTomer Tayar break; 350295691c9cSTomer Tayar default: 350395691c9cSTomer Tayar DP_NOTICE(p_hwfn, 350495691c9cSTomer Tayar "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", 350595691c9cSTomer Tayar mcp_param, opcode); 350695691c9cSTomer Tayar return -EINVAL; 350795691c9cSTomer Tayar } 350895691c9cSTomer Tayar 350995691c9cSTomer Tayar return 0; 351095691c9cSTomer Tayar } 3511f470f22cSsudarsana.kalluru@cavium.com 3512f470f22cSsudarsana.kalluru@cavium.com void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, 3513f470f22cSsudarsana.kalluru@cavium.com struct qed_resc_unlock_params *p_unlock, 3514f470f22cSsudarsana.kalluru@cavium.com enum qed_resc_lock 3515f470f22cSsudarsana.kalluru@cavium.com resource, bool b_is_permanent) 3516f470f22cSsudarsana.kalluru@cavium.com { 3517f470f22cSsudarsana.kalluru@cavium.com if (p_lock) { 3518f470f22cSsudarsana.kalluru@cavium.com memset(p_lock, 0, sizeof(*p_lock)); 3519f470f22cSsudarsana.kalluru@cavium.com 3520f470f22cSsudarsana.kalluru@cavium.com /* Permanent resources don't require aging, and there's no 3521f470f22cSsudarsana.kalluru@cavium.com * point in trying to acquire them more than once since it's 3522f470f22cSsudarsana.kalluru@cavium.com * unexpected another entity would release them. 3523f470f22cSsudarsana.kalluru@cavium.com */ 3524f470f22cSsudarsana.kalluru@cavium.com if (b_is_permanent) { 3525f470f22cSsudarsana.kalluru@cavium.com p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; 3526f470f22cSsudarsana.kalluru@cavium.com } else { 3527f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; 3528f470f22cSsudarsana.kalluru@cavium.com p_lock->retry_interval = 3529f470f22cSsudarsana.kalluru@cavium.com QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; 3530f470f22cSsudarsana.kalluru@cavium.com p_lock->sleep_b4_retry = true; 3531f470f22cSsudarsana.kalluru@cavium.com } 3532f470f22cSsudarsana.kalluru@cavium.com 3533f470f22cSsudarsana.kalluru@cavium.com p_lock->resource = resource; 3534f470f22cSsudarsana.kalluru@cavium.com } 3535f470f22cSsudarsana.kalluru@cavium.com 3536f470f22cSsudarsana.kalluru@cavium.com if (p_unlock) { 3537f470f22cSsudarsana.kalluru@cavium.com memset(p_unlock, 0, sizeof(*p_unlock)); 3538f470f22cSsudarsana.kalluru@cavium.com p_unlock->resource = resource; 3539f470f22cSsudarsana.kalluru@cavium.com } 3540f470f22cSsudarsana.kalluru@cavium.com } 3541645874e5SSudarsana Reddy Kalluru 3542645874e5SSudarsana Reddy Kalluru int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3543645874e5SSudarsana Reddy Kalluru { 3544645874e5SSudarsana Reddy Kalluru u32 mcp_resp; 3545645874e5SSudarsana Reddy Kalluru int rc; 3546645874e5SSudarsana Reddy Kalluru 3547645874e5SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT, 3548645874e5SSudarsana Reddy Kalluru 0, &mcp_resp, &p_hwfn->mcp_info->capabilities); 3549645874e5SSudarsana Reddy Kalluru if (!rc) 3550645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE), 3551645874e5SSudarsana Reddy Kalluru "MFW supported features: %08x\n", 3552645874e5SSudarsana Reddy Kalluru p_hwfn->mcp_info->capabilities); 3553645874e5SSudarsana Reddy Kalluru 3554645874e5SSudarsana Reddy Kalluru return rc; 3555645874e5SSudarsana Reddy Kalluru } 3556645874e5SSudarsana Reddy Kalluru 3557645874e5SSudarsana Reddy Kalluru int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3558645874e5SSudarsana Reddy Kalluru { 3559645874e5SSudarsana Reddy Kalluru u32 mcp_resp, mcp_param, features; 3560645874e5SSudarsana Reddy Kalluru 3561e40a826aSSudarsana Reddy Kalluru features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE | 3562e40a826aSSudarsana Reddy Kalluru DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK; 3563645874e5SSudarsana Reddy Kalluru 3564645874e5SSudarsana Reddy Kalluru return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT, 3565645874e5SSudarsana Reddy Kalluru features, &mcp_resp, &mcp_param); 3566645874e5SSudarsana Reddy Kalluru } 3567