1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/stddef.h> 34 #include <linux/pci.h> 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/string.h> 41 #include <linux/module.h> 42 #include <linux/interrupt.h> 43 #include <linux/workqueue.h> 44 #include <linux/ethtool.h> 45 #include <linux/etherdevice.h> 46 #include <linux/vmalloc.h> 47 #include <linux/crash_dump.h> 48 #include <linux/crc32.h> 49 #include <linux/qed/qed_if.h> 50 #include <linux/qed/qed_ll2_if.h> 51 52 #include "qed.h" 53 #include "qed_sriov.h" 54 #include "qed_sp.h" 55 #include "qed_dev_api.h" 56 #include "qed_ll2.h" 57 #include "qed_fcoe.h" 58 #include "qed_iscsi.h" 59 60 #include "qed_mcp.h" 61 #include "qed_hw.h" 62 #include "qed_selftest.h" 63 #include "qed_debug.h" 64 65 #define QED_ROCE_QPS (8192) 66 #define QED_ROCE_DPIS (8) 67 #define QED_RDMA_SRQS QED_ROCE_QPS 68 69 static char version[] = 70 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 71 72 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 73 MODULE_LICENSE("GPL"); 74 MODULE_VERSION(DRV_MODULE_VERSION); 75 76 #define FW_FILE_VERSION \ 77 __stringify(FW_MAJOR_VERSION) "." \ 78 __stringify(FW_MINOR_VERSION) "." \ 79 __stringify(FW_REVISION_VERSION) "." \ 80 __stringify(FW_ENGINEERING_VERSION) 81 82 #define QED_FW_FILE_NAME \ 83 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 84 85 MODULE_FIRMWARE(QED_FW_FILE_NAME); 86 87 static int __init qed_init(void) 88 { 89 pr_info("%s", version); 90 91 return 0; 92 } 93 94 static void __exit qed_cleanup(void) 95 { 96 pr_notice("qed_cleanup called\n"); 97 } 98 99 module_init(qed_init); 100 module_exit(qed_cleanup); 101 102 /* Check if the DMA controller on the machine can properly handle the DMA 103 * addressing required by the device. 104 */ 105 static int qed_set_coherency_mask(struct qed_dev *cdev) 106 { 107 struct device *dev = &cdev->pdev->dev; 108 109 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 110 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 111 DP_NOTICE(cdev, 112 "Can't request 64-bit consistent allocations\n"); 113 return -EIO; 114 } 115 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 116 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 117 return -EIO; 118 } 119 120 return 0; 121 } 122 123 static void qed_free_pci(struct qed_dev *cdev) 124 { 125 struct pci_dev *pdev = cdev->pdev; 126 127 if (cdev->doorbells && cdev->db_size) 128 iounmap(cdev->doorbells); 129 if (cdev->regview) 130 iounmap(cdev->regview); 131 if (atomic_read(&pdev->enable_cnt) == 1) 132 pci_release_regions(pdev); 133 134 pci_disable_device(pdev); 135 } 136 137 #define PCI_REVISION_ID_ERROR_VAL 0xff 138 139 /* Performs PCI initializations as well as initializing PCI-related parameters 140 * in the device structrue. Returns 0 in case of success. 141 */ 142 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 143 { 144 u8 rev_id; 145 int rc; 146 147 cdev->pdev = pdev; 148 149 rc = pci_enable_device(pdev); 150 if (rc) { 151 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 152 goto err0; 153 } 154 155 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 156 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 157 rc = -EIO; 158 goto err1; 159 } 160 161 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 162 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 163 rc = -EIO; 164 goto err1; 165 } 166 167 if (atomic_read(&pdev->enable_cnt) == 1) { 168 rc = pci_request_regions(pdev, "qed"); 169 if (rc) { 170 DP_NOTICE(cdev, 171 "Failed to request PCI memory resources\n"); 172 goto err1; 173 } 174 pci_set_master(pdev); 175 pci_save_state(pdev); 176 } 177 178 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 179 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 180 DP_NOTICE(cdev, 181 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 182 rev_id); 183 rc = -ENODEV; 184 goto err2; 185 } 186 if (!pci_is_pcie(pdev)) { 187 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 188 rc = -EIO; 189 goto err2; 190 } 191 192 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 193 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 194 DP_NOTICE(cdev, "Cannot find power management capability\n"); 195 196 rc = qed_set_coherency_mask(cdev); 197 if (rc) 198 goto err2; 199 200 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 201 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 202 cdev->pci_params.irq = pdev->irq; 203 204 cdev->regview = pci_ioremap_bar(pdev, 0); 205 if (!cdev->regview) { 206 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 207 rc = -ENOMEM; 208 goto err2; 209 } 210 211 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 212 cdev->db_size = pci_resource_len(cdev->pdev, 2); 213 if (!cdev->db_size) { 214 if (IS_PF(cdev)) { 215 DP_NOTICE(cdev, "No Doorbell bar available\n"); 216 return -EINVAL; 217 } else { 218 return 0; 219 } 220 } 221 222 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 223 224 if (!cdev->doorbells) { 225 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 226 return -ENOMEM; 227 } 228 229 return 0; 230 231 err2: 232 pci_release_regions(pdev); 233 err1: 234 pci_disable_device(pdev); 235 err0: 236 return rc; 237 } 238 239 int qed_fill_dev_info(struct qed_dev *cdev, 240 struct qed_dev_info *dev_info) 241 { 242 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 243 struct qed_hw_info *hw_info = &p_hwfn->hw_info; 244 struct qed_tunnel_info *tun = &cdev->tunnel; 245 struct qed_ptt *ptt; 246 247 memset(dev_info, 0, sizeof(struct qed_dev_info)); 248 249 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 250 tun->vxlan.b_mode_enabled) 251 dev_info->vxlan_enable = true; 252 253 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled && 254 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 255 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 256 dev_info->gre_enable = true; 257 258 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled && 259 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 260 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 261 dev_info->geneve_enable = true; 262 263 dev_info->num_hwfns = cdev->num_hwfns; 264 dev_info->pci_mem_start = cdev->pci_params.mem_start; 265 dev_info->pci_mem_end = cdev->pci_params.mem_end; 266 dev_info->pci_irq = cdev->pci_params.irq; 267 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn); 268 dev_info->dev_type = cdev->type; 269 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr); 270 271 if (IS_PF(cdev)) { 272 dev_info->fw_major = FW_MAJOR_VERSION; 273 dev_info->fw_minor = FW_MINOR_VERSION; 274 dev_info->fw_rev = FW_REVISION_VERSION; 275 dev_info->fw_eng = FW_ENGINEERING_VERSION; 276 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH, 277 &cdev->mf_bits); 278 dev_info->tx_switching = true; 279 280 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME) 281 dev_info->wol_support = true; 282 283 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id; 284 } else { 285 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 286 &dev_info->fw_minor, &dev_info->fw_rev, 287 &dev_info->fw_eng); 288 } 289 290 if (IS_PF(cdev)) { 291 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 292 if (ptt) { 293 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 294 &dev_info->mfw_rev, NULL); 295 296 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt, 297 &dev_info->mbi_version); 298 299 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 300 &dev_info->flash_size); 301 302 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 303 } 304 } else { 305 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 306 &dev_info->mfw_rev, NULL); 307 } 308 309 dev_info->mtu = hw_info->mtu; 310 311 return 0; 312 } 313 314 static void qed_free_cdev(struct qed_dev *cdev) 315 { 316 kfree((void *)cdev); 317 } 318 319 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 320 { 321 struct qed_dev *cdev; 322 323 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 324 if (!cdev) 325 return cdev; 326 327 qed_init_struct(cdev); 328 329 return cdev; 330 } 331 332 /* Sets the requested power state */ 333 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 334 { 335 if (!cdev) 336 return -ENODEV; 337 338 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 339 return 0; 340 } 341 342 /* probing */ 343 static struct qed_dev *qed_probe(struct pci_dev *pdev, 344 struct qed_probe_params *params) 345 { 346 struct qed_dev *cdev; 347 int rc; 348 349 cdev = qed_alloc_cdev(pdev); 350 if (!cdev) 351 goto err0; 352 353 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 354 cdev->protocol = params->protocol; 355 356 if (params->is_vf) 357 cdev->b_is_vf = true; 358 359 qed_init_dp(cdev, params->dp_module, params->dp_level); 360 361 rc = qed_init_pci(cdev, pdev); 362 if (rc) { 363 DP_ERR(cdev, "init pci failed\n"); 364 goto err1; 365 } 366 DP_INFO(cdev, "PCI init completed successfully\n"); 367 368 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 369 if (rc) { 370 DP_ERR(cdev, "hw prepare failed\n"); 371 goto err2; 372 } 373 374 DP_INFO(cdev, "qed_probe completed successfully\n"); 375 376 return cdev; 377 378 err2: 379 qed_free_pci(cdev); 380 err1: 381 qed_free_cdev(cdev); 382 err0: 383 return NULL; 384 } 385 386 static void qed_remove(struct qed_dev *cdev) 387 { 388 if (!cdev) 389 return; 390 391 qed_hw_remove(cdev); 392 393 qed_free_pci(cdev); 394 395 qed_set_power_state(cdev, PCI_D3hot); 396 397 qed_free_cdev(cdev); 398 } 399 400 static void qed_disable_msix(struct qed_dev *cdev) 401 { 402 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 403 pci_disable_msix(cdev->pdev); 404 kfree(cdev->int_params.msix_table); 405 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 406 pci_disable_msi(cdev->pdev); 407 } 408 409 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 410 } 411 412 static int qed_enable_msix(struct qed_dev *cdev, 413 struct qed_int_params *int_params) 414 { 415 int i, rc, cnt; 416 417 cnt = int_params->in.num_vectors; 418 419 for (i = 0; i < cnt; i++) 420 int_params->msix_table[i].entry = i; 421 422 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 423 int_params->in.min_msix_cnt, cnt); 424 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 425 (rc % cdev->num_hwfns)) { 426 pci_disable_msix(cdev->pdev); 427 428 /* If fastpath is initialized, we need at least one interrupt 429 * per hwfn [and the slow path interrupts]. New requested number 430 * should be a multiple of the number of hwfns. 431 */ 432 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 433 DP_NOTICE(cdev, 434 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 435 cnt, int_params->in.num_vectors); 436 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 437 cnt); 438 if (!rc) 439 rc = cnt; 440 } 441 442 if (rc > 0) { 443 /* MSI-x configuration was achieved */ 444 int_params->out.int_mode = QED_INT_MODE_MSIX; 445 int_params->out.num_vectors = rc; 446 rc = 0; 447 } else { 448 DP_NOTICE(cdev, 449 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 450 cnt, rc); 451 } 452 453 return rc; 454 } 455 456 /* This function outputs the int mode and the number of enabled msix vector */ 457 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 458 { 459 struct qed_int_params *int_params = &cdev->int_params; 460 struct msix_entry *tbl; 461 int rc = 0, cnt; 462 463 switch (int_params->in.int_mode) { 464 case QED_INT_MODE_MSIX: 465 /* Allocate MSIX table */ 466 cnt = int_params->in.num_vectors; 467 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 468 if (!int_params->msix_table) { 469 rc = -ENOMEM; 470 goto out; 471 } 472 473 /* Enable MSIX */ 474 rc = qed_enable_msix(cdev, int_params); 475 if (!rc) 476 goto out; 477 478 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 479 kfree(int_params->msix_table); 480 if (force_mode) 481 goto out; 482 /* Fallthrough */ 483 484 case QED_INT_MODE_MSI: 485 if (cdev->num_hwfns == 1) { 486 rc = pci_enable_msi(cdev->pdev); 487 if (!rc) { 488 int_params->out.int_mode = QED_INT_MODE_MSI; 489 goto out; 490 } 491 492 DP_NOTICE(cdev, "Failed to enable MSI\n"); 493 if (force_mode) 494 goto out; 495 } 496 /* Fallthrough */ 497 498 case QED_INT_MODE_INTA: 499 int_params->out.int_mode = QED_INT_MODE_INTA; 500 rc = 0; 501 goto out; 502 default: 503 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 504 int_params->in.int_mode); 505 rc = -EINVAL; 506 } 507 508 out: 509 if (!rc) 510 DP_INFO(cdev, "Using %s interrupts\n", 511 int_params->out.int_mode == QED_INT_MODE_INTA ? 512 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 513 "MSI" : "MSIX"); 514 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 515 516 return rc; 517 } 518 519 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 520 int index, void(*handler)(void *)) 521 { 522 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 523 int relative_idx = index / cdev->num_hwfns; 524 525 hwfn->simd_proto_handler[relative_idx].func = handler; 526 hwfn->simd_proto_handler[relative_idx].token = token; 527 } 528 529 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 530 { 531 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 532 int relative_idx = index / cdev->num_hwfns; 533 534 memset(&hwfn->simd_proto_handler[relative_idx], 0, 535 sizeof(struct qed_simd_fp_handler)); 536 } 537 538 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 539 { 540 tasklet_schedule((struct tasklet_struct *)tasklet); 541 return IRQ_HANDLED; 542 } 543 544 static irqreturn_t qed_single_int(int irq, void *dev_instance) 545 { 546 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 547 struct qed_hwfn *hwfn; 548 irqreturn_t rc = IRQ_NONE; 549 u64 status; 550 int i, j; 551 552 for (i = 0; i < cdev->num_hwfns; i++) { 553 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 554 555 if (!status) 556 continue; 557 558 hwfn = &cdev->hwfns[i]; 559 560 /* Slowpath interrupt */ 561 if (unlikely(status & 0x1)) { 562 tasklet_schedule(hwfn->sp_dpc); 563 status &= ~0x1; 564 rc = IRQ_HANDLED; 565 } 566 567 /* Fastpath interrupts */ 568 for (j = 0; j < 64; j++) { 569 if ((0x2ULL << j) & status) { 570 struct qed_simd_fp_handler *p_handler = 571 &hwfn->simd_proto_handler[j]; 572 573 if (p_handler->func) 574 p_handler->func(p_handler->token); 575 else 576 DP_NOTICE(hwfn, 577 "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n", 578 j, status); 579 580 status &= ~(0x2ULL << j); 581 rc = IRQ_HANDLED; 582 } 583 } 584 585 if (unlikely(status)) 586 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 587 "got an unknown interrupt status 0x%llx\n", 588 status); 589 } 590 591 return rc; 592 } 593 594 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 595 { 596 struct qed_dev *cdev = hwfn->cdev; 597 u32 int_mode; 598 int rc = 0; 599 u8 id; 600 601 int_mode = cdev->int_params.out.int_mode; 602 if (int_mode == QED_INT_MODE_MSIX) { 603 id = hwfn->my_id; 604 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 605 id, cdev->pdev->bus->number, 606 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 607 rc = request_irq(cdev->int_params.msix_table[id].vector, 608 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 609 } else { 610 unsigned long flags = 0; 611 612 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 613 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 614 PCI_FUNC(cdev->pdev->devfn)); 615 616 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 617 flags |= IRQF_SHARED; 618 619 rc = request_irq(cdev->pdev->irq, qed_single_int, 620 flags, cdev->name, cdev); 621 } 622 623 if (rc) 624 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 625 else 626 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 627 "Requested slowpath %s\n", 628 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 629 630 return rc; 631 } 632 633 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn) 634 { 635 /* Calling the disable function will make sure that any 636 * currently-running function is completed. The following call to the 637 * enable function makes this sequence a flush-like operation. 638 */ 639 if (p_hwfn->b_sp_dpc_enabled) { 640 tasklet_disable(p_hwfn->sp_dpc); 641 tasklet_enable(p_hwfn->sp_dpc); 642 } 643 } 644 645 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn) 646 { 647 struct qed_dev *cdev = p_hwfn->cdev; 648 u8 id = p_hwfn->my_id; 649 u32 int_mode; 650 651 int_mode = cdev->int_params.out.int_mode; 652 if (int_mode == QED_INT_MODE_MSIX) 653 synchronize_irq(cdev->int_params.msix_table[id].vector); 654 else 655 synchronize_irq(cdev->pdev->irq); 656 657 qed_slowpath_tasklet_flush(p_hwfn); 658 } 659 660 static void qed_slowpath_irq_free(struct qed_dev *cdev) 661 { 662 int i; 663 664 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 665 for_each_hwfn(cdev, i) { 666 if (!cdev->hwfns[i].b_int_requested) 667 break; 668 synchronize_irq(cdev->int_params.msix_table[i].vector); 669 free_irq(cdev->int_params.msix_table[i].vector, 670 cdev->hwfns[i].sp_dpc); 671 } 672 } else { 673 if (QED_LEADING_HWFN(cdev)->b_int_requested) 674 free_irq(cdev->pdev->irq, cdev); 675 } 676 qed_int_disable_post_isr_release(cdev); 677 } 678 679 static int qed_nic_stop(struct qed_dev *cdev) 680 { 681 int i, rc; 682 683 rc = qed_hw_stop(cdev); 684 685 for (i = 0; i < cdev->num_hwfns; i++) { 686 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 687 688 if (p_hwfn->b_sp_dpc_enabled) { 689 tasklet_disable(p_hwfn->sp_dpc); 690 p_hwfn->b_sp_dpc_enabled = false; 691 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 692 "Disabled sp tasklet [hwfn %d] at %p\n", 693 i, p_hwfn->sp_dpc); 694 } 695 } 696 697 qed_dbg_pf_exit(cdev); 698 699 return rc; 700 } 701 702 static int qed_nic_setup(struct qed_dev *cdev) 703 { 704 int rc, i; 705 706 /* Determine if interface is going to require LL2 */ 707 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 708 for (i = 0; i < cdev->num_hwfns; i++) { 709 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 710 711 p_hwfn->using_ll2 = true; 712 } 713 } 714 715 rc = qed_resc_alloc(cdev); 716 if (rc) 717 return rc; 718 719 DP_INFO(cdev, "Allocated qed resources\n"); 720 721 qed_resc_setup(cdev); 722 723 return rc; 724 } 725 726 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 727 { 728 int limit = 0; 729 730 /* Mark the fastpath as free/used */ 731 cdev->int_params.fp_initialized = cnt ? true : false; 732 733 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 734 limit = cdev->num_hwfns * 63; 735 else if (cdev->int_params.fp_msix_cnt) 736 limit = cdev->int_params.fp_msix_cnt; 737 738 if (!limit) 739 return -ENOMEM; 740 741 return min_t(int, cnt, limit); 742 } 743 744 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 745 { 746 memset(info, 0, sizeof(struct qed_int_info)); 747 748 if (!cdev->int_params.fp_initialized) { 749 DP_INFO(cdev, 750 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 751 return -EINVAL; 752 } 753 754 /* Need to expose only MSI-X information; Single IRQ is handled solely 755 * by qed. 756 */ 757 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 758 int msix_base = cdev->int_params.fp_msix_base; 759 760 info->msix_cnt = cdev->int_params.fp_msix_cnt; 761 info->msix = &cdev->int_params.msix_table[msix_base]; 762 } 763 764 return 0; 765 } 766 767 static int qed_slowpath_setup_int(struct qed_dev *cdev, 768 enum qed_int_mode int_mode) 769 { 770 struct qed_sb_cnt_info sb_cnt_info; 771 int num_l2_queues = 0; 772 int rc; 773 int i; 774 775 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 776 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 777 return -EINVAL; 778 } 779 780 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 781 cdev->int_params.in.int_mode = int_mode; 782 for_each_hwfn(cdev, i) { 783 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 784 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 785 cdev->int_params.in.num_vectors += sb_cnt_info.cnt; 786 cdev->int_params.in.num_vectors++; /* slowpath */ 787 } 788 789 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 790 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 791 792 if (is_kdump_kernel()) { 793 DP_INFO(cdev, 794 "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n", 795 cdev->int_params.in.min_msix_cnt); 796 cdev->int_params.in.num_vectors = 797 cdev->int_params.in.min_msix_cnt; 798 } 799 800 rc = qed_set_int_mode(cdev, false); 801 if (rc) { 802 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 803 return rc; 804 } 805 806 cdev->int_params.fp_msix_base = cdev->num_hwfns; 807 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 808 cdev->num_hwfns; 809 810 if (!IS_ENABLED(CONFIG_QED_RDMA) || 811 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) 812 return 0; 813 814 for_each_hwfn(cdev, i) 815 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 816 817 DP_VERBOSE(cdev, QED_MSG_RDMA, 818 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 819 cdev->int_params.fp_msix_cnt, num_l2_queues); 820 821 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 822 cdev->int_params.rdma_msix_cnt = 823 (cdev->int_params.fp_msix_cnt - num_l2_queues) 824 / cdev->num_hwfns; 825 cdev->int_params.rdma_msix_base = 826 cdev->int_params.fp_msix_base + num_l2_queues; 827 cdev->int_params.fp_msix_cnt = num_l2_queues; 828 } else { 829 cdev->int_params.rdma_msix_cnt = 0; 830 } 831 832 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 833 cdev->int_params.rdma_msix_cnt, 834 cdev->int_params.rdma_msix_base); 835 836 return 0; 837 } 838 839 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 840 { 841 int rc; 842 843 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 844 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 845 846 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 847 &cdev->int_params.in.num_vectors); 848 if (cdev->num_hwfns > 1) { 849 u8 vectors = 0; 850 851 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 852 cdev->int_params.in.num_vectors += vectors; 853 } 854 855 /* We want a minimum of one fastpath vector per vf hwfn */ 856 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 857 858 rc = qed_set_int_mode(cdev, true); 859 if (rc) 860 return rc; 861 862 cdev->int_params.fp_msix_base = 0; 863 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 864 865 return 0; 866 } 867 868 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 869 u8 *input_buf, u32 max_size, u8 *unzip_buf) 870 { 871 int rc; 872 873 p_hwfn->stream->next_in = input_buf; 874 p_hwfn->stream->avail_in = input_len; 875 p_hwfn->stream->next_out = unzip_buf; 876 p_hwfn->stream->avail_out = max_size; 877 878 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 879 880 if (rc != Z_OK) { 881 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 882 rc); 883 return 0; 884 } 885 886 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 887 zlib_inflateEnd(p_hwfn->stream); 888 889 if (rc != Z_OK && rc != Z_STREAM_END) { 890 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 891 p_hwfn->stream->msg, rc); 892 return 0; 893 } 894 895 return p_hwfn->stream->total_out / 4; 896 } 897 898 static int qed_alloc_stream_mem(struct qed_dev *cdev) 899 { 900 int i; 901 void *workspace; 902 903 for_each_hwfn(cdev, i) { 904 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 905 906 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 907 if (!p_hwfn->stream) 908 return -ENOMEM; 909 910 workspace = vzalloc(zlib_inflate_workspacesize()); 911 if (!workspace) 912 return -ENOMEM; 913 p_hwfn->stream->workspace = workspace; 914 } 915 916 return 0; 917 } 918 919 static void qed_free_stream_mem(struct qed_dev *cdev) 920 { 921 int i; 922 923 for_each_hwfn(cdev, i) { 924 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 925 926 if (!p_hwfn->stream) 927 return; 928 929 vfree(p_hwfn->stream->workspace); 930 kfree(p_hwfn->stream); 931 } 932 } 933 934 static void qed_update_pf_params(struct qed_dev *cdev, 935 struct qed_pf_params *params) 936 { 937 int i; 938 939 if (IS_ENABLED(CONFIG_QED_RDMA)) { 940 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 941 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 942 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS; 943 /* divide by 3 the MRs to avoid MF ILT overflow */ 944 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 945 } 946 947 if (cdev->num_hwfns > 1 || IS_VF(cdev)) 948 params->eth_pf_params.num_arfs_filters = 0; 949 950 /* In case we might support RDMA, don't allow qede to be greedy 951 * with the L2 contexts. Allow for 64 queues [rx, tx cos, xdp] 952 * per hwfn. 953 */ 954 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) { 955 u16 *num_cons; 956 957 num_cons = ¶ms->eth_pf_params.num_cons; 958 *num_cons = min_t(u16, *num_cons, QED_MAX_L2_CONS); 959 } 960 961 for (i = 0; i < cdev->num_hwfns; i++) { 962 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 963 964 p_hwfn->pf_params = *params; 965 } 966 } 967 968 static void qed_slowpath_wq_stop(struct qed_dev *cdev) 969 { 970 int i; 971 972 if (IS_VF(cdev)) 973 return; 974 975 for_each_hwfn(cdev, i) { 976 if (!cdev->hwfns[i].slowpath_wq) 977 continue; 978 979 flush_workqueue(cdev->hwfns[i].slowpath_wq); 980 destroy_workqueue(cdev->hwfns[i].slowpath_wq); 981 } 982 } 983 984 static void qed_slowpath_task(struct work_struct *work) 985 { 986 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn, 987 slowpath_task.work); 988 struct qed_ptt *ptt = qed_ptt_acquire(hwfn); 989 990 if (!ptt) { 991 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); 992 return; 993 } 994 995 if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ, 996 &hwfn->slowpath_task_flags)) 997 qed_mfw_process_tlv_req(hwfn, ptt); 998 999 qed_ptt_release(hwfn, ptt); 1000 } 1001 1002 static int qed_slowpath_wq_start(struct qed_dev *cdev) 1003 { 1004 struct qed_hwfn *hwfn; 1005 char name[NAME_SIZE]; 1006 int i; 1007 1008 if (IS_VF(cdev)) 1009 return 0; 1010 1011 for_each_hwfn(cdev, i) { 1012 hwfn = &cdev->hwfns[i]; 1013 1014 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x", 1015 cdev->pdev->bus->number, 1016 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 1017 1018 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0); 1019 if (!hwfn->slowpath_wq) { 1020 DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n"); 1021 return -ENOMEM; 1022 } 1023 1024 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task); 1025 } 1026 1027 return 0; 1028 } 1029 1030 static int qed_slowpath_start(struct qed_dev *cdev, 1031 struct qed_slowpath_params *params) 1032 { 1033 struct qed_drv_load_params drv_load_params; 1034 struct qed_hw_init_params hw_init_params; 1035 struct qed_mcp_drv_version drv_version; 1036 struct qed_tunnel_info tunn_info; 1037 const u8 *data = NULL; 1038 struct qed_hwfn *hwfn; 1039 struct qed_ptt *p_ptt; 1040 int rc = -EINVAL; 1041 1042 if (qed_iov_wq_start(cdev)) 1043 goto err; 1044 1045 if (qed_slowpath_wq_start(cdev)) 1046 goto err; 1047 1048 if (IS_PF(cdev)) { 1049 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 1050 &cdev->pdev->dev); 1051 if (rc) { 1052 DP_NOTICE(cdev, 1053 "Failed to find fw file - /lib/firmware/%s\n", 1054 QED_FW_FILE_NAME); 1055 goto err; 1056 } 1057 1058 if (cdev->num_hwfns == 1) { 1059 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 1060 if (p_ptt) { 1061 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt; 1062 } else { 1063 DP_NOTICE(cdev, 1064 "Failed to acquire PTT for aRFS\n"); 1065 goto err; 1066 } 1067 } 1068 } 1069 1070 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; 1071 rc = qed_nic_setup(cdev); 1072 if (rc) 1073 goto err; 1074 1075 if (IS_PF(cdev)) 1076 rc = qed_slowpath_setup_int(cdev, params->int_mode); 1077 else 1078 rc = qed_slowpath_vf_setup_int(cdev); 1079 if (rc) 1080 goto err1; 1081 1082 if (IS_PF(cdev)) { 1083 /* Allocate stream for unzipping */ 1084 rc = qed_alloc_stream_mem(cdev); 1085 if (rc) 1086 goto err2; 1087 1088 /* First Dword used to differentiate between various sources */ 1089 data = cdev->firmware->data + sizeof(u32); 1090 1091 qed_dbg_pf_init(cdev); 1092 } 1093 1094 /* Start the slowpath */ 1095 memset(&hw_init_params, 0, sizeof(hw_init_params)); 1096 memset(&tunn_info, 0, sizeof(tunn_info)); 1097 tunn_info.vxlan.b_mode_enabled = true; 1098 tunn_info.l2_gre.b_mode_enabled = true; 1099 tunn_info.ip_gre.b_mode_enabled = true; 1100 tunn_info.l2_geneve.b_mode_enabled = true; 1101 tunn_info.ip_geneve.b_mode_enabled = true; 1102 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1103 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1104 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1105 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1106 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1107 hw_init_params.p_tunn = &tunn_info; 1108 hw_init_params.b_hw_start = true; 1109 hw_init_params.int_mode = cdev->int_params.out.int_mode; 1110 hw_init_params.allow_npar_tx_switch = true; 1111 hw_init_params.bin_fw_data = data; 1112 1113 memset(&drv_load_params, 0, sizeof(drv_load_params)); 1114 drv_load_params.is_crash_kernel = is_kdump_kernel(); 1115 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT; 1116 drv_load_params.avoid_eng_reset = false; 1117 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE; 1118 hw_init_params.p_drv_load_params = &drv_load_params; 1119 1120 rc = qed_hw_init(cdev, &hw_init_params); 1121 if (rc) 1122 goto err2; 1123 1124 DP_INFO(cdev, 1125 "HW initialization and function start completed successfully\n"); 1126 1127 if (IS_PF(cdev)) { 1128 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) | 1129 BIT(QED_MODE_L2GENEVE_TUNN) | 1130 BIT(QED_MODE_IPGENEVE_TUNN) | 1131 BIT(QED_MODE_L2GRE_TUNN) | 1132 BIT(QED_MODE_IPGRE_TUNN)); 1133 } 1134 1135 /* Allocate LL2 interface if needed */ 1136 if (QED_LEADING_HWFN(cdev)->using_ll2) { 1137 rc = qed_ll2_alloc_if(cdev); 1138 if (rc) 1139 goto err3; 1140 } 1141 if (IS_PF(cdev)) { 1142 hwfn = QED_LEADING_HWFN(cdev); 1143 drv_version.version = (params->drv_major << 24) | 1144 (params->drv_minor << 16) | 1145 (params->drv_rev << 8) | 1146 (params->drv_eng); 1147 strlcpy(drv_version.name, params->name, 1148 MCP_DRV_VER_STR_SIZE - 4); 1149 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 1150 &drv_version); 1151 if (rc) { 1152 DP_NOTICE(cdev, "Failed sending drv version command\n"); 1153 return rc; 1154 } 1155 } 1156 1157 qed_reset_vport_stats(cdev); 1158 1159 return 0; 1160 1161 err3: 1162 qed_hw_stop(cdev); 1163 err2: 1164 qed_hw_timers_stop_all(cdev); 1165 if (IS_PF(cdev)) 1166 qed_slowpath_irq_free(cdev); 1167 qed_free_stream_mem(cdev); 1168 qed_disable_msix(cdev); 1169 err1: 1170 qed_resc_free(cdev); 1171 err: 1172 if (IS_PF(cdev)) 1173 release_firmware(cdev->firmware); 1174 1175 if (IS_PF(cdev) && (cdev->num_hwfns == 1) && 1176 QED_LEADING_HWFN(cdev)->p_arfs_ptt) 1177 qed_ptt_release(QED_LEADING_HWFN(cdev), 1178 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1179 1180 qed_iov_wq_stop(cdev, false); 1181 1182 qed_slowpath_wq_stop(cdev); 1183 1184 return rc; 1185 } 1186 1187 static int qed_slowpath_stop(struct qed_dev *cdev) 1188 { 1189 if (!cdev) 1190 return -ENODEV; 1191 1192 qed_slowpath_wq_stop(cdev); 1193 1194 qed_ll2_dealloc_if(cdev); 1195 1196 if (IS_PF(cdev)) { 1197 if (cdev->num_hwfns == 1) 1198 qed_ptt_release(QED_LEADING_HWFN(cdev), 1199 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1200 qed_free_stream_mem(cdev); 1201 if (IS_QED_ETH_IF(cdev)) 1202 qed_sriov_disable(cdev, true); 1203 } 1204 1205 qed_nic_stop(cdev); 1206 1207 if (IS_PF(cdev)) 1208 qed_slowpath_irq_free(cdev); 1209 1210 qed_disable_msix(cdev); 1211 1212 qed_resc_free(cdev); 1213 1214 qed_iov_wq_stop(cdev, true); 1215 1216 if (IS_PF(cdev)) 1217 release_firmware(cdev->firmware); 1218 1219 return 0; 1220 } 1221 1222 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE]) 1223 { 1224 int i; 1225 1226 memcpy(cdev->name, name, NAME_SIZE); 1227 for_each_hwfn(cdev, i) 1228 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1229 } 1230 1231 static u32 qed_sb_init(struct qed_dev *cdev, 1232 struct qed_sb_info *sb_info, 1233 void *sb_virt_addr, 1234 dma_addr_t sb_phy_addr, u16 sb_id, 1235 enum qed_sb_type type) 1236 { 1237 struct qed_hwfn *p_hwfn; 1238 struct qed_ptt *p_ptt; 1239 int hwfn_index; 1240 u16 rel_sb_id; 1241 u8 n_hwfns; 1242 u32 rc; 1243 1244 /* RoCE uses single engine and CMT uses two engines. When using both 1245 * we force only a single engine. Storage uses only engine 0 too. 1246 */ 1247 if (type == QED_SB_TYPE_L2_QUEUE) 1248 n_hwfns = cdev->num_hwfns; 1249 else 1250 n_hwfns = 1; 1251 1252 hwfn_index = sb_id % n_hwfns; 1253 p_hwfn = &cdev->hwfns[hwfn_index]; 1254 rel_sb_id = sb_id / n_hwfns; 1255 1256 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1257 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1258 hwfn_index, rel_sb_id, sb_id); 1259 1260 if (IS_PF(p_hwfn->cdev)) { 1261 p_ptt = qed_ptt_acquire(p_hwfn); 1262 if (!p_ptt) 1263 return -EBUSY; 1264 1265 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr, 1266 sb_phy_addr, rel_sb_id); 1267 qed_ptt_release(p_hwfn, p_ptt); 1268 } else { 1269 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr, 1270 sb_phy_addr, rel_sb_id); 1271 } 1272 1273 return rc; 1274 } 1275 1276 static u32 qed_sb_release(struct qed_dev *cdev, 1277 struct qed_sb_info *sb_info, u16 sb_id) 1278 { 1279 struct qed_hwfn *p_hwfn; 1280 int hwfn_index; 1281 u16 rel_sb_id; 1282 u32 rc; 1283 1284 hwfn_index = sb_id % cdev->num_hwfns; 1285 p_hwfn = &cdev->hwfns[hwfn_index]; 1286 rel_sb_id = sb_id / cdev->num_hwfns; 1287 1288 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1289 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1290 hwfn_index, rel_sb_id, sb_id); 1291 1292 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1293 1294 return rc; 1295 } 1296 1297 static bool qed_can_link_change(struct qed_dev *cdev) 1298 { 1299 return true; 1300 } 1301 1302 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1303 { 1304 struct qed_hwfn *hwfn; 1305 struct qed_mcp_link_params *link_params; 1306 struct qed_ptt *ptt; 1307 int rc; 1308 1309 if (!cdev) 1310 return -ENODEV; 1311 1312 /* The link should be set only once per PF */ 1313 hwfn = &cdev->hwfns[0]; 1314 1315 /* When VF wants to set link, force it to read the bulletin instead. 1316 * This mimics the PF behavior, where a noitification [both immediate 1317 * and possible later] would be generated when changing properties. 1318 */ 1319 if (IS_VF(cdev)) { 1320 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG); 1321 return 0; 1322 } 1323 1324 ptt = qed_ptt_acquire(hwfn); 1325 if (!ptt) 1326 return -EBUSY; 1327 1328 link_params = qed_mcp_get_link_params(hwfn); 1329 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1330 link_params->speed.autoneg = params->autoneg; 1331 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1332 link_params->speed.advertised_speeds = 0; 1333 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1334 (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1335 link_params->speed.advertised_speeds |= 1336 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1337 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1338 link_params->speed.advertised_speeds |= 1339 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1340 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1341 link_params->speed.advertised_speeds |= 1342 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1343 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1344 link_params->speed.advertised_speeds |= 1345 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1346 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1347 link_params->speed.advertised_speeds |= 1348 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1349 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1350 link_params->speed.advertised_speeds |= 1351 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1352 } 1353 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1354 link_params->speed.forced_speed = params->forced_speed; 1355 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1356 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1357 link_params->pause.autoneg = true; 1358 else 1359 link_params->pause.autoneg = false; 1360 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1361 link_params->pause.forced_rx = true; 1362 else 1363 link_params->pause.forced_rx = false; 1364 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1365 link_params->pause.forced_tx = true; 1366 else 1367 link_params->pause.forced_tx = false; 1368 } 1369 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1370 switch (params->loopback_mode) { 1371 case QED_LINK_LOOPBACK_INT_PHY: 1372 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1373 break; 1374 case QED_LINK_LOOPBACK_EXT_PHY: 1375 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1376 break; 1377 case QED_LINK_LOOPBACK_EXT: 1378 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1379 break; 1380 case QED_LINK_LOOPBACK_MAC: 1381 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1382 break; 1383 default: 1384 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1385 break; 1386 } 1387 } 1388 1389 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG) 1390 memcpy(&link_params->eee, ¶ms->eee, 1391 sizeof(link_params->eee)); 1392 1393 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1394 1395 qed_ptt_release(hwfn, ptt); 1396 1397 return rc; 1398 } 1399 1400 static int qed_get_port_type(u32 media_type) 1401 { 1402 int port_type; 1403 1404 switch (media_type) { 1405 case MEDIA_SFPP_10G_FIBER: 1406 case MEDIA_SFP_1G_FIBER: 1407 case MEDIA_XFP_FIBER: 1408 case MEDIA_MODULE_FIBER: 1409 case MEDIA_KR: 1410 port_type = PORT_FIBRE; 1411 break; 1412 case MEDIA_DA_TWINAX: 1413 port_type = PORT_DA; 1414 break; 1415 case MEDIA_BASE_T: 1416 port_type = PORT_TP; 1417 break; 1418 case MEDIA_NOT_PRESENT: 1419 port_type = PORT_NONE; 1420 break; 1421 case MEDIA_UNSPECIFIED: 1422 default: 1423 port_type = PORT_OTHER; 1424 break; 1425 } 1426 return port_type; 1427 } 1428 1429 static int qed_get_link_data(struct qed_hwfn *hwfn, 1430 struct qed_mcp_link_params *params, 1431 struct qed_mcp_link_state *link, 1432 struct qed_mcp_link_capabilities *link_caps) 1433 { 1434 void *p; 1435 1436 if (!IS_PF(hwfn->cdev)) { 1437 qed_vf_get_link_params(hwfn, params); 1438 qed_vf_get_link_state(hwfn, link); 1439 qed_vf_get_link_caps(hwfn, link_caps); 1440 1441 return 0; 1442 } 1443 1444 p = qed_mcp_get_link_params(hwfn); 1445 if (!p) 1446 return -ENXIO; 1447 memcpy(params, p, sizeof(*params)); 1448 1449 p = qed_mcp_get_link_state(hwfn); 1450 if (!p) 1451 return -ENXIO; 1452 memcpy(link, p, sizeof(*link)); 1453 1454 p = qed_mcp_get_link_capabilities(hwfn); 1455 if (!p) 1456 return -ENXIO; 1457 memcpy(link_caps, p, sizeof(*link_caps)); 1458 1459 return 0; 1460 } 1461 1462 static void qed_fill_link(struct qed_hwfn *hwfn, 1463 struct qed_link_output *if_link) 1464 { 1465 struct qed_mcp_link_params params; 1466 struct qed_mcp_link_state link; 1467 struct qed_mcp_link_capabilities link_caps; 1468 u32 media_type; 1469 1470 memset(if_link, 0, sizeof(*if_link)); 1471 1472 /* Prepare source inputs */ 1473 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1474 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1475 return; 1476 } 1477 1478 /* Set the link parameters to pass to protocol driver */ 1479 if (link.link_up) 1480 if_link->link_up = true; 1481 1482 /* TODO - at the moment assume supported and advertised speed equal */ 1483 if_link->supported_caps = QED_LM_FIBRE_BIT; 1484 if (link_caps.default_speed_autoneg) 1485 if_link->supported_caps |= QED_LM_Autoneg_BIT; 1486 if (params.pause.autoneg || 1487 (params.pause.forced_rx && params.pause.forced_tx)) 1488 if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1489 if (params.pause.autoneg || params.pause.forced_rx || 1490 params.pause.forced_tx) 1491 if_link->supported_caps |= QED_LM_Pause_BIT; 1492 1493 if_link->advertised_caps = if_link->supported_caps; 1494 if (params.speed.autoneg) 1495 if_link->advertised_caps |= QED_LM_Autoneg_BIT; 1496 else 1497 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT; 1498 if (params.speed.advertised_speeds & 1499 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1500 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1501 QED_LM_1000baseT_Full_BIT; 1502 if (params.speed.advertised_speeds & 1503 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1504 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1505 if (params.speed.advertised_speeds & 1506 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1507 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1508 if (params.speed.advertised_speeds & 1509 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1510 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1511 if (params.speed.advertised_speeds & 1512 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1513 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1514 if (params.speed.advertised_speeds & 1515 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1516 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1517 1518 if (link_caps.speed_capabilities & 1519 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1520 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1521 QED_LM_1000baseT_Full_BIT; 1522 if (link_caps.speed_capabilities & 1523 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1524 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1525 if (link_caps.speed_capabilities & 1526 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1527 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1528 if (link_caps.speed_capabilities & 1529 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1530 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1531 if (link_caps.speed_capabilities & 1532 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1533 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1534 if (link_caps.speed_capabilities & 1535 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1536 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1537 1538 if (link.link_up) 1539 if_link->speed = link.speed; 1540 1541 /* TODO - fill duplex properly */ 1542 if_link->duplex = DUPLEX_FULL; 1543 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1544 if_link->port = qed_get_port_type(media_type); 1545 1546 if_link->autoneg = params.speed.autoneg; 1547 1548 if (params.pause.autoneg) 1549 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1550 if (params.pause.forced_rx) 1551 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1552 if (params.pause.forced_tx) 1553 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1554 1555 /* Link partner capabilities */ 1556 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1557 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1558 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1559 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1560 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1561 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1562 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1563 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1564 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1565 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1566 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1567 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1568 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1569 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1570 1571 if (link.an_complete) 1572 if_link->lp_caps |= QED_LM_Autoneg_BIT; 1573 1574 if (link.partner_adv_pause) 1575 if_link->lp_caps |= QED_LM_Pause_BIT; 1576 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1577 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1578 if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1579 1580 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) { 1581 if_link->eee_supported = false; 1582 } else { 1583 if_link->eee_supported = true; 1584 if_link->eee_active = link.eee_active; 1585 if_link->sup_caps = link_caps.eee_speed_caps; 1586 /* MFW clears adv_caps on eee disable; use configured value */ 1587 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps : 1588 params.eee.adv_caps; 1589 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps; 1590 if_link->eee.enable = params.eee.enable; 1591 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable; 1592 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer; 1593 } 1594 } 1595 1596 static void qed_get_current_link(struct qed_dev *cdev, 1597 struct qed_link_output *if_link) 1598 { 1599 int i; 1600 1601 qed_fill_link(&cdev->hwfns[0], if_link); 1602 1603 for_each_hwfn(cdev, i) 1604 qed_inform_vf_link_state(&cdev->hwfns[i]); 1605 } 1606 1607 void qed_link_update(struct qed_hwfn *hwfn) 1608 { 1609 void *cookie = hwfn->cdev->ops_cookie; 1610 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1611 struct qed_link_output if_link; 1612 1613 qed_fill_link(hwfn, &if_link); 1614 qed_inform_vf_link_state(hwfn); 1615 1616 if (IS_LEAD_HWFN(hwfn) && cookie) 1617 op->link_update(cookie, &if_link); 1618 } 1619 1620 static int qed_drain(struct qed_dev *cdev) 1621 { 1622 struct qed_hwfn *hwfn; 1623 struct qed_ptt *ptt; 1624 int i, rc; 1625 1626 if (IS_VF(cdev)) 1627 return 0; 1628 1629 for_each_hwfn(cdev, i) { 1630 hwfn = &cdev->hwfns[i]; 1631 ptt = qed_ptt_acquire(hwfn); 1632 if (!ptt) { 1633 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1634 return -EBUSY; 1635 } 1636 rc = qed_mcp_drain(hwfn, ptt); 1637 if (rc) 1638 return rc; 1639 qed_ptt_release(hwfn, ptt); 1640 } 1641 1642 return 0; 1643 } 1644 1645 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev, 1646 struct qed_nvm_image_att *nvm_image, 1647 u32 *crc) 1648 { 1649 u8 *buf = NULL; 1650 int rc, j; 1651 u32 val; 1652 1653 /* Allocate a buffer for holding the nvram image */ 1654 buf = kzalloc(nvm_image->length, GFP_KERNEL); 1655 if (!buf) 1656 return -ENOMEM; 1657 1658 /* Read image into buffer */ 1659 rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr, 1660 buf, nvm_image->length); 1661 if (rc) { 1662 DP_ERR(cdev, "Failed reading image from nvm\n"); 1663 goto out; 1664 } 1665 1666 /* Convert the buffer into big-endian format (excluding the 1667 * closing 4 bytes of CRC). 1668 */ 1669 for (j = 0; j < nvm_image->length - 4; j += 4) { 1670 val = cpu_to_be32(*(u32 *)&buf[j]); 1671 *(u32 *)&buf[j] = val; 1672 } 1673 1674 /* Calc CRC for the "actual" image buffer, i.e. not including 1675 * the last 4 CRC bytes. 1676 */ 1677 *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4))); 1678 1679 out: 1680 kfree(buf); 1681 1682 return rc; 1683 } 1684 1685 /* Binary file format - 1686 * /----------------------------------------------------------------------\ 1687 * 0B | 0x4 [command index] | 1688 * 4B | image_type | Options | Number of register settings | 1689 * 8B | Value | 1690 * 12B | Mask | 1691 * 16B | Offset | 1692 * \----------------------------------------------------------------------/ 1693 * There can be several Value-Mask-Offset sets as specified by 'Number of...'. 1694 * Options - 0'b - Calculate & Update CRC for image 1695 */ 1696 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data, 1697 bool *check_resp) 1698 { 1699 struct qed_nvm_image_att nvm_image; 1700 struct qed_hwfn *p_hwfn; 1701 bool is_crc = false; 1702 u32 image_type; 1703 int rc = 0, i; 1704 u16 len; 1705 1706 *data += 4; 1707 image_type = **data; 1708 p_hwfn = QED_LEADING_HWFN(cdev); 1709 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 1710 if (image_type == p_hwfn->nvm_info.image_att[i].image_type) 1711 break; 1712 if (i == p_hwfn->nvm_info.num_images) { 1713 DP_ERR(cdev, "Failed to find nvram image of type %08x\n", 1714 image_type); 1715 return -ENOENT; 1716 } 1717 1718 nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 1719 nvm_image.length = p_hwfn->nvm_info.image_att[i].len; 1720 1721 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1722 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n", 1723 **data, image_type, nvm_image.start_addr, 1724 nvm_image.start_addr + nvm_image.length - 1); 1725 (*data)++; 1726 is_crc = !!(**data & BIT(0)); 1727 (*data)++; 1728 len = *((u16 *)*data); 1729 *data += 2; 1730 if (is_crc) { 1731 u32 crc = 0; 1732 1733 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc); 1734 if (rc) { 1735 DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc); 1736 goto exit; 1737 } 1738 1739 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1740 (nvm_image.start_addr + 1741 nvm_image.length - 4), (u8 *)&crc, 4); 1742 if (rc) 1743 DP_ERR(cdev, "Failed writing to %08x, rc = %d\n", 1744 nvm_image.start_addr + nvm_image.length - 4, rc); 1745 goto exit; 1746 } 1747 1748 /* Iterate over the values for setting */ 1749 while (len) { 1750 u32 offset, mask, value, cur_value; 1751 u8 buf[4]; 1752 1753 value = *((u32 *)*data); 1754 *data += 4; 1755 mask = *((u32 *)*data); 1756 *data += 4; 1757 offset = *((u32 *)*data); 1758 *data += 4; 1759 1760 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf, 1761 4); 1762 if (rc) { 1763 DP_ERR(cdev, "Failed reading from %08x\n", 1764 nvm_image.start_addr + offset); 1765 goto exit; 1766 } 1767 1768 cur_value = le32_to_cpu(*((__le32 *)buf)); 1769 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1770 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n", 1771 nvm_image.start_addr + offset, cur_value, 1772 (cur_value & ~mask) | (value & mask), value, mask); 1773 value = (value & mask) | (cur_value & ~mask); 1774 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1775 nvm_image.start_addr + offset, 1776 (u8 *)&value, 4); 1777 if (rc) { 1778 DP_ERR(cdev, "Failed writing to %08x\n", 1779 nvm_image.start_addr + offset); 1780 goto exit; 1781 } 1782 1783 len--; 1784 } 1785 exit: 1786 return rc; 1787 } 1788 1789 /* Binary file format - 1790 * /----------------------------------------------------------------------\ 1791 * 0B | 0x3 [command index] | 1792 * 4B | b'0: check_response? | b'1-31 reserved | 1793 * 8B | File-type | reserved | 1794 * \----------------------------------------------------------------------/ 1795 * Start a new file of the provided type 1796 */ 1797 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev, 1798 const u8 **data, bool *check_resp) 1799 { 1800 int rc; 1801 1802 *data += 4; 1803 *check_resp = !!(**data & BIT(0)); 1804 *data += 4; 1805 1806 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1807 "About to start a new file of type %02x\n", **data); 1808 rc = qed_mcp_nvm_put_file_begin(cdev, **data); 1809 *data += 4; 1810 1811 return rc; 1812 } 1813 1814 /* Binary file format - 1815 * /----------------------------------------------------------------------\ 1816 * 0B | 0x2 [command index] | 1817 * 4B | Length in bytes | 1818 * 8B | b'0: check_response? | b'1-31 reserved | 1819 * 12B | Offset in bytes | 1820 * 16B | Data ... | 1821 * \----------------------------------------------------------------------/ 1822 * Write data as part of a file that was previously started. Data should be 1823 * of length equal to that provided in the message 1824 */ 1825 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev, 1826 const u8 **data, bool *check_resp) 1827 { 1828 u32 offset, len; 1829 int rc; 1830 1831 *data += 4; 1832 len = *((u32 *)(*data)); 1833 *data += 4; 1834 *check_resp = !!(**data & BIT(0)); 1835 *data += 4; 1836 offset = *((u32 *)(*data)); 1837 *data += 4; 1838 1839 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1840 "About to write File-data: %08x bytes to offset %08x\n", 1841 len, offset); 1842 1843 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset, 1844 (char *)(*data), len); 1845 *data += len; 1846 1847 return rc; 1848 } 1849 1850 /* Binary file format [General header] - 1851 * /----------------------------------------------------------------------\ 1852 * 0B | QED_NVM_SIGNATURE | 1853 * 4B | Length in bytes | 1854 * 8B | Highest command in this batchfile | Reserved | 1855 * \----------------------------------------------------------------------/ 1856 */ 1857 static int qed_nvm_flash_image_validate(struct qed_dev *cdev, 1858 const struct firmware *image, 1859 const u8 **data) 1860 { 1861 u32 signature, len; 1862 1863 /* Check minimum size */ 1864 if (image->size < 12) { 1865 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size); 1866 return -EINVAL; 1867 } 1868 1869 /* Check signature */ 1870 signature = *((u32 *)(*data)); 1871 if (signature != QED_NVM_SIGNATURE) { 1872 DP_ERR(cdev, "Wrong signature '%08x'\n", signature); 1873 return -EINVAL; 1874 } 1875 1876 *data += 4; 1877 /* Validate internal size equals the image-size */ 1878 len = *((u32 *)(*data)); 1879 if (len != image->size) { 1880 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n", 1881 len, (u32)image->size); 1882 return -EINVAL; 1883 } 1884 1885 *data += 4; 1886 /* Make sure driver familiar with all commands necessary for this */ 1887 if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) { 1888 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n", 1889 *((u16 *)(*data))); 1890 return -EINVAL; 1891 } 1892 1893 *data += 4; 1894 1895 return 0; 1896 } 1897 1898 static int qed_nvm_flash(struct qed_dev *cdev, const char *name) 1899 { 1900 const struct firmware *image; 1901 const u8 *data, *data_end; 1902 u32 cmd_type; 1903 int rc; 1904 1905 rc = request_firmware(&image, name, &cdev->pdev->dev); 1906 if (rc) { 1907 DP_ERR(cdev, "Failed to find '%s'\n", name); 1908 return rc; 1909 } 1910 1911 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1912 "Flashing '%s' - firmware's data at %p, size is %08x\n", 1913 name, image->data, (u32)image->size); 1914 data = image->data; 1915 data_end = data + image->size; 1916 1917 rc = qed_nvm_flash_image_validate(cdev, image, &data); 1918 if (rc) 1919 goto exit; 1920 1921 while (data < data_end) { 1922 bool check_resp = false; 1923 1924 /* Parse the actual command */ 1925 cmd_type = *((u32 *)data); 1926 switch (cmd_type) { 1927 case QED_NVM_FLASH_CMD_FILE_DATA: 1928 rc = qed_nvm_flash_image_file_data(cdev, &data, 1929 &check_resp); 1930 break; 1931 case QED_NVM_FLASH_CMD_FILE_START: 1932 rc = qed_nvm_flash_image_file_start(cdev, &data, 1933 &check_resp); 1934 break; 1935 case QED_NVM_FLASH_CMD_NVM_CHANGE: 1936 rc = qed_nvm_flash_image_access(cdev, &data, 1937 &check_resp); 1938 break; 1939 default: 1940 DP_ERR(cdev, "Unknown command %08x\n", cmd_type); 1941 rc = -EINVAL; 1942 goto exit; 1943 } 1944 1945 if (rc) { 1946 DP_ERR(cdev, "Command %08x failed\n", cmd_type); 1947 goto exit; 1948 } 1949 1950 /* Check response if needed */ 1951 if (check_resp) { 1952 u32 mcp_response = 0; 1953 1954 if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) { 1955 DP_ERR(cdev, "Failed getting MCP response\n"); 1956 rc = -EINVAL; 1957 goto exit; 1958 } 1959 1960 switch (mcp_response & FW_MSG_CODE_MASK) { 1961 case FW_MSG_CODE_OK: 1962 case FW_MSG_CODE_NVM_OK: 1963 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK: 1964 case FW_MSG_CODE_PHY_OK: 1965 break; 1966 default: 1967 DP_ERR(cdev, "MFW returns error: %08x\n", 1968 mcp_response); 1969 rc = -EINVAL; 1970 goto exit; 1971 } 1972 } 1973 } 1974 1975 exit: 1976 release_firmware(image); 1977 1978 return rc; 1979 } 1980 1981 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, 1982 u8 *buf, u16 len) 1983 { 1984 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1985 1986 return qed_mcp_get_nvm_image(hwfn, type, buf, len); 1987 } 1988 1989 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1990 void *handle) 1991 { 1992 return qed_set_queue_coalesce(rx_coal, tx_coal, handle); 1993 } 1994 1995 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1996 { 1997 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1998 struct qed_ptt *ptt; 1999 int status = 0; 2000 2001 ptt = qed_ptt_acquire(hwfn); 2002 if (!ptt) 2003 return -EAGAIN; 2004 2005 status = qed_mcp_set_led(hwfn, ptt, mode); 2006 2007 qed_ptt_release(hwfn, ptt); 2008 2009 return status; 2010 } 2011 2012 static int qed_update_wol(struct qed_dev *cdev, bool enabled) 2013 { 2014 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2015 struct qed_ptt *ptt; 2016 int rc = 0; 2017 2018 if (IS_VF(cdev)) 2019 return 0; 2020 2021 ptt = qed_ptt_acquire(hwfn); 2022 if (!ptt) 2023 return -EAGAIN; 2024 2025 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED 2026 : QED_OV_WOL_DISABLED); 2027 if (rc) 2028 goto out; 2029 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2030 2031 out: 2032 qed_ptt_release(hwfn, ptt); 2033 return rc; 2034 } 2035 2036 static int qed_update_drv_state(struct qed_dev *cdev, bool active) 2037 { 2038 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2039 struct qed_ptt *ptt; 2040 int status = 0; 2041 2042 if (IS_VF(cdev)) 2043 return 0; 2044 2045 ptt = qed_ptt_acquire(hwfn); 2046 if (!ptt) 2047 return -EAGAIN; 2048 2049 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ? 2050 QED_OV_DRIVER_STATE_ACTIVE : 2051 QED_OV_DRIVER_STATE_DISABLED); 2052 2053 qed_ptt_release(hwfn, ptt); 2054 2055 return status; 2056 } 2057 2058 static int qed_update_mac(struct qed_dev *cdev, u8 *mac) 2059 { 2060 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2061 struct qed_ptt *ptt; 2062 int status = 0; 2063 2064 if (IS_VF(cdev)) 2065 return 0; 2066 2067 ptt = qed_ptt_acquire(hwfn); 2068 if (!ptt) 2069 return -EAGAIN; 2070 2071 status = qed_mcp_ov_update_mac(hwfn, ptt, mac); 2072 if (status) 2073 goto out; 2074 2075 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2076 2077 out: 2078 qed_ptt_release(hwfn, ptt); 2079 return status; 2080 } 2081 2082 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) 2083 { 2084 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2085 struct qed_ptt *ptt; 2086 int status = 0; 2087 2088 if (IS_VF(cdev)) 2089 return 0; 2090 2091 ptt = qed_ptt_acquire(hwfn); 2092 if (!ptt) 2093 return -EAGAIN; 2094 2095 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu); 2096 if (status) 2097 goto out; 2098 2099 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2100 2101 out: 2102 qed_ptt_release(hwfn, ptt); 2103 return status; 2104 } 2105 2106 static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf, 2107 u8 dev_addr, u32 offset, u32 len) 2108 { 2109 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2110 struct qed_ptt *ptt; 2111 int rc = 0; 2112 2113 if (IS_VF(cdev)) 2114 return 0; 2115 2116 ptt = qed_ptt_acquire(hwfn); 2117 if (!ptt) 2118 return -EAGAIN; 2119 2120 rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr, 2121 offset, len, buf); 2122 2123 qed_ptt_release(hwfn, ptt); 2124 2125 return rc; 2126 } 2127 2128 static struct qed_selftest_ops qed_selftest_ops_pass = { 2129 .selftest_memory = &qed_selftest_memory, 2130 .selftest_interrupt = &qed_selftest_interrupt, 2131 .selftest_register = &qed_selftest_register, 2132 .selftest_clock = &qed_selftest_clock, 2133 .selftest_nvram = &qed_selftest_nvram, 2134 }; 2135 2136 const struct qed_common_ops qed_common_ops_pass = { 2137 .selftest = &qed_selftest_ops_pass, 2138 .probe = &qed_probe, 2139 .remove = &qed_remove, 2140 .set_power_state = &qed_set_power_state, 2141 .set_name = &qed_set_name, 2142 .update_pf_params = &qed_update_pf_params, 2143 .slowpath_start = &qed_slowpath_start, 2144 .slowpath_stop = &qed_slowpath_stop, 2145 .set_fp_int = &qed_set_int_fp, 2146 .get_fp_int = &qed_get_int_fp, 2147 .sb_init = &qed_sb_init, 2148 .sb_release = &qed_sb_release, 2149 .simd_handler_config = &qed_simd_handler_config, 2150 .simd_handler_clean = &qed_simd_handler_clean, 2151 .dbg_grc = &qed_dbg_grc, 2152 .dbg_grc_size = &qed_dbg_grc_size, 2153 .can_link_change = &qed_can_link_change, 2154 .set_link = &qed_set_link, 2155 .get_link = &qed_get_current_link, 2156 .drain = &qed_drain, 2157 .update_msglvl = &qed_init_dp, 2158 .dbg_all_data = &qed_dbg_all_data, 2159 .dbg_all_data_size = &qed_dbg_all_data_size, 2160 .chain_alloc = &qed_chain_alloc, 2161 .chain_free = &qed_chain_free, 2162 .nvm_flash = &qed_nvm_flash, 2163 .nvm_get_image = &qed_nvm_get_image, 2164 .set_coalesce = &qed_set_coalesce, 2165 .set_led = &qed_set_led, 2166 .update_drv_state = &qed_update_drv_state, 2167 .update_mac = &qed_update_mac, 2168 .update_mtu = &qed_update_mtu, 2169 .update_wol = &qed_update_wol, 2170 .read_module_eeprom = &qed_read_module_eeprom, 2171 }; 2172 2173 void qed_get_protocol_stats(struct qed_dev *cdev, 2174 enum qed_mcp_protocol_type type, 2175 union qed_mcp_protocol_stats *stats) 2176 { 2177 struct qed_eth_stats eth_stats; 2178 2179 memset(stats, 0, sizeof(*stats)); 2180 2181 switch (type) { 2182 case QED_MCP_LAN_STATS: 2183 qed_get_vport_stats(cdev, ð_stats); 2184 stats->lan_stats.ucast_rx_pkts = 2185 eth_stats.common.rx_ucast_pkts; 2186 stats->lan_stats.ucast_tx_pkts = 2187 eth_stats.common.tx_ucast_pkts; 2188 stats->lan_stats.fcs_err = -1; 2189 break; 2190 case QED_MCP_FCOE_STATS: 2191 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats); 2192 break; 2193 case QED_MCP_ISCSI_STATS: 2194 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats); 2195 break; 2196 default: 2197 DP_VERBOSE(cdev, QED_MSG_SP, 2198 "Invalid protocol type = %d\n", type); 2199 return; 2200 } 2201 } 2202 2203 int qed_mfw_tlv_req(struct qed_hwfn *hwfn) 2204 { 2205 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV, 2206 "Scheduling slowpath task [Flag: %d]\n", 2207 QED_SLOWPATH_MFW_TLV_REQ); 2208 smp_mb__before_atomic(); 2209 set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags); 2210 smp_mb__after_atomic(); 2211 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); 2212 2213 return 0; 2214 } 2215 2216 static void 2217 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv) 2218 { 2219 struct qed_common_cb_ops *op = cdev->protocol_ops.common; 2220 struct qed_eth_stats_common *p_common; 2221 struct qed_generic_tlvs gen_tlvs; 2222 struct qed_eth_stats stats; 2223 int i; 2224 2225 memset(&gen_tlvs, 0, sizeof(gen_tlvs)); 2226 op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs); 2227 2228 if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM) 2229 tlv->flags.ipv4_csum_offload = true; 2230 if (gen_tlvs.feat_flags & QED_TLV_LSO) 2231 tlv->flags.lso_supported = true; 2232 tlv->flags.b_set = true; 2233 2234 for (i = 0; i < QED_TLV_MAC_COUNT; i++) { 2235 if (is_valid_ether_addr(gen_tlvs.mac[i])) { 2236 ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]); 2237 tlv->mac_set[i] = true; 2238 } 2239 } 2240 2241 qed_get_vport_stats(cdev, &stats); 2242 p_common = &stats.common; 2243 tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts + 2244 p_common->rx_bcast_pkts; 2245 tlv->rx_frames_set = true; 2246 tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes + 2247 p_common->rx_bcast_bytes; 2248 tlv->rx_bytes_set = true; 2249 tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts + 2250 p_common->tx_bcast_pkts; 2251 tlv->tx_frames_set = true; 2252 tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes + 2253 p_common->tx_bcast_bytes; 2254 tlv->rx_bytes_set = true; 2255 } 2256 2257 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type, 2258 union qed_mfw_tlv_data *tlv_buf) 2259 { 2260 struct qed_dev *cdev = hwfn->cdev; 2261 struct qed_common_cb_ops *ops; 2262 2263 ops = cdev->protocol_ops.common; 2264 if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) { 2265 DP_NOTICE(hwfn, "Can't collect TLV management info\n"); 2266 return -EINVAL; 2267 } 2268 2269 switch (type) { 2270 case QED_MFW_TLV_GENERIC: 2271 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic); 2272 break; 2273 case QED_MFW_TLV_ETH: 2274 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth); 2275 break; 2276 case QED_MFW_TLV_FCOE: 2277 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe); 2278 break; 2279 case QED_MFW_TLV_ISCSI: 2280 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi); 2281 break; 2282 default: 2283 break; 2284 } 2285 2286 return 0; 2287 } 2288