1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/stddef.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/version.h> 14 #include <linux/delay.h> 15 #include <asm/byteorder.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/string.h> 18 #include <linux/module.h> 19 #include <linux/interrupt.h> 20 #include <linux/workqueue.h> 21 #include <linux/ethtool.h> 22 #include <linux/etherdevice.h> 23 #include <linux/vmalloc.h> 24 #include <linux/qed/qed_if.h> 25 #include <linux/qed/qed_ll2_if.h> 26 27 #include "qed.h" 28 #include "qed_sriov.h" 29 #include "qed_sp.h" 30 #include "qed_dev_api.h" 31 #include "qed_ll2.h" 32 #include "qed_mcp.h" 33 #include "qed_hw.h" 34 #include "qed_selftest.h" 35 36 #if IS_ENABLED(CONFIG_INFINIBAND_QEDR) 37 #define QED_ROCE_QPS (8192) 38 #define QED_ROCE_DPIS (8) 39 #endif 40 41 static char version[] = 42 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 43 44 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 45 MODULE_LICENSE("GPL"); 46 MODULE_VERSION(DRV_MODULE_VERSION); 47 48 #define FW_FILE_VERSION \ 49 __stringify(FW_MAJOR_VERSION) "." \ 50 __stringify(FW_MINOR_VERSION) "." \ 51 __stringify(FW_REVISION_VERSION) "." \ 52 __stringify(FW_ENGINEERING_VERSION) 53 54 #define QED_FW_FILE_NAME \ 55 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 56 57 MODULE_FIRMWARE(QED_FW_FILE_NAME); 58 59 static int __init qed_init(void) 60 { 61 pr_info("%s", version); 62 63 return 0; 64 } 65 66 static void __exit qed_cleanup(void) 67 { 68 pr_notice("qed_cleanup called\n"); 69 } 70 71 module_init(qed_init); 72 module_exit(qed_cleanup); 73 74 /* Check if the DMA controller on the machine can properly handle the DMA 75 * addressing required by the device. 76 */ 77 static int qed_set_coherency_mask(struct qed_dev *cdev) 78 { 79 struct device *dev = &cdev->pdev->dev; 80 81 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 82 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 83 DP_NOTICE(cdev, 84 "Can't request 64-bit consistent allocations\n"); 85 return -EIO; 86 } 87 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 88 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 89 return -EIO; 90 } 91 92 return 0; 93 } 94 95 static void qed_free_pci(struct qed_dev *cdev) 96 { 97 struct pci_dev *pdev = cdev->pdev; 98 99 if (cdev->doorbells) 100 iounmap(cdev->doorbells); 101 if (cdev->regview) 102 iounmap(cdev->regview); 103 if (atomic_read(&pdev->enable_cnt) == 1) 104 pci_release_regions(pdev); 105 106 pci_disable_device(pdev); 107 } 108 109 #define PCI_REVISION_ID_ERROR_VAL 0xff 110 111 /* Performs PCI initializations as well as initializing PCI-related parameters 112 * in the device structrue. Returns 0 in case of success. 113 */ 114 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 115 { 116 u8 rev_id; 117 int rc; 118 119 cdev->pdev = pdev; 120 121 rc = pci_enable_device(pdev); 122 if (rc) { 123 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 124 goto err0; 125 } 126 127 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 128 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 129 rc = -EIO; 130 goto err1; 131 } 132 133 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 134 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 135 rc = -EIO; 136 goto err1; 137 } 138 139 if (atomic_read(&pdev->enable_cnt) == 1) { 140 rc = pci_request_regions(pdev, "qed"); 141 if (rc) { 142 DP_NOTICE(cdev, 143 "Failed to request PCI memory resources\n"); 144 goto err1; 145 } 146 pci_set_master(pdev); 147 pci_save_state(pdev); 148 } 149 150 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 151 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 152 DP_NOTICE(cdev, 153 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 154 rev_id); 155 rc = -ENODEV; 156 goto err2; 157 } 158 if (!pci_is_pcie(pdev)) { 159 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 160 rc = -EIO; 161 goto err2; 162 } 163 164 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 165 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 166 DP_NOTICE(cdev, "Cannot find power management capability\n"); 167 168 rc = qed_set_coherency_mask(cdev); 169 if (rc) 170 goto err2; 171 172 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 173 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 174 cdev->pci_params.irq = pdev->irq; 175 176 cdev->regview = pci_ioremap_bar(pdev, 0); 177 if (!cdev->regview) { 178 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 179 rc = -ENOMEM; 180 goto err2; 181 } 182 183 if (IS_PF(cdev)) { 184 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 185 cdev->db_size = pci_resource_len(cdev->pdev, 2); 186 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 187 if (!cdev->doorbells) { 188 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 189 return -ENOMEM; 190 } 191 } 192 193 return 0; 194 195 err2: 196 pci_release_regions(pdev); 197 err1: 198 pci_disable_device(pdev); 199 err0: 200 return rc; 201 } 202 203 int qed_fill_dev_info(struct qed_dev *cdev, 204 struct qed_dev_info *dev_info) 205 { 206 struct qed_ptt *ptt; 207 208 memset(dev_info, 0, sizeof(struct qed_dev_info)); 209 210 dev_info->num_hwfns = cdev->num_hwfns; 211 dev_info->pci_mem_start = cdev->pci_params.mem_start; 212 dev_info->pci_mem_end = cdev->pci_params.mem_end; 213 dev_info->pci_irq = cdev->pci_params.irq; 214 dev_info->rdma_supported = (cdev->hwfns[0].hw_info.personality == 215 QED_PCI_ETH_ROCE); 216 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]); 217 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr); 218 219 if (IS_PF(cdev)) { 220 dev_info->fw_major = FW_MAJOR_VERSION; 221 dev_info->fw_minor = FW_MINOR_VERSION; 222 dev_info->fw_rev = FW_REVISION_VERSION; 223 dev_info->fw_eng = FW_ENGINEERING_VERSION; 224 dev_info->mf_mode = cdev->mf_mode; 225 dev_info->tx_switching = true; 226 } else { 227 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 228 &dev_info->fw_minor, &dev_info->fw_rev, 229 &dev_info->fw_eng); 230 } 231 232 if (IS_PF(cdev)) { 233 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 234 if (ptt) { 235 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 236 &dev_info->mfw_rev, NULL); 237 238 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 239 &dev_info->flash_size); 240 241 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 242 } 243 } else { 244 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 245 &dev_info->mfw_rev, NULL); 246 } 247 248 return 0; 249 } 250 251 static void qed_free_cdev(struct qed_dev *cdev) 252 { 253 kfree((void *)cdev); 254 } 255 256 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 257 { 258 struct qed_dev *cdev; 259 260 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 261 if (!cdev) 262 return cdev; 263 264 qed_init_struct(cdev); 265 266 return cdev; 267 } 268 269 /* Sets the requested power state */ 270 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 271 { 272 if (!cdev) 273 return -ENODEV; 274 275 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 276 return 0; 277 } 278 279 /* probing */ 280 static struct qed_dev *qed_probe(struct pci_dev *pdev, 281 struct qed_probe_params *params) 282 { 283 struct qed_dev *cdev; 284 int rc; 285 286 cdev = qed_alloc_cdev(pdev); 287 if (!cdev) 288 goto err0; 289 290 cdev->protocol = params->protocol; 291 292 if (params->is_vf) 293 cdev->b_is_vf = true; 294 295 qed_init_dp(cdev, params->dp_module, params->dp_level); 296 297 rc = qed_init_pci(cdev, pdev); 298 if (rc) { 299 DP_ERR(cdev, "init pci failed\n"); 300 goto err1; 301 } 302 DP_INFO(cdev, "PCI init completed successfully\n"); 303 304 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 305 if (rc) { 306 DP_ERR(cdev, "hw prepare failed\n"); 307 goto err2; 308 } 309 310 DP_INFO(cdev, "qed_probe completed successffuly\n"); 311 312 return cdev; 313 314 err2: 315 qed_free_pci(cdev); 316 err1: 317 qed_free_cdev(cdev); 318 err0: 319 return NULL; 320 } 321 322 static void qed_remove(struct qed_dev *cdev) 323 { 324 if (!cdev) 325 return; 326 327 qed_hw_remove(cdev); 328 329 qed_free_pci(cdev); 330 331 qed_set_power_state(cdev, PCI_D3hot); 332 333 qed_free_cdev(cdev); 334 } 335 336 static void qed_disable_msix(struct qed_dev *cdev) 337 { 338 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 339 pci_disable_msix(cdev->pdev); 340 kfree(cdev->int_params.msix_table); 341 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 342 pci_disable_msi(cdev->pdev); 343 } 344 345 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 346 } 347 348 static int qed_enable_msix(struct qed_dev *cdev, 349 struct qed_int_params *int_params) 350 { 351 int i, rc, cnt; 352 353 cnt = int_params->in.num_vectors; 354 355 for (i = 0; i < cnt; i++) 356 int_params->msix_table[i].entry = i; 357 358 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 359 int_params->in.min_msix_cnt, cnt); 360 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 361 (rc % cdev->num_hwfns)) { 362 pci_disable_msix(cdev->pdev); 363 364 /* If fastpath is initialized, we need at least one interrupt 365 * per hwfn [and the slow path interrupts]. New requested number 366 * should be a multiple of the number of hwfns. 367 */ 368 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 369 DP_NOTICE(cdev, 370 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 371 cnt, int_params->in.num_vectors); 372 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 373 cnt); 374 if (!rc) 375 rc = cnt; 376 } 377 378 if (rc > 0) { 379 /* MSI-x configuration was achieved */ 380 int_params->out.int_mode = QED_INT_MODE_MSIX; 381 int_params->out.num_vectors = rc; 382 rc = 0; 383 } else { 384 DP_NOTICE(cdev, 385 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 386 cnt, rc); 387 } 388 389 return rc; 390 } 391 392 /* This function outputs the int mode and the number of enabled msix vector */ 393 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 394 { 395 struct qed_int_params *int_params = &cdev->int_params; 396 struct msix_entry *tbl; 397 int rc = 0, cnt; 398 399 switch (int_params->in.int_mode) { 400 case QED_INT_MODE_MSIX: 401 /* Allocate MSIX table */ 402 cnt = int_params->in.num_vectors; 403 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 404 if (!int_params->msix_table) { 405 rc = -ENOMEM; 406 goto out; 407 } 408 409 /* Enable MSIX */ 410 rc = qed_enable_msix(cdev, int_params); 411 if (!rc) 412 goto out; 413 414 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 415 kfree(int_params->msix_table); 416 if (force_mode) 417 goto out; 418 /* Fallthrough */ 419 420 case QED_INT_MODE_MSI: 421 if (cdev->num_hwfns == 1) { 422 rc = pci_enable_msi(cdev->pdev); 423 if (!rc) { 424 int_params->out.int_mode = QED_INT_MODE_MSI; 425 goto out; 426 } 427 428 DP_NOTICE(cdev, "Failed to enable MSI\n"); 429 if (force_mode) 430 goto out; 431 } 432 /* Fallthrough */ 433 434 case QED_INT_MODE_INTA: 435 int_params->out.int_mode = QED_INT_MODE_INTA; 436 rc = 0; 437 goto out; 438 default: 439 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 440 int_params->in.int_mode); 441 rc = -EINVAL; 442 } 443 444 out: 445 if (!rc) 446 DP_INFO(cdev, "Using %s interrupts\n", 447 int_params->out.int_mode == QED_INT_MODE_INTA ? 448 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 449 "MSI" : "MSIX"); 450 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 451 452 return rc; 453 } 454 455 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 456 int index, void(*handler)(void *)) 457 { 458 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 459 int relative_idx = index / cdev->num_hwfns; 460 461 hwfn->simd_proto_handler[relative_idx].func = handler; 462 hwfn->simd_proto_handler[relative_idx].token = token; 463 } 464 465 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 466 { 467 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 468 int relative_idx = index / cdev->num_hwfns; 469 470 memset(&hwfn->simd_proto_handler[relative_idx], 0, 471 sizeof(struct qed_simd_fp_handler)); 472 } 473 474 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 475 { 476 tasklet_schedule((struct tasklet_struct *)tasklet); 477 return IRQ_HANDLED; 478 } 479 480 static irqreturn_t qed_single_int(int irq, void *dev_instance) 481 { 482 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 483 struct qed_hwfn *hwfn; 484 irqreturn_t rc = IRQ_NONE; 485 u64 status; 486 int i, j; 487 488 for (i = 0; i < cdev->num_hwfns; i++) { 489 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 490 491 if (!status) 492 continue; 493 494 hwfn = &cdev->hwfns[i]; 495 496 /* Slowpath interrupt */ 497 if (unlikely(status & 0x1)) { 498 tasklet_schedule(hwfn->sp_dpc); 499 status &= ~0x1; 500 rc = IRQ_HANDLED; 501 } 502 503 /* Fastpath interrupts */ 504 for (j = 0; j < 64; j++) { 505 if ((0x2ULL << j) & status) { 506 hwfn->simd_proto_handler[j].func( 507 hwfn->simd_proto_handler[j].token); 508 status &= ~(0x2ULL << j); 509 rc = IRQ_HANDLED; 510 } 511 } 512 513 if (unlikely(status)) 514 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 515 "got an unknown interrupt status 0x%llx\n", 516 status); 517 } 518 519 return rc; 520 } 521 522 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 523 { 524 struct qed_dev *cdev = hwfn->cdev; 525 u32 int_mode; 526 int rc = 0; 527 u8 id; 528 529 int_mode = cdev->int_params.out.int_mode; 530 if (int_mode == QED_INT_MODE_MSIX) { 531 id = hwfn->my_id; 532 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 533 id, cdev->pdev->bus->number, 534 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 535 rc = request_irq(cdev->int_params.msix_table[id].vector, 536 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 537 } else { 538 unsigned long flags = 0; 539 540 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 541 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 542 PCI_FUNC(cdev->pdev->devfn)); 543 544 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 545 flags |= IRQF_SHARED; 546 547 rc = request_irq(cdev->pdev->irq, qed_single_int, 548 flags, cdev->name, cdev); 549 } 550 551 if (rc) 552 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 553 else 554 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 555 "Requested slowpath %s\n", 556 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 557 558 return rc; 559 } 560 561 static void qed_slowpath_irq_free(struct qed_dev *cdev) 562 { 563 int i; 564 565 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 566 for_each_hwfn(cdev, i) { 567 if (!cdev->hwfns[i].b_int_requested) 568 break; 569 synchronize_irq(cdev->int_params.msix_table[i].vector); 570 free_irq(cdev->int_params.msix_table[i].vector, 571 cdev->hwfns[i].sp_dpc); 572 } 573 } else { 574 if (QED_LEADING_HWFN(cdev)->b_int_requested) 575 free_irq(cdev->pdev->irq, cdev); 576 } 577 qed_int_disable_post_isr_release(cdev); 578 } 579 580 static int qed_nic_stop(struct qed_dev *cdev) 581 { 582 int i, rc; 583 584 rc = qed_hw_stop(cdev); 585 586 for (i = 0; i < cdev->num_hwfns; i++) { 587 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 588 589 if (p_hwfn->b_sp_dpc_enabled) { 590 tasklet_disable(p_hwfn->sp_dpc); 591 p_hwfn->b_sp_dpc_enabled = false; 592 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 593 "Disabled sp taskelt [hwfn %d] at %p\n", 594 i, p_hwfn->sp_dpc); 595 } 596 } 597 598 qed_dbg_pf_exit(cdev); 599 600 return rc; 601 } 602 603 static int qed_nic_reset(struct qed_dev *cdev) 604 { 605 int rc; 606 607 rc = qed_hw_reset(cdev); 608 if (rc) 609 return rc; 610 611 qed_resc_free(cdev); 612 613 return 0; 614 } 615 616 static int qed_nic_setup(struct qed_dev *cdev) 617 { 618 int rc, i; 619 620 /* Determine if interface is going to require LL2 */ 621 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 622 for (i = 0; i < cdev->num_hwfns; i++) { 623 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 624 625 p_hwfn->using_ll2 = true; 626 } 627 } 628 629 rc = qed_resc_alloc(cdev); 630 if (rc) 631 return rc; 632 633 DP_INFO(cdev, "Allocated qed resources\n"); 634 635 qed_resc_setup(cdev); 636 637 return rc; 638 } 639 640 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 641 { 642 int limit = 0; 643 644 /* Mark the fastpath as free/used */ 645 cdev->int_params.fp_initialized = cnt ? true : false; 646 647 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 648 limit = cdev->num_hwfns * 63; 649 else if (cdev->int_params.fp_msix_cnt) 650 limit = cdev->int_params.fp_msix_cnt; 651 652 if (!limit) 653 return -ENOMEM; 654 655 return min_t(int, cnt, limit); 656 } 657 658 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 659 { 660 memset(info, 0, sizeof(struct qed_int_info)); 661 662 if (!cdev->int_params.fp_initialized) { 663 DP_INFO(cdev, 664 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 665 return -EINVAL; 666 } 667 668 /* Need to expose only MSI-X information; Single IRQ is handled solely 669 * by qed. 670 */ 671 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 672 int msix_base = cdev->int_params.fp_msix_base; 673 674 info->msix_cnt = cdev->int_params.fp_msix_cnt; 675 info->msix = &cdev->int_params.msix_table[msix_base]; 676 } 677 678 return 0; 679 } 680 681 static int qed_slowpath_setup_int(struct qed_dev *cdev, 682 enum qed_int_mode int_mode) 683 { 684 struct qed_sb_cnt_info sb_cnt_info; 685 #if IS_ENABLED(CONFIG_INFINIBAND_QEDR) 686 int num_l2_queues; 687 #endif 688 int rc; 689 int i; 690 691 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 692 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 693 return -EINVAL; 694 } 695 696 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 697 cdev->int_params.in.int_mode = int_mode; 698 for_each_hwfn(cdev, i) { 699 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 700 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 701 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt; 702 cdev->int_params.in.num_vectors++; /* slowpath */ 703 } 704 705 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 706 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 707 708 rc = qed_set_int_mode(cdev, false); 709 if (rc) { 710 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 711 return rc; 712 } 713 714 cdev->int_params.fp_msix_base = cdev->num_hwfns; 715 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 716 cdev->num_hwfns; 717 718 #if IS_ENABLED(CONFIG_INFINIBAND_QEDR) 719 num_l2_queues = 0; 720 for_each_hwfn(cdev, i) 721 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 722 723 DP_VERBOSE(cdev, QED_MSG_RDMA, 724 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 725 cdev->int_params.fp_msix_cnt, num_l2_queues); 726 727 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 728 cdev->int_params.rdma_msix_cnt = 729 (cdev->int_params.fp_msix_cnt - num_l2_queues) 730 / cdev->num_hwfns; 731 cdev->int_params.rdma_msix_base = 732 cdev->int_params.fp_msix_base + num_l2_queues; 733 cdev->int_params.fp_msix_cnt = num_l2_queues; 734 } else { 735 cdev->int_params.rdma_msix_cnt = 0; 736 } 737 738 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 739 cdev->int_params.rdma_msix_cnt, 740 cdev->int_params.rdma_msix_base); 741 #endif 742 743 return 0; 744 } 745 746 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 747 { 748 int rc; 749 750 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 751 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 752 753 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 754 &cdev->int_params.in.num_vectors); 755 if (cdev->num_hwfns > 1) { 756 u8 vectors = 0; 757 758 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 759 cdev->int_params.in.num_vectors += vectors; 760 } 761 762 /* We want a minimum of one fastpath vector per vf hwfn */ 763 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 764 765 rc = qed_set_int_mode(cdev, true); 766 if (rc) 767 return rc; 768 769 cdev->int_params.fp_msix_base = 0; 770 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 771 772 return 0; 773 } 774 775 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 776 u8 *input_buf, u32 max_size, u8 *unzip_buf) 777 { 778 int rc; 779 780 p_hwfn->stream->next_in = input_buf; 781 p_hwfn->stream->avail_in = input_len; 782 p_hwfn->stream->next_out = unzip_buf; 783 p_hwfn->stream->avail_out = max_size; 784 785 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 786 787 if (rc != Z_OK) { 788 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 789 rc); 790 return 0; 791 } 792 793 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 794 zlib_inflateEnd(p_hwfn->stream); 795 796 if (rc != Z_OK && rc != Z_STREAM_END) { 797 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 798 p_hwfn->stream->msg, rc); 799 return 0; 800 } 801 802 return p_hwfn->stream->total_out / 4; 803 } 804 805 static int qed_alloc_stream_mem(struct qed_dev *cdev) 806 { 807 int i; 808 void *workspace; 809 810 for_each_hwfn(cdev, i) { 811 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 812 813 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 814 if (!p_hwfn->stream) 815 return -ENOMEM; 816 817 workspace = vzalloc(zlib_inflate_workspacesize()); 818 if (!workspace) 819 return -ENOMEM; 820 p_hwfn->stream->workspace = workspace; 821 } 822 823 return 0; 824 } 825 826 static void qed_free_stream_mem(struct qed_dev *cdev) 827 { 828 int i; 829 830 for_each_hwfn(cdev, i) { 831 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 832 833 if (!p_hwfn->stream) 834 return; 835 836 vfree(p_hwfn->stream->workspace); 837 kfree(p_hwfn->stream); 838 } 839 } 840 841 static void qed_update_pf_params(struct qed_dev *cdev, 842 struct qed_pf_params *params) 843 { 844 int i; 845 846 #if IS_ENABLED(CONFIG_INFINIBAND_QEDR) 847 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 848 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 849 /* divide by 3 the MRs to avoid MF ILT overflow */ 850 params->rdma_pf_params.num_mrs = RDMA_MAX_TIDS; 851 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 852 #endif 853 for (i = 0; i < cdev->num_hwfns; i++) { 854 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 855 856 p_hwfn->pf_params = *params; 857 } 858 } 859 860 static int qed_slowpath_start(struct qed_dev *cdev, 861 struct qed_slowpath_params *params) 862 { 863 struct qed_tunn_start_params tunn_info; 864 struct qed_mcp_drv_version drv_version; 865 const u8 *data = NULL; 866 struct qed_hwfn *hwfn; 867 int rc = -EINVAL; 868 869 if (qed_iov_wq_start(cdev)) 870 goto err; 871 872 if (IS_PF(cdev)) { 873 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 874 &cdev->pdev->dev); 875 if (rc) { 876 DP_NOTICE(cdev, 877 "Failed to find fw file - /lib/firmware/%s\n", 878 QED_FW_FILE_NAME); 879 goto err; 880 } 881 } 882 883 rc = qed_nic_setup(cdev); 884 if (rc) 885 goto err; 886 887 if (IS_PF(cdev)) 888 rc = qed_slowpath_setup_int(cdev, params->int_mode); 889 else 890 rc = qed_slowpath_vf_setup_int(cdev); 891 if (rc) 892 goto err1; 893 894 if (IS_PF(cdev)) { 895 /* Allocate stream for unzipping */ 896 rc = qed_alloc_stream_mem(cdev); 897 if (rc) 898 goto err2; 899 900 /* First Dword used to diffrentiate between various sources */ 901 data = cdev->firmware->data + sizeof(u32); 902 903 qed_dbg_pf_init(cdev); 904 } 905 906 memset(&tunn_info, 0, sizeof(tunn_info)); 907 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN | 908 1 << QED_MODE_L2GRE_TUNN | 909 1 << QED_MODE_IPGRE_TUNN | 910 1 << QED_MODE_L2GENEVE_TUNN | 911 1 << QED_MODE_IPGENEVE_TUNN; 912 913 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN; 914 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN; 915 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN; 916 917 /* Start the slowpath */ 918 rc = qed_hw_init(cdev, &tunn_info, true, 919 cdev->int_params.out.int_mode, 920 true, data); 921 if (rc) 922 goto err2; 923 924 DP_INFO(cdev, 925 "HW initialization and function start completed successfully\n"); 926 927 /* Allocate LL2 interface if needed */ 928 if (QED_LEADING_HWFN(cdev)->using_ll2) { 929 rc = qed_ll2_alloc_if(cdev); 930 if (rc) 931 goto err3; 932 } 933 if (IS_PF(cdev)) { 934 hwfn = QED_LEADING_HWFN(cdev); 935 drv_version.version = (params->drv_major << 24) | 936 (params->drv_minor << 16) | 937 (params->drv_rev << 8) | 938 (params->drv_eng); 939 strlcpy(drv_version.name, params->name, 940 MCP_DRV_VER_STR_SIZE - 4); 941 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 942 &drv_version); 943 if (rc) { 944 DP_NOTICE(cdev, "Failed sending drv version command\n"); 945 return rc; 946 } 947 } 948 949 qed_reset_vport_stats(cdev); 950 951 return 0; 952 953 err3: 954 qed_hw_stop(cdev); 955 err2: 956 qed_hw_timers_stop_all(cdev); 957 if (IS_PF(cdev)) 958 qed_slowpath_irq_free(cdev); 959 qed_free_stream_mem(cdev); 960 qed_disable_msix(cdev); 961 err1: 962 qed_resc_free(cdev); 963 err: 964 if (IS_PF(cdev)) 965 release_firmware(cdev->firmware); 966 967 qed_iov_wq_stop(cdev, false); 968 969 return rc; 970 } 971 972 static int qed_slowpath_stop(struct qed_dev *cdev) 973 { 974 if (!cdev) 975 return -ENODEV; 976 977 qed_ll2_dealloc_if(cdev); 978 979 if (IS_PF(cdev)) { 980 qed_free_stream_mem(cdev); 981 if (IS_QED_ETH_IF(cdev)) 982 qed_sriov_disable(cdev, true); 983 984 qed_nic_stop(cdev); 985 qed_slowpath_irq_free(cdev); 986 } 987 988 qed_disable_msix(cdev); 989 qed_nic_reset(cdev); 990 991 qed_iov_wq_stop(cdev, true); 992 993 if (IS_PF(cdev)) 994 release_firmware(cdev->firmware); 995 996 return 0; 997 } 998 999 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE], 1000 char ver_str[VER_SIZE]) 1001 { 1002 int i; 1003 1004 memcpy(cdev->name, name, NAME_SIZE); 1005 for_each_hwfn(cdev, i) 1006 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1007 1008 memcpy(cdev->ver_str, ver_str, VER_SIZE); 1009 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 1010 } 1011 1012 static u32 qed_sb_init(struct qed_dev *cdev, 1013 struct qed_sb_info *sb_info, 1014 void *sb_virt_addr, 1015 dma_addr_t sb_phy_addr, u16 sb_id, 1016 enum qed_sb_type type) 1017 { 1018 struct qed_hwfn *p_hwfn; 1019 int hwfn_index; 1020 u16 rel_sb_id; 1021 u8 n_hwfns; 1022 u32 rc; 1023 1024 /* RoCE uses single engine and CMT uses two engines. When using both 1025 * we force only a single engine. Storage uses only engine 0 too. 1026 */ 1027 if (type == QED_SB_TYPE_L2_QUEUE) 1028 n_hwfns = cdev->num_hwfns; 1029 else 1030 n_hwfns = 1; 1031 1032 hwfn_index = sb_id % n_hwfns; 1033 p_hwfn = &cdev->hwfns[hwfn_index]; 1034 rel_sb_id = sb_id / n_hwfns; 1035 1036 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1037 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1038 hwfn_index, rel_sb_id, sb_id); 1039 1040 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 1041 sb_virt_addr, sb_phy_addr, rel_sb_id); 1042 1043 return rc; 1044 } 1045 1046 static u32 qed_sb_release(struct qed_dev *cdev, 1047 struct qed_sb_info *sb_info, u16 sb_id) 1048 { 1049 struct qed_hwfn *p_hwfn; 1050 int hwfn_index; 1051 u16 rel_sb_id; 1052 u32 rc; 1053 1054 hwfn_index = sb_id % cdev->num_hwfns; 1055 p_hwfn = &cdev->hwfns[hwfn_index]; 1056 rel_sb_id = sb_id / cdev->num_hwfns; 1057 1058 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1059 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1060 hwfn_index, rel_sb_id, sb_id); 1061 1062 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1063 1064 return rc; 1065 } 1066 1067 static bool qed_can_link_change(struct qed_dev *cdev) 1068 { 1069 return true; 1070 } 1071 1072 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1073 { 1074 struct qed_hwfn *hwfn; 1075 struct qed_mcp_link_params *link_params; 1076 struct qed_ptt *ptt; 1077 int rc; 1078 1079 if (!cdev) 1080 return -ENODEV; 1081 1082 if (IS_VF(cdev)) 1083 return 0; 1084 1085 /* The link should be set only once per PF */ 1086 hwfn = &cdev->hwfns[0]; 1087 1088 ptt = qed_ptt_acquire(hwfn); 1089 if (!ptt) 1090 return -EBUSY; 1091 1092 link_params = qed_mcp_get_link_params(hwfn); 1093 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1094 link_params->speed.autoneg = params->autoneg; 1095 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1096 link_params->speed.advertised_speeds = 0; 1097 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1098 (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1099 link_params->speed.advertised_speeds |= 1100 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1101 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1102 link_params->speed.advertised_speeds |= 1103 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1104 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1105 link_params->speed.advertised_speeds |= 1106 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1107 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1108 link_params->speed.advertised_speeds |= 1109 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1110 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1111 link_params->speed.advertised_speeds |= 1112 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1113 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1114 link_params->speed.advertised_speeds |= 1115 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1116 } 1117 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1118 link_params->speed.forced_speed = params->forced_speed; 1119 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1120 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1121 link_params->pause.autoneg = true; 1122 else 1123 link_params->pause.autoneg = false; 1124 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1125 link_params->pause.forced_rx = true; 1126 else 1127 link_params->pause.forced_rx = false; 1128 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1129 link_params->pause.forced_tx = true; 1130 else 1131 link_params->pause.forced_tx = false; 1132 } 1133 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1134 switch (params->loopback_mode) { 1135 case QED_LINK_LOOPBACK_INT_PHY: 1136 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1137 break; 1138 case QED_LINK_LOOPBACK_EXT_PHY: 1139 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1140 break; 1141 case QED_LINK_LOOPBACK_EXT: 1142 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1143 break; 1144 case QED_LINK_LOOPBACK_MAC: 1145 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1146 break; 1147 default: 1148 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1149 break; 1150 } 1151 } 1152 1153 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1154 1155 qed_ptt_release(hwfn, ptt); 1156 1157 return rc; 1158 } 1159 1160 static int qed_get_port_type(u32 media_type) 1161 { 1162 int port_type; 1163 1164 switch (media_type) { 1165 case MEDIA_SFPP_10G_FIBER: 1166 case MEDIA_SFP_1G_FIBER: 1167 case MEDIA_XFP_FIBER: 1168 case MEDIA_MODULE_FIBER: 1169 case MEDIA_KR: 1170 port_type = PORT_FIBRE; 1171 break; 1172 case MEDIA_DA_TWINAX: 1173 port_type = PORT_DA; 1174 break; 1175 case MEDIA_BASE_T: 1176 port_type = PORT_TP; 1177 break; 1178 case MEDIA_NOT_PRESENT: 1179 port_type = PORT_NONE; 1180 break; 1181 case MEDIA_UNSPECIFIED: 1182 default: 1183 port_type = PORT_OTHER; 1184 break; 1185 } 1186 return port_type; 1187 } 1188 1189 static int qed_get_link_data(struct qed_hwfn *hwfn, 1190 struct qed_mcp_link_params *params, 1191 struct qed_mcp_link_state *link, 1192 struct qed_mcp_link_capabilities *link_caps) 1193 { 1194 void *p; 1195 1196 if (!IS_PF(hwfn->cdev)) { 1197 qed_vf_get_link_params(hwfn, params); 1198 qed_vf_get_link_state(hwfn, link); 1199 qed_vf_get_link_caps(hwfn, link_caps); 1200 1201 return 0; 1202 } 1203 1204 p = qed_mcp_get_link_params(hwfn); 1205 if (!p) 1206 return -ENXIO; 1207 memcpy(params, p, sizeof(*params)); 1208 1209 p = qed_mcp_get_link_state(hwfn); 1210 if (!p) 1211 return -ENXIO; 1212 memcpy(link, p, sizeof(*link)); 1213 1214 p = qed_mcp_get_link_capabilities(hwfn); 1215 if (!p) 1216 return -ENXIO; 1217 memcpy(link_caps, p, sizeof(*link_caps)); 1218 1219 return 0; 1220 } 1221 1222 static void qed_fill_link(struct qed_hwfn *hwfn, 1223 struct qed_link_output *if_link) 1224 { 1225 struct qed_mcp_link_params params; 1226 struct qed_mcp_link_state link; 1227 struct qed_mcp_link_capabilities link_caps; 1228 u32 media_type; 1229 1230 memset(if_link, 0, sizeof(*if_link)); 1231 1232 /* Prepare source inputs */ 1233 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1234 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1235 return; 1236 } 1237 1238 /* Set the link parameters to pass to protocol driver */ 1239 if (link.link_up) 1240 if_link->link_up = true; 1241 1242 /* TODO - at the moment assume supported and advertised speed equal */ 1243 if_link->supported_caps = QED_LM_FIBRE_BIT; 1244 if (params.speed.autoneg) 1245 if_link->supported_caps |= QED_LM_Autoneg_BIT; 1246 if (params.pause.autoneg || 1247 (params.pause.forced_rx && params.pause.forced_tx)) 1248 if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1249 if (params.pause.autoneg || params.pause.forced_rx || 1250 params.pause.forced_tx) 1251 if_link->supported_caps |= QED_LM_Pause_BIT; 1252 1253 if_link->advertised_caps = if_link->supported_caps; 1254 if (params.speed.advertised_speeds & 1255 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1256 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1257 QED_LM_1000baseT_Full_BIT; 1258 if (params.speed.advertised_speeds & 1259 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1260 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1261 if (params.speed.advertised_speeds & 1262 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1263 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1264 if (params.speed.advertised_speeds & 1265 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1266 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1267 if (params.speed.advertised_speeds & 1268 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1269 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1270 if (params.speed.advertised_speeds & 1271 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1272 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1273 1274 if (link_caps.speed_capabilities & 1275 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1276 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1277 QED_LM_1000baseT_Full_BIT; 1278 if (link_caps.speed_capabilities & 1279 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1280 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1281 if (link_caps.speed_capabilities & 1282 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1283 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1284 if (link_caps.speed_capabilities & 1285 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1286 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1287 if (link_caps.speed_capabilities & 1288 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1289 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1290 if (link_caps.speed_capabilities & 1291 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1292 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1293 1294 if (link.link_up) 1295 if_link->speed = link.speed; 1296 1297 /* TODO - fill duplex properly */ 1298 if_link->duplex = DUPLEX_FULL; 1299 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1300 if_link->port = qed_get_port_type(media_type); 1301 1302 if_link->autoneg = params.speed.autoneg; 1303 1304 if (params.pause.autoneg) 1305 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1306 if (params.pause.forced_rx) 1307 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1308 if (params.pause.forced_tx) 1309 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1310 1311 /* Link partner capabilities */ 1312 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1313 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1314 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1315 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1316 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1317 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1318 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1319 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1320 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1321 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1322 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1323 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1324 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1325 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1326 1327 if (link.an_complete) 1328 if_link->lp_caps |= QED_LM_Autoneg_BIT; 1329 1330 if (link.partner_adv_pause) 1331 if_link->lp_caps |= QED_LM_Pause_BIT; 1332 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1333 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1334 if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1335 } 1336 1337 static void qed_get_current_link(struct qed_dev *cdev, 1338 struct qed_link_output *if_link) 1339 { 1340 int i; 1341 1342 qed_fill_link(&cdev->hwfns[0], if_link); 1343 1344 for_each_hwfn(cdev, i) 1345 qed_inform_vf_link_state(&cdev->hwfns[i]); 1346 } 1347 1348 void qed_link_update(struct qed_hwfn *hwfn) 1349 { 1350 void *cookie = hwfn->cdev->ops_cookie; 1351 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1352 struct qed_link_output if_link; 1353 1354 qed_fill_link(hwfn, &if_link); 1355 qed_inform_vf_link_state(hwfn); 1356 1357 if (IS_LEAD_HWFN(hwfn) && cookie) 1358 op->link_update(cookie, &if_link); 1359 } 1360 1361 static int qed_drain(struct qed_dev *cdev) 1362 { 1363 struct qed_hwfn *hwfn; 1364 struct qed_ptt *ptt; 1365 int i, rc; 1366 1367 if (IS_VF(cdev)) 1368 return 0; 1369 1370 for_each_hwfn(cdev, i) { 1371 hwfn = &cdev->hwfns[i]; 1372 ptt = qed_ptt_acquire(hwfn); 1373 if (!ptt) { 1374 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1375 return -EBUSY; 1376 } 1377 rc = qed_mcp_drain(hwfn, ptt); 1378 if (rc) 1379 return rc; 1380 qed_ptt_release(hwfn, ptt); 1381 } 1382 1383 return 0; 1384 } 1385 1386 static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal) 1387 { 1388 *rx_coal = cdev->rx_coalesce_usecs; 1389 *tx_coal = cdev->tx_coalesce_usecs; 1390 } 1391 1392 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1393 u8 qid, u16 sb_id) 1394 { 1395 struct qed_hwfn *hwfn; 1396 struct qed_ptt *ptt; 1397 int hwfn_index; 1398 int status = 0; 1399 1400 hwfn_index = qid % cdev->num_hwfns; 1401 hwfn = &cdev->hwfns[hwfn_index]; 1402 ptt = qed_ptt_acquire(hwfn); 1403 if (!ptt) 1404 return -EAGAIN; 1405 1406 status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal, 1407 qid / cdev->num_hwfns, sb_id); 1408 if (status) 1409 goto out; 1410 status = qed_set_txq_coalesce(hwfn, ptt, tx_coal, 1411 qid / cdev->num_hwfns, sb_id); 1412 out: 1413 qed_ptt_release(hwfn, ptt); 1414 1415 return status; 1416 } 1417 1418 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1419 { 1420 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1421 struct qed_ptt *ptt; 1422 int status = 0; 1423 1424 ptt = qed_ptt_acquire(hwfn); 1425 if (!ptt) 1426 return -EAGAIN; 1427 1428 status = qed_mcp_set_led(hwfn, ptt, mode); 1429 1430 qed_ptt_release(hwfn, ptt); 1431 1432 return status; 1433 } 1434 1435 struct qed_selftest_ops qed_selftest_ops_pass = { 1436 .selftest_memory = &qed_selftest_memory, 1437 .selftest_interrupt = &qed_selftest_interrupt, 1438 .selftest_register = &qed_selftest_register, 1439 .selftest_clock = &qed_selftest_clock, 1440 }; 1441 1442 const struct qed_common_ops qed_common_ops_pass = { 1443 .selftest = &qed_selftest_ops_pass, 1444 .probe = &qed_probe, 1445 .remove = &qed_remove, 1446 .set_power_state = &qed_set_power_state, 1447 .set_id = &qed_set_id, 1448 .update_pf_params = &qed_update_pf_params, 1449 .slowpath_start = &qed_slowpath_start, 1450 .slowpath_stop = &qed_slowpath_stop, 1451 .set_fp_int = &qed_set_int_fp, 1452 .get_fp_int = &qed_get_int_fp, 1453 .sb_init = &qed_sb_init, 1454 .sb_release = &qed_sb_release, 1455 .simd_handler_config = &qed_simd_handler_config, 1456 .simd_handler_clean = &qed_simd_handler_clean, 1457 .can_link_change = &qed_can_link_change, 1458 .set_link = &qed_set_link, 1459 .get_link = &qed_get_current_link, 1460 .drain = &qed_drain, 1461 .update_msglvl = &qed_init_dp, 1462 .dbg_all_data = &qed_dbg_all_data, 1463 .dbg_all_data_size = &qed_dbg_all_data_size, 1464 .chain_alloc = &qed_chain_alloc, 1465 .chain_free = &qed_chain_free, 1466 .get_coalesce = &qed_get_coalesce, 1467 .set_coalesce = &qed_set_coalesce, 1468 .set_led = &qed_set_led, 1469 }; 1470 1471 void qed_get_protocol_stats(struct qed_dev *cdev, 1472 enum qed_mcp_protocol_type type, 1473 union qed_mcp_protocol_stats *stats) 1474 { 1475 struct qed_eth_stats eth_stats; 1476 1477 memset(stats, 0, sizeof(*stats)); 1478 1479 switch (type) { 1480 case QED_MCP_LAN_STATS: 1481 qed_get_vport_stats(cdev, ð_stats); 1482 stats->lan_stats.ucast_rx_pkts = eth_stats.rx_ucast_pkts; 1483 stats->lan_stats.ucast_tx_pkts = eth_stats.tx_ucast_pkts; 1484 stats->lan_stats.fcs_err = -1; 1485 break; 1486 default: 1487 DP_ERR(cdev, "Invalid protocol type = %d\n", type); 1488 return; 1489 } 1490 } 1491