1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #include <linux/stddef.h> 8 #include <linux/pci.h> 9 #include <linux/kernel.h> 10 #include <linux/slab.h> 11 #include <linux/delay.h> 12 #include <asm/byteorder.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/string.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/workqueue.h> 18 #include <linux/ethtool.h> 19 #include <linux/etherdevice.h> 20 #include <linux/vmalloc.h> 21 #include <linux/crash_dump.h> 22 #include <linux/crc32.h> 23 #include <linux/qed/qed_if.h> 24 #include <linux/qed/qed_ll2_if.h> 25 #include <net/devlink.h> 26 #include <linux/aer.h> 27 #include <linux/phylink.h> 28 29 #include "qed.h" 30 #include "qed_sriov.h" 31 #include "qed_sp.h" 32 #include "qed_dev_api.h" 33 #include "qed_ll2.h" 34 #include "qed_fcoe.h" 35 #include "qed_iscsi.h" 36 37 #include "qed_mcp.h" 38 #include "qed_reg_addr.h" 39 #include "qed_hw.h" 40 #include "qed_selftest.h" 41 #include "qed_debug.h" 42 43 #define QED_ROCE_QPS (8192) 44 #define QED_ROCE_DPIS (8) 45 #define QED_RDMA_SRQS QED_ROCE_QPS 46 #define QED_NVM_CFG_GET_FLAGS 0xA 47 #define QED_NVM_CFG_GET_PF_FLAGS 0x1A 48 #define QED_NVM_CFG_MAX_ATTRS 50 49 50 static char version[] = 51 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 52 53 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 54 MODULE_LICENSE("GPL"); 55 MODULE_VERSION(DRV_MODULE_VERSION); 56 57 #define FW_FILE_VERSION \ 58 __stringify(FW_MAJOR_VERSION) "." \ 59 __stringify(FW_MINOR_VERSION) "." \ 60 __stringify(FW_REVISION_VERSION) "." \ 61 __stringify(FW_ENGINEERING_VERSION) 62 63 #define QED_FW_FILE_NAME \ 64 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 65 66 MODULE_FIRMWARE(QED_FW_FILE_NAME); 67 68 /* MFW speed capabilities maps */ 69 70 struct qed_mfw_speed_map { 71 u32 mfw_val; 72 __ETHTOOL_DECLARE_LINK_MODE_MASK(caps); 73 74 const u32 *cap_arr; 75 u32 arr_size; 76 }; 77 78 #define QED_MFW_SPEED_MAP(type, arr) \ 79 { \ 80 .mfw_val = (type), \ 81 .cap_arr = (arr), \ 82 .arr_size = ARRAY_SIZE(arr), \ 83 } 84 85 static const u32 qed_mfw_ext_1g[] __initconst = { 86 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 87 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 88 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 89 }; 90 91 static const u32 qed_mfw_ext_10g[] __initconst = { 92 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 93 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 94 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 95 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 96 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 97 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 98 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 99 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 100 }; 101 102 static const u32 qed_mfw_ext_20g[] __initconst = { 103 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 104 }; 105 106 static const u32 qed_mfw_ext_25g[] __initconst = { 107 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 108 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 109 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 110 }; 111 112 static const u32 qed_mfw_ext_40g[] __initconst = { 113 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 114 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 115 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 116 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 117 }; 118 119 static const u32 qed_mfw_ext_50g_base_r[] __initconst = { 120 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 121 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 122 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 123 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 124 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 125 }; 126 127 static const u32 qed_mfw_ext_50g_base_r2[] __initconst = { 128 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 129 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 130 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 131 }; 132 133 static const u32 qed_mfw_ext_100g_base_r2[] __initconst = { 134 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 135 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 136 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 137 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 138 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 139 }; 140 141 static const u32 qed_mfw_ext_100g_base_r4[] __initconst = { 142 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 143 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 144 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 145 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 146 }; 147 148 static struct qed_mfw_speed_map qed_mfw_ext_maps[] __ro_after_init = { 149 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_1G, qed_mfw_ext_1g), 150 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_10G, qed_mfw_ext_10g), 151 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_20G, qed_mfw_ext_20g), 152 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_25G, qed_mfw_ext_25g), 153 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_40G, qed_mfw_ext_40g), 154 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_50G_BASE_R, 155 qed_mfw_ext_50g_base_r), 156 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_50G_BASE_R2, 157 qed_mfw_ext_50g_base_r2), 158 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_100G_BASE_R2, 159 qed_mfw_ext_100g_base_r2), 160 QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_100G_BASE_R4, 161 qed_mfw_ext_100g_base_r4), 162 }; 163 164 static const u32 qed_mfw_legacy_1g[] __initconst = { 165 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 166 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 167 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 168 }; 169 170 static const u32 qed_mfw_legacy_10g[] __initconst = { 171 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 172 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 173 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 174 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 175 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 176 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 177 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 178 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 179 }; 180 181 static const u32 qed_mfw_legacy_20g[] __initconst = { 182 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 183 }; 184 185 static const u32 qed_mfw_legacy_25g[] __initconst = { 186 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 187 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 188 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 189 }; 190 191 static const u32 qed_mfw_legacy_40g[] __initconst = { 192 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 193 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 194 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 195 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 196 }; 197 198 static const u32 qed_mfw_legacy_50g[] __initconst = { 199 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 200 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 201 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 202 }; 203 204 static const u32 qed_mfw_legacy_bb_100g[] __initconst = { 205 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 206 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 207 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 208 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 209 }; 210 211 static struct qed_mfw_speed_map qed_mfw_legacy_maps[] __ro_after_init = { 212 QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G, 213 qed_mfw_legacy_1g), 214 QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G, 215 qed_mfw_legacy_10g), 216 QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G, 217 qed_mfw_legacy_20g), 218 QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G, 219 qed_mfw_legacy_25g), 220 QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G, 221 qed_mfw_legacy_40g), 222 QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G, 223 qed_mfw_legacy_50g), 224 QED_MFW_SPEED_MAP(NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G, 225 qed_mfw_legacy_bb_100g), 226 }; 227 228 static void __init qed_mfw_speed_map_populate(struct qed_mfw_speed_map *map) 229 { 230 linkmode_set_bit_array(map->cap_arr, map->arr_size, map->caps); 231 232 map->cap_arr = NULL; 233 map->arr_size = 0; 234 } 235 236 static void __init qed_mfw_speed_maps_init(void) 237 { 238 u32 i; 239 240 for (i = 0; i < ARRAY_SIZE(qed_mfw_ext_maps); i++) 241 qed_mfw_speed_map_populate(qed_mfw_ext_maps + i); 242 243 for (i = 0; i < ARRAY_SIZE(qed_mfw_legacy_maps); i++) 244 qed_mfw_speed_map_populate(qed_mfw_legacy_maps + i); 245 } 246 247 static int __init qed_init(void) 248 { 249 pr_info("%s", version); 250 251 qed_mfw_speed_maps_init(); 252 253 return 0; 254 } 255 module_init(qed_init); 256 257 static void __exit qed_exit(void) 258 { 259 /* To prevent marking this module as "permanent" */ 260 } 261 module_exit(qed_exit); 262 263 /* Check if the DMA controller on the machine can properly handle the DMA 264 * addressing required by the device. 265 */ 266 static int qed_set_coherency_mask(struct qed_dev *cdev) 267 { 268 struct device *dev = &cdev->pdev->dev; 269 270 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 271 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 272 DP_NOTICE(cdev, 273 "Can't request 64-bit consistent allocations\n"); 274 return -EIO; 275 } 276 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 277 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 278 return -EIO; 279 } 280 281 return 0; 282 } 283 284 static void qed_free_pci(struct qed_dev *cdev) 285 { 286 struct pci_dev *pdev = cdev->pdev; 287 288 pci_disable_pcie_error_reporting(pdev); 289 290 if (cdev->doorbells && cdev->db_size) 291 iounmap(cdev->doorbells); 292 if (cdev->regview) 293 iounmap(cdev->regview); 294 if (atomic_read(&pdev->enable_cnt) == 1) 295 pci_release_regions(pdev); 296 297 pci_disable_device(pdev); 298 } 299 300 #define PCI_REVISION_ID_ERROR_VAL 0xff 301 302 /* Performs PCI initializations as well as initializing PCI-related parameters 303 * in the device structrue. Returns 0 in case of success. 304 */ 305 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 306 { 307 u8 rev_id; 308 int rc; 309 310 cdev->pdev = pdev; 311 312 rc = pci_enable_device(pdev); 313 if (rc) { 314 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 315 goto err0; 316 } 317 318 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 319 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 320 rc = -EIO; 321 goto err1; 322 } 323 324 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 325 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 326 rc = -EIO; 327 goto err1; 328 } 329 330 if (atomic_read(&pdev->enable_cnt) == 1) { 331 rc = pci_request_regions(pdev, "qed"); 332 if (rc) { 333 DP_NOTICE(cdev, 334 "Failed to request PCI memory resources\n"); 335 goto err1; 336 } 337 pci_set_master(pdev); 338 pci_save_state(pdev); 339 } 340 341 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 342 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 343 DP_NOTICE(cdev, 344 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 345 rev_id); 346 rc = -ENODEV; 347 goto err2; 348 } 349 if (!pci_is_pcie(pdev)) { 350 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 351 rc = -EIO; 352 goto err2; 353 } 354 355 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 356 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 357 DP_NOTICE(cdev, "Cannot find power management capability\n"); 358 359 rc = qed_set_coherency_mask(cdev); 360 if (rc) 361 goto err2; 362 363 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 364 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 365 cdev->pci_params.irq = pdev->irq; 366 367 cdev->regview = pci_ioremap_bar(pdev, 0); 368 if (!cdev->regview) { 369 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 370 rc = -ENOMEM; 371 goto err2; 372 } 373 374 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 375 cdev->db_size = pci_resource_len(cdev->pdev, 2); 376 if (!cdev->db_size) { 377 if (IS_PF(cdev)) { 378 DP_NOTICE(cdev, "No Doorbell bar available\n"); 379 return -EINVAL; 380 } else { 381 return 0; 382 } 383 } 384 385 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 386 387 if (!cdev->doorbells) { 388 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 389 return -ENOMEM; 390 } 391 392 /* AER (Advanced Error reporting) configuration */ 393 rc = pci_enable_pcie_error_reporting(pdev); 394 if (rc) 395 DP_VERBOSE(cdev, NETIF_MSG_DRV, 396 "Failed to configure PCIe AER [%d]\n", rc); 397 398 return 0; 399 400 err2: 401 pci_release_regions(pdev); 402 err1: 403 pci_disable_device(pdev); 404 err0: 405 return rc; 406 } 407 408 int qed_fill_dev_info(struct qed_dev *cdev, 409 struct qed_dev_info *dev_info) 410 { 411 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 412 struct qed_hw_info *hw_info = &p_hwfn->hw_info; 413 struct qed_tunnel_info *tun = &cdev->tunnel; 414 struct qed_ptt *ptt; 415 416 memset(dev_info, 0, sizeof(struct qed_dev_info)); 417 418 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 419 tun->vxlan.b_mode_enabled) 420 dev_info->vxlan_enable = true; 421 422 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled && 423 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 424 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 425 dev_info->gre_enable = true; 426 427 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled && 428 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 429 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 430 dev_info->geneve_enable = true; 431 432 dev_info->num_hwfns = cdev->num_hwfns; 433 dev_info->pci_mem_start = cdev->pci_params.mem_start; 434 dev_info->pci_mem_end = cdev->pci_params.mem_end; 435 dev_info->pci_irq = cdev->pci_params.irq; 436 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn); 437 dev_info->dev_type = cdev->type; 438 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr); 439 440 if (IS_PF(cdev)) { 441 dev_info->fw_major = FW_MAJOR_VERSION; 442 dev_info->fw_minor = FW_MINOR_VERSION; 443 dev_info->fw_rev = FW_REVISION_VERSION; 444 dev_info->fw_eng = FW_ENGINEERING_VERSION; 445 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH, 446 &cdev->mf_bits); 447 if (!test_bit(QED_MF_DISABLE_ARFS, &cdev->mf_bits)) 448 dev_info->b_arfs_capable = true; 449 dev_info->tx_switching = true; 450 451 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME) 452 dev_info->wol_support = true; 453 454 dev_info->smart_an = qed_mcp_is_smart_an_supported(p_hwfn); 455 456 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id; 457 } else { 458 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 459 &dev_info->fw_minor, &dev_info->fw_rev, 460 &dev_info->fw_eng); 461 } 462 463 if (IS_PF(cdev)) { 464 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 465 if (ptt) { 466 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 467 &dev_info->mfw_rev, NULL); 468 469 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt, 470 &dev_info->mbi_version); 471 472 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 473 &dev_info->flash_size); 474 475 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 476 } 477 } else { 478 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 479 &dev_info->mfw_rev, NULL); 480 } 481 482 dev_info->mtu = hw_info->mtu; 483 484 return 0; 485 } 486 487 static void qed_free_cdev(struct qed_dev *cdev) 488 { 489 kfree((void *)cdev); 490 } 491 492 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 493 { 494 struct qed_dev *cdev; 495 496 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 497 if (!cdev) 498 return cdev; 499 500 qed_init_struct(cdev); 501 502 return cdev; 503 } 504 505 /* Sets the requested power state */ 506 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 507 { 508 if (!cdev) 509 return -ENODEV; 510 511 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 512 return 0; 513 } 514 515 struct qed_devlink { 516 struct qed_dev *cdev; 517 }; 518 519 enum qed_devlink_param_id { 520 QED_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 521 QED_DEVLINK_PARAM_ID_IWARP_CMT, 522 }; 523 524 static int qed_dl_param_get(struct devlink *dl, u32 id, 525 struct devlink_param_gset_ctx *ctx) 526 { 527 struct qed_devlink *qed_dl; 528 struct qed_dev *cdev; 529 530 qed_dl = devlink_priv(dl); 531 cdev = qed_dl->cdev; 532 ctx->val.vbool = cdev->iwarp_cmt; 533 534 return 0; 535 } 536 537 static int qed_dl_param_set(struct devlink *dl, u32 id, 538 struct devlink_param_gset_ctx *ctx) 539 { 540 struct qed_devlink *qed_dl; 541 struct qed_dev *cdev; 542 543 qed_dl = devlink_priv(dl); 544 cdev = qed_dl->cdev; 545 cdev->iwarp_cmt = ctx->val.vbool; 546 547 return 0; 548 } 549 550 static const struct devlink_param qed_devlink_params[] = { 551 DEVLINK_PARAM_DRIVER(QED_DEVLINK_PARAM_ID_IWARP_CMT, 552 "iwarp_cmt", DEVLINK_PARAM_TYPE_BOOL, 553 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 554 qed_dl_param_get, qed_dl_param_set, NULL), 555 }; 556 557 static const struct devlink_ops qed_dl_ops; 558 559 static int qed_devlink_register(struct qed_dev *cdev) 560 { 561 union devlink_param_value value; 562 struct qed_devlink *qed_dl; 563 struct devlink *dl; 564 int rc; 565 566 dl = devlink_alloc(&qed_dl_ops, sizeof(*qed_dl)); 567 if (!dl) 568 return -ENOMEM; 569 570 qed_dl = devlink_priv(dl); 571 572 cdev->dl = dl; 573 qed_dl->cdev = cdev; 574 575 rc = devlink_register(dl, &cdev->pdev->dev); 576 if (rc) 577 goto err_free; 578 579 rc = devlink_params_register(dl, qed_devlink_params, 580 ARRAY_SIZE(qed_devlink_params)); 581 if (rc) 582 goto err_unregister; 583 584 value.vbool = false; 585 devlink_param_driverinit_value_set(dl, 586 QED_DEVLINK_PARAM_ID_IWARP_CMT, 587 value); 588 589 devlink_params_publish(dl); 590 cdev->iwarp_cmt = false; 591 592 return 0; 593 594 err_unregister: 595 devlink_unregister(dl); 596 597 err_free: 598 cdev->dl = NULL; 599 devlink_free(dl); 600 601 return rc; 602 } 603 604 static void qed_devlink_unregister(struct qed_dev *cdev) 605 { 606 if (!cdev->dl) 607 return; 608 609 devlink_params_unregister(cdev->dl, qed_devlink_params, 610 ARRAY_SIZE(qed_devlink_params)); 611 612 devlink_unregister(cdev->dl); 613 devlink_free(cdev->dl); 614 } 615 616 /* probing */ 617 static struct qed_dev *qed_probe(struct pci_dev *pdev, 618 struct qed_probe_params *params) 619 { 620 struct qed_dev *cdev; 621 int rc; 622 623 cdev = qed_alloc_cdev(pdev); 624 if (!cdev) 625 goto err0; 626 627 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 628 cdev->protocol = params->protocol; 629 630 if (params->is_vf) 631 cdev->b_is_vf = true; 632 633 qed_init_dp(cdev, params->dp_module, params->dp_level); 634 635 cdev->recov_in_prog = params->recov_in_prog; 636 637 rc = qed_init_pci(cdev, pdev); 638 if (rc) { 639 DP_ERR(cdev, "init pci failed\n"); 640 goto err1; 641 } 642 DP_INFO(cdev, "PCI init completed successfully\n"); 643 644 rc = qed_devlink_register(cdev); 645 if (rc) { 646 DP_INFO(cdev, "Failed to register devlink.\n"); 647 goto err2; 648 } 649 650 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 651 if (rc) { 652 DP_ERR(cdev, "hw prepare failed\n"); 653 goto err2; 654 } 655 656 DP_INFO(cdev, "qed_probe completed successfully\n"); 657 658 return cdev; 659 660 err2: 661 qed_free_pci(cdev); 662 err1: 663 qed_free_cdev(cdev); 664 err0: 665 return NULL; 666 } 667 668 static void qed_remove(struct qed_dev *cdev) 669 { 670 if (!cdev) 671 return; 672 673 qed_hw_remove(cdev); 674 675 qed_free_pci(cdev); 676 677 qed_set_power_state(cdev, PCI_D3hot); 678 679 qed_devlink_unregister(cdev); 680 681 qed_free_cdev(cdev); 682 } 683 684 static void qed_disable_msix(struct qed_dev *cdev) 685 { 686 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 687 pci_disable_msix(cdev->pdev); 688 kfree(cdev->int_params.msix_table); 689 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 690 pci_disable_msi(cdev->pdev); 691 } 692 693 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 694 } 695 696 static int qed_enable_msix(struct qed_dev *cdev, 697 struct qed_int_params *int_params) 698 { 699 int i, rc, cnt; 700 701 cnt = int_params->in.num_vectors; 702 703 for (i = 0; i < cnt; i++) 704 int_params->msix_table[i].entry = i; 705 706 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 707 int_params->in.min_msix_cnt, cnt); 708 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 709 (rc % cdev->num_hwfns)) { 710 pci_disable_msix(cdev->pdev); 711 712 /* If fastpath is initialized, we need at least one interrupt 713 * per hwfn [and the slow path interrupts]. New requested number 714 * should be a multiple of the number of hwfns. 715 */ 716 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 717 DP_NOTICE(cdev, 718 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 719 cnt, int_params->in.num_vectors); 720 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 721 cnt); 722 if (!rc) 723 rc = cnt; 724 } 725 726 if (rc > 0) { 727 /* MSI-x configuration was achieved */ 728 int_params->out.int_mode = QED_INT_MODE_MSIX; 729 int_params->out.num_vectors = rc; 730 rc = 0; 731 } else { 732 DP_NOTICE(cdev, 733 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 734 cnt, rc); 735 } 736 737 return rc; 738 } 739 740 /* This function outputs the int mode and the number of enabled msix vector */ 741 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 742 { 743 struct qed_int_params *int_params = &cdev->int_params; 744 struct msix_entry *tbl; 745 int rc = 0, cnt; 746 747 switch (int_params->in.int_mode) { 748 case QED_INT_MODE_MSIX: 749 /* Allocate MSIX table */ 750 cnt = int_params->in.num_vectors; 751 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 752 if (!int_params->msix_table) { 753 rc = -ENOMEM; 754 goto out; 755 } 756 757 /* Enable MSIX */ 758 rc = qed_enable_msix(cdev, int_params); 759 if (!rc) 760 goto out; 761 762 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 763 kfree(int_params->msix_table); 764 if (force_mode) 765 goto out; 766 fallthrough; 767 768 case QED_INT_MODE_MSI: 769 if (cdev->num_hwfns == 1) { 770 rc = pci_enable_msi(cdev->pdev); 771 if (!rc) { 772 int_params->out.int_mode = QED_INT_MODE_MSI; 773 goto out; 774 } 775 776 DP_NOTICE(cdev, "Failed to enable MSI\n"); 777 if (force_mode) 778 goto out; 779 } 780 fallthrough; 781 782 case QED_INT_MODE_INTA: 783 int_params->out.int_mode = QED_INT_MODE_INTA; 784 rc = 0; 785 goto out; 786 default: 787 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 788 int_params->in.int_mode); 789 rc = -EINVAL; 790 } 791 792 out: 793 if (!rc) 794 DP_INFO(cdev, "Using %s interrupts\n", 795 int_params->out.int_mode == QED_INT_MODE_INTA ? 796 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 797 "MSI" : "MSIX"); 798 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 799 800 return rc; 801 } 802 803 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 804 int index, void(*handler)(void *)) 805 { 806 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 807 int relative_idx = index / cdev->num_hwfns; 808 809 hwfn->simd_proto_handler[relative_idx].func = handler; 810 hwfn->simd_proto_handler[relative_idx].token = token; 811 } 812 813 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 814 { 815 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 816 int relative_idx = index / cdev->num_hwfns; 817 818 memset(&hwfn->simd_proto_handler[relative_idx], 0, 819 sizeof(struct qed_simd_fp_handler)); 820 } 821 822 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 823 { 824 tasklet_schedule((struct tasklet_struct *)tasklet); 825 return IRQ_HANDLED; 826 } 827 828 static irqreturn_t qed_single_int(int irq, void *dev_instance) 829 { 830 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 831 struct qed_hwfn *hwfn; 832 irqreturn_t rc = IRQ_NONE; 833 u64 status; 834 int i, j; 835 836 for (i = 0; i < cdev->num_hwfns; i++) { 837 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 838 839 if (!status) 840 continue; 841 842 hwfn = &cdev->hwfns[i]; 843 844 /* Slowpath interrupt */ 845 if (unlikely(status & 0x1)) { 846 tasklet_schedule(hwfn->sp_dpc); 847 status &= ~0x1; 848 rc = IRQ_HANDLED; 849 } 850 851 /* Fastpath interrupts */ 852 for (j = 0; j < 64; j++) { 853 if ((0x2ULL << j) & status) { 854 struct qed_simd_fp_handler *p_handler = 855 &hwfn->simd_proto_handler[j]; 856 857 if (p_handler->func) 858 p_handler->func(p_handler->token); 859 else 860 DP_NOTICE(hwfn, 861 "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n", 862 j, status); 863 864 status &= ~(0x2ULL << j); 865 rc = IRQ_HANDLED; 866 } 867 } 868 869 if (unlikely(status)) 870 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 871 "got an unknown interrupt status 0x%llx\n", 872 status); 873 } 874 875 return rc; 876 } 877 878 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 879 { 880 struct qed_dev *cdev = hwfn->cdev; 881 u32 int_mode; 882 int rc = 0; 883 u8 id; 884 885 int_mode = cdev->int_params.out.int_mode; 886 if (int_mode == QED_INT_MODE_MSIX) { 887 id = hwfn->my_id; 888 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 889 id, cdev->pdev->bus->number, 890 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 891 rc = request_irq(cdev->int_params.msix_table[id].vector, 892 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 893 } else { 894 unsigned long flags = 0; 895 896 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 897 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 898 PCI_FUNC(cdev->pdev->devfn)); 899 900 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 901 flags |= IRQF_SHARED; 902 903 rc = request_irq(cdev->pdev->irq, qed_single_int, 904 flags, cdev->name, cdev); 905 } 906 907 if (rc) 908 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 909 else 910 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 911 "Requested slowpath %s\n", 912 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 913 914 return rc; 915 } 916 917 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn) 918 { 919 /* Calling the disable function will make sure that any 920 * currently-running function is completed. The following call to the 921 * enable function makes this sequence a flush-like operation. 922 */ 923 if (p_hwfn->b_sp_dpc_enabled) { 924 tasklet_disable(p_hwfn->sp_dpc); 925 tasklet_enable(p_hwfn->sp_dpc); 926 } 927 } 928 929 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn) 930 { 931 struct qed_dev *cdev = p_hwfn->cdev; 932 u8 id = p_hwfn->my_id; 933 u32 int_mode; 934 935 int_mode = cdev->int_params.out.int_mode; 936 if (int_mode == QED_INT_MODE_MSIX) 937 synchronize_irq(cdev->int_params.msix_table[id].vector); 938 else 939 synchronize_irq(cdev->pdev->irq); 940 941 qed_slowpath_tasklet_flush(p_hwfn); 942 } 943 944 static void qed_slowpath_irq_free(struct qed_dev *cdev) 945 { 946 int i; 947 948 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 949 for_each_hwfn(cdev, i) { 950 if (!cdev->hwfns[i].b_int_requested) 951 break; 952 synchronize_irq(cdev->int_params.msix_table[i].vector); 953 free_irq(cdev->int_params.msix_table[i].vector, 954 cdev->hwfns[i].sp_dpc); 955 } 956 } else { 957 if (QED_LEADING_HWFN(cdev)->b_int_requested) 958 free_irq(cdev->pdev->irq, cdev); 959 } 960 qed_int_disable_post_isr_release(cdev); 961 } 962 963 static int qed_nic_stop(struct qed_dev *cdev) 964 { 965 int i, rc; 966 967 rc = qed_hw_stop(cdev); 968 969 for (i = 0; i < cdev->num_hwfns; i++) { 970 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 971 972 if (p_hwfn->b_sp_dpc_enabled) { 973 tasklet_disable(p_hwfn->sp_dpc); 974 p_hwfn->b_sp_dpc_enabled = false; 975 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 976 "Disabled sp tasklet [hwfn %d] at %p\n", 977 i, p_hwfn->sp_dpc); 978 } 979 } 980 981 qed_dbg_pf_exit(cdev); 982 983 return rc; 984 } 985 986 static int qed_nic_setup(struct qed_dev *cdev) 987 { 988 int rc, i; 989 990 /* Determine if interface is going to require LL2 */ 991 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 992 for (i = 0; i < cdev->num_hwfns; i++) { 993 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 994 995 p_hwfn->using_ll2 = true; 996 } 997 } 998 999 rc = qed_resc_alloc(cdev); 1000 if (rc) 1001 return rc; 1002 1003 DP_INFO(cdev, "Allocated qed resources\n"); 1004 1005 qed_resc_setup(cdev); 1006 1007 return rc; 1008 } 1009 1010 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 1011 { 1012 int limit = 0; 1013 1014 /* Mark the fastpath as free/used */ 1015 cdev->int_params.fp_initialized = cnt ? true : false; 1016 1017 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 1018 limit = cdev->num_hwfns * 63; 1019 else if (cdev->int_params.fp_msix_cnt) 1020 limit = cdev->int_params.fp_msix_cnt; 1021 1022 if (!limit) 1023 return -ENOMEM; 1024 1025 return min_t(int, cnt, limit); 1026 } 1027 1028 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 1029 { 1030 memset(info, 0, sizeof(struct qed_int_info)); 1031 1032 if (!cdev->int_params.fp_initialized) { 1033 DP_INFO(cdev, 1034 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 1035 return -EINVAL; 1036 } 1037 1038 /* Need to expose only MSI-X information; Single IRQ is handled solely 1039 * by qed. 1040 */ 1041 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 1042 int msix_base = cdev->int_params.fp_msix_base; 1043 1044 info->msix_cnt = cdev->int_params.fp_msix_cnt; 1045 info->msix = &cdev->int_params.msix_table[msix_base]; 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int qed_slowpath_setup_int(struct qed_dev *cdev, 1052 enum qed_int_mode int_mode) 1053 { 1054 struct qed_sb_cnt_info sb_cnt_info; 1055 int num_l2_queues = 0; 1056 int rc; 1057 int i; 1058 1059 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1060 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1061 return -EINVAL; 1062 } 1063 1064 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 1065 cdev->int_params.in.int_mode = int_mode; 1066 for_each_hwfn(cdev, i) { 1067 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 1068 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 1069 cdev->int_params.in.num_vectors += sb_cnt_info.cnt; 1070 cdev->int_params.in.num_vectors++; /* slowpath */ 1071 } 1072 1073 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 1074 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 1075 1076 if (is_kdump_kernel()) { 1077 DP_INFO(cdev, 1078 "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n", 1079 cdev->int_params.in.min_msix_cnt); 1080 cdev->int_params.in.num_vectors = 1081 cdev->int_params.in.min_msix_cnt; 1082 } 1083 1084 rc = qed_set_int_mode(cdev, false); 1085 if (rc) { 1086 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 1087 return rc; 1088 } 1089 1090 cdev->int_params.fp_msix_base = cdev->num_hwfns; 1091 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 1092 cdev->num_hwfns; 1093 1094 if (!IS_ENABLED(CONFIG_QED_RDMA) || 1095 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) 1096 return 0; 1097 1098 for_each_hwfn(cdev, i) 1099 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 1100 1101 DP_VERBOSE(cdev, QED_MSG_RDMA, 1102 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 1103 cdev->int_params.fp_msix_cnt, num_l2_queues); 1104 1105 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 1106 cdev->int_params.rdma_msix_cnt = 1107 (cdev->int_params.fp_msix_cnt - num_l2_queues) 1108 / cdev->num_hwfns; 1109 cdev->int_params.rdma_msix_base = 1110 cdev->int_params.fp_msix_base + num_l2_queues; 1111 cdev->int_params.fp_msix_cnt = num_l2_queues; 1112 } else { 1113 cdev->int_params.rdma_msix_cnt = 0; 1114 } 1115 1116 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 1117 cdev->int_params.rdma_msix_cnt, 1118 cdev->int_params.rdma_msix_base); 1119 1120 return 0; 1121 } 1122 1123 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 1124 { 1125 int rc; 1126 1127 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 1128 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 1129 1130 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 1131 &cdev->int_params.in.num_vectors); 1132 if (cdev->num_hwfns > 1) { 1133 u8 vectors = 0; 1134 1135 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 1136 cdev->int_params.in.num_vectors += vectors; 1137 } 1138 1139 /* We want a minimum of one fastpath vector per vf hwfn */ 1140 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 1141 1142 rc = qed_set_int_mode(cdev, true); 1143 if (rc) 1144 return rc; 1145 1146 cdev->int_params.fp_msix_base = 0; 1147 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 1148 1149 return 0; 1150 } 1151 1152 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 1153 u8 *input_buf, u32 max_size, u8 *unzip_buf) 1154 { 1155 int rc; 1156 1157 p_hwfn->stream->next_in = input_buf; 1158 p_hwfn->stream->avail_in = input_len; 1159 p_hwfn->stream->next_out = unzip_buf; 1160 p_hwfn->stream->avail_out = max_size; 1161 1162 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 1163 1164 if (rc != Z_OK) { 1165 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 1166 rc); 1167 return 0; 1168 } 1169 1170 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 1171 zlib_inflateEnd(p_hwfn->stream); 1172 1173 if (rc != Z_OK && rc != Z_STREAM_END) { 1174 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 1175 p_hwfn->stream->msg, rc); 1176 return 0; 1177 } 1178 1179 return p_hwfn->stream->total_out / 4; 1180 } 1181 1182 static int qed_alloc_stream_mem(struct qed_dev *cdev) 1183 { 1184 int i; 1185 void *workspace; 1186 1187 for_each_hwfn(cdev, i) { 1188 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1189 1190 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 1191 if (!p_hwfn->stream) 1192 return -ENOMEM; 1193 1194 workspace = vzalloc(zlib_inflate_workspacesize()); 1195 if (!workspace) 1196 return -ENOMEM; 1197 p_hwfn->stream->workspace = workspace; 1198 } 1199 1200 return 0; 1201 } 1202 1203 static void qed_free_stream_mem(struct qed_dev *cdev) 1204 { 1205 int i; 1206 1207 for_each_hwfn(cdev, i) { 1208 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1209 1210 if (!p_hwfn->stream) 1211 return; 1212 1213 vfree(p_hwfn->stream->workspace); 1214 kfree(p_hwfn->stream); 1215 } 1216 } 1217 1218 static void qed_update_pf_params(struct qed_dev *cdev, 1219 struct qed_pf_params *params) 1220 { 1221 int i; 1222 1223 if (IS_ENABLED(CONFIG_QED_RDMA)) { 1224 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 1225 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 1226 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS; 1227 /* divide by 3 the MRs to avoid MF ILT overflow */ 1228 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 1229 } 1230 1231 if (cdev->num_hwfns > 1 || IS_VF(cdev)) 1232 params->eth_pf_params.num_arfs_filters = 0; 1233 1234 /* In case we might support RDMA, don't allow qede to be greedy 1235 * with the L2 contexts. Allow for 64 queues [rx, tx cos, xdp] 1236 * per hwfn. 1237 */ 1238 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) { 1239 u16 *num_cons; 1240 1241 num_cons = ¶ms->eth_pf_params.num_cons; 1242 *num_cons = min_t(u16, *num_cons, QED_MAX_L2_CONS); 1243 } 1244 1245 for (i = 0; i < cdev->num_hwfns; i++) { 1246 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1247 1248 p_hwfn->pf_params = *params; 1249 } 1250 } 1251 1252 #define QED_PERIODIC_DB_REC_COUNT 10 1253 #define QED_PERIODIC_DB_REC_INTERVAL_MS 100 1254 #define QED_PERIODIC_DB_REC_INTERVAL \ 1255 msecs_to_jiffies(QED_PERIODIC_DB_REC_INTERVAL_MS) 1256 1257 static int qed_slowpath_delayed_work(struct qed_hwfn *hwfn, 1258 enum qed_slowpath_wq_flag wq_flag, 1259 unsigned long delay) 1260 { 1261 if (!hwfn->slowpath_wq_active) 1262 return -EINVAL; 1263 1264 /* Memory barrier for setting atomic bit */ 1265 smp_mb__before_atomic(); 1266 set_bit(wq_flag, &hwfn->slowpath_task_flags); 1267 smp_mb__after_atomic(); 1268 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, delay); 1269 1270 return 0; 1271 } 1272 1273 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn) 1274 { 1275 /* Reset periodic Doorbell Recovery counter */ 1276 p_hwfn->periodic_db_rec_count = QED_PERIODIC_DB_REC_COUNT; 1277 1278 /* Don't schedule periodic Doorbell Recovery if already scheduled */ 1279 if (test_bit(QED_SLOWPATH_PERIODIC_DB_REC, 1280 &p_hwfn->slowpath_task_flags)) 1281 return; 1282 1283 qed_slowpath_delayed_work(p_hwfn, QED_SLOWPATH_PERIODIC_DB_REC, 1284 QED_PERIODIC_DB_REC_INTERVAL); 1285 } 1286 1287 static void qed_slowpath_wq_stop(struct qed_dev *cdev) 1288 { 1289 int i; 1290 1291 if (IS_VF(cdev)) 1292 return; 1293 1294 for_each_hwfn(cdev, i) { 1295 if (!cdev->hwfns[i].slowpath_wq) 1296 continue; 1297 1298 /* Stop queuing new delayed works */ 1299 cdev->hwfns[i].slowpath_wq_active = false; 1300 1301 cancel_delayed_work(&cdev->hwfns[i].slowpath_task); 1302 destroy_workqueue(cdev->hwfns[i].slowpath_wq); 1303 } 1304 } 1305 1306 static void qed_slowpath_task(struct work_struct *work) 1307 { 1308 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn, 1309 slowpath_task.work); 1310 struct qed_ptt *ptt = qed_ptt_acquire(hwfn); 1311 1312 if (!ptt) { 1313 if (hwfn->slowpath_wq_active) 1314 queue_delayed_work(hwfn->slowpath_wq, 1315 &hwfn->slowpath_task, 0); 1316 1317 return; 1318 } 1319 1320 if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ, 1321 &hwfn->slowpath_task_flags)) 1322 qed_mfw_process_tlv_req(hwfn, ptt); 1323 1324 if (test_and_clear_bit(QED_SLOWPATH_PERIODIC_DB_REC, 1325 &hwfn->slowpath_task_flags)) { 1326 qed_db_rec_handler(hwfn, ptt); 1327 if (hwfn->periodic_db_rec_count--) 1328 qed_slowpath_delayed_work(hwfn, 1329 QED_SLOWPATH_PERIODIC_DB_REC, 1330 QED_PERIODIC_DB_REC_INTERVAL); 1331 } 1332 1333 qed_ptt_release(hwfn, ptt); 1334 } 1335 1336 static int qed_slowpath_wq_start(struct qed_dev *cdev) 1337 { 1338 struct qed_hwfn *hwfn; 1339 char name[NAME_SIZE]; 1340 int i; 1341 1342 if (IS_VF(cdev)) 1343 return 0; 1344 1345 for_each_hwfn(cdev, i) { 1346 hwfn = &cdev->hwfns[i]; 1347 1348 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x", 1349 cdev->pdev->bus->number, 1350 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 1351 1352 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0); 1353 if (!hwfn->slowpath_wq) { 1354 DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n"); 1355 return -ENOMEM; 1356 } 1357 1358 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task); 1359 hwfn->slowpath_wq_active = true; 1360 } 1361 1362 return 0; 1363 } 1364 1365 static int qed_slowpath_start(struct qed_dev *cdev, 1366 struct qed_slowpath_params *params) 1367 { 1368 struct qed_drv_load_params drv_load_params; 1369 struct qed_hw_init_params hw_init_params; 1370 struct qed_mcp_drv_version drv_version; 1371 struct qed_tunnel_info tunn_info; 1372 const u8 *data = NULL; 1373 struct qed_hwfn *hwfn; 1374 struct qed_ptt *p_ptt; 1375 int rc = -EINVAL; 1376 1377 if (qed_iov_wq_start(cdev)) 1378 goto err; 1379 1380 if (qed_slowpath_wq_start(cdev)) 1381 goto err; 1382 1383 if (IS_PF(cdev)) { 1384 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 1385 &cdev->pdev->dev); 1386 if (rc) { 1387 DP_NOTICE(cdev, 1388 "Failed to find fw file - /lib/firmware/%s\n", 1389 QED_FW_FILE_NAME); 1390 goto err; 1391 } 1392 1393 if (cdev->num_hwfns == 1) { 1394 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 1395 if (p_ptt) { 1396 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt; 1397 } else { 1398 DP_NOTICE(cdev, 1399 "Failed to acquire PTT for aRFS\n"); 1400 goto err; 1401 } 1402 } 1403 } 1404 1405 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; 1406 rc = qed_nic_setup(cdev); 1407 if (rc) 1408 goto err; 1409 1410 if (IS_PF(cdev)) 1411 rc = qed_slowpath_setup_int(cdev, params->int_mode); 1412 else 1413 rc = qed_slowpath_vf_setup_int(cdev); 1414 if (rc) 1415 goto err1; 1416 1417 if (IS_PF(cdev)) { 1418 /* Allocate stream for unzipping */ 1419 rc = qed_alloc_stream_mem(cdev); 1420 if (rc) 1421 goto err2; 1422 1423 /* First Dword used to differentiate between various sources */ 1424 data = cdev->firmware->data + sizeof(u32); 1425 1426 qed_dbg_pf_init(cdev); 1427 } 1428 1429 /* Start the slowpath */ 1430 memset(&hw_init_params, 0, sizeof(hw_init_params)); 1431 memset(&tunn_info, 0, sizeof(tunn_info)); 1432 tunn_info.vxlan.b_mode_enabled = true; 1433 tunn_info.l2_gre.b_mode_enabled = true; 1434 tunn_info.ip_gre.b_mode_enabled = true; 1435 tunn_info.l2_geneve.b_mode_enabled = true; 1436 tunn_info.ip_geneve.b_mode_enabled = true; 1437 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1438 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1439 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1440 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1441 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1442 hw_init_params.p_tunn = &tunn_info; 1443 hw_init_params.b_hw_start = true; 1444 hw_init_params.int_mode = cdev->int_params.out.int_mode; 1445 hw_init_params.allow_npar_tx_switch = true; 1446 hw_init_params.bin_fw_data = data; 1447 1448 memset(&drv_load_params, 0, sizeof(drv_load_params)); 1449 drv_load_params.is_crash_kernel = is_kdump_kernel(); 1450 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT; 1451 drv_load_params.avoid_eng_reset = false; 1452 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE; 1453 hw_init_params.p_drv_load_params = &drv_load_params; 1454 1455 rc = qed_hw_init(cdev, &hw_init_params); 1456 if (rc) 1457 goto err2; 1458 1459 DP_INFO(cdev, 1460 "HW initialization and function start completed successfully\n"); 1461 1462 if (IS_PF(cdev)) { 1463 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) | 1464 BIT(QED_MODE_L2GENEVE_TUNN) | 1465 BIT(QED_MODE_IPGENEVE_TUNN) | 1466 BIT(QED_MODE_L2GRE_TUNN) | 1467 BIT(QED_MODE_IPGRE_TUNN)); 1468 } 1469 1470 /* Allocate LL2 interface if needed */ 1471 if (QED_LEADING_HWFN(cdev)->using_ll2) { 1472 rc = qed_ll2_alloc_if(cdev); 1473 if (rc) 1474 goto err3; 1475 } 1476 if (IS_PF(cdev)) { 1477 hwfn = QED_LEADING_HWFN(cdev); 1478 drv_version.version = (params->drv_major << 24) | 1479 (params->drv_minor << 16) | 1480 (params->drv_rev << 8) | 1481 (params->drv_eng); 1482 strlcpy(drv_version.name, params->name, 1483 MCP_DRV_VER_STR_SIZE - 4); 1484 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 1485 &drv_version); 1486 if (rc) { 1487 DP_NOTICE(cdev, "Failed sending drv version command\n"); 1488 goto err4; 1489 } 1490 } 1491 1492 qed_reset_vport_stats(cdev); 1493 1494 return 0; 1495 1496 err4: 1497 qed_ll2_dealloc_if(cdev); 1498 err3: 1499 qed_hw_stop(cdev); 1500 err2: 1501 qed_hw_timers_stop_all(cdev); 1502 if (IS_PF(cdev)) 1503 qed_slowpath_irq_free(cdev); 1504 qed_free_stream_mem(cdev); 1505 qed_disable_msix(cdev); 1506 err1: 1507 qed_resc_free(cdev); 1508 err: 1509 if (IS_PF(cdev)) 1510 release_firmware(cdev->firmware); 1511 1512 if (IS_PF(cdev) && (cdev->num_hwfns == 1) && 1513 QED_LEADING_HWFN(cdev)->p_arfs_ptt) 1514 qed_ptt_release(QED_LEADING_HWFN(cdev), 1515 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1516 1517 qed_iov_wq_stop(cdev, false); 1518 1519 qed_slowpath_wq_stop(cdev); 1520 1521 return rc; 1522 } 1523 1524 static int qed_slowpath_stop(struct qed_dev *cdev) 1525 { 1526 if (!cdev) 1527 return -ENODEV; 1528 1529 qed_slowpath_wq_stop(cdev); 1530 1531 qed_ll2_dealloc_if(cdev); 1532 1533 if (IS_PF(cdev)) { 1534 if (cdev->num_hwfns == 1) 1535 qed_ptt_release(QED_LEADING_HWFN(cdev), 1536 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1537 qed_free_stream_mem(cdev); 1538 if (IS_QED_ETH_IF(cdev)) 1539 qed_sriov_disable(cdev, true); 1540 } 1541 1542 qed_nic_stop(cdev); 1543 1544 if (IS_PF(cdev)) 1545 qed_slowpath_irq_free(cdev); 1546 1547 qed_disable_msix(cdev); 1548 1549 qed_resc_free(cdev); 1550 1551 qed_iov_wq_stop(cdev, true); 1552 1553 if (IS_PF(cdev)) 1554 release_firmware(cdev->firmware); 1555 1556 return 0; 1557 } 1558 1559 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE]) 1560 { 1561 int i; 1562 1563 memcpy(cdev->name, name, NAME_SIZE); 1564 for_each_hwfn(cdev, i) 1565 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1566 } 1567 1568 static u32 qed_sb_init(struct qed_dev *cdev, 1569 struct qed_sb_info *sb_info, 1570 void *sb_virt_addr, 1571 dma_addr_t sb_phy_addr, u16 sb_id, 1572 enum qed_sb_type type) 1573 { 1574 struct qed_hwfn *p_hwfn; 1575 struct qed_ptt *p_ptt; 1576 u16 rel_sb_id; 1577 u32 rc; 1578 1579 /* RoCE/Storage use a single engine in CMT mode while L2 uses both */ 1580 if (type == QED_SB_TYPE_L2_QUEUE) { 1581 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns]; 1582 rel_sb_id = sb_id / cdev->num_hwfns; 1583 } else { 1584 p_hwfn = QED_AFFIN_HWFN(cdev); 1585 rel_sb_id = sb_id; 1586 } 1587 1588 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1589 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1590 IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id); 1591 1592 if (IS_PF(p_hwfn->cdev)) { 1593 p_ptt = qed_ptt_acquire(p_hwfn); 1594 if (!p_ptt) 1595 return -EBUSY; 1596 1597 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr, 1598 sb_phy_addr, rel_sb_id); 1599 qed_ptt_release(p_hwfn, p_ptt); 1600 } else { 1601 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr, 1602 sb_phy_addr, rel_sb_id); 1603 } 1604 1605 return rc; 1606 } 1607 1608 static u32 qed_sb_release(struct qed_dev *cdev, 1609 struct qed_sb_info *sb_info, 1610 u16 sb_id, 1611 enum qed_sb_type type) 1612 { 1613 struct qed_hwfn *p_hwfn; 1614 u16 rel_sb_id; 1615 u32 rc; 1616 1617 /* RoCE/Storage use a single engine in CMT mode while L2 uses both */ 1618 if (type == QED_SB_TYPE_L2_QUEUE) { 1619 p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns]; 1620 rel_sb_id = sb_id / cdev->num_hwfns; 1621 } else { 1622 p_hwfn = QED_AFFIN_HWFN(cdev); 1623 rel_sb_id = sb_id; 1624 } 1625 1626 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1627 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1628 IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id); 1629 1630 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1631 1632 return rc; 1633 } 1634 1635 static bool qed_can_link_change(struct qed_dev *cdev) 1636 { 1637 return true; 1638 } 1639 1640 static void qed_set_ext_speed_params(struct qed_mcp_link_params *link_params, 1641 const struct qed_link_params *params) 1642 { 1643 struct qed_mcp_link_speed_params *ext_speed = &link_params->ext_speed; 1644 const struct qed_mfw_speed_map *map; 1645 u32 i; 1646 1647 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1648 ext_speed->autoneg = !!params->autoneg; 1649 1650 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1651 ext_speed->advertised_speeds = 0; 1652 1653 for (i = 0; i < ARRAY_SIZE(qed_mfw_ext_maps); i++) { 1654 map = qed_mfw_ext_maps + i; 1655 1656 if (linkmode_intersects(params->adv_speeds, map->caps)) 1657 ext_speed->advertised_speeds |= map->mfw_val; 1658 } 1659 } 1660 1661 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) { 1662 switch (params->forced_speed) { 1663 case SPEED_1000: 1664 ext_speed->forced_speed = QED_EXT_SPEED_1G; 1665 break; 1666 case SPEED_10000: 1667 ext_speed->forced_speed = QED_EXT_SPEED_10G; 1668 break; 1669 case SPEED_20000: 1670 ext_speed->forced_speed = QED_EXT_SPEED_20G; 1671 break; 1672 case SPEED_25000: 1673 ext_speed->forced_speed = QED_EXT_SPEED_25G; 1674 break; 1675 case SPEED_40000: 1676 ext_speed->forced_speed = QED_EXT_SPEED_40G; 1677 break; 1678 case SPEED_50000: 1679 ext_speed->forced_speed = QED_EXT_SPEED_50G_R | 1680 QED_EXT_SPEED_50G_R2; 1681 break; 1682 case SPEED_100000: 1683 ext_speed->forced_speed = QED_EXT_SPEED_100G_R2 | 1684 QED_EXT_SPEED_100G_R4 | 1685 QED_EXT_SPEED_100G_P4; 1686 break; 1687 default: 1688 break; 1689 } 1690 } 1691 1692 if (!(params->override_flags & QED_LINK_OVERRIDE_FEC_CONFIG)) 1693 return; 1694 1695 switch (params->forced_speed) { 1696 case SPEED_25000: 1697 switch (params->fec) { 1698 case FEC_FORCE_MODE_NONE: 1699 link_params->ext_fec_mode = ETH_EXT_FEC_25G_NONE; 1700 break; 1701 case FEC_FORCE_MODE_FIRECODE: 1702 link_params->ext_fec_mode = ETH_EXT_FEC_25G_BASE_R; 1703 break; 1704 case FEC_FORCE_MODE_RS: 1705 link_params->ext_fec_mode = ETH_EXT_FEC_25G_RS528; 1706 break; 1707 case FEC_FORCE_MODE_AUTO: 1708 link_params->ext_fec_mode = ETH_EXT_FEC_25G_RS528 | 1709 ETH_EXT_FEC_25G_BASE_R | 1710 ETH_EXT_FEC_25G_NONE; 1711 break; 1712 default: 1713 break; 1714 } 1715 1716 break; 1717 case SPEED_40000: 1718 switch (params->fec) { 1719 case FEC_FORCE_MODE_NONE: 1720 link_params->ext_fec_mode = ETH_EXT_FEC_40G_NONE; 1721 break; 1722 case FEC_FORCE_MODE_FIRECODE: 1723 link_params->ext_fec_mode = ETH_EXT_FEC_40G_BASE_R; 1724 break; 1725 case FEC_FORCE_MODE_AUTO: 1726 link_params->ext_fec_mode = ETH_EXT_FEC_40G_BASE_R | 1727 ETH_EXT_FEC_40G_NONE; 1728 break; 1729 default: 1730 break; 1731 } 1732 1733 break; 1734 case SPEED_50000: 1735 switch (params->fec) { 1736 case FEC_FORCE_MODE_NONE: 1737 link_params->ext_fec_mode = ETH_EXT_FEC_50G_NONE; 1738 break; 1739 case FEC_FORCE_MODE_FIRECODE: 1740 link_params->ext_fec_mode = ETH_EXT_FEC_50G_BASE_R; 1741 break; 1742 case FEC_FORCE_MODE_RS: 1743 link_params->ext_fec_mode = ETH_EXT_FEC_50G_RS528; 1744 break; 1745 case FEC_FORCE_MODE_AUTO: 1746 link_params->ext_fec_mode = ETH_EXT_FEC_50G_RS528 | 1747 ETH_EXT_FEC_50G_BASE_R | 1748 ETH_EXT_FEC_50G_NONE; 1749 break; 1750 default: 1751 break; 1752 } 1753 1754 break; 1755 case SPEED_100000: 1756 switch (params->fec) { 1757 case FEC_FORCE_MODE_NONE: 1758 link_params->ext_fec_mode = ETH_EXT_FEC_100G_NONE; 1759 break; 1760 case FEC_FORCE_MODE_FIRECODE: 1761 link_params->ext_fec_mode = ETH_EXT_FEC_100G_BASE_R; 1762 break; 1763 case FEC_FORCE_MODE_RS: 1764 link_params->ext_fec_mode = ETH_EXT_FEC_100G_RS528; 1765 break; 1766 case FEC_FORCE_MODE_AUTO: 1767 link_params->ext_fec_mode = ETH_EXT_FEC_100G_RS528 | 1768 ETH_EXT_FEC_100G_BASE_R | 1769 ETH_EXT_FEC_100G_NONE; 1770 break; 1771 default: 1772 break; 1773 } 1774 1775 break; 1776 default: 1777 break; 1778 } 1779 } 1780 1781 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1782 { 1783 struct qed_mcp_link_params *link_params; 1784 struct qed_mcp_link_speed_params *speed; 1785 const struct qed_mfw_speed_map *map; 1786 struct qed_hwfn *hwfn; 1787 struct qed_ptt *ptt; 1788 int rc; 1789 u32 i; 1790 1791 if (!cdev) 1792 return -ENODEV; 1793 1794 /* The link should be set only once per PF */ 1795 hwfn = &cdev->hwfns[0]; 1796 1797 /* When VF wants to set link, force it to read the bulletin instead. 1798 * This mimics the PF behavior, where a noitification [both immediate 1799 * and possible later] would be generated when changing properties. 1800 */ 1801 if (IS_VF(cdev)) { 1802 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG); 1803 return 0; 1804 } 1805 1806 ptt = qed_ptt_acquire(hwfn); 1807 if (!ptt) 1808 return -EBUSY; 1809 1810 link_params = qed_mcp_get_link_params(hwfn); 1811 if (!link_params) 1812 return -ENODATA; 1813 1814 speed = &link_params->speed; 1815 1816 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1817 speed->autoneg = !!params->autoneg; 1818 1819 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1820 speed->advertised_speeds = 0; 1821 1822 for (i = 0; i < ARRAY_SIZE(qed_mfw_legacy_maps); i++) { 1823 map = qed_mfw_legacy_maps + i; 1824 1825 if (linkmode_intersects(params->adv_speeds, map->caps)) 1826 speed->advertised_speeds |= map->mfw_val; 1827 } 1828 } 1829 1830 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1831 speed->forced_speed = params->forced_speed; 1832 1833 if (qed_mcp_is_ext_speed_supported(hwfn)) 1834 qed_set_ext_speed_params(link_params, params); 1835 1836 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1837 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1838 link_params->pause.autoneg = true; 1839 else 1840 link_params->pause.autoneg = false; 1841 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1842 link_params->pause.forced_rx = true; 1843 else 1844 link_params->pause.forced_rx = false; 1845 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1846 link_params->pause.forced_tx = true; 1847 else 1848 link_params->pause.forced_tx = false; 1849 } 1850 1851 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1852 switch (params->loopback_mode) { 1853 case QED_LINK_LOOPBACK_INT_PHY: 1854 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1855 break; 1856 case QED_LINK_LOOPBACK_EXT_PHY: 1857 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1858 break; 1859 case QED_LINK_LOOPBACK_EXT: 1860 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1861 break; 1862 case QED_LINK_LOOPBACK_MAC: 1863 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1864 break; 1865 case QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123: 1866 link_params->loopback_mode = 1867 ETH_LOOPBACK_CNIG_AH_ONLY_0123; 1868 break; 1869 case QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301: 1870 link_params->loopback_mode = 1871 ETH_LOOPBACK_CNIG_AH_ONLY_2301; 1872 break; 1873 case QED_LINK_LOOPBACK_PCS_AH_ONLY: 1874 link_params->loopback_mode = ETH_LOOPBACK_PCS_AH_ONLY; 1875 break; 1876 case QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY: 1877 link_params->loopback_mode = 1878 ETH_LOOPBACK_REVERSE_MAC_AH_ONLY; 1879 break; 1880 case QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY: 1881 link_params->loopback_mode = 1882 ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY; 1883 break; 1884 default: 1885 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1886 break; 1887 } 1888 } 1889 1890 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG) 1891 memcpy(&link_params->eee, ¶ms->eee, 1892 sizeof(link_params->eee)); 1893 1894 if (params->override_flags & QED_LINK_OVERRIDE_FEC_CONFIG) 1895 link_params->fec = params->fec; 1896 1897 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1898 1899 qed_ptt_release(hwfn, ptt); 1900 1901 return rc; 1902 } 1903 1904 static int qed_get_port_type(u32 media_type) 1905 { 1906 int port_type; 1907 1908 switch (media_type) { 1909 case MEDIA_SFPP_10G_FIBER: 1910 case MEDIA_SFP_1G_FIBER: 1911 case MEDIA_XFP_FIBER: 1912 case MEDIA_MODULE_FIBER: 1913 port_type = PORT_FIBRE; 1914 break; 1915 case MEDIA_DA_TWINAX: 1916 port_type = PORT_DA; 1917 break; 1918 case MEDIA_BASE_T: 1919 port_type = PORT_TP; 1920 break; 1921 case MEDIA_KR: 1922 case MEDIA_NOT_PRESENT: 1923 port_type = PORT_NONE; 1924 break; 1925 case MEDIA_UNSPECIFIED: 1926 default: 1927 port_type = PORT_OTHER; 1928 break; 1929 } 1930 return port_type; 1931 } 1932 1933 static int qed_get_link_data(struct qed_hwfn *hwfn, 1934 struct qed_mcp_link_params *params, 1935 struct qed_mcp_link_state *link, 1936 struct qed_mcp_link_capabilities *link_caps) 1937 { 1938 void *p; 1939 1940 if (!IS_PF(hwfn->cdev)) { 1941 qed_vf_get_link_params(hwfn, params); 1942 qed_vf_get_link_state(hwfn, link); 1943 qed_vf_get_link_caps(hwfn, link_caps); 1944 1945 return 0; 1946 } 1947 1948 p = qed_mcp_get_link_params(hwfn); 1949 if (!p) 1950 return -ENXIO; 1951 memcpy(params, p, sizeof(*params)); 1952 1953 p = qed_mcp_get_link_state(hwfn); 1954 if (!p) 1955 return -ENXIO; 1956 memcpy(link, p, sizeof(*link)); 1957 1958 p = qed_mcp_get_link_capabilities(hwfn); 1959 if (!p) 1960 return -ENXIO; 1961 memcpy(link_caps, p, sizeof(*link_caps)); 1962 1963 return 0; 1964 } 1965 1966 static void qed_fill_link_capability(struct qed_hwfn *hwfn, 1967 struct qed_ptt *ptt, u32 capability, 1968 unsigned long *if_caps) 1969 { 1970 u32 media_type, tcvr_state, tcvr_type; 1971 u32 speed_mask, board_cfg; 1972 1973 if (qed_mcp_get_media_type(hwfn, ptt, &media_type)) 1974 media_type = MEDIA_UNSPECIFIED; 1975 1976 if (qed_mcp_get_transceiver_data(hwfn, ptt, &tcvr_state, &tcvr_type)) 1977 tcvr_type = ETH_TRANSCEIVER_STATE_UNPLUGGED; 1978 1979 if (qed_mcp_trans_speed_mask(hwfn, ptt, &speed_mask)) 1980 speed_mask = 0xFFFFFFFF; 1981 1982 if (qed_mcp_get_board_config(hwfn, ptt, &board_cfg)) 1983 board_cfg = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED; 1984 1985 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV, 1986 "Media_type = 0x%x tcvr_state = 0x%x tcvr_type = 0x%x speed_mask = 0x%x board_cfg = 0x%x\n", 1987 media_type, tcvr_state, tcvr_type, speed_mask, board_cfg); 1988 1989 switch (media_type) { 1990 case MEDIA_DA_TWINAX: 1991 phylink_set(if_caps, FIBRE); 1992 1993 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) 1994 phylink_set(if_caps, 20000baseKR2_Full); 1995 1996 /* For DAC media multiple speed capabilities are supported */ 1997 capability |= speed_mask; 1998 1999 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 2000 phylink_set(if_caps, 1000baseKX_Full); 2001 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 2002 phylink_set(if_caps, 10000baseCR_Full); 2003 2004 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 2005 switch (tcvr_type) { 2006 case ETH_TRANSCEIVER_TYPE_40G_CR4: 2007 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR: 2008 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2009 phylink_set(if_caps, 40000baseCR4_Full); 2010 break; 2011 default: 2012 break; 2013 } 2014 2015 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 2016 phylink_set(if_caps, 25000baseCR_Full); 2017 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 2018 phylink_set(if_caps, 50000baseCR2_Full); 2019 2020 if (capability & 2021 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 2022 switch (tcvr_type) { 2023 case ETH_TRANSCEIVER_TYPE_100G_CR4: 2024 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR: 2025 phylink_set(if_caps, 100000baseCR4_Full); 2026 break; 2027 default: 2028 break; 2029 } 2030 2031 break; 2032 case MEDIA_BASE_T: 2033 phylink_set(if_caps, TP); 2034 2035 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) { 2036 if (capability & 2037 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 2038 phylink_set(if_caps, 1000baseT_Full); 2039 if (capability & 2040 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 2041 phylink_set(if_caps, 10000baseT_Full); 2042 } 2043 2044 if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) { 2045 phylink_set(if_caps, FIBRE); 2046 2047 switch (tcvr_type) { 2048 case ETH_TRANSCEIVER_TYPE_1000BASET: 2049 phylink_set(if_caps, 1000baseT_Full); 2050 break; 2051 case ETH_TRANSCEIVER_TYPE_10G_BASET: 2052 phylink_set(if_caps, 10000baseT_Full); 2053 break; 2054 default: 2055 break; 2056 } 2057 } 2058 2059 break; 2060 case MEDIA_SFP_1G_FIBER: 2061 case MEDIA_SFPP_10G_FIBER: 2062 case MEDIA_XFP_FIBER: 2063 case MEDIA_MODULE_FIBER: 2064 phylink_set(if_caps, FIBRE); 2065 capability |= speed_mask; 2066 2067 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 2068 switch (tcvr_type) { 2069 case ETH_TRANSCEIVER_TYPE_1G_LX: 2070 case ETH_TRANSCEIVER_TYPE_1G_SX: 2071 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR: 2072 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR: 2073 phylink_set(if_caps, 1000baseKX_Full); 2074 break; 2075 default: 2076 break; 2077 } 2078 2079 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 2080 switch (tcvr_type) { 2081 case ETH_TRANSCEIVER_TYPE_10G_SR: 2082 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2083 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR: 2084 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR: 2085 phylink_set(if_caps, 10000baseSR_Full); 2086 break; 2087 case ETH_TRANSCEIVER_TYPE_10G_LR: 2088 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2089 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR: 2090 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR: 2091 phylink_set(if_caps, 10000baseLR_Full); 2092 break; 2093 case ETH_TRANSCEIVER_TYPE_10G_LRM: 2094 phylink_set(if_caps, 10000baseLRM_Full); 2095 break; 2096 case ETH_TRANSCEIVER_TYPE_10G_ER: 2097 phylink_set(if_caps, 10000baseR_FEC); 2098 break; 2099 default: 2100 break; 2101 } 2102 2103 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) 2104 phylink_set(if_caps, 20000baseKR2_Full); 2105 2106 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 2107 switch (tcvr_type) { 2108 case ETH_TRANSCEIVER_TYPE_25G_SR: 2109 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR: 2110 phylink_set(if_caps, 25000baseSR_Full); 2111 break; 2112 default: 2113 break; 2114 } 2115 2116 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 2117 switch (tcvr_type) { 2118 case ETH_TRANSCEIVER_TYPE_40G_LR4: 2119 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR: 2120 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2121 phylink_set(if_caps, 40000baseLR4_Full); 2122 break; 2123 case ETH_TRANSCEIVER_TYPE_40G_SR4: 2124 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2125 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR: 2126 phylink_set(if_caps, 40000baseSR4_Full); 2127 break; 2128 default: 2129 break; 2130 } 2131 2132 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 2133 phylink_set(if_caps, 50000baseKR2_Full); 2134 2135 if (capability & 2136 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 2137 switch (tcvr_type) { 2138 case ETH_TRANSCEIVER_TYPE_100G_SR4: 2139 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR: 2140 phylink_set(if_caps, 100000baseSR4_Full); 2141 break; 2142 case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR: 2143 phylink_set(if_caps, 100000baseLR4_ER4_Full); 2144 break; 2145 default: 2146 break; 2147 } 2148 2149 break; 2150 case MEDIA_KR: 2151 phylink_set(if_caps, Backplane); 2152 2153 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) 2154 phylink_set(if_caps, 20000baseKR2_Full); 2155 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 2156 phylink_set(if_caps, 1000baseKX_Full); 2157 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 2158 phylink_set(if_caps, 10000baseKR_Full); 2159 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 2160 phylink_set(if_caps, 25000baseKR_Full); 2161 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 2162 phylink_set(if_caps, 40000baseKR4_Full); 2163 if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 2164 phylink_set(if_caps, 50000baseKR2_Full); 2165 if (capability & 2166 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 2167 phylink_set(if_caps, 100000baseKR4_Full); 2168 2169 break; 2170 case MEDIA_UNSPECIFIED: 2171 case MEDIA_NOT_PRESENT: 2172 default: 2173 DP_VERBOSE(hwfn->cdev, QED_MSG_DEBUG, 2174 "Unknown media and transceiver type;\n"); 2175 break; 2176 } 2177 } 2178 2179 static void qed_lp_caps_to_speed_mask(u32 caps, u32 *speed_mask) 2180 { 2181 *speed_mask = 0; 2182 2183 if (caps & 2184 (QED_LINK_PARTNER_SPEED_1G_FD | QED_LINK_PARTNER_SPEED_1G_HD)) 2185 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 2186 if (caps & QED_LINK_PARTNER_SPEED_10G) 2187 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 2188 if (caps & QED_LINK_PARTNER_SPEED_20G) 2189 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G; 2190 if (caps & QED_LINK_PARTNER_SPEED_25G) 2191 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 2192 if (caps & QED_LINK_PARTNER_SPEED_40G) 2193 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 2194 if (caps & QED_LINK_PARTNER_SPEED_50G) 2195 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 2196 if (caps & QED_LINK_PARTNER_SPEED_100G) 2197 *speed_mask |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 2198 } 2199 2200 static void qed_fill_link(struct qed_hwfn *hwfn, 2201 struct qed_ptt *ptt, 2202 struct qed_link_output *if_link) 2203 { 2204 struct qed_mcp_link_capabilities link_caps; 2205 struct qed_mcp_link_params params; 2206 struct qed_mcp_link_state link; 2207 u32 media_type, speed_mask; 2208 2209 memset(if_link, 0, sizeof(*if_link)); 2210 2211 /* Prepare source inputs */ 2212 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 2213 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 2214 return; 2215 } 2216 2217 /* Set the link parameters to pass to protocol driver */ 2218 if (link.link_up) 2219 if_link->link_up = true; 2220 2221 if (IS_PF(hwfn->cdev) && qed_mcp_is_ext_speed_supported(hwfn)) { 2222 if (link_caps.default_ext_autoneg) 2223 phylink_set(if_link->supported_caps, Autoneg); 2224 2225 linkmode_copy(if_link->advertised_caps, if_link->supported_caps); 2226 2227 if (params.ext_speed.autoneg) 2228 phylink_set(if_link->advertised_caps, Autoneg); 2229 else 2230 phylink_clear(if_link->advertised_caps, Autoneg); 2231 2232 qed_fill_link_capability(hwfn, ptt, 2233 params.ext_speed.advertised_speeds, 2234 if_link->advertised_caps); 2235 } else { 2236 if (link_caps.default_speed_autoneg) 2237 phylink_set(if_link->supported_caps, Autoneg); 2238 2239 linkmode_copy(if_link->advertised_caps, if_link->supported_caps); 2240 2241 if (params.speed.autoneg) 2242 phylink_set(if_link->advertised_caps, Autoneg); 2243 else 2244 phylink_clear(if_link->advertised_caps, Autoneg); 2245 } 2246 2247 if (params.pause.autoneg || 2248 (params.pause.forced_rx && params.pause.forced_tx)) 2249 phylink_set(if_link->supported_caps, Asym_Pause); 2250 if (params.pause.autoneg || params.pause.forced_rx || 2251 params.pause.forced_tx) 2252 phylink_set(if_link->supported_caps, Pause); 2253 2254 if_link->sup_fec = link_caps.fec_default; 2255 if_link->active_fec = params.fec; 2256 2257 /* Fill link advertised capability */ 2258 qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds, 2259 if_link->advertised_caps); 2260 2261 /* Fill link supported capability */ 2262 qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities, 2263 if_link->supported_caps); 2264 2265 /* Fill partner advertised capability */ 2266 qed_lp_caps_to_speed_mask(link.partner_adv_speed, &speed_mask); 2267 qed_fill_link_capability(hwfn, ptt, speed_mask, if_link->lp_caps); 2268 2269 if (link.link_up) 2270 if_link->speed = link.speed; 2271 2272 /* TODO - fill duplex properly */ 2273 if_link->duplex = DUPLEX_FULL; 2274 qed_mcp_get_media_type(hwfn, ptt, &media_type); 2275 if_link->port = qed_get_port_type(media_type); 2276 2277 if_link->autoneg = params.speed.autoneg; 2278 2279 if (params.pause.autoneg) 2280 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 2281 if (params.pause.forced_rx) 2282 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 2283 if (params.pause.forced_tx) 2284 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 2285 2286 if (link.an_complete) 2287 phylink_set(if_link->lp_caps, Autoneg); 2288 if (link.partner_adv_pause) 2289 phylink_set(if_link->lp_caps, Pause); 2290 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 2291 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 2292 phylink_set(if_link->lp_caps, Asym_Pause); 2293 2294 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) { 2295 if_link->eee_supported = false; 2296 } else { 2297 if_link->eee_supported = true; 2298 if_link->eee_active = link.eee_active; 2299 if_link->sup_caps = link_caps.eee_speed_caps; 2300 /* MFW clears adv_caps on eee disable; use configured value */ 2301 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps : 2302 params.eee.adv_caps; 2303 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps; 2304 if_link->eee.enable = params.eee.enable; 2305 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable; 2306 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer; 2307 } 2308 } 2309 2310 static void qed_get_current_link(struct qed_dev *cdev, 2311 struct qed_link_output *if_link) 2312 { 2313 struct qed_hwfn *hwfn; 2314 struct qed_ptt *ptt; 2315 int i; 2316 2317 hwfn = &cdev->hwfns[0]; 2318 if (IS_PF(cdev)) { 2319 ptt = qed_ptt_acquire(hwfn); 2320 if (ptt) { 2321 qed_fill_link(hwfn, ptt, if_link); 2322 qed_ptt_release(hwfn, ptt); 2323 } else { 2324 DP_NOTICE(hwfn, "Failed to fill link; No PTT\n"); 2325 } 2326 } else { 2327 qed_fill_link(hwfn, NULL, if_link); 2328 } 2329 2330 for_each_hwfn(cdev, i) 2331 qed_inform_vf_link_state(&cdev->hwfns[i]); 2332 } 2333 2334 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt) 2335 { 2336 void *cookie = hwfn->cdev->ops_cookie; 2337 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 2338 struct qed_link_output if_link; 2339 2340 qed_fill_link(hwfn, ptt, &if_link); 2341 qed_inform_vf_link_state(hwfn); 2342 2343 if (IS_LEAD_HWFN(hwfn) && cookie) 2344 op->link_update(cookie, &if_link); 2345 } 2346 2347 void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt) 2348 { 2349 void *cookie = hwfn->cdev->ops_cookie; 2350 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 2351 2352 if (IS_LEAD_HWFN(hwfn) && cookie && op && op->bw_update) 2353 op->bw_update(cookie); 2354 } 2355 2356 static int qed_drain(struct qed_dev *cdev) 2357 { 2358 struct qed_hwfn *hwfn; 2359 struct qed_ptt *ptt; 2360 int i, rc; 2361 2362 if (IS_VF(cdev)) 2363 return 0; 2364 2365 for_each_hwfn(cdev, i) { 2366 hwfn = &cdev->hwfns[i]; 2367 ptt = qed_ptt_acquire(hwfn); 2368 if (!ptt) { 2369 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 2370 return -EBUSY; 2371 } 2372 rc = qed_mcp_drain(hwfn, ptt); 2373 qed_ptt_release(hwfn, ptt); 2374 if (rc) 2375 return rc; 2376 } 2377 2378 return 0; 2379 } 2380 2381 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev, 2382 struct qed_nvm_image_att *nvm_image, 2383 u32 *crc) 2384 { 2385 u8 *buf = NULL; 2386 int rc; 2387 2388 /* Allocate a buffer for holding the nvram image */ 2389 buf = kzalloc(nvm_image->length, GFP_KERNEL); 2390 if (!buf) 2391 return -ENOMEM; 2392 2393 /* Read image into buffer */ 2394 rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr, 2395 buf, nvm_image->length); 2396 if (rc) { 2397 DP_ERR(cdev, "Failed reading image from nvm\n"); 2398 goto out; 2399 } 2400 2401 /* Convert the buffer into big-endian format (excluding the 2402 * closing 4 bytes of CRC). 2403 */ 2404 cpu_to_be32_array((__force __be32 *)buf, (const u32 *)buf, 2405 DIV_ROUND_UP(nvm_image->length - 4, 4)); 2406 2407 /* Calc CRC for the "actual" image buffer, i.e. not including 2408 * the last 4 CRC bytes. 2409 */ 2410 *crc = ~crc32(~0U, buf, nvm_image->length - 4); 2411 *crc = (__force u32)cpu_to_be32p(crc); 2412 2413 out: 2414 kfree(buf); 2415 2416 return rc; 2417 } 2418 2419 /* Binary file format - 2420 * /----------------------------------------------------------------------\ 2421 * 0B | 0x4 [command index] | 2422 * 4B | image_type | Options | Number of register settings | 2423 * 8B | Value | 2424 * 12B | Mask | 2425 * 16B | Offset | 2426 * \----------------------------------------------------------------------/ 2427 * There can be several Value-Mask-Offset sets as specified by 'Number of...'. 2428 * Options - 0'b - Calculate & Update CRC for image 2429 */ 2430 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data, 2431 bool *check_resp) 2432 { 2433 struct qed_nvm_image_att nvm_image; 2434 struct qed_hwfn *p_hwfn; 2435 bool is_crc = false; 2436 u32 image_type; 2437 int rc = 0, i; 2438 u16 len; 2439 2440 *data += 4; 2441 image_type = **data; 2442 p_hwfn = QED_LEADING_HWFN(cdev); 2443 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 2444 if (image_type == p_hwfn->nvm_info.image_att[i].image_type) 2445 break; 2446 if (i == p_hwfn->nvm_info.num_images) { 2447 DP_ERR(cdev, "Failed to find nvram image of type %08x\n", 2448 image_type); 2449 return -ENOENT; 2450 } 2451 2452 nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 2453 nvm_image.length = p_hwfn->nvm_info.image_att[i].len; 2454 2455 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2456 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n", 2457 **data, image_type, nvm_image.start_addr, 2458 nvm_image.start_addr + nvm_image.length - 1); 2459 (*data)++; 2460 is_crc = !!(**data & BIT(0)); 2461 (*data)++; 2462 len = *((u16 *)*data); 2463 *data += 2; 2464 if (is_crc) { 2465 u32 crc = 0; 2466 2467 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc); 2468 if (rc) { 2469 DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc); 2470 goto exit; 2471 } 2472 2473 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 2474 (nvm_image.start_addr + 2475 nvm_image.length - 4), (u8 *)&crc, 4); 2476 if (rc) 2477 DP_ERR(cdev, "Failed writing to %08x, rc = %d\n", 2478 nvm_image.start_addr + nvm_image.length - 4, rc); 2479 goto exit; 2480 } 2481 2482 /* Iterate over the values for setting */ 2483 while (len) { 2484 u32 offset, mask, value, cur_value; 2485 u8 buf[4]; 2486 2487 value = *((u32 *)*data); 2488 *data += 4; 2489 mask = *((u32 *)*data); 2490 *data += 4; 2491 offset = *((u32 *)*data); 2492 *data += 4; 2493 2494 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf, 2495 4); 2496 if (rc) { 2497 DP_ERR(cdev, "Failed reading from %08x\n", 2498 nvm_image.start_addr + offset); 2499 goto exit; 2500 } 2501 2502 cur_value = le32_to_cpu(*((__le32 *)buf)); 2503 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2504 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n", 2505 nvm_image.start_addr + offset, cur_value, 2506 (cur_value & ~mask) | (value & mask), value, mask); 2507 value = (value & mask) | (cur_value & ~mask); 2508 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 2509 nvm_image.start_addr + offset, 2510 (u8 *)&value, 4); 2511 if (rc) { 2512 DP_ERR(cdev, "Failed writing to %08x\n", 2513 nvm_image.start_addr + offset); 2514 goto exit; 2515 } 2516 2517 len--; 2518 } 2519 exit: 2520 return rc; 2521 } 2522 2523 /* Binary file format - 2524 * /----------------------------------------------------------------------\ 2525 * 0B | 0x3 [command index] | 2526 * 4B | b'0: check_response? | b'1-31 reserved | 2527 * 8B | File-type | reserved | 2528 * 12B | Image length in bytes | 2529 * \----------------------------------------------------------------------/ 2530 * Start a new file of the provided type 2531 */ 2532 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev, 2533 const u8 **data, bool *check_resp) 2534 { 2535 u32 file_type, file_size = 0; 2536 int rc; 2537 2538 *data += 4; 2539 *check_resp = !!(**data & BIT(0)); 2540 *data += 4; 2541 file_type = **data; 2542 2543 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2544 "About to start a new file of type %02x\n", file_type); 2545 if (file_type == DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI) { 2546 *data += 4; 2547 file_size = *((u32 *)(*data)); 2548 } 2549 2550 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_BEGIN, file_type, 2551 (u8 *)(&file_size), 4); 2552 *data += 4; 2553 2554 return rc; 2555 } 2556 2557 /* Binary file format - 2558 * /----------------------------------------------------------------------\ 2559 * 0B | 0x2 [command index] | 2560 * 4B | Length in bytes | 2561 * 8B | b'0: check_response? | b'1-31 reserved | 2562 * 12B | Offset in bytes | 2563 * 16B | Data ... | 2564 * \----------------------------------------------------------------------/ 2565 * Write data as part of a file that was previously started. Data should be 2566 * of length equal to that provided in the message 2567 */ 2568 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev, 2569 const u8 **data, bool *check_resp) 2570 { 2571 u32 offset, len; 2572 int rc; 2573 2574 *data += 4; 2575 len = *((u32 *)(*data)); 2576 *data += 4; 2577 *check_resp = !!(**data & BIT(0)); 2578 *data += 4; 2579 offset = *((u32 *)(*data)); 2580 *data += 4; 2581 2582 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2583 "About to write File-data: %08x bytes to offset %08x\n", 2584 len, offset); 2585 2586 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset, 2587 (char *)(*data), len); 2588 *data += len; 2589 2590 return rc; 2591 } 2592 2593 /* Binary file format [General header] - 2594 * /----------------------------------------------------------------------\ 2595 * 0B | QED_NVM_SIGNATURE | 2596 * 4B | Length in bytes | 2597 * 8B | Highest command in this batchfile | Reserved | 2598 * \----------------------------------------------------------------------/ 2599 */ 2600 static int qed_nvm_flash_image_validate(struct qed_dev *cdev, 2601 const struct firmware *image, 2602 const u8 **data) 2603 { 2604 u32 signature, len; 2605 2606 /* Check minimum size */ 2607 if (image->size < 12) { 2608 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size); 2609 return -EINVAL; 2610 } 2611 2612 /* Check signature */ 2613 signature = *((u32 *)(*data)); 2614 if (signature != QED_NVM_SIGNATURE) { 2615 DP_ERR(cdev, "Wrong signature '%08x'\n", signature); 2616 return -EINVAL; 2617 } 2618 2619 *data += 4; 2620 /* Validate internal size equals the image-size */ 2621 len = *((u32 *)(*data)); 2622 if (len != image->size) { 2623 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n", 2624 len, (u32)image->size); 2625 return -EINVAL; 2626 } 2627 2628 *data += 4; 2629 /* Make sure driver familiar with all commands necessary for this */ 2630 if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) { 2631 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n", 2632 *((u16 *)(*data))); 2633 return -EINVAL; 2634 } 2635 2636 *data += 4; 2637 2638 return 0; 2639 } 2640 2641 /* Binary file format - 2642 * /----------------------------------------------------------------------\ 2643 * 0B | 0x5 [command index] | 2644 * 4B | Number of config attributes | Reserved | 2645 * 4B | Config ID | Entity ID | Length | 2646 * 4B | Value | 2647 * | | 2648 * \----------------------------------------------------------------------/ 2649 * There can be several cfg_id-entity_id-Length-Value sets as specified by 2650 * 'Number of config attributes'. 2651 * 2652 * The API parses config attributes from the user provided buffer and flashes 2653 * them to the respective NVM path using Management FW inerface. 2654 */ 2655 static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data) 2656 { 2657 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2658 u8 entity_id, len, buf[32]; 2659 bool need_nvm_init = true; 2660 struct qed_ptt *ptt; 2661 u16 cfg_id, count; 2662 int rc = 0, i; 2663 u32 flags; 2664 2665 ptt = qed_ptt_acquire(hwfn); 2666 if (!ptt) 2667 return -EAGAIN; 2668 2669 /* NVM CFG ID attribute header */ 2670 *data += 4; 2671 count = *((u16 *)*data); 2672 *data += 4; 2673 2674 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2675 "Read config ids: num_attrs = %0d\n", count); 2676 /* NVM CFG ID attributes. Start loop index from 1 to avoid additional 2677 * arithmetic operations in the implementation. 2678 */ 2679 for (i = 1; i <= count; i++) { 2680 cfg_id = *((u16 *)*data); 2681 *data += 2; 2682 entity_id = **data; 2683 (*data)++; 2684 len = **data; 2685 (*data)++; 2686 memcpy(buf, *data, len); 2687 *data += len; 2688 2689 flags = 0; 2690 if (need_nvm_init) { 2691 flags |= QED_NVM_CFG_OPTION_INIT; 2692 need_nvm_init = false; 2693 } 2694 2695 /* Commit to flash and free the resources */ 2696 if (!(i % QED_NVM_CFG_MAX_ATTRS) || i == count) { 2697 flags |= QED_NVM_CFG_OPTION_COMMIT | 2698 QED_NVM_CFG_OPTION_FREE; 2699 need_nvm_init = true; 2700 } 2701 2702 if (entity_id) 2703 flags |= QED_NVM_CFG_OPTION_ENTITY_SEL; 2704 2705 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2706 "cfg_id = %d entity = %d len = %d\n", cfg_id, 2707 entity_id, len); 2708 rc = qed_mcp_nvm_set_cfg(hwfn, ptt, cfg_id, entity_id, flags, 2709 buf, len); 2710 if (rc) { 2711 DP_ERR(cdev, "Error %d configuring %d\n", rc, cfg_id); 2712 break; 2713 } 2714 } 2715 2716 qed_ptt_release(hwfn, ptt); 2717 2718 return rc; 2719 } 2720 2721 #define QED_MAX_NVM_BUF_LEN 32 2722 static int qed_nvm_flash_cfg_len(struct qed_dev *cdev, u32 cmd) 2723 { 2724 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2725 u8 buf[QED_MAX_NVM_BUF_LEN]; 2726 struct qed_ptt *ptt; 2727 u32 len; 2728 int rc; 2729 2730 ptt = qed_ptt_acquire(hwfn); 2731 if (!ptt) 2732 return QED_MAX_NVM_BUF_LEN; 2733 2734 rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, 0, QED_NVM_CFG_GET_FLAGS, buf, 2735 &len); 2736 if (rc || !len) { 2737 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd); 2738 len = QED_MAX_NVM_BUF_LEN; 2739 } 2740 2741 qed_ptt_release(hwfn, ptt); 2742 2743 return len; 2744 } 2745 2746 static int qed_nvm_flash_cfg_read(struct qed_dev *cdev, u8 **data, 2747 u32 cmd, u32 entity_id) 2748 { 2749 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2750 struct qed_ptt *ptt; 2751 u32 flags, len; 2752 int rc = 0; 2753 2754 ptt = qed_ptt_acquire(hwfn); 2755 if (!ptt) 2756 return -EAGAIN; 2757 2758 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2759 "Read config cmd = %d entity id %d\n", cmd, entity_id); 2760 flags = entity_id ? QED_NVM_CFG_GET_PF_FLAGS : QED_NVM_CFG_GET_FLAGS; 2761 rc = qed_mcp_nvm_get_cfg(hwfn, ptt, cmd, entity_id, flags, *data, &len); 2762 if (rc) 2763 DP_ERR(cdev, "Error %d reading %d\n", rc, cmd); 2764 2765 qed_ptt_release(hwfn, ptt); 2766 2767 return rc; 2768 } 2769 2770 static int qed_nvm_flash(struct qed_dev *cdev, const char *name) 2771 { 2772 const struct firmware *image; 2773 const u8 *data, *data_end; 2774 u32 cmd_type; 2775 int rc; 2776 2777 rc = request_firmware(&image, name, &cdev->pdev->dev); 2778 if (rc) { 2779 DP_ERR(cdev, "Failed to find '%s'\n", name); 2780 return rc; 2781 } 2782 2783 DP_VERBOSE(cdev, NETIF_MSG_DRV, 2784 "Flashing '%s' - firmware's data at %p, size is %08x\n", 2785 name, image->data, (u32)image->size); 2786 data = image->data; 2787 data_end = data + image->size; 2788 2789 rc = qed_nvm_flash_image_validate(cdev, image, &data); 2790 if (rc) 2791 goto exit; 2792 2793 while (data < data_end) { 2794 bool check_resp = false; 2795 2796 /* Parse the actual command */ 2797 cmd_type = *((u32 *)data); 2798 switch (cmd_type) { 2799 case QED_NVM_FLASH_CMD_FILE_DATA: 2800 rc = qed_nvm_flash_image_file_data(cdev, &data, 2801 &check_resp); 2802 break; 2803 case QED_NVM_FLASH_CMD_FILE_START: 2804 rc = qed_nvm_flash_image_file_start(cdev, &data, 2805 &check_resp); 2806 break; 2807 case QED_NVM_FLASH_CMD_NVM_CHANGE: 2808 rc = qed_nvm_flash_image_access(cdev, &data, 2809 &check_resp); 2810 break; 2811 case QED_NVM_FLASH_CMD_NVM_CFG_ID: 2812 rc = qed_nvm_flash_cfg_write(cdev, &data); 2813 break; 2814 default: 2815 DP_ERR(cdev, "Unknown command %08x\n", cmd_type); 2816 rc = -EINVAL; 2817 goto exit; 2818 } 2819 2820 if (rc) { 2821 DP_ERR(cdev, "Command %08x failed\n", cmd_type); 2822 goto exit; 2823 } 2824 2825 /* Check response if needed */ 2826 if (check_resp) { 2827 u32 mcp_response = 0; 2828 2829 if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) { 2830 DP_ERR(cdev, "Failed getting MCP response\n"); 2831 rc = -EINVAL; 2832 goto exit; 2833 } 2834 2835 switch (mcp_response & FW_MSG_CODE_MASK) { 2836 case FW_MSG_CODE_OK: 2837 case FW_MSG_CODE_NVM_OK: 2838 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK: 2839 case FW_MSG_CODE_PHY_OK: 2840 break; 2841 default: 2842 DP_ERR(cdev, "MFW returns error: %08x\n", 2843 mcp_response); 2844 rc = -EINVAL; 2845 goto exit; 2846 } 2847 } 2848 } 2849 2850 exit: 2851 release_firmware(image); 2852 2853 return rc; 2854 } 2855 2856 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, 2857 u8 *buf, u16 len) 2858 { 2859 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2860 2861 return qed_mcp_get_nvm_image(hwfn, type, buf, len); 2862 } 2863 2864 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn) 2865 { 2866 struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common; 2867 void *cookie = p_hwfn->cdev->ops_cookie; 2868 2869 if (ops && ops->schedule_recovery_handler) 2870 ops->schedule_recovery_handler(cookie); 2871 } 2872 2873 static const char * const qed_hw_err_type_descr[] = { 2874 [QED_HW_ERR_FAN_FAIL] = "Fan Failure", 2875 [QED_HW_ERR_MFW_RESP_FAIL] = "MFW Response Failure", 2876 [QED_HW_ERR_HW_ATTN] = "HW Attention", 2877 [QED_HW_ERR_DMAE_FAIL] = "DMAE Failure", 2878 [QED_HW_ERR_RAMROD_FAIL] = "Ramrod Failure", 2879 [QED_HW_ERR_FW_ASSERT] = "FW Assertion", 2880 [QED_HW_ERR_LAST] = "Unknown", 2881 }; 2882 2883 void qed_hw_error_occurred(struct qed_hwfn *p_hwfn, 2884 enum qed_hw_err_type err_type) 2885 { 2886 struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common; 2887 void *cookie = p_hwfn->cdev->ops_cookie; 2888 const char *err_str; 2889 2890 if (err_type > QED_HW_ERR_LAST) 2891 err_type = QED_HW_ERR_LAST; 2892 err_str = qed_hw_err_type_descr[err_type]; 2893 2894 DP_NOTICE(p_hwfn, "HW error occurred [%s]\n", err_str); 2895 2896 /* Call the HW error handler of the protocol driver. 2897 * If it is not available - perform a minimal handling of preventing 2898 * HW attentions from being reasserted. 2899 */ 2900 if (ops && ops->schedule_hw_err_handler) 2901 ops->schedule_hw_err_handler(cookie, err_type); 2902 else 2903 qed_int_attn_clr_enable(p_hwfn->cdev, true); 2904 } 2905 2906 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 2907 void *handle) 2908 { 2909 return qed_set_queue_coalesce(rx_coal, tx_coal, handle); 2910 } 2911 2912 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 2913 { 2914 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2915 struct qed_ptt *ptt; 2916 int status = 0; 2917 2918 ptt = qed_ptt_acquire(hwfn); 2919 if (!ptt) 2920 return -EAGAIN; 2921 2922 status = qed_mcp_set_led(hwfn, ptt, mode); 2923 2924 qed_ptt_release(hwfn, ptt); 2925 2926 return status; 2927 } 2928 2929 static int qed_recovery_process(struct qed_dev *cdev) 2930 { 2931 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2932 struct qed_ptt *p_ptt; 2933 int rc = 0; 2934 2935 p_ptt = qed_ptt_acquire(p_hwfn); 2936 if (!p_ptt) 2937 return -EAGAIN; 2938 2939 rc = qed_start_recovery_process(p_hwfn, p_ptt); 2940 2941 qed_ptt_release(p_hwfn, p_ptt); 2942 2943 return rc; 2944 } 2945 2946 static int qed_update_wol(struct qed_dev *cdev, bool enabled) 2947 { 2948 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2949 struct qed_ptt *ptt; 2950 int rc = 0; 2951 2952 if (IS_VF(cdev)) 2953 return 0; 2954 2955 ptt = qed_ptt_acquire(hwfn); 2956 if (!ptt) 2957 return -EAGAIN; 2958 2959 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED 2960 : QED_OV_WOL_DISABLED); 2961 if (rc) 2962 goto out; 2963 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2964 2965 out: 2966 qed_ptt_release(hwfn, ptt); 2967 return rc; 2968 } 2969 2970 static int qed_update_drv_state(struct qed_dev *cdev, bool active) 2971 { 2972 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2973 struct qed_ptt *ptt; 2974 int status = 0; 2975 2976 if (IS_VF(cdev)) 2977 return 0; 2978 2979 ptt = qed_ptt_acquire(hwfn); 2980 if (!ptt) 2981 return -EAGAIN; 2982 2983 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ? 2984 QED_OV_DRIVER_STATE_ACTIVE : 2985 QED_OV_DRIVER_STATE_DISABLED); 2986 2987 qed_ptt_release(hwfn, ptt); 2988 2989 return status; 2990 } 2991 2992 static int qed_update_mac(struct qed_dev *cdev, u8 *mac) 2993 { 2994 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2995 struct qed_ptt *ptt; 2996 int status = 0; 2997 2998 if (IS_VF(cdev)) 2999 return 0; 3000 3001 ptt = qed_ptt_acquire(hwfn); 3002 if (!ptt) 3003 return -EAGAIN; 3004 3005 status = qed_mcp_ov_update_mac(hwfn, ptt, mac); 3006 if (status) 3007 goto out; 3008 3009 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 3010 3011 out: 3012 qed_ptt_release(hwfn, ptt); 3013 return status; 3014 } 3015 3016 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) 3017 { 3018 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 3019 struct qed_ptt *ptt; 3020 int status = 0; 3021 3022 if (IS_VF(cdev)) 3023 return 0; 3024 3025 ptt = qed_ptt_acquire(hwfn); 3026 if (!ptt) 3027 return -EAGAIN; 3028 3029 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu); 3030 if (status) 3031 goto out; 3032 3033 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 3034 3035 out: 3036 qed_ptt_release(hwfn, ptt); 3037 return status; 3038 } 3039 3040 static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf, 3041 u8 dev_addr, u32 offset, u32 len) 3042 { 3043 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 3044 struct qed_ptt *ptt; 3045 int rc = 0; 3046 3047 if (IS_VF(cdev)) 3048 return 0; 3049 3050 ptt = qed_ptt_acquire(hwfn); 3051 if (!ptt) 3052 return -EAGAIN; 3053 3054 rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr, 3055 offset, len, buf); 3056 3057 qed_ptt_release(hwfn, ptt); 3058 3059 return rc; 3060 } 3061 3062 static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val) 3063 { 3064 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 3065 struct qed_ptt *ptt; 3066 int rc = 0; 3067 3068 if (IS_VF(cdev)) 3069 return 0; 3070 3071 ptt = qed_ptt_acquire(hwfn); 3072 if (!ptt) 3073 return -EAGAIN; 3074 3075 rc = qed_dbg_grc_config(hwfn, cfg_id, val); 3076 3077 qed_ptt_release(hwfn, ptt); 3078 3079 return rc; 3080 } 3081 3082 static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev) 3083 { 3084 return QED_AFFIN_HWFN_IDX(cdev); 3085 } 3086 3087 static struct qed_selftest_ops qed_selftest_ops_pass = { 3088 .selftest_memory = &qed_selftest_memory, 3089 .selftest_interrupt = &qed_selftest_interrupt, 3090 .selftest_register = &qed_selftest_register, 3091 .selftest_clock = &qed_selftest_clock, 3092 .selftest_nvram = &qed_selftest_nvram, 3093 }; 3094 3095 const struct qed_common_ops qed_common_ops_pass = { 3096 .selftest = &qed_selftest_ops_pass, 3097 .probe = &qed_probe, 3098 .remove = &qed_remove, 3099 .set_power_state = &qed_set_power_state, 3100 .set_name = &qed_set_name, 3101 .update_pf_params = &qed_update_pf_params, 3102 .slowpath_start = &qed_slowpath_start, 3103 .slowpath_stop = &qed_slowpath_stop, 3104 .set_fp_int = &qed_set_int_fp, 3105 .get_fp_int = &qed_get_int_fp, 3106 .sb_init = &qed_sb_init, 3107 .sb_release = &qed_sb_release, 3108 .simd_handler_config = &qed_simd_handler_config, 3109 .simd_handler_clean = &qed_simd_handler_clean, 3110 .dbg_grc = &qed_dbg_grc, 3111 .dbg_grc_size = &qed_dbg_grc_size, 3112 .can_link_change = &qed_can_link_change, 3113 .set_link = &qed_set_link, 3114 .get_link = &qed_get_current_link, 3115 .drain = &qed_drain, 3116 .update_msglvl = &qed_init_dp, 3117 .dbg_all_data = &qed_dbg_all_data, 3118 .dbg_all_data_size = &qed_dbg_all_data_size, 3119 .chain_alloc = &qed_chain_alloc, 3120 .chain_free = &qed_chain_free, 3121 .nvm_flash = &qed_nvm_flash, 3122 .nvm_get_image = &qed_nvm_get_image, 3123 .set_coalesce = &qed_set_coalesce, 3124 .set_led = &qed_set_led, 3125 .recovery_process = &qed_recovery_process, 3126 .recovery_prolog = &qed_recovery_prolog, 3127 .attn_clr_enable = &qed_int_attn_clr_enable, 3128 .update_drv_state = &qed_update_drv_state, 3129 .update_mac = &qed_update_mac, 3130 .update_mtu = &qed_update_mtu, 3131 .update_wol = &qed_update_wol, 3132 .db_recovery_add = &qed_db_recovery_add, 3133 .db_recovery_del = &qed_db_recovery_del, 3134 .read_module_eeprom = &qed_read_module_eeprom, 3135 .get_affin_hwfn_idx = &qed_get_affin_hwfn_idx, 3136 .read_nvm_cfg = &qed_nvm_flash_cfg_read, 3137 .read_nvm_cfg_len = &qed_nvm_flash_cfg_len, 3138 .set_grc_config = &qed_set_grc_config, 3139 }; 3140 3141 void qed_get_protocol_stats(struct qed_dev *cdev, 3142 enum qed_mcp_protocol_type type, 3143 union qed_mcp_protocol_stats *stats) 3144 { 3145 struct qed_eth_stats eth_stats; 3146 3147 memset(stats, 0, sizeof(*stats)); 3148 3149 switch (type) { 3150 case QED_MCP_LAN_STATS: 3151 qed_get_vport_stats(cdev, ð_stats); 3152 stats->lan_stats.ucast_rx_pkts = 3153 eth_stats.common.rx_ucast_pkts; 3154 stats->lan_stats.ucast_tx_pkts = 3155 eth_stats.common.tx_ucast_pkts; 3156 stats->lan_stats.fcs_err = -1; 3157 break; 3158 case QED_MCP_FCOE_STATS: 3159 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats); 3160 break; 3161 case QED_MCP_ISCSI_STATS: 3162 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats); 3163 break; 3164 default: 3165 DP_VERBOSE(cdev, QED_MSG_SP, 3166 "Invalid protocol type = %d\n", type); 3167 return; 3168 } 3169 } 3170 3171 int qed_mfw_tlv_req(struct qed_hwfn *hwfn) 3172 { 3173 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV, 3174 "Scheduling slowpath task [Flag: %d]\n", 3175 QED_SLOWPATH_MFW_TLV_REQ); 3176 smp_mb__before_atomic(); 3177 set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags); 3178 smp_mb__after_atomic(); 3179 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); 3180 3181 return 0; 3182 } 3183 3184 static void 3185 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv) 3186 { 3187 struct qed_common_cb_ops *op = cdev->protocol_ops.common; 3188 struct qed_eth_stats_common *p_common; 3189 struct qed_generic_tlvs gen_tlvs; 3190 struct qed_eth_stats stats; 3191 int i; 3192 3193 memset(&gen_tlvs, 0, sizeof(gen_tlvs)); 3194 op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs); 3195 3196 if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM) 3197 tlv->flags.ipv4_csum_offload = true; 3198 if (gen_tlvs.feat_flags & QED_TLV_LSO) 3199 tlv->flags.lso_supported = true; 3200 tlv->flags.b_set = true; 3201 3202 for (i = 0; i < QED_TLV_MAC_COUNT; i++) { 3203 if (is_valid_ether_addr(gen_tlvs.mac[i])) { 3204 ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]); 3205 tlv->mac_set[i] = true; 3206 } 3207 } 3208 3209 qed_get_vport_stats(cdev, &stats); 3210 p_common = &stats.common; 3211 tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts + 3212 p_common->rx_bcast_pkts; 3213 tlv->rx_frames_set = true; 3214 tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes + 3215 p_common->rx_bcast_bytes; 3216 tlv->rx_bytes_set = true; 3217 tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts + 3218 p_common->tx_bcast_pkts; 3219 tlv->tx_frames_set = true; 3220 tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes + 3221 p_common->tx_bcast_bytes; 3222 tlv->rx_bytes_set = true; 3223 } 3224 3225 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type, 3226 union qed_mfw_tlv_data *tlv_buf) 3227 { 3228 struct qed_dev *cdev = hwfn->cdev; 3229 struct qed_common_cb_ops *ops; 3230 3231 ops = cdev->protocol_ops.common; 3232 if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) { 3233 DP_NOTICE(hwfn, "Can't collect TLV management info\n"); 3234 return -EINVAL; 3235 } 3236 3237 switch (type) { 3238 case QED_MFW_TLV_GENERIC: 3239 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic); 3240 break; 3241 case QED_MFW_TLV_ETH: 3242 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth); 3243 break; 3244 case QED_MFW_TLV_FCOE: 3245 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe); 3246 break; 3247 case QED_MFW_TLV_ISCSI: 3248 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi); 3249 break; 3250 default: 3251 break; 3252 } 3253 3254 return 0; 3255 } 3256