1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/stddef.h> 34 #include <linux/pci.h> 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/string.h> 41 #include <linux/module.h> 42 #include <linux/interrupt.h> 43 #include <linux/workqueue.h> 44 #include <linux/ethtool.h> 45 #include <linux/etherdevice.h> 46 #include <linux/vmalloc.h> 47 #include <linux/crash_dump.h> 48 #include <linux/crc32.h> 49 #include <linux/qed/qed_if.h> 50 #include <linux/qed/qed_ll2_if.h> 51 52 #include "qed.h" 53 #include "qed_sriov.h" 54 #include "qed_sp.h" 55 #include "qed_dev_api.h" 56 #include "qed_ll2.h" 57 #include "qed_fcoe.h" 58 #include "qed_iscsi.h" 59 60 #include "qed_mcp.h" 61 #include "qed_hw.h" 62 #include "qed_selftest.h" 63 #include "qed_debug.h" 64 65 #define QED_ROCE_QPS (8192) 66 #define QED_ROCE_DPIS (8) 67 68 static char version[] = 69 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 70 71 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 72 MODULE_LICENSE("GPL"); 73 MODULE_VERSION(DRV_MODULE_VERSION); 74 75 #define FW_FILE_VERSION \ 76 __stringify(FW_MAJOR_VERSION) "." \ 77 __stringify(FW_MINOR_VERSION) "." \ 78 __stringify(FW_REVISION_VERSION) "." \ 79 __stringify(FW_ENGINEERING_VERSION) 80 81 #define QED_FW_FILE_NAME \ 82 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 83 84 MODULE_FIRMWARE(QED_FW_FILE_NAME); 85 86 static int __init qed_init(void) 87 { 88 pr_info("%s", version); 89 90 return 0; 91 } 92 93 static void __exit qed_cleanup(void) 94 { 95 pr_notice("qed_cleanup called\n"); 96 } 97 98 module_init(qed_init); 99 module_exit(qed_cleanup); 100 101 /* Check if the DMA controller on the machine can properly handle the DMA 102 * addressing required by the device. 103 */ 104 static int qed_set_coherency_mask(struct qed_dev *cdev) 105 { 106 struct device *dev = &cdev->pdev->dev; 107 108 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 109 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 110 DP_NOTICE(cdev, 111 "Can't request 64-bit consistent allocations\n"); 112 return -EIO; 113 } 114 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 115 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 116 return -EIO; 117 } 118 119 return 0; 120 } 121 122 static void qed_free_pci(struct qed_dev *cdev) 123 { 124 struct pci_dev *pdev = cdev->pdev; 125 126 if (cdev->doorbells && cdev->db_size) 127 iounmap(cdev->doorbells); 128 if (cdev->regview) 129 iounmap(cdev->regview); 130 if (atomic_read(&pdev->enable_cnt) == 1) 131 pci_release_regions(pdev); 132 133 pci_disable_device(pdev); 134 } 135 136 #define PCI_REVISION_ID_ERROR_VAL 0xff 137 138 /* Performs PCI initializations as well as initializing PCI-related parameters 139 * in the device structrue. Returns 0 in case of success. 140 */ 141 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 142 { 143 u8 rev_id; 144 int rc; 145 146 cdev->pdev = pdev; 147 148 rc = pci_enable_device(pdev); 149 if (rc) { 150 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 151 goto err0; 152 } 153 154 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 155 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 156 rc = -EIO; 157 goto err1; 158 } 159 160 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 161 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 162 rc = -EIO; 163 goto err1; 164 } 165 166 if (atomic_read(&pdev->enable_cnt) == 1) { 167 rc = pci_request_regions(pdev, "qed"); 168 if (rc) { 169 DP_NOTICE(cdev, 170 "Failed to request PCI memory resources\n"); 171 goto err1; 172 } 173 pci_set_master(pdev); 174 pci_save_state(pdev); 175 } 176 177 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 178 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 179 DP_NOTICE(cdev, 180 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 181 rev_id); 182 rc = -ENODEV; 183 goto err2; 184 } 185 if (!pci_is_pcie(pdev)) { 186 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 187 rc = -EIO; 188 goto err2; 189 } 190 191 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 192 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 193 DP_NOTICE(cdev, "Cannot find power management capability\n"); 194 195 rc = qed_set_coherency_mask(cdev); 196 if (rc) 197 goto err2; 198 199 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 200 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 201 cdev->pci_params.irq = pdev->irq; 202 203 cdev->regview = pci_ioremap_bar(pdev, 0); 204 if (!cdev->regview) { 205 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 206 rc = -ENOMEM; 207 goto err2; 208 } 209 210 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 211 cdev->db_size = pci_resource_len(cdev->pdev, 2); 212 if (!cdev->db_size) { 213 if (IS_PF(cdev)) { 214 DP_NOTICE(cdev, "No Doorbell bar available\n"); 215 return -EINVAL; 216 } else { 217 return 0; 218 } 219 } 220 221 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 222 223 if (!cdev->doorbells) { 224 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 225 return -ENOMEM; 226 } 227 228 return 0; 229 230 err2: 231 pci_release_regions(pdev); 232 err1: 233 pci_disable_device(pdev); 234 err0: 235 return rc; 236 } 237 238 int qed_fill_dev_info(struct qed_dev *cdev, 239 struct qed_dev_info *dev_info) 240 { 241 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 242 struct qed_hw_info *hw_info = &p_hwfn->hw_info; 243 struct qed_tunnel_info *tun = &cdev->tunnel; 244 struct qed_ptt *ptt; 245 246 memset(dev_info, 0, sizeof(struct qed_dev_info)); 247 248 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 249 tun->vxlan.b_mode_enabled) 250 dev_info->vxlan_enable = true; 251 252 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled && 253 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 254 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 255 dev_info->gre_enable = true; 256 257 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled && 258 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 259 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 260 dev_info->geneve_enable = true; 261 262 dev_info->num_hwfns = cdev->num_hwfns; 263 dev_info->pci_mem_start = cdev->pci_params.mem_start; 264 dev_info->pci_mem_end = cdev->pci_params.mem_end; 265 dev_info->pci_irq = cdev->pci_params.irq; 266 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn); 267 dev_info->dev_type = cdev->type; 268 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr); 269 270 if (IS_PF(cdev)) { 271 dev_info->fw_major = FW_MAJOR_VERSION; 272 dev_info->fw_minor = FW_MINOR_VERSION; 273 dev_info->fw_rev = FW_REVISION_VERSION; 274 dev_info->fw_eng = FW_ENGINEERING_VERSION; 275 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH, 276 &cdev->mf_bits); 277 dev_info->tx_switching = true; 278 279 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME) 280 dev_info->wol_support = true; 281 282 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id; 283 } else { 284 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 285 &dev_info->fw_minor, &dev_info->fw_rev, 286 &dev_info->fw_eng); 287 } 288 289 if (IS_PF(cdev)) { 290 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 291 if (ptt) { 292 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 293 &dev_info->mfw_rev, NULL); 294 295 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt, 296 &dev_info->mbi_version); 297 298 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 299 &dev_info->flash_size); 300 301 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 302 } 303 } else { 304 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 305 &dev_info->mfw_rev, NULL); 306 } 307 308 dev_info->mtu = hw_info->mtu; 309 310 return 0; 311 } 312 313 static void qed_free_cdev(struct qed_dev *cdev) 314 { 315 kfree((void *)cdev); 316 } 317 318 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 319 { 320 struct qed_dev *cdev; 321 322 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 323 if (!cdev) 324 return cdev; 325 326 qed_init_struct(cdev); 327 328 return cdev; 329 } 330 331 /* Sets the requested power state */ 332 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 333 { 334 if (!cdev) 335 return -ENODEV; 336 337 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 338 return 0; 339 } 340 341 /* probing */ 342 static struct qed_dev *qed_probe(struct pci_dev *pdev, 343 struct qed_probe_params *params) 344 { 345 struct qed_dev *cdev; 346 int rc; 347 348 cdev = qed_alloc_cdev(pdev); 349 if (!cdev) 350 goto err0; 351 352 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 353 cdev->protocol = params->protocol; 354 355 if (params->is_vf) 356 cdev->b_is_vf = true; 357 358 qed_init_dp(cdev, params->dp_module, params->dp_level); 359 360 rc = qed_init_pci(cdev, pdev); 361 if (rc) { 362 DP_ERR(cdev, "init pci failed\n"); 363 goto err1; 364 } 365 DP_INFO(cdev, "PCI init completed successfully\n"); 366 367 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 368 if (rc) { 369 DP_ERR(cdev, "hw prepare failed\n"); 370 goto err2; 371 } 372 373 DP_INFO(cdev, "qed_probe completed successffuly\n"); 374 375 return cdev; 376 377 err2: 378 qed_free_pci(cdev); 379 err1: 380 qed_free_cdev(cdev); 381 err0: 382 return NULL; 383 } 384 385 static void qed_remove(struct qed_dev *cdev) 386 { 387 if (!cdev) 388 return; 389 390 qed_hw_remove(cdev); 391 392 qed_free_pci(cdev); 393 394 qed_set_power_state(cdev, PCI_D3hot); 395 396 qed_free_cdev(cdev); 397 } 398 399 static void qed_disable_msix(struct qed_dev *cdev) 400 { 401 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 402 pci_disable_msix(cdev->pdev); 403 kfree(cdev->int_params.msix_table); 404 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 405 pci_disable_msi(cdev->pdev); 406 } 407 408 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 409 } 410 411 static int qed_enable_msix(struct qed_dev *cdev, 412 struct qed_int_params *int_params) 413 { 414 int i, rc, cnt; 415 416 cnt = int_params->in.num_vectors; 417 418 for (i = 0; i < cnt; i++) 419 int_params->msix_table[i].entry = i; 420 421 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 422 int_params->in.min_msix_cnt, cnt); 423 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 424 (rc % cdev->num_hwfns)) { 425 pci_disable_msix(cdev->pdev); 426 427 /* If fastpath is initialized, we need at least one interrupt 428 * per hwfn [and the slow path interrupts]. New requested number 429 * should be a multiple of the number of hwfns. 430 */ 431 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 432 DP_NOTICE(cdev, 433 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 434 cnt, int_params->in.num_vectors); 435 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 436 cnt); 437 if (!rc) 438 rc = cnt; 439 } 440 441 if (rc > 0) { 442 /* MSI-x configuration was achieved */ 443 int_params->out.int_mode = QED_INT_MODE_MSIX; 444 int_params->out.num_vectors = rc; 445 rc = 0; 446 } else { 447 DP_NOTICE(cdev, 448 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 449 cnt, rc); 450 } 451 452 return rc; 453 } 454 455 /* This function outputs the int mode and the number of enabled msix vector */ 456 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 457 { 458 struct qed_int_params *int_params = &cdev->int_params; 459 struct msix_entry *tbl; 460 int rc = 0, cnt; 461 462 switch (int_params->in.int_mode) { 463 case QED_INT_MODE_MSIX: 464 /* Allocate MSIX table */ 465 cnt = int_params->in.num_vectors; 466 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 467 if (!int_params->msix_table) { 468 rc = -ENOMEM; 469 goto out; 470 } 471 472 /* Enable MSIX */ 473 rc = qed_enable_msix(cdev, int_params); 474 if (!rc) 475 goto out; 476 477 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 478 kfree(int_params->msix_table); 479 if (force_mode) 480 goto out; 481 /* Fallthrough */ 482 483 case QED_INT_MODE_MSI: 484 if (cdev->num_hwfns == 1) { 485 rc = pci_enable_msi(cdev->pdev); 486 if (!rc) { 487 int_params->out.int_mode = QED_INT_MODE_MSI; 488 goto out; 489 } 490 491 DP_NOTICE(cdev, "Failed to enable MSI\n"); 492 if (force_mode) 493 goto out; 494 } 495 /* Fallthrough */ 496 497 case QED_INT_MODE_INTA: 498 int_params->out.int_mode = QED_INT_MODE_INTA; 499 rc = 0; 500 goto out; 501 default: 502 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 503 int_params->in.int_mode); 504 rc = -EINVAL; 505 } 506 507 out: 508 if (!rc) 509 DP_INFO(cdev, "Using %s interrupts\n", 510 int_params->out.int_mode == QED_INT_MODE_INTA ? 511 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 512 "MSI" : "MSIX"); 513 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 514 515 return rc; 516 } 517 518 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 519 int index, void(*handler)(void *)) 520 { 521 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 522 int relative_idx = index / cdev->num_hwfns; 523 524 hwfn->simd_proto_handler[relative_idx].func = handler; 525 hwfn->simd_proto_handler[relative_idx].token = token; 526 } 527 528 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 529 { 530 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 531 int relative_idx = index / cdev->num_hwfns; 532 533 memset(&hwfn->simd_proto_handler[relative_idx], 0, 534 sizeof(struct qed_simd_fp_handler)); 535 } 536 537 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 538 { 539 tasklet_schedule((struct tasklet_struct *)tasklet); 540 return IRQ_HANDLED; 541 } 542 543 static irqreturn_t qed_single_int(int irq, void *dev_instance) 544 { 545 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 546 struct qed_hwfn *hwfn; 547 irqreturn_t rc = IRQ_NONE; 548 u64 status; 549 int i, j; 550 551 for (i = 0; i < cdev->num_hwfns; i++) { 552 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 553 554 if (!status) 555 continue; 556 557 hwfn = &cdev->hwfns[i]; 558 559 /* Slowpath interrupt */ 560 if (unlikely(status & 0x1)) { 561 tasklet_schedule(hwfn->sp_dpc); 562 status &= ~0x1; 563 rc = IRQ_HANDLED; 564 } 565 566 /* Fastpath interrupts */ 567 for (j = 0; j < 64; j++) { 568 if ((0x2ULL << j) & status) { 569 hwfn->simd_proto_handler[j].func( 570 hwfn->simd_proto_handler[j].token); 571 status &= ~(0x2ULL << j); 572 rc = IRQ_HANDLED; 573 } 574 } 575 576 if (unlikely(status)) 577 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 578 "got an unknown interrupt status 0x%llx\n", 579 status); 580 } 581 582 return rc; 583 } 584 585 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 586 { 587 struct qed_dev *cdev = hwfn->cdev; 588 u32 int_mode; 589 int rc = 0; 590 u8 id; 591 592 int_mode = cdev->int_params.out.int_mode; 593 if (int_mode == QED_INT_MODE_MSIX) { 594 id = hwfn->my_id; 595 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 596 id, cdev->pdev->bus->number, 597 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 598 rc = request_irq(cdev->int_params.msix_table[id].vector, 599 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 600 } else { 601 unsigned long flags = 0; 602 603 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 604 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 605 PCI_FUNC(cdev->pdev->devfn)); 606 607 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 608 flags |= IRQF_SHARED; 609 610 rc = request_irq(cdev->pdev->irq, qed_single_int, 611 flags, cdev->name, cdev); 612 } 613 614 if (rc) 615 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 616 else 617 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 618 "Requested slowpath %s\n", 619 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 620 621 return rc; 622 } 623 624 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn) 625 { 626 /* Calling the disable function will make sure that any 627 * currently-running function is completed. The following call to the 628 * enable function makes this sequence a flush-like operation. 629 */ 630 if (p_hwfn->b_sp_dpc_enabled) { 631 tasklet_disable(p_hwfn->sp_dpc); 632 tasklet_enable(p_hwfn->sp_dpc); 633 } 634 } 635 636 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn) 637 { 638 struct qed_dev *cdev = p_hwfn->cdev; 639 u8 id = p_hwfn->my_id; 640 u32 int_mode; 641 642 int_mode = cdev->int_params.out.int_mode; 643 if (int_mode == QED_INT_MODE_MSIX) 644 synchronize_irq(cdev->int_params.msix_table[id].vector); 645 else 646 synchronize_irq(cdev->pdev->irq); 647 648 qed_slowpath_tasklet_flush(p_hwfn); 649 } 650 651 static void qed_slowpath_irq_free(struct qed_dev *cdev) 652 { 653 int i; 654 655 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 656 for_each_hwfn(cdev, i) { 657 if (!cdev->hwfns[i].b_int_requested) 658 break; 659 synchronize_irq(cdev->int_params.msix_table[i].vector); 660 free_irq(cdev->int_params.msix_table[i].vector, 661 cdev->hwfns[i].sp_dpc); 662 } 663 } else { 664 if (QED_LEADING_HWFN(cdev)->b_int_requested) 665 free_irq(cdev->pdev->irq, cdev); 666 } 667 qed_int_disable_post_isr_release(cdev); 668 } 669 670 static int qed_nic_stop(struct qed_dev *cdev) 671 { 672 int i, rc; 673 674 rc = qed_hw_stop(cdev); 675 676 for (i = 0; i < cdev->num_hwfns; i++) { 677 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 678 679 if (p_hwfn->b_sp_dpc_enabled) { 680 tasklet_disable(p_hwfn->sp_dpc); 681 p_hwfn->b_sp_dpc_enabled = false; 682 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 683 "Disabled sp tasklet [hwfn %d] at %p\n", 684 i, p_hwfn->sp_dpc); 685 } 686 } 687 688 qed_dbg_pf_exit(cdev); 689 690 return rc; 691 } 692 693 static int qed_nic_setup(struct qed_dev *cdev) 694 { 695 int rc, i; 696 697 /* Determine if interface is going to require LL2 */ 698 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 699 for (i = 0; i < cdev->num_hwfns; i++) { 700 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 701 702 p_hwfn->using_ll2 = true; 703 } 704 } 705 706 rc = qed_resc_alloc(cdev); 707 if (rc) 708 return rc; 709 710 DP_INFO(cdev, "Allocated qed resources\n"); 711 712 qed_resc_setup(cdev); 713 714 return rc; 715 } 716 717 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 718 { 719 int limit = 0; 720 721 /* Mark the fastpath as free/used */ 722 cdev->int_params.fp_initialized = cnt ? true : false; 723 724 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 725 limit = cdev->num_hwfns * 63; 726 else if (cdev->int_params.fp_msix_cnt) 727 limit = cdev->int_params.fp_msix_cnt; 728 729 if (!limit) 730 return -ENOMEM; 731 732 return min_t(int, cnt, limit); 733 } 734 735 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 736 { 737 memset(info, 0, sizeof(struct qed_int_info)); 738 739 if (!cdev->int_params.fp_initialized) { 740 DP_INFO(cdev, 741 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 742 return -EINVAL; 743 } 744 745 /* Need to expose only MSI-X information; Single IRQ is handled solely 746 * by qed. 747 */ 748 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 749 int msix_base = cdev->int_params.fp_msix_base; 750 751 info->msix_cnt = cdev->int_params.fp_msix_cnt; 752 info->msix = &cdev->int_params.msix_table[msix_base]; 753 } 754 755 return 0; 756 } 757 758 static int qed_slowpath_setup_int(struct qed_dev *cdev, 759 enum qed_int_mode int_mode) 760 { 761 struct qed_sb_cnt_info sb_cnt_info; 762 int num_l2_queues = 0; 763 int rc; 764 int i; 765 766 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 767 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 768 return -EINVAL; 769 } 770 771 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 772 cdev->int_params.in.int_mode = int_mode; 773 for_each_hwfn(cdev, i) { 774 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 775 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 776 cdev->int_params.in.num_vectors += sb_cnt_info.cnt; 777 cdev->int_params.in.num_vectors++; /* slowpath */ 778 } 779 780 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 781 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 782 783 rc = qed_set_int_mode(cdev, false); 784 if (rc) { 785 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 786 return rc; 787 } 788 789 cdev->int_params.fp_msix_base = cdev->num_hwfns; 790 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 791 cdev->num_hwfns; 792 793 if (!IS_ENABLED(CONFIG_QED_RDMA) || 794 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) 795 return 0; 796 797 for_each_hwfn(cdev, i) 798 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 799 800 DP_VERBOSE(cdev, QED_MSG_RDMA, 801 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 802 cdev->int_params.fp_msix_cnt, num_l2_queues); 803 804 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 805 cdev->int_params.rdma_msix_cnt = 806 (cdev->int_params.fp_msix_cnt - num_l2_queues) 807 / cdev->num_hwfns; 808 cdev->int_params.rdma_msix_base = 809 cdev->int_params.fp_msix_base + num_l2_queues; 810 cdev->int_params.fp_msix_cnt = num_l2_queues; 811 } else { 812 cdev->int_params.rdma_msix_cnt = 0; 813 } 814 815 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 816 cdev->int_params.rdma_msix_cnt, 817 cdev->int_params.rdma_msix_base); 818 819 return 0; 820 } 821 822 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 823 { 824 int rc; 825 826 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 827 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 828 829 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 830 &cdev->int_params.in.num_vectors); 831 if (cdev->num_hwfns > 1) { 832 u8 vectors = 0; 833 834 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 835 cdev->int_params.in.num_vectors += vectors; 836 } 837 838 /* We want a minimum of one fastpath vector per vf hwfn */ 839 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 840 841 rc = qed_set_int_mode(cdev, true); 842 if (rc) 843 return rc; 844 845 cdev->int_params.fp_msix_base = 0; 846 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 847 848 return 0; 849 } 850 851 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 852 u8 *input_buf, u32 max_size, u8 *unzip_buf) 853 { 854 int rc; 855 856 p_hwfn->stream->next_in = input_buf; 857 p_hwfn->stream->avail_in = input_len; 858 p_hwfn->stream->next_out = unzip_buf; 859 p_hwfn->stream->avail_out = max_size; 860 861 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 862 863 if (rc != Z_OK) { 864 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 865 rc); 866 return 0; 867 } 868 869 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 870 zlib_inflateEnd(p_hwfn->stream); 871 872 if (rc != Z_OK && rc != Z_STREAM_END) { 873 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 874 p_hwfn->stream->msg, rc); 875 return 0; 876 } 877 878 return p_hwfn->stream->total_out / 4; 879 } 880 881 static int qed_alloc_stream_mem(struct qed_dev *cdev) 882 { 883 int i; 884 void *workspace; 885 886 for_each_hwfn(cdev, i) { 887 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 888 889 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 890 if (!p_hwfn->stream) 891 return -ENOMEM; 892 893 workspace = vzalloc(zlib_inflate_workspacesize()); 894 if (!workspace) 895 return -ENOMEM; 896 p_hwfn->stream->workspace = workspace; 897 } 898 899 return 0; 900 } 901 902 static void qed_free_stream_mem(struct qed_dev *cdev) 903 { 904 int i; 905 906 for_each_hwfn(cdev, i) { 907 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 908 909 if (!p_hwfn->stream) 910 return; 911 912 vfree(p_hwfn->stream->workspace); 913 kfree(p_hwfn->stream); 914 } 915 } 916 917 static void qed_update_pf_params(struct qed_dev *cdev, 918 struct qed_pf_params *params) 919 { 920 int i; 921 922 if (IS_ENABLED(CONFIG_QED_RDMA)) { 923 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 924 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 925 /* divide by 3 the MRs to avoid MF ILT overflow */ 926 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 927 } 928 929 if (cdev->num_hwfns > 1 || IS_VF(cdev)) 930 params->eth_pf_params.num_arfs_filters = 0; 931 932 /* In case we might support RDMA, don't allow qede to be greedy 933 * with the L2 contexts. Allow for 64 queues [rx, tx, xdp] per hwfn. 934 */ 935 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) { 936 u16 *num_cons; 937 938 num_cons = ¶ms->eth_pf_params.num_cons; 939 *num_cons = min_t(u16, *num_cons, 192); 940 } 941 942 for (i = 0; i < cdev->num_hwfns; i++) { 943 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 944 945 p_hwfn->pf_params = *params; 946 } 947 } 948 949 static void qed_slowpath_wq_stop(struct qed_dev *cdev) 950 { 951 int i; 952 953 if (IS_VF(cdev)) 954 return; 955 956 for_each_hwfn(cdev, i) { 957 if (!cdev->hwfns[i].slowpath_wq) 958 continue; 959 960 flush_workqueue(cdev->hwfns[i].slowpath_wq); 961 destroy_workqueue(cdev->hwfns[i].slowpath_wq); 962 } 963 } 964 965 static void qed_slowpath_task(struct work_struct *work) 966 { 967 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn, 968 slowpath_task.work); 969 struct qed_ptt *ptt = qed_ptt_acquire(hwfn); 970 971 if (!ptt) { 972 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); 973 return; 974 } 975 976 if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ, 977 &hwfn->slowpath_task_flags)) 978 qed_mfw_process_tlv_req(hwfn, ptt); 979 980 qed_ptt_release(hwfn, ptt); 981 } 982 983 static int qed_slowpath_wq_start(struct qed_dev *cdev) 984 { 985 struct qed_hwfn *hwfn; 986 char name[NAME_SIZE]; 987 int i; 988 989 if (IS_VF(cdev)) 990 return 0; 991 992 for_each_hwfn(cdev, i) { 993 hwfn = &cdev->hwfns[i]; 994 995 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x", 996 cdev->pdev->bus->number, 997 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 998 999 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0); 1000 if (!hwfn->slowpath_wq) { 1001 DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n"); 1002 return -ENOMEM; 1003 } 1004 1005 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task); 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int qed_slowpath_start(struct qed_dev *cdev, 1012 struct qed_slowpath_params *params) 1013 { 1014 struct qed_drv_load_params drv_load_params; 1015 struct qed_hw_init_params hw_init_params; 1016 struct qed_mcp_drv_version drv_version; 1017 struct qed_tunnel_info tunn_info; 1018 const u8 *data = NULL; 1019 struct qed_hwfn *hwfn; 1020 struct qed_ptt *p_ptt; 1021 int rc = -EINVAL; 1022 1023 if (qed_iov_wq_start(cdev)) 1024 goto err; 1025 1026 if (qed_slowpath_wq_start(cdev)) 1027 goto err; 1028 1029 if (IS_PF(cdev)) { 1030 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 1031 &cdev->pdev->dev); 1032 if (rc) { 1033 DP_NOTICE(cdev, 1034 "Failed to find fw file - /lib/firmware/%s\n", 1035 QED_FW_FILE_NAME); 1036 goto err; 1037 } 1038 1039 if (cdev->num_hwfns == 1) { 1040 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 1041 if (p_ptt) { 1042 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt; 1043 } else { 1044 DP_NOTICE(cdev, 1045 "Failed to acquire PTT for aRFS\n"); 1046 goto err; 1047 } 1048 } 1049 } 1050 1051 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; 1052 rc = qed_nic_setup(cdev); 1053 if (rc) 1054 goto err; 1055 1056 if (IS_PF(cdev)) 1057 rc = qed_slowpath_setup_int(cdev, params->int_mode); 1058 else 1059 rc = qed_slowpath_vf_setup_int(cdev); 1060 if (rc) 1061 goto err1; 1062 1063 if (IS_PF(cdev)) { 1064 /* Allocate stream for unzipping */ 1065 rc = qed_alloc_stream_mem(cdev); 1066 if (rc) 1067 goto err2; 1068 1069 /* First Dword used to differentiate between various sources */ 1070 data = cdev->firmware->data + sizeof(u32); 1071 1072 qed_dbg_pf_init(cdev); 1073 } 1074 1075 /* Start the slowpath */ 1076 memset(&hw_init_params, 0, sizeof(hw_init_params)); 1077 memset(&tunn_info, 0, sizeof(tunn_info)); 1078 tunn_info.vxlan.b_mode_enabled = true; 1079 tunn_info.l2_gre.b_mode_enabled = true; 1080 tunn_info.ip_gre.b_mode_enabled = true; 1081 tunn_info.l2_geneve.b_mode_enabled = true; 1082 tunn_info.ip_geneve.b_mode_enabled = true; 1083 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1084 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1085 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1086 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1087 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1088 hw_init_params.p_tunn = &tunn_info; 1089 hw_init_params.b_hw_start = true; 1090 hw_init_params.int_mode = cdev->int_params.out.int_mode; 1091 hw_init_params.allow_npar_tx_switch = true; 1092 hw_init_params.bin_fw_data = data; 1093 1094 memset(&drv_load_params, 0, sizeof(drv_load_params)); 1095 drv_load_params.is_crash_kernel = is_kdump_kernel(); 1096 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT; 1097 drv_load_params.avoid_eng_reset = false; 1098 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE; 1099 hw_init_params.p_drv_load_params = &drv_load_params; 1100 1101 rc = qed_hw_init(cdev, &hw_init_params); 1102 if (rc) 1103 goto err2; 1104 1105 DP_INFO(cdev, 1106 "HW initialization and function start completed successfully\n"); 1107 1108 if (IS_PF(cdev)) { 1109 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) | 1110 BIT(QED_MODE_L2GENEVE_TUNN) | 1111 BIT(QED_MODE_IPGENEVE_TUNN) | 1112 BIT(QED_MODE_L2GRE_TUNN) | 1113 BIT(QED_MODE_IPGRE_TUNN)); 1114 } 1115 1116 /* Allocate LL2 interface if needed */ 1117 if (QED_LEADING_HWFN(cdev)->using_ll2) { 1118 rc = qed_ll2_alloc_if(cdev); 1119 if (rc) 1120 goto err3; 1121 } 1122 if (IS_PF(cdev)) { 1123 hwfn = QED_LEADING_HWFN(cdev); 1124 drv_version.version = (params->drv_major << 24) | 1125 (params->drv_minor << 16) | 1126 (params->drv_rev << 8) | 1127 (params->drv_eng); 1128 strlcpy(drv_version.name, params->name, 1129 MCP_DRV_VER_STR_SIZE - 4); 1130 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 1131 &drv_version); 1132 if (rc) { 1133 DP_NOTICE(cdev, "Failed sending drv version command\n"); 1134 return rc; 1135 } 1136 } 1137 1138 qed_reset_vport_stats(cdev); 1139 1140 return 0; 1141 1142 err3: 1143 qed_hw_stop(cdev); 1144 err2: 1145 qed_hw_timers_stop_all(cdev); 1146 if (IS_PF(cdev)) 1147 qed_slowpath_irq_free(cdev); 1148 qed_free_stream_mem(cdev); 1149 qed_disable_msix(cdev); 1150 err1: 1151 qed_resc_free(cdev); 1152 err: 1153 if (IS_PF(cdev)) 1154 release_firmware(cdev->firmware); 1155 1156 if (IS_PF(cdev) && (cdev->num_hwfns == 1) && 1157 QED_LEADING_HWFN(cdev)->p_arfs_ptt) 1158 qed_ptt_release(QED_LEADING_HWFN(cdev), 1159 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1160 1161 qed_iov_wq_stop(cdev, false); 1162 1163 qed_slowpath_wq_stop(cdev); 1164 1165 return rc; 1166 } 1167 1168 static int qed_slowpath_stop(struct qed_dev *cdev) 1169 { 1170 if (!cdev) 1171 return -ENODEV; 1172 1173 qed_slowpath_wq_stop(cdev); 1174 1175 qed_ll2_dealloc_if(cdev); 1176 1177 if (IS_PF(cdev)) { 1178 if (cdev->num_hwfns == 1) 1179 qed_ptt_release(QED_LEADING_HWFN(cdev), 1180 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1181 qed_free_stream_mem(cdev); 1182 if (IS_QED_ETH_IF(cdev)) 1183 qed_sriov_disable(cdev, true); 1184 } 1185 1186 qed_nic_stop(cdev); 1187 1188 if (IS_PF(cdev)) 1189 qed_slowpath_irq_free(cdev); 1190 1191 qed_disable_msix(cdev); 1192 1193 qed_resc_free(cdev); 1194 1195 qed_iov_wq_stop(cdev, true); 1196 1197 if (IS_PF(cdev)) 1198 release_firmware(cdev->firmware); 1199 1200 return 0; 1201 } 1202 1203 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE]) 1204 { 1205 int i; 1206 1207 memcpy(cdev->name, name, NAME_SIZE); 1208 for_each_hwfn(cdev, i) 1209 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1210 } 1211 1212 static u32 qed_sb_init(struct qed_dev *cdev, 1213 struct qed_sb_info *sb_info, 1214 void *sb_virt_addr, 1215 dma_addr_t sb_phy_addr, u16 sb_id, 1216 enum qed_sb_type type) 1217 { 1218 struct qed_hwfn *p_hwfn; 1219 struct qed_ptt *p_ptt; 1220 int hwfn_index; 1221 u16 rel_sb_id; 1222 u8 n_hwfns; 1223 u32 rc; 1224 1225 /* RoCE uses single engine and CMT uses two engines. When using both 1226 * we force only a single engine. Storage uses only engine 0 too. 1227 */ 1228 if (type == QED_SB_TYPE_L2_QUEUE) 1229 n_hwfns = cdev->num_hwfns; 1230 else 1231 n_hwfns = 1; 1232 1233 hwfn_index = sb_id % n_hwfns; 1234 p_hwfn = &cdev->hwfns[hwfn_index]; 1235 rel_sb_id = sb_id / n_hwfns; 1236 1237 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1238 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1239 hwfn_index, rel_sb_id, sb_id); 1240 1241 if (IS_PF(p_hwfn->cdev)) { 1242 p_ptt = qed_ptt_acquire(p_hwfn); 1243 if (!p_ptt) 1244 return -EBUSY; 1245 1246 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr, 1247 sb_phy_addr, rel_sb_id); 1248 qed_ptt_release(p_hwfn, p_ptt); 1249 } else { 1250 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr, 1251 sb_phy_addr, rel_sb_id); 1252 } 1253 1254 return rc; 1255 } 1256 1257 static u32 qed_sb_release(struct qed_dev *cdev, 1258 struct qed_sb_info *sb_info, u16 sb_id) 1259 { 1260 struct qed_hwfn *p_hwfn; 1261 int hwfn_index; 1262 u16 rel_sb_id; 1263 u32 rc; 1264 1265 hwfn_index = sb_id % cdev->num_hwfns; 1266 p_hwfn = &cdev->hwfns[hwfn_index]; 1267 rel_sb_id = sb_id / cdev->num_hwfns; 1268 1269 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1270 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1271 hwfn_index, rel_sb_id, sb_id); 1272 1273 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1274 1275 return rc; 1276 } 1277 1278 static bool qed_can_link_change(struct qed_dev *cdev) 1279 { 1280 return true; 1281 } 1282 1283 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1284 { 1285 struct qed_hwfn *hwfn; 1286 struct qed_mcp_link_params *link_params; 1287 struct qed_ptt *ptt; 1288 int rc; 1289 1290 if (!cdev) 1291 return -ENODEV; 1292 1293 /* The link should be set only once per PF */ 1294 hwfn = &cdev->hwfns[0]; 1295 1296 /* When VF wants to set link, force it to read the bulletin instead. 1297 * This mimics the PF behavior, where a noitification [both immediate 1298 * and possible later] would be generated when changing properties. 1299 */ 1300 if (IS_VF(cdev)) { 1301 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG); 1302 return 0; 1303 } 1304 1305 ptt = qed_ptt_acquire(hwfn); 1306 if (!ptt) 1307 return -EBUSY; 1308 1309 link_params = qed_mcp_get_link_params(hwfn); 1310 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1311 link_params->speed.autoneg = params->autoneg; 1312 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1313 link_params->speed.advertised_speeds = 0; 1314 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1315 (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1316 link_params->speed.advertised_speeds |= 1317 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1318 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1319 link_params->speed.advertised_speeds |= 1320 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1321 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1322 link_params->speed.advertised_speeds |= 1323 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1324 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1325 link_params->speed.advertised_speeds |= 1326 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1327 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1328 link_params->speed.advertised_speeds |= 1329 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1330 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1331 link_params->speed.advertised_speeds |= 1332 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1333 } 1334 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1335 link_params->speed.forced_speed = params->forced_speed; 1336 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1337 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1338 link_params->pause.autoneg = true; 1339 else 1340 link_params->pause.autoneg = false; 1341 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1342 link_params->pause.forced_rx = true; 1343 else 1344 link_params->pause.forced_rx = false; 1345 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1346 link_params->pause.forced_tx = true; 1347 else 1348 link_params->pause.forced_tx = false; 1349 } 1350 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1351 switch (params->loopback_mode) { 1352 case QED_LINK_LOOPBACK_INT_PHY: 1353 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1354 break; 1355 case QED_LINK_LOOPBACK_EXT_PHY: 1356 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1357 break; 1358 case QED_LINK_LOOPBACK_EXT: 1359 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1360 break; 1361 case QED_LINK_LOOPBACK_MAC: 1362 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1363 break; 1364 default: 1365 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1366 break; 1367 } 1368 } 1369 1370 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG) 1371 memcpy(&link_params->eee, ¶ms->eee, 1372 sizeof(link_params->eee)); 1373 1374 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1375 1376 qed_ptt_release(hwfn, ptt); 1377 1378 return rc; 1379 } 1380 1381 static int qed_get_port_type(u32 media_type) 1382 { 1383 int port_type; 1384 1385 switch (media_type) { 1386 case MEDIA_SFPP_10G_FIBER: 1387 case MEDIA_SFP_1G_FIBER: 1388 case MEDIA_XFP_FIBER: 1389 case MEDIA_MODULE_FIBER: 1390 case MEDIA_KR: 1391 port_type = PORT_FIBRE; 1392 break; 1393 case MEDIA_DA_TWINAX: 1394 port_type = PORT_DA; 1395 break; 1396 case MEDIA_BASE_T: 1397 port_type = PORT_TP; 1398 break; 1399 case MEDIA_NOT_PRESENT: 1400 port_type = PORT_NONE; 1401 break; 1402 case MEDIA_UNSPECIFIED: 1403 default: 1404 port_type = PORT_OTHER; 1405 break; 1406 } 1407 return port_type; 1408 } 1409 1410 static int qed_get_link_data(struct qed_hwfn *hwfn, 1411 struct qed_mcp_link_params *params, 1412 struct qed_mcp_link_state *link, 1413 struct qed_mcp_link_capabilities *link_caps) 1414 { 1415 void *p; 1416 1417 if (!IS_PF(hwfn->cdev)) { 1418 qed_vf_get_link_params(hwfn, params); 1419 qed_vf_get_link_state(hwfn, link); 1420 qed_vf_get_link_caps(hwfn, link_caps); 1421 1422 return 0; 1423 } 1424 1425 p = qed_mcp_get_link_params(hwfn); 1426 if (!p) 1427 return -ENXIO; 1428 memcpy(params, p, sizeof(*params)); 1429 1430 p = qed_mcp_get_link_state(hwfn); 1431 if (!p) 1432 return -ENXIO; 1433 memcpy(link, p, sizeof(*link)); 1434 1435 p = qed_mcp_get_link_capabilities(hwfn); 1436 if (!p) 1437 return -ENXIO; 1438 memcpy(link_caps, p, sizeof(*link_caps)); 1439 1440 return 0; 1441 } 1442 1443 static void qed_fill_link(struct qed_hwfn *hwfn, 1444 struct qed_link_output *if_link) 1445 { 1446 struct qed_mcp_link_params params; 1447 struct qed_mcp_link_state link; 1448 struct qed_mcp_link_capabilities link_caps; 1449 u32 media_type; 1450 1451 memset(if_link, 0, sizeof(*if_link)); 1452 1453 /* Prepare source inputs */ 1454 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1455 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1456 return; 1457 } 1458 1459 /* Set the link parameters to pass to protocol driver */ 1460 if (link.link_up) 1461 if_link->link_up = true; 1462 1463 /* TODO - at the moment assume supported and advertised speed equal */ 1464 if_link->supported_caps = QED_LM_FIBRE_BIT; 1465 if (link_caps.default_speed_autoneg) 1466 if_link->supported_caps |= QED_LM_Autoneg_BIT; 1467 if (params.pause.autoneg || 1468 (params.pause.forced_rx && params.pause.forced_tx)) 1469 if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1470 if (params.pause.autoneg || params.pause.forced_rx || 1471 params.pause.forced_tx) 1472 if_link->supported_caps |= QED_LM_Pause_BIT; 1473 1474 if_link->advertised_caps = if_link->supported_caps; 1475 if (params.speed.autoneg) 1476 if_link->advertised_caps |= QED_LM_Autoneg_BIT; 1477 else 1478 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT; 1479 if (params.speed.advertised_speeds & 1480 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1481 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1482 QED_LM_1000baseT_Full_BIT; 1483 if (params.speed.advertised_speeds & 1484 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1485 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1486 if (params.speed.advertised_speeds & 1487 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1488 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1489 if (params.speed.advertised_speeds & 1490 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1491 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1492 if (params.speed.advertised_speeds & 1493 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1494 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1495 if (params.speed.advertised_speeds & 1496 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1497 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1498 1499 if (link_caps.speed_capabilities & 1500 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1501 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1502 QED_LM_1000baseT_Full_BIT; 1503 if (link_caps.speed_capabilities & 1504 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1505 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1506 if (link_caps.speed_capabilities & 1507 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1508 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1509 if (link_caps.speed_capabilities & 1510 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1511 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1512 if (link_caps.speed_capabilities & 1513 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1514 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1515 if (link_caps.speed_capabilities & 1516 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1517 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1518 1519 if (link.link_up) 1520 if_link->speed = link.speed; 1521 1522 /* TODO - fill duplex properly */ 1523 if_link->duplex = DUPLEX_FULL; 1524 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1525 if_link->port = qed_get_port_type(media_type); 1526 1527 if_link->autoneg = params.speed.autoneg; 1528 1529 if (params.pause.autoneg) 1530 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1531 if (params.pause.forced_rx) 1532 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1533 if (params.pause.forced_tx) 1534 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1535 1536 /* Link partner capabilities */ 1537 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1538 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1539 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1540 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1541 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1542 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1543 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1544 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1545 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1546 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1547 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1548 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1549 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1550 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1551 1552 if (link.an_complete) 1553 if_link->lp_caps |= QED_LM_Autoneg_BIT; 1554 1555 if (link.partner_adv_pause) 1556 if_link->lp_caps |= QED_LM_Pause_BIT; 1557 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1558 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1559 if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1560 1561 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) { 1562 if_link->eee_supported = false; 1563 } else { 1564 if_link->eee_supported = true; 1565 if_link->eee_active = link.eee_active; 1566 if_link->sup_caps = link_caps.eee_speed_caps; 1567 /* MFW clears adv_caps on eee disable; use configured value */ 1568 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps : 1569 params.eee.adv_caps; 1570 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps; 1571 if_link->eee.enable = params.eee.enable; 1572 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable; 1573 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer; 1574 } 1575 } 1576 1577 static void qed_get_current_link(struct qed_dev *cdev, 1578 struct qed_link_output *if_link) 1579 { 1580 int i; 1581 1582 qed_fill_link(&cdev->hwfns[0], if_link); 1583 1584 for_each_hwfn(cdev, i) 1585 qed_inform_vf_link_state(&cdev->hwfns[i]); 1586 } 1587 1588 void qed_link_update(struct qed_hwfn *hwfn) 1589 { 1590 void *cookie = hwfn->cdev->ops_cookie; 1591 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1592 struct qed_link_output if_link; 1593 1594 qed_fill_link(hwfn, &if_link); 1595 qed_inform_vf_link_state(hwfn); 1596 1597 if (IS_LEAD_HWFN(hwfn) && cookie) 1598 op->link_update(cookie, &if_link); 1599 } 1600 1601 static int qed_drain(struct qed_dev *cdev) 1602 { 1603 struct qed_hwfn *hwfn; 1604 struct qed_ptt *ptt; 1605 int i, rc; 1606 1607 if (IS_VF(cdev)) 1608 return 0; 1609 1610 for_each_hwfn(cdev, i) { 1611 hwfn = &cdev->hwfns[i]; 1612 ptt = qed_ptt_acquire(hwfn); 1613 if (!ptt) { 1614 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1615 return -EBUSY; 1616 } 1617 rc = qed_mcp_drain(hwfn, ptt); 1618 if (rc) 1619 return rc; 1620 qed_ptt_release(hwfn, ptt); 1621 } 1622 1623 return 0; 1624 } 1625 1626 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev, 1627 struct qed_nvm_image_att *nvm_image, 1628 u32 *crc) 1629 { 1630 u8 *buf = NULL; 1631 int rc, j; 1632 u32 val; 1633 1634 /* Allocate a buffer for holding the nvram image */ 1635 buf = kzalloc(nvm_image->length, GFP_KERNEL); 1636 if (!buf) 1637 return -ENOMEM; 1638 1639 /* Read image into buffer */ 1640 rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr, 1641 buf, nvm_image->length); 1642 if (rc) { 1643 DP_ERR(cdev, "Failed reading image from nvm\n"); 1644 goto out; 1645 } 1646 1647 /* Convert the buffer into big-endian format (excluding the 1648 * closing 4 bytes of CRC). 1649 */ 1650 for (j = 0; j < nvm_image->length - 4; j += 4) { 1651 val = cpu_to_be32(*(u32 *)&buf[j]); 1652 *(u32 *)&buf[j] = val; 1653 } 1654 1655 /* Calc CRC for the "actual" image buffer, i.e. not including 1656 * the last 4 CRC bytes. 1657 */ 1658 *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4))); 1659 1660 out: 1661 kfree(buf); 1662 1663 return rc; 1664 } 1665 1666 /* Binary file format - 1667 * /----------------------------------------------------------------------\ 1668 * 0B | 0x4 [command index] | 1669 * 4B | image_type | Options | Number of register settings | 1670 * 8B | Value | 1671 * 12B | Mask | 1672 * 16B | Offset | 1673 * \----------------------------------------------------------------------/ 1674 * There can be several Value-Mask-Offset sets as specified by 'Number of...'. 1675 * Options - 0'b - Calculate & Update CRC for image 1676 */ 1677 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data, 1678 bool *check_resp) 1679 { 1680 struct qed_nvm_image_att nvm_image; 1681 struct qed_hwfn *p_hwfn; 1682 bool is_crc = false; 1683 u32 image_type; 1684 int rc = 0, i; 1685 u16 len; 1686 1687 *data += 4; 1688 image_type = **data; 1689 p_hwfn = QED_LEADING_HWFN(cdev); 1690 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 1691 if (image_type == p_hwfn->nvm_info.image_att[i].image_type) 1692 break; 1693 if (i == p_hwfn->nvm_info.num_images) { 1694 DP_ERR(cdev, "Failed to find nvram image of type %08x\n", 1695 image_type); 1696 return -ENOENT; 1697 } 1698 1699 nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 1700 nvm_image.length = p_hwfn->nvm_info.image_att[i].len; 1701 1702 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1703 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n", 1704 **data, image_type, nvm_image.start_addr, 1705 nvm_image.start_addr + nvm_image.length - 1); 1706 (*data)++; 1707 is_crc = !!(**data & BIT(0)); 1708 (*data)++; 1709 len = *((u16 *)*data); 1710 *data += 2; 1711 if (is_crc) { 1712 u32 crc = 0; 1713 1714 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc); 1715 if (rc) { 1716 DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc); 1717 goto exit; 1718 } 1719 1720 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1721 (nvm_image.start_addr + 1722 nvm_image.length - 4), (u8 *)&crc, 4); 1723 if (rc) 1724 DP_ERR(cdev, "Failed writing to %08x, rc = %d\n", 1725 nvm_image.start_addr + nvm_image.length - 4, rc); 1726 goto exit; 1727 } 1728 1729 /* Iterate over the values for setting */ 1730 while (len) { 1731 u32 offset, mask, value, cur_value; 1732 u8 buf[4]; 1733 1734 value = *((u32 *)*data); 1735 *data += 4; 1736 mask = *((u32 *)*data); 1737 *data += 4; 1738 offset = *((u32 *)*data); 1739 *data += 4; 1740 1741 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf, 1742 4); 1743 if (rc) { 1744 DP_ERR(cdev, "Failed reading from %08x\n", 1745 nvm_image.start_addr + offset); 1746 goto exit; 1747 } 1748 1749 cur_value = le32_to_cpu(*((__le32 *)buf)); 1750 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1751 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n", 1752 nvm_image.start_addr + offset, cur_value, 1753 (cur_value & ~mask) | (value & mask), value, mask); 1754 value = (value & mask) | (cur_value & ~mask); 1755 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1756 nvm_image.start_addr + offset, 1757 (u8 *)&value, 4); 1758 if (rc) { 1759 DP_ERR(cdev, "Failed writing to %08x\n", 1760 nvm_image.start_addr + offset); 1761 goto exit; 1762 } 1763 1764 len--; 1765 } 1766 exit: 1767 return rc; 1768 } 1769 1770 /* Binary file format - 1771 * /----------------------------------------------------------------------\ 1772 * 0B | 0x3 [command index] | 1773 * 4B | b'0: check_response? | b'1-31 reserved | 1774 * 8B | File-type | reserved | 1775 * \----------------------------------------------------------------------/ 1776 * Start a new file of the provided type 1777 */ 1778 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev, 1779 const u8 **data, bool *check_resp) 1780 { 1781 int rc; 1782 1783 *data += 4; 1784 *check_resp = !!(**data & BIT(0)); 1785 *data += 4; 1786 1787 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1788 "About to start a new file of type %02x\n", **data); 1789 rc = qed_mcp_nvm_put_file_begin(cdev, **data); 1790 *data += 4; 1791 1792 return rc; 1793 } 1794 1795 /* Binary file format - 1796 * /----------------------------------------------------------------------\ 1797 * 0B | 0x2 [command index] | 1798 * 4B | Length in bytes | 1799 * 8B | b'0: check_response? | b'1-31 reserved | 1800 * 12B | Offset in bytes | 1801 * 16B | Data ... | 1802 * \----------------------------------------------------------------------/ 1803 * Write data as part of a file that was previously started. Data should be 1804 * of length equal to that provided in the message 1805 */ 1806 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev, 1807 const u8 **data, bool *check_resp) 1808 { 1809 u32 offset, len; 1810 int rc; 1811 1812 *data += 4; 1813 len = *((u32 *)(*data)); 1814 *data += 4; 1815 *check_resp = !!(**data & BIT(0)); 1816 *data += 4; 1817 offset = *((u32 *)(*data)); 1818 *data += 4; 1819 1820 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1821 "About to write File-data: %08x bytes to offset %08x\n", 1822 len, offset); 1823 1824 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset, 1825 (char *)(*data), len); 1826 *data += len; 1827 1828 return rc; 1829 } 1830 1831 /* Binary file format [General header] - 1832 * /----------------------------------------------------------------------\ 1833 * 0B | QED_NVM_SIGNATURE | 1834 * 4B | Length in bytes | 1835 * 8B | Highest command in this batchfile | Reserved | 1836 * \----------------------------------------------------------------------/ 1837 */ 1838 static int qed_nvm_flash_image_validate(struct qed_dev *cdev, 1839 const struct firmware *image, 1840 const u8 **data) 1841 { 1842 u32 signature, len; 1843 1844 /* Check minimum size */ 1845 if (image->size < 12) { 1846 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size); 1847 return -EINVAL; 1848 } 1849 1850 /* Check signature */ 1851 signature = *((u32 *)(*data)); 1852 if (signature != QED_NVM_SIGNATURE) { 1853 DP_ERR(cdev, "Wrong signature '%08x'\n", signature); 1854 return -EINVAL; 1855 } 1856 1857 *data += 4; 1858 /* Validate internal size equals the image-size */ 1859 len = *((u32 *)(*data)); 1860 if (len != image->size) { 1861 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n", 1862 len, (u32)image->size); 1863 return -EINVAL; 1864 } 1865 1866 *data += 4; 1867 /* Make sure driver familiar with all commands necessary for this */ 1868 if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) { 1869 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n", 1870 *((u16 *)(*data))); 1871 return -EINVAL; 1872 } 1873 1874 *data += 4; 1875 1876 return 0; 1877 } 1878 1879 static int qed_nvm_flash(struct qed_dev *cdev, const char *name) 1880 { 1881 const struct firmware *image; 1882 const u8 *data, *data_end; 1883 u32 cmd_type; 1884 int rc; 1885 1886 rc = request_firmware(&image, name, &cdev->pdev->dev); 1887 if (rc) { 1888 DP_ERR(cdev, "Failed to find '%s'\n", name); 1889 return rc; 1890 } 1891 1892 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1893 "Flashing '%s' - firmware's data at %p, size is %08x\n", 1894 name, image->data, (u32)image->size); 1895 data = image->data; 1896 data_end = data + image->size; 1897 1898 rc = qed_nvm_flash_image_validate(cdev, image, &data); 1899 if (rc) 1900 goto exit; 1901 1902 while (data < data_end) { 1903 bool check_resp = false; 1904 1905 /* Parse the actual command */ 1906 cmd_type = *((u32 *)data); 1907 switch (cmd_type) { 1908 case QED_NVM_FLASH_CMD_FILE_DATA: 1909 rc = qed_nvm_flash_image_file_data(cdev, &data, 1910 &check_resp); 1911 break; 1912 case QED_NVM_FLASH_CMD_FILE_START: 1913 rc = qed_nvm_flash_image_file_start(cdev, &data, 1914 &check_resp); 1915 break; 1916 case QED_NVM_FLASH_CMD_NVM_CHANGE: 1917 rc = qed_nvm_flash_image_access(cdev, &data, 1918 &check_resp); 1919 break; 1920 default: 1921 DP_ERR(cdev, "Unknown command %08x\n", cmd_type); 1922 rc = -EINVAL; 1923 goto exit; 1924 } 1925 1926 if (rc) { 1927 DP_ERR(cdev, "Command %08x failed\n", cmd_type); 1928 goto exit; 1929 } 1930 1931 /* Check response if needed */ 1932 if (check_resp) { 1933 u32 mcp_response = 0; 1934 1935 if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) { 1936 DP_ERR(cdev, "Failed getting MCP response\n"); 1937 rc = -EINVAL; 1938 goto exit; 1939 } 1940 1941 switch (mcp_response & FW_MSG_CODE_MASK) { 1942 case FW_MSG_CODE_OK: 1943 case FW_MSG_CODE_NVM_OK: 1944 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK: 1945 case FW_MSG_CODE_PHY_OK: 1946 break; 1947 default: 1948 DP_ERR(cdev, "MFW returns error: %08x\n", 1949 mcp_response); 1950 rc = -EINVAL; 1951 goto exit; 1952 } 1953 } 1954 } 1955 1956 exit: 1957 release_firmware(image); 1958 1959 return rc; 1960 } 1961 1962 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, 1963 u8 *buf, u16 len) 1964 { 1965 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1966 1967 return qed_mcp_get_nvm_image(hwfn, type, buf, len); 1968 } 1969 1970 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1971 void *handle) 1972 { 1973 return qed_set_queue_coalesce(rx_coal, tx_coal, handle); 1974 } 1975 1976 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1977 { 1978 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1979 struct qed_ptt *ptt; 1980 int status = 0; 1981 1982 ptt = qed_ptt_acquire(hwfn); 1983 if (!ptt) 1984 return -EAGAIN; 1985 1986 status = qed_mcp_set_led(hwfn, ptt, mode); 1987 1988 qed_ptt_release(hwfn, ptt); 1989 1990 return status; 1991 } 1992 1993 static int qed_update_wol(struct qed_dev *cdev, bool enabled) 1994 { 1995 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1996 struct qed_ptt *ptt; 1997 int rc = 0; 1998 1999 if (IS_VF(cdev)) 2000 return 0; 2001 2002 ptt = qed_ptt_acquire(hwfn); 2003 if (!ptt) 2004 return -EAGAIN; 2005 2006 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED 2007 : QED_OV_WOL_DISABLED); 2008 if (rc) 2009 goto out; 2010 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2011 2012 out: 2013 qed_ptt_release(hwfn, ptt); 2014 return rc; 2015 } 2016 2017 static int qed_update_drv_state(struct qed_dev *cdev, bool active) 2018 { 2019 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2020 struct qed_ptt *ptt; 2021 int status = 0; 2022 2023 if (IS_VF(cdev)) 2024 return 0; 2025 2026 ptt = qed_ptt_acquire(hwfn); 2027 if (!ptt) 2028 return -EAGAIN; 2029 2030 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ? 2031 QED_OV_DRIVER_STATE_ACTIVE : 2032 QED_OV_DRIVER_STATE_DISABLED); 2033 2034 qed_ptt_release(hwfn, ptt); 2035 2036 return status; 2037 } 2038 2039 static int qed_update_mac(struct qed_dev *cdev, u8 *mac) 2040 { 2041 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2042 struct qed_ptt *ptt; 2043 int status = 0; 2044 2045 if (IS_VF(cdev)) 2046 return 0; 2047 2048 ptt = qed_ptt_acquire(hwfn); 2049 if (!ptt) 2050 return -EAGAIN; 2051 2052 status = qed_mcp_ov_update_mac(hwfn, ptt, mac); 2053 if (status) 2054 goto out; 2055 2056 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2057 2058 out: 2059 qed_ptt_release(hwfn, ptt); 2060 return status; 2061 } 2062 2063 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) 2064 { 2065 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2066 struct qed_ptt *ptt; 2067 int status = 0; 2068 2069 if (IS_VF(cdev)) 2070 return 0; 2071 2072 ptt = qed_ptt_acquire(hwfn); 2073 if (!ptt) 2074 return -EAGAIN; 2075 2076 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu); 2077 if (status) 2078 goto out; 2079 2080 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2081 2082 out: 2083 qed_ptt_release(hwfn, ptt); 2084 return status; 2085 } 2086 2087 static struct qed_selftest_ops qed_selftest_ops_pass = { 2088 .selftest_memory = &qed_selftest_memory, 2089 .selftest_interrupt = &qed_selftest_interrupt, 2090 .selftest_register = &qed_selftest_register, 2091 .selftest_clock = &qed_selftest_clock, 2092 .selftest_nvram = &qed_selftest_nvram, 2093 }; 2094 2095 const struct qed_common_ops qed_common_ops_pass = { 2096 .selftest = &qed_selftest_ops_pass, 2097 .probe = &qed_probe, 2098 .remove = &qed_remove, 2099 .set_power_state = &qed_set_power_state, 2100 .set_name = &qed_set_name, 2101 .update_pf_params = &qed_update_pf_params, 2102 .slowpath_start = &qed_slowpath_start, 2103 .slowpath_stop = &qed_slowpath_stop, 2104 .set_fp_int = &qed_set_int_fp, 2105 .get_fp_int = &qed_get_int_fp, 2106 .sb_init = &qed_sb_init, 2107 .sb_release = &qed_sb_release, 2108 .simd_handler_config = &qed_simd_handler_config, 2109 .simd_handler_clean = &qed_simd_handler_clean, 2110 .dbg_grc = &qed_dbg_grc, 2111 .dbg_grc_size = &qed_dbg_grc_size, 2112 .can_link_change = &qed_can_link_change, 2113 .set_link = &qed_set_link, 2114 .get_link = &qed_get_current_link, 2115 .drain = &qed_drain, 2116 .update_msglvl = &qed_init_dp, 2117 .dbg_all_data = &qed_dbg_all_data, 2118 .dbg_all_data_size = &qed_dbg_all_data_size, 2119 .chain_alloc = &qed_chain_alloc, 2120 .chain_free = &qed_chain_free, 2121 .nvm_flash = &qed_nvm_flash, 2122 .nvm_get_image = &qed_nvm_get_image, 2123 .set_coalesce = &qed_set_coalesce, 2124 .set_led = &qed_set_led, 2125 .update_drv_state = &qed_update_drv_state, 2126 .update_mac = &qed_update_mac, 2127 .update_mtu = &qed_update_mtu, 2128 .update_wol = &qed_update_wol, 2129 }; 2130 2131 void qed_get_protocol_stats(struct qed_dev *cdev, 2132 enum qed_mcp_protocol_type type, 2133 union qed_mcp_protocol_stats *stats) 2134 { 2135 struct qed_eth_stats eth_stats; 2136 2137 memset(stats, 0, sizeof(*stats)); 2138 2139 switch (type) { 2140 case QED_MCP_LAN_STATS: 2141 qed_get_vport_stats(cdev, ð_stats); 2142 stats->lan_stats.ucast_rx_pkts = 2143 eth_stats.common.rx_ucast_pkts; 2144 stats->lan_stats.ucast_tx_pkts = 2145 eth_stats.common.tx_ucast_pkts; 2146 stats->lan_stats.fcs_err = -1; 2147 break; 2148 case QED_MCP_FCOE_STATS: 2149 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats); 2150 break; 2151 case QED_MCP_ISCSI_STATS: 2152 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats); 2153 break; 2154 default: 2155 DP_VERBOSE(cdev, QED_MSG_SP, 2156 "Invalid protocol type = %d\n", type); 2157 return; 2158 } 2159 } 2160 2161 int qed_mfw_tlv_req(struct qed_hwfn *hwfn) 2162 { 2163 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV, 2164 "Scheduling slowpath task [Flag: %d]\n", 2165 QED_SLOWPATH_MFW_TLV_REQ); 2166 smp_mb__before_atomic(); 2167 set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags); 2168 smp_mb__after_atomic(); 2169 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); 2170 2171 return 0; 2172 } 2173 2174 static void 2175 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv) 2176 { 2177 struct qed_common_cb_ops *op = cdev->protocol_ops.common; 2178 struct qed_eth_stats_common *p_common; 2179 struct qed_generic_tlvs gen_tlvs; 2180 struct qed_eth_stats stats; 2181 int i; 2182 2183 memset(&gen_tlvs, 0, sizeof(gen_tlvs)); 2184 op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs); 2185 2186 if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM) 2187 tlv->flags.ipv4_csum_offload = true; 2188 if (gen_tlvs.feat_flags & QED_TLV_LSO) 2189 tlv->flags.lso_supported = true; 2190 tlv->flags.b_set = true; 2191 2192 for (i = 0; i < QED_TLV_MAC_COUNT; i++) { 2193 if (is_valid_ether_addr(gen_tlvs.mac[i])) { 2194 ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]); 2195 tlv->mac_set[i] = true; 2196 } 2197 } 2198 2199 qed_get_vport_stats(cdev, &stats); 2200 p_common = &stats.common; 2201 tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts + 2202 p_common->rx_bcast_pkts; 2203 tlv->rx_frames_set = true; 2204 tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes + 2205 p_common->rx_bcast_bytes; 2206 tlv->rx_bytes_set = true; 2207 tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts + 2208 p_common->tx_bcast_pkts; 2209 tlv->tx_frames_set = true; 2210 tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes + 2211 p_common->tx_bcast_bytes; 2212 tlv->rx_bytes_set = true; 2213 } 2214 2215 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type, 2216 union qed_mfw_tlv_data *tlv_buf) 2217 { 2218 struct qed_dev *cdev = hwfn->cdev; 2219 struct qed_common_cb_ops *ops; 2220 2221 ops = cdev->protocol_ops.common; 2222 if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) { 2223 DP_NOTICE(hwfn, "Can't collect TLV management info\n"); 2224 return -EINVAL; 2225 } 2226 2227 switch (type) { 2228 case QED_MFW_TLV_GENERIC: 2229 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic); 2230 break; 2231 case QED_MFW_TLV_ETH: 2232 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth); 2233 break; 2234 case QED_MFW_TLV_FCOE: 2235 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe); 2236 break; 2237 case QED_MFW_TLV_ISCSI: 2238 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi); 2239 break; 2240 default: 2241 break; 2242 } 2243 2244 return 0; 2245 } 2246