1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/stddef.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/version.h> 14 #include <linux/delay.h> 15 #include <asm/byteorder.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/string.h> 18 #include <linux/module.h> 19 #include <linux/interrupt.h> 20 #include <linux/workqueue.h> 21 #include <linux/ethtool.h> 22 #include <linux/etherdevice.h> 23 #include <linux/vmalloc.h> 24 #include <linux/qed/qed_if.h> 25 26 #include "qed.h" 27 #include "qed_sp.h" 28 #include "qed_dev_api.h" 29 #include "qed_mcp.h" 30 #include "qed_hw.h" 31 32 static const char version[] = 33 "QLogic QL4xxx 40G/100G Ethernet Driver qed " DRV_MODULE_VERSION "\n"; 34 35 MODULE_DESCRIPTION("QLogic 25G/40G/50G/100G Core Module"); 36 MODULE_LICENSE("GPL"); 37 MODULE_VERSION(DRV_MODULE_VERSION); 38 39 #define FW_FILE_VERSION \ 40 __stringify(FW_MAJOR_VERSION) "." \ 41 __stringify(FW_MINOR_VERSION) "." \ 42 __stringify(FW_REVISION_VERSION) "." \ 43 __stringify(FW_ENGINEERING_VERSION) 44 45 #define QED_FW_FILE_NAME \ 46 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 47 48 static int __init qed_init(void) 49 { 50 pr_notice("qed_init called\n"); 51 52 pr_info("%s", version); 53 54 return 0; 55 } 56 57 static void __exit qed_cleanup(void) 58 { 59 pr_notice("qed_cleanup called\n"); 60 } 61 62 module_init(qed_init); 63 module_exit(qed_cleanup); 64 65 /* Check if the DMA controller on the machine can properly handle the DMA 66 * addressing required by the device. 67 */ 68 static int qed_set_coherency_mask(struct qed_dev *cdev) 69 { 70 struct device *dev = &cdev->pdev->dev; 71 72 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 73 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 74 DP_NOTICE(cdev, 75 "Can't request 64-bit consistent allocations\n"); 76 return -EIO; 77 } 78 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 79 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 80 return -EIO; 81 } 82 83 return 0; 84 } 85 86 static void qed_free_pci(struct qed_dev *cdev) 87 { 88 struct pci_dev *pdev = cdev->pdev; 89 90 if (cdev->doorbells) 91 iounmap(cdev->doorbells); 92 if (cdev->regview) 93 iounmap(cdev->regview); 94 if (atomic_read(&pdev->enable_cnt) == 1) 95 pci_release_regions(pdev); 96 97 pci_disable_device(pdev); 98 } 99 100 /* Performs PCI initializations as well as initializing PCI-related parameters 101 * in the device structrue. Returns 0 in case of success. 102 */ 103 static int qed_init_pci(struct qed_dev *cdev, 104 struct pci_dev *pdev) 105 { 106 int rc; 107 108 cdev->pdev = pdev; 109 110 rc = pci_enable_device(pdev); 111 if (rc) { 112 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 113 goto err0; 114 } 115 116 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 117 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 118 rc = -EIO; 119 goto err1; 120 } 121 122 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 123 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 124 rc = -EIO; 125 goto err1; 126 } 127 128 if (atomic_read(&pdev->enable_cnt) == 1) { 129 rc = pci_request_regions(pdev, "qed"); 130 if (rc) { 131 DP_NOTICE(cdev, 132 "Failed to request PCI memory resources\n"); 133 goto err1; 134 } 135 pci_set_master(pdev); 136 pci_save_state(pdev); 137 } 138 139 if (!pci_is_pcie(pdev)) { 140 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 141 rc = -EIO; 142 goto err2; 143 } 144 145 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 146 if (cdev->pci_params.pm_cap == 0) 147 DP_NOTICE(cdev, "Cannot find power management capability\n"); 148 149 rc = qed_set_coherency_mask(cdev); 150 if (rc) 151 goto err2; 152 153 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 154 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 155 cdev->pci_params.irq = pdev->irq; 156 157 cdev->regview = pci_ioremap_bar(pdev, 0); 158 if (!cdev->regview) { 159 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 160 rc = -ENOMEM; 161 goto err2; 162 } 163 164 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 165 cdev->db_size = pci_resource_len(cdev->pdev, 2); 166 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 167 if (!cdev->doorbells) { 168 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 169 return -ENOMEM; 170 } 171 172 return 0; 173 174 err2: 175 pci_release_regions(pdev); 176 err1: 177 pci_disable_device(pdev); 178 err0: 179 return rc; 180 } 181 182 int qed_fill_dev_info(struct qed_dev *cdev, 183 struct qed_dev_info *dev_info) 184 { 185 struct qed_ptt *ptt; 186 187 memset(dev_info, 0, sizeof(struct qed_dev_info)); 188 189 dev_info->num_hwfns = cdev->num_hwfns; 190 dev_info->pci_mem_start = cdev->pci_params.mem_start; 191 dev_info->pci_mem_end = cdev->pci_params.mem_end; 192 dev_info->pci_irq = cdev->pci_params.irq; 193 dev_info->is_mf = IS_MF(&cdev->hwfns[0]); 194 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr); 195 196 dev_info->fw_major = FW_MAJOR_VERSION; 197 dev_info->fw_minor = FW_MINOR_VERSION; 198 dev_info->fw_rev = FW_REVISION_VERSION; 199 dev_info->fw_eng = FW_ENGINEERING_VERSION; 200 dev_info->mf_mode = cdev->mf_mode; 201 202 qed_mcp_get_mfw_ver(cdev, &dev_info->mfw_rev); 203 204 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 205 if (ptt) { 206 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 207 &dev_info->flash_size); 208 209 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 210 } 211 212 return 0; 213 } 214 215 static void qed_free_cdev(struct qed_dev *cdev) 216 { 217 kfree((void *)cdev); 218 } 219 220 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 221 { 222 struct qed_dev *cdev; 223 224 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 225 if (!cdev) 226 return cdev; 227 228 qed_init_struct(cdev); 229 230 return cdev; 231 } 232 233 /* Sets the requested power state */ 234 static int qed_set_power_state(struct qed_dev *cdev, 235 pci_power_t state) 236 { 237 if (!cdev) 238 return -ENODEV; 239 240 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 241 return 0; 242 } 243 244 /* probing */ 245 static struct qed_dev *qed_probe(struct pci_dev *pdev, 246 enum qed_protocol protocol, 247 u32 dp_module, 248 u8 dp_level) 249 { 250 struct qed_dev *cdev; 251 int rc; 252 253 cdev = qed_alloc_cdev(pdev); 254 if (!cdev) 255 goto err0; 256 257 cdev->protocol = protocol; 258 259 qed_init_dp(cdev, dp_module, dp_level); 260 261 rc = qed_init_pci(cdev, pdev); 262 if (rc) { 263 DP_ERR(cdev, "init pci failed\n"); 264 goto err1; 265 } 266 DP_INFO(cdev, "PCI init completed successfully\n"); 267 268 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 269 if (rc) { 270 DP_ERR(cdev, "hw prepare failed\n"); 271 goto err2; 272 } 273 274 DP_INFO(cdev, "qed_probe completed successffuly\n"); 275 276 return cdev; 277 278 err2: 279 qed_free_pci(cdev); 280 err1: 281 qed_free_cdev(cdev); 282 err0: 283 return NULL; 284 } 285 286 static void qed_remove(struct qed_dev *cdev) 287 { 288 if (!cdev) 289 return; 290 291 qed_hw_remove(cdev); 292 293 qed_free_pci(cdev); 294 295 qed_set_power_state(cdev, PCI_D3hot); 296 297 qed_free_cdev(cdev); 298 } 299 300 static void qed_disable_msix(struct qed_dev *cdev) 301 { 302 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 303 pci_disable_msix(cdev->pdev); 304 kfree(cdev->int_params.msix_table); 305 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 306 pci_disable_msi(cdev->pdev); 307 } 308 309 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 310 } 311 312 static int qed_enable_msix(struct qed_dev *cdev, 313 struct qed_int_params *int_params) 314 { 315 int i, rc, cnt; 316 317 cnt = int_params->in.num_vectors; 318 319 for (i = 0; i < cnt; i++) 320 int_params->msix_table[i].entry = i; 321 322 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 323 int_params->in.min_msix_cnt, cnt); 324 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 325 (rc % cdev->num_hwfns)) { 326 pci_disable_msix(cdev->pdev); 327 328 /* If fastpath is initialized, we need at least one interrupt 329 * per hwfn [and the slow path interrupts]. New requested number 330 * should be a multiple of the number of hwfns. 331 */ 332 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 333 DP_NOTICE(cdev, 334 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 335 cnt, int_params->in.num_vectors); 336 rc = pci_enable_msix_exact(cdev->pdev, 337 int_params->msix_table, cnt); 338 if (!rc) 339 rc = cnt; 340 } 341 342 if (rc > 0) { 343 /* MSI-x configuration was achieved */ 344 int_params->out.int_mode = QED_INT_MODE_MSIX; 345 int_params->out.num_vectors = rc; 346 rc = 0; 347 } else { 348 DP_NOTICE(cdev, 349 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 350 cnt, rc); 351 } 352 353 return rc; 354 } 355 356 /* This function outputs the int mode and the number of enabled msix vector */ 357 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 358 { 359 struct qed_int_params *int_params = &cdev->int_params; 360 struct msix_entry *tbl; 361 int rc = 0, cnt; 362 363 switch (int_params->in.int_mode) { 364 case QED_INT_MODE_MSIX: 365 /* Allocate MSIX table */ 366 cnt = int_params->in.num_vectors; 367 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 368 if (!int_params->msix_table) { 369 rc = -ENOMEM; 370 goto out; 371 } 372 373 /* Enable MSIX */ 374 rc = qed_enable_msix(cdev, int_params); 375 if (!rc) 376 goto out; 377 378 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 379 kfree(int_params->msix_table); 380 if (force_mode) 381 goto out; 382 /* Fallthrough */ 383 384 case QED_INT_MODE_MSI: 385 rc = pci_enable_msi(cdev->pdev); 386 if (!rc) { 387 int_params->out.int_mode = QED_INT_MODE_MSI; 388 goto out; 389 } 390 391 DP_NOTICE(cdev, "Failed to enable MSI\n"); 392 if (force_mode) 393 goto out; 394 /* Fallthrough */ 395 396 case QED_INT_MODE_INTA: 397 int_params->out.int_mode = QED_INT_MODE_INTA; 398 rc = 0; 399 goto out; 400 default: 401 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 402 int_params->in.int_mode); 403 rc = -EINVAL; 404 } 405 406 out: 407 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 408 409 return rc; 410 } 411 412 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 413 int index, void(*handler)(void *)) 414 { 415 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 416 int relative_idx = index / cdev->num_hwfns; 417 418 hwfn->simd_proto_handler[relative_idx].func = handler; 419 hwfn->simd_proto_handler[relative_idx].token = token; 420 } 421 422 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 423 { 424 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 425 int relative_idx = index / cdev->num_hwfns; 426 427 memset(&hwfn->simd_proto_handler[relative_idx], 0, 428 sizeof(struct qed_simd_fp_handler)); 429 } 430 431 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 432 { 433 tasklet_schedule((struct tasklet_struct *)tasklet); 434 return IRQ_HANDLED; 435 } 436 437 static irqreturn_t qed_single_int(int irq, void *dev_instance) 438 { 439 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 440 struct qed_hwfn *hwfn; 441 irqreturn_t rc = IRQ_NONE; 442 u64 status; 443 int i, j; 444 445 for (i = 0; i < cdev->num_hwfns; i++) { 446 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 447 448 if (!status) 449 continue; 450 451 hwfn = &cdev->hwfns[i]; 452 453 /* Slowpath interrupt */ 454 if (unlikely(status & 0x1)) { 455 tasklet_schedule(hwfn->sp_dpc); 456 status &= ~0x1; 457 rc = IRQ_HANDLED; 458 } 459 460 /* Fastpath interrupts */ 461 for (j = 0; j < 64; j++) { 462 if ((0x2ULL << j) & status) { 463 hwfn->simd_proto_handler[j].func( 464 hwfn->simd_proto_handler[j].token); 465 status &= ~(0x2ULL << j); 466 rc = IRQ_HANDLED; 467 } 468 } 469 470 if (unlikely(status)) 471 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 472 "got an unknown interrupt status 0x%llx\n", 473 status); 474 } 475 476 return rc; 477 } 478 479 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 480 { 481 struct qed_dev *cdev = hwfn->cdev; 482 int rc = 0; 483 u8 id; 484 485 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 486 id = hwfn->my_id; 487 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 488 id, cdev->pdev->bus->number, 489 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 490 rc = request_irq(cdev->int_params.msix_table[id].vector, 491 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 492 if (!rc) 493 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 494 "Requested slowpath MSI-X\n"); 495 } else { 496 unsigned long flags = 0; 497 498 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 499 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 500 PCI_FUNC(cdev->pdev->devfn)); 501 502 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 503 flags |= IRQF_SHARED; 504 505 rc = request_irq(cdev->pdev->irq, qed_single_int, 506 flags, cdev->name, cdev); 507 } 508 509 return rc; 510 } 511 512 static void qed_slowpath_irq_free(struct qed_dev *cdev) 513 { 514 int i; 515 516 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 517 for_each_hwfn(cdev, i) { 518 if (!cdev->hwfns[i].b_int_requested) 519 break; 520 synchronize_irq(cdev->int_params.msix_table[i].vector); 521 free_irq(cdev->int_params.msix_table[i].vector, 522 cdev->hwfns[i].sp_dpc); 523 } 524 } else { 525 if (QED_LEADING_HWFN(cdev)->b_int_requested) 526 free_irq(cdev->pdev->irq, cdev); 527 } 528 qed_int_disable_post_isr_release(cdev); 529 } 530 531 static int qed_nic_stop(struct qed_dev *cdev) 532 { 533 int i, rc; 534 535 rc = qed_hw_stop(cdev); 536 537 for (i = 0; i < cdev->num_hwfns; i++) { 538 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 539 540 if (p_hwfn->b_sp_dpc_enabled) { 541 tasklet_disable(p_hwfn->sp_dpc); 542 p_hwfn->b_sp_dpc_enabled = false; 543 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 544 "Disabled sp taskelt [hwfn %d] at %p\n", 545 i, p_hwfn->sp_dpc); 546 } 547 } 548 549 return rc; 550 } 551 552 static int qed_nic_reset(struct qed_dev *cdev) 553 { 554 int rc; 555 556 rc = qed_hw_reset(cdev); 557 if (rc) 558 return rc; 559 560 qed_resc_free(cdev); 561 562 return 0; 563 } 564 565 static int qed_nic_setup(struct qed_dev *cdev) 566 { 567 int rc; 568 569 rc = qed_resc_alloc(cdev); 570 if (rc) 571 return rc; 572 573 DP_INFO(cdev, "Allocated qed resources\n"); 574 575 qed_resc_setup(cdev); 576 577 return rc; 578 } 579 580 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 581 { 582 int limit = 0; 583 584 /* Mark the fastpath as free/used */ 585 cdev->int_params.fp_initialized = cnt ? true : false; 586 587 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 588 limit = cdev->num_hwfns * 63; 589 else if (cdev->int_params.fp_msix_cnt) 590 limit = cdev->int_params.fp_msix_cnt; 591 592 if (!limit) 593 return -ENOMEM; 594 595 return min_t(int, cnt, limit); 596 } 597 598 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 599 { 600 memset(info, 0, sizeof(struct qed_int_info)); 601 602 if (!cdev->int_params.fp_initialized) { 603 DP_INFO(cdev, 604 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 605 return -EINVAL; 606 } 607 608 /* Need to expose only MSI-X information; Single IRQ is handled solely 609 * by qed. 610 */ 611 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 612 int msix_base = cdev->int_params.fp_msix_base; 613 614 info->msix_cnt = cdev->int_params.fp_msix_cnt; 615 info->msix = &cdev->int_params.msix_table[msix_base]; 616 } 617 618 return 0; 619 } 620 621 static int qed_slowpath_setup_int(struct qed_dev *cdev, 622 enum qed_int_mode int_mode) 623 { 624 int rc, i; 625 u8 num_vectors = 0; 626 627 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 628 629 cdev->int_params.in.int_mode = int_mode; 630 for_each_hwfn(cdev, i) 631 num_vectors += qed_int_get_num_sbs(&cdev->hwfns[i], NULL) + 1; 632 cdev->int_params.in.num_vectors = num_vectors; 633 634 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 635 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 636 637 rc = qed_set_int_mode(cdev, false); 638 if (rc) { 639 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 640 return rc; 641 } 642 643 cdev->int_params.fp_msix_base = cdev->num_hwfns; 644 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 645 cdev->num_hwfns; 646 647 return 0; 648 } 649 650 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 651 u8 *input_buf, u32 max_size, u8 *unzip_buf) 652 { 653 int rc; 654 655 p_hwfn->stream->next_in = input_buf; 656 p_hwfn->stream->avail_in = input_len; 657 p_hwfn->stream->next_out = unzip_buf; 658 p_hwfn->stream->avail_out = max_size; 659 660 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 661 662 if (rc != Z_OK) { 663 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 664 rc); 665 return 0; 666 } 667 668 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 669 zlib_inflateEnd(p_hwfn->stream); 670 671 if (rc != Z_OK && rc != Z_STREAM_END) { 672 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 673 p_hwfn->stream->msg, rc); 674 return 0; 675 } 676 677 return p_hwfn->stream->total_out / 4; 678 } 679 680 static int qed_alloc_stream_mem(struct qed_dev *cdev) 681 { 682 int i; 683 void *workspace; 684 685 for_each_hwfn(cdev, i) { 686 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 687 688 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 689 if (!p_hwfn->stream) 690 return -ENOMEM; 691 692 workspace = vzalloc(zlib_inflate_workspacesize()); 693 if (!workspace) 694 return -ENOMEM; 695 p_hwfn->stream->workspace = workspace; 696 } 697 698 return 0; 699 } 700 701 static void qed_free_stream_mem(struct qed_dev *cdev) 702 { 703 int i; 704 705 for_each_hwfn(cdev, i) { 706 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 707 708 if (!p_hwfn->stream) 709 return; 710 711 vfree(p_hwfn->stream->workspace); 712 kfree(p_hwfn->stream); 713 } 714 } 715 716 static void qed_update_pf_params(struct qed_dev *cdev, 717 struct qed_pf_params *params) 718 { 719 int i; 720 721 for (i = 0; i < cdev->num_hwfns; i++) { 722 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 723 724 p_hwfn->pf_params = *params; 725 } 726 } 727 728 static int qed_slowpath_start(struct qed_dev *cdev, 729 struct qed_slowpath_params *params) 730 { 731 struct qed_mcp_drv_version drv_version; 732 const u8 *data = NULL; 733 struct qed_hwfn *hwfn; 734 int rc; 735 736 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 737 &cdev->pdev->dev); 738 if (rc) { 739 DP_NOTICE(cdev, 740 "Failed to find fw file - /lib/firmware/%s\n", 741 QED_FW_FILE_NAME); 742 goto err; 743 } 744 745 rc = qed_nic_setup(cdev); 746 if (rc) 747 goto err; 748 749 rc = qed_slowpath_setup_int(cdev, params->int_mode); 750 if (rc) 751 goto err1; 752 753 /* Allocate stream for unzipping */ 754 rc = qed_alloc_stream_mem(cdev); 755 if (rc) { 756 DP_NOTICE(cdev, "Failed to allocate stream memory\n"); 757 goto err2; 758 } 759 760 /* Start the slowpath */ 761 data = cdev->firmware->data; 762 763 rc = qed_hw_init(cdev, true, cdev->int_params.out.int_mode, 764 true, data); 765 if (rc) 766 goto err3; 767 768 DP_INFO(cdev, 769 "HW initialization and function start completed successfully\n"); 770 771 hwfn = QED_LEADING_HWFN(cdev); 772 drv_version.version = (params->drv_major << 24) | 773 (params->drv_minor << 16) | 774 (params->drv_rev << 8) | 775 (params->drv_eng); 776 strlcpy(drv_version.name, params->name, 777 MCP_DRV_VER_STR_SIZE - 4); 778 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 779 &drv_version); 780 if (rc) { 781 DP_NOTICE(cdev, "Failed sending drv version command\n"); 782 return rc; 783 } 784 785 return 0; 786 787 err3: 788 qed_free_stream_mem(cdev); 789 qed_slowpath_irq_free(cdev); 790 err2: 791 qed_disable_msix(cdev); 792 err1: 793 qed_resc_free(cdev); 794 err: 795 release_firmware(cdev->firmware); 796 797 return rc; 798 } 799 800 static int qed_slowpath_stop(struct qed_dev *cdev) 801 { 802 if (!cdev) 803 return -ENODEV; 804 805 qed_free_stream_mem(cdev); 806 807 qed_nic_stop(cdev); 808 qed_slowpath_irq_free(cdev); 809 810 qed_disable_msix(cdev); 811 qed_nic_reset(cdev); 812 813 release_firmware(cdev->firmware); 814 815 return 0; 816 } 817 818 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE], 819 char ver_str[VER_SIZE]) 820 { 821 int i; 822 823 memcpy(cdev->name, name, NAME_SIZE); 824 for_each_hwfn(cdev, i) 825 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 826 827 memcpy(cdev->ver_str, ver_str, VER_SIZE); 828 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 829 } 830 831 static u32 qed_sb_init(struct qed_dev *cdev, 832 struct qed_sb_info *sb_info, 833 void *sb_virt_addr, 834 dma_addr_t sb_phy_addr, u16 sb_id, 835 enum qed_sb_type type) 836 { 837 struct qed_hwfn *p_hwfn; 838 int hwfn_index; 839 u16 rel_sb_id; 840 u8 n_hwfns; 841 u32 rc; 842 843 /* RoCE uses single engine and CMT uses two engines. When using both 844 * we force only a single engine. Storage uses only engine 0 too. 845 */ 846 if (type == QED_SB_TYPE_L2_QUEUE) 847 n_hwfns = cdev->num_hwfns; 848 else 849 n_hwfns = 1; 850 851 hwfn_index = sb_id % n_hwfns; 852 p_hwfn = &cdev->hwfns[hwfn_index]; 853 rel_sb_id = sb_id / n_hwfns; 854 855 DP_VERBOSE(cdev, NETIF_MSG_INTR, 856 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 857 hwfn_index, rel_sb_id, sb_id); 858 859 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 860 sb_virt_addr, sb_phy_addr, rel_sb_id); 861 862 return rc; 863 } 864 865 static u32 qed_sb_release(struct qed_dev *cdev, 866 struct qed_sb_info *sb_info, 867 u16 sb_id) 868 { 869 struct qed_hwfn *p_hwfn; 870 int hwfn_index; 871 u16 rel_sb_id; 872 u32 rc; 873 874 hwfn_index = sb_id % cdev->num_hwfns; 875 p_hwfn = &cdev->hwfns[hwfn_index]; 876 rel_sb_id = sb_id / cdev->num_hwfns; 877 878 DP_VERBOSE(cdev, NETIF_MSG_INTR, 879 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 880 hwfn_index, rel_sb_id, sb_id); 881 882 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 883 884 return rc; 885 } 886 887 static int qed_set_link(struct qed_dev *cdev, 888 struct qed_link_params *params) 889 { 890 struct qed_hwfn *hwfn; 891 struct qed_mcp_link_params *link_params; 892 struct qed_ptt *ptt; 893 int rc; 894 895 if (!cdev) 896 return -ENODEV; 897 898 /* The link should be set only once per PF */ 899 hwfn = &cdev->hwfns[0]; 900 901 ptt = qed_ptt_acquire(hwfn); 902 if (!ptt) 903 return -EBUSY; 904 905 link_params = qed_mcp_get_link_params(hwfn); 906 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 907 link_params->speed.autoneg = params->autoneg; 908 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 909 link_params->speed.advertised_speeds = 0; 910 if ((params->adv_speeds & SUPPORTED_1000baseT_Half) || 911 (params->adv_speeds & SUPPORTED_1000baseT_Full)) 912 link_params->speed.advertised_speeds |= 913 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 914 if (params->adv_speeds & SUPPORTED_10000baseKR_Full) 915 link_params->speed.advertised_speeds |= 916 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 917 if (params->adv_speeds & SUPPORTED_40000baseLR4_Full) 918 link_params->speed.advertised_speeds |= 919 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 920 if (params->adv_speeds & 0) 921 link_params->speed.advertised_speeds |= 922 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 923 if (params->adv_speeds & 0) 924 link_params->speed.advertised_speeds |= 925 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G; 926 } 927 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 928 link_params->speed.forced_speed = params->forced_speed; 929 930 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 931 932 qed_ptt_release(hwfn, ptt); 933 934 return rc; 935 } 936 937 static int qed_get_port_type(u32 media_type) 938 { 939 int port_type; 940 941 switch (media_type) { 942 case MEDIA_SFPP_10G_FIBER: 943 case MEDIA_SFP_1G_FIBER: 944 case MEDIA_XFP_FIBER: 945 case MEDIA_KR: 946 port_type = PORT_FIBRE; 947 break; 948 case MEDIA_DA_TWINAX: 949 port_type = PORT_DA; 950 break; 951 case MEDIA_BASE_T: 952 port_type = PORT_TP; 953 break; 954 case MEDIA_NOT_PRESENT: 955 port_type = PORT_NONE; 956 break; 957 case MEDIA_UNSPECIFIED: 958 default: 959 port_type = PORT_OTHER; 960 break; 961 } 962 return port_type; 963 } 964 965 static void qed_fill_link(struct qed_hwfn *hwfn, 966 struct qed_link_output *if_link) 967 { 968 struct qed_mcp_link_params params; 969 struct qed_mcp_link_state link; 970 struct qed_mcp_link_capabilities link_caps; 971 u32 media_type; 972 973 memset(if_link, 0, sizeof(*if_link)); 974 975 /* Prepare source inputs */ 976 memcpy(¶ms, qed_mcp_get_link_params(hwfn), sizeof(params)); 977 memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link)); 978 memcpy(&link_caps, qed_mcp_get_link_capabilities(hwfn), 979 sizeof(link_caps)); 980 981 /* Set the link parameters to pass to protocol driver */ 982 if (link.link_up) 983 if_link->link_up = true; 984 985 /* TODO - at the moment assume supported and advertised speed equal */ 986 if_link->supported_caps = SUPPORTED_FIBRE; 987 if (params.speed.autoneg) 988 if_link->supported_caps |= SUPPORTED_Autoneg; 989 if (params.pause.autoneg || 990 (params.pause.forced_rx && params.pause.forced_tx)) 991 if_link->supported_caps |= SUPPORTED_Asym_Pause; 992 if (params.pause.autoneg || params.pause.forced_rx || 993 params.pause.forced_tx) 994 if_link->supported_caps |= SUPPORTED_Pause; 995 996 if_link->advertised_caps = if_link->supported_caps; 997 if (params.speed.advertised_speeds & 998 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 999 if_link->advertised_caps |= SUPPORTED_1000baseT_Half | 1000 SUPPORTED_1000baseT_Full; 1001 if (params.speed.advertised_speeds & 1002 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1003 if_link->advertised_caps |= SUPPORTED_10000baseKR_Full; 1004 if (params.speed.advertised_speeds & 1005 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1006 if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full; 1007 if (params.speed.advertised_speeds & 1008 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1009 if_link->advertised_caps |= 0; 1010 if (params.speed.advertised_speeds & 1011 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G) 1012 if_link->advertised_caps |= 0; 1013 1014 if (link_caps.speed_capabilities & 1015 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1016 if_link->supported_caps |= SUPPORTED_1000baseT_Half | 1017 SUPPORTED_1000baseT_Full; 1018 if (link_caps.speed_capabilities & 1019 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1020 if_link->supported_caps |= SUPPORTED_10000baseKR_Full; 1021 if (link_caps.speed_capabilities & 1022 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1023 if_link->supported_caps |= SUPPORTED_40000baseLR4_Full; 1024 if (link_caps.speed_capabilities & 1025 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1026 if_link->supported_caps |= 0; 1027 if (link_caps.speed_capabilities & 1028 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G) 1029 if_link->supported_caps |= 0; 1030 1031 if (link.link_up) 1032 if_link->speed = link.speed; 1033 1034 /* TODO - fill duplex properly */ 1035 if_link->duplex = DUPLEX_FULL; 1036 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1037 if_link->port = qed_get_port_type(media_type); 1038 1039 if_link->autoneg = params.speed.autoneg; 1040 1041 if (params.pause.autoneg) 1042 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1043 if (params.pause.forced_rx) 1044 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1045 if (params.pause.forced_tx) 1046 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1047 1048 /* Link partner capabilities */ 1049 if (link.partner_adv_speed & 1050 QED_LINK_PARTNER_SPEED_1G_HD) 1051 if_link->lp_caps |= SUPPORTED_1000baseT_Half; 1052 if (link.partner_adv_speed & 1053 QED_LINK_PARTNER_SPEED_1G_FD) 1054 if_link->lp_caps |= SUPPORTED_1000baseT_Full; 1055 if (link.partner_adv_speed & 1056 QED_LINK_PARTNER_SPEED_10G) 1057 if_link->lp_caps |= SUPPORTED_10000baseKR_Full; 1058 if (link.partner_adv_speed & 1059 QED_LINK_PARTNER_SPEED_40G) 1060 if_link->lp_caps |= SUPPORTED_40000baseLR4_Full; 1061 if (link.partner_adv_speed & 1062 QED_LINK_PARTNER_SPEED_50G) 1063 if_link->lp_caps |= 0; 1064 if (link.partner_adv_speed & 1065 QED_LINK_PARTNER_SPEED_100G) 1066 if_link->lp_caps |= 0; 1067 1068 if (link.an_complete) 1069 if_link->lp_caps |= SUPPORTED_Autoneg; 1070 1071 if (link.partner_adv_pause) 1072 if_link->lp_caps |= SUPPORTED_Pause; 1073 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1074 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1075 if_link->lp_caps |= SUPPORTED_Asym_Pause; 1076 } 1077 1078 static void qed_get_current_link(struct qed_dev *cdev, 1079 struct qed_link_output *if_link) 1080 { 1081 qed_fill_link(&cdev->hwfns[0], if_link); 1082 } 1083 1084 void qed_link_update(struct qed_hwfn *hwfn) 1085 { 1086 void *cookie = hwfn->cdev->ops_cookie; 1087 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1088 struct qed_link_output if_link; 1089 1090 qed_fill_link(hwfn, &if_link); 1091 1092 if (IS_LEAD_HWFN(hwfn) && cookie) 1093 op->link_update(cookie, &if_link); 1094 } 1095 1096 static int qed_drain(struct qed_dev *cdev) 1097 { 1098 struct qed_hwfn *hwfn; 1099 struct qed_ptt *ptt; 1100 int i, rc; 1101 1102 for_each_hwfn(cdev, i) { 1103 hwfn = &cdev->hwfns[i]; 1104 ptt = qed_ptt_acquire(hwfn); 1105 if (!ptt) { 1106 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1107 return -EBUSY; 1108 } 1109 rc = qed_mcp_drain(hwfn, ptt); 1110 if (rc) 1111 return rc; 1112 qed_ptt_release(hwfn, ptt); 1113 } 1114 1115 return 0; 1116 } 1117 1118 const struct qed_common_ops qed_common_ops_pass = { 1119 .probe = &qed_probe, 1120 .remove = &qed_remove, 1121 .set_power_state = &qed_set_power_state, 1122 .set_id = &qed_set_id, 1123 .update_pf_params = &qed_update_pf_params, 1124 .slowpath_start = &qed_slowpath_start, 1125 .slowpath_stop = &qed_slowpath_stop, 1126 .set_fp_int = &qed_set_int_fp, 1127 .get_fp_int = &qed_get_int_fp, 1128 .sb_init = &qed_sb_init, 1129 .sb_release = &qed_sb_release, 1130 .simd_handler_config = &qed_simd_handler_config, 1131 .simd_handler_clean = &qed_simd_handler_clean, 1132 .set_link = &qed_set_link, 1133 .get_link = &qed_get_current_link, 1134 .drain = &qed_drain, 1135 .update_msglvl = &qed_init_dp, 1136 .chain_alloc = &qed_chain_alloc, 1137 .chain_free = &qed_chain_free, 1138 }; 1139 1140 u32 qed_get_protocol_version(enum qed_protocol protocol) 1141 { 1142 switch (protocol) { 1143 case QED_PROTOCOL_ETH: 1144 return QED_ETH_INTERFACE_VERSION; 1145 default: 1146 return 0; 1147 } 1148 } 1149 EXPORT_SYMBOL(qed_get_protocol_version); 1150