1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/stddef.h> 34 #include <linux/pci.h> 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/string.h> 41 #include <linux/module.h> 42 #include <linux/interrupt.h> 43 #include <linux/workqueue.h> 44 #include <linux/ethtool.h> 45 #include <linux/etherdevice.h> 46 #include <linux/vmalloc.h> 47 #include <linux/crash_dump.h> 48 #include <linux/crc32.h> 49 #include <linux/qed/qed_if.h> 50 #include <linux/qed/qed_ll2_if.h> 51 52 #include "qed.h" 53 #include "qed_sriov.h" 54 #include "qed_sp.h" 55 #include "qed_dev_api.h" 56 #include "qed_ll2.h" 57 #include "qed_fcoe.h" 58 #include "qed_iscsi.h" 59 60 #include "qed_mcp.h" 61 #include "qed_hw.h" 62 #include "qed_selftest.h" 63 #include "qed_debug.h" 64 65 #define QED_ROCE_QPS (8192) 66 #define QED_ROCE_DPIS (8) 67 68 static char version[] = 69 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 70 71 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 72 MODULE_LICENSE("GPL"); 73 MODULE_VERSION(DRV_MODULE_VERSION); 74 75 #define FW_FILE_VERSION \ 76 __stringify(FW_MAJOR_VERSION) "." \ 77 __stringify(FW_MINOR_VERSION) "." \ 78 __stringify(FW_REVISION_VERSION) "." \ 79 __stringify(FW_ENGINEERING_VERSION) 80 81 #define QED_FW_FILE_NAME \ 82 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 83 84 MODULE_FIRMWARE(QED_FW_FILE_NAME); 85 86 static int __init qed_init(void) 87 { 88 pr_info("%s", version); 89 90 return 0; 91 } 92 93 static void __exit qed_cleanup(void) 94 { 95 pr_notice("qed_cleanup called\n"); 96 } 97 98 module_init(qed_init); 99 module_exit(qed_cleanup); 100 101 /* Check if the DMA controller on the machine can properly handle the DMA 102 * addressing required by the device. 103 */ 104 static int qed_set_coherency_mask(struct qed_dev *cdev) 105 { 106 struct device *dev = &cdev->pdev->dev; 107 108 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 109 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 110 DP_NOTICE(cdev, 111 "Can't request 64-bit consistent allocations\n"); 112 return -EIO; 113 } 114 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 115 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 116 return -EIO; 117 } 118 119 return 0; 120 } 121 122 static void qed_free_pci(struct qed_dev *cdev) 123 { 124 struct pci_dev *pdev = cdev->pdev; 125 126 if (cdev->doorbells && cdev->db_size) 127 iounmap(cdev->doorbells); 128 if (cdev->regview) 129 iounmap(cdev->regview); 130 if (atomic_read(&pdev->enable_cnt) == 1) 131 pci_release_regions(pdev); 132 133 pci_disable_device(pdev); 134 } 135 136 #define PCI_REVISION_ID_ERROR_VAL 0xff 137 138 /* Performs PCI initializations as well as initializing PCI-related parameters 139 * in the device structrue. Returns 0 in case of success. 140 */ 141 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 142 { 143 u8 rev_id; 144 int rc; 145 146 cdev->pdev = pdev; 147 148 rc = pci_enable_device(pdev); 149 if (rc) { 150 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 151 goto err0; 152 } 153 154 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 155 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 156 rc = -EIO; 157 goto err1; 158 } 159 160 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 161 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 162 rc = -EIO; 163 goto err1; 164 } 165 166 if (atomic_read(&pdev->enable_cnt) == 1) { 167 rc = pci_request_regions(pdev, "qed"); 168 if (rc) { 169 DP_NOTICE(cdev, 170 "Failed to request PCI memory resources\n"); 171 goto err1; 172 } 173 pci_set_master(pdev); 174 pci_save_state(pdev); 175 } 176 177 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 178 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 179 DP_NOTICE(cdev, 180 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 181 rev_id); 182 rc = -ENODEV; 183 goto err2; 184 } 185 if (!pci_is_pcie(pdev)) { 186 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 187 rc = -EIO; 188 goto err2; 189 } 190 191 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 192 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 193 DP_NOTICE(cdev, "Cannot find power management capability\n"); 194 195 rc = qed_set_coherency_mask(cdev); 196 if (rc) 197 goto err2; 198 199 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 200 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 201 cdev->pci_params.irq = pdev->irq; 202 203 cdev->regview = pci_ioremap_bar(pdev, 0); 204 if (!cdev->regview) { 205 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 206 rc = -ENOMEM; 207 goto err2; 208 } 209 210 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 211 cdev->db_size = pci_resource_len(cdev->pdev, 2); 212 if (!cdev->db_size) { 213 if (IS_PF(cdev)) { 214 DP_NOTICE(cdev, "No Doorbell bar available\n"); 215 return -EINVAL; 216 } else { 217 return 0; 218 } 219 } 220 221 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 222 223 if (!cdev->doorbells) { 224 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 225 return -ENOMEM; 226 } 227 228 return 0; 229 230 err2: 231 pci_release_regions(pdev); 232 err1: 233 pci_disable_device(pdev); 234 err0: 235 return rc; 236 } 237 238 int qed_fill_dev_info(struct qed_dev *cdev, 239 struct qed_dev_info *dev_info) 240 { 241 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 242 struct qed_hw_info *hw_info = &p_hwfn->hw_info; 243 struct qed_tunnel_info *tun = &cdev->tunnel; 244 struct qed_ptt *ptt; 245 246 memset(dev_info, 0, sizeof(struct qed_dev_info)); 247 248 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 249 tun->vxlan.b_mode_enabled) 250 dev_info->vxlan_enable = true; 251 252 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled && 253 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 254 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 255 dev_info->gre_enable = true; 256 257 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled && 258 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 259 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 260 dev_info->geneve_enable = true; 261 262 dev_info->num_hwfns = cdev->num_hwfns; 263 dev_info->pci_mem_start = cdev->pci_params.mem_start; 264 dev_info->pci_mem_end = cdev->pci_params.mem_end; 265 dev_info->pci_irq = cdev->pci_params.irq; 266 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn); 267 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]); 268 dev_info->dev_type = cdev->type; 269 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr); 270 271 if (IS_PF(cdev)) { 272 dev_info->fw_major = FW_MAJOR_VERSION; 273 dev_info->fw_minor = FW_MINOR_VERSION; 274 dev_info->fw_rev = FW_REVISION_VERSION; 275 dev_info->fw_eng = FW_ENGINEERING_VERSION; 276 dev_info->mf_mode = cdev->mf_mode; 277 dev_info->tx_switching = true; 278 279 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME) 280 dev_info->wol_support = true; 281 282 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id; 283 } else { 284 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 285 &dev_info->fw_minor, &dev_info->fw_rev, 286 &dev_info->fw_eng); 287 } 288 289 if (IS_PF(cdev)) { 290 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 291 if (ptt) { 292 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 293 &dev_info->mfw_rev, NULL); 294 295 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt, 296 &dev_info->mbi_version); 297 298 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 299 &dev_info->flash_size); 300 301 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 302 } 303 } else { 304 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 305 &dev_info->mfw_rev, NULL); 306 } 307 308 dev_info->mtu = hw_info->mtu; 309 310 return 0; 311 } 312 313 static void qed_free_cdev(struct qed_dev *cdev) 314 { 315 kfree((void *)cdev); 316 } 317 318 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 319 { 320 struct qed_dev *cdev; 321 322 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 323 if (!cdev) 324 return cdev; 325 326 qed_init_struct(cdev); 327 328 return cdev; 329 } 330 331 /* Sets the requested power state */ 332 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 333 { 334 if (!cdev) 335 return -ENODEV; 336 337 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 338 return 0; 339 } 340 341 /* probing */ 342 static struct qed_dev *qed_probe(struct pci_dev *pdev, 343 struct qed_probe_params *params) 344 { 345 struct qed_dev *cdev; 346 int rc; 347 348 cdev = qed_alloc_cdev(pdev); 349 if (!cdev) 350 goto err0; 351 352 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 353 cdev->protocol = params->protocol; 354 355 if (params->is_vf) 356 cdev->b_is_vf = true; 357 358 qed_init_dp(cdev, params->dp_module, params->dp_level); 359 360 rc = qed_init_pci(cdev, pdev); 361 if (rc) { 362 DP_ERR(cdev, "init pci failed\n"); 363 goto err1; 364 } 365 DP_INFO(cdev, "PCI init completed successfully\n"); 366 367 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 368 if (rc) { 369 DP_ERR(cdev, "hw prepare failed\n"); 370 goto err2; 371 } 372 373 DP_INFO(cdev, "qed_probe completed successffuly\n"); 374 375 return cdev; 376 377 err2: 378 qed_free_pci(cdev); 379 err1: 380 qed_free_cdev(cdev); 381 err0: 382 return NULL; 383 } 384 385 static void qed_remove(struct qed_dev *cdev) 386 { 387 if (!cdev) 388 return; 389 390 qed_hw_remove(cdev); 391 392 qed_free_pci(cdev); 393 394 qed_set_power_state(cdev, PCI_D3hot); 395 396 qed_free_cdev(cdev); 397 } 398 399 static void qed_disable_msix(struct qed_dev *cdev) 400 { 401 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 402 pci_disable_msix(cdev->pdev); 403 kfree(cdev->int_params.msix_table); 404 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 405 pci_disable_msi(cdev->pdev); 406 } 407 408 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 409 } 410 411 static int qed_enable_msix(struct qed_dev *cdev, 412 struct qed_int_params *int_params) 413 { 414 int i, rc, cnt; 415 416 cnt = int_params->in.num_vectors; 417 418 for (i = 0; i < cnt; i++) 419 int_params->msix_table[i].entry = i; 420 421 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 422 int_params->in.min_msix_cnt, cnt); 423 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 424 (rc % cdev->num_hwfns)) { 425 pci_disable_msix(cdev->pdev); 426 427 /* If fastpath is initialized, we need at least one interrupt 428 * per hwfn [and the slow path interrupts]. New requested number 429 * should be a multiple of the number of hwfns. 430 */ 431 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 432 DP_NOTICE(cdev, 433 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 434 cnt, int_params->in.num_vectors); 435 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 436 cnt); 437 if (!rc) 438 rc = cnt; 439 } 440 441 if (rc > 0) { 442 /* MSI-x configuration was achieved */ 443 int_params->out.int_mode = QED_INT_MODE_MSIX; 444 int_params->out.num_vectors = rc; 445 rc = 0; 446 } else { 447 DP_NOTICE(cdev, 448 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 449 cnt, rc); 450 } 451 452 return rc; 453 } 454 455 /* This function outputs the int mode and the number of enabled msix vector */ 456 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 457 { 458 struct qed_int_params *int_params = &cdev->int_params; 459 struct msix_entry *tbl; 460 int rc = 0, cnt; 461 462 switch (int_params->in.int_mode) { 463 case QED_INT_MODE_MSIX: 464 /* Allocate MSIX table */ 465 cnt = int_params->in.num_vectors; 466 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 467 if (!int_params->msix_table) { 468 rc = -ENOMEM; 469 goto out; 470 } 471 472 /* Enable MSIX */ 473 rc = qed_enable_msix(cdev, int_params); 474 if (!rc) 475 goto out; 476 477 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 478 kfree(int_params->msix_table); 479 if (force_mode) 480 goto out; 481 /* Fallthrough */ 482 483 case QED_INT_MODE_MSI: 484 if (cdev->num_hwfns == 1) { 485 rc = pci_enable_msi(cdev->pdev); 486 if (!rc) { 487 int_params->out.int_mode = QED_INT_MODE_MSI; 488 goto out; 489 } 490 491 DP_NOTICE(cdev, "Failed to enable MSI\n"); 492 if (force_mode) 493 goto out; 494 } 495 /* Fallthrough */ 496 497 case QED_INT_MODE_INTA: 498 int_params->out.int_mode = QED_INT_MODE_INTA; 499 rc = 0; 500 goto out; 501 default: 502 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 503 int_params->in.int_mode); 504 rc = -EINVAL; 505 } 506 507 out: 508 if (!rc) 509 DP_INFO(cdev, "Using %s interrupts\n", 510 int_params->out.int_mode == QED_INT_MODE_INTA ? 511 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 512 "MSI" : "MSIX"); 513 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 514 515 return rc; 516 } 517 518 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 519 int index, void(*handler)(void *)) 520 { 521 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 522 int relative_idx = index / cdev->num_hwfns; 523 524 hwfn->simd_proto_handler[relative_idx].func = handler; 525 hwfn->simd_proto_handler[relative_idx].token = token; 526 } 527 528 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 529 { 530 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 531 int relative_idx = index / cdev->num_hwfns; 532 533 memset(&hwfn->simd_proto_handler[relative_idx], 0, 534 sizeof(struct qed_simd_fp_handler)); 535 } 536 537 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 538 { 539 tasklet_schedule((struct tasklet_struct *)tasklet); 540 return IRQ_HANDLED; 541 } 542 543 static irqreturn_t qed_single_int(int irq, void *dev_instance) 544 { 545 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 546 struct qed_hwfn *hwfn; 547 irqreturn_t rc = IRQ_NONE; 548 u64 status; 549 int i, j; 550 551 for (i = 0; i < cdev->num_hwfns; i++) { 552 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 553 554 if (!status) 555 continue; 556 557 hwfn = &cdev->hwfns[i]; 558 559 /* Slowpath interrupt */ 560 if (unlikely(status & 0x1)) { 561 tasklet_schedule(hwfn->sp_dpc); 562 status &= ~0x1; 563 rc = IRQ_HANDLED; 564 } 565 566 /* Fastpath interrupts */ 567 for (j = 0; j < 64; j++) { 568 if ((0x2ULL << j) & status) { 569 hwfn->simd_proto_handler[j].func( 570 hwfn->simd_proto_handler[j].token); 571 status &= ~(0x2ULL << j); 572 rc = IRQ_HANDLED; 573 } 574 } 575 576 if (unlikely(status)) 577 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 578 "got an unknown interrupt status 0x%llx\n", 579 status); 580 } 581 582 return rc; 583 } 584 585 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 586 { 587 struct qed_dev *cdev = hwfn->cdev; 588 u32 int_mode; 589 int rc = 0; 590 u8 id; 591 592 int_mode = cdev->int_params.out.int_mode; 593 if (int_mode == QED_INT_MODE_MSIX) { 594 id = hwfn->my_id; 595 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 596 id, cdev->pdev->bus->number, 597 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 598 rc = request_irq(cdev->int_params.msix_table[id].vector, 599 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 600 } else { 601 unsigned long flags = 0; 602 603 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 604 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 605 PCI_FUNC(cdev->pdev->devfn)); 606 607 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 608 flags |= IRQF_SHARED; 609 610 rc = request_irq(cdev->pdev->irq, qed_single_int, 611 flags, cdev->name, cdev); 612 } 613 614 if (rc) 615 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 616 else 617 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 618 "Requested slowpath %s\n", 619 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 620 621 return rc; 622 } 623 624 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn) 625 { 626 /* Calling the disable function will make sure that any 627 * currently-running function is completed. The following call to the 628 * enable function makes this sequence a flush-like operation. 629 */ 630 if (p_hwfn->b_sp_dpc_enabled) { 631 tasklet_disable(p_hwfn->sp_dpc); 632 tasklet_enable(p_hwfn->sp_dpc); 633 } 634 } 635 636 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn) 637 { 638 struct qed_dev *cdev = p_hwfn->cdev; 639 u8 id = p_hwfn->my_id; 640 u32 int_mode; 641 642 int_mode = cdev->int_params.out.int_mode; 643 if (int_mode == QED_INT_MODE_MSIX) 644 synchronize_irq(cdev->int_params.msix_table[id].vector); 645 else 646 synchronize_irq(cdev->pdev->irq); 647 648 qed_slowpath_tasklet_flush(p_hwfn); 649 } 650 651 static void qed_slowpath_irq_free(struct qed_dev *cdev) 652 { 653 int i; 654 655 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 656 for_each_hwfn(cdev, i) { 657 if (!cdev->hwfns[i].b_int_requested) 658 break; 659 synchronize_irq(cdev->int_params.msix_table[i].vector); 660 free_irq(cdev->int_params.msix_table[i].vector, 661 cdev->hwfns[i].sp_dpc); 662 } 663 } else { 664 if (QED_LEADING_HWFN(cdev)->b_int_requested) 665 free_irq(cdev->pdev->irq, cdev); 666 } 667 qed_int_disable_post_isr_release(cdev); 668 } 669 670 static int qed_nic_stop(struct qed_dev *cdev) 671 { 672 int i, rc; 673 674 rc = qed_hw_stop(cdev); 675 676 for (i = 0; i < cdev->num_hwfns; i++) { 677 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 678 679 if (p_hwfn->b_sp_dpc_enabled) { 680 tasklet_disable(p_hwfn->sp_dpc); 681 p_hwfn->b_sp_dpc_enabled = false; 682 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 683 "Disabled sp taskelt [hwfn %d] at %p\n", 684 i, p_hwfn->sp_dpc); 685 } 686 } 687 688 qed_dbg_pf_exit(cdev); 689 690 return rc; 691 } 692 693 static int qed_nic_setup(struct qed_dev *cdev) 694 { 695 int rc, i; 696 697 /* Determine if interface is going to require LL2 */ 698 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 699 for (i = 0; i < cdev->num_hwfns; i++) { 700 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 701 702 p_hwfn->using_ll2 = true; 703 } 704 } 705 706 rc = qed_resc_alloc(cdev); 707 if (rc) 708 return rc; 709 710 DP_INFO(cdev, "Allocated qed resources\n"); 711 712 qed_resc_setup(cdev); 713 714 return rc; 715 } 716 717 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 718 { 719 int limit = 0; 720 721 /* Mark the fastpath as free/used */ 722 cdev->int_params.fp_initialized = cnt ? true : false; 723 724 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 725 limit = cdev->num_hwfns * 63; 726 else if (cdev->int_params.fp_msix_cnt) 727 limit = cdev->int_params.fp_msix_cnt; 728 729 if (!limit) 730 return -ENOMEM; 731 732 return min_t(int, cnt, limit); 733 } 734 735 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 736 { 737 memset(info, 0, sizeof(struct qed_int_info)); 738 739 if (!cdev->int_params.fp_initialized) { 740 DP_INFO(cdev, 741 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 742 return -EINVAL; 743 } 744 745 /* Need to expose only MSI-X information; Single IRQ is handled solely 746 * by qed. 747 */ 748 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 749 int msix_base = cdev->int_params.fp_msix_base; 750 751 info->msix_cnt = cdev->int_params.fp_msix_cnt; 752 info->msix = &cdev->int_params.msix_table[msix_base]; 753 } 754 755 return 0; 756 } 757 758 static int qed_slowpath_setup_int(struct qed_dev *cdev, 759 enum qed_int_mode int_mode) 760 { 761 struct qed_sb_cnt_info sb_cnt_info; 762 int num_l2_queues = 0; 763 int rc; 764 int i; 765 766 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 767 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 768 return -EINVAL; 769 } 770 771 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 772 cdev->int_params.in.int_mode = int_mode; 773 for_each_hwfn(cdev, i) { 774 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 775 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 776 cdev->int_params.in.num_vectors += sb_cnt_info.cnt; 777 cdev->int_params.in.num_vectors++; /* slowpath */ 778 } 779 780 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 781 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 782 783 rc = qed_set_int_mode(cdev, false); 784 if (rc) { 785 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 786 return rc; 787 } 788 789 cdev->int_params.fp_msix_base = cdev->num_hwfns; 790 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 791 cdev->num_hwfns; 792 793 if (!IS_ENABLED(CONFIG_QED_RDMA) || 794 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) 795 return 0; 796 797 for_each_hwfn(cdev, i) 798 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 799 800 DP_VERBOSE(cdev, QED_MSG_RDMA, 801 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 802 cdev->int_params.fp_msix_cnt, num_l2_queues); 803 804 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 805 cdev->int_params.rdma_msix_cnt = 806 (cdev->int_params.fp_msix_cnt - num_l2_queues) 807 / cdev->num_hwfns; 808 cdev->int_params.rdma_msix_base = 809 cdev->int_params.fp_msix_base + num_l2_queues; 810 cdev->int_params.fp_msix_cnt = num_l2_queues; 811 } else { 812 cdev->int_params.rdma_msix_cnt = 0; 813 } 814 815 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 816 cdev->int_params.rdma_msix_cnt, 817 cdev->int_params.rdma_msix_base); 818 819 return 0; 820 } 821 822 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 823 { 824 int rc; 825 826 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 827 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 828 829 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 830 &cdev->int_params.in.num_vectors); 831 if (cdev->num_hwfns > 1) { 832 u8 vectors = 0; 833 834 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 835 cdev->int_params.in.num_vectors += vectors; 836 } 837 838 /* We want a minimum of one fastpath vector per vf hwfn */ 839 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 840 841 rc = qed_set_int_mode(cdev, true); 842 if (rc) 843 return rc; 844 845 cdev->int_params.fp_msix_base = 0; 846 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 847 848 return 0; 849 } 850 851 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 852 u8 *input_buf, u32 max_size, u8 *unzip_buf) 853 { 854 int rc; 855 856 p_hwfn->stream->next_in = input_buf; 857 p_hwfn->stream->avail_in = input_len; 858 p_hwfn->stream->next_out = unzip_buf; 859 p_hwfn->stream->avail_out = max_size; 860 861 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 862 863 if (rc != Z_OK) { 864 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 865 rc); 866 return 0; 867 } 868 869 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 870 zlib_inflateEnd(p_hwfn->stream); 871 872 if (rc != Z_OK && rc != Z_STREAM_END) { 873 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 874 p_hwfn->stream->msg, rc); 875 return 0; 876 } 877 878 return p_hwfn->stream->total_out / 4; 879 } 880 881 static int qed_alloc_stream_mem(struct qed_dev *cdev) 882 { 883 int i; 884 void *workspace; 885 886 for_each_hwfn(cdev, i) { 887 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 888 889 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 890 if (!p_hwfn->stream) 891 return -ENOMEM; 892 893 workspace = vzalloc(zlib_inflate_workspacesize()); 894 if (!workspace) 895 return -ENOMEM; 896 p_hwfn->stream->workspace = workspace; 897 } 898 899 return 0; 900 } 901 902 static void qed_free_stream_mem(struct qed_dev *cdev) 903 { 904 int i; 905 906 for_each_hwfn(cdev, i) { 907 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 908 909 if (!p_hwfn->stream) 910 return; 911 912 vfree(p_hwfn->stream->workspace); 913 kfree(p_hwfn->stream); 914 } 915 } 916 917 static void qed_update_pf_params(struct qed_dev *cdev, 918 struct qed_pf_params *params) 919 { 920 int i; 921 922 if (IS_ENABLED(CONFIG_QED_RDMA)) { 923 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 924 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 925 /* divide by 3 the MRs to avoid MF ILT overflow */ 926 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 927 } 928 929 if (cdev->num_hwfns > 1 || IS_VF(cdev)) 930 params->eth_pf_params.num_arfs_filters = 0; 931 932 /* In case we might support RDMA, don't allow qede to be greedy 933 * with the L2 contexts. Allow for 64 queues [rx, tx, xdp] per hwfn. 934 */ 935 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) { 936 u16 *num_cons; 937 938 num_cons = ¶ms->eth_pf_params.num_cons; 939 *num_cons = min_t(u16, *num_cons, 192); 940 } 941 942 for (i = 0; i < cdev->num_hwfns; i++) { 943 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 944 945 p_hwfn->pf_params = *params; 946 } 947 } 948 949 static int qed_slowpath_start(struct qed_dev *cdev, 950 struct qed_slowpath_params *params) 951 { 952 struct qed_drv_load_params drv_load_params; 953 struct qed_hw_init_params hw_init_params; 954 struct qed_mcp_drv_version drv_version; 955 struct qed_tunnel_info tunn_info; 956 const u8 *data = NULL; 957 struct qed_hwfn *hwfn; 958 struct qed_ptt *p_ptt; 959 int rc = -EINVAL; 960 961 if (qed_iov_wq_start(cdev)) 962 goto err; 963 964 if (IS_PF(cdev)) { 965 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 966 &cdev->pdev->dev); 967 if (rc) { 968 DP_NOTICE(cdev, 969 "Failed to find fw file - /lib/firmware/%s\n", 970 QED_FW_FILE_NAME); 971 goto err; 972 } 973 974 if (cdev->num_hwfns == 1) { 975 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 976 if (p_ptt) { 977 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt; 978 } else { 979 DP_NOTICE(cdev, 980 "Failed to acquire PTT for aRFS\n"); 981 goto err; 982 } 983 } 984 } 985 986 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; 987 rc = qed_nic_setup(cdev); 988 if (rc) 989 goto err; 990 991 if (IS_PF(cdev)) 992 rc = qed_slowpath_setup_int(cdev, params->int_mode); 993 else 994 rc = qed_slowpath_vf_setup_int(cdev); 995 if (rc) 996 goto err1; 997 998 if (IS_PF(cdev)) { 999 /* Allocate stream for unzipping */ 1000 rc = qed_alloc_stream_mem(cdev); 1001 if (rc) 1002 goto err2; 1003 1004 /* First Dword used to differentiate between various sources */ 1005 data = cdev->firmware->data + sizeof(u32); 1006 1007 qed_dbg_pf_init(cdev); 1008 } 1009 1010 /* Start the slowpath */ 1011 memset(&hw_init_params, 0, sizeof(hw_init_params)); 1012 memset(&tunn_info, 0, sizeof(tunn_info)); 1013 tunn_info.vxlan.b_mode_enabled = true; 1014 tunn_info.l2_gre.b_mode_enabled = true; 1015 tunn_info.ip_gre.b_mode_enabled = true; 1016 tunn_info.l2_geneve.b_mode_enabled = true; 1017 tunn_info.ip_geneve.b_mode_enabled = true; 1018 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1019 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1020 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1021 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1022 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1023 hw_init_params.p_tunn = &tunn_info; 1024 hw_init_params.b_hw_start = true; 1025 hw_init_params.int_mode = cdev->int_params.out.int_mode; 1026 hw_init_params.allow_npar_tx_switch = true; 1027 hw_init_params.bin_fw_data = data; 1028 1029 memset(&drv_load_params, 0, sizeof(drv_load_params)); 1030 drv_load_params.is_crash_kernel = is_kdump_kernel(); 1031 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT; 1032 drv_load_params.avoid_eng_reset = false; 1033 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE; 1034 hw_init_params.p_drv_load_params = &drv_load_params; 1035 1036 rc = qed_hw_init(cdev, &hw_init_params); 1037 if (rc) 1038 goto err2; 1039 1040 DP_INFO(cdev, 1041 "HW initialization and function start completed successfully\n"); 1042 1043 if (IS_PF(cdev)) { 1044 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) | 1045 BIT(QED_MODE_L2GENEVE_TUNN) | 1046 BIT(QED_MODE_IPGENEVE_TUNN) | 1047 BIT(QED_MODE_L2GRE_TUNN) | 1048 BIT(QED_MODE_IPGRE_TUNN)); 1049 } 1050 1051 /* Allocate LL2 interface if needed */ 1052 if (QED_LEADING_HWFN(cdev)->using_ll2) { 1053 rc = qed_ll2_alloc_if(cdev); 1054 if (rc) 1055 goto err3; 1056 } 1057 if (IS_PF(cdev)) { 1058 hwfn = QED_LEADING_HWFN(cdev); 1059 drv_version.version = (params->drv_major << 24) | 1060 (params->drv_minor << 16) | 1061 (params->drv_rev << 8) | 1062 (params->drv_eng); 1063 strlcpy(drv_version.name, params->name, 1064 MCP_DRV_VER_STR_SIZE - 4); 1065 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 1066 &drv_version); 1067 if (rc) { 1068 DP_NOTICE(cdev, "Failed sending drv version command\n"); 1069 return rc; 1070 } 1071 } 1072 1073 qed_reset_vport_stats(cdev); 1074 1075 return 0; 1076 1077 err3: 1078 qed_hw_stop(cdev); 1079 err2: 1080 qed_hw_timers_stop_all(cdev); 1081 if (IS_PF(cdev)) 1082 qed_slowpath_irq_free(cdev); 1083 qed_free_stream_mem(cdev); 1084 qed_disable_msix(cdev); 1085 err1: 1086 qed_resc_free(cdev); 1087 err: 1088 if (IS_PF(cdev)) 1089 release_firmware(cdev->firmware); 1090 1091 if (IS_PF(cdev) && (cdev->num_hwfns == 1) && 1092 QED_LEADING_HWFN(cdev)->p_arfs_ptt) 1093 qed_ptt_release(QED_LEADING_HWFN(cdev), 1094 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1095 1096 qed_iov_wq_stop(cdev, false); 1097 1098 return rc; 1099 } 1100 1101 static int qed_slowpath_stop(struct qed_dev *cdev) 1102 { 1103 if (!cdev) 1104 return -ENODEV; 1105 1106 qed_ll2_dealloc_if(cdev); 1107 1108 if (IS_PF(cdev)) { 1109 if (cdev->num_hwfns == 1) 1110 qed_ptt_release(QED_LEADING_HWFN(cdev), 1111 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1112 qed_free_stream_mem(cdev); 1113 if (IS_QED_ETH_IF(cdev)) 1114 qed_sriov_disable(cdev, true); 1115 } 1116 1117 qed_nic_stop(cdev); 1118 1119 if (IS_PF(cdev)) 1120 qed_slowpath_irq_free(cdev); 1121 1122 qed_disable_msix(cdev); 1123 1124 qed_resc_free(cdev); 1125 1126 qed_iov_wq_stop(cdev, true); 1127 1128 if (IS_PF(cdev)) 1129 release_firmware(cdev->firmware); 1130 1131 return 0; 1132 } 1133 1134 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE]) 1135 { 1136 int i; 1137 1138 memcpy(cdev->name, name, NAME_SIZE); 1139 for_each_hwfn(cdev, i) 1140 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1141 } 1142 1143 static u32 qed_sb_init(struct qed_dev *cdev, 1144 struct qed_sb_info *sb_info, 1145 void *sb_virt_addr, 1146 dma_addr_t sb_phy_addr, u16 sb_id, 1147 enum qed_sb_type type) 1148 { 1149 struct qed_hwfn *p_hwfn; 1150 struct qed_ptt *p_ptt; 1151 int hwfn_index; 1152 u16 rel_sb_id; 1153 u8 n_hwfns; 1154 u32 rc; 1155 1156 /* RoCE uses single engine and CMT uses two engines. When using both 1157 * we force only a single engine. Storage uses only engine 0 too. 1158 */ 1159 if (type == QED_SB_TYPE_L2_QUEUE) 1160 n_hwfns = cdev->num_hwfns; 1161 else 1162 n_hwfns = 1; 1163 1164 hwfn_index = sb_id % n_hwfns; 1165 p_hwfn = &cdev->hwfns[hwfn_index]; 1166 rel_sb_id = sb_id / n_hwfns; 1167 1168 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1169 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1170 hwfn_index, rel_sb_id, sb_id); 1171 1172 if (IS_PF(p_hwfn->cdev)) { 1173 p_ptt = qed_ptt_acquire(p_hwfn); 1174 if (!p_ptt) 1175 return -EBUSY; 1176 1177 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr, 1178 sb_phy_addr, rel_sb_id); 1179 qed_ptt_release(p_hwfn, p_ptt); 1180 } else { 1181 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr, 1182 sb_phy_addr, rel_sb_id); 1183 } 1184 1185 return rc; 1186 } 1187 1188 static u32 qed_sb_release(struct qed_dev *cdev, 1189 struct qed_sb_info *sb_info, u16 sb_id) 1190 { 1191 struct qed_hwfn *p_hwfn; 1192 int hwfn_index; 1193 u16 rel_sb_id; 1194 u32 rc; 1195 1196 hwfn_index = sb_id % cdev->num_hwfns; 1197 p_hwfn = &cdev->hwfns[hwfn_index]; 1198 rel_sb_id = sb_id / cdev->num_hwfns; 1199 1200 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1201 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1202 hwfn_index, rel_sb_id, sb_id); 1203 1204 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1205 1206 return rc; 1207 } 1208 1209 static bool qed_can_link_change(struct qed_dev *cdev) 1210 { 1211 return true; 1212 } 1213 1214 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1215 { 1216 struct qed_hwfn *hwfn; 1217 struct qed_mcp_link_params *link_params; 1218 struct qed_ptt *ptt; 1219 int rc; 1220 1221 if (!cdev) 1222 return -ENODEV; 1223 1224 /* The link should be set only once per PF */ 1225 hwfn = &cdev->hwfns[0]; 1226 1227 /* When VF wants to set link, force it to read the bulletin instead. 1228 * This mimics the PF behavior, where a noitification [both immediate 1229 * and possible later] would be generated when changing properties. 1230 */ 1231 if (IS_VF(cdev)) { 1232 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG); 1233 return 0; 1234 } 1235 1236 ptt = qed_ptt_acquire(hwfn); 1237 if (!ptt) 1238 return -EBUSY; 1239 1240 link_params = qed_mcp_get_link_params(hwfn); 1241 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1242 link_params->speed.autoneg = params->autoneg; 1243 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1244 link_params->speed.advertised_speeds = 0; 1245 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1246 (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1247 link_params->speed.advertised_speeds |= 1248 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1249 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1250 link_params->speed.advertised_speeds |= 1251 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1252 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1253 link_params->speed.advertised_speeds |= 1254 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1255 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1256 link_params->speed.advertised_speeds |= 1257 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1258 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1259 link_params->speed.advertised_speeds |= 1260 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1261 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1262 link_params->speed.advertised_speeds |= 1263 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1264 } 1265 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1266 link_params->speed.forced_speed = params->forced_speed; 1267 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1268 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1269 link_params->pause.autoneg = true; 1270 else 1271 link_params->pause.autoneg = false; 1272 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1273 link_params->pause.forced_rx = true; 1274 else 1275 link_params->pause.forced_rx = false; 1276 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1277 link_params->pause.forced_tx = true; 1278 else 1279 link_params->pause.forced_tx = false; 1280 } 1281 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1282 switch (params->loopback_mode) { 1283 case QED_LINK_LOOPBACK_INT_PHY: 1284 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1285 break; 1286 case QED_LINK_LOOPBACK_EXT_PHY: 1287 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1288 break; 1289 case QED_LINK_LOOPBACK_EXT: 1290 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1291 break; 1292 case QED_LINK_LOOPBACK_MAC: 1293 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1294 break; 1295 default: 1296 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1297 break; 1298 } 1299 } 1300 1301 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG) 1302 memcpy(&link_params->eee, ¶ms->eee, 1303 sizeof(link_params->eee)); 1304 1305 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1306 1307 qed_ptt_release(hwfn, ptt); 1308 1309 return rc; 1310 } 1311 1312 static int qed_get_port_type(u32 media_type) 1313 { 1314 int port_type; 1315 1316 switch (media_type) { 1317 case MEDIA_SFPP_10G_FIBER: 1318 case MEDIA_SFP_1G_FIBER: 1319 case MEDIA_XFP_FIBER: 1320 case MEDIA_MODULE_FIBER: 1321 case MEDIA_KR: 1322 port_type = PORT_FIBRE; 1323 break; 1324 case MEDIA_DA_TWINAX: 1325 port_type = PORT_DA; 1326 break; 1327 case MEDIA_BASE_T: 1328 port_type = PORT_TP; 1329 break; 1330 case MEDIA_NOT_PRESENT: 1331 port_type = PORT_NONE; 1332 break; 1333 case MEDIA_UNSPECIFIED: 1334 default: 1335 port_type = PORT_OTHER; 1336 break; 1337 } 1338 return port_type; 1339 } 1340 1341 static int qed_get_link_data(struct qed_hwfn *hwfn, 1342 struct qed_mcp_link_params *params, 1343 struct qed_mcp_link_state *link, 1344 struct qed_mcp_link_capabilities *link_caps) 1345 { 1346 void *p; 1347 1348 if (!IS_PF(hwfn->cdev)) { 1349 qed_vf_get_link_params(hwfn, params); 1350 qed_vf_get_link_state(hwfn, link); 1351 qed_vf_get_link_caps(hwfn, link_caps); 1352 1353 return 0; 1354 } 1355 1356 p = qed_mcp_get_link_params(hwfn); 1357 if (!p) 1358 return -ENXIO; 1359 memcpy(params, p, sizeof(*params)); 1360 1361 p = qed_mcp_get_link_state(hwfn); 1362 if (!p) 1363 return -ENXIO; 1364 memcpy(link, p, sizeof(*link)); 1365 1366 p = qed_mcp_get_link_capabilities(hwfn); 1367 if (!p) 1368 return -ENXIO; 1369 memcpy(link_caps, p, sizeof(*link_caps)); 1370 1371 return 0; 1372 } 1373 1374 static void qed_fill_link(struct qed_hwfn *hwfn, 1375 struct qed_link_output *if_link) 1376 { 1377 struct qed_mcp_link_params params; 1378 struct qed_mcp_link_state link; 1379 struct qed_mcp_link_capabilities link_caps; 1380 u32 media_type; 1381 1382 memset(if_link, 0, sizeof(*if_link)); 1383 1384 /* Prepare source inputs */ 1385 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1386 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1387 return; 1388 } 1389 1390 /* Set the link parameters to pass to protocol driver */ 1391 if (link.link_up) 1392 if_link->link_up = true; 1393 1394 /* TODO - at the moment assume supported and advertised speed equal */ 1395 if_link->supported_caps = QED_LM_FIBRE_BIT; 1396 if (link_caps.default_speed_autoneg) 1397 if_link->supported_caps |= QED_LM_Autoneg_BIT; 1398 if (params.pause.autoneg || 1399 (params.pause.forced_rx && params.pause.forced_tx)) 1400 if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1401 if (params.pause.autoneg || params.pause.forced_rx || 1402 params.pause.forced_tx) 1403 if_link->supported_caps |= QED_LM_Pause_BIT; 1404 1405 if_link->advertised_caps = if_link->supported_caps; 1406 if (params.speed.autoneg) 1407 if_link->advertised_caps |= QED_LM_Autoneg_BIT; 1408 else 1409 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT; 1410 if (params.speed.advertised_speeds & 1411 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1412 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1413 QED_LM_1000baseT_Full_BIT; 1414 if (params.speed.advertised_speeds & 1415 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1416 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1417 if (params.speed.advertised_speeds & 1418 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1419 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1420 if (params.speed.advertised_speeds & 1421 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1422 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1423 if (params.speed.advertised_speeds & 1424 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1425 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1426 if (params.speed.advertised_speeds & 1427 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1428 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1429 1430 if (link_caps.speed_capabilities & 1431 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1432 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1433 QED_LM_1000baseT_Full_BIT; 1434 if (link_caps.speed_capabilities & 1435 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1436 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1437 if (link_caps.speed_capabilities & 1438 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1439 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1440 if (link_caps.speed_capabilities & 1441 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1442 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1443 if (link_caps.speed_capabilities & 1444 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1445 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1446 if (link_caps.speed_capabilities & 1447 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1448 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1449 1450 if (link.link_up) 1451 if_link->speed = link.speed; 1452 1453 /* TODO - fill duplex properly */ 1454 if_link->duplex = DUPLEX_FULL; 1455 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1456 if_link->port = qed_get_port_type(media_type); 1457 1458 if_link->autoneg = params.speed.autoneg; 1459 1460 if (params.pause.autoneg) 1461 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1462 if (params.pause.forced_rx) 1463 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1464 if (params.pause.forced_tx) 1465 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1466 1467 /* Link partner capabilities */ 1468 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1469 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1470 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1471 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1472 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1473 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1474 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1475 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1476 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1477 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1478 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1479 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1480 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1481 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1482 1483 if (link.an_complete) 1484 if_link->lp_caps |= QED_LM_Autoneg_BIT; 1485 1486 if (link.partner_adv_pause) 1487 if_link->lp_caps |= QED_LM_Pause_BIT; 1488 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1489 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1490 if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1491 1492 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) { 1493 if_link->eee_supported = false; 1494 } else { 1495 if_link->eee_supported = true; 1496 if_link->eee_active = link.eee_active; 1497 if_link->sup_caps = link_caps.eee_speed_caps; 1498 /* MFW clears adv_caps on eee disable; use configured value */ 1499 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps : 1500 params.eee.adv_caps; 1501 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps; 1502 if_link->eee.enable = params.eee.enable; 1503 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable; 1504 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer; 1505 } 1506 } 1507 1508 static void qed_get_current_link(struct qed_dev *cdev, 1509 struct qed_link_output *if_link) 1510 { 1511 int i; 1512 1513 qed_fill_link(&cdev->hwfns[0], if_link); 1514 1515 for_each_hwfn(cdev, i) 1516 qed_inform_vf_link_state(&cdev->hwfns[i]); 1517 } 1518 1519 void qed_link_update(struct qed_hwfn *hwfn) 1520 { 1521 void *cookie = hwfn->cdev->ops_cookie; 1522 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1523 struct qed_link_output if_link; 1524 1525 qed_fill_link(hwfn, &if_link); 1526 qed_inform_vf_link_state(hwfn); 1527 1528 if (IS_LEAD_HWFN(hwfn) && cookie) 1529 op->link_update(cookie, &if_link); 1530 } 1531 1532 static int qed_drain(struct qed_dev *cdev) 1533 { 1534 struct qed_hwfn *hwfn; 1535 struct qed_ptt *ptt; 1536 int i, rc; 1537 1538 if (IS_VF(cdev)) 1539 return 0; 1540 1541 for_each_hwfn(cdev, i) { 1542 hwfn = &cdev->hwfns[i]; 1543 ptt = qed_ptt_acquire(hwfn); 1544 if (!ptt) { 1545 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1546 return -EBUSY; 1547 } 1548 rc = qed_mcp_drain(hwfn, ptt); 1549 if (rc) 1550 return rc; 1551 qed_ptt_release(hwfn, ptt); 1552 } 1553 1554 return 0; 1555 } 1556 1557 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev, 1558 struct qed_nvm_image_att *nvm_image, 1559 u32 *crc) 1560 { 1561 u8 *buf = NULL; 1562 int rc, j; 1563 u32 val; 1564 1565 /* Allocate a buffer for holding the nvram image */ 1566 buf = kzalloc(nvm_image->length, GFP_KERNEL); 1567 if (!buf) 1568 return -ENOMEM; 1569 1570 /* Read image into buffer */ 1571 rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr, 1572 buf, nvm_image->length); 1573 if (rc) { 1574 DP_ERR(cdev, "Failed reading image from nvm\n"); 1575 goto out; 1576 } 1577 1578 /* Convert the buffer into big-endian format (excluding the 1579 * closing 4 bytes of CRC). 1580 */ 1581 for (j = 0; j < nvm_image->length - 4; j += 4) { 1582 val = cpu_to_be32(*(u32 *)&buf[j]); 1583 *(u32 *)&buf[j] = val; 1584 } 1585 1586 /* Calc CRC for the "actual" image buffer, i.e. not including 1587 * the last 4 CRC bytes. 1588 */ 1589 *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4))); 1590 1591 out: 1592 kfree(buf); 1593 1594 return rc; 1595 } 1596 1597 /* Binary file format - 1598 * /----------------------------------------------------------------------\ 1599 * 0B | 0x4 [command index] | 1600 * 4B | image_type | Options | Number of register settings | 1601 * 8B | Value | 1602 * 12B | Mask | 1603 * 16B | Offset | 1604 * \----------------------------------------------------------------------/ 1605 * There can be several Value-Mask-Offset sets as specified by 'Number of...'. 1606 * Options - 0'b - Calculate & Update CRC for image 1607 */ 1608 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data, 1609 bool *check_resp) 1610 { 1611 struct qed_nvm_image_att nvm_image; 1612 struct qed_hwfn *p_hwfn; 1613 bool is_crc = false; 1614 u32 image_type; 1615 int rc = 0, i; 1616 u16 len; 1617 1618 *data += 4; 1619 image_type = **data; 1620 p_hwfn = QED_LEADING_HWFN(cdev); 1621 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 1622 if (image_type == p_hwfn->nvm_info.image_att[i].image_type) 1623 break; 1624 if (i == p_hwfn->nvm_info.num_images) { 1625 DP_ERR(cdev, "Failed to find nvram image of type %08x\n", 1626 image_type); 1627 return -ENOENT; 1628 } 1629 1630 nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 1631 nvm_image.length = p_hwfn->nvm_info.image_att[i].len; 1632 1633 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1634 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n", 1635 **data, image_type, nvm_image.start_addr, 1636 nvm_image.start_addr + nvm_image.length - 1); 1637 (*data)++; 1638 is_crc = !!(**data & BIT(0)); 1639 (*data)++; 1640 len = *((u16 *)*data); 1641 *data += 2; 1642 if (is_crc) { 1643 u32 crc = 0; 1644 1645 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc); 1646 if (rc) { 1647 DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc); 1648 goto exit; 1649 } 1650 1651 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1652 (nvm_image.start_addr + 1653 nvm_image.length - 4), (u8 *)&crc, 4); 1654 if (rc) 1655 DP_ERR(cdev, "Failed writing to %08x, rc = %d\n", 1656 nvm_image.start_addr + nvm_image.length - 4, rc); 1657 goto exit; 1658 } 1659 1660 /* Iterate over the values for setting */ 1661 while (len) { 1662 u32 offset, mask, value, cur_value; 1663 u8 buf[4]; 1664 1665 value = *((u32 *)*data); 1666 *data += 4; 1667 mask = *((u32 *)*data); 1668 *data += 4; 1669 offset = *((u32 *)*data); 1670 *data += 4; 1671 1672 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf, 1673 4); 1674 if (rc) { 1675 DP_ERR(cdev, "Failed reading from %08x\n", 1676 nvm_image.start_addr + offset); 1677 goto exit; 1678 } 1679 1680 cur_value = le32_to_cpu(*((__le32 *)buf)); 1681 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1682 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n", 1683 nvm_image.start_addr + offset, cur_value, 1684 (cur_value & ~mask) | (value & mask), value, mask); 1685 value = (value & mask) | (cur_value & ~mask); 1686 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1687 nvm_image.start_addr + offset, 1688 (u8 *)&value, 4); 1689 if (rc) { 1690 DP_ERR(cdev, "Failed writing to %08x\n", 1691 nvm_image.start_addr + offset); 1692 goto exit; 1693 } 1694 1695 len--; 1696 } 1697 exit: 1698 return rc; 1699 } 1700 1701 /* Binary file format - 1702 * /----------------------------------------------------------------------\ 1703 * 0B | 0x3 [command index] | 1704 * 4B | b'0: check_response? | b'1-31 reserved | 1705 * 8B | File-type | reserved | 1706 * \----------------------------------------------------------------------/ 1707 * Start a new file of the provided type 1708 */ 1709 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev, 1710 const u8 **data, bool *check_resp) 1711 { 1712 int rc; 1713 1714 *data += 4; 1715 *check_resp = !!(**data & BIT(0)); 1716 *data += 4; 1717 1718 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1719 "About to start a new file of type %02x\n", **data); 1720 rc = qed_mcp_nvm_put_file_begin(cdev, **data); 1721 *data += 4; 1722 1723 return rc; 1724 } 1725 1726 /* Binary file format - 1727 * /----------------------------------------------------------------------\ 1728 * 0B | 0x2 [command index] | 1729 * 4B | Length in bytes | 1730 * 8B | b'0: check_response? | b'1-31 reserved | 1731 * 12B | Offset in bytes | 1732 * 16B | Data ... | 1733 * \----------------------------------------------------------------------/ 1734 * Write data as part of a file that was previously started. Data should be 1735 * of length equal to that provided in the message 1736 */ 1737 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev, 1738 const u8 **data, bool *check_resp) 1739 { 1740 u32 offset, len; 1741 int rc; 1742 1743 *data += 4; 1744 len = *((u32 *)(*data)); 1745 *data += 4; 1746 *check_resp = !!(**data & BIT(0)); 1747 *data += 4; 1748 offset = *((u32 *)(*data)); 1749 *data += 4; 1750 1751 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1752 "About to write File-data: %08x bytes to offset %08x\n", 1753 len, offset); 1754 1755 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset, 1756 (char *)(*data), len); 1757 *data += len; 1758 1759 return rc; 1760 } 1761 1762 /* Binary file format [General header] - 1763 * /----------------------------------------------------------------------\ 1764 * 0B | QED_NVM_SIGNATURE | 1765 * 4B | Length in bytes | 1766 * 8B | Highest command in this batchfile | Reserved | 1767 * \----------------------------------------------------------------------/ 1768 */ 1769 static int qed_nvm_flash_image_validate(struct qed_dev *cdev, 1770 const struct firmware *image, 1771 const u8 **data) 1772 { 1773 u32 signature, len; 1774 1775 /* Check minimum size */ 1776 if (image->size < 12) { 1777 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size); 1778 return -EINVAL; 1779 } 1780 1781 /* Check signature */ 1782 signature = *((u32 *)(*data)); 1783 if (signature != QED_NVM_SIGNATURE) { 1784 DP_ERR(cdev, "Wrong signature '%08x'\n", signature); 1785 return -EINVAL; 1786 } 1787 1788 *data += 4; 1789 /* Validate internal size equals the image-size */ 1790 len = *((u32 *)(*data)); 1791 if (len != image->size) { 1792 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n", 1793 len, (u32)image->size); 1794 return -EINVAL; 1795 } 1796 1797 *data += 4; 1798 /* Make sure driver familiar with all commands necessary for this */ 1799 if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) { 1800 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n", 1801 *((u16 *)(*data))); 1802 return -EINVAL; 1803 } 1804 1805 *data += 4; 1806 1807 return 0; 1808 } 1809 1810 static int qed_nvm_flash(struct qed_dev *cdev, const char *name) 1811 { 1812 const struct firmware *image; 1813 const u8 *data, *data_end; 1814 u32 cmd_type; 1815 int rc; 1816 1817 rc = request_firmware(&image, name, &cdev->pdev->dev); 1818 if (rc) { 1819 DP_ERR(cdev, "Failed to find '%s'\n", name); 1820 return rc; 1821 } 1822 1823 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1824 "Flashing '%s' - firmware's data at %p, size is %08x\n", 1825 name, image->data, (u32)image->size); 1826 data = image->data; 1827 data_end = data + image->size; 1828 1829 rc = qed_nvm_flash_image_validate(cdev, image, &data); 1830 if (rc) 1831 goto exit; 1832 1833 while (data < data_end) { 1834 bool check_resp = false; 1835 1836 /* Parse the actual command */ 1837 cmd_type = *((u32 *)data); 1838 switch (cmd_type) { 1839 case QED_NVM_FLASH_CMD_FILE_DATA: 1840 rc = qed_nvm_flash_image_file_data(cdev, &data, 1841 &check_resp); 1842 break; 1843 case QED_NVM_FLASH_CMD_FILE_START: 1844 rc = qed_nvm_flash_image_file_start(cdev, &data, 1845 &check_resp); 1846 break; 1847 case QED_NVM_FLASH_CMD_NVM_CHANGE: 1848 rc = qed_nvm_flash_image_access(cdev, &data, 1849 &check_resp); 1850 break; 1851 default: 1852 DP_ERR(cdev, "Unknown command %08x\n", cmd_type); 1853 rc = -EINVAL; 1854 goto exit; 1855 } 1856 1857 if (rc) { 1858 DP_ERR(cdev, "Command %08x failed\n", cmd_type); 1859 goto exit; 1860 } 1861 1862 /* Check response if needed */ 1863 if (check_resp) { 1864 u32 mcp_response = 0; 1865 1866 if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) { 1867 DP_ERR(cdev, "Failed getting MCP response\n"); 1868 rc = -EINVAL; 1869 goto exit; 1870 } 1871 1872 switch (mcp_response & FW_MSG_CODE_MASK) { 1873 case FW_MSG_CODE_OK: 1874 case FW_MSG_CODE_NVM_OK: 1875 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK: 1876 case FW_MSG_CODE_PHY_OK: 1877 break; 1878 default: 1879 DP_ERR(cdev, "MFW returns error: %08x\n", 1880 mcp_response); 1881 rc = -EINVAL; 1882 goto exit; 1883 } 1884 } 1885 } 1886 1887 exit: 1888 release_firmware(image); 1889 1890 return rc; 1891 } 1892 1893 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, 1894 u8 *buf, u16 len) 1895 { 1896 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1897 struct qed_ptt *ptt = qed_ptt_acquire(hwfn); 1898 int rc; 1899 1900 if (!ptt) 1901 return -EAGAIN; 1902 1903 rc = qed_mcp_get_nvm_image(hwfn, ptt, type, buf, len); 1904 qed_ptt_release(hwfn, ptt); 1905 return rc; 1906 } 1907 1908 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1909 void *handle) 1910 { 1911 return qed_set_queue_coalesce(rx_coal, tx_coal, handle); 1912 } 1913 1914 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1915 { 1916 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1917 struct qed_ptt *ptt; 1918 int status = 0; 1919 1920 ptt = qed_ptt_acquire(hwfn); 1921 if (!ptt) 1922 return -EAGAIN; 1923 1924 status = qed_mcp_set_led(hwfn, ptt, mode); 1925 1926 qed_ptt_release(hwfn, ptt); 1927 1928 return status; 1929 } 1930 1931 static int qed_update_wol(struct qed_dev *cdev, bool enabled) 1932 { 1933 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1934 struct qed_ptt *ptt; 1935 int rc = 0; 1936 1937 if (IS_VF(cdev)) 1938 return 0; 1939 1940 ptt = qed_ptt_acquire(hwfn); 1941 if (!ptt) 1942 return -EAGAIN; 1943 1944 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED 1945 : QED_OV_WOL_DISABLED); 1946 if (rc) 1947 goto out; 1948 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 1949 1950 out: 1951 qed_ptt_release(hwfn, ptt); 1952 return rc; 1953 } 1954 1955 static int qed_update_drv_state(struct qed_dev *cdev, bool active) 1956 { 1957 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1958 struct qed_ptt *ptt; 1959 int status = 0; 1960 1961 if (IS_VF(cdev)) 1962 return 0; 1963 1964 ptt = qed_ptt_acquire(hwfn); 1965 if (!ptt) 1966 return -EAGAIN; 1967 1968 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ? 1969 QED_OV_DRIVER_STATE_ACTIVE : 1970 QED_OV_DRIVER_STATE_DISABLED); 1971 1972 qed_ptt_release(hwfn, ptt); 1973 1974 return status; 1975 } 1976 1977 static int qed_update_mac(struct qed_dev *cdev, u8 *mac) 1978 { 1979 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1980 struct qed_ptt *ptt; 1981 int status = 0; 1982 1983 if (IS_VF(cdev)) 1984 return 0; 1985 1986 ptt = qed_ptt_acquire(hwfn); 1987 if (!ptt) 1988 return -EAGAIN; 1989 1990 status = qed_mcp_ov_update_mac(hwfn, ptt, mac); 1991 if (status) 1992 goto out; 1993 1994 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 1995 1996 out: 1997 qed_ptt_release(hwfn, ptt); 1998 return status; 1999 } 2000 2001 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) 2002 { 2003 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2004 struct qed_ptt *ptt; 2005 int status = 0; 2006 2007 if (IS_VF(cdev)) 2008 return 0; 2009 2010 ptt = qed_ptt_acquire(hwfn); 2011 if (!ptt) 2012 return -EAGAIN; 2013 2014 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu); 2015 if (status) 2016 goto out; 2017 2018 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2019 2020 out: 2021 qed_ptt_release(hwfn, ptt); 2022 return status; 2023 } 2024 2025 static struct qed_selftest_ops qed_selftest_ops_pass = { 2026 .selftest_memory = &qed_selftest_memory, 2027 .selftest_interrupt = &qed_selftest_interrupt, 2028 .selftest_register = &qed_selftest_register, 2029 .selftest_clock = &qed_selftest_clock, 2030 .selftest_nvram = &qed_selftest_nvram, 2031 }; 2032 2033 const struct qed_common_ops qed_common_ops_pass = { 2034 .selftest = &qed_selftest_ops_pass, 2035 .probe = &qed_probe, 2036 .remove = &qed_remove, 2037 .set_power_state = &qed_set_power_state, 2038 .set_name = &qed_set_name, 2039 .update_pf_params = &qed_update_pf_params, 2040 .slowpath_start = &qed_slowpath_start, 2041 .slowpath_stop = &qed_slowpath_stop, 2042 .set_fp_int = &qed_set_int_fp, 2043 .get_fp_int = &qed_get_int_fp, 2044 .sb_init = &qed_sb_init, 2045 .sb_release = &qed_sb_release, 2046 .simd_handler_config = &qed_simd_handler_config, 2047 .simd_handler_clean = &qed_simd_handler_clean, 2048 .dbg_grc = &qed_dbg_grc, 2049 .dbg_grc_size = &qed_dbg_grc_size, 2050 .can_link_change = &qed_can_link_change, 2051 .set_link = &qed_set_link, 2052 .get_link = &qed_get_current_link, 2053 .drain = &qed_drain, 2054 .update_msglvl = &qed_init_dp, 2055 .dbg_all_data = &qed_dbg_all_data, 2056 .dbg_all_data_size = &qed_dbg_all_data_size, 2057 .chain_alloc = &qed_chain_alloc, 2058 .chain_free = &qed_chain_free, 2059 .nvm_flash = &qed_nvm_flash, 2060 .nvm_get_image = &qed_nvm_get_image, 2061 .set_coalesce = &qed_set_coalesce, 2062 .set_led = &qed_set_led, 2063 .update_drv_state = &qed_update_drv_state, 2064 .update_mac = &qed_update_mac, 2065 .update_mtu = &qed_update_mtu, 2066 .update_wol = &qed_update_wol, 2067 }; 2068 2069 void qed_get_protocol_stats(struct qed_dev *cdev, 2070 enum qed_mcp_protocol_type type, 2071 union qed_mcp_protocol_stats *stats) 2072 { 2073 struct qed_eth_stats eth_stats; 2074 2075 memset(stats, 0, sizeof(*stats)); 2076 2077 switch (type) { 2078 case QED_MCP_LAN_STATS: 2079 qed_get_vport_stats(cdev, ð_stats); 2080 stats->lan_stats.ucast_rx_pkts = 2081 eth_stats.common.rx_ucast_pkts; 2082 stats->lan_stats.ucast_tx_pkts = 2083 eth_stats.common.tx_ucast_pkts; 2084 stats->lan_stats.fcs_err = -1; 2085 break; 2086 case QED_MCP_FCOE_STATS: 2087 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats); 2088 break; 2089 case QED_MCP_ISCSI_STATS: 2090 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats); 2091 break; 2092 default: 2093 DP_VERBOSE(cdev, QED_MSG_SP, 2094 "Invalid protocol type = %d\n", type); 2095 return; 2096 } 2097 } 2098