1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/stddef.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/version.h> 14 #include <linux/delay.h> 15 #include <asm/byteorder.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/string.h> 18 #include <linux/module.h> 19 #include <linux/interrupt.h> 20 #include <linux/workqueue.h> 21 #include <linux/ethtool.h> 22 #include <linux/etherdevice.h> 23 #include <linux/vmalloc.h> 24 #include <linux/qed/qed_if.h> 25 #include <linux/qed/qed_ll2_if.h> 26 27 #include "qed.h" 28 #include "qed_sriov.h" 29 #include "qed_sp.h" 30 #include "qed_dev_api.h" 31 #include "qed_ll2.h" 32 #include "qed_mcp.h" 33 #include "qed_hw.h" 34 #include "qed_selftest.h" 35 36 #define QED_ROCE_QPS (8192) 37 #define QED_ROCE_DPIS (8) 38 39 static char version[] = 40 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 41 42 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 43 MODULE_LICENSE("GPL"); 44 MODULE_VERSION(DRV_MODULE_VERSION); 45 46 #define FW_FILE_VERSION \ 47 __stringify(FW_MAJOR_VERSION) "." \ 48 __stringify(FW_MINOR_VERSION) "." \ 49 __stringify(FW_REVISION_VERSION) "." \ 50 __stringify(FW_ENGINEERING_VERSION) 51 52 #define QED_FW_FILE_NAME \ 53 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 54 55 MODULE_FIRMWARE(QED_FW_FILE_NAME); 56 57 static int __init qed_init(void) 58 { 59 pr_info("%s", version); 60 61 return 0; 62 } 63 64 static void __exit qed_cleanup(void) 65 { 66 pr_notice("qed_cleanup called\n"); 67 } 68 69 module_init(qed_init); 70 module_exit(qed_cleanup); 71 72 /* Check if the DMA controller on the machine can properly handle the DMA 73 * addressing required by the device. 74 */ 75 static int qed_set_coherency_mask(struct qed_dev *cdev) 76 { 77 struct device *dev = &cdev->pdev->dev; 78 79 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 80 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 81 DP_NOTICE(cdev, 82 "Can't request 64-bit consistent allocations\n"); 83 return -EIO; 84 } 85 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 86 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 87 return -EIO; 88 } 89 90 return 0; 91 } 92 93 static void qed_free_pci(struct qed_dev *cdev) 94 { 95 struct pci_dev *pdev = cdev->pdev; 96 97 if (cdev->doorbells) 98 iounmap(cdev->doorbells); 99 if (cdev->regview) 100 iounmap(cdev->regview); 101 if (atomic_read(&pdev->enable_cnt) == 1) 102 pci_release_regions(pdev); 103 104 pci_disable_device(pdev); 105 } 106 107 #define PCI_REVISION_ID_ERROR_VAL 0xff 108 109 /* Performs PCI initializations as well as initializing PCI-related parameters 110 * in the device structrue. Returns 0 in case of success. 111 */ 112 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 113 { 114 u8 rev_id; 115 int rc; 116 117 cdev->pdev = pdev; 118 119 rc = pci_enable_device(pdev); 120 if (rc) { 121 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 122 goto err0; 123 } 124 125 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 126 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 127 rc = -EIO; 128 goto err1; 129 } 130 131 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 132 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 133 rc = -EIO; 134 goto err1; 135 } 136 137 if (atomic_read(&pdev->enable_cnt) == 1) { 138 rc = pci_request_regions(pdev, "qed"); 139 if (rc) { 140 DP_NOTICE(cdev, 141 "Failed to request PCI memory resources\n"); 142 goto err1; 143 } 144 pci_set_master(pdev); 145 pci_save_state(pdev); 146 } 147 148 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 149 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 150 DP_NOTICE(cdev, 151 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 152 rev_id); 153 rc = -ENODEV; 154 goto err2; 155 } 156 if (!pci_is_pcie(pdev)) { 157 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 158 rc = -EIO; 159 goto err2; 160 } 161 162 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 163 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 164 DP_NOTICE(cdev, "Cannot find power management capability\n"); 165 166 rc = qed_set_coherency_mask(cdev); 167 if (rc) 168 goto err2; 169 170 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 171 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 172 cdev->pci_params.irq = pdev->irq; 173 174 cdev->regview = pci_ioremap_bar(pdev, 0); 175 if (!cdev->regview) { 176 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 177 rc = -ENOMEM; 178 goto err2; 179 } 180 181 if (IS_PF(cdev)) { 182 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 183 cdev->db_size = pci_resource_len(cdev->pdev, 2); 184 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 185 if (!cdev->doorbells) { 186 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 187 return -ENOMEM; 188 } 189 } 190 191 return 0; 192 193 err2: 194 pci_release_regions(pdev); 195 err1: 196 pci_disable_device(pdev); 197 err0: 198 return rc; 199 } 200 201 int qed_fill_dev_info(struct qed_dev *cdev, 202 struct qed_dev_info *dev_info) 203 { 204 struct qed_ptt *ptt; 205 206 memset(dev_info, 0, sizeof(struct qed_dev_info)); 207 208 dev_info->num_hwfns = cdev->num_hwfns; 209 dev_info->pci_mem_start = cdev->pci_params.mem_start; 210 dev_info->pci_mem_end = cdev->pci_params.mem_end; 211 dev_info->pci_irq = cdev->pci_params.irq; 212 dev_info->rdma_supported = (cdev->hwfns[0].hw_info.personality == 213 QED_PCI_ETH_ROCE); 214 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]); 215 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr); 216 217 if (IS_PF(cdev)) { 218 dev_info->fw_major = FW_MAJOR_VERSION; 219 dev_info->fw_minor = FW_MINOR_VERSION; 220 dev_info->fw_rev = FW_REVISION_VERSION; 221 dev_info->fw_eng = FW_ENGINEERING_VERSION; 222 dev_info->mf_mode = cdev->mf_mode; 223 dev_info->tx_switching = true; 224 } else { 225 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 226 &dev_info->fw_minor, &dev_info->fw_rev, 227 &dev_info->fw_eng); 228 } 229 230 if (IS_PF(cdev)) { 231 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 232 if (ptt) { 233 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 234 &dev_info->mfw_rev, NULL); 235 236 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 237 &dev_info->flash_size); 238 239 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 240 } 241 } else { 242 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 243 &dev_info->mfw_rev, NULL); 244 } 245 246 return 0; 247 } 248 249 static void qed_free_cdev(struct qed_dev *cdev) 250 { 251 kfree((void *)cdev); 252 } 253 254 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 255 { 256 struct qed_dev *cdev; 257 258 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 259 if (!cdev) 260 return cdev; 261 262 qed_init_struct(cdev); 263 264 return cdev; 265 } 266 267 /* Sets the requested power state */ 268 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 269 { 270 if (!cdev) 271 return -ENODEV; 272 273 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 274 return 0; 275 } 276 277 /* probing */ 278 static struct qed_dev *qed_probe(struct pci_dev *pdev, 279 struct qed_probe_params *params) 280 { 281 struct qed_dev *cdev; 282 int rc; 283 284 cdev = qed_alloc_cdev(pdev); 285 if (!cdev) 286 goto err0; 287 288 cdev->protocol = params->protocol; 289 290 if (params->is_vf) 291 cdev->b_is_vf = true; 292 293 qed_init_dp(cdev, params->dp_module, params->dp_level); 294 295 rc = qed_init_pci(cdev, pdev); 296 if (rc) { 297 DP_ERR(cdev, "init pci failed\n"); 298 goto err1; 299 } 300 DP_INFO(cdev, "PCI init completed successfully\n"); 301 302 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 303 if (rc) { 304 DP_ERR(cdev, "hw prepare failed\n"); 305 goto err2; 306 } 307 308 DP_INFO(cdev, "qed_probe completed successffuly\n"); 309 310 return cdev; 311 312 err2: 313 qed_free_pci(cdev); 314 err1: 315 qed_free_cdev(cdev); 316 err0: 317 return NULL; 318 } 319 320 static void qed_remove(struct qed_dev *cdev) 321 { 322 if (!cdev) 323 return; 324 325 qed_hw_remove(cdev); 326 327 qed_free_pci(cdev); 328 329 qed_set_power_state(cdev, PCI_D3hot); 330 331 qed_free_cdev(cdev); 332 } 333 334 static void qed_disable_msix(struct qed_dev *cdev) 335 { 336 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 337 pci_disable_msix(cdev->pdev); 338 kfree(cdev->int_params.msix_table); 339 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 340 pci_disable_msi(cdev->pdev); 341 } 342 343 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 344 } 345 346 static int qed_enable_msix(struct qed_dev *cdev, 347 struct qed_int_params *int_params) 348 { 349 int i, rc, cnt; 350 351 cnt = int_params->in.num_vectors; 352 353 for (i = 0; i < cnt; i++) 354 int_params->msix_table[i].entry = i; 355 356 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 357 int_params->in.min_msix_cnt, cnt); 358 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 359 (rc % cdev->num_hwfns)) { 360 pci_disable_msix(cdev->pdev); 361 362 /* If fastpath is initialized, we need at least one interrupt 363 * per hwfn [and the slow path interrupts]. New requested number 364 * should be a multiple of the number of hwfns. 365 */ 366 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 367 DP_NOTICE(cdev, 368 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 369 cnt, int_params->in.num_vectors); 370 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 371 cnt); 372 if (!rc) 373 rc = cnt; 374 } 375 376 if (rc > 0) { 377 /* MSI-x configuration was achieved */ 378 int_params->out.int_mode = QED_INT_MODE_MSIX; 379 int_params->out.num_vectors = rc; 380 rc = 0; 381 } else { 382 DP_NOTICE(cdev, 383 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 384 cnt, rc); 385 } 386 387 return rc; 388 } 389 390 /* This function outputs the int mode and the number of enabled msix vector */ 391 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 392 { 393 struct qed_int_params *int_params = &cdev->int_params; 394 struct msix_entry *tbl; 395 int rc = 0, cnt; 396 397 switch (int_params->in.int_mode) { 398 case QED_INT_MODE_MSIX: 399 /* Allocate MSIX table */ 400 cnt = int_params->in.num_vectors; 401 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 402 if (!int_params->msix_table) { 403 rc = -ENOMEM; 404 goto out; 405 } 406 407 /* Enable MSIX */ 408 rc = qed_enable_msix(cdev, int_params); 409 if (!rc) 410 goto out; 411 412 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 413 kfree(int_params->msix_table); 414 if (force_mode) 415 goto out; 416 /* Fallthrough */ 417 418 case QED_INT_MODE_MSI: 419 if (cdev->num_hwfns == 1) { 420 rc = pci_enable_msi(cdev->pdev); 421 if (!rc) { 422 int_params->out.int_mode = QED_INT_MODE_MSI; 423 goto out; 424 } 425 426 DP_NOTICE(cdev, "Failed to enable MSI\n"); 427 if (force_mode) 428 goto out; 429 } 430 /* Fallthrough */ 431 432 case QED_INT_MODE_INTA: 433 int_params->out.int_mode = QED_INT_MODE_INTA; 434 rc = 0; 435 goto out; 436 default: 437 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 438 int_params->in.int_mode); 439 rc = -EINVAL; 440 } 441 442 out: 443 if (!rc) 444 DP_INFO(cdev, "Using %s interrupts\n", 445 int_params->out.int_mode == QED_INT_MODE_INTA ? 446 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 447 "MSI" : "MSIX"); 448 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 449 450 return rc; 451 } 452 453 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 454 int index, void(*handler)(void *)) 455 { 456 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 457 int relative_idx = index / cdev->num_hwfns; 458 459 hwfn->simd_proto_handler[relative_idx].func = handler; 460 hwfn->simd_proto_handler[relative_idx].token = token; 461 } 462 463 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 464 { 465 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 466 int relative_idx = index / cdev->num_hwfns; 467 468 memset(&hwfn->simd_proto_handler[relative_idx], 0, 469 sizeof(struct qed_simd_fp_handler)); 470 } 471 472 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 473 { 474 tasklet_schedule((struct tasklet_struct *)tasklet); 475 return IRQ_HANDLED; 476 } 477 478 static irqreturn_t qed_single_int(int irq, void *dev_instance) 479 { 480 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 481 struct qed_hwfn *hwfn; 482 irqreturn_t rc = IRQ_NONE; 483 u64 status; 484 int i, j; 485 486 for (i = 0; i < cdev->num_hwfns; i++) { 487 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 488 489 if (!status) 490 continue; 491 492 hwfn = &cdev->hwfns[i]; 493 494 /* Slowpath interrupt */ 495 if (unlikely(status & 0x1)) { 496 tasklet_schedule(hwfn->sp_dpc); 497 status &= ~0x1; 498 rc = IRQ_HANDLED; 499 } 500 501 /* Fastpath interrupts */ 502 for (j = 0; j < 64; j++) { 503 if ((0x2ULL << j) & status) { 504 hwfn->simd_proto_handler[j].func( 505 hwfn->simd_proto_handler[j].token); 506 status &= ~(0x2ULL << j); 507 rc = IRQ_HANDLED; 508 } 509 } 510 511 if (unlikely(status)) 512 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 513 "got an unknown interrupt status 0x%llx\n", 514 status); 515 } 516 517 return rc; 518 } 519 520 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 521 { 522 struct qed_dev *cdev = hwfn->cdev; 523 u32 int_mode; 524 int rc = 0; 525 u8 id; 526 527 int_mode = cdev->int_params.out.int_mode; 528 if (int_mode == QED_INT_MODE_MSIX) { 529 id = hwfn->my_id; 530 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 531 id, cdev->pdev->bus->number, 532 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 533 rc = request_irq(cdev->int_params.msix_table[id].vector, 534 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 535 } else { 536 unsigned long flags = 0; 537 538 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 539 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 540 PCI_FUNC(cdev->pdev->devfn)); 541 542 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 543 flags |= IRQF_SHARED; 544 545 rc = request_irq(cdev->pdev->irq, qed_single_int, 546 flags, cdev->name, cdev); 547 } 548 549 if (rc) 550 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 551 else 552 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 553 "Requested slowpath %s\n", 554 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 555 556 return rc; 557 } 558 559 static void qed_slowpath_irq_free(struct qed_dev *cdev) 560 { 561 int i; 562 563 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 564 for_each_hwfn(cdev, i) { 565 if (!cdev->hwfns[i].b_int_requested) 566 break; 567 synchronize_irq(cdev->int_params.msix_table[i].vector); 568 free_irq(cdev->int_params.msix_table[i].vector, 569 cdev->hwfns[i].sp_dpc); 570 } 571 } else { 572 if (QED_LEADING_HWFN(cdev)->b_int_requested) 573 free_irq(cdev->pdev->irq, cdev); 574 } 575 qed_int_disable_post_isr_release(cdev); 576 } 577 578 static int qed_nic_stop(struct qed_dev *cdev) 579 { 580 int i, rc; 581 582 rc = qed_hw_stop(cdev); 583 584 for (i = 0; i < cdev->num_hwfns; i++) { 585 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 586 587 if (p_hwfn->b_sp_dpc_enabled) { 588 tasklet_disable(p_hwfn->sp_dpc); 589 p_hwfn->b_sp_dpc_enabled = false; 590 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 591 "Disabled sp taskelt [hwfn %d] at %p\n", 592 i, p_hwfn->sp_dpc); 593 } 594 } 595 596 qed_dbg_pf_exit(cdev); 597 598 return rc; 599 } 600 601 static int qed_nic_reset(struct qed_dev *cdev) 602 { 603 int rc; 604 605 rc = qed_hw_reset(cdev); 606 if (rc) 607 return rc; 608 609 qed_resc_free(cdev); 610 611 return 0; 612 } 613 614 static int qed_nic_setup(struct qed_dev *cdev) 615 { 616 int rc, i; 617 618 /* Determine if interface is going to require LL2 */ 619 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 620 for (i = 0; i < cdev->num_hwfns; i++) { 621 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 622 623 p_hwfn->using_ll2 = true; 624 } 625 } 626 627 rc = qed_resc_alloc(cdev); 628 if (rc) 629 return rc; 630 631 DP_INFO(cdev, "Allocated qed resources\n"); 632 633 qed_resc_setup(cdev); 634 635 return rc; 636 } 637 638 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 639 { 640 int limit = 0; 641 642 /* Mark the fastpath as free/used */ 643 cdev->int_params.fp_initialized = cnt ? true : false; 644 645 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 646 limit = cdev->num_hwfns * 63; 647 else if (cdev->int_params.fp_msix_cnt) 648 limit = cdev->int_params.fp_msix_cnt; 649 650 if (!limit) 651 return -ENOMEM; 652 653 return min_t(int, cnt, limit); 654 } 655 656 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 657 { 658 memset(info, 0, sizeof(struct qed_int_info)); 659 660 if (!cdev->int_params.fp_initialized) { 661 DP_INFO(cdev, 662 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 663 return -EINVAL; 664 } 665 666 /* Need to expose only MSI-X information; Single IRQ is handled solely 667 * by qed. 668 */ 669 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 670 int msix_base = cdev->int_params.fp_msix_base; 671 672 info->msix_cnt = cdev->int_params.fp_msix_cnt; 673 info->msix = &cdev->int_params.msix_table[msix_base]; 674 } 675 676 return 0; 677 } 678 679 static int qed_slowpath_setup_int(struct qed_dev *cdev, 680 enum qed_int_mode int_mode) 681 { 682 struct qed_sb_cnt_info sb_cnt_info; 683 int num_l2_queues = 0; 684 int rc; 685 int i; 686 687 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 688 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 689 return -EINVAL; 690 } 691 692 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 693 cdev->int_params.in.int_mode = int_mode; 694 for_each_hwfn(cdev, i) { 695 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 696 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 697 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt; 698 cdev->int_params.in.num_vectors++; /* slowpath */ 699 } 700 701 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 702 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 703 704 rc = qed_set_int_mode(cdev, false); 705 if (rc) { 706 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 707 return rc; 708 } 709 710 cdev->int_params.fp_msix_base = cdev->num_hwfns; 711 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 712 cdev->num_hwfns; 713 714 if (!IS_ENABLED(CONFIG_QED_RDMA)) 715 return 0; 716 717 for_each_hwfn(cdev, i) 718 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 719 720 DP_VERBOSE(cdev, QED_MSG_RDMA, 721 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 722 cdev->int_params.fp_msix_cnt, num_l2_queues); 723 724 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 725 cdev->int_params.rdma_msix_cnt = 726 (cdev->int_params.fp_msix_cnt - num_l2_queues) 727 / cdev->num_hwfns; 728 cdev->int_params.rdma_msix_base = 729 cdev->int_params.fp_msix_base + num_l2_queues; 730 cdev->int_params.fp_msix_cnt = num_l2_queues; 731 } else { 732 cdev->int_params.rdma_msix_cnt = 0; 733 } 734 735 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 736 cdev->int_params.rdma_msix_cnt, 737 cdev->int_params.rdma_msix_base); 738 739 return 0; 740 } 741 742 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 743 { 744 int rc; 745 746 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 747 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 748 749 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 750 &cdev->int_params.in.num_vectors); 751 if (cdev->num_hwfns > 1) { 752 u8 vectors = 0; 753 754 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 755 cdev->int_params.in.num_vectors += vectors; 756 } 757 758 /* We want a minimum of one fastpath vector per vf hwfn */ 759 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 760 761 rc = qed_set_int_mode(cdev, true); 762 if (rc) 763 return rc; 764 765 cdev->int_params.fp_msix_base = 0; 766 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 767 768 return 0; 769 } 770 771 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 772 u8 *input_buf, u32 max_size, u8 *unzip_buf) 773 { 774 int rc; 775 776 p_hwfn->stream->next_in = input_buf; 777 p_hwfn->stream->avail_in = input_len; 778 p_hwfn->stream->next_out = unzip_buf; 779 p_hwfn->stream->avail_out = max_size; 780 781 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 782 783 if (rc != Z_OK) { 784 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 785 rc); 786 return 0; 787 } 788 789 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 790 zlib_inflateEnd(p_hwfn->stream); 791 792 if (rc != Z_OK && rc != Z_STREAM_END) { 793 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 794 p_hwfn->stream->msg, rc); 795 return 0; 796 } 797 798 return p_hwfn->stream->total_out / 4; 799 } 800 801 static int qed_alloc_stream_mem(struct qed_dev *cdev) 802 { 803 int i; 804 void *workspace; 805 806 for_each_hwfn(cdev, i) { 807 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 808 809 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 810 if (!p_hwfn->stream) 811 return -ENOMEM; 812 813 workspace = vzalloc(zlib_inflate_workspacesize()); 814 if (!workspace) 815 return -ENOMEM; 816 p_hwfn->stream->workspace = workspace; 817 } 818 819 return 0; 820 } 821 822 static void qed_free_stream_mem(struct qed_dev *cdev) 823 { 824 int i; 825 826 for_each_hwfn(cdev, i) { 827 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 828 829 if (!p_hwfn->stream) 830 return; 831 832 vfree(p_hwfn->stream->workspace); 833 kfree(p_hwfn->stream); 834 } 835 } 836 837 static void qed_update_pf_params(struct qed_dev *cdev, 838 struct qed_pf_params *params) 839 { 840 int i; 841 842 for (i = 0; i < cdev->num_hwfns; i++) { 843 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 844 845 p_hwfn->pf_params = *params; 846 } 847 848 if (!IS_ENABLED(CONFIG_QED_RDMA)) 849 return; 850 851 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 852 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 853 /* divide by 3 the MRs to avoid MF ILT overflow */ 854 params->rdma_pf_params.num_mrs = RDMA_MAX_TIDS; 855 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 856 } 857 858 static int qed_slowpath_start(struct qed_dev *cdev, 859 struct qed_slowpath_params *params) 860 { 861 struct qed_tunn_start_params tunn_info; 862 struct qed_mcp_drv_version drv_version; 863 const u8 *data = NULL; 864 struct qed_hwfn *hwfn; 865 int rc = -EINVAL; 866 867 if (qed_iov_wq_start(cdev)) 868 goto err; 869 870 if (IS_PF(cdev)) { 871 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 872 &cdev->pdev->dev); 873 if (rc) { 874 DP_NOTICE(cdev, 875 "Failed to find fw file - /lib/firmware/%s\n", 876 QED_FW_FILE_NAME); 877 goto err; 878 } 879 } 880 881 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; 882 rc = qed_nic_setup(cdev); 883 if (rc) 884 goto err; 885 886 if (IS_PF(cdev)) 887 rc = qed_slowpath_setup_int(cdev, params->int_mode); 888 else 889 rc = qed_slowpath_vf_setup_int(cdev); 890 if (rc) 891 goto err1; 892 893 if (IS_PF(cdev)) { 894 /* Allocate stream for unzipping */ 895 rc = qed_alloc_stream_mem(cdev); 896 if (rc) 897 goto err2; 898 899 /* First Dword used to diffrentiate between various sources */ 900 data = cdev->firmware->data + sizeof(u32); 901 902 qed_dbg_pf_init(cdev); 903 } 904 905 memset(&tunn_info, 0, sizeof(tunn_info)); 906 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN | 907 1 << QED_MODE_L2GRE_TUNN | 908 1 << QED_MODE_IPGRE_TUNN | 909 1 << QED_MODE_L2GENEVE_TUNN | 910 1 << QED_MODE_IPGENEVE_TUNN; 911 912 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN; 913 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN; 914 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN; 915 916 /* Start the slowpath */ 917 rc = qed_hw_init(cdev, &tunn_info, true, 918 cdev->int_params.out.int_mode, 919 true, data); 920 if (rc) 921 goto err2; 922 923 DP_INFO(cdev, 924 "HW initialization and function start completed successfully\n"); 925 926 /* Allocate LL2 interface if needed */ 927 if (QED_LEADING_HWFN(cdev)->using_ll2) { 928 rc = qed_ll2_alloc_if(cdev); 929 if (rc) 930 goto err3; 931 } 932 if (IS_PF(cdev)) { 933 hwfn = QED_LEADING_HWFN(cdev); 934 drv_version.version = (params->drv_major << 24) | 935 (params->drv_minor << 16) | 936 (params->drv_rev << 8) | 937 (params->drv_eng); 938 strlcpy(drv_version.name, params->name, 939 MCP_DRV_VER_STR_SIZE - 4); 940 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 941 &drv_version); 942 if (rc) { 943 DP_NOTICE(cdev, "Failed sending drv version command\n"); 944 return rc; 945 } 946 } 947 948 qed_reset_vport_stats(cdev); 949 950 return 0; 951 952 err3: 953 qed_hw_stop(cdev); 954 err2: 955 qed_hw_timers_stop_all(cdev); 956 if (IS_PF(cdev)) 957 qed_slowpath_irq_free(cdev); 958 qed_free_stream_mem(cdev); 959 qed_disable_msix(cdev); 960 err1: 961 qed_resc_free(cdev); 962 err: 963 if (IS_PF(cdev)) 964 release_firmware(cdev->firmware); 965 966 qed_iov_wq_stop(cdev, false); 967 968 return rc; 969 } 970 971 static int qed_slowpath_stop(struct qed_dev *cdev) 972 { 973 if (!cdev) 974 return -ENODEV; 975 976 qed_ll2_dealloc_if(cdev); 977 978 if (IS_PF(cdev)) { 979 qed_free_stream_mem(cdev); 980 if (IS_QED_ETH_IF(cdev)) 981 qed_sriov_disable(cdev, true); 982 983 qed_nic_stop(cdev); 984 qed_slowpath_irq_free(cdev); 985 } 986 987 qed_disable_msix(cdev); 988 qed_nic_reset(cdev); 989 990 qed_iov_wq_stop(cdev, true); 991 992 if (IS_PF(cdev)) 993 release_firmware(cdev->firmware); 994 995 return 0; 996 } 997 998 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE], 999 char ver_str[VER_SIZE]) 1000 { 1001 int i; 1002 1003 memcpy(cdev->name, name, NAME_SIZE); 1004 for_each_hwfn(cdev, i) 1005 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1006 1007 memcpy(cdev->ver_str, ver_str, VER_SIZE); 1008 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 1009 } 1010 1011 static u32 qed_sb_init(struct qed_dev *cdev, 1012 struct qed_sb_info *sb_info, 1013 void *sb_virt_addr, 1014 dma_addr_t sb_phy_addr, u16 sb_id, 1015 enum qed_sb_type type) 1016 { 1017 struct qed_hwfn *p_hwfn; 1018 int hwfn_index; 1019 u16 rel_sb_id; 1020 u8 n_hwfns; 1021 u32 rc; 1022 1023 /* RoCE uses single engine and CMT uses two engines. When using both 1024 * we force only a single engine. Storage uses only engine 0 too. 1025 */ 1026 if (type == QED_SB_TYPE_L2_QUEUE) 1027 n_hwfns = cdev->num_hwfns; 1028 else 1029 n_hwfns = 1; 1030 1031 hwfn_index = sb_id % n_hwfns; 1032 p_hwfn = &cdev->hwfns[hwfn_index]; 1033 rel_sb_id = sb_id / n_hwfns; 1034 1035 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1036 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1037 hwfn_index, rel_sb_id, sb_id); 1038 1039 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 1040 sb_virt_addr, sb_phy_addr, rel_sb_id); 1041 1042 return rc; 1043 } 1044 1045 static u32 qed_sb_release(struct qed_dev *cdev, 1046 struct qed_sb_info *sb_info, u16 sb_id) 1047 { 1048 struct qed_hwfn *p_hwfn; 1049 int hwfn_index; 1050 u16 rel_sb_id; 1051 u32 rc; 1052 1053 hwfn_index = sb_id % cdev->num_hwfns; 1054 p_hwfn = &cdev->hwfns[hwfn_index]; 1055 rel_sb_id = sb_id / cdev->num_hwfns; 1056 1057 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1058 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1059 hwfn_index, rel_sb_id, sb_id); 1060 1061 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1062 1063 return rc; 1064 } 1065 1066 static bool qed_can_link_change(struct qed_dev *cdev) 1067 { 1068 return true; 1069 } 1070 1071 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1072 { 1073 struct qed_hwfn *hwfn; 1074 struct qed_mcp_link_params *link_params; 1075 struct qed_ptt *ptt; 1076 int rc; 1077 1078 if (!cdev) 1079 return -ENODEV; 1080 1081 if (IS_VF(cdev)) 1082 return 0; 1083 1084 /* The link should be set only once per PF */ 1085 hwfn = &cdev->hwfns[0]; 1086 1087 ptt = qed_ptt_acquire(hwfn); 1088 if (!ptt) 1089 return -EBUSY; 1090 1091 link_params = qed_mcp_get_link_params(hwfn); 1092 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1093 link_params->speed.autoneg = params->autoneg; 1094 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1095 link_params->speed.advertised_speeds = 0; 1096 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1097 (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1098 link_params->speed.advertised_speeds |= 1099 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1100 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1101 link_params->speed.advertised_speeds |= 1102 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1103 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1104 link_params->speed.advertised_speeds |= 1105 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1106 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1107 link_params->speed.advertised_speeds |= 1108 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1109 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1110 link_params->speed.advertised_speeds |= 1111 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1112 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1113 link_params->speed.advertised_speeds |= 1114 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1115 } 1116 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1117 link_params->speed.forced_speed = params->forced_speed; 1118 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1119 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1120 link_params->pause.autoneg = true; 1121 else 1122 link_params->pause.autoneg = false; 1123 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1124 link_params->pause.forced_rx = true; 1125 else 1126 link_params->pause.forced_rx = false; 1127 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1128 link_params->pause.forced_tx = true; 1129 else 1130 link_params->pause.forced_tx = false; 1131 } 1132 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1133 switch (params->loopback_mode) { 1134 case QED_LINK_LOOPBACK_INT_PHY: 1135 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1136 break; 1137 case QED_LINK_LOOPBACK_EXT_PHY: 1138 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1139 break; 1140 case QED_LINK_LOOPBACK_EXT: 1141 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1142 break; 1143 case QED_LINK_LOOPBACK_MAC: 1144 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1145 break; 1146 default: 1147 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1148 break; 1149 } 1150 } 1151 1152 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1153 1154 qed_ptt_release(hwfn, ptt); 1155 1156 return rc; 1157 } 1158 1159 static int qed_get_port_type(u32 media_type) 1160 { 1161 int port_type; 1162 1163 switch (media_type) { 1164 case MEDIA_SFPP_10G_FIBER: 1165 case MEDIA_SFP_1G_FIBER: 1166 case MEDIA_XFP_FIBER: 1167 case MEDIA_MODULE_FIBER: 1168 case MEDIA_KR: 1169 port_type = PORT_FIBRE; 1170 break; 1171 case MEDIA_DA_TWINAX: 1172 port_type = PORT_DA; 1173 break; 1174 case MEDIA_BASE_T: 1175 port_type = PORT_TP; 1176 break; 1177 case MEDIA_NOT_PRESENT: 1178 port_type = PORT_NONE; 1179 break; 1180 case MEDIA_UNSPECIFIED: 1181 default: 1182 port_type = PORT_OTHER; 1183 break; 1184 } 1185 return port_type; 1186 } 1187 1188 static int qed_get_link_data(struct qed_hwfn *hwfn, 1189 struct qed_mcp_link_params *params, 1190 struct qed_mcp_link_state *link, 1191 struct qed_mcp_link_capabilities *link_caps) 1192 { 1193 void *p; 1194 1195 if (!IS_PF(hwfn->cdev)) { 1196 qed_vf_get_link_params(hwfn, params); 1197 qed_vf_get_link_state(hwfn, link); 1198 qed_vf_get_link_caps(hwfn, link_caps); 1199 1200 return 0; 1201 } 1202 1203 p = qed_mcp_get_link_params(hwfn); 1204 if (!p) 1205 return -ENXIO; 1206 memcpy(params, p, sizeof(*params)); 1207 1208 p = qed_mcp_get_link_state(hwfn); 1209 if (!p) 1210 return -ENXIO; 1211 memcpy(link, p, sizeof(*link)); 1212 1213 p = qed_mcp_get_link_capabilities(hwfn); 1214 if (!p) 1215 return -ENXIO; 1216 memcpy(link_caps, p, sizeof(*link_caps)); 1217 1218 return 0; 1219 } 1220 1221 static void qed_fill_link(struct qed_hwfn *hwfn, 1222 struct qed_link_output *if_link) 1223 { 1224 struct qed_mcp_link_params params; 1225 struct qed_mcp_link_state link; 1226 struct qed_mcp_link_capabilities link_caps; 1227 u32 media_type; 1228 1229 memset(if_link, 0, sizeof(*if_link)); 1230 1231 /* Prepare source inputs */ 1232 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1233 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1234 return; 1235 } 1236 1237 /* Set the link parameters to pass to protocol driver */ 1238 if (link.link_up) 1239 if_link->link_up = true; 1240 1241 /* TODO - at the moment assume supported and advertised speed equal */ 1242 if_link->supported_caps = QED_LM_FIBRE_BIT; 1243 if (params.speed.autoneg) 1244 if_link->supported_caps |= QED_LM_Autoneg_BIT; 1245 if (params.pause.autoneg || 1246 (params.pause.forced_rx && params.pause.forced_tx)) 1247 if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1248 if (params.pause.autoneg || params.pause.forced_rx || 1249 params.pause.forced_tx) 1250 if_link->supported_caps |= QED_LM_Pause_BIT; 1251 1252 if_link->advertised_caps = if_link->supported_caps; 1253 if (params.speed.advertised_speeds & 1254 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1255 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1256 QED_LM_1000baseT_Full_BIT; 1257 if (params.speed.advertised_speeds & 1258 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1259 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1260 if (params.speed.advertised_speeds & 1261 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1262 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1263 if (params.speed.advertised_speeds & 1264 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1265 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1266 if (params.speed.advertised_speeds & 1267 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1268 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1269 if (params.speed.advertised_speeds & 1270 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1271 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1272 1273 if (link_caps.speed_capabilities & 1274 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1275 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1276 QED_LM_1000baseT_Full_BIT; 1277 if (link_caps.speed_capabilities & 1278 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1279 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1280 if (link_caps.speed_capabilities & 1281 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1282 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1283 if (link_caps.speed_capabilities & 1284 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1285 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1286 if (link_caps.speed_capabilities & 1287 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1288 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1289 if (link_caps.speed_capabilities & 1290 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1291 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1292 1293 if (link.link_up) 1294 if_link->speed = link.speed; 1295 1296 /* TODO - fill duplex properly */ 1297 if_link->duplex = DUPLEX_FULL; 1298 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1299 if_link->port = qed_get_port_type(media_type); 1300 1301 if_link->autoneg = params.speed.autoneg; 1302 1303 if (params.pause.autoneg) 1304 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1305 if (params.pause.forced_rx) 1306 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1307 if (params.pause.forced_tx) 1308 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1309 1310 /* Link partner capabilities */ 1311 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1312 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1313 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1314 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1315 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1316 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1317 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1318 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1319 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1320 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1321 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1322 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1323 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1324 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1325 1326 if (link.an_complete) 1327 if_link->lp_caps |= QED_LM_Autoneg_BIT; 1328 1329 if (link.partner_adv_pause) 1330 if_link->lp_caps |= QED_LM_Pause_BIT; 1331 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1332 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1333 if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1334 } 1335 1336 static void qed_get_current_link(struct qed_dev *cdev, 1337 struct qed_link_output *if_link) 1338 { 1339 int i; 1340 1341 qed_fill_link(&cdev->hwfns[0], if_link); 1342 1343 for_each_hwfn(cdev, i) 1344 qed_inform_vf_link_state(&cdev->hwfns[i]); 1345 } 1346 1347 void qed_link_update(struct qed_hwfn *hwfn) 1348 { 1349 void *cookie = hwfn->cdev->ops_cookie; 1350 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1351 struct qed_link_output if_link; 1352 1353 qed_fill_link(hwfn, &if_link); 1354 qed_inform_vf_link_state(hwfn); 1355 1356 if (IS_LEAD_HWFN(hwfn) && cookie) 1357 op->link_update(cookie, &if_link); 1358 } 1359 1360 static int qed_drain(struct qed_dev *cdev) 1361 { 1362 struct qed_hwfn *hwfn; 1363 struct qed_ptt *ptt; 1364 int i, rc; 1365 1366 if (IS_VF(cdev)) 1367 return 0; 1368 1369 for_each_hwfn(cdev, i) { 1370 hwfn = &cdev->hwfns[i]; 1371 ptt = qed_ptt_acquire(hwfn); 1372 if (!ptt) { 1373 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1374 return -EBUSY; 1375 } 1376 rc = qed_mcp_drain(hwfn, ptt); 1377 if (rc) 1378 return rc; 1379 qed_ptt_release(hwfn, ptt); 1380 } 1381 1382 return 0; 1383 } 1384 1385 static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal) 1386 { 1387 *rx_coal = cdev->rx_coalesce_usecs; 1388 *tx_coal = cdev->tx_coalesce_usecs; 1389 } 1390 1391 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1392 u8 qid, u16 sb_id) 1393 { 1394 struct qed_hwfn *hwfn; 1395 struct qed_ptt *ptt; 1396 int hwfn_index; 1397 int status = 0; 1398 1399 hwfn_index = qid % cdev->num_hwfns; 1400 hwfn = &cdev->hwfns[hwfn_index]; 1401 ptt = qed_ptt_acquire(hwfn); 1402 if (!ptt) 1403 return -EAGAIN; 1404 1405 status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal, 1406 qid / cdev->num_hwfns, sb_id); 1407 if (status) 1408 goto out; 1409 status = qed_set_txq_coalesce(hwfn, ptt, tx_coal, 1410 qid / cdev->num_hwfns, sb_id); 1411 out: 1412 qed_ptt_release(hwfn, ptt); 1413 1414 return status; 1415 } 1416 1417 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1418 { 1419 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1420 struct qed_ptt *ptt; 1421 int status = 0; 1422 1423 ptt = qed_ptt_acquire(hwfn); 1424 if (!ptt) 1425 return -EAGAIN; 1426 1427 status = qed_mcp_set_led(hwfn, ptt, mode); 1428 1429 qed_ptt_release(hwfn, ptt); 1430 1431 return status; 1432 } 1433 1434 static struct qed_selftest_ops qed_selftest_ops_pass = { 1435 .selftest_memory = &qed_selftest_memory, 1436 .selftest_interrupt = &qed_selftest_interrupt, 1437 .selftest_register = &qed_selftest_register, 1438 .selftest_clock = &qed_selftest_clock, 1439 }; 1440 1441 const struct qed_common_ops qed_common_ops_pass = { 1442 .selftest = &qed_selftest_ops_pass, 1443 .probe = &qed_probe, 1444 .remove = &qed_remove, 1445 .set_power_state = &qed_set_power_state, 1446 .set_id = &qed_set_id, 1447 .update_pf_params = &qed_update_pf_params, 1448 .slowpath_start = &qed_slowpath_start, 1449 .slowpath_stop = &qed_slowpath_stop, 1450 .set_fp_int = &qed_set_int_fp, 1451 .get_fp_int = &qed_get_int_fp, 1452 .sb_init = &qed_sb_init, 1453 .sb_release = &qed_sb_release, 1454 .simd_handler_config = &qed_simd_handler_config, 1455 .simd_handler_clean = &qed_simd_handler_clean, 1456 .can_link_change = &qed_can_link_change, 1457 .set_link = &qed_set_link, 1458 .get_link = &qed_get_current_link, 1459 .drain = &qed_drain, 1460 .update_msglvl = &qed_init_dp, 1461 .dbg_all_data = &qed_dbg_all_data, 1462 .dbg_all_data_size = &qed_dbg_all_data_size, 1463 .chain_alloc = &qed_chain_alloc, 1464 .chain_free = &qed_chain_free, 1465 .get_coalesce = &qed_get_coalesce, 1466 .set_coalesce = &qed_set_coalesce, 1467 .set_led = &qed_set_led, 1468 }; 1469 1470 void qed_get_protocol_stats(struct qed_dev *cdev, 1471 enum qed_mcp_protocol_type type, 1472 union qed_mcp_protocol_stats *stats) 1473 { 1474 struct qed_eth_stats eth_stats; 1475 1476 memset(stats, 0, sizeof(*stats)); 1477 1478 switch (type) { 1479 case QED_MCP_LAN_STATS: 1480 qed_get_vport_stats(cdev, ð_stats); 1481 stats->lan_stats.ucast_rx_pkts = eth_stats.rx_ucast_pkts; 1482 stats->lan_stats.ucast_tx_pkts = eth_stats.tx_ucast_pkts; 1483 stats->lan_stats.fcs_err = -1; 1484 break; 1485 default: 1486 DP_ERR(cdev, "Invalid protocol type = %d\n", type); 1487 return; 1488 } 1489 } 1490