1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/stddef.h> 34 #include <linux/pci.h> 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/string.h> 41 #include <linux/module.h> 42 #include <linux/interrupt.h> 43 #include <linux/workqueue.h> 44 #include <linux/ethtool.h> 45 #include <linux/etherdevice.h> 46 #include <linux/vmalloc.h> 47 #include <linux/crash_dump.h> 48 #include <linux/crc32.h> 49 #include <linux/qed/qed_if.h> 50 #include <linux/qed/qed_ll2_if.h> 51 52 #include "qed.h" 53 #include "qed_sriov.h" 54 #include "qed_sp.h" 55 #include "qed_dev_api.h" 56 #include "qed_ll2.h" 57 #include "qed_fcoe.h" 58 #include "qed_iscsi.h" 59 60 #include "qed_mcp.h" 61 #include "qed_hw.h" 62 #include "qed_selftest.h" 63 #include "qed_debug.h" 64 65 #define QED_ROCE_QPS (8192) 66 #define QED_ROCE_DPIS (8) 67 #define QED_RDMA_SRQS QED_ROCE_QPS 68 69 static char version[] = 70 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 71 72 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 73 MODULE_LICENSE("GPL"); 74 MODULE_VERSION(DRV_MODULE_VERSION); 75 76 #define FW_FILE_VERSION \ 77 __stringify(FW_MAJOR_VERSION) "." \ 78 __stringify(FW_MINOR_VERSION) "." \ 79 __stringify(FW_REVISION_VERSION) "." \ 80 __stringify(FW_ENGINEERING_VERSION) 81 82 #define QED_FW_FILE_NAME \ 83 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 84 85 MODULE_FIRMWARE(QED_FW_FILE_NAME); 86 87 static int __init qed_init(void) 88 { 89 pr_info("%s", version); 90 91 return 0; 92 } 93 94 static void __exit qed_cleanup(void) 95 { 96 pr_notice("qed_cleanup called\n"); 97 } 98 99 module_init(qed_init); 100 module_exit(qed_cleanup); 101 102 /* Check if the DMA controller on the machine can properly handle the DMA 103 * addressing required by the device. 104 */ 105 static int qed_set_coherency_mask(struct qed_dev *cdev) 106 { 107 struct device *dev = &cdev->pdev->dev; 108 109 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 110 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 111 DP_NOTICE(cdev, 112 "Can't request 64-bit consistent allocations\n"); 113 return -EIO; 114 } 115 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 116 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 117 return -EIO; 118 } 119 120 return 0; 121 } 122 123 static void qed_free_pci(struct qed_dev *cdev) 124 { 125 struct pci_dev *pdev = cdev->pdev; 126 127 if (cdev->doorbells && cdev->db_size) 128 iounmap(cdev->doorbells); 129 if (cdev->regview) 130 iounmap(cdev->regview); 131 if (atomic_read(&pdev->enable_cnt) == 1) 132 pci_release_regions(pdev); 133 134 pci_disable_device(pdev); 135 } 136 137 #define PCI_REVISION_ID_ERROR_VAL 0xff 138 139 /* Performs PCI initializations as well as initializing PCI-related parameters 140 * in the device structrue. Returns 0 in case of success. 141 */ 142 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 143 { 144 u8 rev_id; 145 int rc; 146 147 cdev->pdev = pdev; 148 149 rc = pci_enable_device(pdev); 150 if (rc) { 151 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 152 goto err0; 153 } 154 155 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 156 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 157 rc = -EIO; 158 goto err1; 159 } 160 161 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 162 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 163 rc = -EIO; 164 goto err1; 165 } 166 167 if (atomic_read(&pdev->enable_cnt) == 1) { 168 rc = pci_request_regions(pdev, "qed"); 169 if (rc) { 170 DP_NOTICE(cdev, 171 "Failed to request PCI memory resources\n"); 172 goto err1; 173 } 174 pci_set_master(pdev); 175 pci_save_state(pdev); 176 } 177 178 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 179 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 180 DP_NOTICE(cdev, 181 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 182 rev_id); 183 rc = -ENODEV; 184 goto err2; 185 } 186 if (!pci_is_pcie(pdev)) { 187 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 188 rc = -EIO; 189 goto err2; 190 } 191 192 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 193 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 194 DP_NOTICE(cdev, "Cannot find power management capability\n"); 195 196 rc = qed_set_coherency_mask(cdev); 197 if (rc) 198 goto err2; 199 200 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 201 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 202 cdev->pci_params.irq = pdev->irq; 203 204 cdev->regview = pci_ioremap_bar(pdev, 0); 205 if (!cdev->regview) { 206 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 207 rc = -ENOMEM; 208 goto err2; 209 } 210 211 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 212 cdev->db_size = pci_resource_len(cdev->pdev, 2); 213 if (!cdev->db_size) { 214 if (IS_PF(cdev)) { 215 DP_NOTICE(cdev, "No Doorbell bar available\n"); 216 return -EINVAL; 217 } else { 218 return 0; 219 } 220 } 221 222 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 223 224 if (!cdev->doorbells) { 225 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 226 return -ENOMEM; 227 } 228 229 return 0; 230 231 err2: 232 pci_release_regions(pdev); 233 err1: 234 pci_disable_device(pdev); 235 err0: 236 return rc; 237 } 238 239 int qed_fill_dev_info(struct qed_dev *cdev, 240 struct qed_dev_info *dev_info) 241 { 242 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 243 struct qed_hw_info *hw_info = &p_hwfn->hw_info; 244 struct qed_tunnel_info *tun = &cdev->tunnel; 245 struct qed_ptt *ptt; 246 247 memset(dev_info, 0, sizeof(struct qed_dev_info)); 248 249 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 250 tun->vxlan.b_mode_enabled) 251 dev_info->vxlan_enable = true; 252 253 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled && 254 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 255 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 256 dev_info->gre_enable = true; 257 258 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled && 259 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN && 260 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN) 261 dev_info->geneve_enable = true; 262 263 dev_info->num_hwfns = cdev->num_hwfns; 264 dev_info->pci_mem_start = cdev->pci_params.mem_start; 265 dev_info->pci_mem_end = cdev->pci_params.mem_end; 266 dev_info->pci_irq = cdev->pci_params.irq; 267 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn); 268 dev_info->dev_type = cdev->type; 269 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr); 270 271 if (IS_PF(cdev)) { 272 dev_info->fw_major = FW_MAJOR_VERSION; 273 dev_info->fw_minor = FW_MINOR_VERSION; 274 dev_info->fw_rev = FW_REVISION_VERSION; 275 dev_info->fw_eng = FW_ENGINEERING_VERSION; 276 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH, 277 &cdev->mf_bits); 278 dev_info->tx_switching = true; 279 280 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME) 281 dev_info->wol_support = true; 282 283 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id; 284 } else { 285 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 286 &dev_info->fw_minor, &dev_info->fw_rev, 287 &dev_info->fw_eng); 288 } 289 290 if (IS_PF(cdev)) { 291 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 292 if (ptt) { 293 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 294 &dev_info->mfw_rev, NULL); 295 296 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt, 297 &dev_info->mbi_version); 298 299 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 300 &dev_info->flash_size); 301 302 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 303 } 304 } else { 305 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 306 &dev_info->mfw_rev, NULL); 307 } 308 309 dev_info->mtu = hw_info->mtu; 310 311 return 0; 312 } 313 314 static void qed_free_cdev(struct qed_dev *cdev) 315 { 316 kfree((void *)cdev); 317 } 318 319 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 320 { 321 struct qed_dev *cdev; 322 323 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 324 if (!cdev) 325 return cdev; 326 327 qed_init_struct(cdev); 328 329 return cdev; 330 } 331 332 /* Sets the requested power state */ 333 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 334 { 335 if (!cdev) 336 return -ENODEV; 337 338 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 339 return 0; 340 } 341 342 /* probing */ 343 static struct qed_dev *qed_probe(struct pci_dev *pdev, 344 struct qed_probe_params *params) 345 { 346 struct qed_dev *cdev; 347 int rc; 348 349 cdev = qed_alloc_cdev(pdev); 350 if (!cdev) 351 goto err0; 352 353 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 354 cdev->protocol = params->protocol; 355 356 if (params->is_vf) 357 cdev->b_is_vf = true; 358 359 qed_init_dp(cdev, params->dp_module, params->dp_level); 360 361 rc = qed_init_pci(cdev, pdev); 362 if (rc) { 363 DP_ERR(cdev, "init pci failed\n"); 364 goto err1; 365 } 366 DP_INFO(cdev, "PCI init completed successfully\n"); 367 368 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 369 if (rc) { 370 DP_ERR(cdev, "hw prepare failed\n"); 371 goto err2; 372 } 373 374 DP_INFO(cdev, "qed_probe completed successffuly\n"); 375 376 return cdev; 377 378 err2: 379 qed_free_pci(cdev); 380 err1: 381 qed_free_cdev(cdev); 382 err0: 383 return NULL; 384 } 385 386 static void qed_remove(struct qed_dev *cdev) 387 { 388 if (!cdev) 389 return; 390 391 qed_hw_remove(cdev); 392 393 qed_free_pci(cdev); 394 395 qed_set_power_state(cdev, PCI_D3hot); 396 397 qed_free_cdev(cdev); 398 } 399 400 static void qed_disable_msix(struct qed_dev *cdev) 401 { 402 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 403 pci_disable_msix(cdev->pdev); 404 kfree(cdev->int_params.msix_table); 405 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 406 pci_disable_msi(cdev->pdev); 407 } 408 409 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 410 } 411 412 static int qed_enable_msix(struct qed_dev *cdev, 413 struct qed_int_params *int_params) 414 { 415 int i, rc, cnt; 416 417 cnt = int_params->in.num_vectors; 418 419 for (i = 0; i < cnt; i++) 420 int_params->msix_table[i].entry = i; 421 422 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 423 int_params->in.min_msix_cnt, cnt); 424 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 425 (rc % cdev->num_hwfns)) { 426 pci_disable_msix(cdev->pdev); 427 428 /* If fastpath is initialized, we need at least one interrupt 429 * per hwfn [and the slow path interrupts]. New requested number 430 * should be a multiple of the number of hwfns. 431 */ 432 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 433 DP_NOTICE(cdev, 434 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 435 cnt, int_params->in.num_vectors); 436 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 437 cnt); 438 if (!rc) 439 rc = cnt; 440 } 441 442 if (rc > 0) { 443 /* MSI-x configuration was achieved */ 444 int_params->out.int_mode = QED_INT_MODE_MSIX; 445 int_params->out.num_vectors = rc; 446 rc = 0; 447 } else { 448 DP_NOTICE(cdev, 449 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 450 cnt, rc); 451 } 452 453 return rc; 454 } 455 456 /* This function outputs the int mode and the number of enabled msix vector */ 457 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 458 { 459 struct qed_int_params *int_params = &cdev->int_params; 460 struct msix_entry *tbl; 461 int rc = 0, cnt; 462 463 switch (int_params->in.int_mode) { 464 case QED_INT_MODE_MSIX: 465 /* Allocate MSIX table */ 466 cnt = int_params->in.num_vectors; 467 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 468 if (!int_params->msix_table) { 469 rc = -ENOMEM; 470 goto out; 471 } 472 473 /* Enable MSIX */ 474 rc = qed_enable_msix(cdev, int_params); 475 if (!rc) 476 goto out; 477 478 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 479 kfree(int_params->msix_table); 480 if (force_mode) 481 goto out; 482 /* Fallthrough */ 483 484 case QED_INT_MODE_MSI: 485 if (cdev->num_hwfns == 1) { 486 rc = pci_enable_msi(cdev->pdev); 487 if (!rc) { 488 int_params->out.int_mode = QED_INT_MODE_MSI; 489 goto out; 490 } 491 492 DP_NOTICE(cdev, "Failed to enable MSI\n"); 493 if (force_mode) 494 goto out; 495 } 496 /* Fallthrough */ 497 498 case QED_INT_MODE_INTA: 499 int_params->out.int_mode = QED_INT_MODE_INTA; 500 rc = 0; 501 goto out; 502 default: 503 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 504 int_params->in.int_mode); 505 rc = -EINVAL; 506 } 507 508 out: 509 if (!rc) 510 DP_INFO(cdev, "Using %s interrupts\n", 511 int_params->out.int_mode == QED_INT_MODE_INTA ? 512 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? 513 "MSI" : "MSIX"); 514 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 515 516 return rc; 517 } 518 519 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 520 int index, void(*handler)(void *)) 521 { 522 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 523 int relative_idx = index / cdev->num_hwfns; 524 525 hwfn->simd_proto_handler[relative_idx].func = handler; 526 hwfn->simd_proto_handler[relative_idx].token = token; 527 } 528 529 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 530 { 531 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 532 int relative_idx = index / cdev->num_hwfns; 533 534 memset(&hwfn->simd_proto_handler[relative_idx], 0, 535 sizeof(struct qed_simd_fp_handler)); 536 } 537 538 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 539 { 540 tasklet_schedule((struct tasklet_struct *)tasklet); 541 return IRQ_HANDLED; 542 } 543 544 static irqreturn_t qed_single_int(int irq, void *dev_instance) 545 { 546 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 547 struct qed_hwfn *hwfn; 548 irqreturn_t rc = IRQ_NONE; 549 u64 status; 550 int i, j; 551 552 for (i = 0; i < cdev->num_hwfns; i++) { 553 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 554 555 if (!status) 556 continue; 557 558 hwfn = &cdev->hwfns[i]; 559 560 /* Slowpath interrupt */ 561 if (unlikely(status & 0x1)) { 562 tasklet_schedule(hwfn->sp_dpc); 563 status &= ~0x1; 564 rc = IRQ_HANDLED; 565 } 566 567 /* Fastpath interrupts */ 568 for (j = 0; j < 64; j++) { 569 if ((0x2ULL << j) & status) { 570 struct qed_simd_fp_handler *p_handler = 571 &hwfn->simd_proto_handler[j]; 572 573 if (p_handler->func) 574 p_handler->func(p_handler->token); 575 else 576 DP_NOTICE(hwfn, 577 "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n", 578 j, status); 579 580 status &= ~(0x2ULL << j); 581 rc = IRQ_HANDLED; 582 } 583 } 584 585 if (unlikely(status)) 586 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 587 "got an unknown interrupt status 0x%llx\n", 588 status); 589 } 590 591 return rc; 592 } 593 594 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 595 { 596 struct qed_dev *cdev = hwfn->cdev; 597 u32 int_mode; 598 int rc = 0; 599 u8 id; 600 601 int_mode = cdev->int_params.out.int_mode; 602 if (int_mode == QED_INT_MODE_MSIX) { 603 id = hwfn->my_id; 604 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 605 id, cdev->pdev->bus->number, 606 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 607 rc = request_irq(cdev->int_params.msix_table[id].vector, 608 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 609 } else { 610 unsigned long flags = 0; 611 612 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 613 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 614 PCI_FUNC(cdev->pdev->devfn)); 615 616 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 617 flags |= IRQF_SHARED; 618 619 rc = request_irq(cdev->pdev->irq, qed_single_int, 620 flags, cdev->name, cdev); 621 } 622 623 if (rc) 624 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); 625 else 626 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 627 "Requested slowpath %s\n", 628 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); 629 630 return rc; 631 } 632 633 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn) 634 { 635 /* Calling the disable function will make sure that any 636 * currently-running function is completed. The following call to the 637 * enable function makes this sequence a flush-like operation. 638 */ 639 if (p_hwfn->b_sp_dpc_enabled) { 640 tasklet_disable(p_hwfn->sp_dpc); 641 tasklet_enable(p_hwfn->sp_dpc); 642 } 643 } 644 645 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn) 646 { 647 struct qed_dev *cdev = p_hwfn->cdev; 648 u8 id = p_hwfn->my_id; 649 u32 int_mode; 650 651 int_mode = cdev->int_params.out.int_mode; 652 if (int_mode == QED_INT_MODE_MSIX) 653 synchronize_irq(cdev->int_params.msix_table[id].vector); 654 else 655 synchronize_irq(cdev->pdev->irq); 656 657 qed_slowpath_tasklet_flush(p_hwfn); 658 } 659 660 static void qed_slowpath_irq_free(struct qed_dev *cdev) 661 { 662 int i; 663 664 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 665 for_each_hwfn(cdev, i) { 666 if (!cdev->hwfns[i].b_int_requested) 667 break; 668 synchronize_irq(cdev->int_params.msix_table[i].vector); 669 free_irq(cdev->int_params.msix_table[i].vector, 670 cdev->hwfns[i].sp_dpc); 671 } 672 } else { 673 if (QED_LEADING_HWFN(cdev)->b_int_requested) 674 free_irq(cdev->pdev->irq, cdev); 675 } 676 qed_int_disable_post_isr_release(cdev); 677 } 678 679 static int qed_nic_stop(struct qed_dev *cdev) 680 { 681 int i, rc; 682 683 rc = qed_hw_stop(cdev); 684 685 for (i = 0; i < cdev->num_hwfns; i++) { 686 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 687 688 if (p_hwfn->b_sp_dpc_enabled) { 689 tasklet_disable(p_hwfn->sp_dpc); 690 p_hwfn->b_sp_dpc_enabled = false; 691 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 692 "Disabled sp tasklet [hwfn %d] at %p\n", 693 i, p_hwfn->sp_dpc); 694 } 695 } 696 697 qed_dbg_pf_exit(cdev); 698 699 return rc; 700 } 701 702 static int qed_nic_setup(struct qed_dev *cdev) 703 { 704 int rc, i; 705 706 /* Determine if interface is going to require LL2 */ 707 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { 708 for (i = 0; i < cdev->num_hwfns; i++) { 709 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 710 711 p_hwfn->using_ll2 = true; 712 } 713 } 714 715 rc = qed_resc_alloc(cdev); 716 if (rc) 717 return rc; 718 719 DP_INFO(cdev, "Allocated qed resources\n"); 720 721 qed_resc_setup(cdev); 722 723 return rc; 724 } 725 726 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 727 { 728 int limit = 0; 729 730 /* Mark the fastpath as free/used */ 731 cdev->int_params.fp_initialized = cnt ? true : false; 732 733 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 734 limit = cdev->num_hwfns * 63; 735 else if (cdev->int_params.fp_msix_cnt) 736 limit = cdev->int_params.fp_msix_cnt; 737 738 if (!limit) 739 return -ENOMEM; 740 741 return min_t(int, cnt, limit); 742 } 743 744 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 745 { 746 memset(info, 0, sizeof(struct qed_int_info)); 747 748 if (!cdev->int_params.fp_initialized) { 749 DP_INFO(cdev, 750 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 751 return -EINVAL; 752 } 753 754 /* Need to expose only MSI-X information; Single IRQ is handled solely 755 * by qed. 756 */ 757 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 758 int msix_base = cdev->int_params.fp_msix_base; 759 760 info->msix_cnt = cdev->int_params.fp_msix_cnt; 761 info->msix = &cdev->int_params.msix_table[msix_base]; 762 } 763 764 return 0; 765 } 766 767 static int qed_slowpath_setup_int(struct qed_dev *cdev, 768 enum qed_int_mode int_mode) 769 { 770 struct qed_sb_cnt_info sb_cnt_info; 771 int num_l2_queues = 0; 772 int rc; 773 int i; 774 775 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 776 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 777 return -EINVAL; 778 } 779 780 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 781 cdev->int_params.in.int_mode = int_mode; 782 for_each_hwfn(cdev, i) { 783 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 784 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 785 cdev->int_params.in.num_vectors += sb_cnt_info.cnt; 786 cdev->int_params.in.num_vectors++; /* slowpath */ 787 } 788 789 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 790 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 791 792 rc = qed_set_int_mode(cdev, false); 793 if (rc) { 794 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 795 return rc; 796 } 797 798 cdev->int_params.fp_msix_base = cdev->num_hwfns; 799 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 800 cdev->num_hwfns; 801 802 if (!IS_ENABLED(CONFIG_QED_RDMA) || 803 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) 804 return 0; 805 806 for_each_hwfn(cdev, i) 807 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 808 809 DP_VERBOSE(cdev, QED_MSG_RDMA, 810 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n", 811 cdev->int_params.fp_msix_cnt, num_l2_queues); 812 813 if (cdev->int_params.fp_msix_cnt > num_l2_queues) { 814 cdev->int_params.rdma_msix_cnt = 815 (cdev->int_params.fp_msix_cnt - num_l2_queues) 816 / cdev->num_hwfns; 817 cdev->int_params.rdma_msix_base = 818 cdev->int_params.fp_msix_base + num_l2_queues; 819 cdev->int_params.fp_msix_cnt = num_l2_queues; 820 } else { 821 cdev->int_params.rdma_msix_cnt = 0; 822 } 823 824 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n", 825 cdev->int_params.rdma_msix_cnt, 826 cdev->int_params.rdma_msix_base); 827 828 return 0; 829 } 830 831 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 832 { 833 int rc; 834 835 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 836 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 837 838 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 839 &cdev->int_params.in.num_vectors); 840 if (cdev->num_hwfns > 1) { 841 u8 vectors = 0; 842 843 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 844 cdev->int_params.in.num_vectors += vectors; 845 } 846 847 /* We want a minimum of one fastpath vector per vf hwfn */ 848 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 849 850 rc = qed_set_int_mode(cdev, true); 851 if (rc) 852 return rc; 853 854 cdev->int_params.fp_msix_base = 0; 855 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 856 857 return 0; 858 } 859 860 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 861 u8 *input_buf, u32 max_size, u8 *unzip_buf) 862 { 863 int rc; 864 865 p_hwfn->stream->next_in = input_buf; 866 p_hwfn->stream->avail_in = input_len; 867 p_hwfn->stream->next_out = unzip_buf; 868 p_hwfn->stream->avail_out = max_size; 869 870 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 871 872 if (rc != Z_OK) { 873 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 874 rc); 875 return 0; 876 } 877 878 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 879 zlib_inflateEnd(p_hwfn->stream); 880 881 if (rc != Z_OK && rc != Z_STREAM_END) { 882 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 883 p_hwfn->stream->msg, rc); 884 return 0; 885 } 886 887 return p_hwfn->stream->total_out / 4; 888 } 889 890 static int qed_alloc_stream_mem(struct qed_dev *cdev) 891 { 892 int i; 893 void *workspace; 894 895 for_each_hwfn(cdev, i) { 896 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 897 898 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 899 if (!p_hwfn->stream) 900 return -ENOMEM; 901 902 workspace = vzalloc(zlib_inflate_workspacesize()); 903 if (!workspace) 904 return -ENOMEM; 905 p_hwfn->stream->workspace = workspace; 906 } 907 908 return 0; 909 } 910 911 static void qed_free_stream_mem(struct qed_dev *cdev) 912 { 913 int i; 914 915 for_each_hwfn(cdev, i) { 916 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 917 918 if (!p_hwfn->stream) 919 return; 920 921 vfree(p_hwfn->stream->workspace); 922 kfree(p_hwfn->stream); 923 } 924 } 925 926 static void qed_update_pf_params(struct qed_dev *cdev, 927 struct qed_pf_params *params) 928 { 929 int i; 930 931 if (IS_ENABLED(CONFIG_QED_RDMA)) { 932 params->rdma_pf_params.num_qps = QED_ROCE_QPS; 933 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; 934 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS; 935 /* divide by 3 the MRs to avoid MF ILT overflow */ 936 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; 937 } 938 939 if (cdev->num_hwfns > 1 || IS_VF(cdev)) 940 params->eth_pf_params.num_arfs_filters = 0; 941 942 /* In case we might support RDMA, don't allow qede to be greedy 943 * with the L2 contexts. Allow for 64 queues [rx, tx, xdp] per hwfn. 944 */ 945 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) { 946 u16 *num_cons; 947 948 num_cons = ¶ms->eth_pf_params.num_cons; 949 *num_cons = min_t(u16, *num_cons, 192); 950 } 951 952 for (i = 0; i < cdev->num_hwfns; i++) { 953 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 954 955 p_hwfn->pf_params = *params; 956 } 957 } 958 959 static void qed_slowpath_wq_stop(struct qed_dev *cdev) 960 { 961 int i; 962 963 if (IS_VF(cdev)) 964 return; 965 966 for_each_hwfn(cdev, i) { 967 if (!cdev->hwfns[i].slowpath_wq) 968 continue; 969 970 flush_workqueue(cdev->hwfns[i].slowpath_wq); 971 destroy_workqueue(cdev->hwfns[i].slowpath_wq); 972 } 973 } 974 975 static void qed_slowpath_task(struct work_struct *work) 976 { 977 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn, 978 slowpath_task.work); 979 struct qed_ptt *ptt = qed_ptt_acquire(hwfn); 980 981 if (!ptt) { 982 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); 983 return; 984 } 985 986 if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ, 987 &hwfn->slowpath_task_flags)) 988 qed_mfw_process_tlv_req(hwfn, ptt); 989 990 qed_ptt_release(hwfn, ptt); 991 } 992 993 static int qed_slowpath_wq_start(struct qed_dev *cdev) 994 { 995 struct qed_hwfn *hwfn; 996 char name[NAME_SIZE]; 997 int i; 998 999 if (IS_VF(cdev)) 1000 return 0; 1001 1002 for_each_hwfn(cdev, i) { 1003 hwfn = &cdev->hwfns[i]; 1004 1005 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x", 1006 cdev->pdev->bus->number, 1007 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 1008 1009 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0); 1010 if (!hwfn->slowpath_wq) { 1011 DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n"); 1012 return -ENOMEM; 1013 } 1014 1015 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task); 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int qed_slowpath_start(struct qed_dev *cdev, 1022 struct qed_slowpath_params *params) 1023 { 1024 struct qed_drv_load_params drv_load_params; 1025 struct qed_hw_init_params hw_init_params; 1026 struct qed_mcp_drv_version drv_version; 1027 struct qed_tunnel_info tunn_info; 1028 const u8 *data = NULL; 1029 struct qed_hwfn *hwfn; 1030 struct qed_ptt *p_ptt; 1031 int rc = -EINVAL; 1032 1033 if (qed_iov_wq_start(cdev)) 1034 goto err; 1035 1036 if (qed_slowpath_wq_start(cdev)) 1037 goto err; 1038 1039 if (IS_PF(cdev)) { 1040 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 1041 &cdev->pdev->dev); 1042 if (rc) { 1043 DP_NOTICE(cdev, 1044 "Failed to find fw file - /lib/firmware/%s\n", 1045 QED_FW_FILE_NAME); 1046 goto err; 1047 } 1048 1049 if (cdev->num_hwfns == 1) { 1050 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 1051 if (p_ptt) { 1052 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt; 1053 } else { 1054 DP_NOTICE(cdev, 1055 "Failed to acquire PTT for aRFS\n"); 1056 goto err; 1057 } 1058 } 1059 } 1060 1061 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; 1062 rc = qed_nic_setup(cdev); 1063 if (rc) 1064 goto err; 1065 1066 if (IS_PF(cdev)) 1067 rc = qed_slowpath_setup_int(cdev, params->int_mode); 1068 else 1069 rc = qed_slowpath_vf_setup_int(cdev); 1070 if (rc) 1071 goto err1; 1072 1073 if (IS_PF(cdev)) { 1074 /* Allocate stream for unzipping */ 1075 rc = qed_alloc_stream_mem(cdev); 1076 if (rc) 1077 goto err2; 1078 1079 /* First Dword used to differentiate between various sources */ 1080 data = cdev->firmware->data + sizeof(u32); 1081 1082 qed_dbg_pf_init(cdev); 1083 } 1084 1085 /* Start the slowpath */ 1086 memset(&hw_init_params, 0, sizeof(hw_init_params)); 1087 memset(&tunn_info, 0, sizeof(tunn_info)); 1088 tunn_info.vxlan.b_mode_enabled = true; 1089 tunn_info.l2_gre.b_mode_enabled = true; 1090 tunn_info.ip_gre.b_mode_enabled = true; 1091 tunn_info.l2_geneve.b_mode_enabled = true; 1092 tunn_info.ip_geneve.b_mode_enabled = true; 1093 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1094 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1095 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1096 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1097 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; 1098 hw_init_params.p_tunn = &tunn_info; 1099 hw_init_params.b_hw_start = true; 1100 hw_init_params.int_mode = cdev->int_params.out.int_mode; 1101 hw_init_params.allow_npar_tx_switch = true; 1102 hw_init_params.bin_fw_data = data; 1103 1104 memset(&drv_load_params, 0, sizeof(drv_load_params)); 1105 drv_load_params.is_crash_kernel = is_kdump_kernel(); 1106 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT; 1107 drv_load_params.avoid_eng_reset = false; 1108 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE; 1109 hw_init_params.p_drv_load_params = &drv_load_params; 1110 1111 rc = qed_hw_init(cdev, &hw_init_params); 1112 if (rc) 1113 goto err2; 1114 1115 DP_INFO(cdev, 1116 "HW initialization and function start completed successfully\n"); 1117 1118 if (IS_PF(cdev)) { 1119 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) | 1120 BIT(QED_MODE_L2GENEVE_TUNN) | 1121 BIT(QED_MODE_IPGENEVE_TUNN) | 1122 BIT(QED_MODE_L2GRE_TUNN) | 1123 BIT(QED_MODE_IPGRE_TUNN)); 1124 } 1125 1126 /* Allocate LL2 interface if needed */ 1127 if (QED_LEADING_HWFN(cdev)->using_ll2) { 1128 rc = qed_ll2_alloc_if(cdev); 1129 if (rc) 1130 goto err3; 1131 } 1132 if (IS_PF(cdev)) { 1133 hwfn = QED_LEADING_HWFN(cdev); 1134 drv_version.version = (params->drv_major << 24) | 1135 (params->drv_minor << 16) | 1136 (params->drv_rev << 8) | 1137 (params->drv_eng); 1138 strlcpy(drv_version.name, params->name, 1139 MCP_DRV_VER_STR_SIZE - 4); 1140 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 1141 &drv_version); 1142 if (rc) { 1143 DP_NOTICE(cdev, "Failed sending drv version command\n"); 1144 return rc; 1145 } 1146 } 1147 1148 qed_reset_vport_stats(cdev); 1149 1150 return 0; 1151 1152 err3: 1153 qed_hw_stop(cdev); 1154 err2: 1155 qed_hw_timers_stop_all(cdev); 1156 if (IS_PF(cdev)) 1157 qed_slowpath_irq_free(cdev); 1158 qed_free_stream_mem(cdev); 1159 qed_disable_msix(cdev); 1160 err1: 1161 qed_resc_free(cdev); 1162 err: 1163 if (IS_PF(cdev)) 1164 release_firmware(cdev->firmware); 1165 1166 if (IS_PF(cdev) && (cdev->num_hwfns == 1) && 1167 QED_LEADING_HWFN(cdev)->p_arfs_ptt) 1168 qed_ptt_release(QED_LEADING_HWFN(cdev), 1169 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1170 1171 qed_iov_wq_stop(cdev, false); 1172 1173 qed_slowpath_wq_stop(cdev); 1174 1175 return rc; 1176 } 1177 1178 static int qed_slowpath_stop(struct qed_dev *cdev) 1179 { 1180 if (!cdev) 1181 return -ENODEV; 1182 1183 qed_slowpath_wq_stop(cdev); 1184 1185 qed_ll2_dealloc_if(cdev); 1186 1187 if (IS_PF(cdev)) { 1188 if (cdev->num_hwfns == 1) 1189 qed_ptt_release(QED_LEADING_HWFN(cdev), 1190 QED_LEADING_HWFN(cdev)->p_arfs_ptt); 1191 qed_free_stream_mem(cdev); 1192 if (IS_QED_ETH_IF(cdev)) 1193 qed_sriov_disable(cdev, true); 1194 } 1195 1196 qed_nic_stop(cdev); 1197 1198 if (IS_PF(cdev)) 1199 qed_slowpath_irq_free(cdev); 1200 1201 qed_disable_msix(cdev); 1202 1203 qed_resc_free(cdev); 1204 1205 qed_iov_wq_stop(cdev, true); 1206 1207 if (IS_PF(cdev)) 1208 release_firmware(cdev->firmware); 1209 1210 return 0; 1211 } 1212 1213 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE]) 1214 { 1215 int i; 1216 1217 memcpy(cdev->name, name, NAME_SIZE); 1218 for_each_hwfn(cdev, i) 1219 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 1220 } 1221 1222 static u32 qed_sb_init(struct qed_dev *cdev, 1223 struct qed_sb_info *sb_info, 1224 void *sb_virt_addr, 1225 dma_addr_t sb_phy_addr, u16 sb_id, 1226 enum qed_sb_type type) 1227 { 1228 struct qed_hwfn *p_hwfn; 1229 struct qed_ptt *p_ptt; 1230 int hwfn_index; 1231 u16 rel_sb_id; 1232 u8 n_hwfns; 1233 u32 rc; 1234 1235 /* RoCE uses single engine and CMT uses two engines. When using both 1236 * we force only a single engine. Storage uses only engine 0 too. 1237 */ 1238 if (type == QED_SB_TYPE_L2_QUEUE) 1239 n_hwfns = cdev->num_hwfns; 1240 else 1241 n_hwfns = 1; 1242 1243 hwfn_index = sb_id % n_hwfns; 1244 p_hwfn = &cdev->hwfns[hwfn_index]; 1245 rel_sb_id = sb_id / n_hwfns; 1246 1247 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1248 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1249 hwfn_index, rel_sb_id, sb_id); 1250 1251 if (IS_PF(p_hwfn->cdev)) { 1252 p_ptt = qed_ptt_acquire(p_hwfn); 1253 if (!p_ptt) 1254 return -EBUSY; 1255 1256 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr, 1257 sb_phy_addr, rel_sb_id); 1258 qed_ptt_release(p_hwfn, p_ptt); 1259 } else { 1260 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr, 1261 sb_phy_addr, rel_sb_id); 1262 } 1263 1264 return rc; 1265 } 1266 1267 static u32 qed_sb_release(struct qed_dev *cdev, 1268 struct qed_sb_info *sb_info, u16 sb_id) 1269 { 1270 struct qed_hwfn *p_hwfn; 1271 int hwfn_index; 1272 u16 rel_sb_id; 1273 u32 rc; 1274 1275 hwfn_index = sb_id % cdev->num_hwfns; 1276 p_hwfn = &cdev->hwfns[hwfn_index]; 1277 rel_sb_id = sb_id / cdev->num_hwfns; 1278 1279 DP_VERBOSE(cdev, NETIF_MSG_INTR, 1280 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 1281 hwfn_index, rel_sb_id, sb_id); 1282 1283 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 1284 1285 return rc; 1286 } 1287 1288 static bool qed_can_link_change(struct qed_dev *cdev) 1289 { 1290 return true; 1291 } 1292 1293 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1294 { 1295 struct qed_hwfn *hwfn; 1296 struct qed_mcp_link_params *link_params; 1297 struct qed_ptt *ptt; 1298 int rc; 1299 1300 if (!cdev) 1301 return -ENODEV; 1302 1303 /* The link should be set only once per PF */ 1304 hwfn = &cdev->hwfns[0]; 1305 1306 /* When VF wants to set link, force it to read the bulletin instead. 1307 * This mimics the PF behavior, where a noitification [both immediate 1308 * and possible later] would be generated when changing properties. 1309 */ 1310 if (IS_VF(cdev)) { 1311 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG); 1312 return 0; 1313 } 1314 1315 ptt = qed_ptt_acquire(hwfn); 1316 if (!ptt) 1317 return -EBUSY; 1318 1319 link_params = qed_mcp_get_link_params(hwfn); 1320 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1321 link_params->speed.autoneg = params->autoneg; 1322 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1323 link_params->speed.advertised_speeds = 0; 1324 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1325 (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1326 link_params->speed.advertised_speeds |= 1327 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1328 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1329 link_params->speed.advertised_speeds |= 1330 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1331 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1332 link_params->speed.advertised_speeds |= 1333 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1334 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1335 link_params->speed.advertised_speeds |= 1336 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1337 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1338 link_params->speed.advertised_speeds |= 1339 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1340 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1341 link_params->speed.advertised_speeds |= 1342 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1343 } 1344 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1345 link_params->speed.forced_speed = params->forced_speed; 1346 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1347 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1348 link_params->pause.autoneg = true; 1349 else 1350 link_params->pause.autoneg = false; 1351 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1352 link_params->pause.forced_rx = true; 1353 else 1354 link_params->pause.forced_rx = false; 1355 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1356 link_params->pause.forced_tx = true; 1357 else 1358 link_params->pause.forced_tx = false; 1359 } 1360 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1361 switch (params->loopback_mode) { 1362 case QED_LINK_LOOPBACK_INT_PHY: 1363 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 1364 break; 1365 case QED_LINK_LOOPBACK_EXT_PHY: 1366 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 1367 break; 1368 case QED_LINK_LOOPBACK_EXT: 1369 link_params->loopback_mode = ETH_LOOPBACK_EXT; 1370 break; 1371 case QED_LINK_LOOPBACK_MAC: 1372 link_params->loopback_mode = ETH_LOOPBACK_MAC; 1373 break; 1374 default: 1375 link_params->loopback_mode = ETH_LOOPBACK_NONE; 1376 break; 1377 } 1378 } 1379 1380 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG) 1381 memcpy(&link_params->eee, ¶ms->eee, 1382 sizeof(link_params->eee)); 1383 1384 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1385 1386 qed_ptt_release(hwfn, ptt); 1387 1388 return rc; 1389 } 1390 1391 static int qed_get_port_type(u32 media_type) 1392 { 1393 int port_type; 1394 1395 switch (media_type) { 1396 case MEDIA_SFPP_10G_FIBER: 1397 case MEDIA_SFP_1G_FIBER: 1398 case MEDIA_XFP_FIBER: 1399 case MEDIA_MODULE_FIBER: 1400 case MEDIA_KR: 1401 port_type = PORT_FIBRE; 1402 break; 1403 case MEDIA_DA_TWINAX: 1404 port_type = PORT_DA; 1405 break; 1406 case MEDIA_BASE_T: 1407 port_type = PORT_TP; 1408 break; 1409 case MEDIA_NOT_PRESENT: 1410 port_type = PORT_NONE; 1411 break; 1412 case MEDIA_UNSPECIFIED: 1413 default: 1414 port_type = PORT_OTHER; 1415 break; 1416 } 1417 return port_type; 1418 } 1419 1420 static int qed_get_link_data(struct qed_hwfn *hwfn, 1421 struct qed_mcp_link_params *params, 1422 struct qed_mcp_link_state *link, 1423 struct qed_mcp_link_capabilities *link_caps) 1424 { 1425 void *p; 1426 1427 if (!IS_PF(hwfn->cdev)) { 1428 qed_vf_get_link_params(hwfn, params); 1429 qed_vf_get_link_state(hwfn, link); 1430 qed_vf_get_link_caps(hwfn, link_caps); 1431 1432 return 0; 1433 } 1434 1435 p = qed_mcp_get_link_params(hwfn); 1436 if (!p) 1437 return -ENXIO; 1438 memcpy(params, p, sizeof(*params)); 1439 1440 p = qed_mcp_get_link_state(hwfn); 1441 if (!p) 1442 return -ENXIO; 1443 memcpy(link, p, sizeof(*link)); 1444 1445 p = qed_mcp_get_link_capabilities(hwfn); 1446 if (!p) 1447 return -ENXIO; 1448 memcpy(link_caps, p, sizeof(*link_caps)); 1449 1450 return 0; 1451 } 1452 1453 static void qed_fill_link(struct qed_hwfn *hwfn, 1454 struct qed_link_output *if_link) 1455 { 1456 struct qed_mcp_link_params params; 1457 struct qed_mcp_link_state link; 1458 struct qed_mcp_link_capabilities link_caps; 1459 u32 media_type; 1460 1461 memset(if_link, 0, sizeof(*if_link)); 1462 1463 /* Prepare source inputs */ 1464 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1465 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1466 return; 1467 } 1468 1469 /* Set the link parameters to pass to protocol driver */ 1470 if (link.link_up) 1471 if_link->link_up = true; 1472 1473 /* TODO - at the moment assume supported and advertised speed equal */ 1474 if_link->supported_caps = QED_LM_FIBRE_BIT; 1475 if (link_caps.default_speed_autoneg) 1476 if_link->supported_caps |= QED_LM_Autoneg_BIT; 1477 if (params.pause.autoneg || 1478 (params.pause.forced_rx && params.pause.forced_tx)) 1479 if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1480 if (params.pause.autoneg || params.pause.forced_rx || 1481 params.pause.forced_tx) 1482 if_link->supported_caps |= QED_LM_Pause_BIT; 1483 1484 if_link->advertised_caps = if_link->supported_caps; 1485 if (params.speed.autoneg) 1486 if_link->advertised_caps |= QED_LM_Autoneg_BIT; 1487 else 1488 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT; 1489 if (params.speed.advertised_speeds & 1490 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1491 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1492 QED_LM_1000baseT_Full_BIT; 1493 if (params.speed.advertised_speeds & 1494 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1495 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1496 if (params.speed.advertised_speeds & 1497 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1498 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1499 if (params.speed.advertised_speeds & 1500 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1501 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1502 if (params.speed.advertised_speeds & 1503 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1504 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1505 if (params.speed.advertised_speeds & 1506 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1507 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1508 1509 if (link_caps.speed_capabilities & 1510 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1511 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1512 QED_LM_1000baseT_Full_BIT; 1513 if (link_caps.speed_capabilities & 1514 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1515 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1516 if (link_caps.speed_capabilities & 1517 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1518 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1519 if (link_caps.speed_capabilities & 1520 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1521 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1522 if (link_caps.speed_capabilities & 1523 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1524 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1525 if (link_caps.speed_capabilities & 1526 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1527 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1528 1529 if (link.link_up) 1530 if_link->speed = link.speed; 1531 1532 /* TODO - fill duplex properly */ 1533 if_link->duplex = DUPLEX_FULL; 1534 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1535 if_link->port = qed_get_port_type(media_type); 1536 1537 if_link->autoneg = params.speed.autoneg; 1538 1539 if (params.pause.autoneg) 1540 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1541 if (params.pause.forced_rx) 1542 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1543 if (params.pause.forced_tx) 1544 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1545 1546 /* Link partner capabilities */ 1547 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1548 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1549 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1550 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1551 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1552 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1553 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1554 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1555 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1556 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1557 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1558 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1559 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1560 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1561 1562 if (link.an_complete) 1563 if_link->lp_caps |= QED_LM_Autoneg_BIT; 1564 1565 if (link.partner_adv_pause) 1566 if_link->lp_caps |= QED_LM_Pause_BIT; 1567 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1568 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1569 if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1570 1571 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) { 1572 if_link->eee_supported = false; 1573 } else { 1574 if_link->eee_supported = true; 1575 if_link->eee_active = link.eee_active; 1576 if_link->sup_caps = link_caps.eee_speed_caps; 1577 /* MFW clears adv_caps on eee disable; use configured value */ 1578 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps : 1579 params.eee.adv_caps; 1580 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps; 1581 if_link->eee.enable = params.eee.enable; 1582 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable; 1583 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer; 1584 } 1585 } 1586 1587 static void qed_get_current_link(struct qed_dev *cdev, 1588 struct qed_link_output *if_link) 1589 { 1590 int i; 1591 1592 qed_fill_link(&cdev->hwfns[0], if_link); 1593 1594 for_each_hwfn(cdev, i) 1595 qed_inform_vf_link_state(&cdev->hwfns[i]); 1596 } 1597 1598 void qed_link_update(struct qed_hwfn *hwfn) 1599 { 1600 void *cookie = hwfn->cdev->ops_cookie; 1601 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1602 struct qed_link_output if_link; 1603 1604 qed_fill_link(hwfn, &if_link); 1605 qed_inform_vf_link_state(hwfn); 1606 1607 if (IS_LEAD_HWFN(hwfn) && cookie) 1608 op->link_update(cookie, &if_link); 1609 } 1610 1611 static int qed_drain(struct qed_dev *cdev) 1612 { 1613 struct qed_hwfn *hwfn; 1614 struct qed_ptt *ptt; 1615 int i, rc; 1616 1617 if (IS_VF(cdev)) 1618 return 0; 1619 1620 for_each_hwfn(cdev, i) { 1621 hwfn = &cdev->hwfns[i]; 1622 ptt = qed_ptt_acquire(hwfn); 1623 if (!ptt) { 1624 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1625 return -EBUSY; 1626 } 1627 rc = qed_mcp_drain(hwfn, ptt); 1628 if (rc) 1629 return rc; 1630 qed_ptt_release(hwfn, ptt); 1631 } 1632 1633 return 0; 1634 } 1635 1636 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev, 1637 struct qed_nvm_image_att *nvm_image, 1638 u32 *crc) 1639 { 1640 u8 *buf = NULL; 1641 int rc, j; 1642 u32 val; 1643 1644 /* Allocate a buffer for holding the nvram image */ 1645 buf = kzalloc(nvm_image->length, GFP_KERNEL); 1646 if (!buf) 1647 return -ENOMEM; 1648 1649 /* Read image into buffer */ 1650 rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr, 1651 buf, nvm_image->length); 1652 if (rc) { 1653 DP_ERR(cdev, "Failed reading image from nvm\n"); 1654 goto out; 1655 } 1656 1657 /* Convert the buffer into big-endian format (excluding the 1658 * closing 4 bytes of CRC). 1659 */ 1660 for (j = 0; j < nvm_image->length - 4; j += 4) { 1661 val = cpu_to_be32(*(u32 *)&buf[j]); 1662 *(u32 *)&buf[j] = val; 1663 } 1664 1665 /* Calc CRC for the "actual" image buffer, i.e. not including 1666 * the last 4 CRC bytes. 1667 */ 1668 *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4))); 1669 1670 out: 1671 kfree(buf); 1672 1673 return rc; 1674 } 1675 1676 /* Binary file format - 1677 * /----------------------------------------------------------------------\ 1678 * 0B | 0x4 [command index] | 1679 * 4B | image_type | Options | Number of register settings | 1680 * 8B | Value | 1681 * 12B | Mask | 1682 * 16B | Offset | 1683 * \----------------------------------------------------------------------/ 1684 * There can be several Value-Mask-Offset sets as specified by 'Number of...'. 1685 * Options - 0'b - Calculate & Update CRC for image 1686 */ 1687 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data, 1688 bool *check_resp) 1689 { 1690 struct qed_nvm_image_att nvm_image; 1691 struct qed_hwfn *p_hwfn; 1692 bool is_crc = false; 1693 u32 image_type; 1694 int rc = 0, i; 1695 u16 len; 1696 1697 *data += 4; 1698 image_type = **data; 1699 p_hwfn = QED_LEADING_HWFN(cdev); 1700 for (i = 0; i < p_hwfn->nvm_info.num_images; i++) 1701 if (image_type == p_hwfn->nvm_info.image_att[i].image_type) 1702 break; 1703 if (i == p_hwfn->nvm_info.num_images) { 1704 DP_ERR(cdev, "Failed to find nvram image of type %08x\n", 1705 image_type); 1706 return -ENOENT; 1707 } 1708 1709 nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; 1710 nvm_image.length = p_hwfn->nvm_info.image_att[i].len; 1711 1712 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1713 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n", 1714 **data, image_type, nvm_image.start_addr, 1715 nvm_image.start_addr + nvm_image.length - 1); 1716 (*data)++; 1717 is_crc = !!(**data & BIT(0)); 1718 (*data)++; 1719 len = *((u16 *)*data); 1720 *data += 2; 1721 if (is_crc) { 1722 u32 crc = 0; 1723 1724 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc); 1725 if (rc) { 1726 DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc); 1727 goto exit; 1728 } 1729 1730 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1731 (nvm_image.start_addr + 1732 nvm_image.length - 4), (u8 *)&crc, 4); 1733 if (rc) 1734 DP_ERR(cdev, "Failed writing to %08x, rc = %d\n", 1735 nvm_image.start_addr + nvm_image.length - 4, rc); 1736 goto exit; 1737 } 1738 1739 /* Iterate over the values for setting */ 1740 while (len) { 1741 u32 offset, mask, value, cur_value; 1742 u8 buf[4]; 1743 1744 value = *((u32 *)*data); 1745 *data += 4; 1746 mask = *((u32 *)*data); 1747 *data += 4; 1748 offset = *((u32 *)*data); 1749 *data += 4; 1750 1751 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf, 1752 4); 1753 if (rc) { 1754 DP_ERR(cdev, "Failed reading from %08x\n", 1755 nvm_image.start_addr + offset); 1756 goto exit; 1757 } 1758 1759 cur_value = le32_to_cpu(*((__le32 *)buf)); 1760 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1761 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n", 1762 nvm_image.start_addr + offset, cur_value, 1763 (cur_value & ~mask) | (value & mask), value, mask); 1764 value = (value & mask) | (cur_value & ~mask); 1765 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, 1766 nvm_image.start_addr + offset, 1767 (u8 *)&value, 4); 1768 if (rc) { 1769 DP_ERR(cdev, "Failed writing to %08x\n", 1770 nvm_image.start_addr + offset); 1771 goto exit; 1772 } 1773 1774 len--; 1775 } 1776 exit: 1777 return rc; 1778 } 1779 1780 /* Binary file format - 1781 * /----------------------------------------------------------------------\ 1782 * 0B | 0x3 [command index] | 1783 * 4B | b'0: check_response? | b'1-31 reserved | 1784 * 8B | File-type | reserved | 1785 * \----------------------------------------------------------------------/ 1786 * Start a new file of the provided type 1787 */ 1788 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev, 1789 const u8 **data, bool *check_resp) 1790 { 1791 int rc; 1792 1793 *data += 4; 1794 *check_resp = !!(**data & BIT(0)); 1795 *data += 4; 1796 1797 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1798 "About to start a new file of type %02x\n", **data); 1799 rc = qed_mcp_nvm_put_file_begin(cdev, **data); 1800 *data += 4; 1801 1802 return rc; 1803 } 1804 1805 /* Binary file format - 1806 * /----------------------------------------------------------------------\ 1807 * 0B | 0x2 [command index] | 1808 * 4B | Length in bytes | 1809 * 8B | b'0: check_response? | b'1-31 reserved | 1810 * 12B | Offset in bytes | 1811 * 16B | Data ... | 1812 * \----------------------------------------------------------------------/ 1813 * Write data as part of a file that was previously started. Data should be 1814 * of length equal to that provided in the message 1815 */ 1816 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev, 1817 const u8 **data, bool *check_resp) 1818 { 1819 u32 offset, len; 1820 int rc; 1821 1822 *data += 4; 1823 len = *((u32 *)(*data)); 1824 *data += 4; 1825 *check_resp = !!(**data & BIT(0)); 1826 *data += 4; 1827 offset = *((u32 *)(*data)); 1828 *data += 4; 1829 1830 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1831 "About to write File-data: %08x bytes to offset %08x\n", 1832 len, offset); 1833 1834 rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset, 1835 (char *)(*data), len); 1836 *data += len; 1837 1838 return rc; 1839 } 1840 1841 /* Binary file format [General header] - 1842 * /----------------------------------------------------------------------\ 1843 * 0B | QED_NVM_SIGNATURE | 1844 * 4B | Length in bytes | 1845 * 8B | Highest command in this batchfile | Reserved | 1846 * \----------------------------------------------------------------------/ 1847 */ 1848 static int qed_nvm_flash_image_validate(struct qed_dev *cdev, 1849 const struct firmware *image, 1850 const u8 **data) 1851 { 1852 u32 signature, len; 1853 1854 /* Check minimum size */ 1855 if (image->size < 12) { 1856 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size); 1857 return -EINVAL; 1858 } 1859 1860 /* Check signature */ 1861 signature = *((u32 *)(*data)); 1862 if (signature != QED_NVM_SIGNATURE) { 1863 DP_ERR(cdev, "Wrong signature '%08x'\n", signature); 1864 return -EINVAL; 1865 } 1866 1867 *data += 4; 1868 /* Validate internal size equals the image-size */ 1869 len = *((u32 *)(*data)); 1870 if (len != image->size) { 1871 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n", 1872 len, (u32)image->size); 1873 return -EINVAL; 1874 } 1875 1876 *data += 4; 1877 /* Make sure driver familiar with all commands necessary for this */ 1878 if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) { 1879 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n", 1880 *((u16 *)(*data))); 1881 return -EINVAL; 1882 } 1883 1884 *data += 4; 1885 1886 return 0; 1887 } 1888 1889 static int qed_nvm_flash(struct qed_dev *cdev, const char *name) 1890 { 1891 const struct firmware *image; 1892 const u8 *data, *data_end; 1893 u32 cmd_type; 1894 int rc; 1895 1896 rc = request_firmware(&image, name, &cdev->pdev->dev); 1897 if (rc) { 1898 DP_ERR(cdev, "Failed to find '%s'\n", name); 1899 return rc; 1900 } 1901 1902 DP_VERBOSE(cdev, NETIF_MSG_DRV, 1903 "Flashing '%s' - firmware's data at %p, size is %08x\n", 1904 name, image->data, (u32)image->size); 1905 data = image->data; 1906 data_end = data + image->size; 1907 1908 rc = qed_nvm_flash_image_validate(cdev, image, &data); 1909 if (rc) 1910 goto exit; 1911 1912 while (data < data_end) { 1913 bool check_resp = false; 1914 1915 /* Parse the actual command */ 1916 cmd_type = *((u32 *)data); 1917 switch (cmd_type) { 1918 case QED_NVM_FLASH_CMD_FILE_DATA: 1919 rc = qed_nvm_flash_image_file_data(cdev, &data, 1920 &check_resp); 1921 break; 1922 case QED_NVM_FLASH_CMD_FILE_START: 1923 rc = qed_nvm_flash_image_file_start(cdev, &data, 1924 &check_resp); 1925 break; 1926 case QED_NVM_FLASH_CMD_NVM_CHANGE: 1927 rc = qed_nvm_flash_image_access(cdev, &data, 1928 &check_resp); 1929 break; 1930 default: 1931 DP_ERR(cdev, "Unknown command %08x\n", cmd_type); 1932 rc = -EINVAL; 1933 goto exit; 1934 } 1935 1936 if (rc) { 1937 DP_ERR(cdev, "Command %08x failed\n", cmd_type); 1938 goto exit; 1939 } 1940 1941 /* Check response if needed */ 1942 if (check_resp) { 1943 u32 mcp_response = 0; 1944 1945 if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) { 1946 DP_ERR(cdev, "Failed getting MCP response\n"); 1947 rc = -EINVAL; 1948 goto exit; 1949 } 1950 1951 switch (mcp_response & FW_MSG_CODE_MASK) { 1952 case FW_MSG_CODE_OK: 1953 case FW_MSG_CODE_NVM_OK: 1954 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK: 1955 case FW_MSG_CODE_PHY_OK: 1956 break; 1957 default: 1958 DP_ERR(cdev, "MFW returns error: %08x\n", 1959 mcp_response); 1960 rc = -EINVAL; 1961 goto exit; 1962 } 1963 } 1964 } 1965 1966 exit: 1967 release_firmware(image); 1968 1969 return rc; 1970 } 1971 1972 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, 1973 u8 *buf, u16 len) 1974 { 1975 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1976 1977 return qed_mcp_get_nvm_image(hwfn, type, buf, len); 1978 } 1979 1980 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1981 void *handle) 1982 { 1983 return qed_set_queue_coalesce(rx_coal, tx_coal, handle); 1984 } 1985 1986 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1987 { 1988 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1989 struct qed_ptt *ptt; 1990 int status = 0; 1991 1992 ptt = qed_ptt_acquire(hwfn); 1993 if (!ptt) 1994 return -EAGAIN; 1995 1996 status = qed_mcp_set_led(hwfn, ptt, mode); 1997 1998 qed_ptt_release(hwfn, ptt); 1999 2000 return status; 2001 } 2002 2003 static int qed_update_wol(struct qed_dev *cdev, bool enabled) 2004 { 2005 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2006 struct qed_ptt *ptt; 2007 int rc = 0; 2008 2009 if (IS_VF(cdev)) 2010 return 0; 2011 2012 ptt = qed_ptt_acquire(hwfn); 2013 if (!ptt) 2014 return -EAGAIN; 2015 2016 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED 2017 : QED_OV_WOL_DISABLED); 2018 if (rc) 2019 goto out; 2020 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2021 2022 out: 2023 qed_ptt_release(hwfn, ptt); 2024 return rc; 2025 } 2026 2027 static int qed_update_drv_state(struct qed_dev *cdev, bool active) 2028 { 2029 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2030 struct qed_ptt *ptt; 2031 int status = 0; 2032 2033 if (IS_VF(cdev)) 2034 return 0; 2035 2036 ptt = qed_ptt_acquire(hwfn); 2037 if (!ptt) 2038 return -EAGAIN; 2039 2040 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ? 2041 QED_OV_DRIVER_STATE_ACTIVE : 2042 QED_OV_DRIVER_STATE_DISABLED); 2043 2044 qed_ptt_release(hwfn, ptt); 2045 2046 return status; 2047 } 2048 2049 static int qed_update_mac(struct qed_dev *cdev, u8 *mac) 2050 { 2051 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2052 struct qed_ptt *ptt; 2053 int status = 0; 2054 2055 if (IS_VF(cdev)) 2056 return 0; 2057 2058 ptt = qed_ptt_acquire(hwfn); 2059 if (!ptt) 2060 return -EAGAIN; 2061 2062 status = qed_mcp_ov_update_mac(hwfn, ptt, mac); 2063 if (status) 2064 goto out; 2065 2066 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2067 2068 out: 2069 qed_ptt_release(hwfn, ptt); 2070 return status; 2071 } 2072 2073 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) 2074 { 2075 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 2076 struct qed_ptt *ptt; 2077 int status = 0; 2078 2079 if (IS_VF(cdev)) 2080 return 0; 2081 2082 ptt = qed_ptt_acquire(hwfn); 2083 if (!ptt) 2084 return -EAGAIN; 2085 2086 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu); 2087 if (status) 2088 goto out; 2089 2090 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); 2091 2092 out: 2093 qed_ptt_release(hwfn, ptt); 2094 return status; 2095 } 2096 2097 static struct qed_selftest_ops qed_selftest_ops_pass = { 2098 .selftest_memory = &qed_selftest_memory, 2099 .selftest_interrupt = &qed_selftest_interrupt, 2100 .selftest_register = &qed_selftest_register, 2101 .selftest_clock = &qed_selftest_clock, 2102 .selftest_nvram = &qed_selftest_nvram, 2103 }; 2104 2105 const struct qed_common_ops qed_common_ops_pass = { 2106 .selftest = &qed_selftest_ops_pass, 2107 .probe = &qed_probe, 2108 .remove = &qed_remove, 2109 .set_power_state = &qed_set_power_state, 2110 .set_name = &qed_set_name, 2111 .update_pf_params = &qed_update_pf_params, 2112 .slowpath_start = &qed_slowpath_start, 2113 .slowpath_stop = &qed_slowpath_stop, 2114 .set_fp_int = &qed_set_int_fp, 2115 .get_fp_int = &qed_get_int_fp, 2116 .sb_init = &qed_sb_init, 2117 .sb_release = &qed_sb_release, 2118 .simd_handler_config = &qed_simd_handler_config, 2119 .simd_handler_clean = &qed_simd_handler_clean, 2120 .dbg_grc = &qed_dbg_grc, 2121 .dbg_grc_size = &qed_dbg_grc_size, 2122 .can_link_change = &qed_can_link_change, 2123 .set_link = &qed_set_link, 2124 .get_link = &qed_get_current_link, 2125 .drain = &qed_drain, 2126 .update_msglvl = &qed_init_dp, 2127 .dbg_all_data = &qed_dbg_all_data, 2128 .dbg_all_data_size = &qed_dbg_all_data_size, 2129 .chain_alloc = &qed_chain_alloc, 2130 .chain_free = &qed_chain_free, 2131 .nvm_flash = &qed_nvm_flash, 2132 .nvm_get_image = &qed_nvm_get_image, 2133 .set_coalesce = &qed_set_coalesce, 2134 .set_led = &qed_set_led, 2135 .update_drv_state = &qed_update_drv_state, 2136 .update_mac = &qed_update_mac, 2137 .update_mtu = &qed_update_mtu, 2138 .update_wol = &qed_update_wol, 2139 }; 2140 2141 void qed_get_protocol_stats(struct qed_dev *cdev, 2142 enum qed_mcp_protocol_type type, 2143 union qed_mcp_protocol_stats *stats) 2144 { 2145 struct qed_eth_stats eth_stats; 2146 2147 memset(stats, 0, sizeof(*stats)); 2148 2149 switch (type) { 2150 case QED_MCP_LAN_STATS: 2151 qed_get_vport_stats(cdev, ð_stats); 2152 stats->lan_stats.ucast_rx_pkts = 2153 eth_stats.common.rx_ucast_pkts; 2154 stats->lan_stats.ucast_tx_pkts = 2155 eth_stats.common.tx_ucast_pkts; 2156 stats->lan_stats.fcs_err = -1; 2157 break; 2158 case QED_MCP_FCOE_STATS: 2159 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats); 2160 break; 2161 case QED_MCP_ISCSI_STATS: 2162 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats); 2163 break; 2164 default: 2165 DP_VERBOSE(cdev, QED_MSG_SP, 2166 "Invalid protocol type = %d\n", type); 2167 return; 2168 } 2169 } 2170 2171 int qed_mfw_tlv_req(struct qed_hwfn *hwfn) 2172 { 2173 DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV, 2174 "Scheduling slowpath task [Flag: %d]\n", 2175 QED_SLOWPATH_MFW_TLV_REQ); 2176 smp_mb__before_atomic(); 2177 set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags); 2178 smp_mb__after_atomic(); 2179 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); 2180 2181 return 0; 2182 } 2183 2184 static void 2185 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv) 2186 { 2187 struct qed_common_cb_ops *op = cdev->protocol_ops.common; 2188 struct qed_eth_stats_common *p_common; 2189 struct qed_generic_tlvs gen_tlvs; 2190 struct qed_eth_stats stats; 2191 int i; 2192 2193 memset(&gen_tlvs, 0, sizeof(gen_tlvs)); 2194 op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs); 2195 2196 if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM) 2197 tlv->flags.ipv4_csum_offload = true; 2198 if (gen_tlvs.feat_flags & QED_TLV_LSO) 2199 tlv->flags.lso_supported = true; 2200 tlv->flags.b_set = true; 2201 2202 for (i = 0; i < QED_TLV_MAC_COUNT; i++) { 2203 if (is_valid_ether_addr(gen_tlvs.mac[i])) { 2204 ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]); 2205 tlv->mac_set[i] = true; 2206 } 2207 } 2208 2209 qed_get_vport_stats(cdev, &stats); 2210 p_common = &stats.common; 2211 tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts + 2212 p_common->rx_bcast_pkts; 2213 tlv->rx_frames_set = true; 2214 tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes + 2215 p_common->rx_bcast_bytes; 2216 tlv->rx_bytes_set = true; 2217 tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts + 2218 p_common->tx_bcast_pkts; 2219 tlv->tx_frames_set = true; 2220 tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes + 2221 p_common->tx_bcast_bytes; 2222 tlv->rx_bytes_set = true; 2223 } 2224 2225 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type, 2226 union qed_mfw_tlv_data *tlv_buf) 2227 { 2228 struct qed_dev *cdev = hwfn->cdev; 2229 struct qed_common_cb_ops *ops; 2230 2231 ops = cdev->protocol_ops.common; 2232 if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) { 2233 DP_NOTICE(hwfn, "Can't collect TLV management info\n"); 2234 return -EINVAL; 2235 } 2236 2237 switch (type) { 2238 case QED_MFW_TLV_GENERIC: 2239 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic); 2240 break; 2241 case QED_MFW_TLV_ETH: 2242 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth); 2243 break; 2244 case QED_MFW_TLV_FCOE: 2245 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe); 2246 break; 2247 case QED_MFW_TLV_ISCSI: 2248 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi); 2249 break; 2250 default: 2251 break; 2252 } 2253 2254 return 0; 2255 } 2256