1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/stddef.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/version.h> 14 #include <linux/delay.h> 15 #include <asm/byteorder.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/string.h> 18 #include <linux/module.h> 19 #include <linux/interrupt.h> 20 #include <linux/workqueue.h> 21 #include <linux/ethtool.h> 22 #include <linux/etherdevice.h> 23 #include <linux/vmalloc.h> 24 #include <linux/qed/qed_if.h> 25 26 #include "qed.h" 27 #include "qed_sriov.h" 28 #include "qed_sp.h" 29 #include "qed_dev_api.h" 30 #include "qed_mcp.h" 31 #include "qed_hw.h" 32 #include "qed_selftest.h" 33 34 static char version[] = 35 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 36 37 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 38 MODULE_LICENSE("GPL"); 39 MODULE_VERSION(DRV_MODULE_VERSION); 40 41 #define FW_FILE_VERSION \ 42 __stringify(FW_MAJOR_VERSION) "." \ 43 __stringify(FW_MINOR_VERSION) "." \ 44 __stringify(FW_REVISION_VERSION) "." \ 45 __stringify(FW_ENGINEERING_VERSION) 46 47 #define QED_FW_FILE_NAME \ 48 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 49 50 MODULE_FIRMWARE(QED_FW_FILE_NAME); 51 52 static int __init qed_init(void) 53 { 54 pr_notice("qed_init called\n"); 55 56 pr_info("%s", version); 57 58 return 0; 59 } 60 61 static void __exit qed_cleanup(void) 62 { 63 pr_notice("qed_cleanup called\n"); 64 } 65 66 module_init(qed_init); 67 module_exit(qed_cleanup); 68 69 /* Check if the DMA controller on the machine can properly handle the DMA 70 * addressing required by the device. 71 */ 72 static int qed_set_coherency_mask(struct qed_dev *cdev) 73 { 74 struct device *dev = &cdev->pdev->dev; 75 76 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 77 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 78 DP_NOTICE(cdev, 79 "Can't request 64-bit consistent allocations\n"); 80 return -EIO; 81 } 82 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 83 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 84 return -EIO; 85 } 86 87 return 0; 88 } 89 90 static void qed_free_pci(struct qed_dev *cdev) 91 { 92 struct pci_dev *pdev = cdev->pdev; 93 94 if (cdev->doorbells) 95 iounmap(cdev->doorbells); 96 if (cdev->regview) 97 iounmap(cdev->regview); 98 if (atomic_read(&pdev->enable_cnt) == 1) 99 pci_release_regions(pdev); 100 101 pci_disable_device(pdev); 102 } 103 104 #define PCI_REVISION_ID_ERROR_VAL 0xff 105 106 /* Performs PCI initializations as well as initializing PCI-related parameters 107 * in the device structrue. Returns 0 in case of success. 108 */ 109 static int qed_init_pci(struct qed_dev *cdev, 110 struct pci_dev *pdev) 111 { 112 u8 rev_id; 113 int rc; 114 115 cdev->pdev = pdev; 116 117 rc = pci_enable_device(pdev); 118 if (rc) { 119 DP_NOTICE(cdev, "Cannot enable PCI device\n"); 120 goto err0; 121 } 122 123 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 124 DP_NOTICE(cdev, "No memory region found in bar #0\n"); 125 rc = -EIO; 126 goto err1; 127 } 128 129 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 130 DP_NOTICE(cdev, "No memory region found in bar #2\n"); 131 rc = -EIO; 132 goto err1; 133 } 134 135 if (atomic_read(&pdev->enable_cnt) == 1) { 136 rc = pci_request_regions(pdev, "qed"); 137 if (rc) { 138 DP_NOTICE(cdev, 139 "Failed to request PCI memory resources\n"); 140 goto err1; 141 } 142 pci_set_master(pdev); 143 pci_save_state(pdev); 144 } 145 146 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 147 if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 148 DP_NOTICE(cdev, 149 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 150 rev_id); 151 rc = -ENODEV; 152 goto err2; 153 } 154 if (!pci_is_pcie(pdev)) { 155 DP_NOTICE(cdev, "The bus is not PCI Express\n"); 156 rc = -EIO; 157 goto err2; 158 } 159 160 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 161 if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 162 DP_NOTICE(cdev, "Cannot find power management capability\n"); 163 164 rc = qed_set_coherency_mask(cdev); 165 if (rc) 166 goto err2; 167 168 cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 169 cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 170 cdev->pci_params.irq = pdev->irq; 171 172 cdev->regview = pci_ioremap_bar(pdev, 0); 173 if (!cdev->regview) { 174 DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 175 rc = -ENOMEM; 176 goto err2; 177 } 178 179 if (IS_PF(cdev)) { 180 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 181 cdev->db_size = pci_resource_len(cdev->pdev, 2); 182 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 183 if (!cdev->doorbells) { 184 DP_NOTICE(cdev, "Cannot map doorbell space\n"); 185 return -ENOMEM; 186 } 187 } 188 189 return 0; 190 191 err2: 192 pci_release_regions(pdev); 193 err1: 194 pci_disable_device(pdev); 195 err0: 196 return rc; 197 } 198 199 int qed_fill_dev_info(struct qed_dev *cdev, 200 struct qed_dev_info *dev_info) 201 { 202 struct qed_ptt *ptt; 203 204 memset(dev_info, 0, sizeof(struct qed_dev_info)); 205 206 dev_info->num_hwfns = cdev->num_hwfns; 207 dev_info->pci_mem_start = cdev->pci_params.mem_start; 208 dev_info->pci_mem_end = cdev->pci_params.mem_end; 209 dev_info->pci_irq = cdev->pci_params.irq; 210 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]); 211 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr); 212 213 if (IS_PF(cdev)) { 214 dev_info->fw_major = FW_MAJOR_VERSION; 215 dev_info->fw_minor = FW_MINOR_VERSION; 216 dev_info->fw_rev = FW_REVISION_VERSION; 217 dev_info->fw_eng = FW_ENGINEERING_VERSION; 218 dev_info->mf_mode = cdev->mf_mode; 219 dev_info->tx_switching = true; 220 } else { 221 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 222 &dev_info->fw_minor, &dev_info->fw_rev, 223 &dev_info->fw_eng); 224 } 225 226 if (IS_PF(cdev)) { 227 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 228 if (ptt) { 229 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 230 &dev_info->mfw_rev, NULL); 231 232 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 233 &dev_info->flash_size); 234 235 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 236 } 237 } else { 238 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 239 &dev_info->mfw_rev, NULL); 240 } 241 242 return 0; 243 } 244 245 static void qed_free_cdev(struct qed_dev *cdev) 246 { 247 kfree((void *)cdev); 248 } 249 250 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 251 { 252 struct qed_dev *cdev; 253 254 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 255 if (!cdev) 256 return cdev; 257 258 qed_init_struct(cdev); 259 260 return cdev; 261 } 262 263 /* Sets the requested power state */ 264 static int qed_set_power_state(struct qed_dev *cdev, 265 pci_power_t state) 266 { 267 if (!cdev) 268 return -ENODEV; 269 270 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 271 return 0; 272 } 273 274 /* probing */ 275 static struct qed_dev *qed_probe(struct pci_dev *pdev, 276 struct qed_probe_params *params) 277 { 278 struct qed_dev *cdev; 279 int rc; 280 281 cdev = qed_alloc_cdev(pdev); 282 if (!cdev) 283 goto err0; 284 285 cdev->protocol = params->protocol; 286 287 if (params->is_vf) 288 cdev->b_is_vf = true; 289 290 qed_init_dp(cdev, params->dp_module, params->dp_level); 291 292 rc = qed_init_pci(cdev, pdev); 293 if (rc) { 294 DP_ERR(cdev, "init pci failed\n"); 295 goto err1; 296 } 297 DP_INFO(cdev, "PCI init completed successfully\n"); 298 299 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 300 if (rc) { 301 DP_ERR(cdev, "hw prepare failed\n"); 302 goto err2; 303 } 304 305 DP_INFO(cdev, "qed_probe completed successffuly\n"); 306 307 return cdev; 308 309 err2: 310 qed_free_pci(cdev); 311 err1: 312 qed_free_cdev(cdev); 313 err0: 314 return NULL; 315 } 316 317 static void qed_remove(struct qed_dev *cdev) 318 { 319 if (!cdev) 320 return; 321 322 qed_hw_remove(cdev); 323 324 qed_free_pci(cdev); 325 326 qed_set_power_state(cdev, PCI_D3hot); 327 328 qed_free_cdev(cdev); 329 } 330 331 static void qed_disable_msix(struct qed_dev *cdev) 332 { 333 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 334 pci_disable_msix(cdev->pdev); 335 kfree(cdev->int_params.msix_table); 336 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 337 pci_disable_msi(cdev->pdev); 338 } 339 340 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 341 } 342 343 static int qed_enable_msix(struct qed_dev *cdev, 344 struct qed_int_params *int_params) 345 { 346 int i, rc, cnt; 347 348 cnt = int_params->in.num_vectors; 349 350 for (i = 0; i < cnt; i++) 351 int_params->msix_table[i].entry = i; 352 353 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 354 int_params->in.min_msix_cnt, cnt); 355 if (rc < cnt && rc >= int_params->in.min_msix_cnt && 356 (rc % cdev->num_hwfns)) { 357 pci_disable_msix(cdev->pdev); 358 359 /* If fastpath is initialized, we need at least one interrupt 360 * per hwfn [and the slow path interrupts]. New requested number 361 * should be a multiple of the number of hwfns. 362 */ 363 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 364 DP_NOTICE(cdev, 365 "Trying to enable MSI-X with less vectors (%d out of %d)\n", 366 cnt, int_params->in.num_vectors); 367 rc = pci_enable_msix_exact(cdev->pdev, 368 int_params->msix_table, cnt); 369 if (!rc) 370 rc = cnt; 371 } 372 373 if (rc > 0) { 374 /* MSI-x configuration was achieved */ 375 int_params->out.int_mode = QED_INT_MODE_MSIX; 376 int_params->out.num_vectors = rc; 377 rc = 0; 378 } else { 379 DP_NOTICE(cdev, 380 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 381 cnt, rc); 382 } 383 384 return rc; 385 } 386 387 /* This function outputs the int mode and the number of enabled msix vector */ 388 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 389 { 390 struct qed_int_params *int_params = &cdev->int_params; 391 struct msix_entry *tbl; 392 int rc = 0, cnt; 393 394 switch (int_params->in.int_mode) { 395 case QED_INT_MODE_MSIX: 396 /* Allocate MSIX table */ 397 cnt = int_params->in.num_vectors; 398 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 399 if (!int_params->msix_table) { 400 rc = -ENOMEM; 401 goto out; 402 } 403 404 /* Enable MSIX */ 405 rc = qed_enable_msix(cdev, int_params); 406 if (!rc) 407 goto out; 408 409 DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 410 kfree(int_params->msix_table); 411 if (force_mode) 412 goto out; 413 /* Fallthrough */ 414 415 case QED_INT_MODE_MSI: 416 if (cdev->num_hwfns == 1) { 417 rc = pci_enable_msi(cdev->pdev); 418 if (!rc) { 419 int_params->out.int_mode = QED_INT_MODE_MSI; 420 goto out; 421 } 422 423 DP_NOTICE(cdev, "Failed to enable MSI\n"); 424 if (force_mode) 425 goto out; 426 } 427 /* Fallthrough */ 428 429 case QED_INT_MODE_INTA: 430 int_params->out.int_mode = QED_INT_MODE_INTA; 431 rc = 0; 432 goto out; 433 default: 434 DP_NOTICE(cdev, "Unknown int_mode value %d\n", 435 int_params->in.int_mode); 436 rc = -EINVAL; 437 } 438 439 out: 440 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 441 442 return rc; 443 } 444 445 static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 446 int index, void(*handler)(void *)) 447 { 448 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 449 int relative_idx = index / cdev->num_hwfns; 450 451 hwfn->simd_proto_handler[relative_idx].func = handler; 452 hwfn->simd_proto_handler[relative_idx].token = token; 453 } 454 455 static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 456 { 457 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 458 int relative_idx = index / cdev->num_hwfns; 459 460 memset(&hwfn->simd_proto_handler[relative_idx], 0, 461 sizeof(struct qed_simd_fp_handler)); 462 } 463 464 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 465 { 466 tasklet_schedule((struct tasklet_struct *)tasklet); 467 return IRQ_HANDLED; 468 } 469 470 static irqreturn_t qed_single_int(int irq, void *dev_instance) 471 { 472 struct qed_dev *cdev = (struct qed_dev *)dev_instance; 473 struct qed_hwfn *hwfn; 474 irqreturn_t rc = IRQ_NONE; 475 u64 status; 476 int i, j; 477 478 for (i = 0; i < cdev->num_hwfns; i++) { 479 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 480 481 if (!status) 482 continue; 483 484 hwfn = &cdev->hwfns[i]; 485 486 /* Slowpath interrupt */ 487 if (unlikely(status & 0x1)) { 488 tasklet_schedule(hwfn->sp_dpc); 489 status &= ~0x1; 490 rc = IRQ_HANDLED; 491 } 492 493 /* Fastpath interrupts */ 494 for (j = 0; j < 64; j++) { 495 if ((0x2ULL << j) & status) { 496 hwfn->simd_proto_handler[j].func( 497 hwfn->simd_proto_handler[j].token); 498 status &= ~(0x2ULL << j); 499 rc = IRQ_HANDLED; 500 } 501 } 502 503 if (unlikely(status)) 504 DP_VERBOSE(hwfn, NETIF_MSG_INTR, 505 "got an unknown interrupt status 0x%llx\n", 506 status); 507 } 508 509 return rc; 510 } 511 512 int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 513 { 514 struct qed_dev *cdev = hwfn->cdev; 515 int rc = 0; 516 u8 id; 517 518 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 519 id = hwfn->my_id; 520 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 521 id, cdev->pdev->bus->number, 522 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 523 rc = request_irq(cdev->int_params.msix_table[id].vector, 524 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 525 if (!rc) 526 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 527 "Requested slowpath MSI-X\n"); 528 } else { 529 unsigned long flags = 0; 530 531 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 532 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 533 PCI_FUNC(cdev->pdev->devfn)); 534 535 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 536 flags |= IRQF_SHARED; 537 538 rc = request_irq(cdev->pdev->irq, qed_single_int, 539 flags, cdev->name, cdev); 540 } 541 542 return rc; 543 } 544 545 static void qed_slowpath_irq_free(struct qed_dev *cdev) 546 { 547 int i; 548 549 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 550 for_each_hwfn(cdev, i) { 551 if (!cdev->hwfns[i].b_int_requested) 552 break; 553 synchronize_irq(cdev->int_params.msix_table[i].vector); 554 free_irq(cdev->int_params.msix_table[i].vector, 555 cdev->hwfns[i].sp_dpc); 556 } 557 } else { 558 if (QED_LEADING_HWFN(cdev)->b_int_requested) 559 free_irq(cdev->pdev->irq, cdev); 560 } 561 qed_int_disable_post_isr_release(cdev); 562 } 563 564 static int qed_nic_stop(struct qed_dev *cdev) 565 { 566 int i, rc; 567 568 rc = qed_hw_stop(cdev); 569 570 for (i = 0; i < cdev->num_hwfns; i++) { 571 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 572 573 if (p_hwfn->b_sp_dpc_enabled) { 574 tasklet_disable(p_hwfn->sp_dpc); 575 p_hwfn->b_sp_dpc_enabled = false; 576 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 577 "Disabled sp taskelt [hwfn %d] at %p\n", 578 i, p_hwfn->sp_dpc); 579 } 580 } 581 582 return rc; 583 } 584 585 static int qed_nic_reset(struct qed_dev *cdev) 586 { 587 int rc; 588 589 rc = qed_hw_reset(cdev); 590 if (rc) 591 return rc; 592 593 qed_resc_free(cdev); 594 595 return 0; 596 } 597 598 static int qed_nic_setup(struct qed_dev *cdev) 599 { 600 int rc; 601 602 rc = qed_resc_alloc(cdev); 603 if (rc) 604 return rc; 605 606 DP_INFO(cdev, "Allocated qed resources\n"); 607 608 qed_resc_setup(cdev); 609 610 return rc; 611 } 612 613 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 614 { 615 int limit = 0; 616 617 /* Mark the fastpath as free/used */ 618 cdev->int_params.fp_initialized = cnt ? true : false; 619 620 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 621 limit = cdev->num_hwfns * 63; 622 else if (cdev->int_params.fp_msix_cnt) 623 limit = cdev->int_params.fp_msix_cnt; 624 625 if (!limit) 626 return -ENOMEM; 627 628 return min_t(int, cnt, limit); 629 } 630 631 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 632 { 633 memset(info, 0, sizeof(struct qed_int_info)); 634 635 if (!cdev->int_params.fp_initialized) { 636 DP_INFO(cdev, 637 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 638 return -EINVAL; 639 } 640 641 /* Need to expose only MSI-X information; Single IRQ is handled solely 642 * by qed. 643 */ 644 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 645 int msix_base = cdev->int_params.fp_msix_base; 646 647 info->msix_cnt = cdev->int_params.fp_msix_cnt; 648 info->msix = &cdev->int_params.msix_table[msix_base]; 649 } 650 651 return 0; 652 } 653 654 static int qed_slowpath_setup_int(struct qed_dev *cdev, 655 enum qed_int_mode int_mode) 656 { 657 struct qed_sb_cnt_info sb_cnt_info; 658 int rc; 659 int i; 660 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 661 662 cdev->int_params.in.int_mode = int_mode; 663 for_each_hwfn(cdev, i) { 664 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 665 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 666 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt; 667 cdev->int_params.in.num_vectors++; /* slowpath */ 668 } 669 670 /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 671 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 672 673 rc = qed_set_int_mode(cdev, false); 674 if (rc) { 675 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 676 return rc; 677 } 678 679 cdev->int_params.fp_msix_base = cdev->num_hwfns; 680 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 681 cdev->num_hwfns; 682 683 return 0; 684 } 685 686 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 687 { 688 int rc; 689 690 memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 691 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 692 693 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 694 &cdev->int_params.in.num_vectors); 695 if (cdev->num_hwfns > 1) { 696 u8 vectors = 0; 697 698 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 699 cdev->int_params.in.num_vectors += vectors; 700 } 701 702 /* We want a minimum of one fastpath vector per vf hwfn */ 703 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 704 705 rc = qed_set_int_mode(cdev, true); 706 if (rc) 707 return rc; 708 709 cdev->int_params.fp_msix_base = 0; 710 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 711 712 return 0; 713 } 714 715 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 716 u8 *input_buf, u32 max_size, u8 *unzip_buf) 717 { 718 int rc; 719 720 p_hwfn->stream->next_in = input_buf; 721 p_hwfn->stream->avail_in = input_len; 722 p_hwfn->stream->next_out = unzip_buf; 723 p_hwfn->stream->avail_out = max_size; 724 725 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 726 727 if (rc != Z_OK) { 728 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 729 rc); 730 return 0; 731 } 732 733 rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 734 zlib_inflateEnd(p_hwfn->stream); 735 736 if (rc != Z_OK && rc != Z_STREAM_END) { 737 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 738 p_hwfn->stream->msg, rc); 739 return 0; 740 } 741 742 return p_hwfn->stream->total_out / 4; 743 } 744 745 static int qed_alloc_stream_mem(struct qed_dev *cdev) 746 { 747 int i; 748 void *workspace; 749 750 for_each_hwfn(cdev, i) { 751 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 752 753 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 754 if (!p_hwfn->stream) 755 return -ENOMEM; 756 757 workspace = vzalloc(zlib_inflate_workspacesize()); 758 if (!workspace) 759 return -ENOMEM; 760 p_hwfn->stream->workspace = workspace; 761 } 762 763 return 0; 764 } 765 766 static void qed_free_stream_mem(struct qed_dev *cdev) 767 { 768 int i; 769 770 for_each_hwfn(cdev, i) { 771 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 772 773 if (!p_hwfn->stream) 774 return; 775 776 vfree(p_hwfn->stream->workspace); 777 kfree(p_hwfn->stream); 778 } 779 } 780 781 static void qed_update_pf_params(struct qed_dev *cdev, 782 struct qed_pf_params *params) 783 { 784 int i; 785 786 for (i = 0; i < cdev->num_hwfns; i++) { 787 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 788 789 p_hwfn->pf_params = *params; 790 } 791 } 792 793 static int qed_slowpath_start(struct qed_dev *cdev, 794 struct qed_slowpath_params *params) 795 { 796 struct qed_tunn_start_params tunn_info; 797 struct qed_mcp_drv_version drv_version; 798 const u8 *data = NULL; 799 struct qed_hwfn *hwfn; 800 int rc = -EINVAL; 801 802 if (qed_iov_wq_start(cdev)) 803 goto err; 804 805 if (IS_PF(cdev)) { 806 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 807 &cdev->pdev->dev); 808 if (rc) { 809 DP_NOTICE(cdev, 810 "Failed to find fw file - /lib/firmware/%s\n", 811 QED_FW_FILE_NAME); 812 goto err; 813 } 814 } 815 816 rc = qed_nic_setup(cdev); 817 if (rc) 818 goto err; 819 820 if (IS_PF(cdev)) 821 rc = qed_slowpath_setup_int(cdev, params->int_mode); 822 else 823 rc = qed_slowpath_vf_setup_int(cdev); 824 if (rc) 825 goto err1; 826 827 if (IS_PF(cdev)) { 828 /* Allocate stream for unzipping */ 829 rc = qed_alloc_stream_mem(cdev); 830 if (rc) { 831 DP_NOTICE(cdev, "Failed to allocate stream memory\n"); 832 goto err2; 833 } 834 835 data = cdev->firmware->data; 836 } 837 838 memset(&tunn_info, 0, sizeof(tunn_info)); 839 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN | 840 1 << QED_MODE_L2GRE_TUNN | 841 1 << QED_MODE_IPGRE_TUNN | 842 1 << QED_MODE_L2GENEVE_TUNN | 843 1 << QED_MODE_IPGENEVE_TUNN; 844 845 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN; 846 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN; 847 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN; 848 849 /* Start the slowpath */ 850 rc = qed_hw_init(cdev, &tunn_info, true, 851 cdev->int_params.out.int_mode, 852 true, data); 853 if (rc) 854 goto err2; 855 856 DP_INFO(cdev, 857 "HW initialization and function start completed successfully\n"); 858 859 if (IS_PF(cdev)) { 860 hwfn = QED_LEADING_HWFN(cdev); 861 drv_version.version = (params->drv_major << 24) | 862 (params->drv_minor << 16) | 863 (params->drv_rev << 8) | 864 (params->drv_eng); 865 strlcpy(drv_version.name, params->name, 866 MCP_DRV_VER_STR_SIZE - 4); 867 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 868 &drv_version); 869 if (rc) { 870 DP_NOTICE(cdev, "Failed sending drv version command\n"); 871 return rc; 872 } 873 } 874 875 qed_reset_vport_stats(cdev); 876 877 return 0; 878 879 err2: 880 qed_hw_timers_stop_all(cdev); 881 if (IS_PF(cdev)) 882 qed_slowpath_irq_free(cdev); 883 qed_free_stream_mem(cdev); 884 qed_disable_msix(cdev); 885 err1: 886 qed_resc_free(cdev); 887 err: 888 if (IS_PF(cdev)) 889 release_firmware(cdev->firmware); 890 891 qed_iov_wq_stop(cdev, false); 892 893 return rc; 894 } 895 896 static int qed_slowpath_stop(struct qed_dev *cdev) 897 { 898 if (!cdev) 899 return -ENODEV; 900 901 if (IS_PF(cdev)) { 902 qed_free_stream_mem(cdev); 903 qed_sriov_disable(cdev, true); 904 905 qed_nic_stop(cdev); 906 qed_slowpath_irq_free(cdev); 907 } 908 909 qed_disable_msix(cdev); 910 qed_nic_reset(cdev); 911 912 qed_iov_wq_stop(cdev, true); 913 914 if (IS_PF(cdev)) 915 release_firmware(cdev->firmware); 916 917 return 0; 918 } 919 920 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE], 921 char ver_str[VER_SIZE]) 922 { 923 int i; 924 925 memcpy(cdev->name, name, NAME_SIZE); 926 for_each_hwfn(cdev, i) 927 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 928 929 memcpy(cdev->ver_str, ver_str, VER_SIZE); 930 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 931 } 932 933 static u32 qed_sb_init(struct qed_dev *cdev, 934 struct qed_sb_info *sb_info, 935 void *sb_virt_addr, 936 dma_addr_t sb_phy_addr, u16 sb_id, 937 enum qed_sb_type type) 938 { 939 struct qed_hwfn *p_hwfn; 940 int hwfn_index; 941 u16 rel_sb_id; 942 u8 n_hwfns; 943 u32 rc; 944 945 /* RoCE uses single engine and CMT uses two engines. When using both 946 * we force only a single engine. Storage uses only engine 0 too. 947 */ 948 if (type == QED_SB_TYPE_L2_QUEUE) 949 n_hwfns = cdev->num_hwfns; 950 else 951 n_hwfns = 1; 952 953 hwfn_index = sb_id % n_hwfns; 954 p_hwfn = &cdev->hwfns[hwfn_index]; 955 rel_sb_id = sb_id / n_hwfns; 956 957 DP_VERBOSE(cdev, NETIF_MSG_INTR, 958 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 959 hwfn_index, rel_sb_id, sb_id); 960 961 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 962 sb_virt_addr, sb_phy_addr, rel_sb_id); 963 964 return rc; 965 } 966 967 static u32 qed_sb_release(struct qed_dev *cdev, 968 struct qed_sb_info *sb_info, 969 u16 sb_id) 970 { 971 struct qed_hwfn *p_hwfn; 972 int hwfn_index; 973 u16 rel_sb_id; 974 u32 rc; 975 976 hwfn_index = sb_id % cdev->num_hwfns; 977 p_hwfn = &cdev->hwfns[hwfn_index]; 978 rel_sb_id = sb_id / cdev->num_hwfns; 979 980 DP_VERBOSE(cdev, NETIF_MSG_INTR, 981 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 982 hwfn_index, rel_sb_id, sb_id); 983 984 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 985 986 return rc; 987 } 988 989 static bool qed_can_link_change(struct qed_dev *cdev) 990 { 991 return true; 992 } 993 994 static int qed_set_link(struct qed_dev *cdev, 995 struct qed_link_params *params) 996 { 997 struct qed_hwfn *hwfn; 998 struct qed_mcp_link_params *link_params; 999 struct qed_ptt *ptt; 1000 int rc; 1001 1002 if (!cdev) 1003 return -ENODEV; 1004 1005 if (IS_VF(cdev)) 1006 return 0; 1007 1008 /* The link should be set only once per PF */ 1009 hwfn = &cdev->hwfns[0]; 1010 1011 ptt = qed_ptt_acquire(hwfn); 1012 if (!ptt) 1013 return -EBUSY; 1014 1015 link_params = qed_mcp_get_link_params(hwfn); 1016 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1017 link_params->speed.autoneg = params->autoneg; 1018 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1019 link_params->speed.advertised_speeds = 0; 1020 if ((params->adv_speeds & SUPPORTED_1000baseT_Half) || 1021 (params->adv_speeds & SUPPORTED_1000baseT_Full)) 1022 link_params->speed.advertised_speeds |= 1023 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1024 if (params->adv_speeds & SUPPORTED_10000baseKR_Full) 1025 link_params->speed.advertised_speeds |= 1026 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1027 if (params->adv_speeds & SUPPORTED_40000baseLR4_Full) 1028 link_params->speed.advertised_speeds |= 1029 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1030 if (params->adv_speeds & 0) 1031 link_params->speed.advertised_speeds |= 1032 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1033 if (params->adv_speeds & 0) 1034 link_params->speed.advertised_speeds |= 1035 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G; 1036 } 1037 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1038 link_params->speed.forced_speed = params->forced_speed; 1039 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1040 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1041 link_params->pause.autoneg = true; 1042 else 1043 link_params->pause.autoneg = false; 1044 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1045 link_params->pause.forced_rx = true; 1046 else 1047 link_params->pause.forced_rx = false; 1048 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1049 link_params->pause.forced_tx = true; 1050 else 1051 link_params->pause.forced_tx = false; 1052 } 1053 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 1054 switch (params->loopback_mode) { 1055 case QED_LINK_LOOPBACK_INT_PHY: 1056 link_params->loopback_mode = PMM_LOOPBACK_INT_PHY; 1057 break; 1058 case QED_LINK_LOOPBACK_EXT_PHY: 1059 link_params->loopback_mode = PMM_LOOPBACK_EXT_PHY; 1060 break; 1061 case QED_LINK_LOOPBACK_EXT: 1062 link_params->loopback_mode = PMM_LOOPBACK_EXT; 1063 break; 1064 case QED_LINK_LOOPBACK_MAC: 1065 link_params->loopback_mode = PMM_LOOPBACK_MAC; 1066 break; 1067 default: 1068 link_params->loopback_mode = PMM_LOOPBACK_NONE; 1069 break; 1070 } 1071 } 1072 1073 rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1074 1075 qed_ptt_release(hwfn, ptt); 1076 1077 return rc; 1078 } 1079 1080 static int qed_get_port_type(u32 media_type) 1081 { 1082 int port_type; 1083 1084 switch (media_type) { 1085 case MEDIA_SFPP_10G_FIBER: 1086 case MEDIA_SFP_1G_FIBER: 1087 case MEDIA_XFP_FIBER: 1088 case MEDIA_MODULE_FIBER: 1089 case MEDIA_KR: 1090 port_type = PORT_FIBRE; 1091 break; 1092 case MEDIA_DA_TWINAX: 1093 port_type = PORT_DA; 1094 break; 1095 case MEDIA_BASE_T: 1096 port_type = PORT_TP; 1097 break; 1098 case MEDIA_NOT_PRESENT: 1099 port_type = PORT_NONE; 1100 break; 1101 case MEDIA_UNSPECIFIED: 1102 default: 1103 port_type = PORT_OTHER; 1104 break; 1105 } 1106 return port_type; 1107 } 1108 1109 static int qed_get_link_data(struct qed_hwfn *hwfn, 1110 struct qed_mcp_link_params *params, 1111 struct qed_mcp_link_state *link, 1112 struct qed_mcp_link_capabilities *link_caps) 1113 { 1114 void *p; 1115 1116 if (!IS_PF(hwfn->cdev)) { 1117 qed_vf_get_link_params(hwfn, params); 1118 qed_vf_get_link_state(hwfn, link); 1119 qed_vf_get_link_caps(hwfn, link_caps); 1120 1121 return 0; 1122 } 1123 1124 p = qed_mcp_get_link_params(hwfn); 1125 if (!p) 1126 return -ENXIO; 1127 memcpy(params, p, sizeof(*params)); 1128 1129 p = qed_mcp_get_link_state(hwfn); 1130 if (!p) 1131 return -ENXIO; 1132 memcpy(link, p, sizeof(*link)); 1133 1134 p = qed_mcp_get_link_capabilities(hwfn); 1135 if (!p) 1136 return -ENXIO; 1137 memcpy(link_caps, p, sizeof(*link_caps)); 1138 1139 return 0; 1140 } 1141 1142 static void qed_fill_link(struct qed_hwfn *hwfn, 1143 struct qed_link_output *if_link) 1144 { 1145 struct qed_mcp_link_params params; 1146 struct qed_mcp_link_state link; 1147 struct qed_mcp_link_capabilities link_caps; 1148 u32 media_type; 1149 1150 memset(if_link, 0, sizeof(*if_link)); 1151 1152 /* Prepare source inputs */ 1153 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 1154 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 1155 return; 1156 } 1157 1158 /* Set the link parameters to pass to protocol driver */ 1159 if (link.link_up) 1160 if_link->link_up = true; 1161 1162 /* TODO - at the moment assume supported and advertised speed equal */ 1163 if_link->supported_caps = SUPPORTED_FIBRE; 1164 if (params.speed.autoneg) 1165 if_link->supported_caps |= SUPPORTED_Autoneg; 1166 if (params.pause.autoneg || 1167 (params.pause.forced_rx && params.pause.forced_tx)) 1168 if_link->supported_caps |= SUPPORTED_Asym_Pause; 1169 if (params.pause.autoneg || params.pause.forced_rx || 1170 params.pause.forced_tx) 1171 if_link->supported_caps |= SUPPORTED_Pause; 1172 1173 if_link->advertised_caps = if_link->supported_caps; 1174 if (params.speed.advertised_speeds & 1175 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1176 if_link->advertised_caps |= SUPPORTED_1000baseT_Half | 1177 SUPPORTED_1000baseT_Full; 1178 if (params.speed.advertised_speeds & 1179 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1180 if_link->advertised_caps |= SUPPORTED_10000baseKR_Full; 1181 if (params.speed.advertised_speeds & 1182 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1183 if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full; 1184 if (params.speed.advertised_speeds & 1185 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1186 if_link->advertised_caps |= 0; 1187 if (params.speed.advertised_speeds & 1188 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G) 1189 if_link->advertised_caps |= 0; 1190 1191 if (link_caps.speed_capabilities & 1192 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1193 if_link->supported_caps |= SUPPORTED_1000baseT_Half | 1194 SUPPORTED_1000baseT_Full; 1195 if (link_caps.speed_capabilities & 1196 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1197 if_link->supported_caps |= SUPPORTED_10000baseKR_Full; 1198 if (link_caps.speed_capabilities & 1199 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1200 if_link->supported_caps |= SUPPORTED_40000baseLR4_Full; 1201 if (link_caps.speed_capabilities & 1202 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1203 if_link->supported_caps |= 0; 1204 if (link_caps.speed_capabilities & 1205 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G) 1206 if_link->supported_caps |= 0; 1207 1208 if (link.link_up) 1209 if_link->speed = link.speed; 1210 1211 /* TODO - fill duplex properly */ 1212 if_link->duplex = DUPLEX_FULL; 1213 qed_mcp_get_media_type(hwfn->cdev, &media_type); 1214 if_link->port = qed_get_port_type(media_type); 1215 1216 if_link->autoneg = params.speed.autoneg; 1217 1218 if (params.pause.autoneg) 1219 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1220 if (params.pause.forced_rx) 1221 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1222 if (params.pause.forced_tx) 1223 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1224 1225 /* Link partner capabilities */ 1226 if (link.partner_adv_speed & 1227 QED_LINK_PARTNER_SPEED_1G_HD) 1228 if_link->lp_caps |= SUPPORTED_1000baseT_Half; 1229 if (link.partner_adv_speed & 1230 QED_LINK_PARTNER_SPEED_1G_FD) 1231 if_link->lp_caps |= SUPPORTED_1000baseT_Full; 1232 if (link.partner_adv_speed & 1233 QED_LINK_PARTNER_SPEED_10G) 1234 if_link->lp_caps |= SUPPORTED_10000baseKR_Full; 1235 if (link.partner_adv_speed & 1236 QED_LINK_PARTNER_SPEED_40G) 1237 if_link->lp_caps |= SUPPORTED_40000baseLR4_Full; 1238 if (link.partner_adv_speed & 1239 QED_LINK_PARTNER_SPEED_50G) 1240 if_link->lp_caps |= 0; 1241 if (link.partner_adv_speed & 1242 QED_LINK_PARTNER_SPEED_100G) 1243 if_link->lp_caps |= 0; 1244 1245 if (link.an_complete) 1246 if_link->lp_caps |= SUPPORTED_Autoneg; 1247 1248 if (link.partner_adv_pause) 1249 if_link->lp_caps |= SUPPORTED_Pause; 1250 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1251 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1252 if_link->lp_caps |= SUPPORTED_Asym_Pause; 1253 } 1254 1255 static void qed_get_current_link(struct qed_dev *cdev, 1256 struct qed_link_output *if_link) 1257 { 1258 int i; 1259 1260 qed_fill_link(&cdev->hwfns[0], if_link); 1261 1262 for_each_hwfn(cdev, i) 1263 qed_inform_vf_link_state(&cdev->hwfns[i]); 1264 } 1265 1266 void qed_link_update(struct qed_hwfn *hwfn) 1267 { 1268 void *cookie = hwfn->cdev->ops_cookie; 1269 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1270 struct qed_link_output if_link; 1271 1272 qed_fill_link(hwfn, &if_link); 1273 qed_inform_vf_link_state(hwfn); 1274 1275 if (IS_LEAD_HWFN(hwfn) && cookie) 1276 op->link_update(cookie, &if_link); 1277 } 1278 1279 static int qed_drain(struct qed_dev *cdev) 1280 { 1281 struct qed_hwfn *hwfn; 1282 struct qed_ptt *ptt; 1283 int i, rc; 1284 1285 if (IS_VF(cdev)) 1286 return 0; 1287 1288 for_each_hwfn(cdev, i) { 1289 hwfn = &cdev->hwfns[i]; 1290 ptt = qed_ptt_acquire(hwfn); 1291 if (!ptt) { 1292 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1293 return -EBUSY; 1294 } 1295 rc = qed_mcp_drain(hwfn, ptt); 1296 if (rc) 1297 return rc; 1298 qed_ptt_release(hwfn, ptt); 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 1305 { 1306 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 1307 struct qed_ptt *ptt; 1308 int status = 0; 1309 1310 ptt = qed_ptt_acquire(hwfn); 1311 if (!ptt) 1312 return -EAGAIN; 1313 1314 status = qed_mcp_set_led(hwfn, ptt, mode); 1315 1316 qed_ptt_release(hwfn, ptt); 1317 1318 return status; 1319 } 1320 1321 struct qed_selftest_ops qed_selftest_ops_pass = { 1322 .selftest_memory = &qed_selftest_memory, 1323 .selftest_interrupt = &qed_selftest_interrupt, 1324 .selftest_register = &qed_selftest_register, 1325 .selftest_clock = &qed_selftest_clock, 1326 }; 1327 1328 const struct qed_common_ops qed_common_ops_pass = { 1329 .selftest = &qed_selftest_ops_pass, 1330 .probe = &qed_probe, 1331 .remove = &qed_remove, 1332 .set_power_state = &qed_set_power_state, 1333 .set_id = &qed_set_id, 1334 .update_pf_params = &qed_update_pf_params, 1335 .slowpath_start = &qed_slowpath_start, 1336 .slowpath_stop = &qed_slowpath_stop, 1337 .set_fp_int = &qed_set_int_fp, 1338 .get_fp_int = &qed_get_int_fp, 1339 .sb_init = &qed_sb_init, 1340 .sb_release = &qed_sb_release, 1341 .simd_handler_config = &qed_simd_handler_config, 1342 .simd_handler_clean = &qed_simd_handler_clean, 1343 .can_link_change = &qed_can_link_change, 1344 .set_link = &qed_set_link, 1345 .get_link = &qed_get_current_link, 1346 .drain = &qed_drain, 1347 .update_msglvl = &qed_init_dp, 1348 .chain_alloc = &qed_chain_alloc, 1349 .chain_free = &qed_chain_free, 1350 .set_led = &qed_set_led, 1351 }; 1352