1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/stddef.h> 10fe56b9e6SYuval Mintz #include <linux/pci.h> 11fe56b9e6SYuval Mintz #include <linux/kernel.h> 12fe56b9e6SYuval Mintz #include <linux/slab.h> 13fe56b9e6SYuval Mintz #include <linux/version.h> 14fe56b9e6SYuval Mintz #include <linux/delay.h> 15fe56b9e6SYuval Mintz #include <asm/byteorder.h> 16fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 17fe56b9e6SYuval Mintz #include <linux/string.h> 18fe56b9e6SYuval Mintz #include <linux/module.h> 19fe56b9e6SYuval Mintz #include <linux/interrupt.h> 20fe56b9e6SYuval Mintz #include <linux/workqueue.h> 21fe56b9e6SYuval Mintz #include <linux/ethtool.h> 22fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 23fe56b9e6SYuval Mintz #include <linux/vmalloc.h> 24fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 25fe56b9e6SYuval Mintz 26fe56b9e6SYuval Mintz #include "qed.h" 2737bff2b9SYuval Mintz #include "qed_sriov.h" 28fe56b9e6SYuval Mintz #include "qed_sp.h" 29fe56b9e6SYuval Mintz #include "qed_dev_api.h" 30fe56b9e6SYuval Mintz #include "qed_mcp.h" 31fe56b9e6SYuval Mintz #include "qed_hw.h" 3203dc76caSSudarsana Reddy Kalluru #include "qed_selftest.h" 33fe56b9e6SYuval Mintz 345abd7e92SYuval Mintz static char version[] = 355abd7e92SYuval Mintz "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 36fe56b9e6SYuval Mintz 375abd7e92SYuval Mintz MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 38fe56b9e6SYuval Mintz MODULE_LICENSE("GPL"); 39fe56b9e6SYuval Mintz MODULE_VERSION(DRV_MODULE_VERSION); 40fe56b9e6SYuval Mintz 41fe56b9e6SYuval Mintz #define FW_FILE_VERSION \ 42fe56b9e6SYuval Mintz __stringify(FW_MAJOR_VERSION) "." \ 43fe56b9e6SYuval Mintz __stringify(FW_MINOR_VERSION) "." \ 44fe56b9e6SYuval Mintz __stringify(FW_REVISION_VERSION) "." \ 45fe56b9e6SYuval Mintz __stringify(FW_ENGINEERING_VERSION) 46fe56b9e6SYuval Mintz 47fe56b9e6SYuval Mintz #define QED_FW_FILE_NAME \ 48fe56b9e6SYuval Mintz "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 49fe56b9e6SYuval Mintz 50d43d3f0fSYuval Mintz MODULE_FIRMWARE(QED_FW_FILE_NAME); 51d43d3f0fSYuval Mintz 52fe56b9e6SYuval Mintz static int __init qed_init(void) 53fe56b9e6SYuval Mintz { 54fe56b9e6SYuval Mintz pr_notice("qed_init called\n"); 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz pr_info("%s", version); 57fe56b9e6SYuval Mintz 58fe56b9e6SYuval Mintz return 0; 59fe56b9e6SYuval Mintz } 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz static void __exit qed_cleanup(void) 62fe56b9e6SYuval Mintz { 63fe56b9e6SYuval Mintz pr_notice("qed_cleanup called\n"); 64fe56b9e6SYuval Mintz } 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz module_init(qed_init); 67fe56b9e6SYuval Mintz module_exit(qed_cleanup); 68fe56b9e6SYuval Mintz 69fe56b9e6SYuval Mintz /* Check if the DMA controller on the machine can properly handle the DMA 70fe56b9e6SYuval Mintz * addressing required by the device. 71fe56b9e6SYuval Mintz */ 72fe56b9e6SYuval Mintz static int qed_set_coherency_mask(struct qed_dev *cdev) 73fe56b9e6SYuval Mintz { 74fe56b9e6SYuval Mintz struct device *dev = &cdev->pdev->dev; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 77fe56b9e6SYuval Mintz if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 78fe56b9e6SYuval Mintz DP_NOTICE(cdev, 79fe56b9e6SYuval Mintz "Can't request 64-bit consistent allocations\n"); 80fe56b9e6SYuval Mintz return -EIO; 81fe56b9e6SYuval Mintz } 82fe56b9e6SYuval Mintz } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 83fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 84fe56b9e6SYuval Mintz return -EIO; 85fe56b9e6SYuval Mintz } 86fe56b9e6SYuval Mintz 87fe56b9e6SYuval Mintz return 0; 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz 90fe56b9e6SYuval Mintz static void qed_free_pci(struct qed_dev *cdev) 91fe56b9e6SYuval Mintz { 92fe56b9e6SYuval Mintz struct pci_dev *pdev = cdev->pdev; 93fe56b9e6SYuval Mintz 94fe56b9e6SYuval Mintz if (cdev->doorbells) 95fe56b9e6SYuval Mintz iounmap(cdev->doorbells); 96fe56b9e6SYuval Mintz if (cdev->regview) 97fe56b9e6SYuval Mintz iounmap(cdev->regview); 98fe56b9e6SYuval Mintz if (atomic_read(&pdev->enable_cnt) == 1) 99fe56b9e6SYuval Mintz pci_release_regions(pdev); 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz pci_disable_device(pdev); 102fe56b9e6SYuval Mintz } 103fe56b9e6SYuval Mintz 1040dfaba6dSYuval Mintz #define PCI_REVISION_ID_ERROR_VAL 0xff 1050dfaba6dSYuval Mintz 106fe56b9e6SYuval Mintz /* Performs PCI initializations as well as initializing PCI-related parameters 107fe56b9e6SYuval Mintz * in the device structrue. Returns 0 in case of success. 108fe56b9e6SYuval Mintz */ 109fe56b9e6SYuval Mintz static int qed_init_pci(struct qed_dev *cdev, 110fe56b9e6SYuval Mintz struct pci_dev *pdev) 111fe56b9e6SYuval Mintz { 1120dfaba6dSYuval Mintz u8 rev_id; 113fe56b9e6SYuval Mintz int rc; 114fe56b9e6SYuval Mintz 115fe56b9e6SYuval Mintz cdev->pdev = pdev; 116fe56b9e6SYuval Mintz 117fe56b9e6SYuval Mintz rc = pci_enable_device(pdev); 118fe56b9e6SYuval Mintz if (rc) { 119fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot enable PCI device\n"); 120fe56b9e6SYuval Mintz goto err0; 121fe56b9e6SYuval Mintz } 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 124fe56b9e6SYuval Mintz DP_NOTICE(cdev, "No memory region found in bar #0\n"); 125fe56b9e6SYuval Mintz rc = -EIO; 126fe56b9e6SYuval Mintz goto err1; 127fe56b9e6SYuval Mintz } 128fe56b9e6SYuval Mintz 1291408cc1fSYuval Mintz if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 130fe56b9e6SYuval Mintz DP_NOTICE(cdev, "No memory region found in bar #2\n"); 131fe56b9e6SYuval Mintz rc = -EIO; 132fe56b9e6SYuval Mintz goto err1; 133fe56b9e6SYuval Mintz } 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz if (atomic_read(&pdev->enable_cnt) == 1) { 136fe56b9e6SYuval Mintz rc = pci_request_regions(pdev, "qed"); 137fe56b9e6SYuval Mintz if (rc) { 138fe56b9e6SYuval Mintz DP_NOTICE(cdev, 139fe56b9e6SYuval Mintz "Failed to request PCI memory resources\n"); 140fe56b9e6SYuval Mintz goto err1; 141fe56b9e6SYuval Mintz } 142fe56b9e6SYuval Mintz pci_set_master(pdev); 143fe56b9e6SYuval Mintz pci_save_state(pdev); 144fe56b9e6SYuval Mintz } 145fe56b9e6SYuval Mintz 1460dfaba6dSYuval Mintz pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 1470dfaba6dSYuval Mintz if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 1480dfaba6dSYuval Mintz DP_NOTICE(cdev, 1490dfaba6dSYuval Mintz "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 1500dfaba6dSYuval Mintz rev_id); 1510dfaba6dSYuval Mintz rc = -ENODEV; 1520dfaba6dSYuval Mintz goto err2; 1530dfaba6dSYuval Mintz } 154fe56b9e6SYuval Mintz if (!pci_is_pcie(pdev)) { 155fe56b9e6SYuval Mintz DP_NOTICE(cdev, "The bus is not PCI Express\n"); 156fe56b9e6SYuval Mintz rc = -EIO; 157fe56b9e6SYuval Mintz goto err2; 158fe56b9e6SYuval Mintz } 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 161416cdf06SYuval Mintz if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 162fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot find power management capability\n"); 163fe56b9e6SYuval Mintz 164fe56b9e6SYuval Mintz rc = qed_set_coherency_mask(cdev); 165fe56b9e6SYuval Mintz if (rc) 166fe56b9e6SYuval Mintz goto err2; 167fe56b9e6SYuval Mintz 168fe56b9e6SYuval Mintz cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 169fe56b9e6SYuval Mintz cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 170fe56b9e6SYuval Mintz cdev->pci_params.irq = pdev->irq; 171fe56b9e6SYuval Mintz 172fe56b9e6SYuval Mintz cdev->regview = pci_ioremap_bar(pdev, 0); 173fe56b9e6SYuval Mintz if (!cdev->regview) { 174fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 175fe56b9e6SYuval Mintz rc = -ENOMEM; 176fe56b9e6SYuval Mintz goto err2; 177fe56b9e6SYuval Mintz } 178fe56b9e6SYuval Mintz 1791408cc1fSYuval Mintz if (IS_PF(cdev)) { 180fe56b9e6SYuval Mintz cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 181fe56b9e6SYuval Mintz cdev->db_size = pci_resource_len(cdev->pdev, 2); 182fe56b9e6SYuval Mintz cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 183fe56b9e6SYuval Mintz if (!cdev->doorbells) { 184fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot map doorbell space\n"); 185fe56b9e6SYuval Mintz return -ENOMEM; 186fe56b9e6SYuval Mintz } 1871408cc1fSYuval Mintz } 188fe56b9e6SYuval Mintz 189fe56b9e6SYuval Mintz return 0; 190fe56b9e6SYuval Mintz 191fe56b9e6SYuval Mintz err2: 192fe56b9e6SYuval Mintz pci_release_regions(pdev); 193fe56b9e6SYuval Mintz err1: 194fe56b9e6SYuval Mintz pci_disable_device(pdev); 195fe56b9e6SYuval Mintz err0: 196fe56b9e6SYuval Mintz return rc; 197fe56b9e6SYuval Mintz } 198fe56b9e6SYuval Mintz 199fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 200fe56b9e6SYuval Mintz struct qed_dev_info *dev_info) 201fe56b9e6SYuval Mintz { 202cee4d264SManish Chopra struct qed_ptt *ptt; 203cee4d264SManish Chopra 204fe56b9e6SYuval Mintz memset(dev_info, 0, sizeof(struct qed_dev_info)); 205fe56b9e6SYuval Mintz 206fe56b9e6SYuval Mintz dev_info->num_hwfns = cdev->num_hwfns; 207fe56b9e6SYuval Mintz dev_info->pci_mem_start = cdev->pci_params.mem_start; 208fe56b9e6SYuval Mintz dev_info->pci_mem_end = cdev->pci_params.mem_end; 209fe56b9e6SYuval Mintz dev_info->pci_irq = cdev->pci_params.irq; 210c5ac9319SYuval Mintz dev_info->rdma_supported = 211c5ac9319SYuval Mintz (cdev->hwfns[0].hw_info.personality == QED_PCI_ETH_ROCE); 212fc48b7a6SYuval Mintz dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]); 213fe56b9e6SYuval Mintz ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr); 214fe56b9e6SYuval Mintz 2151408cc1fSYuval Mintz if (IS_PF(cdev)) { 216fe56b9e6SYuval Mintz dev_info->fw_major = FW_MAJOR_VERSION; 217fe56b9e6SYuval Mintz dev_info->fw_minor = FW_MINOR_VERSION; 218fe56b9e6SYuval Mintz dev_info->fw_rev = FW_REVISION_VERSION; 219fe56b9e6SYuval Mintz dev_info->fw_eng = FW_ENGINEERING_VERSION; 220fe56b9e6SYuval Mintz dev_info->mf_mode = cdev->mf_mode; 221831bfb0eSYuval Mintz dev_info->tx_switching = true; 2221408cc1fSYuval Mintz } else { 2231408cc1fSYuval Mintz qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 2241408cc1fSYuval Mintz &dev_info->fw_minor, &dev_info->fw_rev, 2251408cc1fSYuval Mintz &dev_info->fw_eng); 2261408cc1fSYuval Mintz } 227fe56b9e6SYuval Mintz 2281408cc1fSYuval Mintz if (IS_PF(cdev)) { 229cee4d264SManish Chopra ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 230cee4d264SManish Chopra if (ptt) { 2311408cc1fSYuval Mintz qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 2321408cc1fSYuval Mintz &dev_info->mfw_rev, NULL); 2331408cc1fSYuval Mintz 234cee4d264SManish Chopra qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 235cee4d264SManish Chopra &dev_info->flash_size); 236cee4d264SManish Chopra 237cee4d264SManish Chopra qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 238cee4d264SManish Chopra } 2391408cc1fSYuval Mintz } else { 2401408cc1fSYuval Mintz qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 2411408cc1fSYuval Mintz &dev_info->mfw_rev, NULL); 2421408cc1fSYuval Mintz } 243cee4d264SManish Chopra 244fe56b9e6SYuval Mintz return 0; 245fe56b9e6SYuval Mintz } 246fe56b9e6SYuval Mintz 247fe56b9e6SYuval Mintz static void qed_free_cdev(struct qed_dev *cdev) 248fe56b9e6SYuval Mintz { 249fe56b9e6SYuval Mintz kfree((void *)cdev); 250fe56b9e6SYuval Mintz } 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 253fe56b9e6SYuval Mintz { 254fe56b9e6SYuval Mintz struct qed_dev *cdev; 255fe56b9e6SYuval Mintz 256fe56b9e6SYuval Mintz cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 257fe56b9e6SYuval Mintz if (!cdev) 258fe56b9e6SYuval Mintz return cdev; 259fe56b9e6SYuval Mintz 260fe56b9e6SYuval Mintz qed_init_struct(cdev); 261fe56b9e6SYuval Mintz 262fe56b9e6SYuval Mintz return cdev; 263fe56b9e6SYuval Mintz } 264fe56b9e6SYuval Mintz 265fe56b9e6SYuval Mintz /* Sets the requested power state */ 266fe56b9e6SYuval Mintz static int qed_set_power_state(struct qed_dev *cdev, 267fe56b9e6SYuval Mintz pci_power_t state) 268fe56b9e6SYuval Mintz { 269fe56b9e6SYuval Mintz if (!cdev) 270fe56b9e6SYuval Mintz return -ENODEV; 271fe56b9e6SYuval Mintz 272fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 273fe56b9e6SYuval Mintz return 0; 274fe56b9e6SYuval Mintz } 275fe56b9e6SYuval Mintz 276fe56b9e6SYuval Mintz /* probing */ 277fe56b9e6SYuval Mintz static struct qed_dev *qed_probe(struct pci_dev *pdev, 2781408cc1fSYuval Mintz struct qed_probe_params *params) 279fe56b9e6SYuval Mintz { 280fe56b9e6SYuval Mintz struct qed_dev *cdev; 281fe56b9e6SYuval Mintz int rc; 282fe56b9e6SYuval Mintz 283fe56b9e6SYuval Mintz cdev = qed_alloc_cdev(pdev); 284fe56b9e6SYuval Mintz if (!cdev) 285fe56b9e6SYuval Mintz goto err0; 286fe56b9e6SYuval Mintz 2871408cc1fSYuval Mintz cdev->protocol = params->protocol; 288fe56b9e6SYuval Mintz 2891408cc1fSYuval Mintz if (params->is_vf) 2901408cc1fSYuval Mintz cdev->b_is_vf = true; 2911408cc1fSYuval Mintz 2921408cc1fSYuval Mintz qed_init_dp(cdev, params->dp_module, params->dp_level); 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz rc = qed_init_pci(cdev, pdev); 295fe56b9e6SYuval Mintz if (rc) { 296fe56b9e6SYuval Mintz DP_ERR(cdev, "init pci failed\n"); 297fe56b9e6SYuval Mintz goto err1; 298fe56b9e6SYuval Mintz } 299fe56b9e6SYuval Mintz DP_INFO(cdev, "PCI init completed successfully\n"); 300fe56b9e6SYuval Mintz 301fe56b9e6SYuval Mintz rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 302fe56b9e6SYuval Mintz if (rc) { 303fe56b9e6SYuval Mintz DP_ERR(cdev, "hw prepare failed\n"); 304fe56b9e6SYuval Mintz goto err2; 305fe56b9e6SYuval Mintz } 306fe56b9e6SYuval Mintz 307fe56b9e6SYuval Mintz DP_INFO(cdev, "qed_probe completed successffuly\n"); 308fe56b9e6SYuval Mintz 309fe56b9e6SYuval Mintz return cdev; 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz err2: 312fe56b9e6SYuval Mintz qed_free_pci(cdev); 313fe56b9e6SYuval Mintz err1: 314fe56b9e6SYuval Mintz qed_free_cdev(cdev); 315fe56b9e6SYuval Mintz err0: 316fe56b9e6SYuval Mintz return NULL; 317fe56b9e6SYuval Mintz } 318fe56b9e6SYuval Mintz 319fe56b9e6SYuval Mintz static void qed_remove(struct qed_dev *cdev) 320fe56b9e6SYuval Mintz { 321fe56b9e6SYuval Mintz if (!cdev) 322fe56b9e6SYuval Mintz return; 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz qed_hw_remove(cdev); 325fe56b9e6SYuval Mintz 326fe56b9e6SYuval Mintz qed_free_pci(cdev); 327fe56b9e6SYuval Mintz 328fe56b9e6SYuval Mintz qed_set_power_state(cdev, PCI_D3hot); 329fe56b9e6SYuval Mintz 330fe56b9e6SYuval Mintz qed_free_cdev(cdev); 331fe56b9e6SYuval Mintz } 332fe56b9e6SYuval Mintz 333fe56b9e6SYuval Mintz static void qed_disable_msix(struct qed_dev *cdev) 334fe56b9e6SYuval Mintz { 335fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 336fe56b9e6SYuval Mintz pci_disable_msix(cdev->pdev); 337fe56b9e6SYuval Mintz kfree(cdev->int_params.msix_table); 338fe56b9e6SYuval Mintz } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 339fe56b9e6SYuval Mintz pci_disable_msi(cdev->pdev); 340fe56b9e6SYuval Mintz } 341fe56b9e6SYuval Mintz 342fe56b9e6SYuval Mintz memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 343fe56b9e6SYuval Mintz } 344fe56b9e6SYuval Mintz 345fe56b9e6SYuval Mintz static int qed_enable_msix(struct qed_dev *cdev, 346fe56b9e6SYuval Mintz struct qed_int_params *int_params) 347fe56b9e6SYuval Mintz { 348fe56b9e6SYuval Mintz int i, rc, cnt; 349fe56b9e6SYuval Mintz 350fe56b9e6SYuval Mintz cnt = int_params->in.num_vectors; 351fe56b9e6SYuval Mintz 352fe56b9e6SYuval Mintz for (i = 0; i < cnt; i++) 353fe56b9e6SYuval Mintz int_params->msix_table[i].entry = i; 354fe56b9e6SYuval Mintz 355fe56b9e6SYuval Mintz rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 356fe56b9e6SYuval Mintz int_params->in.min_msix_cnt, cnt); 357fe56b9e6SYuval Mintz if (rc < cnt && rc >= int_params->in.min_msix_cnt && 358fe56b9e6SYuval Mintz (rc % cdev->num_hwfns)) { 359fe56b9e6SYuval Mintz pci_disable_msix(cdev->pdev); 360fe56b9e6SYuval Mintz 361fe56b9e6SYuval Mintz /* If fastpath is initialized, we need at least one interrupt 362fe56b9e6SYuval Mintz * per hwfn [and the slow path interrupts]. New requested number 363fe56b9e6SYuval Mintz * should be a multiple of the number of hwfns. 364fe56b9e6SYuval Mintz */ 365fe56b9e6SYuval Mintz cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 366fe56b9e6SYuval Mintz DP_NOTICE(cdev, 367fe56b9e6SYuval Mintz "Trying to enable MSI-X with less vectors (%d out of %d)\n", 368fe56b9e6SYuval Mintz cnt, int_params->in.num_vectors); 369fe56b9e6SYuval Mintz rc = pci_enable_msix_exact(cdev->pdev, 370fe56b9e6SYuval Mintz int_params->msix_table, cnt); 371fe56b9e6SYuval Mintz if (!rc) 372fe56b9e6SYuval Mintz rc = cnt; 373fe56b9e6SYuval Mintz } 374fe56b9e6SYuval Mintz 375fe56b9e6SYuval Mintz if (rc > 0) { 376fe56b9e6SYuval Mintz /* MSI-x configuration was achieved */ 377fe56b9e6SYuval Mintz int_params->out.int_mode = QED_INT_MODE_MSIX; 378fe56b9e6SYuval Mintz int_params->out.num_vectors = rc; 379fe56b9e6SYuval Mintz rc = 0; 380fe56b9e6SYuval Mintz } else { 381fe56b9e6SYuval Mintz DP_NOTICE(cdev, 382fe56b9e6SYuval Mintz "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 383fe56b9e6SYuval Mintz cnt, rc); 384fe56b9e6SYuval Mintz } 385fe56b9e6SYuval Mintz 386fe56b9e6SYuval Mintz return rc; 387fe56b9e6SYuval Mintz } 388fe56b9e6SYuval Mintz 389fe56b9e6SYuval Mintz /* This function outputs the int mode and the number of enabled msix vector */ 390fe56b9e6SYuval Mintz static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 391fe56b9e6SYuval Mintz { 392fe56b9e6SYuval Mintz struct qed_int_params *int_params = &cdev->int_params; 393fe56b9e6SYuval Mintz struct msix_entry *tbl; 394fe56b9e6SYuval Mintz int rc = 0, cnt; 395fe56b9e6SYuval Mintz 396fe56b9e6SYuval Mintz switch (int_params->in.int_mode) { 397fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 398fe56b9e6SYuval Mintz /* Allocate MSIX table */ 399fe56b9e6SYuval Mintz cnt = int_params->in.num_vectors; 400fe56b9e6SYuval Mintz int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 401fe56b9e6SYuval Mintz if (!int_params->msix_table) { 402fe56b9e6SYuval Mintz rc = -ENOMEM; 403fe56b9e6SYuval Mintz goto out; 404fe56b9e6SYuval Mintz } 405fe56b9e6SYuval Mintz 406fe56b9e6SYuval Mintz /* Enable MSIX */ 407fe56b9e6SYuval Mintz rc = qed_enable_msix(cdev, int_params); 408fe56b9e6SYuval Mintz if (!rc) 409fe56b9e6SYuval Mintz goto out; 410fe56b9e6SYuval Mintz 411fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 412fe56b9e6SYuval Mintz kfree(int_params->msix_table); 413fe56b9e6SYuval Mintz if (force_mode) 414fe56b9e6SYuval Mintz goto out; 415fe56b9e6SYuval Mintz /* Fallthrough */ 416fe56b9e6SYuval Mintz 417fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 418bb13ace7SSudarsana Reddy Kalluru if (cdev->num_hwfns == 1) { 419fe56b9e6SYuval Mintz rc = pci_enable_msi(cdev->pdev); 420fe56b9e6SYuval Mintz if (!rc) { 421fe56b9e6SYuval Mintz int_params->out.int_mode = QED_INT_MODE_MSI; 422fe56b9e6SYuval Mintz goto out; 423fe56b9e6SYuval Mintz } 424fe56b9e6SYuval Mintz 425fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed to enable MSI\n"); 426fe56b9e6SYuval Mintz if (force_mode) 427fe56b9e6SYuval Mintz goto out; 428bb13ace7SSudarsana Reddy Kalluru } 429fe56b9e6SYuval Mintz /* Fallthrough */ 430fe56b9e6SYuval Mintz 431fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 432fe56b9e6SYuval Mintz int_params->out.int_mode = QED_INT_MODE_INTA; 433fe56b9e6SYuval Mintz rc = 0; 434fe56b9e6SYuval Mintz goto out; 435fe56b9e6SYuval Mintz default: 436fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Unknown int_mode value %d\n", 437fe56b9e6SYuval Mintz int_params->in.int_mode); 438fe56b9e6SYuval Mintz rc = -EINVAL; 439fe56b9e6SYuval Mintz } 440fe56b9e6SYuval Mintz 441fe56b9e6SYuval Mintz out: 442fe56b9e6SYuval Mintz cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 443fe56b9e6SYuval Mintz 444fe56b9e6SYuval Mintz return rc; 445fe56b9e6SYuval Mintz } 446fe56b9e6SYuval Mintz 447fe56b9e6SYuval Mintz static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 448fe56b9e6SYuval Mintz int index, void(*handler)(void *)) 449fe56b9e6SYuval Mintz { 450fe56b9e6SYuval Mintz struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 451fe56b9e6SYuval Mintz int relative_idx = index / cdev->num_hwfns; 452fe56b9e6SYuval Mintz 453fe56b9e6SYuval Mintz hwfn->simd_proto_handler[relative_idx].func = handler; 454fe56b9e6SYuval Mintz hwfn->simd_proto_handler[relative_idx].token = token; 455fe56b9e6SYuval Mintz } 456fe56b9e6SYuval Mintz 457fe56b9e6SYuval Mintz static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 458fe56b9e6SYuval Mintz { 459fe56b9e6SYuval Mintz struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 460fe56b9e6SYuval Mintz int relative_idx = index / cdev->num_hwfns; 461fe56b9e6SYuval Mintz 462fe56b9e6SYuval Mintz memset(&hwfn->simd_proto_handler[relative_idx], 0, 463fe56b9e6SYuval Mintz sizeof(struct qed_simd_fp_handler)); 464fe56b9e6SYuval Mintz } 465fe56b9e6SYuval Mintz 466fe56b9e6SYuval Mintz static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 467fe56b9e6SYuval Mintz { 468fe56b9e6SYuval Mintz tasklet_schedule((struct tasklet_struct *)tasklet); 469fe56b9e6SYuval Mintz return IRQ_HANDLED; 470fe56b9e6SYuval Mintz } 471fe56b9e6SYuval Mintz 472fe56b9e6SYuval Mintz static irqreturn_t qed_single_int(int irq, void *dev_instance) 473fe56b9e6SYuval Mintz { 474fe56b9e6SYuval Mintz struct qed_dev *cdev = (struct qed_dev *)dev_instance; 475fe56b9e6SYuval Mintz struct qed_hwfn *hwfn; 476fe56b9e6SYuval Mintz irqreturn_t rc = IRQ_NONE; 477fe56b9e6SYuval Mintz u64 status; 478fe56b9e6SYuval Mintz int i, j; 479fe56b9e6SYuval Mintz 480fe56b9e6SYuval Mintz for (i = 0; i < cdev->num_hwfns; i++) { 481fe56b9e6SYuval Mintz status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 482fe56b9e6SYuval Mintz 483fe56b9e6SYuval Mintz if (!status) 484fe56b9e6SYuval Mintz continue; 485fe56b9e6SYuval Mintz 486fe56b9e6SYuval Mintz hwfn = &cdev->hwfns[i]; 487fe56b9e6SYuval Mintz 488fe56b9e6SYuval Mintz /* Slowpath interrupt */ 489fe56b9e6SYuval Mintz if (unlikely(status & 0x1)) { 490fe56b9e6SYuval Mintz tasklet_schedule(hwfn->sp_dpc); 491fe56b9e6SYuval Mintz status &= ~0x1; 492fe56b9e6SYuval Mintz rc = IRQ_HANDLED; 493fe56b9e6SYuval Mintz } 494fe56b9e6SYuval Mintz 495fe56b9e6SYuval Mintz /* Fastpath interrupts */ 496fe56b9e6SYuval Mintz for (j = 0; j < 64; j++) { 497fe56b9e6SYuval Mintz if ((0x2ULL << j) & status) { 498fe56b9e6SYuval Mintz hwfn->simd_proto_handler[j].func( 499fe56b9e6SYuval Mintz hwfn->simd_proto_handler[j].token); 500fe56b9e6SYuval Mintz status &= ~(0x2ULL << j); 501fe56b9e6SYuval Mintz rc = IRQ_HANDLED; 502fe56b9e6SYuval Mintz } 503fe56b9e6SYuval Mintz } 504fe56b9e6SYuval Mintz 505fe56b9e6SYuval Mintz if (unlikely(status)) 506fe56b9e6SYuval Mintz DP_VERBOSE(hwfn, NETIF_MSG_INTR, 507fe56b9e6SYuval Mintz "got an unknown interrupt status 0x%llx\n", 508fe56b9e6SYuval Mintz status); 509fe56b9e6SYuval Mintz } 510fe56b9e6SYuval Mintz 511fe56b9e6SYuval Mintz return rc; 512fe56b9e6SYuval Mintz } 513fe56b9e6SYuval Mintz 5148f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 515fe56b9e6SYuval Mintz { 5168f16bc97SSudarsana Kalluru struct qed_dev *cdev = hwfn->cdev; 5178f16bc97SSudarsana Kalluru int rc = 0; 5188f16bc97SSudarsana Kalluru u8 id; 519fe56b9e6SYuval Mintz 520fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 5218f16bc97SSudarsana Kalluru id = hwfn->my_id; 5228f16bc97SSudarsana Kalluru snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 5238f16bc97SSudarsana Kalluru id, cdev->pdev->bus->number, 5248f16bc97SSudarsana Kalluru PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 5258f16bc97SSudarsana Kalluru rc = request_irq(cdev->int_params.msix_table[id].vector, 5268f16bc97SSudarsana Kalluru qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 5278f16bc97SSudarsana Kalluru if (!rc) 5288f16bc97SSudarsana Kalluru DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 529fe56b9e6SYuval Mintz "Requested slowpath MSI-X\n"); 530fe56b9e6SYuval Mintz } else { 531fe56b9e6SYuval Mintz unsigned long flags = 0; 532fe56b9e6SYuval Mintz 533fe56b9e6SYuval Mintz snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 534fe56b9e6SYuval Mintz cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 535fe56b9e6SYuval Mintz PCI_FUNC(cdev->pdev->devfn)); 536fe56b9e6SYuval Mintz 537fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 538fe56b9e6SYuval Mintz flags |= IRQF_SHARED; 539fe56b9e6SYuval Mintz 540fe56b9e6SYuval Mintz rc = request_irq(cdev->pdev->irq, qed_single_int, 541fe56b9e6SYuval Mintz flags, cdev->name, cdev); 542fe56b9e6SYuval Mintz } 543fe56b9e6SYuval Mintz 544fe56b9e6SYuval Mintz return rc; 545fe56b9e6SYuval Mintz } 546fe56b9e6SYuval Mintz 547fe56b9e6SYuval Mintz static void qed_slowpath_irq_free(struct qed_dev *cdev) 548fe56b9e6SYuval Mintz { 549fe56b9e6SYuval Mintz int i; 550fe56b9e6SYuval Mintz 551fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 552fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 5538f16bc97SSudarsana Kalluru if (!cdev->hwfns[i].b_int_requested) 5548f16bc97SSudarsana Kalluru break; 555fe56b9e6SYuval Mintz synchronize_irq(cdev->int_params.msix_table[i].vector); 556fe56b9e6SYuval Mintz free_irq(cdev->int_params.msix_table[i].vector, 557fe56b9e6SYuval Mintz cdev->hwfns[i].sp_dpc); 558fe56b9e6SYuval Mintz } 559fe56b9e6SYuval Mintz } else { 5608f16bc97SSudarsana Kalluru if (QED_LEADING_HWFN(cdev)->b_int_requested) 561fe56b9e6SYuval Mintz free_irq(cdev->pdev->irq, cdev); 562fe56b9e6SYuval Mintz } 5638f16bc97SSudarsana Kalluru qed_int_disable_post_isr_release(cdev); 564fe56b9e6SYuval Mintz } 565fe56b9e6SYuval Mintz 566fe56b9e6SYuval Mintz static int qed_nic_stop(struct qed_dev *cdev) 567fe56b9e6SYuval Mintz { 568fe56b9e6SYuval Mintz int i, rc; 569fe56b9e6SYuval Mintz 570fe56b9e6SYuval Mintz rc = qed_hw_stop(cdev); 571fe56b9e6SYuval Mintz 572fe56b9e6SYuval Mintz for (i = 0; i < cdev->num_hwfns; i++) { 573fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 574fe56b9e6SYuval Mintz 575fe56b9e6SYuval Mintz if (p_hwfn->b_sp_dpc_enabled) { 576fe56b9e6SYuval Mintz tasklet_disable(p_hwfn->sp_dpc); 577fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = false; 578fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 579fe56b9e6SYuval Mintz "Disabled sp taskelt [hwfn %d] at %p\n", 580fe56b9e6SYuval Mintz i, p_hwfn->sp_dpc); 581fe56b9e6SYuval Mintz } 582fe56b9e6SYuval Mintz } 583fe56b9e6SYuval Mintz 584fe56b9e6SYuval Mintz return rc; 585fe56b9e6SYuval Mintz } 586fe56b9e6SYuval Mintz 587fe56b9e6SYuval Mintz static int qed_nic_reset(struct qed_dev *cdev) 588fe56b9e6SYuval Mintz { 589fe56b9e6SYuval Mintz int rc; 590fe56b9e6SYuval Mintz 591fe56b9e6SYuval Mintz rc = qed_hw_reset(cdev); 592fe56b9e6SYuval Mintz if (rc) 593fe56b9e6SYuval Mintz return rc; 594fe56b9e6SYuval Mintz 595fe56b9e6SYuval Mintz qed_resc_free(cdev); 596fe56b9e6SYuval Mintz 597fe56b9e6SYuval Mintz return 0; 598fe56b9e6SYuval Mintz } 599fe56b9e6SYuval Mintz 600fe56b9e6SYuval Mintz static int qed_nic_setup(struct qed_dev *cdev) 601fe56b9e6SYuval Mintz { 602fe56b9e6SYuval Mintz int rc; 603fe56b9e6SYuval Mintz 604fe56b9e6SYuval Mintz rc = qed_resc_alloc(cdev); 605fe56b9e6SYuval Mintz if (rc) 606fe56b9e6SYuval Mintz return rc; 607fe56b9e6SYuval Mintz 608fe56b9e6SYuval Mintz DP_INFO(cdev, "Allocated qed resources\n"); 609fe56b9e6SYuval Mintz 610fe56b9e6SYuval Mintz qed_resc_setup(cdev); 611fe56b9e6SYuval Mintz 612fe56b9e6SYuval Mintz return rc; 613fe56b9e6SYuval Mintz } 614fe56b9e6SYuval Mintz 615fe56b9e6SYuval Mintz static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 616fe56b9e6SYuval Mintz { 617fe56b9e6SYuval Mintz int limit = 0; 618fe56b9e6SYuval Mintz 619fe56b9e6SYuval Mintz /* Mark the fastpath as free/used */ 620fe56b9e6SYuval Mintz cdev->int_params.fp_initialized = cnt ? true : false; 621fe56b9e6SYuval Mintz 622fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 623fe56b9e6SYuval Mintz limit = cdev->num_hwfns * 63; 624fe56b9e6SYuval Mintz else if (cdev->int_params.fp_msix_cnt) 625fe56b9e6SYuval Mintz limit = cdev->int_params.fp_msix_cnt; 626fe56b9e6SYuval Mintz 627fe56b9e6SYuval Mintz if (!limit) 628fe56b9e6SYuval Mintz return -ENOMEM; 629fe56b9e6SYuval Mintz 630fe56b9e6SYuval Mintz return min_t(int, cnt, limit); 631fe56b9e6SYuval Mintz } 632fe56b9e6SYuval Mintz 633fe56b9e6SYuval Mintz static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 634fe56b9e6SYuval Mintz { 635fe56b9e6SYuval Mintz memset(info, 0, sizeof(struct qed_int_info)); 636fe56b9e6SYuval Mintz 637fe56b9e6SYuval Mintz if (!cdev->int_params.fp_initialized) { 638fe56b9e6SYuval Mintz DP_INFO(cdev, 639fe56b9e6SYuval Mintz "Protocol driver requested interrupt information, but its support is not yet configured\n"); 640fe56b9e6SYuval Mintz return -EINVAL; 641fe56b9e6SYuval Mintz } 642fe56b9e6SYuval Mintz 643fe56b9e6SYuval Mintz /* Need to expose only MSI-X information; Single IRQ is handled solely 644fe56b9e6SYuval Mintz * by qed. 645fe56b9e6SYuval Mintz */ 646fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 647fe56b9e6SYuval Mintz int msix_base = cdev->int_params.fp_msix_base; 648fe56b9e6SYuval Mintz 649fe56b9e6SYuval Mintz info->msix_cnt = cdev->int_params.fp_msix_cnt; 650fe56b9e6SYuval Mintz info->msix = &cdev->int_params.msix_table[msix_base]; 651fe56b9e6SYuval Mintz } 652fe56b9e6SYuval Mintz 653fe56b9e6SYuval Mintz return 0; 654fe56b9e6SYuval Mintz } 655fe56b9e6SYuval Mintz 656fe56b9e6SYuval Mintz static int qed_slowpath_setup_int(struct qed_dev *cdev, 657fe56b9e6SYuval Mintz enum qed_int_mode int_mode) 658fe56b9e6SYuval Mintz { 6594ac801b7SYuval Mintz struct qed_sb_cnt_info sb_cnt_info; 6604ac801b7SYuval Mintz int rc; 6614ac801b7SYuval Mintz int i; 662fe56b9e6SYuval Mintz memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 663fe56b9e6SYuval Mintz 664fe56b9e6SYuval Mintz cdev->int_params.in.int_mode = int_mode; 6654ac801b7SYuval Mintz for_each_hwfn(cdev, i) { 6664ac801b7SYuval Mintz memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 6674ac801b7SYuval Mintz qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 6684ac801b7SYuval Mintz cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt; 6694ac801b7SYuval Mintz cdev->int_params.in.num_vectors++; /* slowpath */ 6704ac801b7SYuval Mintz } 671fe56b9e6SYuval Mintz 672fe56b9e6SYuval Mintz /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 673fe56b9e6SYuval Mintz cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 674fe56b9e6SYuval Mintz 675fe56b9e6SYuval Mintz rc = qed_set_int_mode(cdev, false); 676fe56b9e6SYuval Mintz if (rc) { 677fe56b9e6SYuval Mintz DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 678fe56b9e6SYuval Mintz return rc; 679fe56b9e6SYuval Mintz } 680fe56b9e6SYuval Mintz 681fe56b9e6SYuval Mintz cdev->int_params.fp_msix_base = cdev->num_hwfns; 682fe56b9e6SYuval Mintz cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 683fe56b9e6SYuval Mintz cdev->num_hwfns; 684fe56b9e6SYuval Mintz 685fe56b9e6SYuval Mintz return 0; 686fe56b9e6SYuval Mintz } 687fe56b9e6SYuval Mintz 6881408cc1fSYuval Mintz static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 6891408cc1fSYuval Mintz { 6901408cc1fSYuval Mintz int rc; 6911408cc1fSYuval Mintz 6921408cc1fSYuval Mintz memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 6931408cc1fSYuval Mintz cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 6941408cc1fSYuval Mintz 6951408cc1fSYuval Mintz qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 6961408cc1fSYuval Mintz &cdev->int_params.in.num_vectors); 6971408cc1fSYuval Mintz if (cdev->num_hwfns > 1) { 6981408cc1fSYuval Mintz u8 vectors = 0; 6991408cc1fSYuval Mintz 7001408cc1fSYuval Mintz qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 7011408cc1fSYuval Mintz cdev->int_params.in.num_vectors += vectors; 7021408cc1fSYuval Mintz } 7031408cc1fSYuval Mintz 7041408cc1fSYuval Mintz /* We want a minimum of one fastpath vector per vf hwfn */ 7051408cc1fSYuval Mintz cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 7061408cc1fSYuval Mintz 7071408cc1fSYuval Mintz rc = qed_set_int_mode(cdev, true); 7081408cc1fSYuval Mintz if (rc) 7091408cc1fSYuval Mintz return rc; 7101408cc1fSYuval Mintz 7111408cc1fSYuval Mintz cdev->int_params.fp_msix_base = 0; 7121408cc1fSYuval Mintz cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 7131408cc1fSYuval Mintz 7141408cc1fSYuval Mintz return 0; 7151408cc1fSYuval Mintz } 7161408cc1fSYuval Mintz 717fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 718fe56b9e6SYuval Mintz u8 *input_buf, u32 max_size, u8 *unzip_buf) 719fe56b9e6SYuval Mintz { 720fe56b9e6SYuval Mintz int rc; 721fe56b9e6SYuval Mintz 722fe56b9e6SYuval Mintz p_hwfn->stream->next_in = input_buf; 723fe56b9e6SYuval Mintz p_hwfn->stream->avail_in = input_len; 724fe56b9e6SYuval Mintz p_hwfn->stream->next_out = unzip_buf; 725fe56b9e6SYuval Mintz p_hwfn->stream->avail_out = max_size; 726fe56b9e6SYuval Mintz 727fe56b9e6SYuval Mintz rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 728fe56b9e6SYuval Mintz 729fe56b9e6SYuval Mintz if (rc != Z_OK) { 730fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 731fe56b9e6SYuval Mintz rc); 732fe56b9e6SYuval Mintz return 0; 733fe56b9e6SYuval Mintz } 734fe56b9e6SYuval Mintz 735fe56b9e6SYuval Mintz rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 736fe56b9e6SYuval Mintz zlib_inflateEnd(p_hwfn->stream); 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz if (rc != Z_OK && rc != Z_STREAM_END) { 739fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 740fe56b9e6SYuval Mintz p_hwfn->stream->msg, rc); 741fe56b9e6SYuval Mintz return 0; 742fe56b9e6SYuval Mintz } 743fe56b9e6SYuval Mintz 744fe56b9e6SYuval Mintz return p_hwfn->stream->total_out / 4; 745fe56b9e6SYuval Mintz } 746fe56b9e6SYuval Mintz 747fe56b9e6SYuval Mintz static int qed_alloc_stream_mem(struct qed_dev *cdev) 748fe56b9e6SYuval Mintz { 749fe56b9e6SYuval Mintz int i; 750fe56b9e6SYuval Mintz void *workspace; 751fe56b9e6SYuval Mintz 752fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 753fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 754fe56b9e6SYuval Mintz 755fe56b9e6SYuval Mintz p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 756fe56b9e6SYuval Mintz if (!p_hwfn->stream) 757fe56b9e6SYuval Mintz return -ENOMEM; 758fe56b9e6SYuval Mintz 759fe56b9e6SYuval Mintz workspace = vzalloc(zlib_inflate_workspacesize()); 760fe56b9e6SYuval Mintz if (!workspace) 761fe56b9e6SYuval Mintz return -ENOMEM; 762fe56b9e6SYuval Mintz p_hwfn->stream->workspace = workspace; 763fe56b9e6SYuval Mintz } 764fe56b9e6SYuval Mintz 765fe56b9e6SYuval Mintz return 0; 766fe56b9e6SYuval Mintz } 767fe56b9e6SYuval Mintz 768fe56b9e6SYuval Mintz static void qed_free_stream_mem(struct qed_dev *cdev) 769fe56b9e6SYuval Mintz { 770fe56b9e6SYuval Mintz int i; 771fe56b9e6SYuval Mintz 772fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 773fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 774fe56b9e6SYuval Mintz 775fe56b9e6SYuval Mintz if (!p_hwfn->stream) 776fe56b9e6SYuval Mintz return; 777fe56b9e6SYuval Mintz 778fe56b9e6SYuval Mintz vfree(p_hwfn->stream->workspace); 779fe56b9e6SYuval Mintz kfree(p_hwfn->stream); 780fe56b9e6SYuval Mintz } 781fe56b9e6SYuval Mintz } 782fe56b9e6SYuval Mintz 783fe56b9e6SYuval Mintz static void qed_update_pf_params(struct qed_dev *cdev, 784fe56b9e6SYuval Mintz struct qed_pf_params *params) 785fe56b9e6SYuval Mintz { 786fe56b9e6SYuval Mintz int i; 787fe56b9e6SYuval Mintz 788fe56b9e6SYuval Mintz for (i = 0; i < cdev->num_hwfns; i++) { 789fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 790fe56b9e6SYuval Mintz 791fe56b9e6SYuval Mintz p_hwfn->pf_params = *params; 792fe56b9e6SYuval Mintz } 793fe56b9e6SYuval Mintz } 794fe56b9e6SYuval Mintz 795fe56b9e6SYuval Mintz static int qed_slowpath_start(struct qed_dev *cdev, 796fe56b9e6SYuval Mintz struct qed_slowpath_params *params) 797fe56b9e6SYuval Mintz { 798b18e170cSManish Chopra struct qed_tunn_start_params tunn_info; 799fe56b9e6SYuval Mintz struct qed_mcp_drv_version drv_version; 800fe56b9e6SYuval Mintz const u8 *data = NULL; 801fe56b9e6SYuval Mintz struct qed_hwfn *hwfn; 80237bff2b9SYuval Mintz int rc = -EINVAL; 80337bff2b9SYuval Mintz 80437bff2b9SYuval Mintz if (qed_iov_wq_start(cdev)) 80537bff2b9SYuval Mintz goto err; 806fe56b9e6SYuval Mintz 8071408cc1fSYuval Mintz if (IS_PF(cdev)) { 808fe56b9e6SYuval Mintz rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 809fe56b9e6SYuval Mintz &cdev->pdev->dev); 810fe56b9e6SYuval Mintz if (rc) { 811fe56b9e6SYuval Mintz DP_NOTICE(cdev, 812fe56b9e6SYuval Mintz "Failed to find fw file - /lib/firmware/%s\n", 813fe56b9e6SYuval Mintz QED_FW_FILE_NAME); 814fe56b9e6SYuval Mintz goto err; 815fe56b9e6SYuval Mintz } 8161408cc1fSYuval Mintz } 817fe56b9e6SYuval Mintz 818fe56b9e6SYuval Mintz rc = qed_nic_setup(cdev); 819fe56b9e6SYuval Mintz if (rc) 820fe56b9e6SYuval Mintz goto err; 821fe56b9e6SYuval Mintz 8221408cc1fSYuval Mintz if (IS_PF(cdev)) 823fe56b9e6SYuval Mintz rc = qed_slowpath_setup_int(cdev, params->int_mode); 8241408cc1fSYuval Mintz else 8251408cc1fSYuval Mintz rc = qed_slowpath_vf_setup_int(cdev); 826fe56b9e6SYuval Mintz if (rc) 827fe56b9e6SYuval Mintz goto err1; 828fe56b9e6SYuval Mintz 8291408cc1fSYuval Mintz if (IS_PF(cdev)) { 830fe56b9e6SYuval Mintz /* Allocate stream for unzipping */ 831fe56b9e6SYuval Mintz rc = qed_alloc_stream_mem(cdev); 832fe56b9e6SYuval Mintz if (rc) { 833fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed to allocate stream memory\n"); 8348f16bc97SSudarsana Kalluru goto err2; 835fe56b9e6SYuval Mintz } 836fe56b9e6SYuval Mintz 837351a4dedSYuval Mintz /* First Dword used to diffrentiate between various sources */ 838351a4dedSYuval Mintz data = cdev->firmware->data + sizeof(u32); 8391408cc1fSYuval Mintz } 840fe56b9e6SYuval Mintz 841b18e170cSManish Chopra memset(&tunn_info, 0, sizeof(tunn_info)); 8429a109dd0SManish Chopra tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN | 843f7985869SManish Chopra 1 << QED_MODE_L2GRE_TUNN | 844f7985869SManish Chopra 1 << QED_MODE_IPGRE_TUNN | 8459a109dd0SManish Chopra 1 << QED_MODE_L2GENEVE_TUNN | 8469a109dd0SManish Chopra 1 << QED_MODE_IPGENEVE_TUNN; 8479a109dd0SManish Chopra 848b18e170cSManish Chopra tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN; 849f7985869SManish Chopra tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN; 850f7985869SManish Chopra tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN; 851b18e170cSManish Chopra 8521408cc1fSYuval Mintz /* Start the slowpath */ 853b18e170cSManish Chopra rc = qed_hw_init(cdev, &tunn_info, true, 854b18e170cSManish Chopra cdev->int_params.out.int_mode, 855fe56b9e6SYuval Mintz true, data); 856fe56b9e6SYuval Mintz if (rc) 8578c925c44SYuval Mintz goto err2; 858fe56b9e6SYuval Mintz 859fe56b9e6SYuval Mintz DP_INFO(cdev, 860fe56b9e6SYuval Mintz "HW initialization and function start completed successfully\n"); 861fe56b9e6SYuval Mintz 8621408cc1fSYuval Mintz if (IS_PF(cdev)) { 863fe56b9e6SYuval Mintz hwfn = QED_LEADING_HWFN(cdev); 864fe56b9e6SYuval Mintz drv_version.version = (params->drv_major << 24) | 865fe56b9e6SYuval Mintz (params->drv_minor << 16) | 866fe56b9e6SYuval Mintz (params->drv_rev << 8) | 867fe56b9e6SYuval Mintz (params->drv_eng); 868fe56b9e6SYuval Mintz strlcpy(drv_version.name, params->name, 869fe56b9e6SYuval Mintz MCP_DRV_VER_STR_SIZE - 4); 870fe56b9e6SYuval Mintz rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 871fe56b9e6SYuval Mintz &drv_version); 872fe56b9e6SYuval Mintz if (rc) { 873fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed sending drv version command\n"); 874fe56b9e6SYuval Mintz return rc; 875fe56b9e6SYuval Mintz } 8761408cc1fSYuval Mintz } 877fe56b9e6SYuval Mintz 8788c925c44SYuval Mintz qed_reset_vport_stats(cdev); 8798c925c44SYuval Mintz 880fe56b9e6SYuval Mintz return 0; 881fe56b9e6SYuval Mintz 882fe56b9e6SYuval Mintz err2: 8838c925c44SYuval Mintz qed_hw_timers_stop_all(cdev); 8841408cc1fSYuval Mintz if (IS_PF(cdev)) 8858c925c44SYuval Mintz qed_slowpath_irq_free(cdev); 8868c925c44SYuval Mintz qed_free_stream_mem(cdev); 887fe56b9e6SYuval Mintz qed_disable_msix(cdev); 888fe56b9e6SYuval Mintz err1: 889fe56b9e6SYuval Mintz qed_resc_free(cdev); 890fe56b9e6SYuval Mintz err: 8911408cc1fSYuval Mintz if (IS_PF(cdev)) 892fe56b9e6SYuval Mintz release_firmware(cdev->firmware); 893fe56b9e6SYuval Mintz 89437bff2b9SYuval Mintz qed_iov_wq_stop(cdev, false); 89537bff2b9SYuval Mintz 896fe56b9e6SYuval Mintz return rc; 897fe56b9e6SYuval Mintz } 898fe56b9e6SYuval Mintz 899fe56b9e6SYuval Mintz static int qed_slowpath_stop(struct qed_dev *cdev) 900fe56b9e6SYuval Mintz { 901fe56b9e6SYuval Mintz if (!cdev) 902fe56b9e6SYuval Mintz return -ENODEV; 903fe56b9e6SYuval Mintz 9041408cc1fSYuval Mintz if (IS_PF(cdev)) { 905fe56b9e6SYuval Mintz qed_free_stream_mem(cdev); 906c5ac9319SYuval Mintz if (IS_QED_ETH_IF(cdev)) 9070b55e27dSYuval Mintz qed_sriov_disable(cdev, true); 908fe56b9e6SYuval Mintz 909fe56b9e6SYuval Mintz qed_nic_stop(cdev); 910fe56b9e6SYuval Mintz qed_slowpath_irq_free(cdev); 9111408cc1fSYuval Mintz } 912fe56b9e6SYuval Mintz 913fe56b9e6SYuval Mintz qed_disable_msix(cdev); 914fe56b9e6SYuval Mintz qed_nic_reset(cdev); 915fe56b9e6SYuval Mintz 91637bff2b9SYuval Mintz qed_iov_wq_stop(cdev, true); 91737bff2b9SYuval Mintz 9181408cc1fSYuval Mintz if (IS_PF(cdev)) 919fe56b9e6SYuval Mintz release_firmware(cdev->firmware); 920fe56b9e6SYuval Mintz 921fe56b9e6SYuval Mintz return 0; 922fe56b9e6SYuval Mintz } 923fe56b9e6SYuval Mintz 924fe56b9e6SYuval Mintz static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE], 925fe56b9e6SYuval Mintz char ver_str[VER_SIZE]) 926fe56b9e6SYuval Mintz { 927fe56b9e6SYuval Mintz int i; 928fe56b9e6SYuval Mintz 929fe56b9e6SYuval Mintz memcpy(cdev->name, name, NAME_SIZE); 930fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) 931fe56b9e6SYuval Mintz snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 932fe56b9e6SYuval Mintz 933fe56b9e6SYuval Mintz memcpy(cdev->ver_str, ver_str, VER_SIZE); 934fe56b9e6SYuval Mintz cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 935fe56b9e6SYuval Mintz } 936fe56b9e6SYuval Mintz 937fe56b9e6SYuval Mintz static u32 qed_sb_init(struct qed_dev *cdev, 938fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 939fe56b9e6SYuval Mintz void *sb_virt_addr, 940fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, u16 sb_id, 941fe56b9e6SYuval Mintz enum qed_sb_type type) 942fe56b9e6SYuval Mintz { 943fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn; 944fe56b9e6SYuval Mintz int hwfn_index; 945fe56b9e6SYuval Mintz u16 rel_sb_id; 946fe56b9e6SYuval Mintz u8 n_hwfns; 947fe56b9e6SYuval Mintz u32 rc; 948fe56b9e6SYuval Mintz 949fe56b9e6SYuval Mintz /* RoCE uses single engine and CMT uses two engines. When using both 950fe56b9e6SYuval Mintz * we force only a single engine. Storage uses only engine 0 too. 951fe56b9e6SYuval Mintz */ 952fe56b9e6SYuval Mintz if (type == QED_SB_TYPE_L2_QUEUE) 953fe56b9e6SYuval Mintz n_hwfns = cdev->num_hwfns; 954fe56b9e6SYuval Mintz else 955fe56b9e6SYuval Mintz n_hwfns = 1; 956fe56b9e6SYuval Mintz 957fe56b9e6SYuval Mintz hwfn_index = sb_id % n_hwfns; 958fe56b9e6SYuval Mintz p_hwfn = &cdev->hwfns[hwfn_index]; 959fe56b9e6SYuval Mintz rel_sb_id = sb_id / n_hwfns; 960fe56b9e6SYuval Mintz 961fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_INTR, 962fe56b9e6SYuval Mintz "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 963fe56b9e6SYuval Mintz hwfn_index, rel_sb_id, sb_id); 964fe56b9e6SYuval Mintz 965fe56b9e6SYuval Mintz rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 966fe56b9e6SYuval Mintz sb_virt_addr, sb_phy_addr, rel_sb_id); 967fe56b9e6SYuval Mintz 968fe56b9e6SYuval Mintz return rc; 969fe56b9e6SYuval Mintz } 970fe56b9e6SYuval Mintz 971fe56b9e6SYuval Mintz static u32 qed_sb_release(struct qed_dev *cdev, 972fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 973fe56b9e6SYuval Mintz u16 sb_id) 974fe56b9e6SYuval Mintz { 975fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn; 976fe56b9e6SYuval Mintz int hwfn_index; 977fe56b9e6SYuval Mintz u16 rel_sb_id; 978fe56b9e6SYuval Mintz u32 rc; 979fe56b9e6SYuval Mintz 980fe56b9e6SYuval Mintz hwfn_index = sb_id % cdev->num_hwfns; 981fe56b9e6SYuval Mintz p_hwfn = &cdev->hwfns[hwfn_index]; 982fe56b9e6SYuval Mintz rel_sb_id = sb_id / cdev->num_hwfns; 983fe56b9e6SYuval Mintz 984fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_INTR, 985fe56b9e6SYuval Mintz "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 986fe56b9e6SYuval Mintz hwfn_index, rel_sb_id, sb_id); 987fe56b9e6SYuval Mintz 988fe56b9e6SYuval Mintz rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 989fe56b9e6SYuval Mintz 990fe56b9e6SYuval Mintz return rc; 991fe56b9e6SYuval Mintz } 992fe56b9e6SYuval Mintz 993fe7cd2bfSYuval Mintz static bool qed_can_link_change(struct qed_dev *cdev) 994fe7cd2bfSYuval Mintz { 995fe7cd2bfSYuval Mintz return true; 996fe7cd2bfSYuval Mintz } 997fe7cd2bfSYuval Mintz 998351a4dedSYuval Mintz static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 999cc875c2eSYuval Mintz { 1000cc875c2eSYuval Mintz struct qed_hwfn *hwfn; 1001cc875c2eSYuval Mintz struct qed_mcp_link_params *link_params; 1002cc875c2eSYuval Mintz struct qed_ptt *ptt; 1003cc875c2eSYuval Mintz int rc; 1004cc875c2eSYuval Mintz 1005cc875c2eSYuval Mintz if (!cdev) 1006cc875c2eSYuval Mintz return -ENODEV; 1007cc875c2eSYuval Mintz 10081408cc1fSYuval Mintz if (IS_VF(cdev)) 10091408cc1fSYuval Mintz return 0; 10101408cc1fSYuval Mintz 1011cc875c2eSYuval Mintz /* The link should be set only once per PF */ 1012cc875c2eSYuval Mintz hwfn = &cdev->hwfns[0]; 1013cc875c2eSYuval Mintz 1014cc875c2eSYuval Mintz ptt = qed_ptt_acquire(hwfn); 1015cc875c2eSYuval Mintz if (!ptt) 1016cc875c2eSYuval Mintz return -EBUSY; 1017cc875c2eSYuval Mintz 1018cc875c2eSYuval Mintz link_params = qed_mcp_get_link_params(hwfn); 1019cc875c2eSYuval Mintz if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1020cc875c2eSYuval Mintz link_params->speed.autoneg = params->autoneg; 1021cc875c2eSYuval Mintz if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1022cc875c2eSYuval Mintz link_params->speed.advertised_speeds = 0; 1023cc875c2eSYuval Mintz if ((params->adv_speeds & SUPPORTED_1000baseT_Half) || 1024cc875c2eSYuval Mintz (params->adv_speeds & SUPPORTED_1000baseT_Full)) 1025cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1026cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1027cc875c2eSYuval Mintz if (params->adv_speeds & SUPPORTED_10000baseKR_Full) 1028cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1029cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1030cc875c2eSYuval Mintz if (params->adv_speeds & SUPPORTED_40000baseLR4_Full) 1031cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1032cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1033cc875c2eSYuval Mintz if (params->adv_speeds & 0) 1034cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1035cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1036cc875c2eSYuval Mintz if (params->adv_speeds & 0) 1037cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1038351a4dedSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1039cc875c2eSYuval Mintz } 1040cc875c2eSYuval Mintz if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1041cc875c2eSYuval Mintz link_params->speed.forced_speed = params->forced_speed; 1042a43f235fSSudarsana Reddy Kalluru if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1043a43f235fSSudarsana Reddy Kalluru if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1044a43f235fSSudarsana Reddy Kalluru link_params->pause.autoneg = true; 1045a43f235fSSudarsana Reddy Kalluru else 1046a43f235fSSudarsana Reddy Kalluru link_params->pause.autoneg = false; 1047a43f235fSSudarsana Reddy Kalluru if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1048a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_rx = true; 1049a43f235fSSudarsana Reddy Kalluru else 1050a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_rx = false; 1051a43f235fSSudarsana Reddy Kalluru if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1052a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_tx = true; 1053a43f235fSSudarsana Reddy Kalluru else 1054a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_tx = false; 1055a43f235fSSudarsana Reddy Kalluru } 105603dc76caSSudarsana Reddy Kalluru if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 105703dc76caSSudarsana Reddy Kalluru switch (params->loopback_mode) { 105803dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_INT_PHY: 1059351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 106003dc76caSSudarsana Reddy Kalluru break; 106103dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_EXT_PHY: 1062351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 106303dc76caSSudarsana Reddy Kalluru break; 106403dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_EXT: 1065351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_EXT; 106603dc76caSSudarsana Reddy Kalluru break; 106703dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_MAC: 1068351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_MAC; 106903dc76caSSudarsana Reddy Kalluru break; 107003dc76caSSudarsana Reddy Kalluru default: 1071351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_NONE; 107203dc76caSSudarsana Reddy Kalluru break; 107303dc76caSSudarsana Reddy Kalluru } 107403dc76caSSudarsana Reddy Kalluru } 1075cc875c2eSYuval Mintz 1076cc875c2eSYuval Mintz rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1077cc875c2eSYuval Mintz 1078cc875c2eSYuval Mintz qed_ptt_release(hwfn, ptt); 1079cc875c2eSYuval Mintz 1080cc875c2eSYuval Mintz return rc; 1081cc875c2eSYuval Mintz } 1082cc875c2eSYuval Mintz 1083cc875c2eSYuval Mintz static int qed_get_port_type(u32 media_type) 1084cc875c2eSYuval Mintz { 1085cc875c2eSYuval Mintz int port_type; 1086cc875c2eSYuval Mintz 1087cc875c2eSYuval Mintz switch (media_type) { 1088cc875c2eSYuval Mintz case MEDIA_SFPP_10G_FIBER: 1089cc875c2eSYuval Mintz case MEDIA_SFP_1G_FIBER: 1090cc875c2eSYuval Mintz case MEDIA_XFP_FIBER: 1091cc875c2eSYuval Mintz case MEDIA_KR: 1092cc875c2eSYuval Mintz port_type = PORT_FIBRE; 1093cc875c2eSYuval Mintz break; 1094cc875c2eSYuval Mintz case MEDIA_DA_TWINAX: 1095cc875c2eSYuval Mintz port_type = PORT_DA; 1096cc875c2eSYuval Mintz break; 1097cc875c2eSYuval Mintz case MEDIA_BASE_T: 1098cc875c2eSYuval Mintz port_type = PORT_TP; 1099cc875c2eSYuval Mintz break; 1100cc875c2eSYuval Mintz case MEDIA_NOT_PRESENT: 1101cc875c2eSYuval Mintz port_type = PORT_NONE; 1102cc875c2eSYuval Mintz break; 1103cc875c2eSYuval Mintz case MEDIA_UNSPECIFIED: 1104cc875c2eSYuval Mintz default: 1105cc875c2eSYuval Mintz port_type = PORT_OTHER; 1106cc875c2eSYuval Mintz break; 1107cc875c2eSYuval Mintz } 1108cc875c2eSYuval Mintz return port_type; 1109cc875c2eSYuval Mintz } 1110cc875c2eSYuval Mintz 1111cc875c2eSYuval Mintz static void qed_fill_link(struct qed_hwfn *hwfn, 1112cc875c2eSYuval Mintz struct qed_link_output *if_link) 1113cc875c2eSYuval Mintz { 1114cc875c2eSYuval Mintz struct qed_mcp_link_params params; 1115cc875c2eSYuval Mintz struct qed_mcp_link_state link; 1116cc875c2eSYuval Mintz struct qed_mcp_link_capabilities link_caps; 1117cc875c2eSYuval Mintz u32 media_type; 1118cc875c2eSYuval Mintz 1119cc875c2eSYuval Mintz memset(if_link, 0, sizeof(*if_link)); 1120cc875c2eSYuval Mintz 1121cc875c2eSYuval Mintz /* Prepare source inputs */ 11221408cc1fSYuval Mintz if (IS_PF(hwfn->cdev)) { 1123cc875c2eSYuval Mintz memcpy(¶ms, qed_mcp_get_link_params(hwfn), sizeof(params)); 1124cc875c2eSYuval Mintz memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link)); 1125cc875c2eSYuval Mintz memcpy(&link_caps, qed_mcp_get_link_capabilities(hwfn), 1126cc875c2eSYuval Mintz sizeof(link_caps)); 11271408cc1fSYuval Mintz } else { 112836558c3dSYuval Mintz qed_vf_get_link_params(hwfn, ¶ms); 112936558c3dSYuval Mintz qed_vf_get_link_state(hwfn, &link); 113036558c3dSYuval Mintz qed_vf_get_link_caps(hwfn, &link_caps); 11311408cc1fSYuval Mintz } 1132cc875c2eSYuval Mintz 1133cc875c2eSYuval Mintz /* Set the link parameters to pass to protocol driver */ 1134cc875c2eSYuval Mintz if (link.link_up) 1135cc875c2eSYuval Mintz if_link->link_up = true; 1136cc875c2eSYuval Mintz 1137cc875c2eSYuval Mintz /* TODO - at the moment assume supported and advertised speed equal */ 1138cc875c2eSYuval Mintz if_link->supported_caps = SUPPORTED_FIBRE; 1139cc875c2eSYuval Mintz if (params.speed.autoneg) 1140cc875c2eSYuval Mintz if_link->supported_caps |= SUPPORTED_Autoneg; 1141cc875c2eSYuval Mintz if (params.pause.autoneg || 1142cc875c2eSYuval Mintz (params.pause.forced_rx && params.pause.forced_tx)) 1143cc875c2eSYuval Mintz if_link->supported_caps |= SUPPORTED_Asym_Pause; 1144cc875c2eSYuval Mintz if (params.pause.autoneg || params.pause.forced_rx || 1145cc875c2eSYuval Mintz params.pause.forced_tx) 1146cc875c2eSYuval Mintz if_link->supported_caps |= SUPPORTED_Pause; 1147cc875c2eSYuval Mintz 1148cc875c2eSYuval Mintz if_link->advertised_caps = if_link->supported_caps; 1149cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1150cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1151cc875c2eSYuval Mintz if_link->advertised_caps |= SUPPORTED_1000baseT_Half | 1152cc875c2eSYuval Mintz SUPPORTED_1000baseT_Full; 1153cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1154cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1155cc875c2eSYuval Mintz if_link->advertised_caps |= SUPPORTED_10000baseKR_Full; 1156cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1157cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1158cc875c2eSYuval Mintz if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full; 1159cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1160cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1161cc875c2eSYuval Mintz if_link->advertised_caps |= 0; 1162cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1163351a4dedSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1164cc875c2eSYuval Mintz if_link->advertised_caps |= 0; 1165cc875c2eSYuval Mintz 1166cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1167cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1168cc875c2eSYuval Mintz if_link->supported_caps |= SUPPORTED_1000baseT_Half | 1169cc875c2eSYuval Mintz SUPPORTED_1000baseT_Full; 1170cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1171cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1172cc875c2eSYuval Mintz if_link->supported_caps |= SUPPORTED_10000baseKR_Full; 1173cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1174cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1175cc875c2eSYuval Mintz if_link->supported_caps |= SUPPORTED_40000baseLR4_Full; 1176cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1177cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1178cc875c2eSYuval Mintz if_link->supported_caps |= 0; 1179cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1180351a4dedSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1181cc875c2eSYuval Mintz if_link->supported_caps |= 0; 1182cc875c2eSYuval Mintz 1183cc875c2eSYuval Mintz if (link.link_up) 1184cc875c2eSYuval Mintz if_link->speed = link.speed; 1185cc875c2eSYuval Mintz 1186cc875c2eSYuval Mintz /* TODO - fill duplex properly */ 1187cc875c2eSYuval Mintz if_link->duplex = DUPLEX_FULL; 1188cc875c2eSYuval Mintz qed_mcp_get_media_type(hwfn->cdev, &media_type); 1189cc875c2eSYuval Mintz if_link->port = qed_get_port_type(media_type); 1190cc875c2eSYuval Mintz 1191cc875c2eSYuval Mintz if_link->autoneg = params.speed.autoneg; 1192cc875c2eSYuval Mintz 1193cc875c2eSYuval Mintz if (params.pause.autoneg) 1194cc875c2eSYuval Mintz if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1195cc875c2eSYuval Mintz if (params.pause.forced_rx) 1196cc875c2eSYuval Mintz if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1197cc875c2eSYuval Mintz if (params.pause.forced_tx) 1198cc875c2eSYuval Mintz if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1199cc875c2eSYuval Mintz 1200cc875c2eSYuval Mintz /* Link partner capabilities */ 1201cc875c2eSYuval Mintz if (link.partner_adv_speed & 1202cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_HD) 1203cc875c2eSYuval Mintz if_link->lp_caps |= SUPPORTED_1000baseT_Half; 1204cc875c2eSYuval Mintz if (link.partner_adv_speed & 1205cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_1G_FD) 1206cc875c2eSYuval Mintz if_link->lp_caps |= SUPPORTED_1000baseT_Full; 1207cc875c2eSYuval Mintz if (link.partner_adv_speed & 1208cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_10G) 1209cc875c2eSYuval Mintz if_link->lp_caps |= SUPPORTED_10000baseKR_Full; 1210cc875c2eSYuval Mintz if (link.partner_adv_speed & 1211cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_40G) 1212cc875c2eSYuval Mintz if_link->lp_caps |= SUPPORTED_40000baseLR4_Full; 1213cc875c2eSYuval Mintz if (link.partner_adv_speed & 1214cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_50G) 1215cc875c2eSYuval Mintz if_link->lp_caps |= 0; 1216cc875c2eSYuval Mintz if (link.partner_adv_speed & 1217cc875c2eSYuval Mintz QED_LINK_PARTNER_SPEED_100G) 1218cc875c2eSYuval Mintz if_link->lp_caps |= 0; 1219cc875c2eSYuval Mintz 1220cc875c2eSYuval Mintz if (link.an_complete) 1221cc875c2eSYuval Mintz if_link->lp_caps |= SUPPORTED_Autoneg; 1222cc875c2eSYuval Mintz 1223cc875c2eSYuval Mintz if (link.partner_adv_pause) 1224cc875c2eSYuval Mintz if_link->lp_caps |= SUPPORTED_Pause; 1225cc875c2eSYuval Mintz if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1226cc875c2eSYuval Mintz link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1227cc875c2eSYuval Mintz if_link->lp_caps |= SUPPORTED_Asym_Pause; 1228cc875c2eSYuval Mintz } 1229cc875c2eSYuval Mintz 1230cc875c2eSYuval Mintz static void qed_get_current_link(struct qed_dev *cdev, 1231cc875c2eSYuval Mintz struct qed_link_output *if_link) 1232cc875c2eSYuval Mintz { 123336558c3dSYuval Mintz int i; 123436558c3dSYuval Mintz 1235cc875c2eSYuval Mintz qed_fill_link(&cdev->hwfns[0], if_link); 123636558c3dSYuval Mintz 123736558c3dSYuval Mintz for_each_hwfn(cdev, i) 123836558c3dSYuval Mintz qed_inform_vf_link_state(&cdev->hwfns[i]); 1239cc875c2eSYuval Mintz } 1240cc875c2eSYuval Mintz 1241cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn) 1242cc875c2eSYuval Mintz { 1243cc875c2eSYuval Mintz void *cookie = hwfn->cdev->ops_cookie; 1244cc875c2eSYuval Mintz struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1245cc875c2eSYuval Mintz struct qed_link_output if_link; 1246cc875c2eSYuval Mintz 1247cc875c2eSYuval Mintz qed_fill_link(hwfn, &if_link); 124836558c3dSYuval Mintz qed_inform_vf_link_state(hwfn); 1249cc875c2eSYuval Mintz 1250cc875c2eSYuval Mintz if (IS_LEAD_HWFN(hwfn) && cookie) 1251cc875c2eSYuval Mintz op->link_update(cookie, &if_link); 1252cc875c2eSYuval Mintz } 1253cc875c2eSYuval Mintz 1254fe56b9e6SYuval Mintz static int qed_drain(struct qed_dev *cdev) 1255fe56b9e6SYuval Mintz { 1256fe56b9e6SYuval Mintz struct qed_hwfn *hwfn; 1257fe56b9e6SYuval Mintz struct qed_ptt *ptt; 1258fe56b9e6SYuval Mintz int i, rc; 1259fe56b9e6SYuval Mintz 12601408cc1fSYuval Mintz if (IS_VF(cdev)) 12611408cc1fSYuval Mintz return 0; 12621408cc1fSYuval Mintz 1263fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1264fe56b9e6SYuval Mintz hwfn = &cdev->hwfns[i]; 1265fe56b9e6SYuval Mintz ptt = qed_ptt_acquire(hwfn); 1266fe56b9e6SYuval Mintz if (!ptt) { 1267fe56b9e6SYuval Mintz DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1268fe56b9e6SYuval Mintz return -EBUSY; 1269fe56b9e6SYuval Mintz } 1270fe56b9e6SYuval Mintz rc = qed_mcp_drain(hwfn, ptt); 1271fe56b9e6SYuval Mintz if (rc) 1272fe56b9e6SYuval Mintz return rc; 1273fe56b9e6SYuval Mintz qed_ptt_release(hwfn, ptt); 1274fe56b9e6SYuval Mintz } 1275fe56b9e6SYuval Mintz 1276fe56b9e6SYuval Mintz return 0; 1277fe56b9e6SYuval Mintz } 1278fe56b9e6SYuval Mintz 127991420b83SSudarsana Kalluru static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 128091420b83SSudarsana Kalluru { 128191420b83SSudarsana Kalluru struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 128291420b83SSudarsana Kalluru struct qed_ptt *ptt; 128391420b83SSudarsana Kalluru int status = 0; 128491420b83SSudarsana Kalluru 128591420b83SSudarsana Kalluru ptt = qed_ptt_acquire(hwfn); 128691420b83SSudarsana Kalluru if (!ptt) 128791420b83SSudarsana Kalluru return -EAGAIN; 128891420b83SSudarsana Kalluru 128991420b83SSudarsana Kalluru status = qed_mcp_set_led(hwfn, ptt, mode); 129091420b83SSudarsana Kalluru 129191420b83SSudarsana Kalluru qed_ptt_release(hwfn, ptt); 129291420b83SSudarsana Kalluru 129391420b83SSudarsana Kalluru return status; 129491420b83SSudarsana Kalluru } 129591420b83SSudarsana Kalluru 129603dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops qed_selftest_ops_pass = { 129703dc76caSSudarsana Reddy Kalluru .selftest_memory = &qed_selftest_memory, 129803dc76caSSudarsana Reddy Kalluru .selftest_interrupt = &qed_selftest_interrupt, 129903dc76caSSudarsana Reddy Kalluru .selftest_register = &qed_selftest_register, 130003dc76caSSudarsana Reddy Kalluru .selftest_clock = &qed_selftest_clock, 130103dc76caSSudarsana Reddy Kalluru }; 130203dc76caSSudarsana Reddy Kalluru 1303fe56b9e6SYuval Mintz const struct qed_common_ops qed_common_ops_pass = { 130403dc76caSSudarsana Reddy Kalluru .selftest = &qed_selftest_ops_pass, 1305fe56b9e6SYuval Mintz .probe = &qed_probe, 1306fe56b9e6SYuval Mintz .remove = &qed_remove, 1307fe56b9e6SYuval Mintz .set_power_state = &qed_set_power_state, 1308fe56b9e6SYuval Mintz .set_id = &qed_set_id, 1309fe56b9e6SYuval Mintz .update_pf_params = &qed_update_pf_params, 1310fe56b9e6SYuval Mintz .slowpath_start = &qed_slowpath_start, 1311fe56b9e6SYuval Mintz .slowpath_stop = &qed_slowpath_stop, 1312fe56b9e6SYuval Mintz .set_fp_int = &qed_set_int_fp, 1313fe56b9e6SYuval Mintz .get_fp_int = &qed_get_int_fp, 1314fe56b9e6SYuval Mintz .sb_init = &qed_sb_init, 1315fe56b9e6SYuval Mintz .sb_release = &qed_sb_release, 1316fe56b9e6SYuval Mintz .simd_handler_config = &qed_simd_handler_config, 1317fe56b9e6SYuval Mintz .simd_handler_clean = &qed_simd_handler_clean, 1318fe7cd2bfSYuval Mintz .can_link_change = &qed_can_link_change, 1319cc875c2eSYuval Mintz .set_link = &qed_set_link, 1320cc875c2eSYuval Mintz .get_link = &qed_get_current_link, 1321fe56b9e6SYuval Mintz .drain = &qed_drain, 1322fe56b9e6SYuval Mintz .update_msglvl = &qed_init_dp, 1323fe56b9e6SYuval Mintz .chain_alloc = &qed_chain_alloc, 1324fe56b9e6SYuval Mintz .chain_free = &qed_chain_free, 132591420b83SSudarsana Kalluru .set_led = &qed_set_led, 1326fe56b9e6SYuval Mintz }; 1327