1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/stddef.h> 10fe56b9e6SYuval Mintz #include <linux/pci.h> 11fe56b9e6SYuval Mintz #include <linux/kernel.h> 12fe56b9e6SYuval Mintz #include <linux/slab.h> 13fe56b9e6SYuval Mintz #include <linux/version.h> 14fe56b9e6SYuval Mintz #include <linux/delay.h> 15fe56b9e6SYuval Mintz #include <asm/byteorder.h> 16fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 17fe56b9e6SYuval Mintz #include <linux/string.h> 18fe56b9e6SYuval Mintz #include <linux/module.h> 19fe56b9e6SYuval Mintz #include <linux/interrupt.h> 20fe56b9e6SYuval Mintz #include <linux/workqueue.h> 21fe56b9e6SYuval Mintz #include <linux/ethtool.h> 22fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 23fe56b9e6SYuval Mintz #include <linux/vmalloc.h> 24fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 25fe56b9e6SYuval Mintz 26fe56b9e6SYuval Mintz #include "qed.h" 2737bff2b9SYuval Mintz #include "qed_sriov.h" 28fe56b9e6SYuval Mintz #include "qed_sp.h" 29fe56b9e6SYuval Mintz #include "qed_dev_api.h" 30fe56b9e6SYuval Mintz #include "qed_mcp.h" 31fe56b9e6SYuval Mintz #include "qed_hw.h" 3203dc76caSSudarsana Reddy Kalluru #include "qed_selftest.h" 33fe56b9e6SYuval Mintz 345abd7e92SYuval Mintz static char version[] = 355abd7e92SYuval Mintz "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; 36fe56b9e6SYuval Mintz 375abd7e92SYuval Mintz MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); 38fe56b9e6SYuval Mintz MODULE_LICENSE("GPL"); 39fe56b9e6SYuval Mintz MODULE_VERSION(DRV_MODULE_VERSION); 40fe56b9e6SYuval Mintz 41fe56b9e6SYuval Mintz #define FW_FILE_VERSION \ 42fe56b9e6SYuval Mintz __stringify(FW_MAJOR_VERSION) "." \ 43fe56b9e6SYuval Mintz __stringify(FW_MINOR_VERSION) "." \ 44fe56b9e6SYuval Mintz __stringify(FW_REVISION_VERSION) "." \ 45fe56b9e6SYuval Mintz __stringify(FW_ENGINEERING_VERSION) 46fe56b9e6SYuval Mintz 47fe56b9e6SYuval Mintz #define QED_FW_FILE_NAME \ 48fe56b9e6SYuval Mintz "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" 49fe56b9e6SYuval Mintz 50d43d3f0fSYuval Mintz MODULE_FIRMWARE(QED_FW_FILE_NAME); 51d43d3f0fSYuval Mintz 52fe56b9e6SYuval Mintz static int __init qed_init(void) 53fe56b9e6SYuval Mintz { 54fe56b9e6SYuval Mintz pr_notice("qed_init called\n"); 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz pr_info("%s", version); 57fe56b9e6SYuval Mintz 58fe56b9e6SYuval Mintz return 0; 59fe56b9e6SYuval Mintz } 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz static void __exit qed_cleanup(void) 62fe56b9e6SYuval Mintz { 63fe56b9e6SYuval Mintz pr_notice("qed_cleanup called\n"); 64fe56b9e6SYuval Mintz } 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz module_init(qed_init); 67fe56b9e6SYuval Mintz module_exit(qed_cleanup); 68fe56b9e6SYuval Mintz 69fe56b9e6SYuval Mintz /* Check if the DMA controller on the machine can properly handle the DMA 70fe56b9e6SYuval Mintz * addressing required by the device. 71fe56b9e6SYuval Mintz */ 72fe56b9e6SYuval Mintz static int qed_set_coherency_mask(struct qed_dev *cdev) 73fe56b9e6SYuval Mintz { 74fe56b9e6SYuval Mintz struct device *dev = &cdev->pdev->dev; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 77fe56b9e6SYuval Mintz if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 78fe56b9e6SYuval Mintz DP_NOTICE(cdev, 79fe56b9e6SYuval Mintz "Can't request 64-bit consistent allocations\n"); 80fe56b9e6SYuval Mintz return -EIO; 81fe56b9e6SYuval Mintz } 82fe56b9e6SYuval Mintz } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 83fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); 84fe56b9e6SYuval Mintz return -EIO; 85fe56b9e6SYuval Mintz } 86fe56b9e6SYuval Mintz 87fe56b9e6SYuval Mintz return 0; 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz 90fe56b9e6SYuval Mintz static void qed_free_pci(struct qed_dev *cdev) 91fe56b9e6SYuval Mintz { 92fe56b9e6SYuval Mintz struct pci_dev *pdev = cdev->pdev; 93fe56b9e6SYuval Mintz 94fe56b9e6SYuval Mintz if (cdev->doorbells) 95fe56b9e6SYuval Mintz iounmap(cdev->doorbells); 96fe56b9e6SYuval Mintz if (cdev->regview) 97fe56b9e6SYuval Mintz iounmap(cdev->regview); 98fe56b9e6SYuval Mintz if (atomic_read(&pdev->enable_cnt) == 1) 99fe56b9e6SYuval Mintz pci_release_regions(pdev); 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz pci_disable_device(pdev); 102fe56b9e6SYuval Mintz } 103fe56b9e6SYuval Mintz 1040dfaba6dSYuval Mintz #define PCI_REVISION_ID_ERROR_VAL 0xff 1050dfaba6dSYuval Mintz 106fe56b9e6SYuval Mintz /* Performs PCI initializations as well as initializing PCI-related parameters 107fe56b9e6SYuval Mintz * in the device structrue. Returns 0 in case of success. 108fe56b9e6SYuval Mintz */ 1091a635e48SYuval Mintz static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) 110fe56b9e6SYuval Mintz { 1110dfaba6dSYuval Mintz u8 rev_id; 112fe56b9e6SYuval Mintz int rc; 113fe56b9e6SYuval Mintz 114fe56b9e6SYuval Mintz cdev->pdev = pdev; 115fe56b9e6SYuval Mintz 116fe56b9e6SYuval Mintz rc = pci_enable_device(pdev); 117fe56b9e6SYuval Mintz if (rc) { 118fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot enable PCI device\n"); 119fe56b9e6SYuval Mintz goto err0; 120fe56b9e6SYuval Mintz } 121fe56b9e6SYuval Mintz 122fe56b9e6SYuval Mintz if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 123fe56b9e6SYuval Mintz DP_NOTICE(cdev, "No memory region found in bar #0\n"); 124fe56b9e6SYuval Mintz rc = -EIO; 125fe56b9e6SYuval Mintz goto err1; 126fe56b9e6SYuval Mintz } 127fe56b9e6SYuval Mintz 1281408cc1fSYuval Mintz if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 129fe56b9e6SYuval Mintz DP_NOTICE(cdev, "No memory region found in bar #2\n"); 130fe56b9e6SYuval Mintz rc = -EIO; 131fe56b9e6SYuval Mintz goto err1; 132fe56b9e6SYuval Mintz } 133fe56b9e6SYuval Mintz 134fe56b9e6SYuval Mintz if (atomic_read(&pdev->enable_cnt) == 1) { 135fe56b9e6SYuval Mintz rc = pci_request_regions(pdev, "qed"); 136fe56b9e6SYuval Mintz if (rc) { 137fe56b9e6SYuval Mintz DP_NOTICE(cdev, 138fe56b9e6SYuval Mintz "Failed to request PCI memory resources\n"); 139fe56b9e6SYuval Mintz goto err1; 140fe56b9e6SYuval Mintz } 141fe56b9e6SYuval Mintz pci_set_master(pdev); 142fe56b9e6SYuval Mintz pci_save_state(pdev); 143fe56b9e6SYuval Mintz } 144fe56b9e6SYuval Mintz 1450dfaba6dSYuval Mintz pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 1460dfaba6dSYuval Mintz if (rev_id == PCI_REVISION_ID_ERROR_VAL) { 1470dfaba6dSYuval Mintz DP_NOTICE(cdev, 1480dfaba6dSYuval Mintz "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n", 1490dfaba6dSYuval Mintz rev_id); 1500dfaba6dSYuval Mintz rc = -ENODEV; 1510dfaba6dSYuval Mintz goto err2; 1520dfaba6dSYuval Mintz } 153fe56b9e6SYuval Mintz if (!pci_is_pcie(pdev)) { 154fe56b9e6SYuval Mintz DP_NOTICE(cdev, "The bus is not PCI Express\n"); 155fe56b9e6SYuval Mintz rc = -EIO; 156fe56b9e6SYuval Mintz goto err2; 157fe56b9e6SYuval Mintz } 158fe56b9e6SYuval Mintz 159fe56b9e6SYuval Mintz cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 160416cdf06SYuval Mintz if (IS_PF(cdev) && !cdev->pci_params.pm_cap) 161fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot find power management capability\n"); 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz rc = qed_set_coherency_mask(cdev); 164fe56b9e6SYuval Mintz if (rc) 165fe56b9e6SYuval Mintz goto err2; 166fe56b9e6SYuval Mintz 167fe56b9e6SYuval Mintz cdev->pci_params.mem_start = pci_resource_start(pdev, 0); 168fe56b9e6SYuval Mintz cdev->pci_params.mem_end = pci_resource_end(pdev, 0); 169fe56b9e6SYuval Mintz cdev->pci_params.irq = pdev->irq; 170fe56b9e6SYuval Mintz 171fe56b9e6SYuval Mintz cdev->regview = pci_ioremap_bar(pdev, 0); 172fe56b9e6SYuval Mintz if (!cdev->regview) { 173fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot map register space, aborting\n"); 174fe56b9e6SYuval Mintz rc = -ENOMEM; 175fe56b9e6SYuval Mintz goto err2; 176fe56b9e6SYuval Mintz } 177fe56b9e6SYuval Mintz 1781408cc1fSYuval Mintz if (IS_PF(cdev)) { 179fe56b9e6SYuval Mintz cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); 180fe56b9e6SYuval Mintz cdev->db_size = pci_resource_len(cdev->pdev, 2); 181fe56b9e6SYuval Mintz cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); 182fe56b9e6SYuval Mintz if (!cdev->doorbells) { 183fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Cannot map doorbell space\n"); 184fe56b9e6SYuval Mintz return -ENOMEM; 185fe56b9e6SYuval Mintz } 1861408cc1fSYuval Mintz } 187fe56b9e6SYuval Mintz 188fe56b9e6SYuval Mintz return 0; 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz err2: 191fe56b9e6SYuval Mintz pci_release_regions(pdev); 192fe56b9e6SYuval Mintz err1: 193fe56b9e6SYuval Mintz pci_disable_device(pdev); 194fe56b9e6SYuval Mintz err0: 195fe56b9e6SYuval Mintz return rc; 196fe56b9e6SYuval Mintz } 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 199fe56b9e6SYuval Mintz struct qed_dev_info *dev_info) 200fe56b9e6SYuval Mintz { 201cee4d264SManish Chopra struct qed_ptt *ptt; 202cee4d264SManish Chopra 203fe56b9e6SYuval Mintz memset(dev_info, 0, sizeof(struct qed_dev_info)); 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz dev_info->num_hwfns = cdev->num_hwfns; 206fe56b9e6SYuval Mintz dev_info->pci_mem_start = cdev->pci_params.mem_start; 207fe56b9e6SYuval Mintz dev_info->pci_mem_end = cdev->pci_params.mem_end; 208fe56b9e6SYuval Mintz dev_info->pci_irq = cdev->pci_params.irq; 209c5ac9319SYuval Mintz dev_info->rdma_supported = 210c5ac9319SYuval Mintz (cdev->hwfns[0].hw_info.personality == QED_PCI_ETH_ROCE); 211fc48b7a6SYuval Mintz dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]); 212fe56b9e6SYuval Mintz ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr); 213fe56b9e6SYuval Mintz 2141408cc1fSYuval Mintz if (IS_PF(cdev)) { 215fe56b9e6SYuval Mintz dev_info->fw_major = FW_MAJOR_VERSION; 216fe56b9e6SYuval Mintz dev_info->fw_minor = FW_MINOR_VERSION; 217fe56b9e6SYuval Mintz dev_info->fw_rev = FW_REVISION_VERSION; 218fe56b9e6SYuval Mintz dev_info->fw_eng = FW_ENGINEERING_VERSION; 219fe56b9e6SYuval Mintz dev_info->mf_mode = cdev->mf_mode; 220831bfb0eSYuval Mintz dev_info->tx_switching = true; 2211408cc1fSYuval Mintz } else { 2221408cc1fSYuval Mintz qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, 2231408cc1fSYuval Mintz &dev_info->fw_minor, &dev_info->fw_rev, 2241408cc1fSYuval Mintz &dev_info->fw_eng); 2251408cc1fSYuval Mintz } 226fe56b9e6SYuval Mintz 2271408cc1fSYuval Mintz if (IS_PF(cdev)) { 228cee4d264SManish Chopra ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); 229cee4d264SManish Chopra if (ptt) { 2301408cc1fSYuval Mintz qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, 2311408cc1fSYuval Mintz &dev_info->mfw_rev, NULL); 2321408cc1fSYuval Mintz 233cee4d264SManish Chopra qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, 234cee4d264SManish Chopra &dev_info->flash_size); 235cee4d264SManish Chopra 236cee4d264SManish Chopra qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); 237cee4d264SManish Chopra } 2381408cc1fSYuval Mintz } else { 2391408cc1fSYuval Mintz qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, 2401408cc1fSYuval Mintz &dev_info->mfw_rev, NULL); 2411408cc1fSYuval Mintz } 242cee4d264SManish Chopra 243fe56b9e6SYuval Mintz return 0; 244fe56b9e6SYuval Mintz } 245fe56b9e6SYuval Mintz 246fe56b9e6SYuval Mintz static void qed_free_cdev(struct qed_dev *cdev) 247fe56b9e6SYuval Mintz { 248fe56b9e6SYuval Mintz kfree((void *)cdev); 249fe56b9e6SYuval Mintz } 250fe56b9e6SYuval Mintz 251fe56b9e6SYuval Mintz static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) 252fe56b9e6SYuval Mintz { 253fe56b9e6SYuval Mintz struct qed_dev *cdev; 254fe56b9e6SYuval Mintz 255fe56b9e6SYuval Mintz cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); 256fe56b9e6SYuval Mintz if (!cdev) 257fe56b9e6SYuval Mintz return cdev; 258fe56b9e6SYuval Mintz 259fe56b9e6SYuval Mintz qed_init_struct(cdev); 260fe56b9e6SYuval Mintz 261fe56b9e6SYuval Mintz return cdev; 262fe56b9e6SYuval Mintz } 263fe56b9e6SYuval Mintz 264fe56b9e6SYuval Mintz /* Sets the requested power state */ 2651a635e48SYuval Mintz static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) 266fe56b9e6SYuval Mintz { 267fe56b9e6SYuval Mintz if (!cdev) 268fe56b9e6SYuval Mintz return -ENODEV; 269fe56b9e6SYuval Mintz 270fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); 271fe56b9e6SYuval Mintz return 0; 272fe56b9e6SYuval Mintz } 273fe56b9e6SYuval Mintz 274fe56b9e6SYuval Mintz /* probing */ 275fe56b9e6SYuval Mintz static struct qed_dev *qed_probe(struct pci_dev *pdev, 2761408cc1fSYuval Mintz struct qed_probe_params *params) 277fe56b9e6SYuval Mintz { 278fe56b9e6SYuval Mintz struct qed_dev *cdev; 279fe56b9e6SYuval Mintz int rc; 280fe56b9e6SYuval Mintz 281fe56b9e6SYuval Mintz cdev = qed_alloc_cdev(pdev); 282fe56b9e6SYuval Mintz if (!cdev) 283fe56b9e6SYuval Mintz goto err0; 284fe56b9e6SYuval Mintz 2851408cc1fSYuval Mintz cdev->protocol = params->protocol; 286fe56b9e6SYuval Mintz 2871408cc1fSYuval Mintz if (params->is_vf) 2881408cc1fSYuval Mintz cdev->b_is_vf = true; 2891408cc1fSYuval Mintz 2901408cc1fSYuval Mintz qed_init_dp(cdev, params->dp_module, params->dp_level); 291fe56b9e6SYuval Mintz 292fe56b9e6SYuval Mintz rc = qed_init_pci(cdev, pdev); 293fe56b9e6SYuval Mintz if (rc) { 294fe56b9e6SYuval Mintz DP_ERR(cdev, "init pci failed\n"); 295fe56b9e6SYuval Mintz goto err1; 296fe56b9e6SYuval Mintz } 297fe56b9e6SYuval Mintz DP_INFO(cdev, "PCI init completed successfully\n"); 298fe56b9e6SYuval Mintz 299fe56b9e6SYuval Mintz rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT); 300fe56b9e6SYuval Mintz if (rc) { 301fe56b9e6SYuval Mintz DP_ERR(cdev, "hw prepare failed\n"); 302fe56b9e6SYuval Mintz goto err2; 303fe56b9e6SYuval Mintz } 304fe56b9e6SYuval Mintz 305fe56b9e6SYuval Mintz DP_INFO(cdev, "qed_probe completed successffuly\n"); 306fe56b9e6SYuval Mintz 307fe56b9e6SYuval Mintz return cdev; 308fe56b9e6SYuval Mintz 309fe56b9e6SYuval Mintz err2: 310fe56b9e6SYuval Mintz qed_free_pci(cdev); 311fe56b9e6SYuval Mintz err1: 312fe56b9e6SYuval Mintz qed_free_cdev(cdev); 313fe56b9e6SYuval Mintz err0: 314fe56b9e6SYuval Mintz return NULL; 315fe56b9e6SYuval Mintz } 316fe56b9e6SYuval Mintz 317fe56b9e6SYuval Mintz static void qed_remove(struct qed_dev *cdev) 318fe56b9e6SYuval Mintz { 319fe56b9e6SYuval Mintz if (!cdev) 320fe56b9e6SYuval Mintz return; 321fe56b9e6SYuval Mintz 322fe56b9e6SYuval Mintz qed_hw_remove(cdev); 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz qed_free_pci(cdev); 325fe56b9e6SYuval Mintz 326fe56b9e6SYuval Mintz qed_set_power_state(cdev, PCI_D3hot); 327fe56b9e6SYuval Mintz 328fe56b9e6SYuval Mintz qed_free_cdev(cdev); 329fe56b9e6SYuval Mintz } 330fe56b9e6SYuval Mintz 331fe56b9e6SYuval Mintz static void qed_disable_msix(struct qed_dev *cdev) 332fe56b9e6SYuval Mintz { 333fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 334fe56b9e6SYuval Mintz pci_disable_msix(cdev->pdev); 335fe56b9e6SYuval Mintz kfree(cdev->int_params.msix_table); 336fe56b9e6SYuval Mintz } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { 337fe56b9e6SYuval Mintz pci_disable_msi(cdev->pdev); 338fe56b9e6SYuval Mintz } 339fe56b9e6SYuval Mintz 340fe56b9e6SYuval Mintz memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); 341fe56b9e6SYuval Mintz } 342fe56b9e6SYuval Mintz 343fe56b9e6SYuval Mintz static int qed_enable_msix(struct qed_dev *cdev, 344fe56b9e6SYuval Mintz struct qed_int_params *int_params) 345fe56b9e6SYuval Mintz { 346fe56b9e6SYuval Mintz int i, rc, cnt; 347fe56b9e6SYuval Mintz 348fe56b9e6SYuval Mintz cnt = int_params->in.num_vectors; 349fe56b9e6SYuval Mintz 350fe56b9e6SYuval Mintz for (i = 0; i < cnt; i++) 351fe56b9e6SYuval Mintz int_params->msix_table[i].entry = i; 352fe56b9e6SYuval Mintz 353fe56b9e6SYuval Mintz rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, 354fe56b9e6SYuval Mintz int_params->in.min_msix_cnt, cnt); 355fe56b9e6SYuval Mintz if (rc < cnt && rc >= int_params->in.min_msix_cnt && 356fe56b9e6SYuval Mintz (rc % cdev->num_hwfns)) { 357fe56b9e6SYuval Mintz pci_disable_msix(cdev->pdev); 358fe56b9e6SYuval Mintz 359fe56b9e6SYuval Mintz /* If fastpath is initialized, we need at least one interrupt 360fe56b9e6SYuval Mintz * per hwfn [and the slow path interrupts]. New requested number 361fe56b9e6SYuval Mintz * should be a multiple of the number of hwfns. 362fe56b9e6SYuval Mintz */ 363fe56b9e6SYuval Mintz cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; 364fe56b9e6SYuval Mintz DP_NOTICE(cdev, 365fe56b9e6SYuval Mintz "Trying to enable MSI-X with less vectors (%d out of %d)\n", 366fe56b9e6SYuval Mintz cnt, int_params->in.num_vectors); 3671a635e48SYuval Mintz rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, 3681a635e48SYuval Mintz cnt); 369fe56b9e6SYuval Mintz if (!rc) 370fe56b9e6SYuval Mintz rc = cnt; 371fe56b9e6SYuval Mintz } 372fe56b9e6SYuval Mintz 373fe56b9e6SYuval Mintz if (rc > 0) { 374fe56b9e6SYuval Mintz /* MSI-x configuration was achieved */ 375fe56b9e6SYuval Mintz int_params->out.int_mode = QED_INT_MODE_MSIX; 376fe56b9e6SYuval Mintz int_params->out.num_vectors = rc; 377fe56b9e6SYuval Mintz rc = 0; 378fe56b9e6SYuval Mintz } else { 379fe56b9e6SYuval Mintz DP_NOTICE(cdev, 380fe56b9e6SYuval Mintz "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", 381fe56b9e6SYuval Mintz cnt, rc); 382fe56b9e6SYuval Mintz } 383fe56b9e6SYuval Mintz 384fe56b9e6SYuval Mintz return rc; 385fe56b9e6SYuval Mintz } 386fe56b9e6SYuval Mintz 387fe56b9e6SYuval Mintz /* This function outputs the int mode and the number of enabled msix vector */ 388fe56b9e6SYuval Mintz static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) 389fe56b9e6SYuval Mintz { 390fe56b9e6SYuval Mintz struct qed_int_params *int_params = &cdev->int_params; 391fe56b9e6SYuval Mintz struct msix_entry *tbl; 392fe56b9e6SYuval Mintz int rc = 0, cnt; 393fe56b9e6SYuval Mintz 394fe56b9e6SYuval Mintz switch (int_params->in.int_mode) { 395fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 396fe56b9e6SYuval Mintz /* Allocate MSIX table */ 397fe56b9e6SYuval Mintz cnt = int_params->in.num_vectors; 398fe56b9e6SYuval Mintz int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); 399fe56b9e6SYuval Mintz if (!int_params->msix_table) { 400fe56b9e6SYuval Mintz rc = -ENOMEM; 401fe56b9e6SYuval Mintz goto out; 402fe56b9e6SYuval Mintz } 403fe56b9e6SYuval Mintz 404fe56b9e6SYuval Mintz /* Enable MSIX */ 405fe56b9e6SYuval Mintz rc = qed_enable_msix(cdev, int_params); 406fe56b9e6SYuval Mintz if (!rc) 407fe56b9e6SYuval Mintz goto out; 408fe56b9e6SYuval Mintz 409fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed to enable MSI-X\n"); 410fe56b9e6SYuval Mintz kfree(int_params->msix_table); 411fe56b9e6SYuval Mintz if (force_mode) 412fe56b9e6SYuval Mintz goto out; 413fe56b9e6SYuval Mintz /* Fallthrough */ 414fe56b9e6SYuval Mintz 415fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 416bb13ace7SSudarsana Reddy Kalluru if (cdev->num_hwfns == 1) { 417fe56b9e6SYuval Mintz rc = pci_enable_msi(cdev->pdev); 418fe56b9e6SYuval Mintz if (!rc) { 419fe56b9e6SYuval Mintz int_params->out.int_mode = QED_INT_MODE_MSI; 420fe56b9e6SYuval Mintz goto out; 421fe56b9e6SYuval Mintz } 422fe56b9e6SYuval Mintz 423fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed to enable MSI\n"); 424fe56b9e6SYuval Mintz if (force_mode) 425fe56b9e6SYuval Mintz goto out; 426bb13ace7SSudarsana Reddy Kalluru } 427fe56b9e6SYuval Mintz /* Fallthrough */ 428fe56b9e6SYuval Mintz 429fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 430fe56b9e6SYuval Mintz int_params->out.int_mode = QED_INT_MODE_INTA; 431fe56b9e6SYuval Mintz rc = 0; 432fe56b9e6SYuval Mintz goto out; 433fe56b9e6SYuval Mintz default: 434fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Unknown int_mode value %d\n", 435fe56b9e6SYuval Mintz int_params->in.int_mode); 436fe56b9e6SYuval Mintz rc = -EINVAL; 437fe56b9e6SYuval Mintz } 438fe56b9e6SYuval Mintz 439fe56b9e6SYuval Mintz out: 440fe56b9e6SYuval Mintz cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; 441fe56b9e6SYuval Mintz 442fe56b9e6SYuval Mintz return rc; 443fe56b9e6SYuval Mintz } 444fe56b9e6SYuval Mintz 445fe56b9e6SYuval Mintz static void qed_simd_handler_config(struct qed_dev *cdev, void *token, 446fe56b9e6SYuval Mintz int index, void(*handler)(void *)) 447fe56b9e6SYuval Mintz { 448fe56b9e6SYuval Mintz struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 449fe56b9e6SYuval Mintz int relative_idx = index / cdev->num_hwfns; 450fe56b9e6SYuval Mintz 451fe56b9e6SYuval Mintz hwfn->simd_proto_handler[relative_idx].func = handler; 452fe56b9e6SYuval Mintz hwfn->simd_proto_handler[relative_idx].token = token; 453fe56b9e6SYuval Mintz } 454fe56b9e6SYuval Mintz 455fe56b9e6SYuval Mintz static void qed_simd_handler_clean(struct qed_dev *cdev, int index) 456fe56b9e6SYuval Mintz { 457fe56b9e6SYuval Mintz struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; 458fe56b9e6SYuval Mintz int relative_idx = index / cdev->num_hwfns; 459fe56b9e6SYuval Mintz 460fe56b9e6SYuval Mintz memset(&hwfn->simd_proto_handler[relative_idx], 0, 461fe56b9e6SYuval Mintz sizeof(struct qed_simd_fp_handler)); 462fe56b9e6SYuval Mintz } 463fe56b9e6SYuval Mintz 464fe56b9e6SYuval Mintz static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) 465fe56b9e6SYuval Mintz { 466fe56b9e6SYuval Mintz tasklet_schedule((struct tasklet_struct *)tasklet); 467fe56b9e6SYuval Mintz return IRQ_HANDLED; 468fe56b9e6SYuval Mintz } 469fe56b9e6SYuval Mintz 470fe56b9e6SYuval Mintz static irqreturn_t qed_single_int(int irq, void *dev_instance) 471fe56b9e6SYuval Mintz { 472fe56b9e6SYuval Mintz struct qed_dev *cdev = (struct qed_dev *)dev_instance; 473fe56b9e6SYuval Mintz struct qed_hwfn *hwfn; 474fe56b9e6SYuval Mintz irqreturn_t rc = IRQ_NONE; 475fe56b9e6SYuval Mintz u64 status; 476fe56b9e6SYuval Mintz int i, j; 477fe56b9e6SYuval Mintz 478fe56b9e6SYuval Mintz for (i = 0; i < cdev->num_hwfns; i++) { 479fe56b9e6SYuval Mintz status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); 480fe56b9e6SYuval Mintz 481fe56b9e6SYuval Mintz if (!status) 482fe56b9e6SYuval Mintz continue; 483fe56b9e6SYuval Mintz 484fe56b9e6SYuval Mintz hwfn = &cdev->hwfns[i]; 485fe56b9e6SYuval Mintz 486fe56b9e6SYuval Mintz /* Slowpath interrupt */ 487fe56b9e6SYuval Mintz if (unlikely(status & 0x1)) { 488fe56b9e6SYuval Mintz tasklet_schedule(hwfn->sp_dpc); 489fe56b9e6SYuval Mintz status &= ~0x1; 490fe56b9e6SYuval Mintz rc = IRQ_HANDLED; 491fe56b9e6SYuval Mintz } 492fe56b9e6SYuval Mintz 493fe56b9e6SYuval Mintz /* Fastpath interrupts */ 494fe56b9e6SYuval Mintz for (j = 0; j < 64; j++) { 495fe56b9e6SYuval Mintz if ((0x2ULL << j) & status) { 496fe56b9e6SYuval Mintz hwfn->simd_proto_handler[j].func( 497fe56b9e6SYuval Mintz hwfn->simd_proto_handler[j].token); 498fe56b9e6SYuval Mintz status &= ~(0x2ULL << j); 499fe56b9e6SYuval Mintz rc = IRQ_HANDLED; 500fe56b9e6SYuval Mintz } 501fe56b9e6SYuval Mintz } 502fe56b9e6SYuval Mintz 503fe56b9e6SYuval Mintz if (unlikely(status)) 504fe56b9e6SYuval Mintz DP_VERBOSE(hwfn, NETIF_MSG_INTR, 505fe56b9e6SYuval Mintz "got an unknown interrupt status 0x%llx\n", 506fe56b9e6SYuval Mintz status); 507fe56b9e6SYuval Mintz } 508fe56b9e6SYuval Mintz 509fe56b9e6SYuval Mintz return rc; 510fe56b9e6SYuval Mintz } 511fe56b9e6SYuval Mintz 5128f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn) 513fe56b9e6SYuval Mintz { 5148f16bc97SSudarsana Kalluru struct qed_dev *cdev = hwfn->cdev; 5158f16bc97SSudarsana Kalluru int rc = 0; 5168f16bc97SSudarsana Kalluru u8 id; 517fe56b9e6SYuval Mintz 518fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 5198f16bc97SSudarsana Kalluru id = hwfn->my_id; 5208f16bc97SSudarsana Kalluru snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", 5218f16bc97SSudarsana Kalluru id, cdev->pdev->bus->number, 5228f16bc97SSudarsana Kalluru PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); 5238f16bc97SSudarsana Kalluru rc = request_irq(cdev->int_params.msix_table[id].vector, 5248f16bc97SSudarsana Kalluru qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); 5258f16bc97SSudarsana Kalluru if (!rc) 5268f16bc97SSudarsana Kalluru DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), 527fe56b9e6SYuval Mintz "Requested slowpath MSI-X\n"); 528fe56b9e6SYuval Mintz } else { 529fe56b9e6SYuval Mintz unsigned long flags = 0; 530fe56b9e6SYuval Mintz 531fe56b9e6SYuval Mintz snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", 532fe56b9e6SYuval Mintz cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), 533fe56b9e6SYuval Mintz PCI_FUNC(cdev->pdev->devfn)); 534fe56b9e6SYuval Mintz 535fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) 536fe56b9e6SYuval Mintz flags |= IRQF_SHARED; 537fe56b9e6SYuval Mintz 538fe56b9e6SYuval Mintz rc = request_irq(cdev->pdev->irq, qed_single_int, 539fe56b9e6SYuval Mintz flags, cdev->name, cdev); 540fe56b9e6SYuval Mintz } 541fe56b9e6SYuval Mintz 542fe56b9e6SYuval Mintz return rc; 543fe56b9e6SYuval Mintz } 544fe56b9e6SYuval Mintz 545fe56b9e6SYuval Mintz static void qed_slowpath_irq_free(struct qed_dev *cdev) 546fe56b9e6SYuval Mintz { 547fe56b9e6SYuval Mintz int i; 548fe56b9e6SYuval Mintz 549fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 550fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 5518f16bc97SSudarsana Kalluru if (!cdev->hwfns[i].b_int_requested) 5528f16bc97SSudarsana Kalluru break; 553fe56b9e6SYuval Mintz synchronize_irq(cdev->int_params.msix_table[i].vector); 554fe56b9e6SYuval Mintz free_irq(cdev->int_params.msix_table[i].vector, 555fe56b9e6SYuval Mintz cdev->hwfns[i].sp_dpc); 556fe56b9e6SYuval Mintz } 557fe56b9e6SYuval Mintz } else { 5588f16bc97SSudarsana Kalluru if (QED_LEADING_HWFN(cdev)->b_int_requested) 559fe56b9e6SYuval Mintz free_irq(cdev->pdev->irq, cdev); 560fe56b9e6SYuval Mintz } 5618f16bc97SSudarsana Kalluru qed_int_disable_post_isr_release(cdev); 562fe56b9e6SYuval Mintz } 563fe56b9e6SYuval Mintz 564fe56b9e6SYuval Mintz static int qed_nic_stop(struct qed_dev *cdev) 565fe56b9e6SYuval Mintz { 566fe56b9e6SYuval Mintz int i, rc; 567fe56b9e6SYuval Mintz 568fe56b9e6SYuval Mintz rc = qed_hw_stop(cdev); 569fe56b9e6SYuval Mintz 570fe56b9e6SYuval Mintz for (i = 0; i < cdev->num_hwfns; i++) { 571fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 572fe56b9e6SYuval Mintz 573fe56b9e6SYuval Mintz if (p_hwfn->b_sp_dpc_enabled) { 574fe56b9e6SYuval Mintz tasklet_disable(p_hwfn->sp_dpc); 575fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = false; 576fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, 577fe56b9e6SYuval Mintz "Disabled sp taskelt [hwfn %d] at %p\n", 578fe56b9e6SYuval Mintz i, p_hwfn->sp_dpc); 579fe56b9e6SYuval Mintz } 580fe56b9e6SYuval Mintz } 581fe56b9e6SYuval Mintz 582fe56b9e6SYuval Mintz return rc; 583fe56b9e6SYuval Mintz } 584fe56b9e6SYuval Mintz 585fe56b9e6SYuval Mintz static int qed_nic_reset(struct qed_dev *cdev) 586fe56b9e6SYuval Mintz { 587fe56b9e6SYuval Mintz int rc; 588fe56b9e6SYuval Mintz 589fe56b9e6SYuval Mintz rc = qed_hw_reset(cdev); 590fe56b9e6SYuval Mintz if (rc) 591fe56b9e6SYuval Mintz return rc; 592fe56b9e6SYuval Mintz 593fe56b9e6SYuval Mintz qed_resc_free(cdev); 594fe56b9e6SYuval Mintz 595fe56b9e6SYuval Mintz return 0; 596fe56b9e6SYuval Mintz } 597fe56b9e6SYuval Mintz 598fe56b9e6SYuval Mintz static int qed_nic_setup(struct qed_dev *cdev) 599fe56b9e6SYuval Mintz { 600fe56b9e6SYuval Mintz int rc; 601fe56b9e6SYuval Mintz 602fe56b9e6SYuval Mintz rc = qed_resc_alloc(cdev); 603fe56b9e6SYuval Mintz if (rc) 604fe56b9e6SYuval Mintz return rc; 605fe56b9e6SYuval Mintz 606fe56b9e6SYuval Mintz DP_INFO(cdev, "Allocated qed resources\n"); 607fe56b9e6SYuval Mintz 608fe56b9e6SYuval Mintz qed_resc_setup(cdev); 609fe56b9e6SYuval Mintz 610fe56b9e6SYuval Mintz return rc; 611fe56b9e6SYuval Mintz } 612fe56b9e6SYuval Mintz 613fe56b9e6SYuval Mintz static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) 614fe56b9e6SYuval Mintz { 615fe56b9e6SYuval Mintz int limit = 0; 616fe56b9e6SYuval Mintz 617fe56b9e6SYuval Mintz /* Mark the fastpath as free/used */ 618fe56b9e6SYuval Mintz cdev->int_params.fp_initialized = cnt ? true : false; 619fe56b9e6SYuval Mintz 620fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) 621fe56b9e6SYuval Mintz limit = cdev->num_hwfns * 63; 622fe56b9e6SYuval Mintz else if (cdev->int_params.fp_msix_cnt) 623fe56b9e6SYuval Mintz limit = cdev->int_params.fp_msix_cnt; 624fe56b9e6SYuval Mintz 625fe56b9e6SYuval Mintz if (!limit) 626fe56b9e6SYuval Mintz return -ENOMEM; 627fe56b9e6SYuval Mintz 628fe56b9e6SYuval Mintz return min_t(int, cnt, limit); 629fe56b9e6SYuval Mintz } 630fe56b9e6SYuval Mintz 631fe56b9e6SYuval Mintz static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 632fe56b9e6SYuval Mintz { 633fe56b9e6SYuval Mintz memset(info, 0, sizeof(struct qed_int_info)); 634fe56b9e6SYuval Mintz 635fe56b9e6SYuval Mintz if (!cdev->int_params.fp_initialized) { 636fe56b9e6SYuval Mintz DP_INFO(cdev, 637fe56b9e6SYuval Mintz "Protocol driver requested interrupt information, but its support is not yet configured\n"); 638fe56b9e6SYuval Mintz return -EINVAL; 639fe56b9e6SYuval Mintz } 640fe56b9e6SYuval Mintz 641fe56b9e6SYuval Mintz /* Need to expose only MSI-X information; Single IRQ is handled solely 642fe56b9e6SYuval Mintz * by qed. 643fe56b9e6SYuval Mintz */ 644fe56b9e6SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 645fe56b9e6SYuval Mintz int msix_base = cdev->int_params.fp_msix_base; 646fe56b9e6SYuval Mintz 647fe56b9e6SYuval Mintz info->msix_cnt = cdev->int_params.fp_msix_cnt; 648fe56b9e6SYuval Mintz info->msix = &cdev->int_params.msix_table[msix_base]; 649fe56b9e6SYuval Mintz } 650fe56b9e6SYuval Mintz 651fe56b9e6SYuval Mintz return 0; 652fe56b9e6SYuval Mintz } 653fe56b9e6SYuval Mintz 654fe56b9e6SYuval Mintz static int qed_slowpath_setup_int(struct qed_dev *cdev, 655fe56b9e6SYuval Mintz enum qed_int_mode int_mode) 656fe56b9e6SYuval Mintz { 6574ac801b7SYuval Mintz struct qed_sb_cnt_info sb_cnt_info; 6584ac801b7SYuval Mintz int rc; 6594ac801b7SYuval Mintz int i; 660fe56b9e6SYuval Mintz 6611d2c2024SSudarsana Reddy Kalluru if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 6621d2c2024SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 6631d2c2024SSudarsana Reddy Kalluru return -EINVAL; 6641d2c2024SSudarsana Reddy Kalluru } 6651d2c2024SSudarsana Reddy Kalluru 6661d2c2024SSudarsana Reddy Kalluru memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 667fe56b9e6SYuval Mintz cdev->int_params.in.int_mode = int_mode; 6684ac801b7SYuval Mintz for_each_hwfn(cdev, i) { 6694ac801b7SYuval Mintz memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 6704ac801b7SYuval Mintz qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); 6714ac801b7SYuval Mintz cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt; 6724ac801b7SYuval Mintz cdev->int_params.in.num_vectors++; /* slowpath */ 6734ac801b7SYuval Mintz } 674fe56b9e6SYuval Mintz 675fe56b9e6SYuval Mintz /* We want a minimum of one slowpath and one fastpath vector per hwfn */ 676fe56b9e6SYuval Mintz cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; 677fe56b9e6SYuval Mintz 678fe56b9e6SYuval Mintz rc = qed_set_int_mode(cdev, false); 679fe56b9e6SYuval Mintz if (rc) { 680fe56b9e6SYuval Mintz DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); 681fe56b9e6SYuval Mintz return rc; 682fe56b9e6SYuval Mintz } 683fe56b9e6SYuval Mintz 684fe56b9e6SYuval Mintz cdev->int_params.fp_msix_base = cdev->num_hwfns; 685fe56b9e6SYuval Mintz cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - 686fe56b9e6SYuval Mintz cdev->num_hwfns; 687fe56b9e6SYuval Mintz 688fe56b9e6SYuval Mintz return 0; 689fe56b9e6SYuval Mintz } 690fe56b9e6SYuval Mintz 6911408cc1fSYuval Mintz static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) 6921408cc1fSYuval Mintz { 6931408cc1fSYuval Mintz int rc; 6941408cc1fSYuval Mintz 6951408cc1fSYuval Mintz memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); 6961408cc1fSYuval Mintz cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; 6971408cc1fSYuval Mintz 6981408cc1fSYuval Mintz qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), 6991408cc1fSYuval Mintz &cdev->int_params.in.num_vectors); 7001408cc1fSYuval Mintz if (cdev->num_hwfns > 1) { 7011408cc1fSYuval Mintz u8 vectors = 0; 7021408cc1fSYuval Mintz 7031408cc1fSYuval Mintz qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); 7041408cc1fSYuval Mintz cdev->int_params.in.num_vectors += vectors; 7051408cc1fSYuval Mintz } 7061408cc1fSYuval Mintz 7071408cc1fSYuval Mintz /* We want a minimum of one fastpath vector per vf hwfn */ 7081408cc1fSYuval Mintz cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; 7091408cc1fSYuval Mintz 7101408cc1fSYuval Mintz rc = qed_set_int_mode(cdev, true); 7111408cc1fSYuval Mintz if (rc) 7121408cc1fSYuval Mintz return rc; 7131408cc1fSYuval Mintz 7141408cc1fSYuval Mintz cdev->int_params.fp_msix_base = 0; 7151408cc1fSYuval Mintz cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; 7161408cc1fSYuval Mintz 7171408cc1fSYuval Mintz return 0; 7181408cc1fSYuval Mintz } 7191408cc1fSYuval Mintz 720fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, 721fe56b9e6SYuval Mintz u8 *input_buf, u32 max_size, u8 *unzip_buf) 722fe56b9e6SYuval Mintz { 723fe56b9e6SYuval Mintz int rc; 724fe56b9e6SYuval Mintz 725fe56b9e6SYuval Mintz p_hwfn->stream->next_in = input_buf; 726fe56b9e6SYuval Mintz p_hwfn->stream->avail_in = input_len; 727fe56b9e6SYuval Mintz p_hwfn->stream->next_out = unzip_buf; 728fe56b9e6SYuval Mintz p_hwfn->stream->avail_out = max_size; 729fe56b9e6SYuval Mintz 730fe56b9e6SYuval Mintz rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); 731fe56b9e6SYuval Mintz 732fe56b9e6SYuval Mintz if (rc != Z_OK) { 733fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", 734fe56b9e6SYuval Mintz rc); 735fe56b9e6SYuval Mintz return 0; 736fe56b9e6SYuval Mintz } 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz rc = zlib_inflate(p_hwfn->stream, Z_FINISH); 739fe56b9e6SYuval Mintz zlib_inflateEnd(p_hwfn->stream); 740fe56b9e6SYuval Mintz 741fe56b9e6SYuval Mintz if (rc != Z_OK && rc != Z_STREAM_END) { 742fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", 743fe56b9e6SYuval Mintz p_hwfn->stream->msg, rc); 744fe56b9e6SYuval Mintz return 0; 745fe56b9e6SYuval Mintz } 746fe56b9e6SYuval Mintz 747fe56b9e6SYuval Mintz return p_hwfn->stream->total_out / 4; 748fe56b9e6SYuval Mintz } 749fe56b9e6SYuval Mintz 750fe56b9e6SYuval Mintz static int qed_alloc_stream_mem(struct qed_dev *cdev) 751fe56b9e6SYuval Mintz { 752fe56b9e6SYuval Mintz int i; 753fe56b9e6SYuval Mintz void *workspace; 754fe56b9e6SYuval Mintz 755fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 756fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 757fe56b9e6SYuval Mintz 758fe56b9e6SYuval Mintz p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); 759fe56b9e6SYuval Mintz if (!p_hwfn->stream) 760fe56b9e6SYuval Mintz return -ENOMEM; 761fe56b9e6SYuval Mintz 762fe56b9e6SYuval Mintz workspace = vzalloc(zlib_inflate_workspacesize()); 763fe56b9e6SYuval Mintz if (!workspace) 764fe56b9e6SYuval Mintz return -ENOMEM; 765fe56b9e6SYuval Mintz p_hwfn->stream->workspace = workspace; 766fe56b9e6SYuval Mintz } 767fe56b9e6SYuval Mintz 768fe56b9e6SYuval Mintz return 0; 769fe56b9e6SYuval Mintz } 770fe56b9e6SYuval Mintz 771fe56b9e6SYuval Mintz static void qed_free_stream_mem(struct qed_dev *cdev) 772fe56b9e6SYuval Mintz { 773fe56b9e6SYuval Mintz int i; 774fe56b9e6SYuval Mintz 775fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 776fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 777fe56b9e6SYuval Mintz 778fe56b9e6SYuval Mintz if (!p_hwfn->stream) 779fe56b9e6SYuval Mintz return; 780fe56b9e6SYuval Mintz 781fe56b9e6SYuval Mintz vfree(p_hwfn->stream->workspace); 782fe56b9e6SYuval Mintz kfree(p_hwfn->stream); 783fe56b9e6SYuval Mintz } 784fe56b9e6SYuval Mintz } 785fe56b9e6SYuval Mintz 786fe56b9e6SYuval Mintz static void qed_update_pf_params(struct qed_dev *cdev, 787fe56b9e6SYuval Mintz struct qed_pf_params *params) 788fe56b9e6SYuval Mintz { 789fe56b9e6SYuval Mintz int i; 790fe56b9e6SYuval Mintz 791fe56b9e6SYuval Mintz for (i = 0; i < cdev->num_hwfns; i++) { 792fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 793fe56b9e6SYuval Mintz 794fe56b9e6SYuval Mintz p_hwfn->pf_params = *params; 795fe56b9e6SYuval Mintz } 796fe56b9e6SYuval Mintz } 797fe56b9e6SYuval Mintz 798fe56b9e6SYuval Mintz static int qed_slowpath_start(struct qed_dev *cdev, 799fe56b9e6SYuval Mintz struct qed_slowpath_params *params) 800fe56b9e6SYuval Mintz { 801b18e170cSManish Chopra struct qed_tunn_start_params tunn_info; 802fe56b9e6SYuval Mintz struct qed_mcp_drv_version drv_version; 803fe56b9e6SYuval Mintz const u8 *data = NULL; 804fe56b9e6SYuval Mintz struct qed_hwfn *hwfn; 80537bff2b9SYuval Mintz int rc = -EINVAL; 80637bff2b9SYuval Mintz 80737bff2b9SYuval Mintz if (qed_iov_wq_start(cdev)) 80837bff2b9SYuval Mintz goto err; 809fe56b9e6SYuval Mintz 8101408cc1fSYuval Mintz if (IS_PF(cdev)) { 811fe56b9e6SYuval Mintz rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, 812fe56b9e6SYuval Mintz &cdev->pdev->dev); 813fe56b9e6SYuval Mintz if (rc) { 814fe56b9e6SYuval Mintz DP_NOTICE(cdev, 815fe56b9e6SYuval Mintz "Failed to find fw file - /lib/firmware/%s\n", 816fe56b9e6SYuval Mintz QED_FW_FILE_NAME); 817fe56b9e6SYuval Mintz goto err; 818fe56b9e6SYuval Mintz } 8191408cc1fSYuval Mintz } 820fe56b9e6SYuval Mintz 821fe56b9e6SYuval Mintz rc = qed_nic_setup(cdev); 822fe56b9e6SYuval Mintz if (rc) 823fe56b9e6SYuval Mintz goto err; 824fe56b9e6SYuval Mintz 8251408cc1fSYuval Mintz if (IS_PF(cdev)) 826fe56b9e6SYuval Mintz rc = qed_slowpath_setup_int(cdev, params->int_mode); 8271408cc1fSYuval Mintz else 8281408cc1fSYuval Mintz rc = qed_slowpath_vf_setup_int(cdev); 829fe56b9e6SYuval Mintz if (rc) 830fe56b9e6SYuval Mintz goto err1; 831fe56b9e6SYuval Mintz 8321408cc1fSYuval Mintz if (IS_PF(cdev)) { 833fe56b9e6SYuval Mintz /* Allocate stream for unzipping */ 834fe56b9e6SYuval Mintz rc = qed_alloc_stream_mem(cdev); 835fe56b9e6SYuval Mintz if (rc) { 836fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed to allocate stream memory\n"); 8378f16bc97SSudarsana Kalluru goto err2; 838fe56b9e6SYuval Mintz } 839fe56b9e6SYuval Mintz 840351a4dedSYuval Mintz /* First Dword used to diffrentiate between various sources */ 841351a4dedSYuval Mintz data = cdev->firmware->data + sizeof(u32); 8421408cc1fSYuval Mintz } 843fe56b9e6SYuval Mintz 844b18e170cSManish Chopra memset(&tunn_info, 0, sizeof(tunn_info)); 8459a109dd0SManish Chopra tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN | 846f7985869SManish Chopra 1 << QED_MODE_L2GRE_TUNN | 847f7985869SManish Chopra 1 << QED_MODE_IPGRE_TUNN | 8489a109dd0SManish Chopra 1 << QED_MODE_L2GENEVE_TUNN | 8499a109dd0SManish Chopra 1 << QED_MODE_IPGENEVE_TUNN; 8509a109dd0SManish Chopra 851b18e170cSManish Chopra tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN; 852f7985869SManish Chopra tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN; 853f7985869SManish Chopra tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN; 854b18e170cSManish Chopra 8551408cc1fSYuval Mintz /* Start the slowpath */ 856b18e170cSManish Chopra rc = qed_hw_init(cdev, &tunn_info, true, 857b18e170cSManish Chopra cdev->int_params.out.int_mode, 858fe56b9e6SYuval Mintz true, data); 859fe56b9e6SYuval Mintz if (rc) 8608c925c44SYuval Mintz goto err2; 861fe56b9e6SYuval Mintz 862fe56b9e6SYuval Mintz DP_INFO(cdev, 863fe56b9e6SYuval Mintz "HW initialization and function start completed successfully\n"); 864fe56b9e6SYuval Mintz 8651408cc1fSYuval Mintz if (IS_PF(cdev)) { 866fe56b9e6SYuval Mintz hwfn = QED_LEADING_HWFN(cdev); 867fe56b9e6SYuval Mintz drv_version.version = (params->drv_major << 24) | 868fe56b9e6SYuval Mintz (params->drv_minor << 16) | 869fe56b9e6SYuval Mintz (params->drv_rev << 8) | 870fe56b9e6SYuval Mintz (params->drv_eng); 871fe56b9e6SYuval Mintz strlcpy(drv_version.name, params->name, 872fe56b9e6SYuval Mintz MCP_DRV_VER_STR_SIZE - 4); 873fe56b9e6SYuval Mintz rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 874fe56b9e6SYuval Mintz &drv_version); 875fe56b9e6SYuval Mintz if (rc) { 876fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed sending drv version command\n"); 877fe56b9e6SYuval Mintz return rc; 878fe56b9e6SYuval Mintz } 8791408cc1fSYuval Mintz } 880fe56b9e6SYuval Mintz 8818c925c44SYuval Mintz qed_reset_vport_stats(cdev); 8828c925c44SYuval Mintz 883fe56b9e6SYuval Mintz return 0; 884fe56b9e6SYuval Mintz 885fe56b9e6SYuval Mintz err2: 8868c925c44SYuval Mintz qed_hw_timers_stop_all(cdev); 8871408cc1fSYuval Mintz if (IS_PF(cdev)) 8888c925c44SYuval Mintz qed_slowpath_irq_free(cdev); 8898c925c44SYuval Mintz qed_free_stream_mem(cdev); 890fe56b9e6SYuval Mintz qed_disable_msix(cdev); 891fe56b9e6SYuval Mintz err1: 892fe56b9e6SYuval Mintz qed_resc_free(cdev); 893fe56b9e6SYuval Mintz err: 8941408cc1fSYuval Mintz if (IS_PF(cdev)) 895fe56b9e6SYuval Mintz release_firmware(cdev->firmware); 896fe56b9e6SYuval Mintz 89737bff2b9SYuval Mintz qed_iov_wq_stop(cdev, false); 89837bff2b9SYuval Mintz 899fe56b9e6SYuval Mintz return rc; 900fe56b9e6SYuval Mintz } 901fe56b9e6SYuval Mintz 902fe56b9e6SYuval Mintz static int qed_slowpath_stop(struct qed_dev *cdev) 903fe56b9e6SYuval Mintz { 904fe56b9e6SYuval Mintz if (!cdev) 905fe56b9e6SYuval Mintz return -ENODEV; 906fe56b9e6SYuval Mintz 9071408cc1fSYuval Mintz if (IS_PF(cdev)) { 908fe56b9e6SYuval Mintz qed_free_stream_mem(cdev); 909c5ac9319SYuval Mintz if (IS_QED_ETH_IF(cdev)) 9100b55e27dSYuval Mintz qed_sriov_disable(cdev, true); 911fe56b9e6SYuval Mintz 912fe56b9e6SYuval Mintz qed_nic_stop(cdev); 913fe56b9e6SYuval Mintz qed_slowpath_irq_free(cdev); 9141408cc1fSYuval Mintz } 915fe56b9e6SYuval Mintz 916fe56b9e6SYuval Mintz qed_disable_msix(cdev); 917fe56b9e6SYuval Mintz qed_nic_reset(cdev); 918fe56b9e6SYuval Mintz 91937bff2b9SYuval Mintz qed_iov_wq_stop(cdev, true); 92037bff2b9SYuval Mintz 9211408cc1fSYuval Mintz if (IS_PF(cdev)) 922fe56b9e6SYuval Mintz release_firmware(cdev->firmware); 923fe56b9e6SYuval Mintz 924fe56b9e6SYuval Mintz return 0; 925fe56b9e6SYuval Mintz } 926fe56b9e6SYuval Mintz 927fe56b9e6SYuval Mintz static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE], 928fe56b9e6SYuval Mintz char ver_str[VER_SIZE]) 929fe56b9e6SYuval Mintz { 930fe56b9e6SYuval Mintz int i; 931fe56b9e6SYuval Mintz 932fe56b9e6SYuval Mintz memcpy(cdev->name, name, NAME_SIZE); 933fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) 934fe56b9e6SYuval Mintz snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 935fe56b9e6SYuval Mintz 936fe56b9e6SYuval Mintz memcpy(cdev->ver_str, ver_str, VER_SIZE); 937fe56b9e6SYuval Mintz cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; 938fe56b9e6SYuval Mintz } 939fe56b9e6SYuval Mintz 940fe56b9e6SYuval Mintz static u32 qed_sb_init(struct qed_dev *cdev, 941fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 942fe56b9e6SYuval Mintz void *sb_virt_addr, 943fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, u16 sb_id, 944fe56b9e6SYuval Mintz enum qed_sb_type type) 945fe56b9e6SYuval Mintz { 946fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn; 947fe56b9e6SYuval Mintz int hwfn_index; 948fe56b9e6SYuval Mintz u16 rel_sb_id; 949fe56b9e6SYuval Mintz u8 n_hwfns; 950fe56b9e6SYuval Mintz u32 rc; 951fe56b9e6SYuval Mintz 952fe56b9e6SYuval Mintz /* RoCE uses single engine and CMT uses two engines. When using both 953fe56b9e6SYuval Mintz * we force only a single engine. Storage uses only engine 0 too. 954fe56b9e6SYuval Mintz */ 955fe56b9e6SYuval Mintz if (type == QED_SB_TYPE_L2_QUEUE) 956fe56b9e6SYuval Mintz n_hwfns = cdev->num_hwfns; 957fe56b9e6SYuval Mintz else 958fe56b9e6SYuval Mintz n_hwfns = 1; 959fe56b9e6SYuval Mintz 960fe56b9e6SYuval Mintz hwfn_index = sb_id % n_hwfns; 961fe56b9e6SYuval Mintz p_hwfn = &cdev->hwfns[hwfn_index]; 962fe56b9e6SYuval Mintz rel_sb_id = sb_id / n_hwfns; 963fe56b9e6SYuval Mintz 964fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_INTR, 965fe56b9e6SYuval Mintz "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 966fe56b9e6SYuval Mintz hwfn_index, rel_sb_id, sb_id); 967fe56b9e6SYuval Mintz 968fe56b9e6SYuval Mintz rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 969fe56b9e6SYuval Mintz sb_virt_addr, sb_phy_addr, rel_sb_id); 970fe56b9e6SYuval Mintz 971fe56b9e6SYuval Mintz return rc; 972fe56b9e6SYuval Mintz } 973fe56b9e6SYuval Mintz 974fe56b9e6SYuval Mintz static u32 qed_sb_release(struct qed_dev *cdev, 9751a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 976fe56b9e6SYuval Mintz { 977fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn; 978fe56b9e6SYuval Mintz int hwfn_index; 979fe56b9e6SYuval Mintz u16 rel_sb_id; 980fe56b9e6SYuval Mintz u32 rc; 981fe56b9e6SYuval Mintz 982fe56b9e6SYuval Mintz hwfn_index = sb_id % cdev->num_hwfns; 983fe56b9e6SYuval Mintz p_hwfn = &cdev->hwfns[hwfn_index]; 984fe56b9e6SYuval Mintz rel_sb_id = sb_id / cdev->num_hwfns; 985fe56b9e6SYuval Mintz 986fe56b9e6SYuval Mintz DP_VERBOSE(cdev, NETIF_MSG_INTR, 987fe56b9e6SYuval Mintz "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 988fe56b9e6SYuval Mintz hwfn_index, rel_sb_id, sb_id); 989fe56b9e6SYuval Mintz 990fe56b9e6SYuval Mintz rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); 991fe56b9e6SYuval Mintz 992fe56b9e6SYuval Mintz return rc; 993fe56b9e6SYuval Mintz } 994fe56b9e6SYuval Mintz 995fe7cd2bfSYuval Mintz static bool qed_can_link_change(struct qed_dev *cdev) 996fe7cd2bfSYuval Mintz { 997fe7cd2bfSYuval Mintz return true; 998fe7cd2bfSYuval Mintz } 999fe7cd2bfSYuval Mintz 1000351a4dedSYuval Mintz static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) 1001cc875c2eSYuval Mintz { 1002cc875c2eSYuval Mintz struct qed_hwfn *hwfn; 1003cc875c2eSYuval Mintz struct qed_mcp_link_params *link_params; 1004cc875c2eSYuval Mintz struct qed_ptt *ptt; 1005cc875c2eSYuval Mintz int rc; 1006cc875c2eSYuval Mintz 1007cc875c2eSYuval Mintz if (!cdev) 1008cc875c2eSYuval Mintz return -ENODEV; 1009cc875c2eSYuval Mintz 10101408cc1fSYuval Mintz if (IS_VF(cdev)) 10111408cc1fSYuval Mintz return 0; 10121408cc1fSYuval Mintz 1013cc875c2eSYuval Mintz /* The link should be set only once per PF */ 1014cc875c2eSYuval Mintz hwfn = &cdev->hwfns[0]; 1015cc875c2eSYuval Mintz 1016cc875c2eSYuval Mintz ptt = qed_ptt_acquire(hwfn); 1017cc875c2eSYuval Mintz if (!ptt) 1018cc875c2eSYuval Mintz return -EBUSY; 1019cc875c2eSYuval Mintz 1020cc875c2eSYuval Mintz link_params = qed_mcp_get_link_params(hwfn); 1021cc875c2eSYuval Mintz if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 1022cc875c2eSYuval Mintz link_params->speed.autoneg = params->autoneg; 1023cc875c2eSYuval Mintz if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { 1024cc875c2eSYuval Mintz link_params->speed.advertised_speeds = 0; 1025054c67d1SSudarsana Reddy Kalluru if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) || 1026054c67d1SSudarsana Reddy Kalluru (params->adv_speeds & QED_LM_1000baseT_Full_BIT)) 1027cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1028cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; 1029054c67d1SSudarsana Reddy Kalluru if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) 1030cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1031cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; 1032054c67d1SSudarsana Reddy Kalluru if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) 1033054c67d1SSudarsana Reddy Kalluru link_params->speed.advertised_speeds |= 1034054c67d1SSudarsana Reddy Kalluru NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; 1035054c67d1SSudarsana Reddy Kalluru if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) 1036cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1037cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; 1038054c67d1SSudarsana Reddy Kalluru if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) 1039cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1040cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; 1041054c67d1SSudarsana Reddy Kalluru if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) 1042cc875c2eSYuval Mintz link_params->speed.advertised_speeds |= 1043351a4dedSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; 1044cc875c2eSYuval Mintz } 1045cc875c2eSYuval Mintz if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) 1046cc875c2eSYuval Mintz link_params->speed.forced_speed = params->forced_speed; 1047a43f235fSSudarsana Reddy Kalluru if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 1048a43f235fSSudarsana Reddy Kalluru if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1049a43f235fSSudarsana Reddy Kalluru link_params->pause.autoneg = true; 1050a43f235fSSudarsana Reddy Kalluru else 1051a43f235fSSudarsana Reddy Kalluru link_params->pause.autoneg = false; 1052a43f235fSSudarsana Reddy Kalluru if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 1053a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_rx = true; 1054a43f235fSSudarsana Reddy Kalluru else 1055a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_rx = false; 1056a43f235fSSudarsana Reddy Kalluru if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 1057a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_tx = true; 1058a43f235fSSudarsana Reddy Kalluru else 1059a43f235fSSudarsana Reddy Kalluru link_params->pause.forced_tx = false; 1060a43f235fSSudarsana Reddy Kalluru } 106103dc76caSSudarsana Reddy Kalluru if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { 106203dc76caSSudarsana Reddy Kalluru switch (params->loopback_mode) { 106303dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_INT_PHY: 1064351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; 106503dc76caSSudarsana Reddy Kalluru break; 106603dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_EXT_PHY: 1067351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; 106803dc76caSSudarsana Reddy Kalluru break; 106903dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_EXT: 1070351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_EXT; 107103dc76caSSudarsana Reddy Kalluru break; 107203dc76caSSudarsana Reddy Kalluru case QED_LINK_LOOPBACK_MAC: 1073351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_MAC; 107403dc76caSSudarsana Reddy Kalluru break; 107503dc76caSSudarsana Reddy Kalluru default: 1076351a4dedSYuval Mintz link_params->loopback_mode = ETH_LOOPBACK_NONE; 107703dc76caSSudarsana Reddy Kalluru break; 107803dc76caSSudarsana Reddy Kalluru } 107903dc76caSSudarsana Reddy Kalluru } 1080cc875c2eSYuval Mintz 1081cc875c2eSYuval Mintz rc = qed_mcp_set_link(hwfn, ptt, params->link_up); 1082cc875c2eSYuval Mintz 1083cc875c2eSYuval Mintz qed_ptt_release(hwfn, ptt); 1084cc875c2eSYuval Mintz 1085cc875c2eSYuval Mintz return rc; 1086cc875c2eSYuval Mintz } 1087cc875c2eSYuval Mintz 1088cc875c2eSYuval Mintz static int qed_get_port_type(u32 media_type) 1089cc875c2eSYuval Mintz { 1090cc875c2eSYuval Mintz int port_type; 1091cc875c2eSYuval Mintz 1092cc875c2eSYuval Mintz switch (media_type) { 1093cc875c2eSYuval Mintz case MEDIA_SFPP_10G_FIBER: 1094cc875c2eSYuval Mintz case MEDIA_SFP_1G_FIBER: 1095cc875c2eSYuval Mintz case MEDIA_XFP_FIBER: 1096b639f197SYuval Mintz case MEDIA_MODULE_FIBER: 1097cc875c2eSYuval Mintz case MEDIA_KR: 1098cc875c2eSYuval Mintz port_type = PORT_FIBRE; 1099cc875c2eSYuval Mintz break; 1100cc875c2eSYuval Mintz case MEDIA_DA_TWINAX: 1101cc875c2eSYuval Mintz port_type = PORT_DA; 1102cc875c2eSYuval Mintz break; 1103cc875c2eSYuval Mintz case MEDIA_BASE_T: 1104cc875c2eSYuval Mintz port_type = PORT_TP; 1105cc875c2eSYuval Mintz break; 1106cc875c2eSYuval Mintz case MEDIA_NOT_PRESENT: 1107cc875c2eSYuval Mintz port_type = PORT_NONE; 1108cc875c2eSYuval Mintz break; 1109cc875c2eSYuval Mintz case MEDIA_UNSPECIFIED: 1110cc875c2eSYuval Mintz default: 1111cc875c2eSYuval Mintz port_type = PORT_OTHER; 1112cc875c2eSYuval Mintz break; 1113cc875c2eSYuval Mintz } 1114cc875c2eSYuval Mintz return port_type; 1115cc875c2eSYuval Mintz } 1116cc875c2eSYuval Mintz 111714b84e86SArnd Bergmann static int qed_get_link_data(struct qed_hwfn *hwfn, 111814b84e86SArnd Bergmann struct qed_mcp_link_params *params, 111914b84e86SArnd Bergmann struct qed_mcp_link_state *link, 112014b84e86SArnd Bergmann struct qed_mcp_link_capabilities *link_caps) 112114b84e86SArnd Bergmann { 112214b84e86SArnd Bergmann void *p; 112314b84e86SArnd Bergmann 112414b84e86SArnd Bergmann if (!IS_PF(hwfn->cdev)) { 112514b84e86SArnd Bergmann qed_vf_get_link_params(hwfn, params); 112614b84e86SArnd Bergmann qed_vf_get_link_state(hwfn, link); 112714b84e86SArnd Bergmann qed_vf_get_link_caps(hwfn, link_caps); 112814b84e86SArnd Bergmann 112914b84e86SArnd Bergmann return 0; 113014b84e86SArnd Bergmann } 113114b84e86SArnd Bergmann 113214b84e86SArnd Bergmann p = qed_mcp_get_link_params(hwfn); 113314b84e86SArnd Bergmann if (!p) 113414b84e86SArnd Bergmann return -ENXIO; 113514b84e86SArnd Bergmann memcpy(params, p, sizeof(*params)); 113614b84e86SArnd Bergmann 113714b84e86SArnd Bergmann p = qed_mcp_get_link_state(hwfn); 113814b84e86SArnd Bergmann if (!p) 113914b84e86SArnd Bergmann return -ENXIO; 114014b84e86SArnd Bergmann memcpy(link, p, sizeof(*link)); 114114b84e86SArnd Bergmann 114214b84e86SArnd Bergmann p = qed_mcp_get_link_capabilities(hwfn); 114314b84e86SArnd Bergmann if (!p) 114414b84e86SArnd Bergmann return -ENXIO; 114514b84e86SArnd Bergmann memcpy(link_caps, p, sizeof(*link_caps)); 114614b84e86SArnd Bergmann 114714b84e86SArnd Bergmann return 0; 114814b84e86SArnd Bergmann } 114914b84e86SArnd Bergmann 1150cc875c2eSYuval Mintz static void qed_fill_link(struct qed_hwfn *hwfn, 1151cc875c2eSYuval Mintz struct qed_link_output *if_link) 1152cc875c2eSYuval Mintz { 1153cc875c2eSYuval Mintz struct qed_mcp_link_params params; 1154cc875c2eSYuval Mintz struct qed_mcp_link_state link; 1155cc875c2eSYuval Mintz struct qed_mcp_link_capabilities link_caps; 1156cc875c2eSYuval Mintz u32 media_type; 1157cc875c2eSYuval Mintz 1158cc875c2eSYuval Mintz memset(if_link, 0, sizeof(*if_link)); 1159cc875c2eSYuval Mintz 1160cc875c2eSYuval Mintz /* Prepare source inputs */ 116114b84e86SArnd Bergmann if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) { 116214b84e86SArnd Bergmann dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n"); 116314b84e86SArnd Bergmann return; 11641408cc1fSYuval Mintz } 1165cc875c2eSYuval Mintz 1166cc875c2eSYuval Mintz /* Set the link parameters to pass to protocol driver */ 1167cc875c2eSYuval Mintz if (link.link_up) 1168cc875c2eSYuval Mintz if_link->link_up = true; 1169cc875c2eSYuval Mintz 1170cc875c2eSYuval Mintz /* TODO - at the moment assume supported and advertised speed equal */ 1171054c67d1SSudarsana Reddy Kalluru if_link->supported_caps = QED_LM_FIBRE_BIT; 1172cc875c2eSYuval Mintz if (params.speed.autoneg) 1173054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_Autoneg_BIT; 1174cc875c2eSYuval Mintz if (params.pause.autoneg || 1175cc875c2eSYuval Mintz (params.pause.forced_rx && params.pause.forced_tx)) 1176054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_Asym_Pause_BIT; 1177cc875c2eSYuval Mintz if (params.pause.autoneg || params.pause.forced_rx || 1178cc875c2eSYuval Mintz params.pause.forced_tx) 1179054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_Pause_BIT; 1180cc875c2eSYuval Mintz 1181cc875c2eSYuval Mintz if_link->advertised_caps = if_link->supported_caps; 1182cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1183cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1184054c67d1SSudarsana Reddy Kalluru if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT | 1185054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Full_BIT; 1186cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1187cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1188054c67d1SSudarsana Reddy Kalluru if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT; 1189054c67d1SSudarsana Reddy Kalluru if (params.speed.advertised_speeds & 1190054c67d1SSudarsana Reddy Kalluru NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1191054c67d1SSudarsana Reddy Kalluru if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT; 1192cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1193cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1194054c67d1SSudarsana Reddy Kalluru if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT; 1195cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1196cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1197054c67d1SSudarsana Reddy Kalluru if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT; 1198cc875c2eSYuval Mintz if (params.speed.advertised_speeds & 1199351a4dedSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1200054c67d1SSudarsana Reddy Kalluru if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT; 1201cc875c2eSYuval Mintz 1202cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1203cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1204054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_1000baseT_Half_BIT | 1205054c67d1SSudarsana Reddy Kalluru QED_LM_1000baseT_Full_BIT; 1206cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1207cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1208054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT; 1209054c67d1SSudarsana Reddy Kalluru if (link_caps.speed_capabilities & 1210054c67d1SSudarsana Reddy Kalluru NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1211054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT; 1212cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1213cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1214054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT; 1215cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1216cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1217054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT; 1218cc875c2eSYuval Mintz if (link_caps.speed_capabilities & 1219351a4dedSYuval Mintz NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1220054c67d1SSudarsana Reddy Kalluru if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT; 1221cc875c2eSYuval Mintz 1222cc875c2eSYuval Mintz if (link.link_up) 1223cc875c2eSYuval Mintz if_link->speed = link.speed; 1224cc875c2eSYuval Mintz 1225cc875c2eSYuval Mintz /* TODO - fill duplex properly */ 1226cc875c2eSYuval Mintz if_link->duplex = DUPLEX_FULL; 1227cc875c2eSYuval Mintz qed_mcp_get_media_type(hwfn->cdev, &media_type); 1228cc875c2eSYuval Mintz if_link->port = qed_get_port_type(media_type); 1229cc875c2eSYuval Mintz 1230cc875c2eSYuval Mintz if_link->autoneg = params.speed.autoneg; 1231cc875c2eSYuval Mintz 1232cc875c2eSYuval Mintz if (params.pause.autoneg) 1233cc875c2eSYuval Mintz if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1234cc875c2eSYuval Mintz if (params.pause.forced_rx) 1235cc875c2eSYuval Mintz if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1236cc875c2eSYuval Mintz if (params.pause.forced_tx) 1237cc875c2eSYuval Mintz if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1238cc875c2eSYuval Mintz 1239cc875c2eSYuval Mintz /* Link partner capabilities */ 1240054c67d1SSudarsana Reddy Kalluru if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD) 1241054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_1000baseT_Half_BIT; 1242054c67d1SSudarsana Reddy Kalluru if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) 1243054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; 1244054c67d1SSudarsana Reddy Kalluru if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) 1245054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; 1246054c67d1SSudarsana Reddy Kalluru if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) 1247054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; 1248054c67d1SSudarsana Reddy Kalluru if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) 1249054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; 1250054c67d1SSudarsana Reddy Kalluru if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) 1251054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; 1252054c67d1SSudarsana Reddy Kalluru if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) 1253054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; 1254cc875c2eSYuval Mintz 1255cc875c2eSYuval Mintz if (link.an_complete) 1256054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_Autoneg_BIT; 1257cc875c2eSYuval Mintz 1258cc875c2eSYuval Mintz if (link.partner_adv_pause) 1259054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_Pause_BIT; 1260cc875c2eSYuval Mintz if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || 1261cc875c2eSYuval Mintz link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) 1262054c67d1SSudarsana Reddy Kalluru if_link->lp_caps |= QED_LM_Asym_Pause_BIT; 1263cc875c2eSYuval Mintz } 1264cc875c2eSYuval Mintz 1265cc875c2eSYuval Mintz static void qed_get_current_link(struct qed_dev *cdev, 1266cc875c2eSYuval Mintz struct qed_link_output *if_link) 1267cc875c2eSYuval Mintz { 126836558c3dSYuval Mintz int i; 126936558c3dSYuval Mintz 1270cc875c2eSYuval Mintz qed_fill_link(&cdev->hwfns[0], if_link); 127136558c3dSYuval Mintz 127236558c3dSYuval Mintz for_each_hwfn(cdev, i) 127336558c3dSYuval Mintz qed_inform_vf_link_state(&cdev->hwfns[i]); 1274cc875c2eSYuval Mintz } 1275cc875c2eSYuval Mintz 1276cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn) 1277cc875c2eSYuval Mintz { 1278cc875c2eSYuval Mintz void *cookie = hwfn->cdev->ops_cookie; 1279cc875c2eSYuval Mintz struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; 1280cc875c2eSYuval Mintz struct qed_link_output if_link; 1281cc875c2eSYuval Mintz 1282cc875c2eSYuval Mintz qed_fill_link(hwfn, &if_link); 128336558c3dSYuval Mintz qed_inform_vf_link_state(hwfn); 1284cc875c2eSYuval Mintz 1285cc875c2eSYuval Mintz if (IS_LEAD_HWFN(hwfn) && cookie) 1286cc875c2eSYuval Mintz op->link_update(cookie, &if_link); 1287cc875c2eSYuval Mintz } 1288cc875c2eSYuval Mintz 1289fe56b9e6SYuval Mintz static int qed_drain(struct qed_dev *cdev) 1290fe56b9e6SYuval Mintz { 1291fe56b9e6SYuval Mintz struct qed_hwfn *hwfn; 1292fe56b9e6SYuval Mintz struct qed_ptt *ptt; 1293fe56b9e6SYuval Mintz int i, rc; 1294fe56b9e6SYuval Mintz 12951408cc1fSYuval Mintz if (IS_VF(cdev)) 12961408cc1fSYuval Mintz return 0; 12971408cc1fSYuval Mintz 1298fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1299fe56b9e6SYuval Mintz hwfn = &cdev->hwfns[i]; 1300fe56b9e6SYuval Mintz ptt = qed_ptt_acquire(hwfn); 1301fe56b9e6SYuval Mintz if (!ptt) { 1302fe56b9e6SYuval Mintz DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); 1303fe56b9e6SYuval Mintz return -EBUSY; 1304fe56b9e6SYuval Mintz } 1305fe56b9e6SYuval Mintz rc = qed_mcp_drain(hwfn, ptt); 1306fe56b9e6SYuval Mintz if (rc) 1307fe56b9e6SYuval Mintz return rc; 1308fe56b9e6SYuval Mintz qed_ptt_release(hwfn, ptt); 1309fe56b9e6SYuval Mintz } 1310fe56b9e6SYuval Mintz 1311fe56b9e6SYuval Mintz return 0; 1312fe56b9e6SYuval Mintz } 1313fe56b9e6SYuval Mintz 1314722003acSSudarsana Reddy Kalluru static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal) 1315722003acSSudarsana Reddy Kalluru { 1316722003acSSudarsana Reddy Kalluru *rx_coal = cdev->rx_coalesce_usecs; 1317722003acSSudarsana Reddy Kalluru *tx_coal = cdev->tx_coalesce_usecs; 1318722003acSSudarsana Reddy Kalluru } 1319722003acSSudarsana Reddy Kalluru 1320722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, 1321722003acSSudarsana Reddy Kalluru u8 qid, u16 sb_id) 1322722003acSSudarsana Reddy Kalluru { 1323722003acSSudarsana Reddy Kalluru struct qed_hwfn *hwfn; 1324722003acSSudarsana Reddy Kalluru struct qed_ptt *ptt; 1325722003acSSudarsana Reddy Kalluru int hwfn_index; 1326722003acSSudarsana Reddy Kalluru int status = 0; 1327722003acSSudarsana Reddy Kalluru 1328722003acSSudarsana Reddy Kalluru hwfn_index = qid % cdev->num_hwfns; 1329722003acSSudarsana Reddy Kalluru hwfn = &cdev->hwfns[hwfn_index]; 1330722003acSSudarsana Reddy Kalluru ptt = qed_ptt_acquire(hwfn); 1331722003acSSudarsana Reddy Kalluru if (!ptt) 1332722003acSSudarsana Reddy Kalluru return -EAGAIN; 1333722003acSSudarsana Reddy Kalluru 1334722003acSSudarsana Reddy Kalluru status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal, 1335722003acSSudarsana Reddy Kalluru qid / cdev->num_hwfns, sb_id); 1336722003acSSudarsana Reddy Kalluru if (status) 1337722003acSSudarsana Reddy Kalluru goto out; 1338722003acSSudarsana Reddy Kalluru status = qed_set_txq_coalesce(hwfn, ptt, tx_coal, 1339722003acSSudarsana Reddy Kalluru qid / cdev->num_hwfns, sb_id); 1340722003acSSudarsana Reddy Kalluru out: 1341722003acSSudarsana Reddy Kalluru qed_ptt_release(hwfn, ptt); 1342722003acSSudarsana Reddy Kalluru 1343722003acSSudarsana Reddy Kalluru return status; 1344722003acSSudarsana Reddy Kalluru } 1345722003acSSudarsana Reddy Kalluru 134691420b83SSudarsana Kalluru static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) 134791420b83SSudarsana Kalluru { 134891420b83SSudarsana Kalluru struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); 134991420b83SSudarsana Kalluru struct qed_ptt *ptt; 135091420b83SSudarsana Kalluru int status = 0; 135191420b83SSudarsana Kalluru 135291420b83SSudarsana Kalluru ptt = qed_ptt_acquire(hwfn); 135391420b83SSudarsana Kalluru if (!ptt) 135491420b83SSudarsana Kalluru return -EAGAIN; 135591420b83SSudarsana Kalluru 135691420b83SSudarsana Kalluru status = qed_mcp_set_led(hwfn, ptt, mode); 135791420b83SSudarsana Kalluru 135891420b83SSudarsana Kalluru qed_ptt_release(hwfn, ptt); 135991420b83SSudarsana Kalluru 136091420b83SSudarsana Kalluru return status; 136191420b83SSudarsana Kalluru } 136291420b83SSudarsana Kalluru 136303dc76caSSudarsana Reddy Kalluru struct qed_selftest_ops qed_selftest_ops_pass = { 136403dc76caSSudarsana Reddy Kalluru .selftest_memory = &qed_selftest_memory, 136503dc76caSSudarsana Reddy Kalluru .selftest_interrupt = &qed_selftest_interrupt, 136603dc76caSSudarsana Reddy Kalluru .selftest_register = &qed_selftest_register, 136703dc76caSSudarsana Reddy Kalluru .selftest_clock = &qed_selftest_clock, 136803dc76caSSudarsana Reddy Kalluru }; 136903dc76caSSudarsana Reddy Kalluru 1370fe56b9e6SYuval Mintz const struct qed_common_ops qed_common_ops_pass = { 137103dc76caSSudarsana Reddy Kalluru .selftest = &qed_selftest_ops_pass, 1372fe56b9e6SYuval Mintz .probe = &qed_probe, 1373fe56b9e6SYuval Mintz .remove = &qed_remove, 1374fe56b9e6SYuval Mintz .set_power_state = &qed_set_power_state, 1375fe56b9e6SYuval Mintz .set_id = &qed_set_id, 1376fe56b9e6SYuval Mintz .update_pf_params = &qed_update_pf_params, 1377fe56b9e6SYuval Mintz .slowpath_start = &qed_slowpath_start, 1378fe56b9e6SYuval Mintz .slowpath_stop = &qed_slowpath_stop, 1379fe56b9e6SYuval Mintz .set_fp_int = &qed_set_int_fp, 1380fe56b9e6SYuval Mintz .get_fp_int = &qed_get_int_fp, 1381fe56b9e6SYuval Mintz .sb_init = &qed_sb_init, 1382fe56b9e6SYuval Mintz .sb_release = &qed_sb_release, 1383fe56b9e6SYuval Mintz .simd_handler_config = &qed_simd_handler_config, 1384fe56b9e6SYuval Mintz .simd_handler_clean = &qed_simd_handler_clean, 1385fe7cd2bfSYuval Mintz .can_link_change = &qed_can_link_change, 1386cc875c2eSYuval Mintz .set_link = &qed_set_link, 1387cc875c2eSYuval Mintz .get_link = &qed_get_current_link, 1388fe56b9e6SYuval Mintz .drain = &qed_drain, 1389fe56b9e6SYuval Mintz .update_msglvl = &qed_init_dp, 1390fe56b9e6SYuval Mintz .chain_alloc = &qed_chain_alloc, 1391fe56b9e6SYuval Mintz .chain_free = &qed_chain_free, 1392722003acSSudarsana Reddy Kalluru .get_coalesce = &qed_get_coalesce, 1393722003acSSudarsana Reddy Kalluru .set_coalesce = &qed_set_coalesce, 139491420b83SSudarsana Kalluru .set_led = &qed_set_led, 1395fe56b9e6SYuval Mintz }; 1396