11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2dacd88d6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5dacd88d6SYuval Mintz */ 61f4d4ed6SAlexander Lobakin 7dacd88d6SYuval Mintz #ifndef _QED_L2_H 8dacd88d6SYuval Mintz #define _QED_L2_H 9dacd88d6SYuval Mintz #include <linux/types.h> 10dacd88d6SYuval Mintz #include <linux/io.h> 11dacd88d6SYuval Mintz #include <linux/kernel.h> 12dacd88d6SYuval Mintz #include <linux/slab.h> 13dacd88d6SYuval Mintz #include <linux/qed/qed_eth_if.h> 14dacd88d6SYuval Mintz #include "qed.h" 15dacd88d6SYuval Mintz #include "qed_hw.h" 16dacd88d6SYuval Mintz #include "qed_sp.h" 17f29ffdb6SMintz, Yuval struct qed_rss_params { 18f29ffdb6SMintz, Yuval u8 update_rss_config; 19f29ffdb6SMintz, Yuval u8 rss_enable; 20f29ffdb6SMintz, Yuval u8 rss_eng_id; 21f29ffdb6SMintz, Yuval u8 update_rss_capabilities; 22f29ffdb6SMintz, Yuval u8 update_rss_ind_table; 23f29ffdb6SMintz, Yuval u8 update_rss_key; 24f29ffdb6SMintz, Yuval u8 rss_caps; 25f29ffdb6SMintz, Yuval u8 rss_table_size_log; 26f29ffdb6SMintz, Yuval 27f29ffdb6SMintz, Yuval /* Indirection table consist of rx queue handles */ 28f29ffdb6SMintz, Yuval void *rss_ind_table[QED_RSS_IND_TABLE_SIZE]; 29f29ffdb6SMintz, Yuval u32 rss_key[QED_RSS_KEY_SIZE]; 30f29ffdb6SMintz, Yuval }; 31dacd88d6SYuval Mintz 3217b235c1SYuval Mintz struct qed_sge_tpa_params { 3317b235c1SYuval Mintz u8 max_buffers_per_cqe; 3417b235c1SYuval Mintz 3517b235c1SYuval Mintz u8 update_tpa_en_flg; 3617b235c1SYuval Mintz u8 tpa_ipv4_en_flg; 3717b235c1SYuval Mintz u8 tpa_ipv6_en_flg; 3817b235c1SYuval Mintz u8 tpa_ipv4_tunn_en_flg; 3917b235c1SYuval Mintz u8 tpa_ipv6_tunn_en_flg; 4017b235c1SYuval Mintz 4117b235c1SYuval Mintz u8 update_tpa_param_flg; 4217b235c1SYuval Mintz u8 tpa_pkt_split_flg; 4317b235c1SYuval Mintz u8 tpa_hdr_data_split_flg; 4417b235c1SYuval Mintz u8 tpa_gro_consistent_flg; 4517b235c1SYuval Mintz u8 tpa_max_aggs_num; 4617b235c1SYuval Mintz u16 tpa_max_size; 4717b235c1SYuval Mintz u16 tpa_min_size_to_start; 4817b235c1SYuval Mintz u16 tpa_min_size_to_cont; 4917b235c1SYuval Mintz }; 5017b235c1SYuval Mintz 51dacd88d6SYuval Mintz enum qed_filter_opcode { 52dacd88d6SYuval Mintz QED_FILTER_ADD, 53dacd88d6SYuval Mintz QED_FILTER_REMOVE, 54dacd88d6SYuval Mintz QED_FILTER_MOVE, 55dacd88d6SYuval Mintz QED_FILTER_REPLACE, /* Delete all MACs and add new one instead */ 56dacd88d6SYuval Mintz QED_FILTER_FLUSH, /* Removes all filters */ 57dacd88d6SYuval Mintz }; 58dacd88d6SYuval Mintz 59dacd88d6SYuval Mintz enum qed_filter_ucast_type { 60dacd88d6SYuval Mintz QED_FILTER_MAC, 61dacd88d6SYuval Mintz QED_FILTER_VLAN, 62dacd88d6SYuval Mintz QED_FILTER_MAC_VLAN, 63dacd88d6SYuval Mintz QED_FILTER_INNER_MAC, 64dacd88d6SYuval Mintz QED_FILTER_INNER_VLAN, 65dacd88d6SYuval Mintz QED_FILTER_INNER_PAIR, 66dacd88d6SYuval Mintz QED_FILTER_INNER_MAC_VNI_PAIR, 67dacd88d6SYuval Mintz QED_FILTER_MAC_VNI_PAIR, 68dacd88d6SYuval Mintz QED_FILTER_VNI, 69dacd88d6SYuval Mintz }; 70dacd88d6SYuval Mintz 71dacd88d6SYuval Mintz struct qed_filter_ucast { 72dacd88d6SYuval Mintz enum qed_filter_opcode opcode; 73dacd88d6SYuval Mintz enum qed_filter_ucast_type type; 74dacd88d6SYuval Mintz u8 is_rx_filter; 75dacd88d6SYuval Mintz u8 is_tx_filter; 76dacd88d6SYuval Mintz u8 vport_to_add_to; 77dacd88d6SYuval Mintz u8 vport_to_remove_from; 78dacd88d6SYuval Mintz unsigned char mac[ETH_ALEN]; 79dacd88d6SYuval Mintz u8 assert_on_error; 80dacd88d6SYuval Mintz u16 vlan; 81dacd88d6SYuval Mintz u32 vni; 82dacd88d6SYuval Mintz }; 83dacd88d6SYuval Mintz 84dacd88d6SYuval Mintz struct qed_filter_mcast { 85dacd88d6SYuval Mintz /* MOVE is not supported for multicast */ 86dacd88d6SYuval Mintz enum qed_filter_opcode opcode; 87dacd88d6SYuval Mintz u8 vport_to_add_to; 88dacd88d6SYuval Mintz u8 vport_to_remove_from; 89dacd88d6SYuval Mintz u8 num_mc_addrs; 90dacd88d6SYuval Mintz #define QED_MAX_MC_ADDRS 64 91dacd88d6SYuval Mintz unsigned char mac[QED_MAX_MC_ADDRS][ETH_ALEN]; 92dacd88d6SYuval Mintz }; 93dacd88d6SYuval Mintz 943da7a37aSMintz, Yuval /** 9519198e4eSPrabhakar Kushwaha * qed_eth_rx_queue_stop(): This ramrod closes an Rx queue. 963da7a37aSMintz, Yuval * 9719198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 9819198e4eSPrabhakar Kushwaha * @p_rxq: Handler of queue to close 9919198e4eSPrabhakar Kushwaha * @eq_completion_only: If True completion will be on 1003da7a37aSMintz, Yuval * EQe, if False completion will be 1013da7a37aSMintz, Yuval * on EQe if p_hwfn opaque 1023da7a37aSMintz, Yuval * different from the RXQ opaque 1033da7a37aSMintz, Yuval * otherwise on CQe. 10419198e4eSPrabhakar Kushwaha * @cqe_completion: If True completion will be receive on CQe. 10519198e4eSPrabhakar Kushwaha * 10619198e4eSPrabhakar Kushwaha * Return: Int. 1073da7a37aSMintz, Yuval */ 1083da7a37aSMintz, Yuval int 1093da7a37aSMintz, Yuval qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 1103da7a37aSMintz, Yuval void *p_rxq, 111dacd88d6SYuval Mintz bool eq_completion_only, bool cqe_completion); 112dacd88d6SYuval Mintz 1133da7a37aSMintz, Yuval /** 11419198e4eSPrabhakar Kushwaha * qed_eth_tx_queue_stop(): Closes a Tx queue. 1153da7a37aSMintz, Yuval * 11619198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 11719198e4eSPrabhakar Kushwaha * @p_txq: handle to Tx queue needed to be closed. 1183da7a37aSMintz, Yuval * 11919198e4eSPrabhakar Kushwaha * Return: Int. 1203da7a37aSMintz, Yuval */ 1213da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_txq); 122dacd88d6SYuval Mintz 123dacd88d6SYuval Mintz enum qed_tpa_mode { 124dacd88d6SYuval Mintz QED_TPA_MODE_NONE, 125dacd88d6SYuval Mintz QED_TPA_MODE_UNUSED, 126dacd88d6SYuval Mintz QED_TPA_MODE_GRO, 127dacd88d6SYuval Mintz QED_TPA_MODE_MAX 128dacd88d6SYuval Mintz }; 129dacd88d6SYuval Mintz 130dacd88d6SYuval Mintz struct qed_sp_vport_start_params { 131dacd88d6SYuval Mintz enum qed_tpa_mode tpa_mode; 132dacd88d6SYuval Mintz bool remove_inner_vlan; 133831bfb0eSYuval Mintz bool tx_switching; 134c78c70faSSudarsana Reddy Kalluru bool handle_ptp_pkts; 13508feecd7SYuval Mintz bool only_untagged; 136dacd88d6SYuval Mintz bool drop_ttl0; 137dacd88d6SYuval Mintz u8 max_buffers_per_cqe; 138dacd88d6SYuval Mintz u32 concrete_fid; 139dacd88d6SYuval Mintz u16 opaque_fid; 140dacd88d6SYuval Mintz u8 vport_id; 141dacd88d6SYuval Mintz u16 mtu; 14211a85d75SYuval Mintz bool check_mac; 14311a85d75SYuval Mintz bool check_ethtype; 144dacd88d6SYuval Mintz }; 145dacd88d6SYuval Mintz 146dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 147dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params); 148dacd88d6SYuval Mintz 149dacd88d6SYuval Mintz struct qed_filter_accept_flags { 150dacd88d6SYuval Mintz u8 update_rx_mode_config; 151dacd88d6SYuval Mintz u8 update_tx_mode_config; 152dacd88d6SYuval Mintz u8 rx_accept_filter; 153dacd88d6SYuval Mintz u8 tx_accept_filter; 154dacd88d6SYuval Mintz #define QED_ACCEPT_NONE 0x01 155dacd88d6SYuval Mintz #define QED_ACCEPT_UCAST_MATCHED 0x02 156dacd88d6SYuval Mintz #define QED_ACCEPT_UCAST_UNMATCHED 0x04 157dacd88d6SYuval Mintz #define QED_ACCEPT_MCAST_MATCHED 0x08 158dacd88d6SYuval Mintz #define QED_ACCEPT_MCAST_UNMATCHED 0x10 159dacd88d6SYuval Mintz #define QED_ACCEPT_BCAST 0x20 160d52c89f1SMichal Kalderon #define QED_ACCEPT_ANY_VNI 0x40 161dacd88d6SYuval Mintz }; 162dacd88d6SYuval Mintz 163d51e4af5SChopra, Manish struct qed_arfs_config_params { 164d51e4af5SChopra, Manish bool tcp; 165d51e4af5SChopra, Manish bool udp; 166d51e4af5SChopra, Manish bool ipv4; 167d51e4af5SChopra, Manish bool ipv6; 168da090917STomer Tayar enum qed_filter_config_mode mode; 169d51e4af5SChopra, Manish }; 170d51e4af5SChopra, Manish 171dacd88d6SYuval Mintz struct qed_sp_vport_update_params { 172dacd88d6SYuval Mintz u16 opaque_fid; 173dacd88d6SYuval Mintz u8 vport_id; 174dacd88d6SYuval Mintz u8 update_vport_active_rx_flg; 175dacd88d6SYuval Mintz u8 vport_active_rx_flg; 176dacd88d6SYuval Mintz u8 update_vport_active_tx_flg; 177dacd88d6SYuval Mintz u8 vport_active_tx_flg; 17817b235c1SYuval Mintz u8 update_inner_vlan_removal_flg; 17917b235c1SYuval Mintz u8 inner_vlan_removal_flg; 18008feecd7SYuval Mintz u8 silent_vlan_removal_flg; 18108feecd7SYuval Mintz u8 update_default_vlan_enable_flg; 18208feecd7SYuval Mintz u8 default_vlan_enable_flg; 18308feecd7SYuval Mintz u8 update_default_vlan_flg; 18408feecd7SYuval Mintz u16 default_vlan; 18517b235c1SYuval Mintz u8 update_tx_switching_flg; 18617b235c1SYuval Mintz u8 tx_switching_flg; 187dacd88d6SYuval Mintz u8 update_approx_mcast_flg; 1886ddc7608SYuval Mintz u8 update_anti_spoofing_en_flg; 1896ddc7608SYuval Mintz u8 anti_spoofing_en; 190dacd88d6SYuval Mintz u8 update_accept_any_vlan_flg; 191dacd88d6SYuval Mintz u8 accept_any_vlan; 19225c020a9SSudarsana Reddy Kalluru u32 bins[8]; 193dacd88d6SYuval Mintz struct qed_rss_params *rss_params; 194dacd88d6SYuval Mintz struct qed_filter_accept_flags accept_flags; 19517b235c1SYuval Mintz struct qed_sge_tpa_params *sge_tpa_params; 196ff929696SManish Chopra u8 update_ctl_frame_check; 197ff929696SManish Chopra u8 mac_chk_en; 198ff929696SManish Chopra u8 ethtype_chk_en; 199dacd88d6SYuval Mintz }; 200dacd88d6SYuval Mintz 201dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 202dacd88d6SYuval Mintz struct qed_sp_vport_update_params *p_params, 203dacd88d6SYuval Mintz enum spq_mode comp_mode, 204dacd88d6SYuval Mintz struct qed_spq_comp_cb *p_comp_data); 205dacd88d6SYuval Mintz 206dacd88d6SYuval Mintz /** 20719198e4eSPrabhakar Kushwaha * qed_sp_vport_stop: This ramrod closes a VPort after all its 20819198e4eSPrabhakar Kushwaha * RX and TX queues are terminated. 209dacd88d6SYuval Mintz * An Assert is generated if any queues are left open. 210dacd88d6SYuval Mintz * 21119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 21219198e4eSPrabhakar Kushwaha * @opaque_fid: Opaque FID 21319198e4eSPrabhakar Kushwaha * @vport_id: VPort ID. 214dacd88d6SYuval Mintz * 21519198e4eSPrabhakar Kushwaha * Return: Int. 216dacd88d6SYuval Mintz */ 217dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id); 218dacd88d6SYuval Mintz 219dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 220dacd88d6SYuval Mintz u16 opaque_fid, 221dacd88d6SYuval Mintz struct qed_filter_ucast *p_filter_cmd, 222dacd88d6SYuval Mintz enum spq_mode comp_mode, 223dacd88d6SYuval Mintz struct qed_spq_comp_cb *p_comp_data); 224dacd88d6SYuval Mintz 22517b235c1SYuval Mintz /** 22619198e4eSPrabhakar Kushwaha * qed_sp_eth_rx_queues_update(): This ramrod updates an RX queue. 22719198e4eSPrabhakar Kushwaha * It is used for setting the active state 22819198e4eSPrabhakar Kushwaha * of the queue and updating the TPA and 22919198e4eSPrabhakar Kushwaha * SGE parameters. 23019198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 23119198e4eSPrabhakar Kushwaha * @pp_rxq_handlers: An array of queue handlers to be updated. 23219198e4eSPrabhakar Kushwaha * @num_rxqs: number of queues to update. 23319198e4eSPrabhakar Kushwaha * @complete_cqe_flg: Post completion to the CQE Ring if set. 23419198e4eSPrabhakar Kushwaha * @complete_event_flg: Post completion to the Event Ring if set. 23519198e4eSPrabhakar Kushwaha * @comp_mode: Comp mode. 23619198e4eSPrabhakar Kushwaha * @p_comp_data: Pointer Comp data. 23717b235c1SYuval Mintz * 23819198e4eSPrabhakar Kushwaha * Return: Int. 23917b235c1SYuval Mintz * 24019198e4eSPrabhakar Kushwaha * Note At the moment - only used by non-linux VFs. 24117b235c1SYuval Mintz */ 24217b235c1SYuval Mintz 24317b235c1SYuval Mintz int 24417b235c1SYuval Mintz qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 2453da7a37aSMintz, Yuval void **pp_rxq_handlers, 24617b235c1SYuval Mintz u8 num_rxqs, 24717b235c1SYuval Mintz u8 complete_cqe_flg, 24817b235c1SYuval Mintz u8 complete_event_flg, 24917b235c1SYuval Mintz enum spq_mode comp_mode, 25017b235c1SYuval Mintz struct qed_spq_comp_cb *p_comp_data); 25117b235c1SYuval Mintz 252*e346e231SKonstantin Khorenko /** 253*e346e231SKonstantin Khorenko * qed_get_vport_stats(): Fills provided statistics 254*e346e231SKonstantin Khorenko * struct with statistics. 255*e346e231SKonstantin Khorenko * 256*e346e231SKonstantin Khorenko * @cdev: Qed dev pointer. 257*e346e231SKonstantin Khorenko * @stats: Points to struct that will be filled with statistics. 258*e346e231SKonstantin Khorenko * 259*e346e231SKonstantin Khorenko * Return: Void. 260*e346e231SKonstantin Khorenko */ 2616c754246SSudarsana Reddy Kalluru void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats); 2626c754246SSudarsana Reddy Kalluru 263*e346e231SKonstantin Khorenko /** 264*e346e231SKonstantin Khorenko * qed_get_vport_stats_context(): Fills provided statistics 265*e346e231SKonstantin Khorenko * struct with statistics. 266*e346e231SKonstantin Khorenko * 267*e346e231SKonstantin Khorenko * @cdev: Qed dev pointer. 268*e346e231SKonstantin Khorenko * @stats: Points to struct that will be filled with statistics. 269*e346e231SKonstantin Khorenko * @is_atomic: Hint from the caller - if the func can sleep or not. 270*e346e231SKonstantin Khorenko * 271*e346e231SKonstantin Khorenko * Context: The function should not sleep in case is_atomic == true. 272*e346e231SKonstantin Khorenko * Return: Void. 273*e346e231SKonstantin Khorenko */ 274*e346e231SKonstantin Khorenko void qed_get_vport_stats_context(struct qed_dev *cdev, 275*e346e231SKonstantin Khorenko struct qed_eth_stats *stats, 276*e346e231SKonstantin Khorenko bool is_atomic); 277*e346e231SKonstantin Khorenko 2783da7a37aSMintz, Yuval void qed_reset_vport_stats(struct qed_dev *cdev); 2793da7a37aSMintz, Yuval 280da090917STomer Tayar /** 28119198e4eSPrabhakar Kushwaha * qed_arfs_mode_configure(): Enable or disable rfs mode. 28219198e4eSPrabhakar Kushwaha * It must accept at least one of tcp or udp true 28319198e4eSPrabhakar Kushwaha * and at least one of ipv4 or ipv6 true to enable 28419198e4eSPrabhakar Kushwaha * rfs mode. 285da090917STomer Tayar * 28619198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 28719198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 28819198e4eSPrabhakar Kushwaha * @p_cfg_params: arfs mode configuration parameters. 289da090917STomer Tayar * 29019198e4eSPrabhakar Kushwaha * Return. Void. 291da090917STomer Tayar */ 292da090917STomer Tayar void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, 293da090917STomer Tayar struct qed_ptt *p_ptt, 294da090917STomer Tayar struct qed_arfs_config_params *p_cfg_params); 295da090917STomer Tayar 296da090917STomer Tayar /** 29719198e4eSPrabhakar Kushwaha * qed_configure_rfs_ntuple_filter(): This ramrod should be used to add 29819198e4eSPrabhakar Kushwaha * or remove arfs hw filter 299da090917STomer Tayar * 30019198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 30119198e4eSPrabhakar Kushwaha * @p_cb: Used for QED_SPQ_MODE_CB,where client would initialize 302da090917STomer Tayar * it with cookie and callback function address, if not 303da090917STomer Tayar * using this mode then client must pass NULL. 30419198e4eSPrabhakar Kushwaha * @p_params: Pointer to params. 30519198e4eSPrabhakar Kushwaha * 30619198e4eSPrabhakar Kushwaha * Return: Void. 307da090917STomer Tayar */ 308da090917STomer Tayar int 309da090917STomer Tayar qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, 310da090917STomer Tayar struct qed_spq_comp_cb *p_cb, 311da090917STomer Tayar struct qed_ntuple_filter_params *p_params); 312da090917STomer Tayar 3130db711bbSMintz, Yuval #define MAX_QUEUES_PER_QZONE (sizeof(unsigned long) * 8) 3143946497aSMintz, Yuval #define QED_QUEUE_CID_SELF (0xff) 3150db711bbSMintz, Yuval 316f604b17dSMintz, Yuval /* Almost identical to the qed_queue_start_common_params, 317f604b17dSMintz, Yuval * but here we maintain the SB index in IGU CAM. 3183da7a37aSMintz, Yuval */ 319f604b17dSMintz, Yuval struct qed_queue_cid_params { 320f604b17dSMintz, Yuval u8 vport_id; 321f604b17dSMintz, Yuval u16 queue_id; 322f604b17dSMintz, Yuval u8 stats_id; 323f604b17dSMintz, Yuval }; 324f604b17dSMintz, Yuval 3253946497aSMintz, Yuval /* Additional parameters required for initialization of the queue_cid 3263946497aSMintz, Yuval * and are relevant only for a PF initializing one for its VFs. 3273946497aSMintz, Yuval */ 3283946497aSMintz, Yuval struct qed_queue_cid_vf_params { 3293946497aSMintz, Yuval /* Should match the VF's relative index */ 3303946497aSMintz, Yuval u8 vfid; 3313946497aSMintz, Yuval 3323946497aSMintz, Yuval /* 0-based queue index. Should reflect the relative qzone the 3333946497aSMintz, Yuval * VF thinks is associated with it [in its range]. 3343946497aSMintz, Yuval */ 3353946497aSMintz, Yuval u8 vf_qid; 3363946497aSMintz, Yuval 3373b19f478SMintz, Yuval /* Indicates a VF is legacy, making it differ in several things: 3383946497aSMintz, Yuval * - Producers would be placed in a different place. 3393b19f478SMintz, Yuval * - Makes assumptions regarding the CIDs. 3403946497aSMintz, Yuval */ 3413b19f478SMintz, Yuval u8 vf_legacy; 3423946497aSMintz, Yuval 343bbe3f233SMintz, Yuval u8 qid_usage_idx; 3443946497aSMintz, Yuval }; 3453946497aSMintz, Yuval 346f604b17dSMintz, Yuval struct qed_queue_cid { 347f604b17dSMintz, Yuval /* For stats-id, the `rel' is actually absolute as well */ 348f604b17dSMintz, Yuval struct qed_queue_cid_params rel; 349f604b17dSMintz, Yuval struct qed_queue_cid_params abs; 350f604b17dSMintz, Yuval 351f604b17dSMintz, Yuval /* These have no 'relative' meaning */ 352f604b17dSMintz, Yuval u16 sb_igu_id; 353f604b17dSMintz, Yuval u8 sb_idx; 354f604b17dSMintz, Yuval 3553da7a37aSMintz, Yuval u32 cid; 3563da7a37aSMintz, Yuval u16 opaque_fid; 3573da7a37aSMintz, Yuval 358007bc371SMintz, Yuval bool b_is_rx; 359007bc371SMintz, Yuval 3603da7a37aSMintz, Yuval /* VFs queues are mapped differently, so we need to know the 3613da7a37aSMintz, Yuval * relative queue associated with them [0-based]. 3623da7a37aSMintz, Yuval * Notice this is relevant on the *PF* queue-cid of its VF's queues, 3633da7a37aSMintz, Yuval * and not on the VF itself. 3643da7a37aSMintz, Yuval */ 3653946497aSMintz, Yuval u8 vfid; 3663da7a37aSMintz, Yuval u8 vf_qid; 3673da7a37aSMintz, Yuval 368bbe3f233SMintz, Yuval /* We need an additional index to differentiate between queues opened 369bbe3f233SMintz, Yuval * for same queue-zone, as VFs would have to communicate the info 370bbe3f233SMintz, Yuval * to the PF [otherwise PF has no way to differentiate]. 371bbe3f233SMintz, Yuval */ 372bbe3f233SMintz, Yuval u8 qid_usage_idx; 373bbe3f233SMintz, Yuval 3743b19f478SMintz, Yuval u8 vf_legacy; 3753b19f478SMintz, Yuval #define QED_QCID_LEGACY_VF_RX_PROD (BIT(0)) 3763b19f478SMintz, Yuval #define QED_QCID_LEGACY_VF_CID (BIT(1)) 377f29ffdb6SMintz, Yuval 378f29ffdb6SMintz, Yuval struct qed_hwfn *p_owner; 3793da7a37aSMintz, Yuval }; 3803da7a37aSMintz, Yuval 3810db711bbSMintz, Yuval int qed_l2_alloc(struct qed_hwfn *p_hwfn); 3820db711bbSMintz, Yuval void qed_l2_setup(struct qed_hwfn *p_hwfn); 3830db711bbSMintz, Yuval void qed_l2_free(struct qed_hwfn *p_hwfn); 3840db711bbSMintz, Yuval 3853da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn, 3863da7a37aSMintz, Yuval struct qed_queue_cid *p_cid); 3873da7a37aSMintz, Yuval 3883946497aSMintz, Yuval struct qed_queue_cid * 3893946497aSMintz, Yuval qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 3903da7a37aSMintz, Yuval u16 opaque_fid, 3913946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 392007bc371SMintz, Yuval bool b_is_rx, 3933946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params); 3943da7a37aSMintz, Yuval 3953da7a37aSMintz, Yuval int 3963da7a37aSMintz, Yuval qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 397dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params); 398dacd88d6SYuval Mintz 3993da7a37aSMintz, Yuval /** 40019198e4eSPrabhakar Kushwaha * qed_eth_rxq_start_ramrod(): Starts an Rx queue, when queue_cid is 40119198e4eSPrabhakar Kushwaha * already prepared 4023da7a37aSMintz, Yuval * 40319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 40419198e4eSPrabhakar Kushwaha * @p_cid: Pointer CID. 40519198e4eSPrabhakar Kushwaha * @bd_max_bytes: Max bytes. 40619198e4eSPrabhakar Kushwaha * @bd_chain_phys_addr: Chain physcial address. 40719198e4eSPrabhakar Kushwaha * @cqe_pbl_addr: PBL address. 40819198e4eSPrabhakar Kushwaha * @cqe_pbl_size: PBL size. 4093da7a37aSMintz, Yuval * 41019198e4eSPrabhakar Kushwaha * Return: Int. 4113da7a37aSMintz, Yuval */ 4123da7a37aSMintz, Yuval int 4133da7a37aSMintz, Yuval qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 4143da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 415dacd88d6SYuval Mintz u16 bd_max_bytes, 416dacd88d6SYuval Mintz dma_addr_t bd_chain_phys_addr, 4173da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size); 418dacd88d6SYuval Mintz 4193da7a37aSMintz, Yuval /** 42019198e4eSPrabhakar Kushwaha * qed_eth_txq_start_ramrod(): Starts a Tx queue, where queue_cid is 42119198e4eSPrabhakar Kushwaha * already prepared 4223da7a37aSMintz, Yuval * 42319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 42419198e4eSPrabhakar Kushwaha * @p_cid: Pointer CID. 42519198e4eSPrabhakar Kushwaha * @pbl_addr: PBL address. 42619198e4eSPrabhakar Kushwaha * @pbl_size: PBL size. 42719198e4eSPrabhakar Kushwaha * @pq_id: Parameters for choosing the PQ for this Tx queue. 4283da7a37aSMintz, Yuval * 42919198e4eSPrabhakar Kushwaha * Return: Int. 4303da7a37aSMintz, Yuval */ 4313da7a37aSMintz, Yuval int 4323da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 4333da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 4343da7a37aSMintz, Yuval dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id); 435dacd88d6SYuval Mintz 436dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac); 437dacd88d6SYuval Mintz 438477f2d14SRahul Verma int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 439477f2d14SRahul Verma struct qed_ptt *p_ptt, 440477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid); 441477f2d14SRahul Verma 442477f2d14SRahul Verma int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 443477f2d14SRahul Verma struct qed_ptt *p_ptt, 444477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid); 445bf5a94bfSRahul Verma 446bf5a94bfSRahul Verma int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn, 447bf5a94bfSRahul Verma struct qed_ptt *p_ptt, 448bf5a94bfSRahul Verma struct qed_queue_cid *p_cid, u16 *p_hw_coal); 449bf5a94bfSRahul Verma 450bf5a94bfSRahul Verma int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn, 451bf5a94bfSRahul Verma struct qed_ptt *p_ptt, 452bf5a94bfSRahul Verma struct qed_queue_cid *p_cid, u16 *p_hw_coal); 453bf5a94bfSRahul Verma 454bf5a94bfSRahul Verma #endif 455