1dacd88d6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3dacd88d6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31dacd88d6SYuval Mintz */ 32dacd88d6SYuval Mintz #ifndef _QED_L2_H 33dacd88d6SYuval Mintz #define _QED_L2_H 34dacd88d6SYuval Mintz #include <linux/types.h> 35dacd88d6SYuval Mintz #include <linux/io.h> 36dacd88d6SYuval Mintz #include <linux/kernel.h> 37dacd88d6SYuval Mintz #include <linux/slab.h> 38dacd88d6SYuval Mintz #include <linux/qed/qed_eth_if.h> 39dacd88d6SYuval Mintz #include "qed.h" 40dacd88d6SYuval Mintz #include "qed_hw.h" 41dacd88d6SYuval Mintz #include "qed_sp.h" 42f29ffdb6SMintz, Yuval struct qed_rss_params { 43f29ffdb6SMintz, Yuval u8 update_rss_config; 44f29ffdb6SMintz, Yuval u8 rss_enable; 45f29ffdb6SMintz, Yuval u8 rss_eng_id; 46f29ffdb6SMintz, Yuval u8 update_rss_capabilities; 47f29ffdb6SMintz, Yuval u8 update_rss_ind_table; 48f29ffdb6SMintz, Yuval u8 update_rss_key; 49f29ffdb6SMintz, Yuval u8 rss_caps; 50f29ffdb6SMintz, Yuval u8 rss_table_size_log; 51f29ffdb6SMintz, Yuval 52f29ffdb6SMintz, Yuval /* Indirection table consist of rx queue handles */ 53f29ffdb6SMintz, Yuval void *rss_ind_table[QED_RSS_IND_TABLE_SIZE]; 54f29ffdb6SMintz, Yuval u32 rss_key[QED_RSS_KEY_SIZE]; 55f29ffdb6SMintz, Yuval }; 56dacd88d6SYuval Mintz 5717b235c1SYuval Mintz struct qed_sge_tpa_params { 5817b235c1SYuval Mintz u8 max_buffers_per_cqe; 5917b235c1SYuval Mintz 6017b235c1SYuval Mintz u8 update_tpa_en_flg; 6117b235c1SYuval Mintz u8 tpa_ipv4_en_flg; 6217b235c1SYuval Mintz u8 tpa_ipv6_en_flg; 6317b235c1SYuval Mintz u8 tpa_ipv4_tunn_en_flg; 6417b235c1SYuval Mintz u8 tpa_ipv6_tunn_en_flg; 6517b235c1SYuval Mintz 6617b235c1SYuval Mintz u8 update_tpa_param_flg; 6717b235c1SYuval Mintz u8 tpa_pkt_split_flg; 6817b235c1SYuval Mintz u8 tpa_hdr_data_split_flg; 6917b235c1SYuval Mintz u8 tpa_gro_consistent_flg; 7017b235c1SYuval Mintz u8 tpa_max_aggs_num; 7117b235c1SYuval Mintz u16 tpa_max_size; 7217b235c1SYuval Mintz u16 tpa_min_size_to_start; 7317b235c1SYuval Mintz u16 tpa_min_size_to_cont; 7417b235c1SYuval Mintz }; 7517b235c1SYuval Mintz 76dacd88d6SYuval Mintz enum qed_filter_opcode { 77dacd88d6SYuval Mintz QED_FILTER_ADD, 78dacd88d6SYuval Mintz QED_FILTER_REMOVE, 79dacd88d6SYuval Mintz QED_FILTER_MOVE, 80dacd88d6SYuval Mintz QED_FILTER_REPLACE, /* Delete all MACs and add new one instead */ 81dacd88d6SYuval Mintz QED_FILTER_FLUSH, /* Removes all filters */ 82dacd88d6SYuval Mintz }; 83dacd88d6SYuval Mintz 84dacd88d6SYuval Mintz enum qed_filter_ucast_type { 85dacd88d6SYuval Mintz QED_FILTER_MAC, 86dacd88d6SYuval Mintz QED_FILTER_VLAN, 87dacd88d6SYuval Mintz QED_FILTER_MAC_VLAN, 88dacd88d6SYuval Mintz QED_FILTER_INNER_MAC, 89dacd88d6SYuval Mintz QED_FILTER_INNER_VLAN, 90dacd88d6SYuval Mintz QED_FILTER_INNER_PAIR, 91dacd88d6SYuval Mintz QED_FILTER_INNER_MAC_VNI_PAIR, 92dacd88d6SYuval Mintz QED_FILTER_MAC_VNI_PAIR, 93dacd88d6SYuval Mintz QED_FILTER_VNI, 94dacd88d6SYuval Mintz }; 95dacd88d6SYuval Mintz 96dacd88d6SYuval Mintz struct qed_filter_ucast { 97dacd88d6SYuval Mintz enum qed_filter_opcode opcode; 98dacd88d6SYuval Mintz enum qed_filter_ucast_type type; 99dacd88d6SYuval Mintz u8 is_rx_filter; 100dacd88d6SYuval Mintz u8 is_tx_filter; 101dacd88d6SYuval Mintz u8 vport_to_add_to; 102dacd88d6SYuval Mintz u8 vport_to_remove_from; 103dacd88d6SYuval Mintz unsigned char mac[ETH_ALEN]; 104dacd88d6SYuval Mintz u8 assert_on_error; 105dacd88d6SYuval Mintz u16 vlan; 106dacd88d6SYuval Mintz u32 vni; 107dacd88d6SYuval Mintz }; 108dacd88d6SYuval Mintz 109dacd88d6SYuval Mintz struct qed_filter_mcast { 110dacd88d6SYuval Mintz /* MOVE is not supported for multicast */ 111dacd88d6SYuval Mintz enum qed_filter_opcode opcode; 112dacd88d6SYuval Mintz u8 vport_to_add_to; 113dacd88d6SYuval Mintz u8 vport_to_remove_from; 114dacd88d6SYuval Mintz u8 num_mc_addrs; 115dacd88d6SYuval Mintz #define QED_MAX_MC_ADDRS 64 116dacd88d6SYuval Mintz unsigned char mac[QED_MAX_MC_ADDRS][ETH_ALEN]; 117dacd88d6SYuval Mintz }; 118dacd88d6SYuval Mintz 1193da7a37aSMintz, Yuval /** 1203da7a37aSMintz, Yuval * @brief qed_eth_rx_queue_stop - This ramrod closes an Rx queue 1213da7a37aSMintz, Yuval * 1223da7a37aSMintz, Yuval * @param p_hwfn 1233da7a37aSMintz, Yuval * @param p_rxq Handler of queue to close 1243da7a37aSMintz, Yuval * @param eq_completion_only If True completion will be on 1253da7a37aSMintz, Yuval * EQe, if False completion will be 1263da7a37aSMintz, Yuval * on EQe if p_hwfn opaque 1273da7a37aSMintz, Yuval * different from the RXQ opaque 1283da7a37aSMintz, Yuval * otherwise on CQe. 1293da7a37aSMintz, Yuval * @param cqe_completion If True completion will be 1303da7a37aSMintz, Yuval * receive on CQe. 1313da7a37aSMintz, Yuval * @return int 1323da7a37aSMintz, Yuval */ 1333da7a37aSMintz, Yuval int 1343da7a37aSMintz, Yuval qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 1353da7a37aSMintz, Yuval void *p_rxq, 136dacd88d6SYuval Mintz bool eq_completion_only, bool cqe_completion); 137dacd88d6SYuval Mintz 1383da7a37aSMintz, Yuval /** 1393da7a37aSMintz, Yuval * @brief qed_eth_tx_queue_stop - closes a Tx queue 1403da7a37aSMintz, Yuval * 1413da7a37aSMintz, Yuval * @param p_hwfn 1423da7a37aSMintz, Yuval * @param p_txq - handle to Tx queue needed to be closed 1433da7a37aSMintz, Yuval * 1443da7a37aSMintz, Yuval * @return int 1453da7a37aSMintz, Yuval */ 1463da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_txq); 147dacd88d6SYuval Mintz 148dacd88d6SYuval Mintz enum qed_tpa_mode { 149dacd88d6SYuval Mintz QED_TPA_MODE_NONE, 150dacd88d6SYuval Mintz QED_TPA_MODE_UNUSED, 151dacd88d6SYuval Mintz QED_TPA_MODE_GRO, 152dacd88d6SYuval Mintz QED_TPA_MODE_MAX 153dacd88d6SYuval Mintz }; 154dacd88d6SYuval Mintz 155dacd88d6SYuval Mintz struct qed_sp_vport_start_params { 156dacd88d6SYuval Mintz enum qed_tpa_mode tpa_mode; 157dacd88d6SYuval Mintz bool remove_inner_vlan; 158831bfb0eSYuval Mintz bool tx_switching; 159c78c70faSSudarsana Reddy Kalluru bool handle_ptp_pkts; 16008feecd7SYuval Mintz bool only_untagged; 161dacd88d6SYuval Mintz bool drop_ttl0; 162dacd88d6SYuval Mintz u8 max_buffers_per_cqe; 163dacd88d6SYuval Mintz u32 concrete_fid; 164dacd88d6SYuval Mintz u16 opaque_fid; 165dacd88d6SYuval Mintz u8 vport_id; 166dacd88d6SYuval Mintz u16 mtu; 16711a85d75SYuval Mintz bool check_mac; 16811a85d75SYuval Mintz bool check_ethtype; 169dacd88d6SYuval Mintz }; 170dacd88d6SYuval Mintz 171dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 172dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params); 173dacd88d6SYuval Mintz 174dacd88d6SYuval Mintz 175dacd88d6SYuval Mintz struct qed_filter_accept_flags { 176dacd88d6SYuval Mintz u8 update_rx_mode_config; 177dacd88d6SYuval Mintz u8 update_tx_mode_config; 178dacd88d6SYuval Mintz u8 rx_accept_filter; 179dacd88d6SYuval Mintz u8 tx_accept_filter; 180dacd88d6SYuval Mintz #define QED_ACCEPT_NONE 0x01 181dacd88d6SYuval Mintz #define QED_ACCEPT_UCAST_MATCHED 0x02 182dacd88d6SYuval Mintz #define QED_ACCEPT_UCAST_UNMATCHED 0x04 183dacd88d6SYuval Mintz #define QED_ACCEPT_MCAST_MATCHED 0x08 184dacd88d6SYuval Mintz #define QED_ACCEPT_MCAST_UNMATCHED 0x10 185dacd88d6SYuval Mintz #define QED_ACCEPT_BCAST 0x20 186dacd88d6SYuval Mintz }; 187dacd88d6SYuval Mintz 188d51e4af5SChopra, Manish struct qed_arfs_config_params { 189d51e4af5SChopra, Manish bool tcp; 190d51e4af5SChopra, Manish bool udp; 191d51e4af5SChopra, Manish bool ipv4; 192d51e4af5SChopra, Manish bool ipv6; 193d51e4af5SChopra, Manish bool arfs_enable; 194d51e4af5SChopra, Manish }; 195d51e4af5SChopra, Manish 196dacd88d6SYuval Mintz struct qed_sp_vport_update_params { 197dacd88d6SYuval Mintz u16 opaque_fid; 198dacd88d6SYuval Mintz u8 vport_id; 199dacd88d6SYuval Mintz u8 update_vport_active_rx_flg; 200dacd88d6SYuval Mintz u8 vport_active_rx_flg; 201dacd88d6SYuval Mintz u8 update_vport_active_tx_flg; 202dacd88d6SYuval Mintz u8 vport_active_tx_flg; 20317b235c1SYuval Mintz u8 update_inner_vlan_removal_flg; 20417b235c1SYuval Mintz u8 inner_vlan_removal_flg; 20508feecd7SYuval Mintz u8 silent_vlan_removal_flg; 20608feecd7SYuval Mintz u8 update_default_vlan_enable_flg; 20708feecd7SYuval Mintz u8 default_vlan_enable_flg; 20808feecd7SYuval Mintz u8 update_default_vlan_flg; 20908feecd7SYuval Mintz u16 default_vlan; 21017b235c1SYuval Mintz u8 update_tx_switching_flg; 21117b235c1SYuval Mintz u8 tx_switching_flg; 212dacd88d6SYuval Mintz u8 update_approx_mcast_flg; 2136ddc7608SYuval Mintz u8 update_anti_spoofing_en_flg; 2146ddc7608SYuval Mintz u8 anti_spoofing_en; 215dacd88d6SYuval Mintz u8 update_accept_any_vlan_flg; 216dacd88d6SYuval Mintz u8 accept_any_vlan; 217dacd88d6SYuval Mintz unsigned long bins[8]; 218dacd88d6SYuval Mintz struct qed_rss_params *rss_params; 219dacd88d6SYuval Mintz struct qed_filter_accept_flags accept_flags; 22017b235c1SYuval Mintz struct qed_sge_tpa_params *sge_tpa_params; 221dacd88d6SYuval Mintz }; 222dacd88d6SYuval Mintz 223dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 224dacd88d6SYuval Mintz struct qed_sp_vport_update_params *p_params, 225dacd88d6SYuval Mintz enum spq_mode comp_mode, 226dacd88d6SYuval Mintz struct qed_spq_comp_cb *p_comp_data); 227dacd88d6SYuval Mintz 228dacd88d6SYuval Mintz /** 229dacd88d6SYuval Mintz * @brief qed_sp_vport_stop - 230dacd88d6SYuval Mintz * 231dacd88d6SYuval Mintz * This ramrod closes a VPort after all its RX and TX queues are terminated. 232dacd88d6SYuval Mintz * An Assert is generated if any queues are left open. 233dacd88d6SYuval Mintz * 234dacd88d6SYuval Mintz * @param p_hwfn 235dacd88d6SYuval Mintz * @param opaque_fid 236dacd88d6SYuval Mintz * @param vport_id VPort ID 237dacd88d6SYuval Mintz * 238dacd88d6SYuval Mintz * @return int 239dacd88d6SYuval Mintz */ 240dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id); 241dacd88d6SYuval Mintz 242dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 243dacd88d6SYuval Mintz u16 opaque_fid, 244dacd88d6SYuval Mintz struct qed_filter_ucast *p_filter_cmd, 245dacd88d6SYuval Mintz enum spq_mode comp_mode, 246dacd88d6SYuval Mintz struct qed_spq_comp_cb *p_comp_data); 247dacd88d6SYuval Mintz 24817b235c1SYuval Mintz /** 24917b235c1SYuval Mintz * @brief qed_sp_rx_eth_queues_update - 25017b235c1SYuval Mintz * 25117b235c1SYuval Mintz * This ramrod updates an RX queue. It is used for setting the active state 25217b235c1SYuval Mintz * of the queue and updating the TPA and SGE parameters. 25317b235c1SYuval Mintz * 25417b235c1SYuval Mintz * @note At the moment - only used by non-linux VFs. 25517b235c1SYuval Mintz * 25617b235c1SYuval Mintz * @param p_hwfn 2573da7a37aSMintz, Yuval * @param pp_rxq_handlers An array of queue handlers to be updated. 2583da7a37aSMintz, Yuval * @param num_rxqs number of queues to update. 25917b235c1SYuval Mintz * @param complete_cqe_flg Post completion to the CQE Ring if set 26017b235c1SYuval Mintz * @param complete_event_flg Post completion to the Event Ring if set 2613da7a37aSMintz, Yuval * @param comp_mode 2623da7a37aSMintz, Yuval * @param p_comp_data 26317b235c1SYuval Mintz * 26417b235c1SYuval Mintz * @return int 26517b235c1SYuval Mintz */ 26617b235c1SYuval Mintz 26717b235c1SYuval Mintz int 26817b235c1SYuval Mintz qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 2693da7a37aSMintz, Yuval void **pp_rxq_handlers, 27017b235c1SYuval Mintz u8 num_rxqs, 27117b235c1SYuval Mintz u8 complete_cqe_flg, 27217b235c1SYuval Mintz u8 complete_event_flg, 27317b235c1SYuval Mintz enum spq_mode comp_mode, 27417b235c1SYuval Mintz struct qed_spq_comp_cb *p_comp_data); 27517b235c1SYuval Mintz 2766c754246SSudarsana Reddy Kalluru void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats); 2776c754246SSudarsana Reddy Kalluru 2783da7a37aSMintz, Yuval void qed_reset_vport_stats(struct qed_dev *cdev); 2793da7a37aSMintz, Yuval 2800db711bbSMintz, Yuval #define MAX_QUEUES_PER_QZONE (sizeof(unsigned long) * 8) 2813946497aSMintz, Yuval #define QED_QUEUE_CID_SELF (0xff) 2820db711bbSMintz, Yuval 283f604b17dSMintz, Yuval /* Almost identical to the qed_queue_start_common_params, 284f604b17dSMintz, Yuval * but here we maintain the SB index in IGU CAM. 2853da7a37aSMintz, Yuval */ 286f604b17dSMintz, Yuval struct qed_queue_cid_params { 287f604b17dSMintz, Yuval u8 vport_id; 288f604b17dSMintz, Yuval u16 queue_id; 289f604b17dSMintz, Yuval u8 stats_id; 290f604b17dSMintz, Yuval }; 291f604b17dSMintz, Yuval 2923946497aSMintz, Yuval /* Additional parameters required for initialization of the queue_cid 2933946497aSMintz, Yuval * and are relevant only for a PF initializing one for its VFs. 2943946497aSMintz, Yuval */ 2953946497aSMintz, Yuval struct qed_queue_cid_vf_params { 2963946497aSMintz, Yuval /* Should match the VF's relative index */ 2973946497aSMintz, Yuval u8 vfid; 2983946497aSMintz, Yuval 2993946497aSMintz, Yuval /* 0-based queue index. Should reflect the relative qzone the 3003946497aSMintz, Yuval * VF thinks is associated with it [in its range]. 3013946497aSMintz, Yuval */ 3023946497aSMintz, Yuval u8 vf_qid; 3033946497aSMintz, Yuval 3043b19f478SMintz, Yuval /* Indicates a VF is legacy, making it differ in several things: 3053946497aSMintz, Yuval * - Producers would be placed in a different place. 3063b19f478SMintz, Yuval * - Makes assumptions regarding the CIDs. 3073946497aSMintz, Yuval */ 3083b19f478SMintz, Yuval u8 vf_legacy; 3093946497aSMintz, Yuval 310bbe3f233SMintz, Yuval u8 qid_usage_idx; 3113946497aSMintz, Yuval }; 3123946497aSMintz, Yuval 313f604b17dSMintz, Yuval struct qed_queue_cid { 314f604b17dSMintz, Yuval /* For stats-id, the `rel' is actually absolute as well */ 315f604b17dSMintz, Yuval struct qed_queue_cid_params rel; 316f604b17dSMintz, Yuval struct qed_queue_cid_params abs; 317f604b17dSMintz, Yuval 318f604b17dSMintz, Yuval /* These have no 'relative' meaning */ 319f604b17dSMintz, Yuval u16 sb_igu_id; 320f604b17dSMintz, Yuval u8 sb_idx; 321f604b17dSMintz, Yuval 3223da7a37aSMintz, Yuval u32 cid; 3233da7a37aSMintz, Yuval u16 opaque_fid; 3243da7a37aSMintz, Yuval 325007bc371SMintz, Yuval bool b_is_rx; 326007bc371SMintz, Yuval 3273da7a37aSMintz, Yuval /* VFs queues are mapped differently, so we need to know the 3283da7a37aSMintz, Yuval * relative queue associated with them [0-based]. 3293da7a37aSMintz, Yuval * Notice this is relevant on the *PF* queue-cid of its VF's queues, 3303da7a37aSMintz, Yuval * and not on the VF itself. 3313da7a37aSMintz, Yuval */ 3323946497aSMintz, Yuval u8 vfid; 3333da7a37aSMintz, Yuval u8 vf_qid; 3343da7a37aSMintz, Yuval 335bbe3f233SMintz, Yuval /* We need an additional index to differentiate between queues opened 336bbe3f233SMintz, Yuval * for same queue-zone, as VFs would have to communicate the info 337bbe3f233SMintz, Yuval * to the PF [otherwise PF has no way to differentiate]. 338bbe3f233SMintz, Yuval */ 339bbe3f233SMintz, Yuval u8 qid_usage_idx; 340bbe3f233SMintz, Yuval 3413b19f478SMintz, Yuval u8 vf_legacy; 3423b19f478SMintz, Yuval #define QED_QCID_LEGACY_VF_RX_PROD (BIT(0)) 3433b19f478SMintz, Yuval #define QED_QCID_LEGACY_VF_CID (BIT(1)) 344f29ffdb6SMintz, Yuval 345f29ffdb6SMintz, Yuval struct qed_hwfn *p_owner; 3463da7a37aSMintz, Yuval }; 3473da7a37aSMintz, Yuval 3480db711bbSMintz, Yuval int qed_l2_alloc(struct qed_hwfn *p_hwfn); 3490db711bbSMintz, Yuval void qed_l2_setup(struct qed_hwfn *p_hwfn); 3500db711bbSMintz, Yuval void qed_l2_free(struct qed_hwfn *p_hwfn); 3510db711bbSMintz, Yuval 3523da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn, 3533da7a37aSMintz, Yuval struct qed_queue_cid *p_cid); 3543da7a37aSMintz, Yuval 3553946497aSMintz, Yuval struct qed_queue_cid * 3563946497aSMintz, Yuval qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 3573da7a37aSMintz, Yuval u16 opaque_fid, 3583946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 359007bc371SMintz, Yuval bool b_is_rx, 3603946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params); 3613da7a37aSMintz, Yuval 3623da7a37aSMintz, Yuval int 3633da7a37aSMintz, Yuval qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 364dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params); 365dacd88d6SYuval Mintz 3663da7a37aSMintz, Yuval /** 3673da7a37aSMintz, Yuval * @brief - Starts an Rx queue, when queue_cid is already prepared 3683da7a37aSMintz, Yuval * 3693da7a37aSMintz, Yuval * @param p_hwfn 3703da7a37aSMintz, Yuval * @param p_cid 3713da7a37aSMintz, Yuval * @param bd_max_bytes 3723da7a37aSMintz, Yuval * @param bd_chain_phys_addr 3733da7a37aSMintz, Yuval * @param cqe_pbl_addr 3743da7a37aSMintz, Yuval * @param cqe_pbl_size 3753da7a37aSMintz, Yuval * 3763da7a37aSMintz, Yuval * @return int 3773da7a37aSMintz, Yuval */ 3783da7a37aSMintz, Yuval int 3793da7a37aSMintz, Yuval qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 3803da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 381dacd88d6SYuval Mintz u16 bd_max_bytes, 382dacd88d6SYuval Mintz dma_addr_t bd_chain_phys_addr, 3833da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size); 384dacd88d6SYuval Mintz 3853da7a37aSMintz, Yuval /** 3863da7a37aSMintz, Yuval * @brief - Starts a Tx queue, where queue_cid is already prepared 3873da7a37aSMintz, Yuval * 3883da7a37aSMintz, Yuval * @param p_hwfn 3893da7a37aSMintz, Yuval * @param p_cid 3903da7a37aSMintz, Yuval * @param pbl_addr 3913da7a37aSMintz, Yuval * @param pbl_size 3923da7a37aSMintz, Yuval * @param p_pq_params - parameters for choosing the PQ for this Tx queue 3933da7a37aSMintz, Yuval * 3943da7a37aSMintz, Yuval * @return int 3953da7a37aSMintz, Yuval */ 3963da7a37aSMintz, Yuval int 3973da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 3983da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 3993da7a37aSMintz, Yuval dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id); 400dacd88d6SYuval Mintz 401dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac); 402dacd88d6SYuval Mintz 403477f2d14SRahul Verma int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 404477f2d14SRahul Verma struct qed_ptt *p_ptt, 405477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid); 406477f2d14SRahul Verma 407477f2d14SRahul Verma int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 408477f2d14SRahul Verma struct qed_ptt *p_ptt, 409477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid); 410dacd88d6SYuval Mintz #endif /* _QED_L2_H */ 411