1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <asm/param.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/etherdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/slab.h> 20 #include <linux/stddef.h> 21 #include <linux/string.h> 22 #include <linux/version.h> 23 #include <linux/workqueue.h> 24 #include <linux/bitops.h> 25 #include <linux/bug.h> 26 #include "qed.h" 27 #include <linux/qed/qed_chain.h> 28 #include "qed_cxt.h" 29 #include "qed_dev_api.h" 30 #include <linux/qed/qed_eth_if.h> 31 #include "qed_hsi.h" 32 #include "qed_hw.h" 33 #include "qed_int.h" 34 #include "qed_l2.h" 35 #include "qed_mcp.h" 36 #include "qed_reg_addr.h" 37 #include "qed_sp.h" 38 #include "qed_sriov.h" 39 40 41 #define QED_MAX_SGES_NUM 16 42 #define CRC32_POLY 0x1edc6f41 43 44 int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 45 struct qed_sp_vport_start_params *p_params) 46 { 47 struct vport_start_ramrod_data *p_ramrod = NULL; 48 struct qed_spq_entry *p_ent = NULL; 49 struct qed_sp_init_data init_data; 50 u8 abs_vport_id = 0; 51 int rc = -EINVAL; 52 u16 rx_mode = 0; 53 54 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 55 if (rc != 0) 56 return rc; 57 58 memset(&init_data, 0, sizeof(init_data)); 59 init_data.cid = qed_spq_get_cid(p_hwfn); 60 init_data.opaque_fid = p_params->opaque_fid; 61 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 62 63 rc = qed_sp_init_request(p_hwfn, &p_ent, 64 ETH_RAMROD_VPORT_START, 65 PROTOCOLID_ETH, &init_data); 66 if (rc) 67 return rc; 68 69 p_ramrod = &p_ent->ramrod.vport_start; 70 p_ramrod->vport_id = abs_vport_id; 71 72 p_ramrod->mtu = cpu_to_le16(p_params->mtu); 73 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 74 p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 75 p_ramrod->untagged = p_params->only_untagged; 76 77 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 78 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 79 80 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 81 82 /* TPA related fields */ 83 memset(&p_ramrod->tpa_param, 0, 84 sizeof(struct eth_vport_tpa_param)); 85 86 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; 87 88 switch (p_params->tpa_mode) { 89 case QED_TPA_MODE_GRO: 90 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 91 p_ramrod->tpa_param.tpa_max_size = (u16)-1; 92 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; 93 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; 94 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; 95 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; 96 p_ramrod->tpa_param.tpa_pkt_split_flg = 1; 97 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; 98 break; 99 default: 100 break; 101 } 102 103 p_ramrod->tx_switching_en = p_params->tx_switching; 104 105 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 106 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 107 p_params->concrete_fid); 108 109 return qed_spq_post(p_hwfn, p_ent, NULL); 110 } 111 112 int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 113 struct qed_sp_vport_start_params *p_params) 114 { 115 if (IS_VF(p_hwfn->cdev)) { 116 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, 117 p_params->mtu, 118 p_params->remove_inner_vlan, 119 p_params->tpa_mode, 120 p_params->max_buffers_per_cqe, 121 p_params->only_untagged); 122 } 123 124 return qed_sp_eth_vport_start(p_hwfn, p_params); 125 } 126 127 static int 128 qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 129 struct vport_update_ramrod_data *p_ramrod, 130 struct qed_rss_params *p_params) 131 { 132 struct eth_vport_rss_config *rss = &p_ramrod->rss_config; 133 u16 abs_l2_queue = 0, capabilities = 0; 134 int rc = 0, i; 135 136 if (!p_params) { 137 p_ramrod->common.update_rss_flg = 0; 138 return rc; 139 } 140 141 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != 142 ETH_RSS_IND_TABLE_ENTRIES_NUM); 143 144 rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id); 145 if (rc) 146 return rc; 147 148 p_ramrod->common.update_rss_flg = p_params->update_rss_config; 149 rss->update_rss_capabilities = p_params->update_rss_capabilities; 150 rss->update_rss_ind_table = p_params->update_rss_ind_table; 151 rss->update_rss_key = p_params->update_rss_key; 152 153 rss->rss_mode = p_params->rss_enable ? 154 ETH_VPORT_RSS_MODE_REGULAR : 155 ETH_VPORT_RSS_MODE_DISABLED; 156 157 SET_FIELD(capabilities, 158 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 159 !!(p_params->rss_caps & QED_RSS_IPV4)); 160 SET_FIELD(capabilities, 161 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 162 !!(p_params->rss_caps & QED_RSS_IPV6)); 163 SET_FIELD(capabilities, 164 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 165 !!(p_params->rss_caps & QED_RSS_IPV4_TCP)); 166 SET_FIELD(capabilities, 167 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 168 !!(p_params->rss_caps & QED_RSS_IPV6_TCP)); 169 SET_FIELD(capabilities, 170 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 171 !!(p_params->rss_caps & QED_RSS_IPV4_UDP)); 172 SET_FIELD(capabilities, 173 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 174 !!(p_params->rss_caps & QED_RSS_IPV6_UDP)); 175 rss->tbl_size = p_params->rss_table_size_log; 176 177 rss->capabilities = cpu_to_le16(capabilities); 178 179 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 180 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 181 p_ramrod->common.update_rss_flg, 182 rss->rss_mode, rss->update_rss_capabilities, 183 capabilities, rss->update_rss_ind_table, 184 rss->update_rss_key); 185 186 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 187 rc = qed_fw_l2_queue(p_hwfn, 188 (u8)p_params->rss_ind_table[i], 189 &abs_l2_queue); 190 if (rc) 191 return rc; 192 193 rss->indirection_table[i] = cpu_to_le16(abs_l2_queue); 194 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n", 195 i, rss->indirection_table[i]); 196 } 197 198 for (i = 0; i < 10; i++) 199 rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]); 200 201 return rc; 202 } 203 204 static void 205 qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 206 struct vport_update_ramrod_data *p_ramrod, 207 struct qed_filter_accept_flags accept_flags) 208 { 209 p_ramrod->common.update_rx_mode_flg = 210 accept_flags.update_rx_mode_config; 211 212 p_ramrod->common.update_tx_mode_flg = 213 accept_flags.update_tx_mode_config; 214 215 /* Set Rx mode accept flags */ 216 if (p_ramrod->common.update_rx_mode_flg) { 217 u8 accept_filter = accept_flags.rx_accept_filter; 218 u16 state = 0; 219 220 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 221 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 222 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 223 224 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 225 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 226 227 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 228 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 229 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 230 231 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 232 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 233 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 234 235 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 236 !!(accept_filter & QED_ACCEPT_BCAST)); 237 238 p_ramrod->rx_mode.state = cpu_to_le16(state); 239 DP_VERBOSE(p_hwfn, QED_MSG_SP, 240 "p_ramrod->rx_mode.state = 0x%x\n", state); 241 } 242 243 /* Set Tx mode accept flags */ 244 if (p_ramrod->common.update_tx_mode_flg) { 245 u8 accept_filter = accept_flags.tx_accept_filter; 246 u16 state = 0; 247 248 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 249 !!(accept_filter & QED_ACCEPT_NONE)); 250 251 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 252 !!(accept_filter & QED_ACCEPT_NONE)); 253 254 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 255 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 256 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 257 258 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 259 !!(accept_filter & QED_ACCEPT_BCAST)); 260 261 p_ramrod->tx_mode.state = cpu_to_le16(state); 262 DP_VERBOSE(p_hwfn, QED_MSG_SP, 263 "p_ramrod->tx_mode.state = 0x%x\n", state); 264 } 265 } 266 267 static void 268 qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, 269 struct vport_update_ramrod_data *p_ramrod, 270 struct qed_sge_tpa_params *p_params) 271 { 272 struct eth_vport_tpa_param *p_tpa; 273 274 if (!p_params) { 275 p_ramrod->common.update_tpa_param_flg = 0; 276 p_ramrod->common.update_tpa_en_flg = 0; 277 p_ramrod->common.update_tpa_param_flg = 0; 278 return; 279 } 280 281 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; 282 p_tpa = &p_ramrod->tpa_param; 283 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; 284 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; 285 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; 286 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; 287 288 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; 289 p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 290 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; 291 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; 292 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; 293 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; 294 p_tpa->tpa_max_size = p_params->tpa_max_size; 295 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; 296 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; 297 } 298 299 static void 300 qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 301 struct vport_update_ramrod_data *p_ramrod, 302 struct qed_sp_vport_update_params *p_params) 303 { 304 int i; 305 306 memset(&p_ramrod->approx_mcast.bins, 0, 307 sizeof(p_ramrod->approx_mcast.bins)); 308 309 if (p_params->update_approx_mcast_flg) { 310 p_ramrod->common.update_approx_mcast_flg = 1; 311 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 312 u32 *p_bins = (u32 *)p_params->bins; 313 __le32 val = cpu_to_le32(p_bins[i]); 314 315 p_ramrod->approx_mcast.bins[i] = val; 316 } 317 } 318 } 319 320 int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 321 struct qed_sp_vport_update_params *p_params, 322 enum spq_mode comp_mode, 323 struct qed_spq_comp_cb *p_comp_data) 324 { 325 struct qed_rss_params *p_rss_params = p_params->rss_params; 326 struct vport_update_ramrod_data_cmn *p_cmn; 327 struct qed_sp_init_data init_data; 328 struct vport_update_ramrod_data *p_ramrod = NULL; 329 struct qed_spq_entry *p_ent = NULL; 330 u8 abs_vport_id = 0, val; 331 int rc = -EINVAL; 332 333 if (IS_VF(p_hwfn->cdev)) { 334 rc = qed_vf_pf_vport_update(p_hwfn, p_params); 335 return rc; 336 } 337 338 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 339 if (rc != 0) 340 return rc; 341 342 memset(&init_data, 0, sizeof(init_data)); 343 init_data.cid = qed_spq_get_cid(p_hwfn); 344 init_data.opaque_fid = p_params->opaque_fid; 345 init_data.comp_mode = comp_mode; 346 init_data.p_comp_data = p_comp_data; 347 348 rc = qed_sp_init_request(p_hwfn, &p_ent, 349 ETH_RAMROD_VPORT_UPDATE, 350 PROTOCOLID_ETH, &init_data); 351 if (rc) 352 return rc; 353 354 /* Copy input params to ramrod according to FW struct */ 355 p_ramrod = &p_ent->ramrod.vport_update; 356 p_cmn = &p_ramrod->common; 357 358 p_cmn->vport_id = abs_vport_id; 359 p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 360 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 361 p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 362 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 363 p_cmn->accept_any_vlan = p_params->accept_any_vlan; 364 p_cmn->update_accept_any_vlan_flg = 365 p_params->update_accept_any_vlan_flg; 366 367 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; 368 val = p_params->update_inner_vlan_removal_flg; 369 p_cmn->update_inner_vlan_removal_en_flg = val; 370 371 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; 372 val = p_params->update_default_vlan_enable_flg; 373 p_cmn->update_default_vlan_en_flg = val; 374 375 p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); 376 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; 377 378 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; 379 380 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; 381 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; 382 383 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; 384 val = p_params->update_anti_spoofing_en_flg; 385 p_ramrod->common.update_anti_spoofing_en_flg = val; 386 387 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 388 if (rc) { 389 /* Return spq entry which is taken in qed_sp_init_request()*/ 390 qed_spq_return_entry(p_hwfn, p_ent); 391 return rc; 392 } 393 394 /* Update mcast bins for VFs, PF doesn't use this functionality */ 395 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 396 397 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 398 qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); 399 return qed_spq_post(p_hwfn, p_ent, NULL); 400 } 401 402 int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) 403 { 404 struct vport_stop_ramrod_data *p_ramrod; 405 struct qed_sp_init_data init_data; 406 struct qed_spq_entry *p_ent; 407 u8 abs_vport_id = 0; 408 int rc; 409 410 if (IS_VF(p_hwfn->cdev)) 411 return qed_vf_pf_vport_stop(p_hwfn); 412 413 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 414 if (rc != 0) 415 return rc; 416 417 memset(&init_data, 0, sizeof(init_data)); 418 init_data.cid = qed_spq_get_cid(p_hwfn); 419 init_data.opaque_fid = opaque_fid; 420 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 421 422 rc = qed_sp_init_request(p_hwfn, &p_ent, 423 ETH_RAMROD_VPORT_STOP, 424 PROTOCOLID_ETH, &init_data); 425 if (rc) 426 return rc; 427 428 p_ramrod = &p_ent->ramrod.vport_stop; 429 p_ramrod->vport_id = abs_vport_id; 430 431 return qed_spq_post(p_hwfn, p_ent, NULL); 432 } 433 434 static int 435 qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, 436 struct qed_filter_accept_flags *p_accept_flags) 437 { 438 struct qed_sp_vport_update_params s_params; 439 440 memset(&s_params, 0, sizeof(s_params)); 441 memcpy(&s_params.accept_flags, p_accept_flags, 442 sizeof(struct qed_filter_accept_flags)); 443 444 return qed_vf_pf_vport_update(p_hwfn, &s_params); 445 } 446 447 static int qed_filter_accept_cmd(struct qed_dev *cdev, 448 u8 vport, 449 struct qed_filter_accept_flags accept_flags, 450 u8 update_accept_any_vlan, 451 u8 accept_any_vlan, 452 enum spq_mode comp_mode, 453 struct qed_spq_comp_cb *p_comp_data) 454 { 455 struct qed_sp_vport_update_params vport_update_params; 456 int i, rc; 457 458 /* Prepare and send the vport rx_mode change */ 459 memset(&vport_update_params, 0, sizeof(vport_update_params)); 460 vport_update_params.vport_id = vport; 461 vport_update_params.accept_flags = accept_flags; 462 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 463 vport_update_params.accept_any_vlan = accept_any_vlan; 464 465 for_each_hwfn(cdev, i) { 466 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 467 468 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 469 470 if (IS_VF(cdev)) { 471 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); 472 if (rc) 473 return rc; 474 continue; 475 } 476 477 rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 478 comp_mode, p_comp_data); 479 if (rc != 0) { 480 DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 481 return rc; 482 } 483 484 DP_VERBOSE(p_hwfn, QED_MSG_SP, 485 "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 486 accept_flags.rx_accept_filter, 487 accept_flags.tx_accept_filter); 488 if (update_accept_any_vlan) 489 DP_VERBOSE(p_hwfn, QED_MSG_SP, 490 "accept_any_vlan=%d configured\n", 491 accept_any_vlan); 492 } 493 494 return 0; 495 } 496 497 static int qed_sp_release_queue_cid( 498 struct qed_hwfn *p_hwfn, 499 struct qed_hw_cid_data *p_cid_data) 500 { 501 if (!p_cid_data->b_cid_allocated) 502 return 0; 503 504 qed_cxt_release_cid(p_hwfn, p_cid_data->cid); 505 506 p_cid_data->b_cid_allocated = false; 507 508 return 0; 509 } 510 511 int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 512 u16 opaque_fid, 513 u32 cid, 514 struct qed_queue_start_common_params *params, 515 u8 stats_id, 516 u16 bd_max_bytes, 517 dma_addr_t bd_chain_phys_addr, 518 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size) 519 { 520 struct rx_queue_start_ramrod_data *p_ramrod = NULL; 521 struct qed_spq_entry *p_ent = NULL; 522 struct qed_sp_init_data init_data; 523 struct qed_hw_cid_data *p_rx_cid; 524 u16 abs_rx_q_id = 0; 525 u8 abs_vport_id = 0; 526 int rc = -EINVAL; 527 528 /* Store information for the stop */ 529 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 530 p_rx_cid->cid = cid; 531 p_rx_cid->opaque_fid = opaque_fid; 532 p_rx_cid->vport_id = params->vport_id; 533 534 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id); 535 if (rc != 0) 536 return rc; 537 538 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id); 539 if (rc != 0) 540 return rc; 541 542 DP_VERBOSE(p_hwfn, QED_MSG_SP, 543 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 544 opaque_fid, cid, params->queue_id, params->vport_id, 545 params->sb); 546 547 /* Get SPQ entry */ 548 memset(&init_data, 0, sizeof(init_data)); 549 init_data.cid = cid; 550 init_data.opaque_fid = opaque_fid; 551 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 552 553 rc = qed_sp_init_request(p_hwfn, &p_ent, 554 ETH_RAMROD_RX_QUEUE_START, 555 PROTOCOLID_ETH, &init_data); 556 if (rc) 557 return rc; 558 559 p_ramrod = &p_ent->ramrod.rx_queue_start; 560 561 p_ramrod->sb_id = cpu_to_le16(params->sb); 562 p_ramrod->sb_index = params->sb_idx; 563 p_ramrod->vport_id = abs_vport_id; 564 p_ramrod->stats_counter_id = stats_id; 565 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 566 p_ramrod->complete_cqe_flg = 0; 567 p_ramrod->complete_event_flg = 1; 568 569 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 570 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 571 572 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 573 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 574 575 p_ramrod->vf_rx_prod_index = params->vf_qid; 576 if (params->vf_qid) 577 DP_VERBOSE(p_hwfn, QED_MSG_SP, 578 "Queue is meant for VF rxq[%04x]\n", params->vf_qid); 579 580 return qed_spq_post(p_hwfn, p_ent, NULL); 581 } 582 583 static int 584 qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 585 u16 opaque_fid, 586 struct qed_queue_start_common_params *params, 587 u16 bd_max_bytes, 588 dma_addr_t bd_chain_phys_addr, 589 dma_addr_t cqe_pbl_addr, 590 u16 cqe_pbl_size, void __iomem **pp_prod) 591 { 592 struct qed_hw_cid_data *p_rx_cid; 593 u32 init_prod_val = 0; 594 u16 abs_l2_queue = 0; 595 u8 abs_stats_id = 0; 596 int rc; 597 598 if (IS_VF(p_hwfn->cdev)) { 599 return qed_vf_pf_rxq_start(p_hwfn, 600 params->queue_id, 601 params->sb, 602 params->sb_idx, 603 bd_max_bytes, 604 bd_chain_phys_addr, 605 cqe_pbl_addr, cqe_pbl_size, pp_prod); 606 } 607 608 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue); 609 if (rc != 0) 610 return rc; 611 612 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id); 613 if (rc != 0) 614 return rc; 615 616 *pp_prod = (u8 __iomem *)p_hwfn->regview + 617 GTT_BAR0_MAP_REG_MSDM_RAM + 618 MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue); 619 620 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 621 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), 622 (u32 *)(&init_prod_val)); 623 624 /* Allocate a CID for the queue */ 625 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 626 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 627 &p_rx_cid->cid); 628 if (rc) { 629 DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 630 return rc; 631 } 632 p_rx_cid->b_cid_allocated = true; 633 634 rc = qed_sp_eth_rxq_start_ramrod(p_hwfn, 635 opaque_fid, 636 p_rx_cid->cid, 637 params, 638 abs_stats_id, 639 bd_max_bytes, 640 bd_chain_phys_addr, 641 cqe_pbl_addr, 642 cqe_pbl_size); 643 644 if (rc != 0) 645 qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 646 647 return rc; 648 } 649 650 int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 651 u16 rx_queue_id, 652 u8 num_rxqs, 653 u8 complete_cqe_flg, 654 u8 complete_event_flg, 655 enum spq_mode comp_mode, 656 struct qed_spq_comp_cb *p_comp_data) 657 { 658 struct rx_queue_update_ramrod_data *p_ramrod = NULL; 659 struct qed_spq_entry *p_ent = NULL; 660 struct qed_sp_init_data init_data; 661 struct qed_hw_cid_data *p_rx_cid; 662 u16 qid, abs_rx_q_id = 0; 663 int rc = -EINVAL; 664 u8 i; 665 666 memset(&init_data, 0, sizeof(init_data)); 667 init_data.comp_mode = comp_mode; 668 init_data.p_comp_data = p_comp_data; 669 670 for (i = 0; i < num_rxqs; i++) { 671 qid = rx_queue_id + i; 672 p_rx_cid = &p_hwfn->p_rx_cids[qid]; 673 674 /* Get SPQ entry */ 675 init_data.cid = p_rx_cid->cid; 676 init_data.opaque_fid = p_rx_cid->opaque_fid; 677 678 rc = qed_sp_init_request(p_hwfn, &p_ent, 679 ETH_RAMROD_RX_QUEUE_UPDATE, 680 PROTOCOLID_ETH, &init_data); 681 if (rc) 682 return rc; 683 684 p_ramrod = &p_ent->ramrod.rx_queue_update; 685 686 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); 687 qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id); 688 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 689 p_ramrod->complete_cqe_flg = complete_cqe_flg; 690 p_ramrod->complete_event_flg = complete_event_flg; 691 692 rc = qed_spq_post(p_hwfn, p_ent, NULL); 693 if (rc) 694 return rc; 695 } 696 697 return rc; 698 } 699 700 int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 701 u16 rx_queue_id, 702 bool eq_completion_only, bool cqe_completion) 703 { 704 struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id]; 705 struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 706 struct qed_spq_entry *p_ent = NULL; 707 struct qed_sp_init_data init_data; 708 u16 abs_rx_q_id = 0; 709 int rc = -EINVAL; 710 711 if (IS_VF(p_hwfn->cdev)) 712 return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion); 713 714 /* Get SPQ entry */ 715 memset(&init_data, 0, sizeof(init_data)); 716 init_data.cid = p_rx_cid->cid; 717 init_data.opaque_fid = p_rx_cid->opaque_fid; 718 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 719 720 rc = qed_sp_init_request(p_hwfn, &p_ent, 721 ETH_RAMROD_RX_QUEUE_STOP, 722 PROTOCOLID_ETH, &init_data); 723 if (rc) 724 return rc; 725 726 p_ramrod = &p_ent->ramrod.rx_queue_stop; 727 728 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); 729 qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id); 730 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 731 732 /* Cleaning the queue requires the completion to arrive there. 733 * In addition, VFs require the answer to come as eqe to PF. 734 */ 735 p_ramrod->complete_cqe_flg = 736 (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) && 737 !eq_completion_only) || cqe_completion; 738 p_ramrod->complete_event_flg = 739 !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) || 740 eq_completion_only; 741 742 rc = qed_spq_post(p_hwfn, p_ent, NULL); 743 if (rc) 744 return rc; 745 746 return qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 747 } 748 749 int qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 750 u16 opaque_fid, 751 u32 cid, 752 struct qed_queue_start_common_params *p_params, 753 u8 stats_id, 754 dma_addr_t pbl_addr, 755 u16 pbl_size, 756 union qed_qm_pq_params *p_pq_params) 757 { 758 struct tx_queue_start_ramrod_data *p_ramrod = NULL; 759 struct qed_spq_entry *p_ent = NULL; 760 struct qed_sp_init_data init_data; 761 struct qed_hw_cid_data *p_tx_cid; 762 u16 pq_id, abs_tx_q_id = 0; 763 int rc = -EINVAL; 764 u8 abs_vport_id; 765 766 /* Store information for the stop */ 767 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 768 p_tx_cid->cid = cid; 769 p_tx_cid->opaque_fid = opaque_fid; 770 771 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 772 if (rc) 773 return rc; 774 775 rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_tx_q_id); 776 if (rc) 777 return rc; 778 779 /* Get SPQ entry */ 780 memset(&init_data, 0, sizeof(init_data)); 781 init_data.cid = cid; 782 init_data.opaque_fid = opaque_fid; 783 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 784 785 rc = qed_sp_init_request(p_hwfn, &p_ent, 786 ETH_RAMROD_TX_QUEUE_START, 787 PROTOCOLID_ETH, &init_data); 788 if (rc) 789 return rc; 790 791 p_ramrod = &p_ent->ramrod.tx_queue_start; 792 p_ramrod->vport_id = abs_vport_id; 793 794 p_ramrod->sb_id = cpu_to_le16(p_params->sb); 795 p_ramrod->sb_index = p_params->sb_idx; 796 p_ramrod->stats_counter_id = stats_id; 797 798 p_ramrod->queue_zone_id = cpu_to_le16(abs_tx_q_id); 799 p_ramrod->pbl_size = cpu_to_le16(pbl_size); 800 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 801 802 pq_id = qed_get_qm_pq(p_hwfn, 803 PROTOCOLID_ETH, 804 p_pq_params); 805 p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 806 807 return qed_spq_post(p_hwfn, p_ent, NULL); 808 } 809 810 static int 811 qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 812 u16 opaque_fid, 813 struct qed_queue_start_common_params *p_params, 814 dma_addr_t pbl_addr, 815 u16 pbl_size, void __iomem **pp_doorbell) 816 { 817 struct qed_hw_cid_data *p_tx_cid; 818 union qed_qm_pq_params pq_params; 819 u8 abs_stats_id = 0; 820 int rc; 821 822 if (IS_VF(p_hwfn->cdev)) { 823 return qed_vf_pf_txq_start(p_hwfn, 824 p_params->queue_id, 825 p_params->sb, 826 p_params->sb_idx, 827 pbl_addr, pbl_size, pp_doorbell); 828 } 829 830 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id); 831 if (rc) 832 return rc; 833 834 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 835 memset(p_tx_cid, 0, sizeof(*p_tx_cid)); 836 memset(&pq_params, 0, sizeof(pq_params)); 837 838 /* Allocate a CID for the queue */ 839 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 840 &p_tx_cid->cid); 841 if (rc) { 842 DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 843 return rc; 844 } 845 p_tx_cid->b_cid_allocated = true; 846 847 DP_VERBOSE(p_hwfn, QED_MSG_SP, 848 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 849 opaque_fid, p_tx_cid->cid, 850 p_params->queue_id, p_params->vport_id, p_params->sb); 851 852 rc = qed_sp_eth_txq_start_ramrod(p_hwfn, 853 opaque_fid, 854 p_tx_cid->cid, 855 p_params, 856 abs_stats_id, 857 pbl_addr, 858 pbl_size, 859 &pq_params); 860 861 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + 862 qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY); 863 864 if (rc) 865 qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 866 867 return rc; 868 } 869 870 int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id) 871 { 872 struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id]; 873 struct qed_spq_entry *p_ent = NULL; 874 struct qed_sp_init_data init_data; 875 int rc = -EINVAL; 876 877 if (IS_VF(p_hwfn->cdev)) 878 return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id); 879 880 /* Get SPQ entry */ 881 memset(&init_data, 0, sizeof(init_data)); 882 init_data.cid = p_tx_cid->cid; 883 init_data.opaque_fid = p_tx_cid->opaque_fid; 884 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 885 886 rc = qed_sp_init_request(p_hwfn, &p_ent, 887 ETH_RAMROD_TX_QUEUE_STOP, 888 PROTOCOLID_ETH, &init_data); 889 if (rc) 890 return rc; 891 892 rc = qed_spq_post(p_hwfn, p_ent, NULL); 893 if (rc) 894 return rc; 895 896 return qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 897 } 898 899 static enum eth_filter_action 900 qed_filter_action(enum qed_filter_opcode opcode) 901 { 902 enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 903 904 switch (opcode) { 905 case QED_FILTER_ADD: 906 action = ETH_FILTER_ACTION_ADD; 907 break; 908 case QED_FILTER_REMOVE: 909 action = ETH_FILTER_ACTION_REMOVE; 910 break; 911 case QED_FILTER_FLUSH: 912 action = ETH_FILTER_ACTION_REMOVE_ALL; 913 break; 914 default: 915 action = MAX_ETH_FILTER_ACTION; 916 } 917 918 return action; 919 } 920 921 static void qed_set_fw_mac_addr(__le16 *fw_msb, 922 __le16 *fw_mid, 923 __le16 *fw_lsb, 924 u8 *mac) 925 { 926 ((u8 *)fw_msb)[0] = mac[1]; 927 ((u8 *)fw_msb)[1] = mac[0]; 928 ((u8 *)fw_mid)[0] = mac[3]; 929 ((u8 *)fw_mid)[1] = mac[2]; 930 ((u8 *)fw_lsb)[0] = mac[5]; 931 ((u8 *)fw_lsb)[1] = mac[4]; 932 } 933 934 static int 935 qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 936 u16 opaque_fid, 937 struct qed_filter_ucast *p_filter_cmd, 938 struct vport_filter_update_ramrod_data **pp_ramrod, 939 struct qed_spq_entry **pp_ent, 940 enum spq_mode comp_mode, 941 struct qed_spq_comp_cb *p_comp_data) 942 { 943 u8 vport_to_add_to = 0, vport_to_remove_from = 0; 944 struct vport_filter_update_ramrod_data *p_ramrod; 945 struct eth_filter_cmd *p_first_filter; 946 struct eth_filter_cmd *p_second_filter; 947 struct qed_sp_init_data init_data; 948 enum eth_filter_action action; 949 int rc; 950 951 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 952 &vport_to_remove_from); 953 if (rc) 954 return rc; 955 956 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 957 &vport_to_add_to); 958 if (rc) 959 return rc; 960 961 /* Get SPQ entry */ 962 memset(&init_data, 0, sizeof(init_data)); 963 init_data.cid = qed_spq_get_cid(p_hwfn); 964 init_data.opaque_fid = opaque_fid; 965 init_data.comp_mode = comp_mode; 966 init_data.p_comp_data = p_comp_data; 967 968 rc = qed_sp_init_request(p_hwfn, pp_ent, 969 ETH_RAMROD_FILTERS_UPDATE, 970 PROTOCOLID_ETH, &init_data); 971 if (rc) 972 return rc; 973 974 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 975 p_ramrod = *pp_ramrod; 976 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 977 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 978 979 switch (p_filter_cmd->opcode) { 980 case QED_FILTER_REPLACE: 981 case QED_FILTER_MOVE: 982 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 983 default: 984 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 985 } 986 987 p_first_filter = &p_ramrod->filter_cmds[0]; 988 p_second_filter = &p_ramrod->filter_cmds[1]; 989 990 switch (p_filter_cmd->type) { 991 case QED_FILTER_MAC: 992 p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 993 case QED_FILTER_VLAN: 994 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 995 case QED_FILTER_MAC_VLAN: 996 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 997 case QED_FILTER_INNER_MAC: 998 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 999 case QED_FILTER_INNER_VLAN: 1000 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 1001 case QED_FILTER_INNER_PAIR: 1002 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 1003 case QED_FILTER_INNER_MAC_VNI_PAIR: 1004 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 1005 break; 1006 case QED_FILTER_MAC_VNI_PAIR: 1007 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 1008 case QED_FILTER_VNI: 1009 p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 1010 } 1011 1012 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 1013 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1014 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 1015 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 1016 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1017 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 1018 qed_set_fw_mac_addr(&p_first_filter->mac_msb, 1019 &p_first_filter->mac_mid, 1020 &p_first_filter->mac_lsb, 1021 (u8 *)p_filter_cmd->mac); 1022 } 1023 1024 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 1025 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1026 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 1027 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 1028 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 1029 1030 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1031 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 1032 (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 1033 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 1034 1035 if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 1036 p_second_filter->type = p_first_filter->type; 1037 p_second_filter->mac_msb = p_first_filter->mac_msb; 1038 p_second_filter->mac_mid = p_first_filter->mac_mid; 1039 p_second_filter->mac_lsb = p_first_filter->mac_lsb; 1040 p_second_filter->vlan_id = p_first_filter->vlan_id; 1041 p_second_filter->vni = p_first_filter->vni; 1042 1043 p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 1044 1045 p_first_filter->vport_id = vport_to_remove_from; 1046 1047 p_second_filter->action = ETH_FILTER_ACTION_ADD; 1048 p_second_filter->vport_id = vport_to_add_to; 1049 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 1050 p_first_filter->vport_id = vport_to_add_to; 1051 memcpy(p_second_filter, p_first_filter, 1052 sizeof(*p_second_filter)); 1053 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 1054 p_second_filter->action = ETH_FILTER_ACTION_ADD; 1055 } else { 1056 action = qed_filter_action(p_filter_cmd->opcode); 1057 1058 if (action == MAX_ETH_FILTER_ACTION) { 1059 DP_NOTICE(p_hwfn, 1060 "%d is not supported yet\n", 1061 p_filter_cmd->opcode); 1062 return -EINVAL; 1063 } 1064 1065 p_first_filter->action = action; 1066 p_first_filter->vport_id = (p_filter_cmd->opcode == 1067 QED_FILTER_REMOVE) ? 1068 vport_to_remove_from : 1069 vport_to_add_to; 1070 } 1071 1072 return 0; 1073 } 1074 1075 int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 1076 u16 opaque_fid, 1077 struct qed_filter_ucast *p_filter_cmd, 1078 enum spq_mode comp_mode, 1079 struct qed_spq_comp_cb *p_comp_data) 1080 { 1081 struct vport_filter_update_ramrod_data *p_ramrod = NULL; 1082 struct qed_spq_entry *p_ent = NULL; 1083 struct eth_filter_cmd_header *p_header; 1084 int rc; 1085 1086 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1087 &p_ramrod, &p_ent, 1088 comp_mode, p_comp_data); 1089 if (rc != 0) { 1090 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1091 return rc; 1092 } 1093 p_header = &p_ramrod->filter_cmd_hdr; 1094 p_header->assert_on_error = p_filter_cmd->assert_on_error; 1095 1096 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1097 if (rc != 0) { 1098 DP_ERR(p_hwfn, 1099 "Unicast filter ADD command failed %d\n", 1100 rc); 1101 return rc; 1102 } 1103 1104 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1105 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1106 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1107 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1108 "REMOVE" : 1109 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1110 "MOVE" : "REPLACE")), 1111 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1112 ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1113 "VLAN" : "MAC & VLAN"), 1114 p_ramrod->filter_cmd_hdr.cmd_cnt, 1115 p_filter_cmd->is_rx_filter, 1116 p_filter_cmd->is_tx_filter); 1117 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1118 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1119 p_filter_cmd->vport_to_add_to, 1120 p_filter_cmd->vport_to_remove_from, 1121 p_filter_cmd->mac[0], 1122 p_filter_cmd->mac[1], 1123 p_filter_cmd->mac[2], 1124 p_filter_cmd->mac[3], 1125 p_filter_cmd->mac[4], 1126 p_filter_cmd->mac[5], 1127 p_filter_cmd->vlan); 1128 1129 return 0; 1130 } 1131 1132 /******************************************************************************* 1133 * Description: 1134 * Calculates crc 32 on a buffer 1135 * Note: crc32_length MUST be aligned to 8 1136 * Return: 1137 ******************************************************************************/ 1138 static u32 qed_calc_crc32c(u8 *crc32_packet, 1139 u32 crc32_length, 1140 u32 crc32_seed, 1141 u8 complement) 1142 { 1143 u32 byte = 0; 1144 u32 bit = 0; 1145 u8 msb = 0; 1146 u8 current_byte = 0; 1147 u32 crc32_result = crc32_seed; 1148 1149 if ((!crc32_packet) || 1150 (crc32_length == 0) || 1151 ((crc32_length % 8) != 0)) 1152 return crc32_result; 1153 for (byte = 0; byte < crc32_length; byte++) { 1154 current_byte = crc32_packet[byte]; 1155 for (bit = 0; bit < 8; bit++) { 1156 msb = (u8)(crc32_result >> 31); 1157 crc32_result = crc32_result << 1; 1158 if (msb != (0x1 & (current_byte >> bit))) { 1159 crc32_result = crc32_result ^ CRC32_POLY; 1160 crc32_result |= 1; /*crc32_result[0] = 1;*/ 1161 } 1162 } 1163 } 1164 return crc32_result; 1165 } 1166 1167 static inline u32 qed_crc32c_le(u32 seed, 1168 u8 *mac, 1169 u32 len) 1170 { 1171 u32 packet_buf[2] = { 0 }; 1172 1173 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1174 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1175 } 1176 1177 u8 qed_mcast_bin_from_mac(u8 *mac) 1178 { 1179 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1180 mac, ETH_ALEN); 1181 1182 return crc & 0xff; 1183 } 1184 1185 static int 1186 qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1187 u16 opaque_fid, 1188 struct qed_filter_mcast *p_filter_cmd, 1189 enum spq_mode comp_mode, 1190 struct qed_spq_comp_cb *p_comp_data) 1191 { 1192 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1193 struct vport_update_ramrod_data *p_ramrod = NULL; 1194 struct qed_spq_entry *p_ent = NULL; 1195 struct qed_sp_init_data init_data; 1196 u8 abs_vport_id = 0; 1197 int rc, i; 1198 1199 if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1200 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1201 &abs_vport_id); 1202 if (rc) 1203 return rc; 1204 } else { 1205 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1206 &abs_vport_id); 1207 if (rc) 1208 return rc; 1209 } 1210 1211 /* Get SPQ entry */ 1212 memset(&init_data, 0, sizeof(init_data)); 1213 init_data.cid = qed_spq_get_cid(p_hwfn); 1214 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1215 init_data.comp_mode = comp_mode; 1216 init_data.p_comp_data = p_comp_data; 1217 1218 rc = qed_sp_init_request(p_hwfn, &p_ent, 1219 ETH_RAMROD_VPORT_UPDATE, 1220 PROTOCOLID_ETH, &init_data); 1221 if (rc) { 1222 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1223 return rc; 1224 } 1225 1226 p_ramrod = &p_ent->ramrod.vport_update; 1227 p_ramrod->common.update_approx_mcast_flg = 1; 1228 1229 /* explicitly clear out the entire vector */ 1230 memset(&p_ramrod->approx_mcast.bins, 0, 1231 sizeof(p_ramrod->approx_mcast.bins)); 1232 memset(bins, 0, sizeof(unsigned long) * 1233 ETH_MULTICAST_MAC_BINS_IN_REGS); 1234 /* filter ADD op is explicit set op and it removes 1235 * any existing filters for the vport 1236 */ 1237 if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1238 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 1239 u32 bit; 1240 1241 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 1242 __set_bit(bit, bins); 1243 } 1244 1245 /* Convert to correct endianity */ 1246 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 1247 u32 *p_bins = (u32 *)bins; 1248 struct vport_update_ramrod_mcast *approx_mcast; 1249 1250 approx_mcast = &p_ramrod->approx_mcast; 1251 approx_mcast->bins[i] = cpu_to_le32(p_bins[i]); 1252 } 1253 } 1254 1255 p_ramrod->common.vport_id = abs_vport_id; 1256 1257 return qed_spq_post(p_hwfn, p_ent, NULL); 1258 } 1259 1260 static int qed_filter_mcast_cmd(struct qed_dev *cdev, 1261 struct qed_filter_mcast *p_filter_cmd, 1262 enum spq_mode comp_mode, 1263 struct qed_spq_comp_cb *p_comp_data) 1264 { 1265 int rc = 0; 1266 int i; 1267 1268 /* only ADD and REMOVE operations are supported for multi-cast */ 1269 if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1270 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1271 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1272 return -EINVAL; 1273 1274 for_each_hwfn(cdev, i) { 1275 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1276 1277 u16 opaque_fid; 1278 1279 if (IS_VF(cdev)) { 1280 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); 1281 continue; 1282 } 1283 1284 opaque_fid = p_hwfn->hw_info.opaque_fid; 1285 1286 rc = qed_sp_eth_filter_mcast(p_hwfn, 1287 opaque_fid, 1288 p_filter_cmd, 1289 comp_mode, 1290 p_comp_data); 1291 } 1292 return rc; 1293 } 1294 1295 static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1296 struct qed_filter_ucast *p_filter_cmd, 1297 enum spq_mode comp_mode, 1298 struct qed_spq_comp_cb *p_comp_data) 1299 { 1300 int rc = 0; 1301 int i; 1302 1303 for_each_hwfn(cdev, i) { 1304 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1305 u16 opaque_fid; 1306 1307 if (IS_VF(cdev)) { 1308 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); 1309 continue; 1310 } 1311 1312 opaque_fid = p_hwfn->hw_info.opaque_fid; 1313 1314 rc = qed_sp_eth_filter_ucast(p_hwfn, 1315 opaque_fid, 1316 p_filter_cmd, 1317 comp_mode, 1318 p_comp_data); 1319 if (rc != 0) 1320 break; 1321 } 1322 1323 return rc; 1324 } 1325 1326 /* Statistics related code */ 1327 static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 1328 u32 *p_addr, 1329 u32 *p_len, u16 statistics_bin) 1330 { 1331 if (IS_PF(p_hwfn->cdev)) { 1332 *p_addr = BAR0_MAP_REG_PSDM_RAM + 1333 PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 1334 *p_len = sizeof(struct eth_pstorm_per_queue_stat); 1335 } else { 1336 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1337 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1338 1339 *p_addr = p_resp->pfdev_info.stats_info.pstats.address; 1340 *p_len = p_resp->pfdev_info.stats_info.pstats.len; 1341 } 1342 } 1343 1344 static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 1345 struct qed_ptt *p_ptt, 1346 struct qed_eth_stats *p_stats, 1347 u16 statistics_bin) 1348 { 1349 struct eth_pstorm_per_queue_stat pstats; 1350 u32 pstats_addr = 0, pstats_len = 0; 1351 1352 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 1353 statistics_bin); 1354 1355 memset(&pstats, 0, sizeof(pstats)); 1356 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); 1357 1358 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes); 1359 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes); 1360 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes); 1361 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts); 1362 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts); 1363 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts); 1364 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts); 1365 } 1366 1367 static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 1368 struct qed_ptt *p_ptt, 1369 struct qed_eth_stats *p_stats, 1370 u16 statistics_bin) 1371 { 1372 struct tstorm_per_port_stat tstats; 1373 u32 tstats_addr, tstats_len; 1374 1375 if (IS_PF(p_hwfn->cdev)) { 1376 tstats_addr = BAR0_MAP_REG_TSDM_RAM + 1377 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 1378 tstats_len = sizeof(struct tstorm_per_port_stat); 1379 } else { 1380 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1381 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1382 1383 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; 1384 tstats_len = p_resp->pfdev_info.stats_info.tstats.len; 1385 } 1386 1387 memset(&tstats, 0, sizeof(tstats)); 1388 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); 1389 1390 p_stats->mftag_filter_discards += 1391 HILO_64_REGPAIR(tstats.mftag_filter_discard); 1392 p_stats->mac_filter_discards += 1393 HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 1394 } 1395 1396 static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 1397 u32 *p_addr, 1398 u32 *p_len, u16 statistics_bin) 1399 { 1400 if (IS_PF(p_hwfn->cdev)) { 1401 *p_addr = BAR0_MAP_REG_USDM_RAM + 1402 USTORM_QUEUE_STAT_OFFSET(statistics_bin); 1403 *p_len = sizeof(struct eth_ustorm_per_queue_stat); 1404 } else { 1405 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1406 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1407 1408 *p_addr = p_resp->pfdev_info.stats_info.ustats.address; 1409 *p_len = p_resp->pfdev_info.stats_info.ustats.len; 1410 } 1411 } 1412 1413 static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 1414 struct qed_ptt *p_ptt, 1415 struct qed_eth_stats *p_stats, 1416 u16 statistics_bin) 1417 { 1418 struct eth_ustorm_per_queue_stat ustats; 1419 u32 ustats_addr = 0, ustats_len = 0; 1420 1421 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 1422 statistics_bin); 1423 1424 memset(&ustats, 0, sizeof(ustats)); 1425 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); 1426 1427 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 1428 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 1429 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 1430 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 1431 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 1432 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 1433 } 1434 1435 static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 1436 u32 *p_addr, 1437 u32 *p_len, u16 statistics_bin) 1438 { 1439 if (IS_PF(p_hwfn->cdev)) { 1440 *p_addr = BAR0_MAP_REG_MSDM_RAM + 1441 MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 1442 *p_len = sizeof(struct eth_mstorm_per_queue_stat); 1443 } else { 1444 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1445 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1446 1447 *p_addr = p_resp->pfdev_info.stats_info.mstats.address; 1448 *p_len = p_resp->pfdev_info.stats_info.mstats.len; 1449 } 1450 } 1451 1452 static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 1453 struct qed_ptt *p_ptt, 1454 struct qed_eth_stats *p_stats, 1455 u16 statistics_bin) 1456 { 1457 struct eth_mstorm_per_queue_stat mstats; 1458 u32 mstats_addr = 0, mstats_len = 0; 1459 1460 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 1461 statistics_bin); 1462 1463 memset(&mstats, 0, sizeof(mstats)); 1464 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); 1465 1466 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard); 1467 p_stats->packet_too_big_discard += 1468 HILO_64_REGPAIR(mstats.packet_too_big_discard); 1469 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); 1470 p_stats->tpa_coalesced_pkts += 1471 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 1472 p_stats->tpa_coalesced_events += 1473 HILO_64_REGPAIR(mstats.tpa_coalesced_events); 1474 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num); 1475 p_stats->tpa_coalesced_bytes += 1476 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 1477 } 1478 1479 static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 1480 struct qed_ptt *p_ptt, 1481 struct qed_eth_stats *p_stats) 1482 { 1483 struct port_stats port_stats; 1484 int j; 1485 1486 memset(&port_stats, 0, sizeof(port_stats)); 1487 1488 qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 1489 p_hwfn->mcp_info->port_addr + 1490 offsetof(struct public_port, stats), 1491 sizeof(port_stats)); 1492 1493 p_stats->rx_64_byte_packets += port_stats.eth.r64; 1494 p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127; 1495 p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255; 1496 p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511; 1497 p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023; 1498 p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; 1499 p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522; 1500 p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047; 1501 p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095; 1502 p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216; 1503 p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383; 1504 p_stats->rx_crc_errors += port_stats.eth.rfcs; 1505 p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf; 1506 p_stats->rx_pause_frames += port_stats.eth.rxpf; 1507 p_stats->rx_pfc_frames += port_stats.eth.rxpp; 1508 p_stats->rx_align_errors += port_stats.eth.raln; 1509 p_stats->rx_carrier_errors += port_stats.eth.rfcr; 1510 p_stats->rx_oversize_packets += port_stats.eth.rovr; 1511 p_stats->rx_jabbers += port_stats.eth.rjbr; 1512 p_stats->rx_undersize_packets += port_stats.eth.rund; 1513 p_stats->rx_fragments += port_stats.eth.rfrg; 1514 p_stats->tx_64_byte_packets += port_stats.eth.t64; 1515 p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127; 1516 p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255; 1517 p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511; 1518 p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023; 1519 p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; 1520 p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047; 1521 p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095; 1522 p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216; 1523 p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383; 1524 p_stats->tx_pause_frames += port_stats.eth.txpf; 1525 p_stats->tx_pfc_frames += port_stats.eth.txpp; 1526 p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec; 1527 p_stats->tx_total_collisions += port_stats.eth.tncl; 1528 p_stats->rx_mac_bytes += port_stats.eth.rbyte; 1529 p_stats->rx_mac_uc_packets += port_stats.eth.rxuca; 1530 p_stats->rx_mac_mc_packets += port_stats.eth.rxmca; 1531 p_stats->rx_mac_bc_packets += port_stats.eth.rxbca; 1532 p_stats->rx_mac_frames_ok += port_stats.eth.rxpok; 1533 p_stats->tx_mac_bytes += port_stats.eth.tbyte; 1534 p_stats->tx_mac_uc_packets += port_stats.eth.txuca; 1535 p_stats->tx_mac_mc_packets += port_stats.eth.txmca; 1536 p_stats->tx_mac_bc_packets += port_stats.eth.txbca; 1537 p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf; 1538 for (j = 0; j < 8; j++) { 1539 p_stats->brb_truncates += port_stats.brb.brb_truncate[j]; 1540 p_stats->brb_discards += port_stats.brb.brb_discard[j]; 1541 } 1542 } 1543 1544 static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 1545 struct qed_ptt *p_ptt, 1546 struct qed_eth_stats *stats, 1547 u16 statistics_bin, bool b_get_port_stats) 1548 { 1549 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 1550 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 1551 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 1552 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 1553 1554 if (b_get_port_stats && p_hwfn->mcp_info) 1555 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 1556 } 1557 1558 static void _qed_get_vport_stats(struct qed_dev *cdev, 1559 struct qed_eth_stats *stats) 1560 { 1561 u8 fw_vport = 0; 1562 int i; 1563 1564 memset(stats, 0, sizeof(*stats)); 1565 1566 for_each_hwfn(cdev, i) { 1567 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1568 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1569 : NULL; 1570 1571 if (IS_PF(cdev)) { 1572 /* The main vport index is relative first */ 1573 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 1574 DP_ERR(p_hwfn, "No vport available!\n"); 1575 goto out; 1576 } 1577 } 1578 1579 if (IS_PF(cdev) && !p_ptt) { 1580 DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 1581 continue; 1582 } 1583 1584 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, 1585 IS_PF(cdev) ? true : false); 1586 1587 out: 1588 if (IS_PF(cdev) && p_ptt) 1589 qed_ptt_release(p_hwfn, p_ptt); 1590 } 1591 } 1592 1593 void qed_get_vport_stats(struct qed_dev *cdev, 1594 struct qed_eth_stats *stats) 1595 { 1596 u32 i; 1597 1598 if (!cdev) { 1599 memset(stats, 0, sizeof(*stats)); 1600 return; 1601 } 1602 1603 _qed_get_vport_stats(cdev, stats); 1604 1605 if (!cdev->reset_stats) 1606 return; 1607 1608 /* Reduce the statistics baseline */ 1609 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 1610 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 1611 } 1612 1613 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 1614 void qed_reset_vport_stats(struct qed_dev *cdev) 1615 { 1616 int i; 1617 1618 for_each_hwfn(cdev, i) { 1619 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1620 struct eth_mstorm_per_queue_stat mstats; 1621 struct eth_ustorm_per_queue_stat ustats; 1622 struct eth_pstorm_per_queue_stat pstats; 1623 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1624 : NULL; 1625 u32 addr = 0, len = 0; 1626 1627 if (IS_PF(cdev) && !p_ptt) { 1628 DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 1629 continue; 1630 } 1631 1632 memset(&mstats, 0, sizeof(mstats)); 1633 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 1634 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 1635 1636 memset(&ustats, 0, sizeof(ustats)); 1637 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 1638 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 1639 1640 memset(&pstats, 0, sizeof(pstats)); 1641 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 1642 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 1643 1644 if (IS_PF(cdev)) 1645 qed_ptt_release(p_hwfn, p_ptt); 1646 } 1647 1648 /* PORT statistics are not necessarily reset, so we need to 1649 * read and create a baseline for future statistics. 1650 */ 1651 if (!cdev->reset_stats) 1652 DP_INFO(cdev, "Reset stats not allocated\n"); 1653 else 1654 _qed_get_vport_stats(cdev, cdev->reset_stats); 1655 } 1656 1657 static int qed_fill_eth_dev_info(struct qed_dev *cdev, 1658 struct qed_dev_eth_info *info) 1659 { 1660 int i; 1661 1662 memset(info, 0, sizeof(*info)); 1663 1664 info->num_tc = 1; 1665 1666 if (IS_PF(cdev)) { 1667 int max_vf_vlan_filters = 0; 1668 1669 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 1670 for_each_hwfn(cdev, i) 1671 info->num_queues += 1672 FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 1673 if (cdev->int_params.fp_msix_cnt) 1674 info->num_queues = 1675 min_t(u8, info->num_queues, 1676 cdev->int_params.fp_msix_cnt); 1677 } else { 1678 info->num_queues = cdev->num_hwfns; 1679 } 1680 1681 if (IS_QED_SRIOV(cdev)) 1682 max_vf_vlan_filters = cdev->p_iov_info->total_vfs * 1683 QED_ETH_VF_NUM_VLAN_FILTERS; 1684 info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN) - 1685 max_vf_vlan_filters; 1686 1687 ether_addr_copy(info->port_mac, 1688 cdev->hwfns[0].hw_info.hw_mac_addr); 1689 } else { 1690 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues); 1691 if (cdev->num_hwfns > 1) { 1692 u8 queues = 0; 1693 1694 qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues); 1695 info->num_queues += queues; 1696 } 1697 1698 qed_vf_get_num_vlan_filters(&cdev->hwfns[0], 1699 &info->num_vlan_filters); 1700 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); 1701 } 1702 1703 qed_fill_dev_info(cdev, &info->common); 1704 1705 if (IS_VF(cdev)) 1706 memset(info->common.hw_mac, 0, ETH_ALEN); 1707 1708 return 0; 1709 } 1710 1711 static void qed_register_eth_ops(struct qed_dev *cdev, 1712 struct qed_eth_cb_ops *ops, void *cookie) 1713 { 1714 cdev->protocol_ops.eth = ops; 1715 cdev->ops_cookie = cookie; 1716 1717 /* For VF, we start bulletin reading */ 1718 if (IS_VF(cdev)) 1719 qed_vf_start_iov_wq(cdev); 1720 } 1721 1722 static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) 1723 { 1724 if (IS_PF(cdev)) 1725 return true; 1726 1727 return qed_vf_check_mac(&cdev->hwfns[0], mac); 1728 } 1729 1730 static int qed_start_vport(struct qed_dev *cdev, 1731 struct qed_start_vport_params *params) 1732 { 1733 int rc, i; 1734 1735 for_each_hwfn(cdev, i) { 1736 struct qed_sp_vport_start_params start = { 0 }; 1737 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1738 1739 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : 1740 QED_TPA_MODE_NONE; 1741 start.remove_inner_vlan = params->remove_inner_vlan; 1742 start.only_untagged = true; /* untagged only */ 1743 start.drop_ttl0 = params->drop_ttl0; 1744 start.opaque_fid = p_hwfn->hw_info.opaque_fid; 1745 start.concrete_fid = p_hwfn->hw_info.concrete_fid; 1746 start.vport_id = params->vport_id; 1747 start.max_buffers_per_cqe = 16; 1748 start.mtu = params->mtu; 1749 1750 rc = qed_sp_vport_start(p_hwfn, &start); 1751 if (rc) { 1752 DP_ERR(cdev, "Failed to start VPORT\n"); 1753 return rc; 1754 } 1755 1756 qed_hw_start_fastpath(p_hwfn); 1757 1758 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1759 "Started V-PORT %d with MTU %d\n", 1760 start.vport_id, start.mtu); 1761 } 1762 1763 if (params->clear_stats) 1764 qed_reset_vport_stats(cdev); 1765 1766 return 0; 1767 } 1768 1769 static int qed_stop_vport(struct qed_dev *cdev, 1770 u8 vport_id) 1771 { 1772 int rc, i; 1773 1774 for_each_hwfn(cdev, i) { 1775 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1776 1777 rc = qed_sp_vport_stop(p_hwfn, 1778 p_hwfn->hw_info.opaque_fid, 1779 vport_id); 1780 1781 if (rc) { 1782 DP_ERR(cdev, "Failed to stop VPORT\n"); 1783 return rc; 1784 } 1785 } 1786 return 0; 1787 } 1788 1789 static int qed_update_vport(struct qed_dev *cdev, 1790 struct qed_update_vport_params *params) 1791 { 1792 struct qed_sp_vport_update_params sp_params; 1793 struct qed_rss_params sp_rss_params; 1794 int rc, i; 1795 1796 if (!cdev) 1797 return -ENODEV; 1798 1799 memset(&sp_params, 0, sizeof(sp_params)); 1800 memset(&sp_rss_params, 0, sizeof(sp_rss_params)); 1801 1802 /* Translate protocol params into sp params */ 1803 sp_params.vport_id = params->vport_id; 1804 sp_params.update_vport_active_rx_flg = 1805 params->update_vport_active_flg; 1806 sp_params.update_vport_active_tx_flg = 1807 params->update_vport_active_flg; 1808 sp_params.vport_active_rx_flg = params->vport_active_flg; 1809 sp_params.vport_active_tx_flg = params->vport_active_flg; 1810 sp_params.update_tx_switching_flg = params->update_tx_switching_flg; 1811 sp_params.tx_switching_flg = params->tx_switching_flg; 1812 sp_params.accept_any_vlan = params->accept_any_vlan; 1813 sp_params.update_accept_any_vlan_flg = 1814 params->update_accept_any_vlan_flg; 1815 1816 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns. 1817 * We need to re-fix the rss values per engine for CMT. 1818 */ 1819 if (cdev->num_hwfns > 1 && params->update_rss_flg) { 1820 struct qed_update_vport_rss_params *rss = 1821 ¶ms->rss_params; 1822 int k, max = 0; 1823 1824 /* Find largest entry, since it's possible RSS needs to 1825 * be disabled [in case only 1 queue per-hwfn] 1826 */ 1827 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1828 max = (max > rss->rss_ind_table[k]) ? 1829 max : rss->rss_ind_table[k]; 1830 1831 /* Either fix RSS values or disable RSS */ 1832 if (cdev->num_hwfns < max + 1) { 1833 int divisor = (max + cdev->num_hwfns - 1) / 1834 cdev->num_hwfns; 1835 1836 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1837 "CMT - fixing RSS values (modulo %02x)\n", 1838 divisor); 1839 1840 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1841 rss->rss_ind_table[k] = 1842 rss->rss_ind_table[k] % divisor; 1843 } else { 1844 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1845 "CMT - 1 queue per-hwfn; Disabling RSS\n"); 1846 params->update_rss_flg = 0; 1847 } 1848 } 1849 1850 /* Now, update the RSS configuration for actual configuration */ 1851 if (params->update_rss_flg) { 1852 sp_rss_params.update_rss_config = 1; 1853 sp_rss_params.rss_enable = 1; 1854 sp_rss_params.update_rss_capabilities = 1; 1855 sp_rss_params.update_rss_ind_table = 1; 1856 sp_rss_params.update_rss_key = 1; 1857 sp_rss_params.rss_caps = params->rss_params.rss_caps; 1858 sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */ 1859 memcpy(sp_rss_params.rss_ind_table, 1860 params->rss_params.rss_ind_table, 1861 QED_RSS_IND_TABLE_SIZE * sizeof(u16)); 1862 memcpy(sp_rss_params.rss_key, params->rss_params.rss_key, 1863 QED_RSS_KEY_SIZE * sizeof(u32)); 1864 } 1865 sp_params.rss_params = &sp_rss_params; 1866 1867 for_each_hwfn(cdev, i) { 1868 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1869 1870 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1871 rc = qed_sp_vport_update(p_hwfn, &sp_params, 1872 QED_SPQ_MODE_EBLOCK, 1873 NULL); 1874 if (rc) { 1875 DP_ERR(cdev, "Failed to update VPORT\n"); 1876 return rc; 1877 } 1878 1879 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1880 "Updated V-PORT %d: active_flag %d [update %d]\n", 1881 params->vport_id, params->vport_active_flg, 1882 params->update_vport_active_flg); 1883 } 1884 1885 return 0; 1886 } 1887 1888 static int qed_start_rxq(struct qed_dev *cdev, 1889 struct qed_queue_start_common_params *params, 1890 u16 bd_max_bytes, 1891 dma_addr_t bd_chain_phys_addr, 1892 dma_addr_t cqe_pbl_addr, 1893 u16 cqe_pbl_size, 1894 void __iomem **pp_prod) 1895 { 1896 int rc, hwfn_index; 1897 struct qed_hwfn *p_hwfn; 1898 1899 hwfn_index = params->rss_id % cdev->num_hwfns; 1900 p_hwfn = &cdev->hwfns[hwfn_index]; 1901 1902 /* Fix queue ID in 100g mode */ 1903 params->queue_id /= cdev->num_hwfns; 1904 1905 rc = qed_sp_eth_rx_queue_start(p_hwfn, 1906 p_hwfn->hw_info.opaque_fid, 1907 params, 1908 bd_max_bytes, 1909 bd_chain_phys_addr, 1910 cqe_pbl_addr, 1911 cqe_pbl_size, 1912 pp_prod); 1913 1914 if (rc) { 1915 DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id); 1916 return rc; 1917 } 1918 1919 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1920 "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1921 params->queue_id, params->rss_id, params->vport_id, 1922 params->sb); 1923 1924 return 0; 1925 } 1926 1927 static int qed_stop_rxq(struct qed_dev *cdev, 1928 struct qed_stop_rxq_params *params) 1929 { 1930 int rc, hwfn_index; 1931 struct qed_hwfn *p_hwfn; 1932 1933 hwfn_index = params->rss_id % cdev->num_hwfns; 1934 p_hwfn = &cdev->hwfns[hwfn_index]; 1935 1936 rc = qed_sp_eth_rx_queue_stop(p_hwfn, 1937 params->rx_queue_id / cdev->num_hwfns, 1938 params->eq_completion_only, 1939 false); 1940 if (rc) { 1941 DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id); 1942 return rc; 1943 } 1944 1945 return 0; 1946 } 1947 1948 static int qed_start_txq(struct qed_dev *cdev, 1949 struct qed_queue_start_common_params *p_params, 1950 dma_addr_t pbl_addr, 1951 u16 pbl_size, 1952 void __iomem **pp_doorbell) 1953 { 1954 struct qed_hwfn *p_hwfn; 1955 int rc, hwfn_index; 1956 1957 hwfn_index = p_params->rss_id % cdev->num_hwfns; 1958 p_hwfn = &cdev->hwfns[hwfn_index]; 1959 1960 /* Fix queue ID in 100g mode */ 1961 p_params->queue_id /= cdev->num_hwfns; 1962 1963 rc = qed_sp_eth_tx_queue_start(p_hwfn, 1964 p_hwfn->hw_info.opaque_fid, 1965 p_params, 1966 pbl_addr, 1967 pbl_size, 1968 pp_doorbell); 1969 1970 if (rc) { 1971 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 1972 return rc; 1973 } 1974 1975 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1976 "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1977 p_params->queue_id, p_params->rss_id, p_params->vport_id, 1978 p_params->sb); 1979 1980 return 0; 1981 } 1982 1983 #define QED_HW_STOP_RETRY_LIMIT (10) 1984 static int qed_fastpath_stop(struct qed_dev *cdev) 1985 { 1986 qed_hw_stop_fastpath(cdev); 1987 1988 return 0; 1989 } 1990 1991 static int qed_stop_txq(struct qed_dev *cdev, 1992 struct qed_stop_txq_params *params) 1993 { 1994 struct qed_hwfn *p_hwfn; 1995 int rc, hwfn_index; 1996 1997 hwfn_index = params->rss_id % cdev->num_hwfns; 1998 p_hwfn = &cdev->hwfns[hwfn_index]; 1999 2000 rc = qed_sp_eth_tx_queue_stop(p_hwfn, 2001 params->tx_queue_id / cdev->num_hwfns); 2002 if (rc) { 2003 DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id); 2004 return rc; 2005 } 2006 2007 return 0; 2008 } 2009 2010 static int qed_tunn_configure(struct qed_dev *cdev, 2011 struct qed_tunn_params *tunn_params) 2012 { 2013 struct qed_tunn_update_params tunn_info; 2014 int i, rc; 2015 2016 if (IS_VF(cdev)) 2017 return 0; 2018 2019 memset(&tunn_info, 0, sizeof(tunn_info)); 2020 if (tunn_params->update_vxlan_port == 1) { 2021 tunn_info.update_vxlan_udp_port = 1; 2022 tunn_info.vxlan_udp_port = tunn_params->vxlan_port; 2023 } 2024 2025 if (tunn_params->update_geneve_port == 1) { 2026 tunn_info.update_geneve_udp_port = 1; 2027 tunn_info.geneve_udp_port = tunn_params->geneve_port; 2028 } 2029 2030 for_each_hwfn(cdev, i) { 2031 struct qed_hwfn *hwfn = &cdev->hwfns[i]; 2032 2033 rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info, 2034 QED_SPQ_MODE_EBLOCK, NULL); 2035 2036 if (rc) 2037 return rc; 2038 } 2039 2040 return 0; 2041 } 2042 2043 static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 2044 enum qed_filter_rx_mode_type type) 2045 { 2046 struct qed_filter_accept_flags accept_flags; 2047 2048 memset(&accept_flags, 0, sizeof(accept_flags)); 2049 2050 accept_flags.update_rx_mode_config = 1; 2051 accept_flags.update_tx_mode_config = 1; 2052 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2053 QED_ACCEPT_MCAST_MATCHED | 2054 QED_ACCEPT_BCAST; 2055 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2056 QED_ACCEPT_MCAST_MATCHED | 2057 QED_ACCEPT_BCAST; 2058 2059 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) 2060 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 2061 QED_ACCEPT_MCAST_UNMATCHED; 2062 else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) 2063 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 2064 2065 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 2066 QED_SPQ_MODE_CB, NULL); 2067 } 2068 2069 static int qed_configure_filter_ucast(struct qed_dev *cdev, 2070 struct qed_filter_ucast_params *params) 2071 { 2072 struct qed_filter_ucast ucast; 2073 2074 if (!params->vlan_valid && !params->mac_valid) { 2075 DP_NOTICE( 2076 cdev, 2077 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 2078 return -EINVAL; 2079 } 2080 2081 memset(&ucast, 0, sizeof(ucast)); 2082 switch (params->type) { 2083 case QED_FILTER_XCAST_TYPE_ADD: 2084 ucast.opcode = QED_FILTER_ADD; 2085 break; 2086 case QED_FILTER_XCAST_TYPE_DEL: 2087 ucast.opcode = QED_FILTER_REMOVE; 2088 break; 2089 case QED_FILTER_XCAST_TYPE_REPLACE: 2090 ucast.opcode = QED_FILTER_REPLACE; 2091 break; 2092 default: 2093 DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 2094 params->type); 2095 } 2096 2097 if (params->vlan_valid && params->mac_valid) { 2098 ucast.type = QED_FILTER_MAC_VLAN; 2099 ether_addr_copy(ucast.mac, params->mac); 2100 ucast.vlan = params->vlan; 2101 } else if (params->mac_valid) { 2102 ucast.type = QED_FILTER_MAC; 2103 ether_addr_copy(ucast.mac, params->mac); 2104 } else { 2105 ucast.type = QED_FILTER_VLAN; 2106 ucast.vlan = params->vlan; 2107 } 2108 2109 ucast.is_rx_filter = true; 2110 ucast.is_tx_filter = true; 2111 2112 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 2113 } 2114 2115 static int qed_configure_filter_mcast(struct qed_dev *cdev, 2116 struct qed_filter_mcast_params *params) 2117 { 2118 struct qed_filter_mcast mcast; 2119 int i; 2120 2121 memset(&mcast, 0, sizeof(mcast)); 2122 switch (params->type) { 2123 case QED_FILTER_XCAST_TYPE_ADD: 2124 mcast.opcode = QED_FILTER_ADD; 2125 break; 2126 case QED_FILTER_XCAST_TYPE_DEL: 2127 mcast.opcode = QED_FILTER_REMOVE; 2128 break; 2129 default: 2130 DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 2131 params->type); 2132 } 2133 2134 mcast.num_mc_addrs = params->num; 2135 for (i = 0; i < mcast.num_mc_addrs; i++) 2136 ether_addr_copy(mcast.mac[i], params->mac[i]); 2137 2138 return qed_filter_mcast_cmd(cdev, &mcast, 2139 QED_SPQ_MODE_CB, NULL); 2140 } 2141 2142 static int qed_configure_filter(struct qed_dev *cdev, 2143 struct qed_filter_params *params) 2144 { 2145 enum qed_filter_rx_mode_type accept_flags; 2146 2147 switch (params->type) { 2148 case QED_FILTER_TYPE_UCAST: 2149 return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 2150 case QED_FILTER_TYPE_MCAST: 2151 return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 2152 case QED_FILTER_TYPE_RX_MODE: 2153 accept_flags = params->filter.accept_flags; 2154 return qed_configure_filter_rx_mode(cdev, accept_flags); 2155 default: 2156 DP_NOTICE(cdev, "Unknown filter type %d\n", 2157 (int)params->type); 2158 return -EINVAL; 2159 } 2160 } 2161 2162 static int qed_fp_cqe_completion(struct qed_dev *dev, 2163 u8 rss_id, 2164 struct eth_slow_path_rx_cqe *cqe) 2165 { 2166 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 2167 cqe); 2168 } 2169 2170 #ifdef CONFIG_QED_SRIOV 2171 extern const struct qed_iov_hv_ops qed_iov_ops_pass; 2172 #endif 2173 2174 #ifdef CONFIG_DCB 2175 extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass; 2176 #endif 2177 2178 static const struct qed_eth_ops qed_eth_ops_pass = { 2179 .common = &qed_common_ops_pass, 2180 #ifdef CONFIG_QED_SRIOV 2181 .iov = &qed_iov_ops_pass, 2182 #endif 2183 #ifdef CONFIG_DCB 2184 .dcb = &qed_dcbnl_ops_pass, 2185 #endif 2186 .fill_dev_info = &qed_fill_eth_dev_info, 2187 .register_ops = &qed_register_eth_ops, 2188 .check_mac = &qed_check_mac, 2189 .vport_start = &qed_start_vport, 2190 .vport_stop = &qed_stop_vport, 2191 .vport_update = &qed_update_vport, 2192 .q_rx_start = &qed_start_rxq, 2193 .q_rx_stop = &qed_stop_rxq, 2194 .q_tx_start = &qed_start_txq, 2195 .q_tx_stop = &qed_stop_txq, 2196 .filter_config = &qed_configure_filter, 2197 .fastpath_stop = &qed_fastpath_stop, 2198 .eth_cqe_completion = &qed_fp_cqe_completion, 2199 .get_vport_stats = &qed_get_vport_stats, 2200 .tunn_config = &qed_tunn_configure, 2201 }; 2202 2203 const struct qed_eth_ops *qed_get_eth_ops(void) 2204 { 2205 return &qed_eth_ops_pass; 2206 } 2207 EXPORT_SYMBOL(qed_get_eth_ops); 2208 2209 void qed_put_eth_ops(void) 2210 { 2211 /* TODO - reference count for module? */ 2212 } 2213 EXPORT_SYMBOL(qed_put_eth_ops); 2214