1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <asm/param.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/etherdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/slab.h> 20 #include <linux/stddef.h> 21 #include <linux/string.h> 22 #include <linux/version.h> 23 #include <linux/workqueue.h> 24 #include <linux/bitops.h> 25 #include <linux/bug.h> 26 #include "qed.h" 27 #include <linux/qed/qed_chain.h> 28 #include "qed_cxt.h" 29 #include "qed_dev_api.h" 30 #include <linux/qed/qed_eth_if.h> 31 #include "qed_hsi.h" 32 #include "qed_hw.h" 33 #include "qed_int.h" 34 #include "qed_l2.h" 35 #include "qed_mcp.h" 36 #include "qed_reg_addr.h" 37 #include "qed_sp.h" 38 #include "qed_sriov.h" 39 40 41 #define QED_MAX_SGES_NUM 16 42 #define CRC32_POLY 0x1edc6f41 43 44 int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 45 struct qed_sp_vport_start_params *p_params) 46 { 47 struct vport_start_ramrod_data *p_ramrod = NULL; 48 struct qed_spq_entry *p_ent = NULL; 49 struct qed_sp_init_data init_data; 50 u8 abs_vport_id = 0; 51 int rc = -EINVAL; 52 u16 rx_mode = 0; 53 54 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 55 if (rc != 0) 56 return rc; 57 58 memset(&init_data, 0, sizeof(init_data)); 59 init_data.cid = qed_spq_get_cid(p_hwfn); 60 init_data.opaque_fid = p_params->opaque_fid; 61 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 62 63 rc = qed_sp_init_request(p_hwfn, &p_ent, 64 ETH_RAMROD_VPORT_START, 65 PROTOCOLID_ETH, &init_data); 66 if (rc) 67 return rc; 68 69 p_ramrod = &p_ent->ramrod.vport_start; 70 p_ramrod->vport_id = abs_vport_id; 71 72 p_ramrod->mtu = cpu_to_le16(p_params->mtu); 73 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 74 p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 75 76 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 77 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 78 79 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 80 81 /* TPA related fields */ 82 memset(&p_ramrod->tpa_param, 0, 83 sizeof(struct eth_vport_tpa_param)); 84 85 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; 86 87 switch (p_params->tpa_mode) { 88 case QED_TPA_MODE_GRO: 89 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 90 p_ramrod->tpa_param.tpa_max_size = (u16)-1; 91 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; 92 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; 93 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; 94 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; 95 p_ramrod->tpa_param.tpa_pkt_split_flg = 1; 96 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; 97 break; 98 default: 99 break; 100 } 101 102 p_ramrod->tx_switching_en = p_params->tx_switching; 103 104 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 105 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 106 p_params->concrete_fid); 107 108 return qed_spq_post(p_hwfn, p_ent, NULL); 109 } 110 111 int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 112 struct qed_sp_vport_start_params *p_params) 113 { 114 if (IS_VF(p_hwfn->cdev)) { 115 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, 116 p_params->mtu, 117 p_params->remove_inner_vlan, 118 p_params->tpa_mode, 119 p_params->max_buffers_per_cqe, 120 p_params->only_untagged); 121 } 122 123 return qed_sp_eth_vport_start(p_hwfn, p_params); 124 } 125 126 static int 127 qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 128 struct vport_update_ramrod_data *p_ramrod, 129 struct qed_rss_params *p_params) 130 { 131 struct eth_vport_rss_config *rss = &p_ramrod->rss_config; 132 u16 abs_l2_queue = 0, capabilities = 0; 133 int rc = 0, i; 134 135 if (!p_params) { 136 p_ramrod->common.update_rss_flg = 0; 137 return rc; 138 } 139 140 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != 141 ETH_RSS_IND_TABLE_ENTRIES_NUM); 142 143 rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id); 144 if (rc) 145 return rc; 146 147 p_ramrod->common.update_rss_flg = p_params->update_rss_config; 148 rss->update_rss_capabilities = p_params->update_rss_capabilities; 149 rss->update_rss_ind_table = p_params->update_rss_ind_table; 150 rss->update_rss_key = p_params->update_rss_key; 151 152 rss->rss_mode = p_params->rss_enable ? 153 ETH_VPORT_RSS_MODE_REGULAR : 154 ETH_VPORT_RSS_MODE_DISABLED; 155 156 SET_FIELD(capabilities, 157 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 158 !!(p_params->rss_caps & QED_RSS_IPV4)); 159 SET_FIELD(capabilities, 160 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 161 !!(p_params->rss_caps & QED_RSS_IPV6)); 162 SET_FIELD(capabilities, 163 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 164 !!(p_params->rss_caps & QED_RSS_IPV4_TCP)); 165 SET_FIELD(capabilities, 166 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 167 !!(p_params->rss_caps & QED_RSS_IPV6_TCP)); 168 SET_FIELD(capabilities, 169 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 170 !!(p_params->rss_caps & QED_RSS_IPV4_UDP)); 171 SET_FIELD(capabilities, 172 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 173 !!(p_params->rss_caps & QED_RSS_IPV6_UDP)); 174 rss->tbl_size = p_params->rss_table_size_log; 175 176 rss->capabilities = cpu_to_le16(capabilities); 177 178 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 179 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 180 p_ramrod->common.update_rss_flg, 181 rss->rss_mode, rss->update_rss_capabilities, 182 capabilities, rss->update_rss_ind_table, 183 rss->update_rss_key); 184 185 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 186 rc = qed_fw_l2_queue(p_hwfn, 187 (u8)p_params->rss_ind_table[i], 188 &abs_l2_queue); 189 if (rc) 190 return rc; 191 192 rss->indirection_table[i] = cpu_to_le16(abs_l2_queue); 193 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n", 194 i, rss->indirection_table[i]); 195 } 196 197 for (i = 0; i < 10; i++) 198 rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]); 199 200 return rc; 201 } 202 203 static void 204 qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 205 struct vport_update_ramrod_data *p_ramrod, 206 struct qed_filter_accept_flags accept_flags) 207 { 208 p_ramrod->common.update_rx_mode_flg = 209 accept_flags.update_rx_mode_config; 210 211 p_ramrod->common.update_tx_mode_flg = 212 accept_flags.update_tx_mode_config; 213 214 /* Set Rx mode accept flags */ 215 if (p_ramrod->common.update_rx_mode_flg) { 216 u8 accept_filter = accept_flags.rx_accept_filter; 217 u16 state = 0; 218 219 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 220 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 221 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 222 223 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 224 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 225 226 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 227 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 228 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 229 230 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 231 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 232 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 233 234 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 235 !!(accept_filter & QED_ACCEPT_BCAST)); 236 237 p_ramrod->rx_mode.state = cpu_to_le16(state); 238 DP_VERBOSE(p_hwfn, QED_MSG_SP, 239 "p_ramrod->rx_mode.state = 0x%x\n", state); 240 } 241 242 /* Set Tx mode accept flags */ 243 if (p_ramrod->common.update_tx_mode_flg) { 244 u8 accept_filter = accept_flags.tx_accept_filter; 245 u16 state = 0; 246 247 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 248 !!(accept_filter & QED_ACCEPT_NONE)); 249 250 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL, 251 (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) && 252 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 253 254 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 255 !!(accept_filter & QED_ACCEPT_NONE)); 256 257 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 258 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 259 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 260 261 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 262 !!(accept_filter & QED_ACCEPT_BCAST)); 263 264 p_ramrod->tx_mode.state = cpu_to_le16(state); 265 DP_VERBOSE(p_hwfn, QED_MSG_SP, 266 "p_ramrod->tx_mode.state = 0x%x\n", state); 267 } 268 } 269 270 static void 271 qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, 272 struct vport_update_ramrod_data *p_ramrod, 273 struct qed_sge_tpa_params *p_params) 274 { 275 struct eth_vport_tpa_param *p_tpa; 276 277 if (!p_params) { 278 p_ramrod->common.update_tpa_param_flg = 0; 279 p_ramrod->common.update_tpa_en_flg = 0; 280 p_ramrod->common.update_tpa_param_flg = 0; 281 return; 282 } 283 284 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; 285 p_tpa = &p_ramrod->tpa_param; 286 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; 287 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; 288 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; 289 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; 290 291 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; 292 p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 293 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; 294 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; 295 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; 296 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; 297 p_tpa->tpa_max_size = p_params->tpa_max_size; 298 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; 299 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; 300 } 301 302 static void 303 qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 304 struct vport_update_ramrod_data *p_ramrod, 305 struct qed_sp_vport_update_params *p_params) 306 { 307 int i; 308 309 memset(&p_ramrod->approx_mcast.bins, 0, 310 sizeof(p_ramrod->approx_mcast.bins)); 311 312 if (p_params->update_approx_mcast_flg) { 313 p_ramrod->common.update_approx_mcast_flg = 1; 314 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 315 u32 *p_bins = (u32 *)p_params->bins; 316 __le32 val = cpu_to_le32(p_bins[i]); 317 318 p_ramrod->approx_mcast.bins[i] = val; 319 } 320 } 321 } 322 323 int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 324 struct qed_sp_vport_update_params *p_params, 325 enum spq_mode comp_mode, 326 struct qed_spq_comp_cb *p_comp_data) 327 { 328 struct qed_rss_params *p_rss_params = p_params->rss_params; 329 struct vport_update_ramrod_data_cmn *p_cmn; 330 struct qed_sp_init_data init_data; 331 struct vport_update_ramrod_data *p_ramrod = NULL; 332 struct qed_spq_entry *p_ent = NULL; 333 u8 abs_vport_id = 0, val; 334 int rc = -EINVAL; 335 336 if (IS_VF(p_hwfn->cdev)) { 337 rc = qed_vf_pf_vport_update(p_hwfn, p_params); 338 return rc; 339 } 340 341 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 342 if (rc != 0) 343 return rc; 344 345 memset(&init_data, 0, sizeof(init_data)); 346 init_data.cid = qed_spq_get_cid(p_hwfn); 347 init_data.opaque_fid = p_params->opaque_fid; 348 init_data.comp_mode = comp_mode; 349 init_data.p_comp_data = p_comp_data; 350 351 rc = qed_sp_init_request(p_hwfn, &p_ent, 352 ETH_RAMROD_VPORT_UPDATE, 353 PROTOCOLID_ETH, &init_data); 354 if (rc) 355 return rc; 356 357 /* Copy input params to ramrod according to FW struct */ 358 p_ramrod = &p_ent->ramrod.vport_update; 359 p_cmn = &p_ramrod->common; 360 361 p_cmn->vport_id = abs_vport_id; 362 p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 363 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 364 p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 365 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 366 p_cmn->accept_any_vlan = p_params->accept_any_vlan; 367 p_cmn->update_accept_any_vlan_flg = 368 p_params->update_accept_any_vlan_flg; 369 370 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; 371 val = p_params->update_inner_vlan_removal_flg; 372 p_cmn->update_inner_vlan_removal_en_flg = val; 373 374 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; 375 val = p_params->update_default_vlan_enable_flg; 376 p_cmn->update_default_vlan_en_flg = val; 377 378 p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); 379 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; 380 381 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; 382 383 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; 384 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; 385 386 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; 387 val = p_params->update_anti_spoofing_en_flg; 388 p_ramrod->common.update_anti_spoofing_en_flg = val; 389 390 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 391 if (rc) { 392 /* Return spq entry which is taken in qed_sp_init_request()*/ 393 qed_spq_return_entry(p_hwfn, p_ent); 394 return rc; 395 } 396 397 /* Update mcast bins for VFs, PF doesn't use this functionality */ 398 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 399 400 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 401 qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); 402 return qed_spq_post(p_hwfn, p_ent, NULL); 403 } 404 405 int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) 406 { 407 struct vport_stop_ramrod_data *p_ramrod; 408 struct qed_sp_init_data init_data; 409 struct qed_spq_entry *p_ent; 410 u8 abs_vport_id = 0; 411 int rc; 412 413 if (IS_VF(p_hwfn->cdev)) 414 return qed_vf_pf_vport_stop(p_hwfn); 415 416 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 417 if (rc != 0) 418 return rc; 419 420 memset(&init_data, 0, sizeof(init_data)); 421 init_data.cid = qed_spq_get_cid(p_hwfn); 422 init_data.opaque_fid = opaque_fid; 423 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 424 425 rc = qed_sp_init_request(p_hwfn, &p_ent, 426 ETH_RAMROD_VPORT_STOP, 427 PROTOCOLID_ETH, &init_data); 428 if (rc) 429 return rc; 430 431 p_ramrod = &p_ent->ramrod.vport_stop; 432 p_ramrod->vport_id = abs_vport_id; 433 434 return qed_spq_post(p_hwfn, p_ent, NULL); 435 } 436 437 static int 438 qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, 439 struct qed_filter_accept_flags *p_accept_flags) 440 { 441 struct qed_sp_vport_update_params s_params; 442 443 memset(&s_params, 0, sizeof(s_params)); 444 memcpy(&s_params.accept_flags, p_accept_flags, 445 sizeof(struct qed_filter_accept_flags)); 446 447 return qed_vf_pf_vport_update(p_hwfn, &s_params); 448 } 449 450 static int qed_filter_accept_cmd(struct qed_dev *cdev, 451 u8 vport, 452 struct qed_filter_accept_flags accept_flags, 453 u8 update_accept_any_vlan, 454 u8 accept_any_vlan, 455 enum spq_mode comp_mode, 456 struct qed_spq_comp_cb *p_comp_data) 457 { 458 struct qed_sp_vport_update_params vport_update_params; 459 int i, rc; 460 461 /* Prepare and send the vport rx_mode change */ 462 memset(&vport_update_params, 0, sizeof(vport_update_params)); 463 vport_update_params.vport_id = vport; 464 vport_update_params.accept_flags = accept_flags; 465 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 466 vport_update_params.accept_any_vlan = accept_any_vlan; 467 468 for_each_hwfn(cdev, i) { 469 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 470 471 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 472 473 if (IS_VF(cdev)) { 474 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); 475 if (rc) 476 return rc; 477 continue; 478 } 479 480 rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 481 comp_mode, p_comp_data); 482 if (rc != 0) { 483 DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 484 return rc; 485 } 486 487 DP_VERBOSE(p_hwfn, QED_MSG_SP, 488 "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 489 accept_flags.rx_accept_filter, 490 accept_flags.tx_accept_filter); 491 if (update_accept_any_vlan) 492 DP_VERBOSE(p_hwfn, QED_MSG_SP, 493 "accept_any_vlan=%d configured\n", 494 accept_any_vlan); 495 } 496 497 return 0; 498 } 499 500 static int qed_sp_release_queue_cid( 501 struct qed_hwfn *p_hwfn, 502 struct qed_hw_cid_data *p_cid_data) 503 { 504 if (!p_cid_data->b_cid_allocated) 505 return 0; 506 507 qed_cxt_release_cid(p_hwfn, p_cid_data->cid); 508 509 p_cid_data->b_cid_allocated = false; 510 511 return 0; 512 } 513 514 int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 515 u16 opaque_fid, 516 u32 cid, 517 struct qed_queue_start_common_params *params, 518 u8 stats_id, 519 u16 bd_max_bytes, 520 dma_addr_t bd_chain_phys_addr, 521 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size) 522 { 523 struct rx_queue_start_ramrod_data *p_ramrod = NULL; 524 struct qed_spq_entry *p_ent = NULL; 525 struct qed_sp_init_data init_data; 526 struct qed_hw_cid_data *p_rx_cid; 527 u16 abs_rx_q_id = 0; 528 u8 abs_vport_id = 0; 529 int rc = -EINVAL; 530 531 /* Store information for the stop */ 532 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 533 p_rx_cid->cid = cid; 534 p_rx_cid->opaque_fid = opaque_fid; 535 p_rx_cid->vport_id = params->vport_id; 536 537 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id); 538 if (rc != 0) 539 return rc; 540 541 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id); 542 if (rc != 0) 543 return rc; 544 545 DP_VERBOSE(p_hwfn, QED_MSG_SP, 546 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 547 opaque_fid, cid, params->queue_id, params->vport_id, 548 params->sb); 549 550 /* Get SPQ entry */ 551 memset(&init_data, 0, sizeof(init_data)); 552 init_data.cid = cid; 553 init_data.opaque_fid = opaque_fid; 554 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 555 556 rc = qed_sp_init_request(p_hwfn, &p_ent, 557 ETH_RAMROD_RX_QUEUE_START, 558 PROTOCOLID_ETH, &init_data); 559 if (rc) 560 return rc; 561 562 p_ramrod = &p_ent->ramrod.rx_queue_start; 563 564 p_ramrod->sb_id = cpu_to_le16(params->sb); 565 p_ramrod->sb_index = params->sb_idx; 566 p_ramrod->vport_id = abs_vport_id; 567 p_ramrod->stats_counter_id = stats_id; 568 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 569 p_ramrod->complete_cqe_flg = 0; 570 p_ramrod->complete_event_flg = 1; 571 572 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 573 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 574 575 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 576 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 577 578 rc = qed_spq_post(p_hwfn, p_ent, NULL); 579 580 return rc; 581 } 582 583 static int 584 qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 585 u16 opaque_fid, 586 struct qed_queue_start_common_params *params, 587 u16 bd_max_bytes, 588 dma_addr_t bd_chain_phys_addr, 589 dma_addr_t cqe_pbl_addr, 590 u16 cqe_pbl_size, void __iomem **pp_prod) 591 { 592 struct qed_hw_cid_data *p_rx_cid; 593 u64 init_prod_val = 0; 594 u16 abs_l2_queue = 0; 595 u8 abs_stats_id = 0; 596 int rc; 597 598 if (IS_VF(p_hwfn->cdev)) { 599 return qed_vf_pf_rxq_start(p_hwfn, 600 params->queue_id, 601 params->sb, 602 params->sb_idx, 603 bd_max_bytes, 604 bd_chain_phys_addr, 605 cqe_pbl_addr, cqe_pbl_size, pp_prod); 606 } 607 608 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue); 609 if (rc != 0) 610 return rc; 611 612 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id); 613 if (rc != 0) 614 return rc; 615 616 *pp_prod = (u8 __iomem *)p_hwfn->regview + 617 GTT_BAR0_MAP_REG_MSDM_RAM + 618 MSTORM_PRODS_OFFSET(abs_l2_queue); 619 620 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 621 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64), 622 (u32 *)(&init_prod_val)); 623 624 /* Allocate a CID for the queue */ 625 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 626 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 627 &p_rx_cid->cid); 628 if (rc) { 629 DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 630 return rc; 631 } 632 p_rx_cid->b_cid_allocated = true; 633 634 rc = qed_sp_eth_rxq_start_ramrod(p_hwfn, 635 opaque_fid, 636 p_rx_cid->cid, 637 params, 638 abs_stats_id, 639 bd_max_bytes, 640 bd_chain_phys_addr, 641 cqe_pbl_addr, 642 cqe_pbl_size); 643 644 if (rc != 0) 645 qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 646 647 return rc; 648 } 649 650 int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 651 u16 rx_queue_id, 652 u8 num_rxqs, 653 u8 complete_cqe_flg, 654 u8 complete_event_flg, 655 enum spq_mode comp_mode, 656 struct qed_spq_comp_cb *p_comp_data) 657 { 658 struct rx_queue_update_ramrod_data *p_ramrod = NULL; 659 struct qed_spq_entry *p_ent = NULL; 660 struct qed_sp_init_data init_data; 661 struct qed_hw_cid_data *p_rx_cid; 662 u16 qid, abs_rx_q_id = 0; 663 int rc = -EINVAL; 664 u8 i; 665 666 memset(&init_data, 0, sizeof(init_data)); 667 init_data.comp_mode = comp_mode; 668 init_data.p_comp_data = p_comp_data; 669 670 for (i = 0; i < num_rxqs; i++) { 671 qid = rx_queue_id + i; 672 p_rx_cid = &p_hwfn->p_rx_cids[qid]; 673 674 /* Get SPQ entry */ 675 init_data.cid = p_rx_cid->cid; 676 init_data.opaque_fid = p_rx_cid->opaque_fid; 677 678 rc = qed_sp_init_request(p_hwfn, &p_ent, 679 ETH_RAMROD_RX_QUEUE_UPDATE, 680 PROTOCOLID_ETH, &init_data); 681 if (rc) 682 return rc; 683 684 p_ramrod = &p_ent->ramrod.rx_queue_update; 685 686 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); 687 qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id); 688 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 689 p_ramrod->complete_cqe_flg = complete_cqe_flg; 690 p_ramrod->complete_event_flg = complete_event_flg; 691 692 rc = qed_spq_post(p_hwfn, p_ent, NULL); 693 if (rc) 694 return rc; 695 } 696 697 return rc; 698 } 699 700 int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 701 u16 rx_queue_id, 702 bool eq_completion_only, bool cqe_completion) 703 { 704 struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id]; 705 struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 706 struct qed_spq_entry *p_ent = NULL; 707 struct qed_sp_init_data init_data; 708 u16 abs_rx_q_id = 0; 709 int rc = -EINVAL; 710 711 if (IS_VF(p_hwfn->cdev)) 712 return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion); 713 714 /* Get SPQ entry */ 715 memset(&init_data, 0, sizeof(init_data)); 716 init_data.cid = p_rx_cid->cid; 717 init_data.opaque_fid = p_rx_cid->opaque_fid; 718 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 719 720 rc = qed_sp_init_request(p_hwfn, &p_ent, 721 ETH_RAMROD_RX_QUEUE_STOP, 722 PROTOCOLID_ETH, &init_data); 723 if (rc) 724 return rc; 725 726 p_ramrod = &p_ent->ramrod.rx_queue_stop; 727 728 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); 729 qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id); 730 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 731 732 /* Cleaning the queue requires the completion to arrive there. 733 * In addition, VFs require the answer to come as eqe to PF. 734 */ 735 p_ramrod->complete_cqe_flg = 736 (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) && 737 !eq_completion_only) || cqe_completion; 738 p_ramrod->complete_event_flg = 739 !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) || 740 eq_completion_only; 741 742 rc = qed_spq_post(p_hwfn, p_ent, NULL); 743 if (rc) 744 return rc; 745 746 return qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 747 } 748 749 int qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 750 u16 opaque_fid, 751 u32 cid, 752 struct qed_queue_start_common_params *p_params, 753 u8 stats_id, 754 dma_addr_t pbl_addr, 755 u16 pbl_size, 756 union qed_qm_pq_params *p_pq_params) 757 { 758 struct tx_queue_start_ramrod_data *p_ramrod = NULL; 759 struct qed_spq_entry *p_ent = NULL; 760 struct qed_sp_init_data init_data; 761 struct qed_hw_cid_data *p_tx_cid; 762 u8 abs_vport_id; 763 int rc = -EINVAL; 764 u16 pq_id; 765 766 /* Store information for the stop */ 767 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 768 p_tx_cid->cid = cid; 769 p_tx_cid->opaque_fid = opaque_fid; 770 771 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 772 if (rc) 773 return rc; 774 775 /* Get SPQ entry */ 776 memset(&init_data, 0, sizeof(init_data)); 777 init_data.cid = cid; 778 init_data.opaque_fid = opaque_fid; 779 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 780 781 rc = qed_sp_init_request(p_hwfn, &p_ent, 782 ETH_RAMROD_TX_QUEUE_START, 783 PROTOCOLID_ETH, &init_data); 784 if (rc) 785 return rc; 786 787 p_ramrod = &p_ent->ramrod.tx_queue_start; 788 p_ramrod->vport_id = abs_vport_id; 789 790 p_ramrod->sb_id = cpu_to_le16(p_params->sb); 791 p_ramrod->sb_index = p_params->sb_idx; 792 p_ramrod->stats_counter_id = stats_id; 793 794 p_ramrod->pbl_size = cpu_to_le16(pbl_size); 795 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 796 797 pq_id = qed_get_qm_pq(p_hwfn, 798 PROTOCOLID_ETH, 799 p_pq_params); 800 p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 801 802 return qed_spq_post(p_hwfn, p_ent, NULL); 803 } 804 805 static int 806 qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 807 u16 opaque_fid, 808 struct qed_queue_start_common_params *p_params, 809 dma_addr_t pbl_addr, 810 u16 pbl_size, void __iomem **pp_doorbell) 811 { 812 struct qed_hw_cid_data *p_tx_cid; 813 union qed_qm_pq_params pq_params; 814 u8 abs_stats_id = 0; 815 int rc; 816 817 if (IS_VF(p_hwfn->cdev)) { 818 return qed_vf_pf_txq_start(p_hwfn, 819 p_params->queue_id, 820 p_params->sb, 821 p_params->sb_idx, 822 pbl_addr, pbl_size, pp_doorbell); 823 } 824 825 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id); 826 if (rc) 827 return rc; 828 829 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 830 memset(p_tx_cid, 0, sizeof(*p_tx_cid)); 831 memset(&pq_params, 0, sizeof(pq_params)); 832 833 /* Allocate a CID for the queue */ 834 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 835 &p_tx_cid->cid); 836 if (rc) { 837 DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 838 return rc; 839 } 840 p_tx_cid->b_cid_allocated = true; 841 842 DP_VERBOSE(p_hwfn, QED_MSG_SP, 843 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 844 opaque_fid, p_tx_cid->cid, 845 p_params->queue_id, p_params->vport_id, p_params->sb); 846 847 rc = qed_sp_eth_txq_start_ramrod(p_hwfn, 848 opaque_fid, 849 p_tx_cid->cid, 850 p_params, 851 abs_stats_id, 852 pbl_addr, 853 pbl_size, 854 &pq_params); 855 856 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + 857 qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY); 858 859 if (rc) 860 qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 861 862 return rc; 863 } 864 865 int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id) 866 { 867 struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id]; 868 struct qed_spq_entry *p_ent = NULL; 869 struct qed_sp_init_data init_data; 870 int rc = -EINVAL; 871 872 if (IS_VF(p_hwfn->cdev)) 873 return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id); 874 875 /* Get SPQ entry */ 876 memset(&init_data, 0, sizeof(init_data)); 877 init_data.cid = p_tx_cid->cid; 878 init_data.opaque_fid = p_tx_cid->opaque_fid; 879 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 880 881 rc = qed_sp_init_request(p_hwfn, &p_ent, 882 ETH_RAMROD_TX_QUEUE_STOP, 883 PROTOCOLID_ETH, &init_data); 884 if (rc) 885 return rc; 886 887 rc = qed_spq_post(p_hwfn, p_ent, NULL); 888 if (rc) 889 return rc; 890 891 return qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 892 } 893 894 static enum eth_filter_action 895 qed_filter_action(enum qed_filter_opcode opcode) 896 { 897 enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 898 899 switch (opcode) { 900 case QED_FILTER_ADD: 901 action = ETH_FILTER_ACTION_ADD; 902 break; 903 case QED_FILTER_REMOVE: 904 action = ETH_FILTER_ACTION_REMOVE; 905 break; 906 case QED_FILTER_FLUSH: 907 action = ETH_FILTER_ACTION_REMOVE_ALL; 908 break; 909 default: 910 action = MAX_ETH_FILTER_ACTION; 911 } 912 913 return action; 914 } 915 916 static void qed_set_fw_mac_addr(__le16 *fw_msb, 917 __le16 *fw_mid, 918 __le16 *fw_lsb, 919 u8 *mac) 920 { 921 ((u8 *)fw_msb)[0] = mac[1]; 922 ((u8 *)fw_msb)[1] = mac[0]; 923 ((u8 *)fw_mid)[0] = mac[3]; 924 ((u8 *)fw_mid)[1] = mac[2]; 925 ((u8 *)fw_lsb)[0] = mac[5]; 926 ((u8 *)fw_lsb)[1] = mac[4]; 927 } 928 929 static int 930 qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 931 u16 opaque_fid, 932 struct qed_filter_ucast *p_filter_cmd, 933 struct vport_filter_update_ramrod_data **pp_ramrod, 934 struct qed_spq_entry **pp_ent, 935 enum spq_mode comp_mode, 936 struct qed_spq_comp_cb *p_comp_data) 937 { 938 u8 vport_to_add_to = 0, vport_to_remove_from = 0; 939 struct vport_filter_update_ramrod_data *p_ramrod; 940 struct eth_filter_cmd *p_first_filter; 941 struct eth_filter_cmd *p_second_filter; 942 struct qed_sp_init_data init_data; 943 enum eth_filter_action action; 944 int rc; 945 946 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 947 &vport_to_remove_from); 948 if (rc) 949 return rc; 950 951 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 952 &vport_to_add_to); 953 if (rc) 954 return rc; 955 956 /* Get SPQ entry */ 957 memset(&init_data, 0, sizeof(init_data)); 958 init_data.cid = qed_spq_get_cid(p_hwfn); 959 init_data.opaque_fid = opaque_fid; 960 init_data.comp_mode = comp_mode; 961 init_data.p_comp_data = p_comp_data; 962 963 rc = qed_sp_init_request(p_hwfn, pp_ent, 964 ETH_RAMROD_FILTERS_UPDATE, 965 PROTOCOLID_ETH, &init_data); 966 if (rc) 967 return rc; 968 969 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 970 p_ramrod = *pp_ramrod; 971 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 972 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 973 974 switch (p_filter_cmd->opcode) { 975 case QED_FILTER_REPLACE: 976 case QED_FILTER_MOVE: 977 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 978 default: 979 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 980 } 981 982 p_first_filter = &p_ramrod->filter_cmds[0]; 983 p_second_filter = &p_ramrod->filter_cmds[1]; 984 985 switch (p_filter_cmd->type) { 986 case QED_FILTER_MAC: 987 p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 988 case QED_FILTER_VLAN: 989 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 990 case QED_FILTER_MAC_VLAN: 991 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 992 case QED_FILTER_INNER_MAC: 993 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 994 case QED_FILTER_INNER_VLAN: 995 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 996 case QED_FILTER_INNER_PAIR: 997 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 998 case QED_FILTER_INNER_MAC_VNI_PAIR: 999 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 1000 break; 1001 case QED_FILTER_MAC_VNI_PAIR: 1002 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 1003 case QED_FILTER_VNI: 1004 p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 1005 } 1006 1007 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 1008 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1009 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 1010 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 1011 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1012 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 1013 qed_set_fw_mac_addr(&p_first_filter->mac_msb, 1014 &p_first_filter->mac_mid, 1015 &p_first_filter->mac_lsb, 1016 (u8 *)p_filter_cmd->mac); 1017 } 1018 1019 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 1020 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1021 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 1022 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 1023 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 1024 1025 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1026 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 1027 (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 1028 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 1029 1030 if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 1031 p_second_filter->type = p_first_filter->type; 1032 p_second_filter->mac_msb = p_first_filter->mac_msb; 1033 p_second_filter->mac_mid = p_first_filter->mac_mid; 1034 p_second_filter->mac_lsb = p_first_filter->mac_lsb; 1035 p_second_filter->vlan_id = p_first_filter->vlan_id; 1036 p_second_filter->vni = p_first_filter->vni; 1037 1038 p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 1039 1040 p_first_filter->vport_id = vport_to_remove_from; 1041 1042 p_second_filter->action = ETH_FILTER_ACTION_ADD; 1043 p_second_filter->vport_id = vport_to_add_to; 1044 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 1045 p_first_filter->vport_id = vport_to_add_to; 1046 memcpy(p_second_filter, p_first_filter, 1047 sizeof(*p_second_filter)); 1048 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 1049 p_second_filter->action = ETH_FILTER_ACTION_ADD; 1050 } else { 1051 action = qed_filter_action(p_filter_cmd->opcode); 1052 1053 if (action == MAX_ETH_FILTER_ACTION) { 1054 DP_NOTICE(p_hwfn, 1055 "%d is not supported yet\n", 1056 p_filter_cmd->opcode); 1057 return -EINVAL; 1058 } 1059 1060 p_first_filter->action = action; 1061 p_first_filter->vport_id = (p_filter_cmd->opcode == 1062 QED_FILTER_REMOVE) ? 1063 vport_to_remove_from : 1064 vport_to_add_to; 1065 } 1066 1067 return 0; 1068 } 1069 1070 int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 1071 u16 opaque_fid, 1072 struct qed_filter_ucast *p_filter_cmd, 1073 enum spq_mode comp_mode, 1074 struct qed_spq_comp_cb *p_comp_data) 1075 { 1076 struct vport_filter_update_ramrod_data *p_ramrod = NULL; 1077 struct qed_spq_entry *p_ent = NULL; 1078 struct eth_filter_cmd_header *p_header; 1079 int rc; 1080 1081 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1082 &p_ramrod, &p_ent, 1083 comp_mode, p_comp_data); 1084 if (rc != 0) { 1085 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1086 return rc; 1087 } 1088 p_header = &p_ramrod->filter_cmd_hdr; 1089 p_header->assert_on_error = p_filter_cmd->assert_on_error; 1090 1091 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1092 if (rc != 0) { 1093 DP_ERR(p_hwfn, 1094 "Unicast filter ADD command failed %d\n", 1095 rc); 1096 return rc; 1097 } 1098 1099 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1100 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1101 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1102 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1103 "REMOVE" : 1104 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1105 "MOVE" : "REPLACE")), 1106 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1107 ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1108 "VLAN" : "MAC & VLAN"), 1109 p_ramrod->filter_cmd_hdr.cmd_cnt, 1110 p_filter_cmd->is_rx_filter, 1111 p_filter_cmd->is_tx_filter); 1112 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1113 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1114 p_filter_cmd->vport_to_add_to, 1115 p_filter_cmd->vport_to_remove_from, 1116 p_filter_cmd->mac[0], 1117 p_filter_cmd->mac[1], 1118 p_filter_cmd->mac[2], 1119 p_filter_cmd->mac[3], 1120 p_filter_cmd->mac[4], 1121 p_filter_cmd->mac[5], 1122 p_filter_cmd->vlan); 1123 1124 return 0; 1125 } 1126 1127 /******************************************************************************* 1128 * Description: 1129 * Calculates crc 32 on a buffer 1130 * Note: crc32_length MUST be aligned to 8 1131 * Return: 1132 ******************************************************************************/ 1133 static u32 qed_calc_crc32c(u8 *crc32_packet, 1134 u32 crc32_length, 1135 u32 crc32_seed, 1136 u8 complement) 1137 { 1138 u32 byte = 0; 1139 u32 bit = 0; 1140 u8 msb = 0; 1141 u8 current_byte = 0; 1142 u32 crc32_result = crc32_seed; 1143 1144 if ((!crc32_packet) || 1145 (crc32_length == 0) || 1146 ((crc32_length % 8) != 0)) 1147 return crc32_result; 1148 for (byte = 0; byte < crc32_length; byte++) { 1149 current_byte = crc32_packet[byte]; 1150 for (bit = 0; bit < 8; bit++) { 1151 msb = (u8)(crc32_result >> 31); 1152 crc32_result = crc32_result << 1; 1153 if (msb != (0x1 & (current_byte >> bit))) { 1154 crc32_result = crc32_result ^ CRC32_POLY; 1155 crc32_result |= 1; /*crc32_result[0] = 1;*/ 1156 } 1157 } 1158 } 1159 return crc32_result; 1160 } 1161 1162 static inline u32 qed_crc32c_le(u32 seed, 1163 u8 *mac, 1164 u32 len) 1165 { 1166 u32 packet_buf[2] = { 0 }; 1167 1168 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1169 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1170 } 1171 1172 u8 qed_mcast_bin_from_mac(u8 *mac) 1173 { 1174 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1175 mac, ETH_ALEN); 1176 1177 return crc & 0xff; 1178 } 1179 1180 static int 1181 qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1182 u16 opaque_fid, 1183 struct qed_filter_mcast *p_filter_cmd, 1184 enum spq_mode comp_mode, 1185 struct qed_spq_comp_cb *p_comp_data) 1186 { 1187 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1188 struct vport_update_ramrod_data *p_ramrod = NULL; 1189 struct qed_spq_entry *p_ent = NULL; 1190 struct qed_sp_init_data init_data; 1191 u8 abs_vport_id = 0; 1192 int rc, i; 1193 1194 if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1195 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1196 &abs_vport_id); 1197 if (rc) 1198 return rc; 1199 } else { 1200 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1201 &abs_vport_id); 1202 if (rc) 1203 return rc; 1204 } 1205 1206 /* Get SPQ entry */ 1207 memset(&init_data, 0, sizeof(init_data)); 1208 init_data.cid = qed_spq_get_cid(p_hwfn); 1209 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1210 init_data.comp_mode = comp_mode; 1211 init_data.p_comp_data = p_comp_data; 1212 1213 rc = qed_sp_init_request(p_hwfn, &p_ent, 1214 ETH_RAMROD_VPORT_UPDATE, 1215 PROTOCOLID_ETH, &init_data); 1216 if (rc) { 1217 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1218 return rc; 1219 } 1220 1221 p_ramrod = &p_ent->ramrod.vport_update; 1222 p_ramrod->common.update_approx_mcast_flg = 1; 1223 1224 /* explicitly clear out the entire vector */ 1225 memset(&p_ramrod->approx_mcast.bins, 0, 1226 sizeof(p_ramrod->approx_mcast.bins)); 1227 memset(bins, 0, sizeof(unsigned long) * 1228 ETH_MULTICAST_MAC_BINS_IN_REGS); 1229 /* filter ADD op is explicit set op and it removes 1230 * any existing filters for the vport 1231 */ 1232 if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1233 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 1234 u32 bit; 1235 1236 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 1237 __set_bit(bit, bins); 1238 } 1239 1240 /* Convert to correct endianity */ 1241 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 1242 u32 *p_bins = (u32 *)bins; 1243 struct vport_update_ramrod_mcast *approx_mcast; 1244 1245 approx_mcast = &p_ramrod->approx_mcast; 1246 approx_mcast->bins[i] = cpu_to_le32(p_bins[i]); 1247 } 1248 } 1249 1250 p_ramrod->common.vport_id = abs_vport_id; 1251 1252 return qed_spq_post(p_hwfn, p_ent, NULL); 1253 } 1254 1255 static int qed_filter_mcast_cmd(struct qed_dev *cdev, 1256 struct qed_filter_mcast *p_filter_cmd, 1257 enum spq_mode comp_mode, 1258 struct qed_spq_comp_cb *p_comp_data) 1259 { 1260 int rc = 0; 1261 int i; 1262 1263 /* only ADD and REMOVE operations are supported for multi-cast */ 1264 if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1265 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1266 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1267 return -EINVAL; 1268 1269 for_each_hwfn(cdev, i) { 1270 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1271 1272 u16 opaque_fid; 1273 1274 if (IS_VF(cdev)) { 1275 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); 1276 continue; 1277 } 1278 1279 opaque_fid = p_hwfn->hw_info.opaque_fid; 1280 1281 rc = qed_sp_eth_filter_mcast(p_hwfn, 1282 opaque_fid, 1283 p_filter_cmd, 1284 comp_mode, 1285 p_comp_data); 1286 } 1287 return rc; 1288 } 1289 1290 static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1291 struct qed_filter_ucast *p_filter_cmd, 1292 enum spq_mode comp_mode, 1293 struct qed_spq_comp_cb *p_comp_data) 1294 { 1295 int rc = 0; 1296 int i; 1297 1298 for_each_hwfn(cdev, i) { 1299 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1300 u16 opaque_fid; 1301 1302 if (IS_VF(cdev)) { 1303 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); 1304 continue; 1305 } 1306 1307 opaque_fid = p_hwfn->hw_info.opaque_fid; 1308 1309 rc = qed_sp_eth_filter_ucast(p_hwfn, 1310 opaque_fid, 1311 p_filter_cmd, 1312 comp_mode, 1313 p_comp_data); 1314 if (rc != 0) 1315 break; 1316 } 1317 1318 return rc; 1319 } 1320 1321 /* Statistics related code */ 1322 static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 1323 u32 *p_addr, 1324 u32 *p_len, u16 statistics_bin) 1325 { 1326 if (IS_PF(p_hwfn->cdev)) { 1327 *p_addr = BAR0_MAP_REG_PSDM_RAM + 1328 PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 1329 *p_len = sizeof(struct eth_pstorm_per_queue_stat); 1330 } else { 1331 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1332 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1333 1334 *p_addr = p_resp->pfdev_info.stats_info.pstats.address; 1335 *p_len = p_resp->pfdev_info.stats_info.pstats.len; 1336 } 1337 } 1338 1339 static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 1340 struct qed_ptt *p_ptt, 1341 struct qed_eth_stats *p_stats, 1342 u16 statistics_bin) 1343 { 1344 struct eth_pstorm_per_queue_stat pstats; 1345 u32 pstats_addr = 0, pstats_len = 0; 1346 1347 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 1348 statistics_bin); 1349 1350 memset(&pstats, 0, sizeof(pstats)); 1351 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); 1352 1353 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes); 1354 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes); 1355 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes); 1356 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts); 1357 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts); 1358 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts); 1359 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts); 1360 } 1361 1362 static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 1363 struct qed_ptt *p_ptt, 1364 struct qed_eth_stats *p_stats, 1365 u16 statistics_bin) 1366 { 1367 struct tstorm_per_port_stat tstats; 1368 u32 tstats_addr, tstats_len; 1369 1370 if (IS_PF(p_hwfn->cdev)) { 1371 tstats_addr = BAR0_MAP_REG_TSDM_RAM + 1372 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 1373 tstats_len = sizeof(struct tstorm_per_port_stat); 1374 } else { 1375 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1376 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1377 1378 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; 1379 tstats_len = p_resp->pfdev_info.stats_info.tstats.len; 1380 } 1381 1382 memset(&tstats, 0, sizeof(tstats)); 1383 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); 1384 1385 p_stats->mftag_filter_discards += 1386 HILO_64_REGPAIR(tstats.mftag_filter_discard); 1387 p_stats->mac_filter_discards += 1388 HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 1389 } 1390 1391 static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 1392 u32 *p_addr, 1393 u32 *p_len, u16 statistics_bin) 1394 { 1395 if (IS_PF(p_hwfn->cdev)) { 1396 *p_addr = BAR0_MAP_REG_USDM_RAM + 1397 USTORM_QUEUE_STAT_OFFSET(statistics_bin); 1398 *p_len = sizeof(struct eth_ustorm_per_queue_stat); 1399 } else { 1400 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1401 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1402 1403 *p_addr = p_resp->pfdev_info.stats_info.ustats.address; 1404 *p_len = p_resp->pfdev_info.stats_info.ustats.len; 1405 } 1406 } 1407 1408 static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 1409 struct qed_ptt *p_ptt, 1410 struct qed_eth_stats *p_stats, 1411 u16 statistics_bin) 1412 { 1413 struct eth_ustorm_per_queue_stat ustats; 1414 u32 ustats_addr = 0, ustats_len = 0; 1415 1416 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 1417 statistics_bin); 1418 1419 memset(&ustats, 0, sizeof(ustats)); 1420 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); 1421 1422 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 1423 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 1424 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 1425 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 1426 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 1427 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 1428 } 1429 1430 static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 1431 u32 *p_addr, 1432 u32 *p_len, u16 statistics_bin) 1433 { 1434 if (IS_PF(p_hwfn->cdev)) { 1435 *p_addr = BAR0_MAP_REG_MSDM_RAM + 1436 MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 1437 *p_len = sizeof(struct eth_mstorm_per_queue_stat); 1438 } else { 1439 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1440 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1441 1442 *p_addr = p_resp->pfdev_info.stats_info.mstats.address; 1443 *p_len = p_resp->pfdev_info.stats_info.mstats.len; 1444 } 1445 } 1446 1447 static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 1448 struct qed_ptt *p_ptt, 1449 struct qed_eth_stats *p_stats, 1450 u16 statistics_bin) 1451 { 1452 struct eth_mstorm_per_queue_stat mstats; 1453 u32 mstats_addr = 0, mstats_len = 0; 1454 1455 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 1456 statistics_bin); 1457 1458 memset(&mstats, 0, sizeof(mstats)); 1459 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); 1460 1461 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard); 1462 p_stats->packet_too_big_discard += 1463 HILO_64_REGPAIR(mstats.packet_too_big_discard); 1464 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); 1465 p_stats->tpa_coalesced_pkts += 1466 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 1467 p_stats->tpa_coalesced_events += 1468 HILO_64_REGPAIR(mstats.tpa_coalesced_events); 1469 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num); 1470 p_stats->tpa_coalesced_bytes += 1471 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 1472 } 1473 1474 static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 1475 struct qed_ptt *p_ptt, 1476 struct qed_eth_stats *p_stats) 1477 { 1478 struct port_stats port_stats; 1479 int j; 1480 1481 memset(&port_stats, 0, sizeof(port_stats)); 1482 1483 qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 1484 p_hwfn->mcp_info->port_addr + 1485 offsetof(struct public_port, stats), 1486 sizeof(port_stats)); 1487 1488 p_stats->rx_64_byte_packets += port_stats.pmm.r64; 1489 p_stats->rx_65_to_127_byte_packets += port_stats.pmm.r127; 1490 p_stats->rx_128_to_255_byte_packets += port_stats.pmm.r255; 1491 p_stats->rx_256_to_511_byte_packets += port_stats.pmm.r511; 1492 p_stats->rx_512_to_1023_byte_packets += port_stats.pmm.r1023; 1493 p_stats->rx_1024_to_1518_byte_packets += port_stats.pmm.r1518; 1494 p_stats->rx_1519_to_1522_byte_packets += port_stats.pmm.r1522; 1495 p_stats->rx_1519_to_2047_byte_packets += port_stats.pmm.r2047; 1496 p_stats->rx_2048_to_4095_byte_packets += port_stats.pmm.r4095; 1497 p_stats->rx_4096_to_9216_byte_packets += port_stats.pmm.r9216; 1498 p_stats->rx_9217_to_16383_byte_packets += port_stats.pmm.r16383; 1499 p_stats->rx_crc_errors += port_stats.pmm.rfcs; 1500 p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf; 1501 p_stats->rx_pause_frames += port_stats.pmm.rxpf; 1502 p_stats->rx_pfc_frames += port_stats.pmm.rxpp; 1503 p_stats->rx_align_errors += port_stats.pmm.raln; 1504 p_stats->rx_carrier_errors += port_stats.pmm.rfcr; 1505 p_stats->rx_oversize_packets += port_stats.pmm.rovr; 1506 p_stats->rx_jabbers += port_stats.pmm.rjbr; 1507 p_stats->rx_undersize_packets += port_stats.pmm.rund; 1508 p_stats->rx_fragments += port_stats.pmm.rfrg; 1509 p_stats->tx_64_byte_packets += port_stats.pmm.t64; 1510 p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127; 1511 p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255; 1512 p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511; 1513 p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023; 1514 p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518; 1515 p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047; 1516 p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095; 1517 p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216; 1518 p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383; 1519 p_stats->tx_pause_frames += port_stats.pmm.txpf; 1520 p_stats->tx_pfc_frames += port_stats.pmm.txpp; 1521 p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec; 1522 p_stats->tx_total_collisions += port_stats.pmm.tncl; 1523 p_stats->rx_mac_bytes += port_stats.pmm.rbyte; 1524 p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca; 1525 p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca; 1526 p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca; 1527 p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok; 1528 p_stats->tx_mac_bytes += port_stats.pmm.tbyte; 1529 p_stats->tx_mac_uc_packets += port_stats.pmm.txuca; 1530 p_stats->tx_mac_mc_packets += port_stats.pmm.txmca; 1531 p_stats->tx_mac_bc_packets += port_stats.pmm.txbca; 1532 p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf; 1533 for (j = 0; j < 8; j++) { 1534 p_stats->brb_truncates += port_stats.brb.brb_truncate[j]; 1535 p_stats->brb_discards += port_stats.brb.brb_discard[j]; 1536 } 1537 } 1538 1539 static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 1540 struct qed_ptt *p_ptt, 1541 struct qed_eth_stats *stats, 1542 u16 statistics_bin, bool b_get_port_stats) 1543 { 1544 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 1545 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 1546 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 1547 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 1548 1549 if (b_get_port_stats && p_hwfn->mcp_info) 1550 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 1551 } 1552 1553 static void _qed_get_vport_stats(struct qed_dev *cdev, 1554 struct qed_eth_stats *stats) 1555 { 1556 u8 fw_vport = 0; 1557 int i; 1558 1559 memset(stats, 0, sizeof(*stats)); 1560 1561 for_each_hwfn(cdev, i) { 1562 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1563 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1564 : NULL; 1565 1566 if (IS_PF(cdev)) { 1567 /* The main vport index is relative first */ 1568 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 1569 DP_ERR(p_hwfn, "No vport available!\n"); 1570 goto out; 1571 } 1572 } 1573 1574 if (IS_PF(cdev) && !p_ptt) { 1575 DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 1576 continue; 1577 } 1578 1579 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, 1580 IS_PF(cdev) ? true : false); 1581 1582 out: 1583 if (IS_PF(cdev) && p_ptt) 1584 qed_ptt_release(p_hwfn, p_ptt); 1585 } 1586 } 1587 1588 void qed_get_vport_stats(struct qed_dev *cdev, 1589 struct qed_eth_stats *stats) 1590 { 1591 u32 i; 1592 1593 if (!cdev) { 1594 memset(stats, 0, sizeof(*stats)); 1595 return; 1596 } 1597 1598 _qed_get_vport_stats(cdev, stats); 1599 1600 if (!cdev->reset_stats) 1601 return; 1602 1603 /* Reduce the statistics baseline */ 1604 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 1605 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 1606 } 1607 1608 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 1609 void qed_reset_vport_stats(struct qed_dev *cdev) 1610 { 1611 int i; 1612 1613 for_each_hwfn(cdev, i) { 1614 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1615 struct eth_mstorm_per_queue_stat mstats; 1616 struct eth_ustorm_per_queue_stat ustats; 1617 struct eth_pstorm_per_queue_stat pstats; 1618 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1619 : NULL; 1620 u32 addr = 0, len = 0; 1621 1622 if (IS_PF(cdev) && !p_ptt) { 1623 DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 1624 continue; 1625 } 1626 1627 memset(&mstats, 0, sizeof(mstats)); 1628 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 1629 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 1630 1631 memset(&ustats, 0, sizeof(ustats)); 1632 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 1633 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 1634 1635 memset(&pstats, 0, sizeof(pstats)); 1636 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 1637 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 1638 1639 if (IS_PF(cdev)) 1640 qed_ptt_release(p_hwfn, p_ptt); 1641 } 1642 1643 /* PORT statistics are not necessarily reset, so we need to 1644 * read and create a baseline for future statistics. 1645 */ 1646 if (!cdev->reset_stats) 1647 DP_INFO(cdev, "Reset stats not allocated\n"); 1648 else 1649 _qed_get_vport_stats(cdev, cdev->reset_stats); 1650 } 1651 1652 static int qed_fill_eth_dev_info(struct qed_dev *cdev, 1653 struct qed_dev_eth_info *info) 1654 { 1655 int i; 1656 1657 memset(info, 0, sizeof(*info)); 1658 1659 info->num_tc = 1; 1660 1661 if (IS_PF(cdev)) { 1662 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 1663 for_each_hwfn(cdev, i) 1664 info->num_queues += 1665 FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); 1666 if (cdev->int_params.fp_msix_cnt) 1667 info->num_queues = 1668 min_t(u8, info->num_queues, 1669 cdev->int_params.fp_msix_cnt); 1670 } else { 1671 info->num_queues = cdev->num_hwfns; 1672 } 1673 1674 info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN); 1675 ether_addr_copy(info->port_mac, 1676 cdev->hwfns[0].hw_info.hw_mac_addr); 1677 } else { 1678 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues); 1679 if (cdev->num_hwfns > 1) { 1680 u8 queues = 0; 1681 1682 qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues); 1683 info->num_queues += queues; 1684 } 1685 1686 qed_vf_get_num_vlan_filters(&cdev->hwfns[0], 1687 &info->num_vlan_filters); 1688 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); 1689 } 1690 1691 qed_fill_dev_info(cdev, &info->common); 1692 1693 if (IS_VF(cdev)) 1694 memset(info->common.hw_mac, 0, ETH_ALEN); 1695 1696 return 0; 1697 } 1698 1699 static void qed_register_eth_ops(struct qed_dev *cdev, 1700 struct qed_eth_cb_ops *ops, void *cookie) 1701 { 1702 cdev->protocol_ops.eth = ops; 1703 cdev->ops_cookie = cookie; 1704 1705 /* For VF, we start bulletin reading */ 1706 if (IS_VF(cdev)) 1707 qed_vf_start_iov_wq(cdev); 1708 } 1709 1710 static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) 1711 { 1712 if (IS_PF(cdev)) 1713 return true; 1714 1715 return qed_vf_check_mac(&cdev->hwfns[0], mac); 1716 } 1717 1718 static int qed_start_vport(struct qed_dev *cdev, 1719 struct qed_start_vport_params *params) 1720 { 1721 int rc, i; 1722 1723 for_each_hwfn(cdev, i) { 1724 struct qed_sp_vport_start_params start = { 0 }; 1725 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1726 1727 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : 1728 QED_TPA_MODE_NONE; 1729 start.remove_inner_vlan = params->remove_inner_vlan; 1730 start.only_untagged = true; /* untagged only */ 1731 start.drop_ttl0 = params->drop_ttl0; 1732 start.opaque_fid = p_hwfn->hw_info.opaque_fid; 1733 start.concrete_fid = p_hwfn->hw_info.concrete_fid; 1734 start.vport_id = params->vport_id; 1735 start.max_buffers_per_cqe = 16; 1736 start.mtu = params->mtu; 1737 1738 rc = qed_sp_vport_start(p_hwfn, &start); 1739 if (rc) { 1740 DP_ERR(cdev, "Failed to start VPORT\n"); 1741 return rc; 1742 } 1743 1744 qed_hw_start_fastpath(p_hwfn); 1745 1746 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1747 "Started V-PORT %d with MTU %d\n", 1748 start.vport_id, start.mtu); 1749 } 1750 1751 qed_reset_vport_stats(cdev); 1752 1753 return 0; 1754 } 1755 1756 static int qed_stop_vport(struct qed_dev *cdev, 1757 u8 vport_id) 1758 { 1759 int rc, i; 1760 1761 for_each_hwfn(cdev, i) { 1762 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1763 1764 rc = qed_sp_vport_stop(p_hwfn, 1765 p_hwfn->hw_info.opaque_fid, 1766 vport_id); 1767 1768 if (rc) { 1769 DP_ERR(cdev, "Failed to stop VPORT\n"); 1770 return rc; 1771 } 1772 } 1773 return 0; 1774 } 1775 1776 static int qed_update_vport(struct qed_dev *cdev, 1777 struct qed_update_vport_params *params) 1778 { 1779 struct qed_sp_vport_update_params sp_params; 1780 struct qed_rss_params sp_rss_params; 1781 int rc, i; 1782 1783 if (!cdev) 1784 return -ENODEV; 1785 1786 memset(&sp_params, 0, sizeof(sp_params)); 1787 memset(&sp_rss_params, 0, sizeof(sp_rss_params)); 1788 1789 /* Translate protocol params into sp params */ 1790 sp_params.vport_id = params->vport_id; 1791 sp_params.update_vport_active_rx_flg = 1792 params->update_vport_active_flg; 1793 sp_params.update_vport_active_tx_flg = 1794 params->update_vport_active_flg; 1795 sp_params.vport_active_rx_flg = params->vport_active_flg; 1796 sp_params.vport_active_tx_flg = params->vport_active_flg; 1797 sp_params.update_tx_switching_flg = params->update_tx_switching_flg; 1798 sp_params.tx_switching_flg = params->tx_switching_flg; 1799 sp_params.accept_any_vlan = params->accept_any_vlan; 1800 sp_params.update_accept_any_vlan_flg = 1801 params->update_accept_any_vlan_flg; 1802 1803 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns. 1804 * We need to re-fix the rss values per engine for CMT. 1805 */ 1806 if (cdev->num_hwfns > 1 && params->update_rss_flg) { 1807 struct qed_update_vport_rss_params *rss = 1808 ¶ms->rss_params; 1809 int k, max = 0; 1810 1811 /* Find largest entry, since it's possible RSS needs to 1812 * be disabled [in case only 1 queue per-hwfn] 1813 */ 1814 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1815 max = (max > rss->rss_ind_table[k]) ? 1816 max : rss->rss_ind_table[k]; 1817 1818 /* Either fix RSS values or disable RSS */ 1819 if (cdev->num_hwfns < max + 1) { 1820 int divisor = (max + cdev->num_hwfns - 1) / 1821 cdev->num_hwfns; 1822 1823 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1824 "CMT - fixing RSS values (modulo %02x)\n", 1825 divisor); 1826 1827 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1828 rss->rss_ind_table[k] = 1829 rss->rss_ind_table[k] % divisor; 1830 } else { 1831 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1832 "CMT - 1 queue per-hwfn; Disabling RSS\n"); 1833 params->update_rss_flg = 0; 1834 } 1835 } 1836 1837 /* Now, update the RSS configuration for actual configuration */ 1838 if (params->update_rss_flg) { 1839 sp_rss_params.update_rss_config = 1; 1840 sp_rss_params.rss_enable = 1; 1841 sp_rss_params.update_rss_capabilities = 1; 1842 sp_rss_params.update_rss_ind_table = 1; 1843 sp_rss_params.update_rss_key = 1; 1844 sp_rss_params.rss_caps = params->rss_params.rss_caps; 1845 sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */ 1846 memcpy(sp_rss_params.rss_ind_table, 1847 params->rss_params.rss_ind_table, 1848 QED_RSS_IND_TABLE_SIZE * sizeof(u16)); 1849 memcpy(sp_rss_params.rss_key, params->rss_params.rss_key, 1850 QED_RSS_KEY_SIZE * sizeof(u32)); 1851 } 1852 sp_params.rss_params = &sp_rss_params; 1853 1854 for_each_hwfn(cdev, i) { 1855 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1856 1857 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1858 rc = qed_sp_vport_update(p_hwfn, &sp_params, 1859 QED_SPQ_MODE_EBLOCK, 1860 NULL); 1861 if (rc) { 1862 DP_ERR(cdev, "Failed to update VPORT\n"); 1863 return rc; 1864 } 1865 1866 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1867 "Updated V-PORT %d: active_flag %d [update %d]\n", 1868 params->vport_id, params->vport_active_flg, 1869 params->update_vport_active_flg); 1870 } 1871 1872 return 0; 1873 } 1874 1875 static int qed_start_rxq(struct qed_dev *cdev, 1876 struct qed_queue_start_common_params *params, 1877 u16 bd_max_bytes, 1878 dma_addr_t bd_chain_phys_addr, 1879 dma_addr_t cqe_pbl_addr, 1880 u16 cqe_pbl_size, 1881 void __iomem **pp_prod) 1882 { 1883 int rc, hwfn_index; 1884 struct qed_hwfn *p_hwfn; 1885 1886 hwfn_index = params->rss_id % cdev->num_hwfns; 1887 p_hwfn = &cdev->hwfns[hwfn_index]; 1888 1889 /* Fix queue ID in 100g mode */ 1890 params->queue_id /= cdev->num_hwfns; 1891 1892 rc = qed_sp_eth_rx_queue_start(p_hwfn, 1893 p_hwfn->hw_info.opaque_fid, 1894 params, 1895 bd_max_bytes, 1896 bd_chain_phys_addr, 1897 cqe_pbl_addr, 1898 cqe_pbl_size, 1899 pp_prod); 1900 1901 if (rc) { 1902 DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id); 1903 return rc; 1904 } 1905 1906 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1907 "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1908 params->queue_id, params->rss_id, params->vport_id, 1909 params->sb); 1910 1911 return 0; 1912 } 1913 1914 static int qed_stop_rxq(struct qed_dev *cdev, 1915 struct qed_stop_rxq_params *params) 1916 { 1917 int rc, hwfn_index; 1918 struct qed_hwfn *p_hwfn; 1919 1920 hwfn_index = params->rss_id % cdev->num_hwfns; 1921 p_hwfn = &cdev->hwfns[hwfn_index]; 1922 1923 rc = qed_sp_eth_rx_queue_stop(p_hwfn, 1924 params->rx_queue_id / cdev->num_hwfns, 1925 params->eq_completion_only, 1926 false); 1927 if (rc) { 1928 DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id); 1929 return rc; 1930 } 1931 1932 return 0; 1933 } 1934 1935 static int qed_start_txq(struct qed_dev *cdev, 1936 struct qed_queue_start_common_params *p_params, 1937 dma_addr_t pbl_addr, 1938 u16 pbl_size, 1939 void __iomem **pp_doorbell) 1940 { 1941 struct qed_hwfn *p_hwfn; 1942 int rc, hwfn_index; 1943 1944 hwfn_index = p_params->rss_id % cdev->num_hwfns; 1945 p_hwfn = &cdev->hwfns[hwfn_index]; 1946 1947 /* Fix queue ID in 100g mode */ 1948 p_params->queue_id /= cdev->num_hwfns; 1949 1950 rc = qed_sp_eth_tx_queue_start(p_hwfn, 1951 p_hwfn->hw_info.opaque_fid, 1952 p_params, 1953 pbl_addr, 1954 pbl_size, 1955 pp_doorbell); 1956 1957 if (rc) { 1958 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 1959 return rc; 1960 } 1961 1962 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1963 "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1964 p_params->queue_id, p_params->rss_id, p_params->vport_id, 1965 p_params->sb); 1966 1967 return 0; 1968 } 1969 1970 #define QED_HW_STOP_RETRY_LIMIT (10) 1971 static int qed_fastpath_stop(struct qed_dev *cdev) 1972 { 1973 qed_hw_stop_fastpath(cdev); 1974 1975 return 0; 1976 } 1977 1978 static int qed_stop_txq(struct qed_dev *cdev, 1979 struct qed_stop_txq_params *params) 1980 { 1981 struct qed_hwfn *p_hwfn; 1982 int rc, hwfn_index; 1983 1984 hwfn_index = params->rss_id % cdev->num_hwfns; 1985 p_hwfn = &cdev->hwfns[hwfn_index]; 1986 1987 rc = qed_sp_eth_tx_queue_stop(p_hwfn, 1988 params->tx_queue_id / cdev->num_hwfns); 1989 if (rc) { 1990 DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id); 1991 return rc; 1992 } 1993 1994 return 0; 1995 } 1996 1997 static int qed_tunn_configure(struct qed_dev *cdev, 1998 struct qed_tunn_params *tunn_params) 1999 { 2000 struct qed_tunn_update_params tunn_info; 2001 int i, rc; 2002 2003 if (IS_VF(cdev)) 2004 return 0; 2005 2006 memset(&tunn_info, 0, sizeof(tunn_info)); 2007 if (tunn_params->update_vxlan_port == 1) { 2008 tunn_info.update_vxlan_udp_port = 1; 2009 tunn_info.vxlan_udp_port = tunn_params->vxlan_port; 2010 } 2011 2012 if (tunn_params->update_geneve_port == 1) { 2013 tunn_info.update_geneve_udp_port = 1; 2014 tunn_info.geneve_udp_port = tunn_params->geneve_port; 2015 } 2016 2017 for_each_hwfn(cdev, i) { 2018 struct qed_hwfn *hwfn = &cdev->hwfns[i]; 2019 2020 rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info, 2021 QED_SPQ_MODE_EBLOCK, NULL); 2022 2023 if (rc) 2024 return rc; 2025 } 2026 2027 return 0; 2028 } 2029 2030 static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 2031 enum qed_filter_rx_mode_type type) 2032 { 2033 struct qed_filter_accept_flags accept_flags; 2034 2035 memset(&accept_flags, 0, sizeof(accept_flags)); 2036 2037 accept_flags.update_rx_mode_config = 1; 2038 accept_flags.update_tx_mode_config = 1; 2039 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2040 QED_ACCEPT_MCAST_MATCHED | 2041 QED_ACCEPT_BCAST; 2042 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2043 QED_ACCEPT_MCAST_MATCHED | 2044 QED_ACCEPT_BCAST; 2045 2046 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) 2047 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 2048 QED_ACCEPT_MCAST_UNMATCHED; 2049 else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) 2050 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 2051 2052 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 2053 QED_SPQ_MODE_CB, NULL); 2054 } 2055 2056 static int qed_configure_filter_ucast(struct qed_dev *cdev, 2057 struct qed_filter_ucast_params *params) 2058 { 2059 struct qed_filter_ucast ucast; 2060 2061 if (!params->vlan_valid && !params->mac_valid) { 2062 DP_NOTICE( 2063 cdev, 2064 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 2065 return -EINVAL; 2066 } 2067 2068 memset(&ucast, 0, sizeof(ucast)); 2069 switch (params->type) { 2070 case QED_FILTER_XCAST_TYPE_ADD: 2071 ucast.opcode = QED_FILTER_ADD; 2072 break; 2073 case QED_FILTER_XCAST_TYPE_DEL: 2074 ucast.opcode = QED_FILTER_REMOVE; 2075 break; 2076 case QED_FILTER_XCAST_TYPE_REPLACE: 2077 ucast.opcode = QED_FILTER_REPLACE; 2078 break; 2079 default: 2080 DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 2081 params->type); 2082 } 2083 2084 if (params->vlan_valid && params->mac_valid) { 2085 ucast.type = QED_FILTER_MAC_VLAN; 2086 ether_addr_copy(ucast.mac, params->mac); 2087 ucast.vlan = params->vlan; 2088 } else if (params->mac_valid) { 2089 ucast.type = QED_FILTER_MAC; 2090 ether_addr_copy(ucast.mac, params->mac); 2091 } else { 2092 ucast.type = QED_FILTER_VLAN; 2093 ucast.vlan = params->vlan; 2094 } 2095 2096 ucast.is_rx_filter = true; 2097 ucast.is_tx_filter = true; 2098 2099 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 2100 } 2101 2102 static int qed_configure_filter_mcast(struct qed_dev *cdev, 2103 struct qed_filter_mcast_params *params) 2104 { 2105 struct qed_filter_mcast mcast; 2106 int i; 2107 2108 memset(&mcast, 0, sizeof(mcast)); 2109 switch (params->type) { 2110 case QED_FILTER_XCAST_TYPE_ADD: 2111 mcast.opcode = QED_FILTER_ADD; 2112 break; 2113 case QED_FILTER_XCAST_TYPE_DEL: 2114 mcast.opcode = QED_FILTER_REMOVE; 2115 break; 2116 default: 2117 DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 2118 params->type); 2119 } 2120 2121 mcast.num_mc_addrs = params->num; 2122 for (i = 0; i < mcast.num_mc_addrs; i++) 2123 ether_addr_copy(mcast.mac[i], params->mac[i]); 2124 2125 return qed_filter_mcast_cmd(cdev, &mcast, 2126 QED_SPQ_MODE_CB, NULL); 2127 } 2128 2129 static int qed_configure_filter(struct qed_dev *cdev, 2130 struct qed_filter_params *params) 2131 { 2132 enum qed_filter_rx_mode_type accept_flags; 2133 2134 switch (params->type) { 2135 case QED_FILTER_TYPE_UCAST: 2136 return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 2137 case QED_FILTER_TYPE_MCAST: 2138 return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 2139 case QED_FILTER_TYPE_RX_MODE: 2140 accept_flags = params->filter.accept_flags; 2141 return qed_configure_filter_rx_mode(cdev, accept_flags); 2142 default: 2143 DP_NOTICE(cdev, "Unknown filter type %d\n", 2144 (int)params->type); 2145 return -EINVAL; 2146 } 2147 } 2148 2149 static int qed_fp_cqe_completion(struct qed_dev *dev, 2150 u8 rss_id, 2151 struct eth_slow_path_rx_cqe *cqe) 2152 { 2153 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 2154 cqe); 2155 } 2156 2157 #ifdef CONFIG_QED_SRIOV 2158 extern const struct qed_iov_hv_ops qed_iov_ops_pass; 2159 #endif 2160 2161 static const struct qed_eth_ops qed_eth_ops_pass = { 2162 .common = &qed_common_ops_pass, 2163 #ifdef CONFIG_QED_SRIOV 2164 .iov = &qed_iov_ops_pass, 2165 #endif 2166 .fill_dev_info = &qed_fill_eth_dev_info, 2167 .register_ops = &qed_register_eth_ops, 2168 .check_mac = &qed_check_mac, 2169 .vport_start = &qed_start_vport, 2170 .vport_stop = &qed_stop_vport, 2171 .vport_update = &qed_update_vport, 2172 .q_rx_start = &qed_start_rxq, 2173 .q_rx_stop = &qed_stop_rxq, 2174 .q_tx_start = &qed_start_txq, 2175 .q_tx_stop = &qed_stop_txq, 2176 .filter_config = &qed_configure_filter, 2177 .fastpath_stop = &qed_fastpath_stop, 2178 .eth_cqe_completion = &qed_fp_cqe_completion, 2179 .get_vport_stats = &qed_get_vport_stats, 2180 .tunn_config = &qed_tunn_configure, 2181 }; 2182 2183 const struct qed_eth_ops *qed_get_eth_ops(void) 2184 { 2185 return &qed_eth_ops_pass; 2186 } 2187 EXPORT_SYMBOL(qed_get_eth_ops); 2188 2189 void qed_put_eth_ops(void) 2190 { 2191 /* TODO - reference count for module? */ 2192 } 2193 EXPORT_SYMBOL(qed_put_eth_ops); 2194