125c089d7SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 325c089d7SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 3125c089d7SYuval Mintz */ 3225c089d7SYuval Mintz 3325c089d7SYuval Mintz #include <linux/types.h> 3425c089d7SYuval Mintz #include <asm/byteorder.h> 3525c089d7SYuval Mintz #include <asm/param.h> 3625c089d7SYuval Mintz #include <linux/delay.h> 3725c089d7SYuval Mintz #include <linux/dma-mapping.h> 3825c089d7SYuval Mintz #include <linux/etherdevice.h> 3925c089d7SYuval Mintz #include <linux/interrupt.h> 4025c089d7SYuval Mintz #include <linux/kernel.h> 4125c089d7SYuval Mintz #include <linux/module.h> 4225c089d7SYuval Mintz #include <linux/pci.h> 4325c089d7SYuval Mintz #include <linux/slab.h> 4425c089d7SYuval Mintz #include <linux/stddef.h> 4525c089d7SYuval Mintz #include <linux/string.h> 4625c089d7SYuval Mintz #include <linux/workqueue.h> 4725c089d7SYuval Mintz #include <linux/bitops.h> 4825c089d7SYuval Mintz #include <linux/bug.h> 493da7a37aSMintz, Yuval #include <linux/vmalloc.h> 5025c089d7SYuval Mintz #include "qed.h" 5125c089d7SYuval Mintz #include <linux/qed/qed_chain.h> 5225c089d7SYuval Mintz #include "qed_cxt.h" 5325c089d7SYuval Mintz #include "qed_dev_api.h" 5425c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h> 5525c089d7SYuval Mintz #include "qed_hsi.h" 5625c089d7SYuval Mintz #include "qed_hw.h" 5725c089d7SYuval Mintz #include "qed_int.h" 58dacd88d6SYuval Mintz #include "qed_l2.h" 5986622ee7SYuval Mintz #include "qed_mcp.h" 6025c089d7SYuval Mintz #include "qed_reg_addr.h" 6125c089d7SYuval Mintz #include "qed_sp.h" 621408cc1fSYuval Mintz #include "qed_sriov.h" 6325c089d7SYuval Mintz 64088c8618SManish Chopra 65cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16 66cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41 67cee4d264SManish Chopra 680db711bbSMintz, Yuval struct qed_l2_info { 690db711bbSMintz, Yuval u32 queues; 700db711bbSMintz, Yuval unsigned long **pp_qid_usage; 710db711bbSMintz, Yuval 720db711bbSMintz, Yuval /* The lock is meant to synchronize access to the qid usage */ 730db711bbSMintz, Yuval struct mutex lock; 740db711bbSMintz, Yuval }; 750db711bbSMintz, Yuval 760db711bbSMintz, Yuval int qed_l2_alloc(struct qed_hwfn *p_hwfn) 770db711bbSMintz, Yuval { 780db711bbSMintz, Yuval struct qed_l2_info *p_l2_info; 790db711bbSMintz, Yuval unsigned long **pp_qids; 800db711bbSMintz, Yuval u32 i; 810db711bbSMintz, Yuval 82c851a9dcSKalderon, Michal if (!QED_IS_L2_PERSONALITY(p_hwfn)) 830db711bbSMintz, Yuval return 0; 840db711bbSMintz, Yuval 850db711bbSMintz, Yuval p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL); 860db711bbSMintz, Yuval if (!p_l2_info) 870db711bbSMintz, Yuval return -ENOMEM; 880db711bbSMintz, Yuval p_hwfn->p_l2_info = p_l2_info; 890db711bbSMintz, Yuval 900db711bbSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 910db711bbSMintz, Yuval p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE); 920db711bbSMintz, Yuval } else { 930db711bbSMintz, Yuval u8 rx = 0, tx = 0; 940db711bbSMintz, Yuval 950db711bbSMintz, Yuval qed_vf_get_num_rxqs(p_hwfn, &rx); 960db711bbSMintz, Yuval qed_vf_get_num_txqs(p_hwfn, &tx); 970db711bbSMintz, Yuval 980db711bbSMintz, Yuval p_l2_info->queues = max_t(u8, rx, tx); 990db711bbSMintz, Yuval } 1000db711bbSMintz, Yuval 1016396bb22SKees Cook pp_qids = kcalloc(p_l2_info->queues, sizeof(unsigned long *), 1020db711bbSMintz, Yuval GFP_KERNEL); 1030db711bbSMintz, Yuval if (!pp_qids) 1040db711bbSMintz, Yuval return -ENOMEM; 1050db711bbSMintz, Yuval p_l2_info->pp_qid_usage = pp_qids; 1060db711bbSMintz, Yuval 1070db711bbSMintz, Yuval for (i = 0; i < p_l2_info->queues; i++) { 1080db711bbSMintz, Yuval pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL); 1090db711bbSMintz, Yuval if (!pp_qids[i]) 1100db711bbSMintz, Yuval return -ENOMEM; 1110db711bbSMintz, Yuval } 1120db711bbSMintz, Yuval 1130db711bbSMintz, Yuval return 0; 1140db711bbSMintz, Yuval } 1150db711bbSMintz, Yuval 1160db711bbSMintz, Yuval void qed_l2_setup(struct qed_hwfn *p_hwfn) 1170db711bbSMintz, Yuval { 118af6858eeSMichal Kalderon if (!QED_IS_L2_PERSONALITY(p_hwfn)) 1190db711bbSMintz, Yuval return; 1200db711bbSMintz, Yuval 1210db711bbSMintz, Yuval mutex_init(&p_hwfn->p_l2_info->lock); 1220db711bbSMintz, Yuval } 1230db711bbSMintz, Yuval 1240db711bbSMintz, Yuval void qed_l2_free(struct qed_hwfn *p_hwfn) 1250db711bbSMintz, Yuval { 1260db711bbSMintz, Yuval u32 i; 1270db711bbSMintz, Yuval 128af6858eeSMichal Kalderon if (!QED_IS_L2_PERSONALITY(p_hwfn)) 1290db711bbSMintz, Yuval return; 1300db711bbSMintz, Yuval 1310db711bbSMintz, Yuval if (!p_hwfn->p_l2_info) 1320db711bbSMintz, Yuval return; 1330db711bbSMintz, Yuval 1340db711bbSMintz, Yuval if (!p_hwfn->p_l2_info->pp_qid_usage) 1350db711bbSMintz, Yuval goto out_l2_info; 1360db711bbSMintz, Yuval 1370db711bbSMintz, Yuval /* Free until hit first uninitialized entry */ 1380db711bbSMintz, Yuval for (i = 0; i < p_hwfn->p_l2_info->queues; i++) { 1390db711bbSMintz, Yuval if (!p_hwfn->p_l2_info->pp_qid_usage[i]) 1400db711bbSMintz, Yuval break; 1410db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info->pp_qid_usage[i]); 1420db711bbSMintz, Yuval } 1430db711bbSMintz, Yuval 1440db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info->pp_qid_usage); 1450db711bbSMintz, Yuval 1460db711bbSMintz, Yuval out_l2_info: 1470db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info); 1480db711bbSMintz, Yuval p_hwfn->p_l2_info = NULL; 1490db711bbSMintz, Yuval } 1500db711bbSMintz, Yuval 151bbe3f233SMintz, Yuval static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn, 152bbe3f233SMintz, Yuval struct qed_queue_cid *p_cid) 153bbe3f233SMintz, Yuval { 154bbe3f233SMintz, Yuval struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info; 155bbe3f233SMintz, Yuval u16 queue_id = p_cid->rel.queue_id; 156bbe3f233SMintz, Yuval bool b_rc = true; 157bbe3f233SMintz, Yuval u8 first; 158bbe3f233SMintz, Yuval 159bbe3f233SMintz, Yuval mutex_lock(&p_l2_info->lock); 160bbe3f233SMintz, Yuval 1610331402aSDan Carpenter if (queue_id >= p_l2_info->queues) { 162bbe3f233SMintz, Yuval DP_NOTICE(p_hwfn, 163bbe3f233SMintz, Yuval "Requested to increase usage for qzone %04x out of %08x\n", 164bbe3f233SMintz, Yuval queue_id, p_l2_info->queues); 165bbe3f233SMintz, Yuval b_rc = false; 166bbe3f233SMintz, Yuval goto out; 167bbe3f233SMintz, Yuval } 168bbe3f233SMintz, Yuval 169bbe3f233SMintz, Yuval first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id], 170bbe3f233SMintz, Yuval MAX_QUEUES_PER_QZONE); 171bbe3f233SMintz, Yuval if (first >= MAX_QUEUES_PER_QZONE) { 172bbe3f233SMintz, Yuval b_rc = false; 173bbe3f233SMintz, Yuval goto out; 174bbe3f233SMintz, Yuval } 175bbe3f233SMintz, Yuval 176bbe3f233SMintz, Yuval __set_bit(first, p_l2_info->pp_qid_usage[queue_id]); 177bbe3f233SMintz, Yuval p_cid->qid_usage_idx = first; 178bbe3f233SMintz, Yuval 179bbe3f233SMintz, Yuval out: 180bbe3f233SMintz, Yuval mutex_unlock(&p_l2_info->lock); 181bbe3f233SMintz, Yuval return b_rc; 182bbe3f233SMintz, Yuval } 183bbe3f233SMintz, Yuval 184bbe3f233SMintz, Yuval static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn, 185bbe3f233SMintz, Yuval struct qed_queue_cid *p_cid) 186bbe3f233SMintz, Yuval { 187bbe3f233SMintz, Yuval mutex_lock(&p_hwfn->p_l2_info->lock); 188bbe3f233SMintz, Yuval 189bbe3f233SMintz, Yuval clear_bit(p_cid->qid_usage_idx, 190bbe3f233SMintz, Yuval p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]); 191bbe3f233SMintz, Yuval 192bbe3f233SMintz, Yuval mutex_unlock(&p_hwfn->p_l2_info->lock); 193bbe3f233SMintz, Yuval } 194bbe3f233SMintz, Yuval 1953da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn, 1963da7a37aSMintz, Yuval struct qed_queue_cid *p_cid) 1973da7a37aSMintz, Yuval { 19808bc8f15SMintz, Yuval bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID); 19908bc8f15SMintz, Yuval 20008bc8f15SMintz, Yuval if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) 20108bc8f15SMintz, Yuval _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid); 202bbe3f233SMintz, Yuval 203bbe3f233SMintz, Yuval /* For PF's VFs we maintain the index inside queue-zone in IOV */ 204bbe3f233SMintz, Yuval if (p_cid->vfid == QED_QUEUE_CID_SELF) 205bbe3f233SMintz, Yuval qed_eth_queue_qid_usage_del(p_hwfn, p_cid); 206bbe3f233SMintz, Yuval 2073da7a37aSMintz, Yuval vfree(p_cid); 2083da7a37aSMintz, Yuval } 2093da7a37aSMintz, Yuval 2103da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs 2113da7a37aSMintz, Yuval * for their VFs. 2123da7a37aSMintz, Yuval */ 2133946497aSMintz, Yuval static struct qed_queue_cid * 2143da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 2153da7a37aSMintz, Yuval u16 opaque_fid, 2163da7a37aSMintz, Yuval u32 cid, 2173946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 218007bc371SMintz, Yuval bool b_is_rx, 2193946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params) 2203da7a37aSMintz, Yuval { 2213da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 2223da7a37aSMintz, Yuval int rc; 2233da7a37aSMintz, Yuval 2245f58dff9SHimanshu Jha p_cid = vzalloc(sizeof(*p_cid)); 2253da7a37aSMintz, Yuval if (!p_cid) 2263da7a37aSMintz, Yuval return NULL; 2273da7a37aSMintz, Yuval 2283da7a37aSMintz, Yuval p_cid->opaque_fid = opaque_fid; 2293da7a37aSMintz, Yuval p_cid->cid = cid; 230f29ffdb6SMintz, Yuval p_cid->p_owner = p_hwfn; 2313da7a37aSMintz, Yuval 232f604b17dSMintz, Yuval /* Fill in parameters */ 233f604b17dSMintz, Yuval p_cid->rel.vport_id = p_params->vport_id; 234f604b17dSMintz, Yuval p_cid->rel.queue_id = p_params->queue_id; 235f604b17dSMintz, Yuval p_cid->rel.stats_id = p_params->stats_id; 236f604b17dSMintz, Yuval p_cid->sb_igu_id = p_params->p_sb->igu_sb_id; 237007bc371SMintz, Yuval p_cid->b_is_rx = b_is_rx; 238f604b17dSMintz, Yuval p_cid->sb_idx = p_params->sb_idx; 239f604b17dSMintz, Yuval 2403946497aSMintz, Yuval /* Fill-in bits related to VFs' queues if information was provided */ 2413946497aSMintz, Yuval if (p_vf_params) { 2423946497aSMintz, Yuval p_cid->vfid = p_vf_params->vfid; 2433946497aSMintz, Yuval p_cid->vf_qid = p_vf_params->vf_qid; 2443b19f478SMintz, Yuval p_cid->vf_legacy = p_vf_params->vf_legacy; 2453946497aSMintz, Yuval } else { 2463946497aSMintz, Yuval p_cid->vfid = QED_QUEUE_CID_SELF; 2473946497aSMintz, Yuval } 2483946497aSMintz, Yuval 2493da7a37aSMintz, Yuval /* Don't try calculating the absolute indices for VFs */ 2503da7a37aSMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 2513da7a37aSMintz, Yuval p_cid->abs = p_cid->rel; 2523da7a37aSMintz, Yuval goto out; 2533da7a37aSMintz, Yuval } 2543da7a37aSMintz, Yuval 2553da7a37aSMintz, Yuval /* Calculate the engine-absolute indices of the resources. 2563da7a37aSMintz, Yuval * This would guarantee they're valid later on. 2573da7a37aSMintz, Yuval * In some cases [SBs] we already have the right values. 2583da7a37aSMintz, Yuval */ 2593da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id); 2603da7a37aSMintz, Yuval if (rc) 2613da7a37aSMintz, Yuval goto fail; 2623da7a37aSMintz, Yuval 2633da7a37aSMintz, Yuval rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id); 2643da7a37aSMintz, Yuval if (rc) 2653da7a37aSMintz, Yuval goto fail; 2663da7a37aSMintz, Yuval 2673da7a37aSMintz, Yuval /* In case of a PF configuring its VF's queues, the stats-id is already 2683da7a37aSMintz, Yuval * absolute [since there's a single index that's suitable per-VF]. 2693da7a37aSMintz, Yuval */ 2703946497aSMintz, Yuval if (p_cid->vfid == QED_QUEUE_CID_SELF) { 2713da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id, 2723da7a37aSMintz, Yuval &p_cid->abs.stats_id); 2733da7a37aSMintz, Yuval if (rc) 2743da7a37aSMintz, Yuval goto fail; 2753da7a37aSMintz, Yuval } else { 2763da7a37aSMintz, Yuval p_cid->abs.stats_id = p_cid->rel.stats_id; 2773da7a37aSMintz, Yuval } 2783da7a37aSMintz, Yuval 2793da7a37aSMintz, Yuval out: 280bbe3f233SMintz, Yuval /* VF-images have provided the qid_usage_idx on their own. 281bbe3f233SMintz, Yuval * Otherwise, we need to allocate a unique one. 282bbe3f233SMintz, Yuval */ 283bbe3f233SMintz, Yuval if (!p_vf_params) { 284bbe3f233SMintz, Yuval if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid)) 285bbe3f233SMintz, Yuval goto fail; 286bbe3f233SMintz, Yuval } else { 287bbe3f233SMintz, Yuval p_cid->qid_usage_idx = p_vf_params->qid_usage_idx; 288bbe3f233SMintz, Yuval } 289bbe3f233SMintz, Yuval 2903da7a37aSMintz, Yuval DP_VERBOSE(p_hwfn, 2913da7a37aSMintz, Yuval QED_MSG_SP, 292bbe3f233SMintz, Yuval "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n", 2933da7a37aSMintz, Yuval p_cid->opaque_fid, 2943da7a37aSMintz, Yuval p_cid->cid, 2953da7a37aSMintz, Yuval p_cid->rel.vport_id, 2963da7a37aSMintz, Yuval p_cid->abs.vport_id, 2973da7a37aSMintz, Yuval p_cid->rel.queue_id, 298bbe3f233SMintz, Yuval p_cid->qid_usage_idx, 2993da7a37aSMintz, Yuval p_cid->abs.queue_id, 3003da7a37aSMintz, Yuval p_cid->rel.stats_id, 301f604b17dSMintz, Yuval p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx); 3023da7a37aSMintz, Yuval 3033da7a37aSMintz, Yuval return p_cid; 3043da7a37aSMintz, Yuval 3053da7a37aSMintz, Yuval fail: 3063da7a37aSMintz, Yuval vfree(p_cid); 3073da7a37aSMintz, Yuval return NULL; 3083da7a37aSMintz, Yuval } 3093da7a37aSMintz, Yuval 3103946497aSMintz, Yuval struct qed_queue_cid * 3113946497aSMintz, Yuval qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 3123946497aSMintz, Yuval u16 opaque_fid, 3133946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 314007bc371SMintz, Yuval bool b_is_rx, 3153946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params) 3163da7a37aSMintz, Yuval { 3173da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 31808bc8f15SMintz, Yuval u8 vfid = QED_CXT_PF_CID; 3193946497aSMintz, Yuval bool b_legacy_vf = false; 3203da7a37aSMintz, Yuval u32 cid = 0; 3213da7a37aSMintz, Yuval 32208bc8f15SMintz, Yuval /* In case of legacy VFs, The CID can be derived from the additional 32308bc8f15SMintz, Yuval * VF parameters - the VF assumes queue X uses CID X, so we can simply 32408bc8f15SMintz, Yuval * use the vf_qid for this purpose as well. 32508bc8f15SMintz, Yuval */ 32608bc8f15SMintz, Yuval if (p_vf_params) { 32708bc8f15SMintz, Yuval vfid = p_vf_params->vfid; 32808bc8f15SMintz, Yuval 32908bc8f15SMintz, Yuval if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) { 3303946497aSMintz, Yuval b_legacy_vf = true; 33108bc8f15SMintz, Yuval cid = p_vf_params->vf_qid; 33208bc8f15SMintz, Yuval } 33308bc8f15SMintz, Yuval } 33408bc8f15SMintz, Yuval 3353da7a37aSMintz, Yuval /* Get a unique firmware CID for this queue, in case it's a PF. 3363da7a37aSMintz, Yuval * VF's don't need a CID as the queue configuration will be done 3373da7a37aSMintz, Yuval * by PF. 3383da7a37aSMintz, Yuval */ 3393946497aSMintz, Yuval if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) { 34008bc8f15SMintz, Yuval if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 34108bc8f15SMintz, Yuval &cid, vfid)) { 3423da7a37aSMintz, Yuval DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 3433da7a37aSMintz, Yuval return NULL; 3443da7a37aSMintz, Yuval } 3453da7a37aSMintz, Yuval } 3463da7a37aSMintz, Yuval 3473946497aSMintz, Yuval p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 348007bc371SMintz, Yuval p_params, b_is_rx, p_vf_params); 3493946497aSMintz, Yuval if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf) 35008bc8f15SMintz, Yuval _qed_cxt_release_cid(p_hwfn, cid, vfid); 3513da7a37aSMintz, Yuval 3523da7a37aSMintz, Yuval return p_cid; 3533da7a37aSMintz, Yuval } 3543da7a37aSMintz, Yuval 3553946497aSMintz, Yuval static struct qed_queue_cid * 3563946497aSMintz, Yuval qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn, 3573946497aSMintz, Yuval u16 opaque_fid, 358007bc371SMintz, Yuval bool b_is_rx, 3593946497aSMintz, Yuval struct qed_queue_start_common_params *p_params) 3603946497aSMintz, Yuval { 361007bc371SMintz, Yuval return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx, 3623946497aSMintz, Yuval NULL); 3633946497aSMintz, Yuval } 3643946497aSMintz, Yuval 365dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 366088c8618SManish Chopra struct qed_sp_vport_start_params *p_params) 367cee4d264SManish Chopra { 368cee4d264SManish Chopra struct vport_start_ramrod_data *p_ramrod = NULL; 369cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 37006f56b81SYuval Mintz struct qed_sp_init_data init_data; 371dacd88d6SYuval Mintz u8 abs_vport_id = 0; 372cee4d264SManish Chopra int rc = -EINVAL; 373cee4d264SManish Chopra u16 rx_mode = 0; 374cee4d264SManish Chopra 375088c8618SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 3761a635e48SYuval Mintz if (rc) 377cee4d264SManish Chopra return rc; 378cee4d264SManish Chopra 37906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 38006f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 381088c8618SManish Chopra init_data.opaque_fid = p_params->opaque_fid; 38206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 383cee4d264SManish Chopra 384cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 385cee4d264SManish Chopra ETH_RAMROD_VPORT_START, 38606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 387cee4d264SManish Chopra if (rc) 388cee4d264SManish Chopra return rc; 389cee4d264SManish Chopra 390cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_start; 391cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 392cee4d264SManish Chopra 393088c8618SManish Chopra p_ramrod->mtu = cpu_to_le16(p_params->mtu); 394c78c70faSSudarsana Reddy Kalluru p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts; 395088c8618SManish Chopra p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 396088c8618SManish Chopra p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 397e6bd8923SYuval Mintz p_ramrod->untagged = p_params->only_untagged; 398cee4d264SManish Chopra 399cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 400cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 401cee4d264SManish Chopra 402cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 403cee4d264SManish Chopra 404cee4d264SManish Chopra /* TPA related fields */ 4051a635e48SYuval Mintz memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param)); 406cee4d264SManish Chopra 407088c8618SManish Chopra p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; 408088c8618SManish Chopra 409088c8618SManish Chopra switch (p_params->tpa_mode) { 410088c8618SManish Chopra case QED_TPA_MODE_GRO: 411088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 412088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_size = (u16)-1; 413088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; 414088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; 415088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; 416088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; 417088c8618SManish Chopra p_ramrod->tpa_param.tpa_pkt_split_flg = 1; 418088c8618SManish Chopra p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; 419088c8618SManish Chopra break; 420088c8618SManish Chopra default: 421088c8618SManish Chopra break; 422088c8618SManish Chopra } 423088c8618SManish Chopra 424831bfb0eSYuval Mintz p_ramrod->tx_switching_en = p_params->tx_switching; 425831bfb0eSYuval Mintz 42611a85d75SYuval Mintz p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac; 42711a85d75SYuval Mintz p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype; 42811a85d75SYuval Mintz 429cee4d264SManish Chopra /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 430cee4d264SManish Chopra p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 431088c8618SManish Chopra p_params->concrete_fid); 432cee4d264SManish Chopra 433cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 434cee4d264SManish Chopra } 435cee4d264SManish Chopra 436ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 437dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params) 438dacd88d6SYuval Mintz { 439dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 440dacd88d6SYuval Mintz return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, 441dacd88d6SYuval Mintz p_params->mtu, 442dacd88d6SYuval Mintz p_params->remove_inner_vlan, 443dacd88d6SYuval Mintz p_params->tpa_mode, 44408feecd7SYuval Mintz p_params->max_buffers_per_cqe, 44508feecd7SYuval Mintz p_params->only_untagged); 446dacd88d6SYuval Mintz } 447dacd88d6SYuval Mintz 448dacd88d6SYuval Mintz return qed_sp_eth_vport_start(p_hwfn, p_params); 449dacd88d6SYuval Mintz } 450dacd88d6SYuval Mintz 451cee4d264SManish Chopra static int 452cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 453cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 454f29ffdb6SMintz, Yuval struct qed_rss_params *p_rss) 455cee4d264SManish Chopra { 456f29ffdb6SMintz, Yuval struct eth_vport_rss_config *p_config; 457f29ffdb6SMintz, Yuval u16 capabilities = 0; 458f29ffdb6SMintz, Yuval int i, table_size; 459f29ffdb6SMintz, Yuval int rc = 0; 460cee4d264SManish Chopra 461f29ffdb6SMintz, Yuval if (!p_rss) { 462cee4d264SManish Chopra p_ramrod->common.update_rss_flg = 0; 463cee4d264SManish Chopra return rc; 464cee4d264SManish Chopra } 465f29ffdb6SMintz, Yuval p_config = &p_ramrod->rss_config; 466cee4d264SManish Chopra 467f29ffdb6SMintz, Yuval BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM); 468cee4d264SManish Chopra 469f29ffdb6SMintz, Yuval rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id); 470cee4d264SManish Chopra if (rc) 471cee4d264SManish Chopra return rc; 472cee4d264SManish Chopra 473f29ffdb6SMintz, Yuval p_ramrod->common.update_rss_flg = p_rss->update_rss_config; 474f29ffdb6SMintz, Yuval p_config->update_rss_capabilities = p_rss->update_rss_capabilities; 475f29ffdb6SMintz, Yuval p_config->update_rss_ind_table = p_rss->update_rss_ind_table; 476f29ffdb6SMintz, Yuval p_config->update_rss_key = p_rss->update_rss_key; 477cee4d264SManish Chopra 478f29ffdb6SMintz, Yuval p_config->rss_mode = p_rss->rss_enable ? 479cee4d264SManish Chopra ETH_VPORT_RSS_MODE_REGULAR : 480cee4d264SManish Chopra ETH_VPORT_RSS_MODE_DISABLED; 481cee4d264SManish Chopra 482cee4d264SManish Chopra SET_FIELD(capabilities, 483cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 484f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4)); 485cee4d264SManish Chopra SET_FIELD(capabilities, 486cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 487f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6)); 488cee4d264SManish Chopra SET_FIELD(capabilities, 489cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 490f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_TCP)); 491cee4d264SManish Chopra SET_FIELD(capabilities, 492cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 493f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_TCP)); 494cee4d264SManish Chopra SET_FIELD(capabilities, 495cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 496f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_UDP)); 497cee4d264SManish Chopra SET_FIELD(capabilities, 498cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 499f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_UDP)); 500f29ffdb6SMintz, Yuval p_config->tbl_size = p_rss->rss_table_size_log; 501cee4d264SManish Chopra 502f29ffdb6SMintz, Yuval p_config->capabilities = cpu_to_le16(capabilities); 503cee4d264SManish Chopra 504cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 505cee4d264SManish Chopra "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 506cee4d264SManish Chopra p_ramrod->common.update_rss_flg, 507f29ffdb6SMintz, Yuval p_config->rss_mode, 508f29ffdb6SMintz, Yuval p_config->update_rss_capabilities, 509f29ffdb6SMintz, Yuval p_config->capabilities, 510f29ffdb6SMintz, Yuval p_config->update_rss_ind_table, p_config->update_rss_key); 511cee4d264SManish Chopra 512f29ffdb6SMintz, Yuval table_size = min_t(int, QED_RSS_IND_TABLE_SIZE, 513f29ffdb6SMintz, Yuval 1 << p_config->tbl_size); 514f29ffdb6SMintz, Yuval for (i = 0; i < table_size; i++) { 515f29ffdb6SMintz, Yuval struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i]; 516cee4d264SManish Chopra 517f29ffdb6SMintz, Yuval if (!p_queue) 518f29ffdb6SMintz, Yuval return -EINVAL; 519f29ffdb6SMintz, Yuval 520f29ffdb6SMintz, Yuval p_config->indirection_table[i] = 521f29ffdb6SMintz, Yuval cpu_to_le16(p_queue->abs.queue_id); 522f29ffdb6SMintz, Yuval } 523f29ffdb6SMintz, Yuval 524f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 525f29ffdb6SMintz, Yuval "Configured RSS indirection table [%d entries]:\n", 526f29ffdb6SMintz, Yuval table_size); 527f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) { 528f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, 529f29ffdb6SMintz, Yuval NETIF_MSG_IFUP, 530f29ffdb6SMintz, Yuval "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", 531f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i]), 532f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 1]), 533f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 2]), 534f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 3]), 535f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 4]), 536f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 5]), 537f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 6]), 538f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 7]), 539f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 8]), 540f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 9]), 541f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 10]), 542f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 11]), 543f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 12]), 544f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 13]), 545f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 14]), 546f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 15])); 547cee4d264SManish Chopra } 548cee4d264SManish Chopra 549cee4d264SManish Chopra for (i = 0; i < 10; i++) 550f29ffdb6SMintz, Yuval p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]); 551cee4d264SManish Chopra 552cee4d264SManish Chopra return rc; 553cee4d264SManish Chopra } 554cee4d264SManish Chopra 555cee4d264SManish Chopra static void 556cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 557cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 558cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags) 559cee4d264SManish Chopra { 560cee4d264SManish Chopra p_ramrod->common.update_rx_mode_flg = 561cee4d264SManish Chopra accept_flags.update_rx_mode_config; 562cee4d264SManish Chopra 563cee4d264SManish Chopra p_ramrod->common.update_tx_mode_flg = 564cee4d264SManish Chopra accept_flags.update_tx_mode_config; 565cee4d264SManish Chopra 566cee4d264SManish Chopra /* Set Rx mode accept flags */ 567cee4d264SManish Chopra if (p_ramrod->common.update_rx_mode_flg) { 568cee4d264SManish Chopra u8 accept_filter = accept_flags.rx_accept_filter; 569cee4d264SManish Chopra u16 state = 0; 570cee4d264SManish Chopra 571cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 572cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 573cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 574cee4d264SManish Chopra 575cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 576cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 577cee4d264SManish Chopra 578cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 579cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 580cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 581cee4d264SManish Chopra 582cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 583cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 584cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 585cee4d264SManish Chopra 586cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 587cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 588cee4d264SManish Chopra 589d52c89f1SMichal Kalderon SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI, 590d52c89f1SMichal Kalderon !!(accept_filter & QED_ACCEPT_ANY_VNI)); 591d52c89f1SMichal Kalderon 592cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(state); 593cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 594cee4d264SManish Chopra "p_ramrod->rx_mode.state = 0x%x\n", state); 595cee4d264SManish Chopra } 596cee4d264SManish Chopra 597cee4d264SManish Chopra /* Set Tx mode accept flags */ 598cee4d264SManish Chopra if (p_ramrod->common.update_tx_mode_flg) { 599cee4d264SManish Chopra u8 accept_filter = accept_flags.tx_accept_filter; 600cee4d264SManish Chopra u16 state = 0; 601cee4d264SManish Chopra 602cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 603cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 604cee4d264SManish Chopra 605cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 606cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 607cee4d264SManish Chopra 608cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 609cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 610cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 611cee4d264SManish Chopra 6129e71a15dSManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL, 6139e71a15dSManish Chopra (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) && 6149e71a15dSManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 6159e71a15dSManish Chopra 616cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 617cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 618cee4d264SManish Chopra 619cee4d264SManish Chopra p_ramrod->tx_mode.state = cpu_to_le16(state); 620cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 621cee4d264SManish Chopra "p_ramrod->tx_mode.state = 0x%x\n", state); 622cee4d264SManish Chopra } 623cee4d264SManish Chopra } 624cee4d264SManish Chopra 625cee4d264SManish Chopra static void 62617b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, 62717b235c1SYuval Mintz struct vport_update_ramrod_data *p_ramrod, 62817b235c1SYuval Mintz struct qed_sge_tpa_params *p_params) 62917b235c1SYuval Mintz { 63017b235c1SYuval Mintz struct eth_vport_tpa_param *p_tpa; 63117b235c1SYuval Mintz 63217b235c1SYuval Mintz if (!p_params) { 63317b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 63417b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = 0; 63517b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 63617b235c1SYuval Mintz return; 63717b235c1SYuval Mintz } 63817b235c1SYuval Mintz 63917b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; 64017b235c1SYuval Mintz p_tpa = &p_ramrod->tpa_param; 64117b235c1SYuval Mintz p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; 64217b235c1SYuval Mintz p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; 64317b235c1SYuval Mintz p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; 64417b235c1SYuval Mintz p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; 64517b235c1SYuval Mintz 64617b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; 64717b235c1SYuval Mintz p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 64817b235c1SYuval Mintz p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; 64917b235c1SYuval Mintz p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; 65017b235c1SYuval Mintz p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; 65117b235c1SYuval Mintz p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; 65217b235c1SYuval Mintz p_tpa->tpa_max_size = p_params->tpa_max_size; 65317b235c1SYuval Mintz p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; 65417b235c1SYuval Mintz p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; 65517b235c1SYuval Mintz } 65617b235c1SYuval Mintz 65717b235c1SYuval Mintz static void 658cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 659cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 660cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params) 661cee4d264SManish Chopra { 662cee4d264SManish Chopra int i; 663cee4d264SManish Chopra 664cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 665cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 666cee4d264SManish Chopra 66783aeb933SYuval Mintz if (!p_params->update_approx_mcast_flg) 66883aeb933SYuval Mintz return; 66983aeb933SYuval Mintz 670cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 671cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 67225c020a9SSudarsana Reddy Kalluru u32 *p_bins = p_params->bins; 673cee4d264SManish Chopra 67483aeb933SYuval Mintz p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]); 675cee4d264SManish Chopra } 676cee4d264SManish Chopra } 677cee4d264SManish Chopra 678dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 679cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params, 680cee4d264SManish Chopra enum spq_mode comp_mode, 681cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 682cee4d264SManish Chopra { 683cee4d264SManish Chopra struct qed_rss_params *p_rss_params = p_params->rss_params; 684cee4d264SManish Chopra struct vport_update_ramrod_data_cmn *p_cmn; 68506f56b81SYuval Mintz struct qed_sp_init_data init_data; 686cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 687cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 68817b235c1SYuval Mintz u8 abs_vport_id = 0, val; 689cee4d264SManish Chopra int rc = -EINVAL; 690cee4d264SManish Chopra 691dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 692dacd88d6SYuval Mintz rc = qed_vf_pf_vport_update(p_hwfn, p_params); 693dacd88d6SYuval Mintz return rc; 694dacd88d6SYuval Mintz } 695dacd88d6SYuval Mintz 696cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 6971a635e48SYuval Mintz if (rc) 698cee4d264SManish Chopra return rc; 699cee4d264SManish Chopra 70006f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 70106f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 70206f56b81SYuval Mintz init_data.opaque_fid = p_params->opaque_fid; 70306f56b81SYuval Mintz init_data.comp_mode = comp_mode; 70406f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 705cee4d264SManish Chopra 706cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 707cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 70806f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 709cee4d264SManish Chopra if (rc) 710cee4d264SManish Chopra return rc; 711cee4d264SManish Chopra 712cee4d264SManish Chopra /* Copy input params to ramrod according to FW struct */ 713cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 714cee4d264SManish Chopra p_cmn = &p_ramrod->common; 715cee4d264SManish Chopra 716cee4d264SManish Chopra p_cmn->vport_id = abs_vport_id; 717cee4d264SManish Chopra p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 718cee4d264SManish Chopra p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 719cee4d264SManish Chopra p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 720cee4d264SManish Chopra p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 7213f9b4a69SYuval Mintz p_cmn->accept_any_vlan = p_params->accept_any_vlan; 72283aeb933SYuval Mintz val = p_params->update_accept_any_vlan_flg; 72383aeb933SYuval Mintz p_cmn->update_accept_any_vlan_flg = val; 72417b235c1SYuval Mintz 72517b235c1SYuval Mintz p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; 72617b235c1SYuval Mintz val = p_params->update_inner_vlan_removal_flg; 72717b235c1SYuval Mintz p_cmn->update_inner_vlan_removal_en_flg = val; 72808feecd7SYuval Mintz 72908feecd7SYuval Mintz p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; 73008feecd7SYuval Mintz val = p_params->update_default_vlan_enable_flg; 73108feecd7SYuval Mintz p_cmn->update_default_vlan_en_flg = val; 73208feecd7SYuval Mintz 73308feecd7SYuval Mintz p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); 73408feecd7SYuval Mintz p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; 73508feecd7SYuval Mintz 73608feecd7SYuval Mintz p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; 73708feecd7SYuval Mintz 73817b235c1SYuval Mintz p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; 73917b235c1SYuval Mintz p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; 74017b235c1SYuval Mintz 7416ddc7608SYuval Mintz p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; 7426ddc7608SYuval Mintz val = p_params->update_anti_spoofing_en_flg; 7436ddc7608SYuval Mintz p_ramrod->common.update_anti_spoofing_en_flg = val; 7446ddc7608SYuval Mintz 745cee4d264SManish Chopra rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 746cee4d264SManish Chopra if (rc) { 747fb5e7438SDenis Bolotin qed_sp_destroy_request(p_hwfn, p_ent); 748cee4d264SManish Chopra return rc; 749cee4d264SManish Chopra } 750cee4d264SManish Chopra 751ff929696SManish Chopra if (p_params->update_ctl_frame_check) { 752ff929696SManish Chopra p_cmn->ctl_frame_mac_check_en = p_params->mac_chk_en; 753ff929696SManish Chopra p_cmn->ctl_frame_ethtype_check_en = p_params->ethtype_chk_en; 754ff929696SManish Chopra } 755ff929696SManish Chopra 756cee4d264SManish Chopra /* Update mcast bins for VFs, PF doesn't use this functionality */ 757cee4d264SManish Chopra qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 758cee4d264SManish Chopra 759cee4d264SManish Chopra qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 76017b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); 761cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 762cee4d264SManish Chopra } 763cee4d264SManish Chopra 764dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) 765cee4d264SManish Chopra { 766cee4d264SManish Chopra struct vport_stop_ramrod_data *p_ramrod; 76706f56b81SYuval Mintz struct qed_sp_init_data init_data; 768cee4d264SManish Chopra struct qed_spq_entry *p_ent; 769cee4d264SManish Chopra u8 abs_vport_id = 0; 770cee4d264SManish Chopra int rc; 771cee4d264SManish Chopra 772dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 773dacd88d6SYuval Mintz return qed_vf_pf_vport_stop(p_hwfn); 774dacd88d6SYuval Mintz 775cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 7761a635e48SYuval Mintz if (rc) 777cee4d264SManish Chopra return rc; 778cee4d264SManish Chopra 77906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 78006f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 78106f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 78206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 783cee4d264SManish Chopra 784cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 785cee4d264SManish Chopra ETH_RAMROD_VPORT_STOP, 78606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 787cee4d264SManish Chopra if (rc) 788cee4d264SManish Chopra return rc; 789cee4d264SManish Chopra 790cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_stop; 791cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 792cee4d264SManish Chopra 793cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 794cee4d264SManish Chopra } 795cee4d264SManish Chopra 796dacd88d6SYuval Mintz static int 797dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, 798dacd88d6SYuval Mintz struct qed_filter_accept_flags *p_accept_flags) 799dacd88d6SYuval Mintz { 800dacd88d6SYuval Mintz struct qed_sp_vport_update_params s_params; 801dacd88d6SYuval Mintz 802dacd88d6SYuval Mintz memset(&s_params, 0, sizeof(s_params)); 803dacd88d6SYuval Mintz memcpy(&s_params.accept_flags, p_accept_flags, 804dacd88d6SYuval Mintz sizeof(struct qed_filter_accept_flags)); 805dacd88d6SYuval Mintz 806dacd88d6SYuval Mintz return qed_vf_pf_vport_update(p_hwfn, &s_params); 807dacd88d6SYuval Mintz } 808dacd88d6SYuval Mintz 809cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev, 810cee4d264SManish Chopra u8 vport, 811cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags, 8123f9b4a69SYuval Mintz u8 update_accept_any_vlan, 8133f9b4a69SYuval Mintz u8 accept_any_vlan, 814cee4d264SManish Chopra enum spq_mode comp_mode, 815cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 816cee4d264SManish Chopra { 817cee4d264SManish Chopra struct qed_sp_vport_update_params vport_update_params; 818cee4d264SManish Chopra int i, rc; 819cee4d264SManish Chopra 820cee4d264SManish Chopra /* Prepare and send the vport rx_mode change */ 821cee4d264SManish Chopra memset(&vport_update_params, 0, sizeof(vport_update_params)); 822cee4d264SManish Chopra vport_update_params.vport_id = vport; 823cee4d264SManish Chopra vport_update_params.accept_flags = accept_flags; 8243f9b4a69SYuval Mintz vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 8253f9b4a69SYuval Mintz vport_update_params.accept_any_vlan = accept_any_vlan; 826cee4d264SManish Chopra 827cee4d264SManish Chopra for_each_hwfn(cdev, i) { 828cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 829cee4d264SManish Chopra 830cee4d264SManish Chopra vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 831cee4d264SManish Chopra 832dacd88d6SYuval Mintz if (IS_VF(cdev)) { 833dacd88d6SYuval Mintz rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); 834dacd88d6SYuval Mintz if (rc) 835dacd88d6SYuval Mintz return rc; 836dacd88d6SYuval Mintz continue; 837dacd88d6SYuval Mintz } 838dacd88d6SYuval Mintz 839cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 840cee4d264SManish Chopra comp_mode, p_comp_data); 8411a635e48SYuval Mintz if (rc) { 842cee4d264SManish Chopra DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 843cee4d264SManish Chopra return rc; 844cee4d264SManish Chopra } 845cee4d264SManish Chopra 846cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 847cee4d264SManish Chopra "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 848cee4d264SManish Chopra accept_flags.rx_accept_filter, 849cee4d264SManish Chopra accept_flags.tx_accept_filter); 8503f9b4a69SYuval Mintz if (update_accept_any_vlan) 8513f9b4a69SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 8523f9b4a69SYuval Mintz "accept_any_vlan=%d configured\n", 8533f9b4a69SYuval Mintz accept_any_vlan); 854cee4d264SManish Chopra } 855cee4d264SManish Chopra 856cee4d264SManish Chopra return 0; 857cee4d264SManish Chopra } 858cee4d264SManish Chopra 8593da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 8603da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 861cee4d264SManish Chopra u16 bd_max_bytes, 862cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 8633da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size) 864cee4d264SManish Chopra { 865cee4d264SManish Chopra struct rx_queue_start_ramrod_data *p_ramrod = NULL; 866cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 86706f56b81SYuval Mintz struct qed_sp_init_data init_data; 868cee4d264SManish Chopra int rc = -EINVAL; 869cee4d264SManish Chopra 870cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 8713da7a37aSMintz, Yuval "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n", 8723da7a37aSMintz, Yuval p_cid->opaque_fid, p_cid->cid, 873f604b17dSMintz, Yuval p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id); 874cee4d264SManish Chopra 87506f56b81SYuval Mintz /* Get SPQ entry */ 87606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 8773da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 8783da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 87906f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 880cee4d264SManish Chopra 881cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 882cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_START, 88306f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 884cee4d264SManish Chopra if (rc) 885cee4d264SManish Chopra return rc; 886cee4d264SManish Chopra 887cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_start; 888cee4d264SManish Chopra 889f604b17dSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); 890f604b17dSMintz, Yuval p_ramrod->sb_index = p_cid->sb_idx; 8913da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 8923da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 8933da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 894cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 0; 895cee4d264SManish Chopra p_ramrod->complete_event_flg = 1; 896cee4d264SManish Chopra 897cee4d264SManish Chopra p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 89894494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 899cee4d264SManish Chopra 900cee4d264SManish Chopra p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 90194494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 902cee4d264SManish Chopra 9033946497aSMintz, Yuval if (p_cid->vfid != QED_QUEUE_CID_SELF) { 9043b19f478SMintz, Yuval bool b_legacy_vf = !!(p_cid->vf_legacy & 9053b19f478SMintz, Yuval QED_QCID_LEGACY_VF_RX_PROD); 9063b19f478SMintz, Yuval 9073da7a37aSMintz, Yuval p_ramrod->vf_rx_prod_index = p_cid->vf_qid; 908351a4dedSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 909a044df83SYuval Mintz "Queue%s is meant for VF rxq[%02x]\n", 9103b19f478SMintz, Yuval b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid); 9113b19f478SMintz, Yuval p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf; 912a044df83SYuval Mintz } 913cee4d264SManish Chopra 914351a4dedSYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 915cee4d264SManish Chopra } 916cee4d264SManish Chopra 917cee4d264SManish Chopra static int 9183da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn, 9193da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 920cee4d264SManish Chopra u16 bd_max_bytes, 921cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 922cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 923dacd88d6SYuval Mintz u16 cqe_pbl_size, void __iomem **pp_prod) 924cee4d264SManish Chopra { 925b21290b7SYuval Mintz u32 init_prod_val = 0; 926cee4d264SManish Chopra 9273da7a37aSMintz, Yuval *pp_prod = p_hwfn->regview + 928cee4d264SManish Chopra GTT_BAR0_MAP_REG_MSDM_RAM + 9293da7a37aSMintz, Yuval MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); 930cee4d264SManish Chopra 931cee4d264SManish Chopra /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 932b21290b7SYuval Mintz __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), 933cee4d264SManish Chopra (u32 *)(&init_prod_val)); 934cee4d264SManish Chopra 9353da7a37aSMintz, Yuval return qed_eth_rxq_start_ramrod(p_hwfn, p_cid, 936cee4d264SManish Chopra bd_max_bytes, 937cee4d264SManish Chopra bd_chain_phys_addr, 9383da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size); 9393da7a37aSMintz, Yuval } 940cee4d264SManish Chopra 9413da7a37aSMintz, Yuval static int 9423da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 9433da7a37aSMintz, Yuval u16 opaque_fid, 9443da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 9453da7a37aSMintz, Yuval u16 bd_max_bytes, 9463da7a37aSMintz, Yuval dma_addr_t bd_chain_phys_addr, 9473da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, 9483da7a37aSMintz, Yuval u16 cqe_pbl_size, 9493da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *p_ret_params) 9503da7a37aSMintz, Yuval { 9513da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 9523da7a37aSMintz, Yuval int rc; 9533da7a37aSMintz, Yuval 9543da7a37aSMintz, Yuval /* Allocate a CID for the queue */ 955007bc371SMintz, Yuval p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params); 9563da7a37aSMintz, Yuval if (!p_cid) 9573da7a37aSMintz, Yuval return -ENOMEM; 9583da7a37aSMintz, Yuval 9593da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 9603da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid, 9613da7a37aSMintz, Yuval bd_max_bytes, 9623da7a37aSMintz, Yuval bd_chain_phys_addr, 9633da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, 9643da7a37aSMintz, Yuval &p_ret_params->p_prod); 9653da7a37aSMintz, Yuval } else { 9663da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_start(p_hwfn, p_cid, 9673da7a37aSMintz, Yuval bd_max_bytes, 9683da7a37aSMintz, Yuval bd_chain_phys_addr, 9693da7a37aSMintz, Yuval cqe_pbl_addr, 9703da7a37aSMintz, Yuval cqe_pbl_size, &p_ret_params->p_prod); 9713da7a37aSMintz, Yuval } 9723da7a37aSMintz, Yuval 9733da7a37aSMintz, Yuval /* Provide the caller with a reference to as handler */ 9741a635e48SYuval Mintz if (rc) 9753da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 9763da7a37aSMintz, Yuval else 9773da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 978cee4d264SManish Chopra 979cee4d264SManish Chopra return rc; 980cee4d264SManish Chopra } 981cee4d264SManish Chopra 98217b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 9833da7a37aSMintz, Yuval void **pp_rxq_handles, 98417b235c1SYuval Mintz u8 num_rxqs, 98517b235c1SYuval Mintz u8 complete_cqe_flg, 98617b235c1SYuval Mintz u8 complete_event_flg, 98717b235c1SYuval Mintz enum spq_mode comp_mode, 98817b235c1SYuval Mintz struct qed_spq_comp_cb *p_comp_data) 98917b235c1SYuval Mintz { 99017b235c1SYuval Mintz struct rx_queue_update_ramrod_data *p_ramrod = NULL; 99117b235c1SYuval Mintz struct qed_spq_entry *p_ent = NULL; 99217b235c1SYuval Mintz struct qed_sp_init_data init_data; 9933da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 99417b235c1SYuval Mintz int rc = -EINVAL; 99517b235c1SYuval Mintz u8 i; 99617b235c1SYuval Mintz 99717b235c1SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 99817b235c1SYuval Mintz init_data.comp_mode = comp_mode; 99917b235c1SYuval Mintz init_data.p_comp_data = p_comp_data; 100017b235c1SYuval Mintz 100117b235c1SYuval Mintz for (i = 0; i < num_rxqs; i++) { 10023da7a37aSMintz, Yuval p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i]; 100317b235c1SYuval Mintz 100417b235c1SYuval Mintz /* Get SPQ entry */ 10053da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 10063da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 100717b235c1SYuval Mintz 100817b235c1SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 100917b235c1SYuval Mintz ETH_RAMROD_RX_QUEUE_UPDATE, 101017b235c1SYuval Mintz PROTOCOLID_ETH, &init_data); 101117b235c1SYuval Mintz if (rc) 101217b235c1SYuval Mintz return rc; 101317b235c1SYuval Mintz 101417b235c1SYuval Mintz p_ramrod = &p_ent->ramrod.rx_queue_update; 10153da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 101617b235c1SYuval Mintz 10173da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 101817b235c1SYuval Mintz p_ramrod->complete_cqe_flg = complete_cqe_flg; 101917b235c1SYuval Mintz p_ramrod->complete_event_flg = complete_event_flg; 102017b235c1SYuval Mintz 102117b235c1SYuval Mintz rc = qed_spq_post(p_hwfn, p_ent, NULL); 102217b235c1SYuval Mintz if (rc) 102317b235c1SYuval Mintz return rc; 102417b235c1SYuval Mintz } 102517b235c1SYuval Mintz 102617b235c1SYuval Mintz return rc; 102717b235c1SYuval Mintz } 102817b235c1SYuval Mintz 10293da7a37aSMintz, Yuval static int 10303da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn, 10313da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 10323da7a37aSMintz, Yuval bool b_eq_completion_only, bool b_cqe_completion) 1033cee4d264SManish Chopra { 1034cee4d264SManish Chopra struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 1035cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 103606f56b81SYuval Mintz struct qed_sp_init_data init_data; 10373da7a37aSMintz, Yuval int rc; 1038cee4d264SManish Chopra 103906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 10403da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 10413da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 104206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1043cee4d264SManish Chopra 1044cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1045cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_STOP, 104606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1047cee4d264SManish Chopra if (rc) 1048cee4d264SManish Chopra return rc; 1049cee4d264SManish Chopra 1050cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_stop; 10513da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 10523da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 1053cee4d264SManish Chopra 1054cee4d264SManish Chopra /* Cleaning the queue requires the completion to arrive there. 1055cee4d264SManish Chopra * In addition, VFs require the answer to come as eqe to PF. 1056cee4d264SManish Chopra */ 10573946497aSMintz, Yuval p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) && 10583da7a37aSMintz, Yuval !b_eq_completion_only) || 10593da7a37aSMintz, Yuval b_cqe_completion; 10603946497aSMintz, Yuval p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) || 10613946497aSMintz, Yuval b_eq_completion_only; 1062cee4d264SManish Chopra 10633da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 1064cee4d264SManish Chopra } 1065cee4d264SManish Chopra 10663da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 10673da7a37aSMintz, Yuval void *p_rxq, 10683da7a37aSMintz, Yuval bool eq_completion_only, bool cqe_completion) 10693da7a37aSMintz, Yuval { 10703da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq; 10713da7a37aSMintz, Yuval int rc = -EINVAL; 10723da7a37aSMintz, Yuval 10733da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 10743da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid, 10753da7a37aSMintz, Yuval eq_completion_only, 10763da7a37aSMintz, Yuval cqe_completion); 10773da7a37aSMintz, Yuval else 10783da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion); 10793da7a37aSMintz, Yuval 10803da7a37aSMintz, Yuval if (!rc) 10813da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 10823da7a37aSMintz, Yuval return rc; 10833da7a37aSMintz, Yuval } 10843da7a37aSMintz, Yuval 10853da7a37aSMintz, Yuval int 10863da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 10873da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 10883da7a37aSMintz, Yuval dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id) 1089cee4d264SManish Chopra { 1090cee4d264SManish Chopra struct tx_queue_start_ramrod_data *p_ramrod = NULL; 1091cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 109206f56b81SYuval Mintz struct qed_sp_init_data init_data; 1093cee4d264SManish Chopra int rc = -EINVAL; 1094351a4dedSYuval Mintz 109506f56b81SYuval Mintz /* Get SPQ entry */ 109606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 10973da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 10983da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 109906f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1100cee4d264SManish Chopra 110106f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 1102cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_START, 110306f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1104cee4d264SManish Chopra if (rc) 1105cee4d264SManish Chopra return rc; 1106cee4d264SManish Chopra 1107cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.tx_queue_start; 11083da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 1109cee4d264SManish Chopra 1110f604b17dSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); 1111f604b17dSMintz, Yuval p_ramrod->sb_index = p_cid->sb_idx; 11123da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 1113cee4d264SManish Chopra 11143da7a37aSMintz, Yuval p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id); 11153da7a37aSMintz, Yuval p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id); 11161a635e48SYuval Mintz 1117cee4d264SManish Chopra p_ramrod->pbl_size = cpu_to_le16(pbl_size); 111894494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 1119cee4d264SManish Chopra 1120cee4d264SManish Chopra p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 1121cee4d264SManish Chopra 1122cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1123cee4d264SManish Chopra } 1124cee4d264SManish Chopra 1125cee4d264SManish Chopra static int 11263da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn, 11273da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 11283da7a37aSMintz, Yuval u8 tc, 1129cee4d264SManish Chopra dma_addr_t pbl_addr, 1130dacd88d6SYuval Mintz u16 pbl_size, void __iomem **pp_doorbell) 1131cee4d264SManish Chopra { 1132cee4d264SManish Chopra int rc; 1133cee4d264SManish Chopra 1134cee4d264SManish Chopra 11353da7a37aSMintz, Yuval rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid, 11363da7a37aSMintz, Yuval pbl_addr, pbl_size, 1137b5a9ee7cSAriel Elior qed_get_cm_pq_idx_mcos(p_hwfn, tc)); 11383da7a37aSMintz, Yuval if (rc) 1139cee4d264SManish Chopra return rc; 11403da7a37aSMintz, Yuval 11413da7a37aSMintz, Yuval /* Provide the caller with the necessary return values */ 11423da7a37aSMintz, Yuval *pp_doorbell = p_hwfn->doorbells + 11433da7a37aSMintz, Yuval qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY); 11443da7a37aSMintz, Yuval 11453da7a37aSMintz, Yuval return 0; 1146cee4d264SManish Chopra } 1147cee4d264SManish Chopra 11483da7a37aSMintz, Yuval static int 11493da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 11503da7a37aSMintz, Yuval u16 opaque_fid, 11513da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 11523da7a37aSMintz, Yuval u8 tc, 11533da7a37aSMintz, Yuval dma_addr_t pbl_addr, 11543da7a37aSMintz, Yuval u16 pbl_size, 11553da7a37aSMintz, Yuval struct qed_txq_start_ret_params *p_ret_params) 11563da7a37aSMintz, Yuval { 11573da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 11583da7a37aSMintz, Yuval int rc; 1159cee4d264SManish Chopra 1160007bc371SMintz, Yuval p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params); 11613da7a37aSMintz, Yuval if (!p_cid) 11623da7a37aSMintz, Yuval return -EINVAL; 1163cee4d264SManish Chopra 11643da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 11653da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc, 11663da7a37aSMintz, Yuval pbl_addr, pbl_size, 11673da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 11683da7a37aSMintz, Yuval else 11693da7a37aSMintz, Yuval rc = qed_vf_pf_txq_start(p_hwfn, p_cid, 11703da7a37aSMintz, Yuval pbl_addr, pbl_size, 11713da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 1172cee4d264SManish Chopra 1173cee4d264SManish Chopra if (rc) 11743da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 11753da7a37aSMintz, Yuval else 11763da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 1177cee4d264SManish Chopra 1178cee4d264SManish Chopra return rc; 1179cee4d264SManish Chopra } 1180cee4d264SManish Chopra 11813da7a37aSMintz, Yuval static int 11823da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid) 1183cee4d264SManish Chopra { 1184cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 118506f56b81SYuval Mintz struct qed_sp_init_data init_data; 11863da7a37aSMintz, Yuval int rc; 1187cee4d264SManish Chopra 118806f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 11893da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 11903da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 119106f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1192cee4d264SManish Chopra 1193cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1194cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_STOP, 119506f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1196cee4d264SManish Chopra if (rc) 1197cee4d264SManish Chopra return rc; 1198cee4d264SManish Chopra 11993da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 12003da7a37aSMintz, Yuval } 1201cee4d264SManish Chopra 12023da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle) 12033da7a37aSMintz, Yuval { 12043da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle; 12053da7a37aSMintz, Yuval int rc; 12063da7a37aSMintz, Yuval 12073da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 12083da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid); 12093da7a37aSMintz, Yuval else 12103da7a37aSMintz, Yuval rc = qed_vf_pf_txq_stop(p_hwfn, p_cid); 12113da7a37aSMintz, Yuval 12123da7a37aSMintz, Yuval if (!rc) 12133da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 12143da7a37aSMintz, Yuval return rc; 1215cee4d264SManish Chopra } 1216cee4d264SManish Chopra 12171a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode) 1218cee4d264SManish Chopra { 1219cee4d264SManish Chopra enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 1220cee4d264SManish Chopra 1221cee4d264SManish Chopra switch (opcode) { 1222cee4d264SManish Chopra case QED_FILTER_ADD: 1223cee4d264SManish Chopra action = ETH_FILTER_ACTION_ADD; 1224cee4d264SManish Chopra break; 1225cee4d264SManish Chopra case QED_FILTER_REMOVE: 1226cee4d264SManish Chopra action = ETH_FILTER_ACTION_REMOVE; 1227cee4d264SManish Chopra break; 1228cee4d264SManish Chopra case QED_FILTER_FLUSH: 1229fc48b7a6SYuval Mintz action = ETH_FILTER_ACTION_REMOVE_ALL; 1230cee4d264SManish Chopra break; 1231cee4d264SManish Chopra default: 1232cee4d264SManish Chopra action = MAX_ETH_FILTER_ACTION; 1233cee4d264SManish Chopra } 1234cee4d264SManish Chopra 1235cee4d264SManish Chopra return action; 1236cee4d264SManish Chopra } 1237cee4d264SManish Chopra 1238cee4d264SManish Chopra static int 1239cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 1240cee4d264SManish Chopra u16 opaque_fid, 1241cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1242cee4d264SManish Chopra struct vport_filter_update_ramrod_data **pp_ramrod, 1243cee4d264SManish Chopra struct qed_spq_entry **pp_ent, 1244cee4d264SManish Chopra enum spq_mode comp_mode, 1245cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1246cee4d264SManish Chopra { 1247cee4d264SManish Chopra u8 vport_to_add_to = 0, vport_to_remove_from = 0; 1248cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod; 1249cee4d264SManish Chopra struct eth_filter_cmd *p_first_filter; 1250cee4d264SManish Chopra struct eth_filter_cmd *p_second_filter; 125106f56b81SYuval Mintz struct qed_sp_init_data init_data; 1252cee4d264SManish Chopra enum eth_filter_action action; 1253cee4d264SManish Chopra int rc; 1254cee4d264SManish Chopra 1255cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1256cee4d264SManish Chopra &vport_to_remove_from); 1257cee4d264SManish Chopra if (rc) 1258cee4d264SManish Chopra return rc; 1259cee4d264SManish Chopra 1260cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1261cee4d264SManish Chopra &vport_to_add_to); 1262cee4d264SManish Chopra if (rc) 1263cee4d264SManish Chopra return rc; 1264cee4d264SManish Chopra 126506f56b81SYuval Mintz /* Get SPQ entry */ 126606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 126706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 126806f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 126906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 127006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1271cee4d264SManish Chopra 1272cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, pp_ent, 1273cee4d264SManish Chopra ETH_RAMROD_FILTERS_UPDATE, 127406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1275cee4d264SManish Chopra if (rc) 1276cee4d264SManish Chopra return rc; 1277cee4d264SManish Chopra 1278cee4d264SManish Chopra *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 1279cee4d264SManish Chopra p_ramrod = *pp_ramrod; 1280cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 1281cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 1282cee4d264SManish Chopra 1283cee4d264SManish Chopra switch (p_filter_cmd->opcode) { 1284fc48b7a6SYuval Mintz case QED_FILTER_REPLACE: 1285cee4d264SManish Chopra case QED_FILTER_MOVE: 1286cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 1287cee4d264SManish Chopra default: 1288cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 1289cee4d264SManish Chopra } 1290cee4d264SManish Chopra 1291cee4d264SManish Chopra p_first_filter = &p_ramrod->filter_cmds[0]; 1292cee4d264SManish Chopra p_second_filter = &p_ramrod->filter_cmds[1]; 1293cee4d264SManish Chopra 1294cee4d264SManish Chopra switch (p_filter_cmd->type) { 1295cee4d264SManish Chopra case QED_FILTER_MAC: 1296cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 1297cee4d264SManish Chopra case QED_FILTER_VLAN: 1298cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 1299cee4d264SManish Chopra case QED_FILTER_MAC_VLAN: 1300cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 1301cee4d264SManish Chopra case QED_FILTER_INNER_MAC: 1302cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 1303cee4d264SManish Chopra case QED_FILTER_INNER_VLAN: 1304cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 1305cee4d264SManish Chopra case QED_FILTER_INNER_PAIR: 1306cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 1307cee4d264SManish Chopra case QED_FILTER_INNER_MAC_VNI_PAIR: 1308cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 1309cee4d264SManish Chopra break; 1310cee4d264SManish Chopra case QED_FILTER_MAC_VNI_PAIR: 1311cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 1312cee4d264SManish Chopra case QED_FILTER_VNI: 1313cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 1314cee4d264SManish Chopra } 1315cee4d264SManish Chopra 1316cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 1317cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1318cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 1319cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 1320cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1321cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 1322cee4d264SManish Chopra qed_set_fw_mac_addr(&p_first_filter->mac_msb, 1323cee4d264SManish Chopra &p_first_filter->mac_mid, 1324cee4d264SManish Chopra &p_first_filter->mac_lsb, 1325cee4d264SManish Chopra (u8 *)p_filter_cmd->mac); 1326cee4d264SManish Chopra } 1327cee4d264SManish Chopra 1328cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 1329cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1330cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 1331cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 1332cee4d264SManish Chopra p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 1333cee4d264SManish Chopra 1334cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1335cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 1336cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 1337cee4d264SManish Chopra p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 1338cee4d264SManish Chopra 1339cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 1340cee4d264SManish Chopra p_second_filter->type = p_first_filter->type; 1341cee4d264SManish Chopra p_second_filter->mac_msb = p_first_filter->mac_msb; 1342cee4d264SManish Chopra p_second_filter->mac_mid = p_first_filter->mac_mid; 1343cee4d264SManish Chopra p_second_filter->mac_lsb = p_first_filter->mac_lsb; 1344cee4d264SManish Chopra p_second_filter->vlan_id = p_first_filter->vlan_id; 1345cee4d264SManish Chopra p_second_filter->vni = p_first_filter->vni; 1346cee4d264SManish Chopra 1347cee4d264SManish Chopra p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 1348cee4d264SManish Chopra 1349cee4d264SManish Chopra p_first_filter->vport_id = vport_to_remove_from; 1350cee4d264SManish Chopra 1351cee4d264SManish Chopra p_second_filter->action = ETH_FILTER_ACTION_ADD; 1352cee4d264SManish Chopra p_second_filter->vport_id = vport_to_add_to; 1353fc48b7a6SYuval Mintz } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 1354fc48b7a6SYuval Mintz p_first_filter->vport_id = vport_to_add_to; 1355fc48b7a6SYuval Mintz memcpy(p_second_filter, p_first_filter, 1356fc48b7a6SYuval Mintz sizeof(*p_second_filter)); 1357fc48b7a6SYuval Mintz p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 1358fc48b7a6SYuval Mintz p_second_filter->action = ETH_FILTER_ACTION_ADD; 1359cee4d264SManish Chopra } else { 1360cee4d264SManish Chopra action = qed_filter_action(p_filter_cmd->opcode); 1361cee4d264SManish Chopra 1362cee4d264SManish Chopra if (action == MAX_ETH_FILTER_ACTION) { 1363cee4d264SManish Chopra DP_NOTICE(p_hwfn, 1364cee4d264SManish Chopra "%d is not supported yet\n", 1365cee4d264SManish Chopra p_filter_cmd->opcode); 1366fb5e7438SDenis Bolotin qed_sp_destroy_request(p_hwfn, *pp_ent); 1367cee4d264SManish Chopra return -EINVAL; 1368cee4d264SManish Chopra } 1369cee4d264SManish Chopra 1370cee4d264SManish Chopra p_first_filter->action = action; 1371cee4d264SManish Chopra p_first_filter->vport_id = (p_filter_cmd->opcode == 1372cee4d264SManish Chopra QED_FILTER_REMOVE) ? 1373cee4d264SManish Chopra vport_to_remove_from : 1374cee4d264SManish Chopra vport_to_add_to; 1375cee4d264SManish Chopra } 1376cee4d264SManish Chopra 1377cee4d264SManish Chopra return 0; 1378cee4d264SManish Chopra } 1379cee4d264SManish Chopra 1380dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 1381cee4d264SManish Chopra u16 opaque_fid, 1382cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1383cee4d264SManish Chopra enum spq_mode comp_mode, 1384cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1385cee4d264SManish Chopra { 1386cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod = NULL; 1387cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 1388cee4d264SManish Chopra struct eth_filter_cmd_header *p_header; 1389cee4d264SManish Chopra int rc; 1390cee4d264SManish Chopra 1391cee4d264SManish Chopra rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1392cee4d264SManish Chopra &p_ramrod, &p_ent, 1393cee4d264SManish Chopra comp_mode, p_comp_data); 13941a635e48SYuval Mintz if (rc) { 1395cee4d264SManish Chopra DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1396cee4d264SManish Chopra return rc; 1397cee4d264SManish Chopra } 1398cee4d264SManish Chopra p_header = &p_ramrod->filter_cmd_hdr; 1399cee4d264SManish Chopra p_header->assert_on_error = p_filter_cmd->assert_on_error; 1400cee4d264SManish Chopra 1401cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 14021a635e48SYuval Mintz if (rc) { 14031a635e48SYuval Mintz DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc); 1404cee4d264SManish Chopra return rc; 1405cee4d264SManish Chopra } 1406cee4d264SManish Chopra 1407cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1408cee4d264SManish Chopra "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1409cee4d264SManish Chopra (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1410cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1411cee4d264SManish Chopra "REMOVE" : 1412cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1413cee4d264SManish Chopra "MOVE" : "REPLACE")), 1414cee4d264SManish Chopra (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1415cee4d264SManish Chopra ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1416cee4d264SManish Chopra "VLAN" : "MAC & VLAN"), 1417cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt, 1418cee4d264SManish Chopra p_filter_cmd->is_rx_filter, 1419cee4d264SManish Chopra p_filter_cmd->is_tx_filter); 1420cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1421cee4d264SManish Chopra "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1422cee4d264SManish Chopra p_filter_cmd->vport_to_add_to, 1423cee4d264SManish Chopra p_filter_cmd->vport_to_remove_from, 1424cee4d264SManish Chopra p_filter_cmd->mac[0], 1425cee4d264SManish Chopra p_filter_cmd->mac[1], 1426cee4d264SManish Chopra p_filter_cmd->mac[2], 1427cee4d264SManish Chopra p_filter_cmd->mac[3], 1428cee4d264SManish Chopra p_filter_cmd->mac[4], 1429cee4d264SManish Chopra p_filter_cmd->mac[5], 1430cee4d264SManish Chopra p_filter_cmd->vlan); 1431cee4d264SManish Chopra 1432cee4d264SManish Chopra return 0; 1433cee4d264SManish Chopra } 1434cee4d264SManish Chopra 1435cee4d264SManish Chopra /******************************************************************************* 1436cee4d264SManish Chopra * Description: 1437cee4d264SManish Chopra * Calculates crc 32 on a buffer 1438cee4d264SManish Chopra * Note: crc32_length MUST be aligned to 8 1439cee4d264SManish Chopra * Return: 1440cee4d264SManish Chopra ******************************************************************************/ 1441cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet, 14421a635e48SYuval Mintz u32 crc32_length, u32 crc32_seed, u8 complement) 1443cee4d264SManish Chopra { 14441a635e48SYuval Mintz u32 byte = 0, bit = 0, crc32_result = crc32_seed; 14451a635e48SYuval Mintz u8 msb = 0, current_byte = 0; 1446cee4d264SManish Chopra 1447cee4d264SManish Chopra if ((!crc32_packet) || 1448cee4d264SManish Chopra (crc32_length == 0) || 1449cee4d264SManish Chopra ((crc32_length % 8) != 0)) 1450cee4d264SManish Chopra return crc32_result; 1451cee4d264SManish Chopra for (byte = 0; byte < crc32_length; byte++) { 1452cee4d264SManish Chopra current_byte = crc32_packet[byte]; 1453cee4d264SManish Chopra for (bit = 0; bit < 8; bit++) { 1454cee4d264SManish Chopra msb = (u8)(crc32_result >> 31); 1455cee4d264SManish Chopra crc32_result = crc32_result << 1; 1456cee4d264SManish Chopra if (msb != (0x1 & (current_byte >> bit))) { 1457cee4d264SManish Chopra crc32_result = crc32_result ^ CRC32_POLY; 1458cee4d264SManish Chopra crc32_result |= 1; /*crc32_result[0] = 1;*/ 1459cee4d264SManish Chopra } 1460cee4d264SManish Chopra } 1461cee4d264SManish Chopra } 1462cee4d264SManish Chopra return crc32_result; 1463cee4d264SManish Chopra } 1464cee4d264SManish Chopra 14651a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len) 1466cee4d264SManish Chopra { 1467cee4d264SManish Chopra u32 packet_buf[2] = { 0 }; 1468cee4d264SManish Chopra 1469cee4d264SManish Chopra memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1470cee4d264SManish Chopra return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1471cee4d264SManish Chopra } 1472cee4d264SManish Chopra 1473dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac) 1474cee4d264SManish Chopra { 1475cee4d264SManish Chopra u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1476cee4d264SManish Chopra mac, ETH_ALEN); 1477cee4d264SManish Chopra 1478cee4d264SManish Chopra return crc & 0xff; 1479cee4d264SManish Chopra } 1480cee4d264SManish Chopra 1481cee4d264SManish Chopra static int 1482cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1483cee4d264SManish Chopra u16 opaque_fid, 1484cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1485cee4d264SManish Chopra enum spq_mode comp_mode, 1486cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1487cee4d264SManish Chopra { 1488cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 148925c020a9SSudarsana Reddy Kalluru u32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1490cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 149106f56b81SYuval Mintz struct qed_sp_init_data init_data; 1492cee4d264SManish Chopra u8 abs_vport_id = 0; 1493cee4d264SManish Chopra int rc, i; 1494cee4d264SManish Chopra 149583aeb933SYuval Mintz if (p_filter_cmd->opcode == QED_FILTER_ADD) 1496cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1497cee4d264SManish Chopra &abs_vport_id); 149883aeb933SYuval Mintz else 1499cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1500cee4d264SManish Chopra &abs_vport_id); 1501cee4d264SManish Chopra if (rc) 1502cee4d264SManish Chopra return rc; 1503cee4d264SManish Chopra 150406f56b81SYuval Mintz /* Get SPQ entry */ 150506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 150606f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 150706f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 150806f56b81SYuval Mintz init_data.comp_mode = comp_mode; 150906f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1510cee4d264SManish Chopra 1511cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1512cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 151306f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1514cee4d264SManish Chopra if (rc) { 1515cee4d264SManish Chopra DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1516cee4d264SManish Chopra return rc; 1517cee4d264SManish Chopra } 1518cee4d264SManish Chopra 1519cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 1520cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 1521cee4d264SManish Chopra 1522cee4d264SManish Chopra /* explicitly clear out the entire vector */ 1523cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 1524cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 152525c020a9SSudarsana Reddy Kalluru memset(bins, 0, sizeof(bins)); 1526cee4d264SManish Chopra /* filter ADD op is explicit set op and it removes 1527cee4d264SManish Chopra * any existing filters for the vport 1528cee4d264SManish Chopra */ 1529cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1530cee4d264SManish Chopra for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 153125c020a9SSudarsana Reddy Kalluru u32 bit, nbits; 1532cee4d264SManish Chopra 1533cee4d264SManish Chopra bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 153425c020a9SSudarsana Reddy Kalluru nbits = sizeof(u32) * BITS_PER_BYTE; 153525c020a9SSudarsana Reddy Kalluru bins[bit / nbits] |= 1 << (bit % nbits); 1536cee4d264SManish Chopra } 1537cee4d264SManish Chopra 1538cee4d264SManish Chopra /* Convert to correct endianity */ 1539cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 15401a635e48SYuval Mintz struct vport_update_ramrod_mcast *p_ramrod_bins; 1541cee4d264SManish Chopra 15421a635e48SYuval Mintz p_ramrod_bins = &p_ramrod->approx_mcast; 154325c020a9SSudarsana Reddy Kalluru p_ramrod_bins->bins[i] = cpu_to_le32(bins[i]); 1544cee4d264SManish Chopra } 1545cee4d264SManish Chopra } 1546cee4d264SManish Chopra 1547cee4d264SManish Chopra p_ramrod->common.vport_id = abs_vport_id; 1548cee4d264SManish Chopra 1549cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1550cee4d264SManish Chopra } 1551cee4d264SManish Chopra 1552dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev, 1553cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1554cee4d264SManish Chopra enum spq_mode comp_mode, 1555cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1556cee4d264SManish Chopra { 1557cee4d264SManish Chopra int rc = 0; 1558cee4d264SManish Chopra int i; 1559cee4d264SManish Chopra 1560cee4d264SManish Chopra /* only ADD and REMOVE operations are supported for multi-cast */ 1561cee4d264SManish Chopra if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1562cee4d264SManish Chopra (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1563cee4d264SManish Chopra (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1564cee4d264SManish Chopra return -EINVAL; 1565cee4d264SManish Chopra 1566cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1567cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1568cee4d264SManish Chopra 1569cee4d264SManish Chopra u16 opaque_fid; 1570cee4d264SManish Chopra 1571dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1572dacd88d6SYuval Mintz qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); 1573dacd88d6SYuval Mintz continue; 1574dacd88d6SYuval Mintz } 1575cee4d264SManish Chopra 1576cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1577cee4d264SManish Chopra 1578cee4d264SManish Chopra rc = qed_sp_eth_filter_mcast(p_hwfn, 1579cee4d264SManish Chopra opaque_fid, 1580cee4d264SManish Chopra p_filter_cmd, 15811a635e48SYuval Mintz comp_mode, p_comp_data); 1582cee4d264SManish Chopra } 1583cee4d264SManish Chopra return rc; 1584cee4d264SManish Chopra } 1585cee4d264SManish Chopra 1586cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1587cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1588cee4d264SManish Chopra enum spq_mode comp_mode, 1589cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1590cee4d264SManish Chopra { 1591cee4d264SManish Chopra int rc = 0; 1592cee4d264SManish Chopra int i; 1593cee4d264SManish Chopra 1594cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1595cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1596cee4d264SManish Chopra u16 opaque_fid; 1597cee4d264SManish Chopra 1598dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1599dacd88d6SYuval Mintz rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); 1600dacd88d6SYuval Mintz continue; 1601dacd88d6SYuval Mintz } 1602cee4d264SManish Chopra 1603cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1604cee4d264SManish Chopra 1605cee4d264SManish Chopra rc = qed_sp_eth_filter_ucast(p_hwfn, 1606cee4d264SManish Chopra opaque_fid, 1607cee4d264SManish Chopra p_filter_cmd, 16081a635e48SYuval Mintz comp_mode, p_comp_data); 16091a635e48SYuval Mintz if (rc) 1610dacd88d6SYuval Mintz break; 1611cee4d264SManish Chopra } 1612cee4d264SManish Chopra 1613cee4d264SManish Chopra return rc; 1614cee4d264SManish Chopra } 1615cee4d264SManish Chopra 161686622ee7SYuval Mintz /* Statistics related code */ 161786622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 161886622ee7SYuval Mintz u32 *p_addr, 1619dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 162086622ee7SYuval Mintz { 1621dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 162286622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_PSDM_RAM + 162386622ee7SYuval Mintz PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 162486622ee7SYuval Mintz *p_len = sizeof(struct eth_pstorm_per_queue_stat); 1625dacd88d6SYuval Mintz } else { 1626dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1627dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1628dacd88d6SYuval Mintz 1629dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.pstats.address; 1630dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.pstats.len; 1631dacd88d6SYuval Mintz } 163286622ee7SYuval Mintz } 163386622ee7SYuval Mintz 163486622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 163586622ee7SYuval Mintz struct qed_ptt *p_ptt, 163686622ee7SYuval Mintz struct qed_eth_stats *p_stats, 163786622ee7SYuval Mintz u16 statistics_bin) 163886622ee7SYuval Mintz { 163986622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 164086622ee7SYuval Mintz u32 pstats_addr = 0, pstats_len = 0; 164186622ee7SYuval Mintz 164286622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 164386622ee7SYuval Mintz statistics_bin); 164486622ee7SYuval Mintz 164586622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 1646dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); 164786622ee7SYuval Mintz 16489c79ddaaSMintz, Yuval p_stats->common.tx_ucast_bytes += 16499c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_bytes); 16509c79ddaaSMintz, Yuval p_stats->common.tx_mcast_bytes += 16519c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_bytes); 16529c79ddaaSMintz, Yuval p_stats->common.tx_bcast_bytes += 16539c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_bytes); 16549c79ddaaSMintz, Yuval p_stats->common.tx_ucast_pkts += 16559c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_pkts); 16569c79ddaaSMintz, Yuval p_stats->common.tx_mcast_pkts += 16579c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_pkts); 16589c79ddaaSMintz, Yuval p_stats->common.tx_bcast_pkts += 16599c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_pkts); 16609c79ddaaSMintz, Yuval p_stats->common.tx_err_drop_pkts += 16619c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.error_drop_pkts); 166286622ee7SYuval Mintz } 166386622ee7SYuval Mintz 166486622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 166586622ee7SYuval Mintz struct qed_ptt *p_ptt, 166686622ee7SYuval Mintz struct qed_eth_stats *p_stats, 166786622ee7SYuval Mintz u16 statistics_bin) 166886622ee7SYuval Mintz { 166986622ee7SYuval Mintz struct tstorm_per_port_stat tstats; 1670dacd88d6SYuval Mintz u32 tstats_addr, tstats_len; 167186622ee7SYuval Mintz 1672dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1673dacd88d6SYuval Mintz tstats_addr = BAR0_MAP_REG_TSDM_RAM + 1674dacd88d6SYuval Mintz TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 1675dacd88d6SYuval Mintz tstats_len = sizeof(struct tstorm_per_port_stat); 1676dacd88d6SYuval Mintz } else { 1677dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1678dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1679dacd88d6SYuval Mintz 1680dacd88d6SYuval Mintz tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; 1681dacd88d6SYuval Mintz tstats_len = p_resp->pfdev_info.stats_info.tstats.len; 1682dacd88d6SYuval Mintz } 168386622ee7SYuval Mintz 168486622ee7SYuval Mintz memset(&tstats, 0, sizeof(tstats)); 1685dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); 168686622ee7SYuval Mintz 16879c79ddaaSMintz, Yuval p_stats->common.mftag_filter_discards += 168886622ee7SYuval Mintz HILO_64_REGPAIR(tstats.mftag_filter_discard); 16899c79ddaaSMintz, Yuval p_stats->common.mac_filter_discards += 169086622ee7SYuval Mintz HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 1691608e00d0SManish Chopra p_stats->common.gft_filter_drop += 1692608e00d0SManish Chopra HILO_64_REGPAIR(tstats.eth_gft_drop_pkt); 169386622ee7SYuval Mintz } 169486622ee7SYuval Mintz 169586622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 169686622ee7SYuval Mintz u32 *p_addr, 1697dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 169886622ee7SYuval Mintz { 1699dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 170086622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_USDM_RAM + 170186622ee7SYuval Mintz USTORM_QUEUE_STAT_OFFSET(statistics_bin); 170286622ee7SYuval Mintz *p_len = sizeof(struct eth_ustorm_per_queue_stat); 1703dacd88d6SYuval Mintz } else { 1704dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1705dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1706dacd88d6SYuval Mintz 1707dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.ustats.address; 1708dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.ustats.len; 1709dacd88d6SYuval Mintz } 171086622ee7SYuval Mintz } 171186622ee7SYuval Mintz 171286622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 171386622ee7SYuval Mintz struct qed_ptt *p_ptt, 171486622ee7SYuval Mintz struct qed_eth_stats *p_stats, 171586622ee7SYuval Mintz u16 statistics_bin) 171686622ee7SYuval Mintz { 171786622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 171886622ee7SYuval Mintz u32 ustats_addr = 0, ustats_len = 0; 171986622ee7SYuval Mintz 172086622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 172186622ee7SYuval Mintz statistics_bin); 172286622ee7SYuval Mintz 172386622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 1724dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); 172586622ee7SYuval Mintz 17269c79ddaaSMintz, Yuval p_stats->common.rx_ucast_bytes += 17279c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 17289c79ddaaSMintz, Yuval p_stats->common.rx_mcast_bytes += 17299c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 17309c79ddaaSMintz, Yuval p_stats->common.rx_bcast_bytes += 17319c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 17329c79ddaaSMintz, Yuval p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 17339c79ddaaSMintz, Yuval p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 17349c79ddaaSMintz, Yuval p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 173586622ee7SYuval Mintz } 173686622ee7SYuval Mintz 173786622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 173886622ee7SYuval Mintz u32 *p_addr, 1739dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 174086622ee7SYuval Mintz { 1741dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 174286622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_MSDM_RAM + 174386622ee7SYuval Mintz MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 174486622ee7SYuval Mintz *p_len = sizeof(struct eth_mstorm_per_queue_stat); 1745dacd88d6SYuval Mintz } else { 1746dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1747dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1748dacd88d6SYuval Mintz 1749dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.mstats.address; 1750dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.mstats.len; 1751dacd88d6SYuval Mintz } 175286622ee7SYuval Mintz } 175386622ee7SYuval Mintz 175486622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 175586622ee7SYuval Mintz struct qed_ptt *p_ptt, 175686622ee7SYuval Mintz struct qed_eth_stats *p_stats, 175786622ee7SYuval Mintz u16 statistics_bin) 175886622ee7SYuval Mintz { 175986622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 176086622ee7SYuval Mintz u32 mstats_addr = 0, mstats_len = 0; 176186622ee7SYuval Mintz 176286622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 176386622ee7SYuval Mintz statistics_bin); 176486622ee7SYuval Mintz 176586622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 1766dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); 176786622ee7SYuval Mintz 17689c79ddaaSMintz, Yuval p_stats->common.no_buff_discards += 17699c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.no_buff_discard); 17709c79ddaaSMintz, Yuval p_stats->common.packet_too_big_discard += 177186622ee7SYuval Mintz HILO_64_REGPAIR(mstats.packet_too_big_discard); 17729c79ddaaSMintz, Yuval p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); 17739c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_pkts += 177486622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 17759c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_events += 177686622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_events); 17779c79ddaaSMintz, Yuval p_stats->common.tpa_aborts_num += 17789c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.tpa_aborts_num); 17799c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_bytes += 178086622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 178186622ee7SYuval Mintz } 178286622ee7SYuval Mintz 178386622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 178486622ee7SYuval Mintz struct qed_ptt *p_ptt, 178586622ee7SYuval Mintz struct qed_eth_stats *p_stats) 178686622ee7SYuval Mintz { 17879c79ddaaSMintz, Yuval struct qed_eth_stats_common *p_common = &p_stats->common; 178886622ee7SYuval Mintz struct port_stats port_stats; 178986622ee7SYuval Mintz int j; 179086622ee7SYuval Mintz 179186622ee7SYuval Mintz memset(&port_stats, 0, sizeof(port_stats)); 179286622ee7SYuval Mintz 179386622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 179486622ee7SYuval Mintz p_hwfn->mcp_info->port_addr + 179586622ee7SYuval Mintz offsetof(struct public_port, stats), 179686622ee7SYuval Mintz sizeof(port_stats)); 179786622ee7SYuval Mintz 17989c79ddaaSMintz, Yuval p_common->rx_64_byte_packets += port_stats.eth.r64; 17999c79ddaaSMintz, Yuval p_common->rx_65_to_127_byte_packets += port_stats.eth.r127; 18009c79ddaaSMintz, Yuval p_common->rx_128_to_255_byte_packets += port_stats.eth.r255; 18019c79ddaaSMintz, Yuval p_common->rx_256_to_511_byte_packets += port_stats.eth.r511; 18029c79ddaaSMintz, Yuval p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023; 18039c79ddaaSMintz, Yuval p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; 18049c79ddaaSMintz, Yuval p_common->rx_crc_errors += port_stats.eth.rfcs; 18059c79ddaaSMintz, Yuval p_common->rx_mac_crtl_frames += port_stats.eth.rxcf; 18069c79ddaaSMintz, Yuval p_common->rx_pause_frames += port_stats.eth.rxpf; 18079c79ddaaSMintz, Yuval p_common->rx_pfc_frames += port_stats.eth.rxpp; 18089c79ddaaSMintz, Yuval p_common->rx_align_errors += port_stats.eth.raln; 18099c79ddaaSMintz, Yuval p_common->rx_carrier_errors += port_stats.eth.rfcr; 18109c79ddaaSMintz, Yuval p_common->rx_oversize_packets += port_stats.eth.rovr; 18119c79ddaaSMintz, Yuval p_common->rx_jabbers += port_stats.eth.rjbr; 18129c79ddaaSMintz, Yuval p_common->rx_undersize_packets += port_stats.eth.rund; 18139c79ddaaSMintz, Yuval p_common->rx_fragments += port_stats.eth.rfrg; 18149c79ddaaSMintz, Yuval p_common->tx_64_byte_packets += port_stats.eth.t64; 18159c79ddaaSMintz, Yuval p_common->tx_65_to_127_byte_packets += port_stats.eth.t127; 18169c79ddaaSMintz, Yuval p_common->tx_128_to_255_byte_packets += port_stats.eth.t255; 18179c79ddaaSMintz, Yuval p_common->tx_256_to_511_byte_packets += port_stats.eth.t511; 18189c79ddaaSMintz, Yuval p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023; 18199c79ddaaSMintz, Yuval p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; 18209c79ddaaSMintz, Yuval p_common->tx_pause_frames += port_stats.eth.txpf; 18219c79ddaaSMintz, Yuval p_common->tx_pfc_frames += port_stats.eth.txpp; 18229c79ddaaSMintz, Yuval p_common->rx_mac_bytes += port_stats.eth.rbyte; 18239c79ddaaSMintz, Yuval p_common->rx_mac_uc_packets += port_stats.eth.rxuca; 18249c79ddaaSMintz, Yuval p_common->rx_mac_mc_packets += port_stats.eth.rxmca; 18259c79ddaaSMintz, Yuval p_common->rx_mac_bc_packets += port_stats.eth.rxbca; 18269c79ddaaSMintz, Yuval p_common->rx_mac_frames_ok += port_stats.eth.rxpok; 18279c79ddaaSMintz, Yuval p_common->tx_mac_bytes += port_stats.eth.tbyte; 18289c79ddaaSMintz, Yuval p_common->tx_mac_uc_packets += port_stats.eth.txuca; 18299c79ddaaSMintz, Yuval p_common->tx_mac_mc_packets += port_stats.eth.txmca; 18309c79ddaaSMintz, Yuval p_common->tx_mac_bc_packets += port_stats.eth.txbca; 18319c79ddaaSMintz, Yuval p_common->tx_mac_ctrl_frames += port_stats.eth.txcf; 183286622ee7SYuval Mintz for (j = 0; j < 8; j++) { 18339c79ddaaSMintz, Yuval p_common->brb_truncates += port_stats.brb.brb_truncate[j]; 18349c79ddaaSMintz, Yuval p_common->brb_discards += port_stats.brb.brb_discard[j]; 18359c79ddaaSMintz, Yuval } 18369c79ddaaSMintz, Yuval 18379c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) { 18389c79ddaaSMintz, Yuval struct qed_eth_stats_bb *p_bb = &p_stats->bb; 18399c79ddaaSMintz, Yuval 18409c79ddaaSMintz, Yuval p_bb->rx_1519_to_1522_byte_packets += 18419c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r1522; 18429c79ddaaSMintz, Yuval p_bb->rx_1519_to_2047_byte_packets += 18439c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r2047; 18449c79ddaaSMintz, Yuval p_bb->rx_2048_to_4095_byte_packets += 18459c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r4095; 18469c79ddaaSMintz, Yuval p_bb->rx_4096_to_9216_byte_packets += 18479c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r9216; 18489c79ddaaSMintz, Yuval p_bb->rx_9217_to_16383_byte_packets += 18499c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r16383; 18509c79ddaaSMintz, Yuval p_bb->tx_1519_to_2047_byte_packets += 18519c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t2047; 18529c79ddaaSMintz, Yuval p_bb->tx_2048_to_4095_byte_packets += 18539c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t4095; 18549c79ddaaSMintz, Yuval p_bb->tx_4096_to_9216_byte_packets += 18559c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t9216; 18569c79ddaaSMintz, Yuval p_bb->tx_9217_to_16383_byte_packets += 18579c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t16383; 18589c79ddaaSMintz, Yuval p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec; 18599c79ddaaSMintz, Yuval p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl; 18609c79ddaaSMintz, Yuval } else { 18619c79ddaaSMintz, Yuval struct qed_eth_stats_ah *p_ah = &p_stats->ah; 18629c79ddaaSMintz, Yuval 18639c79ddaaSMintz, Yuval p_ah->rx_1519_to_max_byte_packets += 18649c79ddaaSMintz, Yuval port_stats.eth.u0.ah0.r1519_to_max; 18659c79ddaaSMintz, Yuval p_ah->tx_1519_to_max_byte_packets = 18669c79ddaaSMintz, Yuval port_stats.eth.u1.ah1.t1519_to_max; 186786622ee7SYuval Mintz } 186832d26a68SSudarsana Reddy Kalluru 186932d26a68SSudarsana Reddy Kalluru p_common->link_change_count = qed_rd(p_hwfn, p_ptt, 187032d26a68SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 187132d26a68SSudarsana Reddy Kalluru offsetof(struct public_port, 187232d26a68SSudarsana Reddy Kalluru link_change_count)); 187386622ee7SYuval Mintz } 187486622ee7SYuval Mintz 187586622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 187686622ee7SYuval Mintz struct qed_ptt *p_ptt, 187786622ee7SYuval Mintz struct qed_eth_stats *stats, 1878dacd88d6SYuval Mintz u16 statistics_bin, bool b_get_port_stats) 187986622ee7SYuval Mintz { 188086622ee7SYuval Mintz __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 188186622ee7SYuval Mintz __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 188286622ee7SYuval Mintz __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 188386622ee7SYuval Mintz __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 188486622ee7SYuval Mintz 1885dacd88d6SYuval Mintz if (b_get_port_stats && p_hwfn->mcp_info) 188686622ee7SYuval Mintz __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 188786622ee7SYuval Mintz } 188886622ee7SYuval Mintz 188986622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev, 189086622ee7SYuval Mintz struct qed_eth_stats *stats) 189186622ee7SYuval Mintz { 189286622ee7SYuval Mintz u8 fw_vport = 0; 189386622ee7SYuval Mintz int i; 189486622ee7SYuval Mintz 189586622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 189686622ee7SYuval Mintz 189786622ee7SYuval Mintz for_each_hwfn(cdev, i) { 189886622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1899dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1900dacd88d6SYuval Mintz : NULL; 190186622ee7SYuval Mintz 1902dacd88d6SYuval Mintz if (IS_PF(cdev)) { 190386622ee7SYuval Mintz /* The main vport index is relative first */ 190486622ee7SYuval Mintz if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 190586622ee7SYuval Mintz DP_ERR(p_hwfn, "No vport available!\n"); 1906dacd88d6SYuval Mintz goto out; 1907dacd88d6SYuval Mintz } 190886622ee7SYuval Mintz } 190986622ee7SYuval Mintz 1910dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 191186622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 191286622ee7SYuval Mintz continue; 191386622ee7SYuval Mintz } 191486622ee7SYuval Mintz 1915dacd88d6SYuval Mintz __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, 1916dacd88d6SYuval Mintz IS_PF(cdev) ? true : false); 191786622ee7SYuval Mintz 1918dacd88d6SYuval Mintz out: 1919dacd88d6SYuval Mintz if (IS_PF(cdev) && p_ptt) 192086622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 192186622ee7SYuval Mintz } 192286622ee7SYuval Mintz } 192386622ee7SYuval Mintz 19241a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats) 192586622ee7SYuval Mintz { 192686622ee7SYuval Mintz u32 i; 192786622ee7SYuval Mintz 192886622ee7SYuval Mintz if (!cdev) { 192986622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 193086622ee7SYuval Mintz return; 193186622ee7SYuval Mintz } 193286622ee7SYuval Mintz 193386622ee7SYuval Mintz _qed_get_vport_stats(cdev, stats); 193486622ee7SYuval Mintz 193586622ee7SYuval Mintz if (!cdev->reset_stats) 193686622ee7SYuval Mintz return; 193786622ee7SYuval Mintz 193886622ee7SYuval Mintz /* Reduce the statistics baseline */ 193986622ee7SYuval Mintz for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 194086622ee7SYuval Mintz ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 194186622ee7SYuval Mintz } 194286622ee7SYuval Mintz 194386622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 194486622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev) 194586622ee7SYuval Mintz { 194686622ee7SYuval Mintz int i; 194786622ee7SYuval Mintz 194886622ee7SYuval Mintz for_each_hwfn(cdev, i) { 194986622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 195086622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 195186622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 195286622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 1953dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1954dacd88d6SYuval Mintz : NULL; 195586622ee7SYuval Mintz u32 addr = 0, len = 0; 195686622ee7SYuval Mintz 1957dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 195886622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 195986622ee7SYuval Mintz continue; 196086622ee7SYuval Mintz } 196186622ee7SYuval Mintz 196286622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 196386622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 196486622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 196586622ee7SYuval Mintz 196686622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 196786622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 196886622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 196986622ee7SYuval Mintz 197086622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 197186622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 197286622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 197386622ee7SYuval Mintz 1974dacd88d6SYuval Mintz if (IS_PF(cdev)) 197586622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 197686622ee7SYuval Mintz } 197786622ee7SYuval Mintz 197886622ee7SYuval Mintz /* PORT statistics are not necessarily reset, so we need to 197986622ee7SYuval Mintz * read and create a baseline for future statistics. 198032d26a68SSudarsana Reddy Kalluru * Link change stat is maintained by MFW, return its value as is. 198186622ee7SYuval Mintz */ 198232d26a68SSudarsana Reddy Kalluru if (!cdev->reset_stats) { 198386622ee7SYuval Mintz DP_INFO(cdev, "Reset stats not allocated\n"); 198432d26a68SSudarsana Reddy Kalluru } else { 198586622ee7SYuval Mintz _qed_get_vport_stats(cdev, cdev->reset_stats); 198632d26a68SSudarsana Reddy Kalluru cdev->reset_stats->common.link_change_count = 0; 198732d26a68SSudarsana Reddy Kalluru } 198886622ee7SYuval Mintz } 198986622ee7SYuval Mintz 1990da090917STomer Tayar static enum gft_profile_type 1991da090917STomer Tayar qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode) 1992da090917STomer Tayar { 1993da090917STomer Tayar if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE) 1994da090917STomer Tayar return GFT_PROFILE_TYPE_4_TUPLE; 1995da090917STomer Tayar if (mode == QED_FILTER_CONFIG_MODE_IP_DEST) 199650bc60cbSMichal Kalderon return GFT_PROFILE_TYPE_IP_DST_ADDR; 19973893fc62SManish Chopra if (mode == QED_FILTER_CONFIG_MODE_IP_SRC) 19983893fc62SManish Chopra return GFT_PROFILE_TYPE_IP_SRC_ADDR; 1999da090917STomer Tayar return GFT_PROFILE_TYPE_L4_DST_PORT; 2000da090917STomer Tayar } 2001da090917STomer Tayar 2002da090917STomer Tayar void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, 2003da090917STomer Tayar struct qed_ptt *p_ptt, 2004d51e4af5SChopra, Manish struct qed_arfs_config_params *p_cfg_params) 2005d51e4af5SChopra, Manish { 2006da090917STomer Tayar if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) { 2007da090917STomer Tayar qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 2008da090917STomer Tayar p_cfg_params->tcp, 2009da090917STomer Tayar p_cfg_params->udp, 2010da090917STomer Tayar p_cfg_params->ipv4, 2011da090917STomer Tayar p_cfg_params->ipv6, 2012da090917STomer Tayar qed_arfs_mode_to_hsi(p_cfg_params->mode)); 2013da090917STomer Tayar DP_VERBOSE(p_hwfn, 2014da090917STomer Tayar QED_MSG_SP, 2015da090917STomer Tayar "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n", 2016d51e4af5SChopra, Manish p_cfg_params->tcp ? "Enable" : "Disable", 2017d51e4af5SChopra, Manish p_cfg_params->udp ? "Enable" : "Disable", 2018d51e4af5SChopra, Manish p_cfg_params->ipv4 ? "Enable" : "Disable", 2019da090917STomer Tayar p_cfg_params->ipv6 ? "Enable" : "Disable", 2020da090917STomer Tayar (u32)p_cfg_params->mode); 2021d51e4af5SChopra, Manish } else { 2022da090917STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, "Disabled Filtering\n"); 2023da090917STomer Tayar qed_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2024da090917STomer Tayar } 2025d51e4af5SChopra, Manish } 2026d51e4af5SChopra, Manish 2027da090917STomer Tayar int 2028da090917STomer Tayar qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, 2029d51e4af5SChopra, Manish struct qed_spq_comp_cb *p_cb, 2030da090917STomer Tayar struct qed_ntuple_filter_params *p_params) 2031d51e4af5SChopra, Manish { 2032d51e4af5SChopra, Manish struct rx_update_gft_filter_data *p_ramrod = NULL; 2033d51e4af5SChopra, Manish struct qed_spq_entry *p_ent = NULL; 2034d51e4af5SChopra, Manish struct qed_sp_init_data init_data; 2035d51e4af5SChopra, Manish u16 abs_rx_q_id = 0; 2036d51e4af5SChopra, Manish u8 abs_vport_id = 0; 2037d51e4af5SChopra, Manish int rc = -EINVAL; 2038d51e4af5SChopra, Manish 2039d51e4af5SChopra, Manish /* Get SPQ entry */ 2040d51e4af5SChopra, Manish memset(&init_data, 0, sizeof(init_data)); 2041d51e4af5SChopra, Manish init_data.cid = qed_spq_get_cid(p_hwfn); 2042d51e4af5SChopra, Manish 2043d51e4af5SChopra, Manish init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2044d51e4af5SChopra, Manish 2045d51e4af5SChopra, Manish if (p_cb) { 2046d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_CB; 2047d51e4af5SChopra, Manish init_data.p_comp_data = p_cb; 2048d51e4af5SChopra, Manish } else { 2049d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2050d51e4af5SChopra, Manish } 2051d51e4af5SChopra, Manish 2052d51e4af5SChopra, Manish rc = qed_sp_init_request(p_hwfn, &p_ent, 2053d51e4af5SChopra, Manish ETH_RAMROD_GFT_UPDATE_FILTER, 2054d51e4af5SChopra, Manish PROTOCOLID_ETH, &init_data); 2055d51e4af5SChopra, Manish if (rc) 2056d51e4af5SChopra, Manish return rc; 2057d51e4af5SChopra, Manish 2058d51e4af5SChopra, Manish p_ramrod = &p_ent->ramrod.rx_update_gft; 2059da090917STomer Tayar 2060da090917STomer Tayar DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr); 2061da090917STomer Tayar p_ramrod->pkt_hdr_length = cpu_to_le16(p_params->length); 2062da090917STomer Tayar 2063608e00d0SManish Chopra if (p_params->b_is_drop) { 2064608e00d0SManish Chopra p_ramrod->vport_id = cpu_to_le16(ETH_GFT_TRASHCAN_VPORT); 2065608e00d0SManish Chopra } else { 2066608e00d0SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 2067608e00d0SManish Chopra if (rc) 2068fb5e7438SDenis Bolotin goto err; 2069608e00d0SManish Chopra 2070da090917STomer Tayar if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) { 2071608e00d0SManish Chopra rc = qed_fw_l2_queue(p_hwfn, p_params->qid, 2072608e00d0SManish Chopra &abs_rx_q_id); 2073608e00d0SManish Chopra if (rc) 2074fb5e7438SDenis Bolotin goto err; 2075608e00d0SManish Chopra 2076da090917STomer Tayar p_ramrod->rx_qid_valid = 1; 2077da090917STomer Tayar p_ramrod->rx_qid = cpu_to_le16(abs_rx_q_id); 2078da090917STomer Tayar } 2079da090917STomer Tayar 2080608e00d0SManish Chopra p_ramrod->vport_id = cpu_to_le16((u16)abs_vport_id); 2081608e00d0SManish Chopra } 2082608e00d0SManish Chopra 2083da090917STomer Tayar p_ramrod->flow_id_valid = 0; 2084da090917STomer Tayar p_ramrod->flow_id = 0; 2085da090917STomer Tayar p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER 2086da090917STomer Tayar : GFT_DELETE_FILTER; 2087d51e4af5SChopra, Manish 2088d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, 2089d51e4af5SChopra, Manish "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n", 2090d51e4af5SChopra, Manish abs_vport_id, abs_rx_q_id, 2091da090917STomer Tayar p_params->b_is_add ? "Adding" : "Removing", 2092da090917STomer Tayar (u64)p_params->addr, p_params->length); 2093d51e4af5SChopra, Manish 2094d51e4af5SChopra, Manish return qed_spq_post(p_hwfn, p_ent, NULL); 2095fb5e7438SDenis Bolotin 2096fb5e7438SDenis Bolotin err: 2097fb5e7438SDenis Bolotin qed_sp_destroy_request(p_hwfn, p_ent); 2098fb5e7438SDenis Bolotin return rc; 2099d51e4af5SChopra, Manish } 2100d51e4af5SChopra, Manish 2101bf5a94bfSRahul Verma int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn, 2102bf5a94bfSRahul Verma struct qed_ptt *p_ptt, 2103bf5a94bfSRahul Verma struct qed_queue_cid *p_cid, u16 *p_rx_coal) 2104bf5a94bfSRahul Verma { 2105bf5a94bfSRahul Verma u32 coalesce, address, is_valid; 2106bf5a94bfSRahul Verma struct cau_sb_entry sb_entry; 2107bf5a94bfSRahul Verma u8 timer_res; 2108bf5a94bfSRahul Verma int rc; 2109bf5a94bfSRahul Verma 2110bf5a94bfSRahul Verma rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2111bf5a94bfSRahul Verma p_cid->sb_igu_id * sizeof(u64), 2112bf5a94bfSRahul Verma (u64)(uintptr_t)&sb_entry, 2, 0); 2113bf5a94bfSRahul Verma if (rc) { 2114bf5a94bfSRahul Verma DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2115bf5a94bfSRahul Verma return rc; 2116bf5a94bfSRahul Verma } 2117bf5a94bfSRahul Verma 2118bf5a94bfSRahul Verma timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0); 2119bf5a94bfSRahul Verma 2120bf5a94bfSRahul Verma address = BAR0_MAP_REG_USDM_RAM + 2121bf5a94bfSRahul Verma USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 2122bf5a94bfSRahul Verma coalesce = qed_rd(p_hwfn, p_ptt, address); 2123bf5a94bfSRahul Verma 2124bf5a94bfSRahul Verma is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); 2125bf5a94bfSRahul Verma if (!is_valid) 2126bf5a94bfSRahul Verma return -EINVAL; 2127bf5a94bfSRahul Verma 2128bf5a94bfSRahul Verma coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); 2129bf5a94bfSRahul Verma *p_rx_coal = (u16)(coalesce << timer_res); 2130bf5a94bfSRahul Verma 2131bf5a94bfSRahul Verma return 0; 2132bf5a94bfSRahul Verma } 2133bf5a94bfSRahul Verma 2134bf5a94bfSRahul Verma int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn, 2135bf5a94bfSRahul Verma struct qed_ptt *p_ptt, 2136bf5a94bfSRahul Verma struct qed_queue_cid *p_cid, u16 *p_tx_coal) 2137bf5a94bfSRahul Verma { 2138bf5a94bfSRahul Verma u32 coalesce, address, is_valid; 2139bf5a94bfSRahul Verma struct cau_sb_entry sb_entry; 2140bf5a94bfSRahul Verma u8 timer_res; 2141bf5a94bfSRahul Verma int rc; 2142bf5a94bfSRahul Verma 2143bf5a94bfSRahul Verma rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2144bf5a94bfSRahul Verma p_cid->sb_igu_id * sizeof(u64), 2145bf5a94bfSRahul Verma (u64)(uintptr_t)&sb_entry, 2, 0); 2146bf5a94bfSRahul Verma if (rc) { 2147bf5a94bfSRahul Verma DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2148bf5a94bfSRahul Verma return rc; 2149bf5a94bfSRahul Verma } 2150bf5a94bfSRahul Verma 2151bf5a94bfSRahul Verma timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1); 2152bf5a94bfSRahul Verma 2153bf5a94bfSRahul Verma address = BAR0_MAP_REG_XSDM_RAM + 2154bf5a94bfSRahul Verma XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 2155bf5a94bfSRahul Verma coalesce = qed_rd(p_hwfn, p_ptt, address); 2156bf5a94bfSRahul Verma 2157bf5a94bfSRahul Verma is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); 2158bf5a94bfSRahul Verma if (!is_valid) 2159bf5a94bfSRahul Verma return -EINVAL; 2160bf5a94bfSRahul Verma 2161bf5a94bfSRahul Verma coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); 2162bf5a94bfSRahul Verma *p_tx_coal = (u16)(coalesce << timer_res); 2163bf5a94bfSRahul Verma 2164bf5a94bfSRahul Verma return 0; 2165bf5a94bfSRahul Verma } 2166bf5a94bfSRahul Verma 2167bf5a94bfSRahul Verma int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle) 2168bf5a94bfSRahul Verma { 2169bf5a94bfSRahul Verma struct qed_queue_cid *p_cid = handle; 2170bf5a94bfSRahul Verma struct qed_ptt *p_ptt; 2171bf5a94bfSRahul Verma int rc = 0; 2172bf5a94bfSRahul Verma 2173bf5a94bfSRahul Verma if (IS_VF(p_hwfn->cdev)) { 2174bf5a94bfSRahul Verma rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid); 2175bf5a94bfSRahul Verma if (rc) 2176bf5a94bfSRahul Verma DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n"); 2177bf5a94bfSRahul Verma 2178bf5a94bfSRahul Verma return rc; 2179bf5a94bfSRahul Verma } 2180bf5a94bfSRahul Verma 2181bf5a94bfSRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 2182bf5a94bfSRahul Verma if (!p_ptt) 2183bf5a94bfSRahul Verma return -EAGAIN; 2184bf5a94bfSRahul Verma 2185bf5a94bfSRahul Verma if (p_cid->b_is_rx) { 2186bf5a94bfSRahul Verma rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); 2187bf5a94bfSRahul Verma if (rc) 2188bf5a94bfSRahul Verma goto out; 2189bf5a94bfSRahul Verma } else { 2190bf5a94bfSRahul Verma rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); 2191bf5a94bfSRahul Verma if (rc) 2192bf5a94bfSRahul Verma goto out; 2193bf5a94bfSRahul Verma } 2194bf5a94bfSRahul Verma 2195bf5a94bfSRahul Verma out: 2196bf5a94bfSRahul Verma qed_ptt_release(p_hwfn, p_ptt); 2197bf5a94bfSRahul Verma 2198bf5a94bfSRahul Verma return rc; 2199bf5a94bfSRahul Verma } 2200bf5a94bfSRahul Verma 220125c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev, 220225c089d7SYuval Mintz struct qed_dev_eth_info *info) 220325c089d7SYuval Mintz { 22045e7baf0fSManish Chopra struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 220525c089d7SYuval Mintz int i; 220625c089d7SYuval Mintz 220725c089d7SYuval Mintz memset(info, 0, sizeof(*info)); 220825c089d7SYuval Mintz 22091408cc1fSYuval Mintz if (IS_PF(cdev)) { 221025eb8d46SYuval Mintz int max_vf_vlan_filters = 0; 22117b7e70f9SYuval Mintz int max_vf_mac_filters = 0; 221225eb8d46SYuval Mintz 22135e7baf0fSManish Chopra info->num_tc = p_hwfn->hw_info.num_hw_tc; 22145e7baf0fSManish Chopra 221525c089d7SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 2216e1d32acbSMintz, Yuval u16 num_queues = 0; 2217e1d32acbSMintz, Yuval 2218e1d32acbSMintz, Yuval /* Since the feature controls only queue-zones, 2219e1d32acbSMintz, Yuval * make sure we have the contexts [rx, tx, xdp] to 2220e1d32acbSMintz, Yuval * match. 2221e1d32acbSMintz, Yuval */ 2222e1d32acbSMintz, Yuval for_each_hwfn(cdev, i) { 2223e1d32acbSMintz, Yuval struct qed_hwfn *hwfn = &cdev->hwfns[i]; 2224e1d32acbSMintz, Yuval u16 l2_queues = (u16)FEAT_NUM(hwfn, 2225e1d32acbSMintz, Yuval QED_PF_L2_QUE); 2226e1d32acbSMintz, Yuval u16 cids; 2227e1d32acbSMintz, Yuval 2228e1d32acbSMintz, Yuval cids = hwfn->pf_params.eth_pf_params.num_cons; 2229e1d32acbSMintz, Yuval num_queues += min_t(u16, l2_queues, cids / 3); 2230e1d32acbSMintz, Yuval } 2231e1d32acbSMintz, Yuval 2232e1d32acbSMintz, Yuval /* queues might theoretically be >256, but interrupts' 2233e1d32acbSMintz, Yuval * upper-limit guarantes that it would fit in a u8. 2234e1d32acbSMintz, Yuval */ 2235e1d32acbSMintz, Yuval if (cdev->int_params.fp_msix_cnt) { 2236e1d32acbSMintz, Yuval u8 irqs = cdev->int_params.fp_msix_cnt; 2237e1d32acbSMintz, Yuval 2238e1d32acbSMintz, Yuval info->num_queues = (u8)min_t(u16, 2239e1d32acbSMintz, Yuval num_queues, irqs); 2240e1d32acbSMintz, Yuval } 224125c089d7SYuval Mintz } else { 224225c089d7SYuval Mintz info->num_queues = cdev->num_hwfns; 224325c089d7SYuval Mintz } 224425c089d7SYuval Mintz 22457b7e70f9SYuval Mintz if (IS_QED_SRIOV(cdev)) { 224625eb8d46SYuval Mintz max_vf_vlan_filters = cdev->p_iov_info->total_vfs * 224725eb8d46SYuval Mintz QED_ETH_VF_NUM_VLAN_FILTERS; 22487b7e70f9SYuval Mintz max_vf_mac_filters = cdev->p_iov_info->total_vfs * 22497b7e70f9SYuval Mintz QED_ETH_VF_NUM_MAC_FILTERS; 22507b7e70f9SYuval Mintz } 22517b7e70f9SYuval Mintz info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 22527b7e70f9SYuval Mintz QED_VLAN) - 225325eb8d46SYuval Mintz max_vf_vlan_filters; 22547b7e70f9SYuval Mintz info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 22557b7e70f9SYuval Mintz QED_MAC) - 22567b7e70f9SYuval Mintz max_vf_mac_filters; 225725eb8d46SYuval Mintz 225825c089d7SYuval Mintz ether_addr_copy(info->port_mac, 225925c089d7SYuval Mintz cdev->hwfns[0].hw_info.hw_mac_addr); 22601408cc1fSYuval Mintz 2261cbb8a12cSMintz, Yuval info->xdp_supported = true; 2262cbb8a12cSMintz, Yuval } else { 2263cbb8a12cSMintz, Yuval u16 total_cids = 0; 2264cbb8a12cSMintz, Yuval 22655e7baf0fSManish Chopra info->num_tc = 1; 22665e7baf0fSManish Chopra 2267cbb8a12cSMintz, Yuval /* Determine queues & XDP support */ 2268cbb8a12cSMintz, Yuval for_each_hwfn(cdev, i) { 2269cbb8a12cSMintz, Yuval struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2270cbb8a12cSMintz, Yuval u8 queues, cids; 2271cbb8a12cSMintz, Yuval 2272cbb8a12cSMintz, Yuval qed_vf_get_num_cids(p_hwfn, &cids); 2273cbb8a12cSMintz, Yuval qed_vf_get_num_rxqs(p_hwfn, &queues); 22741408cc1fSYuval Mintz info->num_queues += queues; 2275cbb8a12cSMintz, Yuval total_cids += cids; 22761408cc1fSYuval Mintz } 22771408cc1fSYuval Mintz 2278cbb8a12cSMintz, Yuval /* Enable VF XDP in case PF guarntees sufficient connections */ 2279cbb8a12cSMintz, Yuval if (total_cids >= info->num_queues * 3) 2280cbb8a12cSMintz, Yuval info->xdp_supported = true; 2281cbb8a12cSMintz, Yuval 22821408cc1fSYuval Mintz qed_vf_get_num_vlan_filters(&cdev->hwfns[0], 22832edbff8dSTomer Tayar (u8 *)&info->num_vlan_filters); 2284b0fca312SMintz, Yuval qed_vf_get_num_mac_filters(&cdev->hwfns[0], 2285b0fca312SMintz, Yuval (u8 *)&info->num_mac_filters); 22861408cc1fSYuval Mintz qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); 2287d8c2c7e3SYuval Mintz 2288d8c2c7e3SYuval Mintz info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi; 22891408cc1fSYuval Mintz } 229025c089d7SYuval Mintz 229125c089d7SYuval Mintz qed_fill_dev_info(cdev, &info->common); 229225c089d7SYuval Mintz 22931408cc1fSYuval Mintz if (IS_VF(cdev)) 22940ee28e31SShyam Saini eth_zero_addr(info->common.hw_mac); 22951408cc1fSYuval Mintz 229625c089d7SYuval Mintz return 0; 229725c089d7SYuval Mintz } 229825c089d7SYuval Mintz 2299cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev, 23001408cc1fSYuval Mintz struct qed_eth_cb_ops *ops, void *cookie) 2301cc875c2eSYuval Mintz { 2302cc875c2eSYuval Mintz cdev->protocol_ops.eth = ops; 2303cc875c2eSYuval Mintz cdev->ops_cookie = cookie; 23041408cc1fSYuval Mintz 23051408cc1fSYuval Mintz /* For VF, we start bulletin reading */ 23061408cc1fSYuval Mintz if (IS_VF(cdev)) 23071408cc1fSYuval Mintz qed_vf_start_iov_wq(cdev); 2308cc875c2eSYuval Mintz } 2309cc875c2eSYuval Mintz 2310eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) 2311eff16960SYuval Mintz { 2312eff16960SYuval Mintz if (IS_PF(cdev)) 2313eff16960SYuval Mintz return true; 2314eff16960SYuval Mintz 2315eff16960SYuval Mintz return qed_vf_check_mac(&cdev->hwfns[0], mac); 2316eff16960SYuval Mintz } 2317eff16960SYuval Mintz 2318cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev, 2319088c8618SManish Chopra struct qed_start_vport_params *params) 2320cee4d264SManish Chopra { 2321cee4d264SManish Chopra int rc, i; 2322cee4d264SManish Chopra 2323cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2324088c8618SManish Chopra struct qed_sp_vport_start_params start = { 0 }; 2325cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2326cee4d264SManish Chopra 2327088c8618SManish Chopra start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : 2328088c8618SManish Chopra QED_TPA_MODE_NONE; 2329088c8618SManish Chopra start.remove_inner_vlan = params->remove_inner_vlan; 233008feecd7SYuval Mintz start.only_untagged = true; /* untagged only */ 2331088c8618SManish Chopra start.drop_ttl0 = params->drop_ttl0; 2332088c8618SManish Chopra start.opaque_fid = p_hwfn->hw_info.opaque_fid; 2333088c8618SManish Chopra start.concrete_fid = p_hwfn->hw_info.concrete_fid; 2334c78c70faSSudarsana Reddy Kalluru start.handle_ptp_pkts = params->handle_ptp_pkts; 2335088c8618SManish Chopra start.vport_id = params->vport_id; 2336088c8618SManish Chopra start.max_buffers_per_cqe = 16; 2337088c8618SManish Chopra start.mtu = params->mtu; 2338cee4d264SManish Chopra 2339088c8618SManish Chopra rc = qed_sp_vport_start(p_hwfn, &start); 2340cee4d264SManish Chopra if (rc) { 2341cee4d264SManish Chopra DP_ERR(cdev, "Failed to start VPORT\n"); 2342cee4d264SManish Chopra return rc; 2343cee4d264SManish Chopra } 2344cee4d264SManish Chopra 234515582962SRahul Verma rc = qed_hw_start_fastpath(p_hwfn); 234615582962SRahul Verma if (rc) { 234715582962SRahul Verma DP_ERR(cdev, "Failed to start VPORT fastpath\n"); 234815582962SRahul Verma return rc; 234915582962SRahul Verma } 2350cee4d264SManish Chopra 2351cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2352cee4d264SManish Chopra "Started V-PORT %d with MTU %d\n", 2353088c8618SManish Chopra start.vport_id, start.mtu); 2354cee4d264SManish Chopra } 2355cee4d264SManish Chopra 2356a0d26d5aSYuval Mintz if (params->clear_stats) 23579df2ed04SManish Chopra qed_reset_vport_stats(cdev); 23589df2ed04SManish Chopra 2359cee4d264SManish Chopra return 0; 2360cee4d264SManish Chopra } 2361cee4d264SManish Chopra 23621a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id) 2363cee4d264SManish Chopra { 2364cee4d264SManish Chopra int rc, i; 2365cee4d264SManish Chopra 2366cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2367cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2368cee4d264SManish Chopra 2369cee4d264SManish Chopra rc = qed_sp_vport_stop(p_hwfn, 23701a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid, vport_id); 2371cee4d264SManish Chopra 2372cee4d264SManish Chopra if (rc) { 2373cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop VPORT\n"); 2374cee4d264SManish Chopra return rc; 2375cee4d264SManish Chopra } 2376cee4d264SManish Chopra } 2377cee4d264SManish Chopra return 0; 2378cee4d264SManish Chopra } 2379cee4d264SManish Chopra 2380f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev, 2381f29ffdb6SMintz, Yuval struct qed_update_vport_rss_params *input, 2382f29ffdb6SMintz, Yuval struct qed_rss_params *rss) 2383f29ffdb6SMintz, Yuval { 2384f29ffdb6SMintz, Yuval int i, fn; 2385f29ffdb6SMintz, Yuval 2386f29ffdb6SMintz, Yuval /* Update configuration with what's correct regardless of CMT */ 2387f29ffdb6SMintz, Yuval rss->update_rss_config = 1; 2388f29ffdb6SMintz, Yuval rss->rss_enable = 1; 2389f29ffdb6SMintz, Yuval rss->update_rss_capabilities = 1; 2390f29ffdb6SMintz, Yuval rss->update_rss_ind_table = 1; 2391f29ffdb6SMintz, Yuval rss->update_rss_key = 1; 2392f29ffdb6SMintz, Yuval rss->rss_caps = input->rss_caps; 2393f29ffdb6SMintz, Yuval memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32)); 2394f29ffdb6SMintz, Yuval 2395f29ffdb6SMintz, Yuval /* In regular scenario, we'd simply need to take input handlers. 2396f29ffdb6SMintz, Yuval * But in CMT, we'd have to split the handlers according to the 2397f29ffdb6SMintz, Yuval * engine they were configured on. We'd then have to understand 2398f29ffdb6SMintz, Yuval * whether RSS is really required, since 2-queues on CMT doesn't 2399f29ffdb6SMintz, Yuval * require RSS. 2400f29ffdb6SMintz, Yuval */ 2401f29ffdb6SMintz, Yuval if (cdev->num_hwfns == 1) { 2402f29ffdb6SMintz, Yuval memcpy(rss->rss_ind_table, 2403f29ffdb6SMintz, Yuval input->rss_ind_table, 2404f29ffdb6SMintz, Yuval QED_RSS_IND_TABLE_SIZE * sizeof(void *)); 2405f29ffdb6SMintz, Yuval rss->rss_table_size_log = 7; 2406f29ffdb6SMintz, Yuval return 0; 2407f29ffdb6SMintz, Yuval } 2408f29ffdb6SMintz, Yuval 2409f29ffdb6SMintz, Yuval /* Start by copying the non-spcific information to the 2nd copy */ 2410f29ffdb6SMintz, Yuval memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params)); 2411f29ffdb6SMintz, Yuval 2412f29ffdb6SMintz, Yuval /* CMT should be round-robin */ 2413f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 2414f29ffdb6SMintz, Yuval struct qed_queue_cid *cid = input->rss_ind_table[i]; 2415f29ffdb6SMintz, Yuval struct qed_rss_params *t_rss; 2416f29ffdb6SMintz, Yuval 2417f29ffdb6SMintz, Yuval if (cid->p_owner == QED_LEADING_HWFN(cdev)) 2418f29ffdb6SMintz, Yuval t_rss = &rss[0]; 2419f29ffdb6SMintz, Yuval else 2420f29ffdb6SMintz, Yuval t_rss = &rss[1]; 2421f29ffdb6SMintz, Yuval 2422f29ffdb6SMintz, Yuval t_rss->rss_ind_table[i / cdev->num_hwfns] = cid; 2423f29ffdb6SMintz, Yuval } 2424f29ffdb6SMintz, Yuval 2425f29ffdb6SMintz, Yuval /* Make sure RSS is actually required */ 2426f29ffdb6SMintz, Yuval for_each_hwfn(cdev, fn) { 2427f29ffdb6SMintz, Yuval for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) { 2428f29ffdb6SMintz, Yuval if (rss[fn].rss_ind_table[i] != 2429f29ffdb6SMintz, Yuval rss[fn].rss_ind_table[0]) 2430f29ffdb6SMintz, Yuval break; 2431f29ffdb6SMintz, Yuval } 2432f29ffdb6SMintz, Yuval if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) { 2433f29ffdb6SMintz, Yuval DP_VERBOSE(cdev, NETIF_MSG_IFUP, 2434f29ffdb6SMintz, Yuval "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2435f29ffdb6SMintz, Yuval return -EINVAL; 2436f29ffdb6SMintz, Yuval } 2437f29ffdb6SMintz, Yuval rss[fn].rss_table_size_log = 6; 2438f29ffdb6SMintz, Yuval } 2439f29ffdb6SMintz, Yuval 2440f29ffdb6SMintz, Yuval return 0; 2441f29ffdb6SMintz, Yuval } 2442f29ffdb6SMintz, Yuval 2443cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev, 2444cee4d264SManish Chopra struct qed_update_vport_params *params) 2445cee4d264SManish Chopra { 2446cee4d264SManish Chopra struct qed_sp_vport_update_params sp_params; 2447f29ffdb6SMintz, Yuval struct qed_rss_params *rss; 2448f29ffdb6SMintz, Yuval int rc = 0, i; 2449cee4d264SManish Chopra 2450cee4d264SManish Chopra if (!cdev) 2451cee4d264SManish Chopra return -ENODEV; 2452cee4d264SManish Chopra 2453fad953ceSKees Cook rss = vzalloc(array_size(sizeof(*rss), cdev->num_hwfns)); 2454f29ffdb6SMintz, Yuval if (!rss) 2455f29ffdb6SMintz, Yuval return -ENOMEM; 2456f29ffdb6SMintz, Yuval 2457cee4d264SManish Chopra memset(&sp_params, 0, sizeof(sp_params)); 2458cee4d264SManish Chopra 2459cee4d264SManish Chopra /* Translate protocol params into sp params */ 2460cee4d264SManish Chopra sp_params.vport_id = params->vport_id; 24611a635e48SYuval Mintz sp_params.update_vport_active_rx_flg = params->update_vport_active_flg; 24621a635e48SYuval Mintz sp_params.update_vport_active_tx_flg = params->update_vport_active_flg; 2463cee4d264SManish Chopra sp_params.vport_active_rx_flg = params->vport_active_flg; 2464cee4d264SManish Chopra sp_params.vport_active_tx_flg = params->vport_active_flg; 2465831bfb0eSYuval Mintz sp_params.update_tx_switching_flg = params->update_tx_switching_flg; 2466831bfb0eSYuval Mintz sp_params.tx_switching_flg = params->tx_switching_flg; 24673f9b4a69SYuval Mintz sp_params.accept_any_vlan = params->accept_any_vlan; 24683f9b4a69SYuval Mintz sp_params.update_accept_any_vlan_flg = 24693f9b4a69SYuval Mintz params->update_accept_any_vlan_flg; 2470cee4d264SManish Chopra 2471f29ffdb6SMintz, Yuval /* Prepare the RSS configuration */ 2472f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2473f29ffdb6SMintz, Yuval if (qed_update_vport_rss(cdev, ¶ms->rss_params, rss)) 2474cee4d264SManish Chopra params->update_rss_flg = 0; 2475cee4d264SManish Chopra 2476cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2477cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2478cee4d264SManish Chopra 2479f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2480f29ffdb6SMintz, Yuval sp_params.rss_params = &rss[i]; 2481f29ffdb6SMintz, Yuval 2482cee4d264SManish Chopra sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2483cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &sp_params, 2484cee4d264SManish Chopra QED_SPQ_MODE_EBLOCK, 2485cee4d264SManish Chopra NULL); 2486cee4d264SManish Chopra if (rc) { 2487cee4d264SManish Chopra DP_ERR(cdev, "Failed to update VPORT\n"); 2488f29ffdb6SMintz, Yuval goto out; 2489cee4d264SManish Chopra } 2490cee4d264SManish Chopra 2491cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2492cee4d264SManish Chopra "Updated V-PORT %d: active_flag %d [update %d]\n", 2493cee4d264SManish Chopra params->vport_id, params->vport_active_flg, 2494cee4d264SManish Chopra params->update_vport_active_flg); 2495cee4d264SManish Chopra } 2496cee4d264SManish Chopra 2497f29ffdb6SMintz, Yuval out: 2498f29ffdb6SMintz, Yuval vfree(rss); 2499f29ffdb6SMintz, Yuval return rc; 2500cee4d264SManish Chopra } 2501cee4d264SManish Chopra 2502cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev, 25033da7a37aSMintz, Yuval u8 rss_num, 25043da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 2505cee4d264SManish Chopra u16 bd_max_bytes, 2506cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 2507cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 2508cee4d264SManish Chopra u16 cqe_pbl_size, 25093da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *ret_params) 2510cee4d264SManish Chopra { 2511cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 25121a635e48SYuval Mintz int rc, hwfn_index; 2513cee4d264SManish Chopra 25143da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2515cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2516cee4d264SManish Chopra 25173da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 25183da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2519cee4d264SManish Chopra 25203da7a37aSMintz, Yuval rc = qed_eth_rx_queue_start(p_hwfn, 2521cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 25223da7a37aSMintz, Yuval p_params, 2523cee4d264SManish Chopra bd_max_bytes, 2524cee4d264SManish Chopra bd_chain_phys_addr, 25253da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, ret_params); 2526cee4d264SManish Chopra if (rc) { 25273da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id); 2528cee4d264SManish Chopra return rc; 2529cee4d264SManish Chopra } 2530cee4d264SManish Chopra 2531cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2532f604b17dSMintz, Yuval "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", 25333da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 2534f604b17dSMintz, Yuval p_params->p_sb->igu_sb_id); 2535cee4d264SManish Chopra 2536cee4d264SManish Chopra return 0; 2537cee4d264SManish Chopra } 2538cee4d264SManish Chopra 25393da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle) 2540cee4d264SManish Chopra { 2541cee4d264SManish Chopra int rc, hwfn_index; 2542cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2543cee4d264SManish Chopra 25443da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2545cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2546cee4d264SManish Chopra 25473da7a37aSMintz, Yuval rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false); 2548cee4d264SManish Chopra if (rc) { 25493da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id); 2550cee4d264SManish Chopra return rc; 2551cee4d264SManish Chopra } 2552cee4d264SManish Chopra 2553cee4d264SManish Chopra return 0; 2554cee4d264SManish Chopra } 2555cee4d264SManish Chopra 2556cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev, 25573da7a37aSMintz, Yuval u8 rss_num, 2558cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 2559cee4d264SManish Chopra dma_addr_t pbl_addr, 2560cee4d264SManish Chopra u16 pbl_size, 25613da7a37aSMintz, Yuval struct qed_txq_start_ret_params *ret_params) 2562cee4d264SManish Chopra { 2563cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2564cee4d264SManish Chopra int rc, hwfn_index; 2565cee4d264SManish Chopra 25663da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2567cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 25683da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 25693da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2570cee4d264SManish Chopra 25713da7a37aSMintz, Yuval rc = qed_eth_tx_queue_start(p_hwfn, 2572cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 25735e7baf0fSManish Chopra p_params, p_params->tc, 25743da7a37aSMintz, Yuval pbl_addr, pbl_size, ret_params); 2575cee4d264SManish Chopra 2576cee4d264SManish Chopra if (rc) { 2577cee4d264SManish Chopra DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 2578cee4d264SManish Chopra return rc; 2579cee4d264SManish Chopra } 2580cee4d264SManish Chopra 2581cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2582f604b17dSMintz, Yuval "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", 25833da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 2584f604b17dSMintz, Yuval p_params->p_sb->igu_sb_id); 2585cee4d264SManish Chopra 2586cee4d264SManish Chopra return 0; 2587cee4d264SManish Chopra } 2588cee4d264SManish Chopra 2589cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10) 2590cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev) 2591cee4d264SManish Chopra { 259215582962SRahul Verma int rc; 259315582962SRahul Verma 259415582962SRahul Verma rc = qed_hw_stop_fastpath(cdev); 259515582962SRahul Verma if (rc) { 259615582962SRahul Verma DP_ERR(cdev, "Failed to stop Fastpath\n"); 259715582962SRahul Verma return rc; 259815582962SRahul Verma } 2599cee4d264SManish Chopra 2600cee4d264SManish Chopra return 0; 2601cee4d264SManish Chopra } 2602cee4d264SManish Chopra 26033da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle) 2604cee4d264SManish Chopra { 2605cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2606cee4d264SManish Chopra int rc, hwfn_index; 2607cee4d264SManish Chopra 26083da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2609cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2610cee4d264SManish Chopra 26113da7a37aSMintz, Yuval rc = qed_eth_tx_queue_stop(p_hwfn, handle); 2612cee4d264SManish Chopra if (rc) { 26133da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id); 2614cee4d264SManish Chopra return rc; 2615cee4d264SManish Chopra } 2616cee4d264SManish Chopra 2617cee4d264SManish Chopra return 0; 2618cee4d264SManish Chopra } 2619cee4d264SManish Chopra 2620464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev, 2621464f6645SManish Chopra struct qed_tunn_params *tunn_params) 2622464f6645SManish Chopra { 262319968430SChopra, Manish struct qed_tunnel_info tunn_info; 2624464f6645SManish Chopra int i, rc; 2625464f6645SManish Chopra 2626464f6645SManish Chopra memset(&tunn_info, 0, sizeof(tunn_info)); 262719968430SChopra, Manish if (tunn_params->update_vxlan_port) { 262819968430SChopra, Manish tunn_info.vxlan_port.b_update_port = true; 262919968430SChopra, Manish tunn_info.vxlan_port.port = tunn_params->vxlan_port; 2630464f6645SManish Chopra } 2631464f6645SManish Chopra 263219968430SChopra, Manish if (tunn_params->update_geneve_port) { 263319968430SChopra, Manish tunn_info.geneve_port.b_update_port = true; 263419968430SChopra, Manish tunn_info.geneve_port.port = tunn_params->geneve_port; 2635464f6645SManish Chopra } 2636464f6645SManish Chopra 2637464f6645SManish Chopra for_each_hwfn(cdev, i) { 2638464f6645SManish Chopra struct qed_hwfn *hwfn = &cdev->hwfns[i]; 26394f64675fSManish Chopra struct qed_ptt *p_ptt; 264097379f15SChopra, Manish struct qed_tunnel_info *tun; 264197379f15SChopra, Manish 264297379f15SChopra, Manish tun = &hwfn->cdev->tunnel; 26434f64675fSManish Chopra if (IS_PF(cdev)) { 26444f64675fSManish Chopra p_ptt = qed_ptt_acquire(hwfn); 26454f64675fSManish Chopra if (!p_ptt) 26464f64675fSManish Chopra return -EAGAIN; 26474f64675fSManish Chopra } else { 26484f64675fSManish Chopra p_ptt = NULL; 26494f64675fSManish Chopra } 2650464f6645SManish Chopra 26514f64675fSManish Chopra rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info, 2652464f6645SManish Chopra QED_SPQ_MODE_EBLOCK, NULL); 26534f64675fSManish Chopra if (rc) { 26544f64675fSManish Chopra if (IS_PF(cdev)) 26554f64675fSManish Chopra qed_ptt_release(hwfn, p_ptt); 2656464f6645SManish Chopra return rc; 26574f64675fSManish Chopra } 265897379f15SChopra, Manish 265997379f15SChopra, Manish if (IS_PF_SRIOV(hwfn)) { 266097379f15SChopra, Manish u16 vxlan_port, geneve_port; 266197379f15SChopra, Manish int j; 266297379f15SChopra, Manish 266397379f15SChopra, Manish vxlan_port = tun->vxlan_port.port; 266497379f15SChopra, Manish geneve_port = tun->geneve_port.port; 266597379f15SChopra, Manish 266697379f15SChopra, Manish qed_for_each_vf(hwfn, j) { 266797379f15SChopra, Manish qed_iov_bulletin_set_udp_ports(hwfn, j, 266897379f15SChopra, Manish vxlan_port, 266997379f15SChopra, Manish geneve_port); 267097379f15SChopra, Manish } 267197379f15SChopra, Manish 267297379f15SChopra, Manish qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG); 267397379f15SChopra, Manish } 26744f64675fSManish Chopra if (IS_PF(cdev)) 26754f64675fSManish Chopra qed_ptt_release(hwfn, p_ptt); 2676464f6645SManish Chopra } 2677464f6645SManish Chopra 2678464f6645SManish Chopra return 0; 2679464f6645SManish Chopra } 2680464f6645SManish Chopra 2681cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 2682cee4d264SManish Chopra enum qed_filter_rx_mode_type type) 2683cee4d264SManish Chopra { 2684cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 2685cee4d264SManish Chopra 2686cee4d264SManish Chopra memset(&accept_flags, 0, sizeof(accept_flags)); 2687cee4d264SManish Chopra 2688cee4d264SManish Chopra accept_flags.update_rx_mode_config = 1; 2689cee4d264SManish Chopra accept_flags.update_tx_mode_config = 1; 2690cee4d264SManish Chopra accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2691cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2692cee4d264SManish Chopra QED_ACCEPT_BCAST; 2693cee4d264SManish Chopra accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2694cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2695cee4d264SManish Chopra QED_ACCEPT_BCAST; 2696cee4d264SManish Chopra 269788067876SMintz, Yuval if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 2698cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 2699cee4d264SManish Chopra QED_ACCEPT_MCAST_UNMATCHED; 27009e71a15dSManish Chopra accept_flags.tx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 27019e71a15dSManish Chopra QED_ACCEPT_MCAST_UNMATCHED; 270288067876SMintz, Yuval } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 2703cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 270488067876SMintz, Yuval accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 270588067876SMintz, Yuval } 2706cee4d264SManish Chopra 27073f9b4a69SYuval Mintz return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 2708cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 2709cee4d264SManish Chopra } 2710cee4d264SManish Chopra 2711cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev, 2712cee4d264SManish Chopra struct qed_filter_ucast_params *params) 2713cee4d264SManish Chopra { 2714cee4d264SManish Chopra struct qed_filter_ucast ucast; 2715cee4d264SManish Chopra 2716cee4d264SManish Chopra if (!params->vlan_valid && !params->mac_valid) { 27171a635e48SYuval Mintz DP_NOTICE(cdev, 2718cee4d264SManish Chopra "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 2719cee4d264SManish Chopra return -EINVAL; 2720cee4d264SManish Chopra } 2721cee4d264SManish Chopra 2722cee4d264SManish Chopra memset(&ucast, 0, sizeof(ucast)); 2723cee4d264SManish Chopra switch (params->type) { 2724cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2725cee4d264SManish Chopra ucast.opcode = QED_FILTER_ADD; 2726cee4d264SManish Chopra break; 2727cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2728cee4d264SManish Chopra ucast.opcode = QED_FILTER_REMOVE; 2729cee4d264SManish Chopra break; 2730cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_REPLACE: 2731cee4d264SManish Chopra ucast.opcode = QED_FILTER_REPLACE; 2732cee4d264SManish Chopra break; 2733cee4d264SManish Chopra default: 2734cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 2735cee4d264SManish Chopra params->type); 2736cee4d264SManish Chopra } 2737cee4d264SManish Chopra 2738cee4d264SManish Chopra if (params->vlan_valid && params->mac_valid) { 2739cee4d264SManish Chopra ucast.type = QED_FILTER_MAC_VLAN; 2740cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2741cee4d264SManish Chopra ucast.vlan = params->vlan; 2742cee4d264SManish Chopra } else if (params->mac_valid) { 2743cee4d264SManish Chopra ucast.type = QED_FILTER_MAC; 2744cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2745cee4d264SManish Chopra } else { 2746cee4d264SManish Chopra ucast.type = QED_FILTER_VLAN; 2747cee4d264SManish Chopra ucast.vlan = params->vlan; 2748cee4d264SManish Chopra } 2749cee4d264SManish Chopra 2750cee4d264SManish Chopra ucast.is_rx_filter = true; 2751cee4d264SManish Chopra ucast.is_tx_filter = true; 2752cee4d264SManish Chopra 2753cee4d264SManish Chopra return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 2754cee4d264SManish Chopra } 2755cee4d264SManish Chopra 2756cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev, 2757cee4d264SManish Chopra struct qed_filter_mcast_params *params) 2758cee4d264SManish Chopra { 2759cee4d264SManish Chopra struct qed_filter_mcast mcast; 2760cee4d264SManish Chopra int i; 2761cee4d264SManish Chopra 2762cee4d264SManish Chopra memset(&mcast, 0, sizeof(mcast)); 2763cee4d264SManish Chopra switch (params->type) { 2764cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2765cee4d264SManish Chopra mcast.opcode = QED_FILTER_ADD; 2766cee4d264SManish Chopra break; 2767cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2768cee4d264SManish Chopra mcast.opcode = QED_FILTER_REMOVE; 2769cee4d264SManish Chopra break; 2770cee4d264SManish Chopra default: 2771cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 2772cee4d264SManish Chopra params->type); 2773cee4d264SManish Chopra } 2774cee4d264SManish Chopra 2775cee4d264SManish Chopra mcast.num_mc_addrs = params->num; 2776cee4d264SManish Chopra for (i = 0; i < mcast.num_mc_addrs; i++) 2777cee4d264SManish Chopra ether_addr_copy(mcast.mac[i], params->mac[i]); 2778cee4d264SManish Chopra 27791a635e48SYuval Mintz return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL); 2780cee4d264SManish Chopra } 2781cee4d264SManish Chopra 2782cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev, 2783cee4d264SManish Chopra struct qed_filter_params *params) 2784cee4d264SManish Chopra { 2785cee4d264SManish Chopra enum qed_filter_rx_mode_type accept_flags; 2786cee4d264SManish Chopra 2787cee4d264SManish Chopra switch (params->type) { 2788cee4d264SManish Chopra case QED_FILTER_TYPE_UCAST: 2789cee4d264SManish Chopra return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 2790cee4d264SManish Chopra case QED_FILTER_TYPE_MCAST: 2791cee4d264SManish Chopra return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 2792cee4d264SManish Chopra case QED_FILTER_TYPE_RX_MODE: 2793cee4d264SManish Chopra accept_flags = params->filter.accept_flags; 2794cee4d264SManish Chopra return qed_configure_filter_rx_mode(cdev, accept_flags); 2795cee4d264SManish Chopra default: 27961a635e48SYuval Mintz DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type); 2797cee4d264SManish Chopra return -EINVAL; 2798cee4d264SManish Chopra } 2799cee4d264SManish Chopra } 2800cee4d264SManish Chopra 2801da090917STomer Tayar static int qed_configure_arfs_searcher(struct qed_dev *cdev, 2802da090917STomer Tayar enum qed_filter_config_mode mode) 2803d51e4af5SChopra, Manish { 2804d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2805d51e4af5SChopra, Manish struct qed_arfs_config_params arfs_config_params; 2806d51e4af5SChopra, Manish 2807d51e4af5SChopra, Manish memset(&arfs_config_params, 0, sizeof(arfs_config_params)); 2808d51e4af5SChopra, Manish arfs_config_params.tcp = true; 2809d51e4af5SChopra, Manish arfs_config_params.udp = true; 2810d51e4af5SChopra, Manish arfs_config_params.ipv4 = true; 2811d51e4af5SChopra, Manish arfs_config_params.ipv6 = true; 2812da090917STomer Tayar arfs_config_params.mode = mode; 2813d51e4af5SChopra, Manish qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt, 2814d51e4af5SChopra, Manish &arfs_config_params); 2815d51e4af5SChopra, Manish return 0; 2816d51e4af5SChopra, Manish } 2817d51e4af5SChopra, Manish 2818d51e4af5SChopra, Manish static void 2819d51e4af5SChopra, Manish qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn, 2820da090917STomer Tayar void *cookie, 2821da090917STomer Tayar union event_ring_data *data, u8 fw_return_code) 2822d51e4af5SChopra, Manish { 2823d51e4af5SChopra, Manish struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common; 2824d51e4af5SChopra, Manish void *dev = p_hwfn->cdev->ops_cookie; 2825d51e4af5SChopra, Manish 2826d51e4af5SChopra, Manish op->arfs_filter_op(dev, cookie, fw_return_code); 2827d51e4af5SChopra, Manish } 2828d51e4af5SChopra, Manish 2829da090917STomer Tayar static int 2830da090917STomer Tayar qed_ntuple_arfs_filter_config(struct qed_dev *cdev, 2831da090917STomer Tayar void *cookie, 2832da090917STomer Tayar struct qed_ntuple_filter_params *params) 2833d51e4af5SChopra, Manish { 2834d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2835d51e4af5SChopra, Manish struct qed_spq_comp_cb cb; 2836d51e4af5SChopra, Manish int rc = -EINVAL; 2837d51e4af5SChopra, Manish 2838d51e4af5SChopra, Manish cb.function = qed_arfs_sp_response_handler; 2839d51e4af5SChopra, Manish cb.cookie = cookie; 2840d51e4af5SChopra, Manish 2841da090917STomer Tayar if (params->b_is_vf) { 2842da090917STomer Tayar if (!qed_iov_is_valid_vfid(p_hwfn, params->vf_id, false, 2843da090917STomer Tayar false)) { 2844da090917STomer Tayar DP_INFO(p_hwfn, "vfid 0x%02x is out of bounds\n", 2845da090917STomer Tayar params->vf_id); 2846da090917STomer Tayar return rc; 2847da090917STomer Tayar } 2848da090917STomer Tayar 2849da090917STomer Tayar params->vport_id = params->vf_id + 1; 2850da090917STomer Tayar params->qid = QED_RFS_NTUPLE_QID_RSS; 2851da090917STomer Tayar } 2852da090917STomer Tayar 2853da090917STomer Tayar rc = qed_configure_rfs_ntuple_filter(p_hwfn, &cb, params); 2854d51e4af5SChopra, Manish if (rc) 2855d51e4af5SChopra, Manish DP_NOTICE(p_hwfn, 2856d51e4af5SChopra, Manish "Failed to issue a-RFS filter configuration\n"); 2857d51e4af5SChopra, Manish else 2858d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, 2859d51e4af5SChopra, Manish "Successfully issued a-RFS filter configuration\n"); 2860d51e4af5SChopra, Manish 2861d51e4af5SChopra, Manish return rc; 2862d51e4af5SChopra, Manish } 2863d51e4af5SChopra, Manish 2864bf5a94bfSRahul Verma static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle) 2865bf5a94bfSRahul Verma { 2866bf5a94bfSRahul Verma struct qed_queue_cid *p_cid = handle; 2867bf5a94bfSRahul Verma struct qed_hwfn *p_hwfn; 2868bf5a94bfSRahul Verma int rc; 2869bf5a94bfSRahul Verma 2870bf5a94bfSRahul Verma p_hwfn = p_cid->p_owner; 2871bf5a94bfSRahul Verma rc = qed_get_queue_coalesce(p_hwfn, coal, handle); 2872bf5a94bfSRahul Verma if (rc) 28739e4a5613SColin Ian King DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n"); 2874bf5a94bfSRahul Verma 2875bf5a94bfSRahul Verma return rc; 2876bf5a94bfSRahul Verma } 2877bf5a94bfSRahul Verma 2878cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev, 28791a635e48SYuval Mintz u8 rss_id, struct eth_slow_path_rx_cqe *cqe) 2880cee4d264SManish Chopra { 2881cee4d264SManish Chopra return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 2882cee4d264SManish Chopra cqe); 2883cee4d264SManish Chopra } 2884cee4d264SManish Chopra 2885809c45a0SShahed Shaikh static int qed_req_bulletin_update_mac(struct qed_dev *cdev, u8 *mac) 2886809c45a0SShahed Shaikh { 2887809c45a0SShahed Shaikh int i, ret; 2888809c45a0SShahed Shaikh 2889809c45a0SShahed Shaikh if (IS_PF(cdev)) 2890809c45a0SShahed Shaikh return 0; 2891809c45a0SShahed Shaikh 2892809c45a0SShahed Shaikh for_each_hwfn(cdev, i) { 2893809c45a0SShahed Shaikh struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2894809c45a0SShahed Shaikh 2895809c45a0SShahed Shaikh ret = qed_vf_pf_bulletin_update_mac(p_hwfn, mac); 2896809c45a0SShahed Shaikh if (ret) 2897809c45a0SShahed Shaikh return ret; 2898809c45a0SShahed Shaikh } 2899809c45a0SShahed Shaikh 2900809c45a0SShahed Shaikh return 0; 2901809c45a0SShahed Shaikh } 2902809c45a0SShahed Shaikh 29030b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 29040b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass; 29050b55e27dSYuval Mintz #endif 29060b55e27dSYuval Mintz 2907a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2908a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass; 2909a1d8d8a5SSudarsana Reddy Kalluru #endif 2910a1d8d8a5SSudarsana Reddy Kalluru 2911c78c70faSSudarsana Reddy Kalluru extern const struct qed_eth_ptp_ops qed_ptp_ops_pass; 2912c78c70faSSudarsana Reddy Kalluru 291325c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = { 291425c089d7SYuval Mintz .common = &qed_common_ops_pass, 29150b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 29160b55e27dSYuval Mintz .iov = &qed_iov_ops_pass, 29170b55e27dSYuval Mintz #endif 2918a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2919a1d8d8a5SSudarsana Reddy Kalluru .dcb = &qed_dcbnl_ops_pass, 2920a1d8d8a5SSudarsana Reddy Kalluru #endif 2921c78c70faSSudarsana Reddy Kalluru .ptp = &qed_ptp_ops_pass, 292225c089d7SYuval Mintz .fill_dev_info = &qed_fill_eth_dev_info, 2923cc875c2eSYuval Mintz .register_ops = &qed_register_eth_ops, 2924eff16960SYuval Mintz .check_mac = &qed_check_mac, 2925cee4d264SManish Chopra .vport_start = &qed_start_vport, 2926cee4d264SManish Chopra .vport_stop = &qed_stop_vport, 2927cee4d264SManish Chopra .vport_update = &qed_update_vport, 2928cee4d264SManish Chopra .q_rx_start = &qed_start_rxq, 2929cee4d264SManish Chopra .q_rx_stop = &qed_stop_rxq, 2930cee4d264SManish Chopra .q_tx_start = &qed_start_txq, 2931cee4d264SManish Chopra .q_tx_stop = &qed_stop_txq, 2932cee4d264SManish Chopra .filter_config = &qed_configure_filter, 2933cee4d264SManish Chopra .fastpath_stop = &qed_fastpath_stop, 2934cee4d264SManish Chopra .eth_cqe_completion = &qed_fp_cqe_completion, 29359df2ed04SManish Chopra .get_vport_stats = &qed_get_vport_stats, 2936464f6645SManish Chopra .tunn_config = &qed_tunn_configure, 2937d51e4af5SChopra, Manish .ntuple_filter_config = &qed_ntuple_arfs_filter_config, 2938d51e4af5SChopra, Manish .configure_arfs_searcher = &qed_configure_arfs_searcher, 2939bf5a94bfSRahul Verma .get_coalesce = &qed_get_coalesce, 2940809c45a0SShahed Shaikh .req_bulletin_update_mac = &qed_req_bulletin_update_mac, 294125c089d7SYuval Mintz }; 294225c089d7SYuval Mintz 294395114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void) 294425c089d7SYuval Mintz { 294525c089d7SYuval Mintz return &qed_eth_ops_pass; 294625c089d7SYuval Mintz } 294725c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops); 294825c089d7SYuval Mintz 294925c089d7SYuval Mintz void qed_put_eth_ops(void) 295025c089d7SYuval Mintz { 295125c089d7SYuval Mintz /* TODO - reference count for module? */ 295225c089d7SYuval Mintz } 295325c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops); 2954