125c089d7SYuval Mintz /* QLogic qed NIC Driver
2e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
325c089d7SYuval Mintz  *
4e8f1cb50SMintz, Yuval  * This software is available to you under a choice of one of two
5e8f1cb50SMintz, Yuval  * licenses.  You may choose to be licensed under the terms of the GNU
6e8f1cb50SMintz, Yuval  * General Public License (GPL) Version 2, available from the file
7e8f1cb50SMintz, Yuval  * COPYING in the main directory of this source tree, or the
8e8f1cb50SMintz, Yuval  * OpenIB.org BSD license below:
9e8f1cb50SMintz, Yuval  *
10e8f1cb50SMintz, Yuval  *     Redistribution and use in source and binary forms, with or
11e8f1cb50SMintz, Yuval  *     without modification, are permitted provided that the following
12e8f1cb50SMintz, Yuval  *     conditions are met:
13e8f1cb50SMintz, Yuval  *
14e8f1cb50SMintz, Yuval  *      - Redistributions of source code must retain the above
15e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
16e8f1cb50SMintz, Yuval  *        disclaimer.
17e8f1cb50SMintz, Yuval  *
18e8f1cb50SMintz, Yuval  *      - Redistributions in binary form must reproduce the above
19e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
20e8f1cb50SMintz, Yuval  *        disclaimer in the documentation and /or other materials
21e8f1cb50SMintz, Yuval  *        provided with the distribution.
22e8f1cb50SMintz, Yuval  *
23e8f1cb50SMintz, Yuval  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24e8f1cb50SMintz, Yuval  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25e8f1cb50SMintz, Yuval  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26e8f1cb50SMintz, Yuval  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27e8f1cb50SMintz, Yuval  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28e8f1cb50SMintz, Yuval  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29e8f1cb50SMintz, Yuval  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30e8f1cb50SMintz, Yuval  * SOFTWARE.
3125c089d7SYuval Mintz  */
3225c089d7SYuval Mintz 
3325c089d7SYuval Mintz #include <linux/types.h>
3425c089d7SYuval Mintz #include <asm/byteorder.h>
3525c089d7SYuval Mintz #include <asm/param.h>
3625c089d7SYuval Mintz #include <linux/delay.h>
3725c089d7SYuval Mintz #include <linux/dma-mapping.h>
3825c089d7SYuval Mintz #include <linux/etherdevice.h>
3925c089d7SYuval Mintz #include <linux/interrupt.h>
4025c089d7SYuval Mintz #include <linux/kernel.h>
4125c089d7SYuval Mintz #include <linux/module.h>
4225c089d7SYuval Mintz #include <linux/pci.h>
4325c089d7SYuval Mintz #include <linux/slab.h>
4425c089d7SYuval Mintz #include <linux/stddef.h>
4525c089d7SYuval Mintz #include <linux/string.h>
4625c089d7SYuval Mintz #include <linux/version.h>
4725c089d7SYuval Mintz #include <linux/workqueue.h>
4825c089d7SYuval Mintz #include <linux/bitops.h>
4925c089d7SYuval Mintz #include <linux/bug.h>
503da7a37aSMintz, Yuval #include <linux/vmalloc.h>
5125c089d7SYuval Mintz #include "qed.h"
5225c089d7SYuval Mintz #include <linux/qed/qed_chain.h>
5325c089d7SYuval Mintz #include "qed_cxt.h"
5425c089d7SYuval Mintz #include "qed_dev_api.h"
5525c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h>
5625c089d7SYuval Mintz #include "qed_hsi.h"
5725c089d7SYuval Mintz #include "qed_hw.h"
5825c089d7SYuval Mintz #include "qed_int.h"
59dacd88d6SYuval Mintz #include "qed_l2.h"
6086622ee7SYuval Mintz #include "qed_mcp.h"
6125c089d7SYuval Mintz #include "qed_reg_addr.h"
6225c089d7SYuval Mintz #include "qed_sp.h"
631408cc1fSYuval Mintz #include "qed_sriov.h"
6425c089d7SYuval Mintz 
65088c8618SManish Chopra 
66cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16
67cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41
68cee4d264SManish Chopra 
693da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
703da7a37aSMintz, Yuval 			       struct qed_queue_cid *p_cid)
713da7a37aSMintz, Yuval {
723da7a37aSMintz, Yuval 	/* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */
733da7a37aSMintz, Yuval 	if (!p_cid->is_vf && IS_PF(p_hwfn->cdev))
743da7a37aSMintz, Yuval 		qed_cxt_release_cid(p_hwfn, p_cid->cid);
753da7a37aSMintz, Yuval 	vfree(p_cid);
763da7a37aSMintz, Yuval }
773da7a37aSMintz, Yuval 
783da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs
793da7a37aSMintz, Yuval  * for their VFs.
803da7a37aSMintz, Yuval  */
813da7a37aSMintz, Yuval struct qed_queue_cid *
823da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
833da7a37aSMintz, Yuval 		      u16 opaque_fid,
843da7a37aSMintz, Yuval 		      u32 cid,
853da7a37aSMintz, Yuval 		      u8 vf_qid,
863da7a37aSMintz, Yuval 		      struct qed_queue_start_common_params *p_params)
873da7a37aSMintz, Yuval {
883da7a37aSMintz, Yuval 	bool b_is_same = (p_hwfn->hw_info.opaque_fid == opaque_fid);
893da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
903da7a37aSMintz, Yuval 	int rc;
913da7a37aSMintz, Yuval 
923da7a37aSMintz, Yuval 	p_cid = vmalloc(sizeof(*p_cid));
933da7a37aSMintz, Yuval 	if (!p_cid)
943da7a37aSMintz, Yuval 		return NULL;
953da7a37aSMintz, Yuval 	memset(p_cid, 0, sizeof(*p_cid));
963da7a37aSMintz, Yuval 
973da7a37aSMintz, Yuval 	p_cid->opaque_fid = opaque_fid;
983da7a37aSMintz, Yuval 	p_cid->cid = cid;
993da7a37aSMintz, Yuval 	p_cid->vf_qid = vf_qid;
1003da7a37aSMintz, Yuval 	p_cid->rel = *p_params;
101f29ffdb6SMintz, Yuval 	p_cid->p_owner = p_hwfn;
1023da7a37aSMintz, Yuval 
1033da7a37aSMintz, Yuval 	/* Don't try calculating the absolute indices for VFs */
1043da7a37aSMintz, Yuval 	if (IS_VF(p_hwfn->cdev)) {
1053da7a37aSMintz, Yuval 		p_cid->abs = p_cid->rel;
1063da7a37aSMintz, Yuval 		goto out;
1073da7a37aSMintz, Yuval 	}
1083da7a37aSMintz, Yuval 
1093da7a37aSMintz, Yuval 	/* Calculate the engine-absolute indices of the resources.
1103da7a37aSMintz, Yuval 	 * This would guarantee they're valid later on.
1113da7a37aSMintz, Yuval 	 * In some cases [SBs] we already have the right values.
1123da7a37aSMintz, Yuval 	 */
1133da7a37aSMintz, Yuval 	rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
1143da7a37aSMintz, Yuval 	if (rc)
1153da7a37aSMintz, Yuval 		goto fail;
1163da7a37aSMintz, Yuval 
1173da7a37aSMintz, Yuval 	rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
1183da7a37aSMintz, Yuval 	if (rc)
1193da7a37aSMintz, Yuval 		goto fail;
1203da7a37aSMintz, Yuval 
1213da7a37aSMintz, Yuval 	/* In case of a PF configuring its VF's queues, the stats-id is already
1223da7a37aSMintz, Yuval 	 * absolute [since there's a single index that's suitable per-VF].
1233da7a37aSMintz, Yuval 	 */
1243da7a37aSMintz, Yuval 	if (b_is_same) {
1253da7a37aSMintz, Yuval 		rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
1263da7a37aSMintz, Yuval 				  &p_cid->abs.stats_id);
1273da7a37aSMintz, Yuval 		if (rc)
1283da7a37aSMintz, Yuval 			goto fail;
1293da7a37aSMintz, Yuval 	} else {
1303da7a37aSMintz, Yuval 		p_cid->abs.stats_id = p_cid->rel.stats_id;
1313da7a37aSMintz, Yuval 	}
1323da7a37aSMintz, Yuval 
1333da7a37aSMintz, Yuval 	/* SBs relevant information was already provided as absolute */
1343da7a37aSMintz, Yuval 	p_cid->abs.sb = p_cid->rel.sb;
1353da7a37aSMintz, Yuval 	p_cid->abs.sb_idx = p_cid->rel.sb_idx;
1363da7a37aSMintz, Yuval 
1373da7a37aSMintz, Yuval 	/* This is tricky - we're actually interested in whehter this is a PF
1383da7a37aSMintz, Yuval 	 * entry meant for the VF.
1393da7a37aSMintz, Yuval 	 */
1403da7a37aSMintz, Yuval 	if (!b_is_same)
1413da7a37aSMintz, Yuval 		p_cid->is_vf = true;
1423da7a37aSMintz, Yuval out:
1433da7a37aSMintz, Yuval 	DP_VERBOSE(p_hwfn,
1443da7a37aSMintz, Yuval 		   QED_MSG_SP,
1453da7a37aSMintz, Yuval 		   "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
1463da7a37aSMintz, Yuval 		   p_cid->opaque_fid,
1473da7a37aSMintz, Yuval 		   p_cid->cid,
1483da7a37aSMintz, Yuval 		   p_cid->rel.vport_id,
1493da7a37aSMintz, Yuval 		   p_cid->abs.vport_id,
1503da7a37aSMintz, Yuval 		   p_cid->rel.queue_id,
1513da7a37aSMintz, Yuval 		   p_cid->abs.queue_id,
1523da7a37aSMintz, Yuval 		   p_cid->rel.stats_id,
1533da7a37aSMintz, Yuval 		   p_cid->abs.stats_id, p_cid->abs.sb, p_cid->abs.sb_idx);
1543da7a37aSMintz, Yuval 
1553da7a37aSMintz, Yuval 	return p_cid;
1563da7a37aSMintz, Yuval 
1573da7a37aSMintz, Yuval fail:
1583da7a37aSMintz, Yuval 	vfree(p_cid);
1593da7a37aSMintz, Yuval 	return NULL;
1603da7a37aSMintz, Yuval }
1613da7a37aSMintz, Yuval 
1623da7a37aSMintz, Yuval static struct qed_queue_cid *qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
1633da7a37aSMintz, Yuval 						  u16 opaque_fid, struct
1643da7a37aSMintz, Yuval 						  qed_queue_start_common_params
1653da7a37aSMintz, Yuval 						  *p_params)
1663da7a37aSMintz, Yuval {
1673da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
1683da7a37aSMintz, Yuval 	u32 cid = 0;
1693da7a37aSMintz, Yuval 
1703da7a37aSMintz, Yuval 	/* Get a unique firmware CID for this queue, in case it's a PF.
1713da7a37aSMintz, Yuval 	 * VF's don't need a CID as the queue configuration will be done
1723da7a37aSMintz, Yuval 	 * by PF.
1733da7a37aSMintz, Yuval 	 */
1743da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
1753da7a37aSMintz, Yuval 		if (qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &cid)) {
1763da7a37aSMintz, Yuval 			DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
1773da7a37aSMintz, Yuval 			return NULL;
1783da7a37aSMintz, Yuval 		}
1793da7a37aSMintz, Yuval 	}
1803da7a37aSMintz, Yuval 
1813da7a37aSMintz, Yuval 	p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 0, p_params);
1823da7a37aSMintz, Yuval 	if (!p_cid && IS_PF(p_hwfn->cdev))
1833da7a37aSMintz, Yuval 		qed_cxt_release_cid(p_hwfn, cid);
1843da7a37aSMintz, Yuval 
1853da7a37aSMintz, Yuval 	return p_cid;
1863da7a37aSMintz, Yuval }
1873da7a37aSMintz, Yuval 
188dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
189088c8618SManish Chopra 			   struct qed_sp_vport_start_params *p_params)
190cee4d264SManish Chopra {
191cee4d264SManish Chopra 	struct vport_start_ramrod_data *p_ramrod = NULL;
192cee4d264SManish Chopra 	struct qed_spq_entry *p_ent =  NULL;
19306f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
194dacd88d6SYuval Mintz 	u8 abs_vport_id = 0;
195cee4d264SManish Chopra 	int rc = -EINVAL;
196cee4d264SManish Chopra 	u16 rx_mode = 0;
197cee4d264SManish Chopra 
198088c8618SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1991a635e48SYuval Mintz 	if (rc)
200cee4d264SManish Chopra 		return rc;
201cee4d264SManish Chopra 
20206f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
20306f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
204088c8618SManish Chopra 	init_data.opaque_fid = p_params->opaque_fid;
20506f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
206cee4d264SManish Chopra 
207cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
208cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_START,
20906f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
210cee4d264SManish Chopra 	if (rc)
211cee4d264SManish Chopra 		return rc;
212cee4d264SManish Chopra 
213cee4d264SManish Chopra 	p_ramrod		= &p_ent->ramrod.vport_start;
214cee4d264SManish Chopra 	p_ramrod->vport_id	= abs_vport_id;
215cee4d264SManish Chopra 
216088c8618SManish Chopra 	p_ramrod->mtu			= cpu_to_le16(p_params->mtu);
217088c8618SManish Chopra 	p_ramrod->inner_vlan_removal_en	= p_params->remove_inner_vlan;
218088c8618SManish Chopra 	p_ramrod->drop_ttl0_en		= p_params->drop_ttl0;
219e6bd8923SYuval Mintz 	p_ramrod->untagged		= p_params->only_untagged;
220cee4d264SManish Chopra 
221cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
222cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
223cee4d264SManish Chopra 
224cee4d264SManish Chopra 	p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
225cee4d264SManish Chopra 
226cee4d264SManish Chopra 	/* TPA related fields */
2271a635e48SYuval Mintz 	memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
228cee4d264SManish Chopra 
229088c8618SManish Chopra 	p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
230088c8618SManish Chopra 
231088c8618SManish Chopra 	switch (p_params->tpa_mode) {
232088c8618SManish Chopra 	case QED_TPA_MODE_GRO:
233088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
234088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_size = (u16)-1;
235088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
236088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
237088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
238088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
239088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
240088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
241088c8618SManish Chopra 		break;
242088c8618SManish Chopra 	default:
243088c8618SManish Chopra 		break;
244088c8618SManish Chopra 	}
245088c8618SManish Chopra 
246831bfb0eSYuval Mintz 	p_ramrod->tx_switching_en = p_params->tx_switching;
247831bfb0eSYuval Mintz 
24811a85d75SYuval Mintz 	p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
24911a85d75SYuval Mintz 	p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
25011a85d75SYuval Mintz 
251cee4d264SManish Chopra 	/* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
252cee4d264SManish Chopra 	p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
253088c8618SManish Chopra 						  p_params->concrete_fid);
254cee4d264SManish Chopra 
255cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
256cee4d264SManish Chopra }
257cee4d264SManish Chopra 
258ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
259dacd88d6SYuval Mintz 			      struct qed_sp_vport_start_params *p_params)
260dacd88d6SYuval Mintz {
261dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
262dacd88d6SYuval Mintz 		return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
263dacd88d6SYuval Mintz 					     p_params->mtu,
264dacd88d6SYuval Mintz 					     p_params->remove_inner_vlan,
265dacd88d6SYuval Mintz 					     p_params->tpa_mode,
26608feecd7SYuval Mintz 					     p_params->max_buffers_per_cqe,
26708feecd7SYuval Mintz 					     p_params->only_untagged);
268dacd88d6SYuval Mintz 	}
269dacd88d6SYuval Mintz 
270dacd88d6SYuval Mintz 	return qed_sp_eth_vport_start(p_hwfn, p_params);
271dacd88d6SYuval Mintz }
272dacd88d6SYuval Mintz 
273cee4d264SManish Chopra static int
274cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
275cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
276f29ffdb6SMintz, Yuval 			struct qed_rss_params *p_rss)
277cee4d264SManish Chopra {
278f29ffdb6SMintz, Yuval 	struct eth_vport_rss_config *p_config;
279f29ffdb6SMintz, Yuval 	u16 capabilities = 0;
280f29ffdb6SMintz, Yuval 	int i, table_size;
281f29ffdb6SMintz, Yuval 	int rc = 0;
282cee4d264SManish Chopra 
283f29ffdb6SMintz, Yuval 	if (!p_rss) {
284cee4d264SManish Chopra 		p_ramrod->common.update_rss_flg = 0;
285cee4d264SManish Chopra 		return rc;
286cee4d264SManish Chopra 	}
287f29ffdb6SMintz, Yuval 	p_config = &p_ramrod->rss_config;
288cee4d264SManish Chopra 
289f29ffdb6SMintz, Yuval 	BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
290cee4d264SManish Chopra 
291f29ffdb6SMintz, Yuval 	rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
292cee4d264SManish Chopra 	if (rc)
293cee4d264SManish Chopra 		return rc;
294cee4d264SManish Chopra 
295f29ffdb6SMintz, Yuval 	p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
296f29ffdb6SMintz, Yuval 	p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
297f29ffdb6SMintz, Yuval 	p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
298f29ffdb6SMintz, Yuval 	p_config->update_rss_key = p_rss->update_rss_key;
299cee4d264SManish Chopra 
300f29ffdb6SMintz, Yuval 	p_config->rss_mode = p_rss->rss_enable ?
301cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_REGULAR :
302cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_DISABLED;
303cee4d264SManish Chopra 
304cee4d264SManish Chopra 	SET_FIELD(capabilities,
305cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
306f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4));
307cee4d264SManish Chopra 	SET_FIELD(capabilities,
308cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
309f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6));
310cee4d264SManish Chopra 	SET_FIELD(capabilities,
311cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
312f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
313cee4d264SManish Chopra 	SET_FIELD(capabilities,
314cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
315f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
316cee4d264SManish Chopra 	SET_FIELD(capabilities,
317cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
318f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
319cee4d264SManish Chopra 	SET_FIELD(capabilities,
320cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
321f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
322f29ffdb6SMintz, Yuval 	p_config->tbl_size = p_rss->rss_table_size_log;
323cee4d264SManish Chopra 
324f29ffdb6SMintz, Yuval 	p_config->capabilities = cpu_to_le16(capabilities);
325cee4d264SManish Chopra 
326cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
327cee4d264SManish Chopra 		   "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
328cee4d264SManish Chopra 		   p_ramrod->common.update_rss_flg,
329f29ffdb6SMintz, Yuval 		   p_config->rss_mode,
330f29ffdb6SMintz, Yuval 		   p_config->update_rss_capabilities,
331f29ffdb6SMintz, Yuval 		   p_config->capabilities,
332f29ffdb6SMintz, Yuval 		   p_config->update_rss_ind_table, p_config->update_rss_key);
333cee4d264SManish Chopra 
334f29ffdb6SMintz, Yuval 	table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
335f29ffdb6SMintz, Yuval 			   1 << p_config->tbl_size);
336f29ffdb6SMintz, Yuval 	for (i = 0; i < table_size; i++) {
337f29ffdb6SMintz, Yuval 		struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
338cee4d264SManish Chopra 
339f29ffdb6SMintz, Yuval 		if (!p_queue)
340f29ffdb6SMintz, Yuval 			return -EINVAL;
341f29ffdb6SMintz, Yuval 
342f29ffdb6SMintz, Yuval 		p_config->indirection_table[i] =
343f29ffdb6SMintz, Yuval 		    cpu_to_le16(p_queue->abs.queue_id);
344f29ffdb6SMintz, Yuval 	}
345f29ffdb6SMintz, Yuval 
346f29ffdb6SMintz, Yuval 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
347f29ffdb6SMintz, Yuval 		   "Configured RSS indirection table [%d entries]:\n",
348f29ffdb6SMintz, Yuval 		   table_size);
349f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
350f29ffdb6SMintz, Yuval 		DP_VERBOSE(p_hwfn,
351f29ffdb6SMintz, Yuval 			   NETIF_MSG_IFUP,
352f29ffdb6SMintz, Yuval 			   "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
353f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i]),
354f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 1]),
355f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 2]),
356f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 3]),
357f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 4]),
358f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 5]),
359f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 6]),
360f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 7]),
361f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 8]),
362f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 9]),
363f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 10]),
364f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 11]),
365f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 12]),
366f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 13]),
367f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 14]),
368f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 15]));
369cee4d264SManish Chopra 	}
370cee4d264SManish Chopra 
371cee4d264SManish Chopra 	for (i = 0; i < 10; i++)
372f29ffdb6SMintz, Yuval 		p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
373cee4d264SManish Chopra 
374cee4d264SManish Chopra 	return rc;
375cee4d264SManish Chopra }
376cee4d264SManish Chopra 
377cee4d264SManish Chopra static void
378cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
379cee4d264SManish Chopra 			  struct vport_update_ramrod_data *p_ramrod,
380cee4d264SManish Chopra 			  struct qed_filter_accept_flags accept_flags)
381cee4d264SManish Chopra {
382cee4d264SManish Chopra 	p_ramrod->common.update_rx_mode_flg =
383cee4d264SManish Chopra 		accept_flags.update_rx_mode_config;
384cee4d264SManish Chopra 
385cee4d264SManish Chopra 	p_ramrod->common.update_tx_mode_flg =
386cee4d264SManish Chopra 		accept_flags.update_tx_mode_config;
387cee4d264SManish Chopra 
388cee4d264SManish Chopra 	/* Set Rx mode accept flags */
389cee4d264SManish Chopra 	if (p_ramrod->common.update_rx_mode_flg) {
390cee4d264SManish Chopra 		u8 accept_filter = accept_flags.rx_accept_filter;
391cee4d264SManish Chopra 		u16 state = 0;
392cee4d264SManish Chopra 
393cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
394cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
395cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
396cee4d264SManish Chopra 
397cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
398cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
399cee4d264SManish Chopra 
400cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
401cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
402cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
403cee4d264SManish Chopra 
404cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
405cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
406cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
407cee4d264SManish Chopra 
408cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
409cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
410cee4d264SManish Chopra 
411cee4d264SManish Chopra 		p_ramrod->rx_mode.state = cpu_to_le16(state);
412cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
413cee4d264SManish Chopra 			   "p_ramrod->rx_mode.state = 0x%x\n", state);
414cee4d264SManish Chopra 	}
415cee4d264SManish Chopra 
416cee4d264SManish Chopra 	/* Set Tx mode accept flags */
417cee4d264SManish Chopra 	if (p_ramrod->common.update_tx_mode_flg) {
418cee4d264SManish Chopra 		u8 accept_filter = accept_flags.tx_accept_filter;
419cee4d264SManish Chopra 		u16 state = 0;
420cee4d264SManish Chopra 
421cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
422cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
423cee4d264SManish Chopra 
424cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
425cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
426cee4d264SManish Chopra 
427cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
428cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
429cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
430cee4d264SManish Chopra 
431cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
432cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
433cee4d264SManish Chopra 
434cee4d264SManish Chopra 		p_ramrod->tx_mode.state = cpu_to_le16(state);
435cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
436cee4d264SManish Chopra 			   "p_ramrod->tx_mode.state = 0x%x\n", state);
437cee4d264SManish Chopra 	}
438cee4d264SManish Chopra }
439cee4d264SManish Chopra 
440cee4d264SManish Chopra static void
44117b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
44217b235c1SYuval Mintz 			    struct vport_update_ramrod_data *p_ramrod,
44317b235c1SYuval Mintz 			    struct qed_sge_tpa_params *p_params)
44417b235c1SYuval Mintz {
44517b235c1SYuval Mintz 	struct eth_vport_tpa_param *p_tpa;
44617b235c1SYuval Mintz 
44717b235c1SYuval Mintz 	if (!p_params) {
44817b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
44917b235c1SYuval Mintz 		p_ramrod->common.update_tpa_en_flg = 0;
45017b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
45117b235c1SYuval Mintz 		return;
45217b235c1SYuval Mintz 	}
45317b235c1SYuval Mintz 
45417b235c1SYuval Mintz 	p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
45517b235c1SYuval Mintz 	p_tpa = &p_ramrod->tpa_param;
45617b235c1SYuval Mintz 	p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
45717b235c1SYuval Mintz 	p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
45817b235c1SYuval Mintz 	p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
45917b235c1SYuval Mintz 	p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
46017b235c1SYuval Mintz 
46117b235c1SYuval Mintz 	p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
46217b235c1SYuval Mintz 	p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
46317b235c1SYuval Mintz 	p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
46417b235c1SYuval Mintz 	p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
46517b235c1SYuval Mintz 	p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
46617b235c1SYuval Mintz 	p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
46717b235c1SYuval Mintz 	p_tpa->tpa_max_size = p_params->tpa_max_size;
46817b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
46917b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
47017b235c1SYuval Mintz }
47117b235c1SYuval Mintz 
47217b235c1SYuval Mintz static void
473cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
474cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
475cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params)
476cee4d264SManish Chopra {
477cee4d264SManish Chopra 	int i;
478cee4d264SManish Chopra 
479cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
480cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
481cee4d264SManish Chopra 
48283aeb933SYuval Mintz 	if (!p_params->update_approx_mcast_flg)
48383aeb933SYuval Mintz 		return;
48483aeb933SYuval Mintz 
485cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
486cee4d264SManish Chopra 	for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
487cee4d264SManish Chopra 		u32 *p_bins = (u32 *)p_params->bins;
488cee4d264SManish Chopra 
48983aeb933SYuval Mintz 		p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
490cee4d264SManish Chopra 	}
491cee4d264SManish Chopra }
492cee4d264SManish Chopra 
493dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
494cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params,
495cee4d264SManish Chopra 			enum spq_mode comp_mode,
496cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
497cee4d264SManish Chopra {
498cee4d264SManish Chopra 	struct qed_rss_params *p_rss_params = p_params->rss_params;
499cee4d264SManish Chopra 	struct vport_update_ramrod_data_cmn *p_cmn;
50006f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
501cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
502cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
50317b235c1SYuval Mintz 	u8 abs_vport_id = 0, val;
504cee4d264SManish Chopra 	int rc = -EINVAL;
505cee4d264SManish Chopra 
506dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
507dacd88d6SYuval Mintz 		rc = qed_vf_pf_vport_update(p_hwfn, p_params);
508dacd88d6SYuval Mintz 		return rc;
509dacd88d6SYuval Mintz 	}
510dacd88d6SYuval Mintz 
511cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
5121a635e48SYuval Mintz 	if (rc)
513cee4d264SManish Chopra 		return rc;
514cee4d264SManish Chopra 
51506f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
51606f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
51706f56b81SYuval Mintz 	init_data.opaque_fid = p_params->opaque_fid;
51806f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
51906f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
520cee4d264SManish Chopra 
521cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
522cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
52306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
524cee4d264SManish Chopra 	if (rc)
525cee4d264SManish Chopra 		return rc;
526cee4d264SManish Chopra 
527cee4d264SManish Chopra 	/* Copy input params to ramrod according to FW struct */
528cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
529cee4d264SManish Chopra 	p_cmn = &p_ramrod->common;
530cee4d264SManish Chopra 
531cee4d264SManish Chopra 	p_cmn->vport_id = abs_vport_id;
532cee4d264SManish Chopra 	p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
533cee4d264SManish Chopra 	p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
534cee4d264SManish Chopra 	p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
535cee4d264SManish Chopra 	p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
5363f9b4a69SYuval Mintz 	p_cmn->accept_any_vlan = p_params->accept_any_vlan;
53783aeb933SYuval Mintz 	val = p_params->update_accept_any_vlan_flg;
53883aeb933SYuval Mintz 	p_cmn->update_accept_any_vlan_flg = val;
53917b235c1SYuval Mintz 
54017b235c1SYuval Mintz 	p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
54117b235c1SYuval Mintz 	val = p_params->update_inner_vlan_removal_flg;
54217b235c1SYuval Mintz 	p_cmn->update_inner_vlan_removal_en_flg = val;
54308feecd7SYuval Mintz 
54408feecd7SYuval Mintz 	p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
54508feecd7SYuval Mintz 	val = p_params->update_default_vlan_enable_flg;
54608feecd7SYuval Mintz 	p_cmn->update_default_vlan_en_flg = val;
54708feecd7SYuval Mintz 
54808feecd7SYuval Mintz 	p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
54908feecd7SYuval Mintz 	p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
55008feecd7SYuval Mintz 
55108feecd7SYuval Mintz 	p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
55208feecd7SYuval Mintz 
55317b235c1SYuval Mintz 	p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
55417b235c1SYuval Mintz 	p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
55517b235c1SYuval Mintz 
5566ddc7608SYuval Mintz 	p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
5576ddc7608SYuval Mintz 	val = p_params->update_anti_spoofing_en_flg;
5586ddc7608SYuval Mintz 	p_ramrod->common.update_anti_spoofing_en_flg = val;
5596ddc7608SYuval Mintz 
560cee4d264SManish Chopra 	rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
561cee4d264SManish Chopra 	if (rc) {
562cee4d264SManish Chopra 		/* Return spq entry which is taken in qed_sp_init_request()*/
563cee4d264SManish Chopra 		qed_spq_return_entry(p_hwfn, p_ent);
564cee4d264SManish Chopra 		return rc;
565cee4d264SManish Chopra 	}
566cee4d264SManish Chopra 
567cee4d264SManish Chopra 	/* Update mcast bins for VFs, PF doesn't use this functionality */
568cee4d264SManish Chopra 	qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
569cee4d264SManish Chopra 
570cee4d264SManish Chopra 	qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
57117b235c1SYuval Mintz 	qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
572cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
573cee4d264SManish Chopra }
574cee4d264SManish Chopra 
575dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
576cee4d264SManish Chopra {
577cee4d264SManish Chopra 	struct vport_stop_ramrod_data *p_ramrod;
57806f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
579cee4d264SManish Chopra 	struct qed_spq_entry *p_ent;
580cee4d264SManish Chopra 	u8 abs_vport_id = 0;
581cee4d264SManish Chopra 	int rc;
582cee4d264SManish Chopra 
583dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
584dacd88d6SYuval Mintz 		return qed_vf_pf_vport_stop(p_hwfn);
585dacd88d6SYuval Mintz 
586cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
5871a635e48SYuval Mintz 	if (rc)
588cee4d264SManish Chopra 		return rc;
589cee4d264SManish Chopra 
59006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
59106f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
59206f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
59306f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
594cee4d264SManish Chopra 
595cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
596cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_STOP,
59706f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
598cee4d264SManish Chopra 	if (rc)
599cee4d264SManish Chopra 		return rc;
600cee4d264SManish Chopra 
601cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_stop;
602cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
603cee4d264SManish Chopra 
604cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
605cee4d264SManish Chopra }
606cee4d264SManish Chopra 
607dacd88d6SYuval Mintz static int
608dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
609dacd88d6SYuval Mintz 		       struct qed_filter_accept_flags *p_accept_flags)
610dacd88d6SYuval Mintz {
611dacd88d6SYuval Mintz 	struct qed_sp_vport_update_params s_params;
612dacd88d6SYuval Mintz 
613dacd88d6SYuval Mintz 	memset(&s_params, 0, sizeof(s_params));
614dacd88d6SYuval Mintz 	memcpy(&s_params.accept_flags, p_accept_flags,
615dacd88d6SYuval Mintz 	       sizeof(struct qed_filter_accept_flags));
616dacd88d6SYuval Mintz 
617dacd88d6SYuval Mintz 	return qed_vf_pf_vport_update(p_hwfn, &s_params);
618dacd88d6SYuval Mintz }
619dacd88d6SYuval Mintz 
620cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev,
621cee4d264SManish Chopra 				 u8 vport,
622cee4d264SManish Chopra 				 struct qed_filter_accept_flags accept_flags,
6233f9b4a69SYuval Mintz 				 u8 update_accept_any_vlan,
6243f9b4a69SYuval Mintz 				 u8 accept_any_vlan,
625cee4d264SManish Chopra 				 enum spq_mode comp_mode,
626cee4d264SManish Chopra 				 struct qed_spq_comp_cb *p_comp_data)
627cee4d264SManish Chopra {
628cee4d264SManish Chopra 	struct qed_sp_vport_update_params vport_update_params;
629cee4d264SManish Chopra 	int i, rc;
630cee4d264SManish Chopra 
631cee4d264SManish Chopra 	/* Prepare and send the vport rx_mode change */
632cee4d264SManish Chopra 	memset(&vport_update_params, 0, sizeof(vport_update_params));
633cee4d264SManish Chopra 	vport_update_params.vport_id = vport;
634cee4d264SManish Chopra 	vport_update_params.accept_flags = accept_flags;
6353f9b4a69SYuval Mintz 	vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
6363f9b4a69SYuval Mintz 	vport_update_params.accept_any_vlan = accept_any_vlan;
637cee4d264SManish Chopra 
638cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
639cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
640cee4d264SManish Chopra 
641cee4d264SManish Chopra 		vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
642cee4d264SManish Chopra 
643dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
644dacd88d6SYuval Mintz 			rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
645dacd88d6SYuval Mintz 			if (rc)
646dacd88d6SYuval Mintz 				return rc;
647dacd88d6SYuval Mintz 			continue;
648dacd88d6SYuval Mintz 		}
649dacd88d6SYuval Mintz 
650cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
651cee4d264SManish Chopra 					 comp_mode, p_comp_data);
6521a635e48SYuval Mintz 		if (rc) {
653cee4d264SManish Chopra 			DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
654cee4d264SManish Chopra 			return rc;
655cee4d264SManish Chopra 		}
656cee4d264SManish Chopra 
657cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
658cee4d264SManish Chopra 			   "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
659cee4d264SManish Chopra 			   accept_flags.rx_accept_filter,
660cee4d264SManish Chopra 			   accept_flags.tx_accept_filter);
6613f9b4a69SYuval Mintz 		if (update_accept_any_vlan)
6623f9b4a69SYuval Mintz 			DP_VERBOSE(p_hwfn, QED_MSG_SP,
6633f9b4a69SYuval Mintz 				   "accept_any_vlan=%d configured\n",
6643f9b4a69SYuval Mintz 				   accept_any_vlan);
665cee4d264SManish Chopra 	}
666cee4d264SManish Chopra 
667cee4d264SManish Chopra 	return 0;
668cee4d264SManish Chopra }
669cee4d264SManish Chopra 
6703da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
6713da7a37aSMintz, Yuval 			     struct qed_queue_cid *p_cid,
672cee4d264SManish Chopra 			     u16 bd_max_bytes,
673cee4d264SManish Chopra 			     dma_addr_t bd_chain_phys_addr,
6743da7a37aSMintz, Yuval 			     dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
675cee4d264SManish Chopra {
676cee4d264SManish Chopra 	struct rx_queue_start_ramrod_data *p_ramrod = NULL;
677cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
67806f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
679cee4d264SManish Chopra 	int rc = -EINVAL;
680cee4d264SManish Chopra 
681cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
6823da7a37aSMintz, Yuval 		   "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
6833da7a37aSMintz, Yuval 		   p_cid->opaque_fid, p_cid->cid,
6843da7a37aSMintz, Yuval 		   p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->abs.sb);
685cee4d264SManish Chopra 
68606f56b81SYuval Mintz 	/* Get SPQ entry */
68706f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
6883da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
6893da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
69006f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
691cee4d264SManish Chopra 
692cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
693cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_START,
69406f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
695cee4d264SManish Chopra 	if (rc)
696cee4d264SManish Chopra 		return rc;
697cee4d264SManish Chopra 
698cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_start;
699cee4d264SManish Chopra 
7003da7a37aSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
7013da7a37aSMintz, Yuval 	p_ramrod->sb_index = p_cid->abs.sb_idx;
7023da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
7033da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
7043da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
705cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg = 0;
706cee4d264SManish Chopra 	p_ramrod->complete_event_flg = 1;
707cee4d264SManish Chopra 
708cee4d264SManish Chopra 	p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
70994494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
710cee4d264SManish Chopra 
711cee4d264SManish Chopra 	p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
71294494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
713cee4d264SManish Chopra 
7143da7a37aSMintz, Yuval 	if (p_cid->is_vf) {
7153da7a37aSMintz, Yuval 		p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
716351a4dedSYuval Mintz 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
717a044df83SYuval Mintz 			   "Queue%s is meant for VF rxq[%02x]\n",
7183da7a37aSMintz, Yuval 			   !!p_cid->b_legacy_vf ? " [legacy]" : "",
7193da7a37aSMintz, Yuval 			   p_cid->vf_qid);
7203da7a37aSMintz, Yuval 		p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf;
721a044df83SYuval Mintz 	}
722cee4d264SManish Chopra 
723351a4dedSYuval Mintz 	return qed_spq_post(p_hwfn, p_ent, NULL);
724cee4d264SManish Chopra }
725cee4d264SManish Chopra 
726cee4d264SManish Chopra static int
7273da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
7283da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
729cee4d264SManish Chopra 			  u16 bd_max_bytes,
730cee4d264SManish Chopra 			  dma_addr_t bd_chain_phys_addr,
731cee4d264SManish Chopra 			  dma_addr_t cqe_pbl_addr,
732dacd88d6SYuval Mintz 			  u16 cqe_pbl_size, void __iomem **pp_prod)
733cee4d264SManish Chopra {
734b21290b7SYuval Mintz 	u32 init_prod_val = 0;
735cee4d264SManish Chopra 
7363da7a37aSMintz, Yuval 	*pp_prod = p_hwfn->regview +
737cee4d264SManish Chopra 		   GTT_BAR0_MAP_REG_MSDM_RAM +
7383da7a37aSMintz, Yuval 		    MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
739cee4d264SManish Chopra 
740cee4d264SManish Chopra 	/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
741b21290b7SYuval Mintz 	__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
742cee4d264SManish Chopra 			  (u32 *)(&init_prod_val));
743cee4d264SManish Chopra 
7443da7a37aSMintz, Yuval 	return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
745cee4d264SManish Chopra 					bd_max_bytes,
746cee4d264SManish Chopra 					bd_chain_phys_addr,
7473da7a37aSMintz, Yuval 					cqe_pbl_addr, cqe_pbl_size);
7483da7a37aSMintz, Yuval }
749cee4d264SManish Chopra 
7503da7a37aSMintz, Yuval static int
7513da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
7523da7a37aSMintz, Yuval 		       u16 opaque_fid,
7533da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
7543da7a37aSMintz, Yuval 		       u16 bd_max_bytes,
7553da7a37aSMintz, Yuval 		       dma_addr_t bd_chain_phys_addr,
7563da7a37aSMintz, Yuval 		       dma_addr_t cqe_pbl_addr,
7573da7a37aSMintz, Yuval 		       u16 cqe_pbl_size,
7583da7a37aSMintz, Yuval 		       struct qed_rxq_start_ret_params *p_ret_params)
7593da7a37aSMintz, Yuval {
7603da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
7613da7a37aSMintz, Yuval 	int rc;
7623da7a37aSMintz, Yuval 
7633da7a37aSMintz, Yuval 	/* Allocate a CID for the queue */
7643da7a37aSMintz, Yuval 	p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
7653da7a37aSMintz, Yuval 	if (!p_cid)
7663da7a37aSMintz, Yuval 		return -ENOMEM;
7673da7a37aSMintz, Yuval 
7683da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
7693da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
7703da7a37aSMintz, Yuval 					       bd_max_bytes,
7713da7a37aSMintz, Yuval 					       bd_chain_phys_addr,
7723da7a37aSMintz, Yuval 					       cqe_pbl_addr, cqe_pbl_size,
7733da7a37aSMintz, Yuval 					       &p_ret_params->p_prod);
7743da7a37aSMintz, Yuval 	} else {
7753da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
7763da7a37aSMintz, Yuval 					 bd_max_bytes,
7773da7a37aSMintz, Yuval 					 bd_chain_phys_addr,
7783da7a37aSMintz, Yuval 					 cqe_pbl_addr,
7793da7a37aSMintz, Yuval 					 cqe_pbl_size, &p_ret_params->p_prod);
7803da7a37aSMintz, Yuval 	}
7813da7a37aSMintz, Yuval 
7823da7a37aSMintz, Yuval 	/* Provide the caller with a reference to as handler */
7831a635e48SYuval Mintz 	if (rc)
7843da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
7853da7a37aSMintz, Yuval 	else
7863da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
787cee4d264SManish Chopra 
788cee4d264SManish Chopra 	return rc;
789cee4d264SManish Chopra }
790cee4d264SManish Chopra 
79117b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
7923da7a37aSMintz, Yuval 				void **pp_rxq_handles,
79317b235c1SYuval Mintz 				u8 num_rxqs,
79417b235c1SYuval Mintz 				u8 complete_cqe_flg,
79517b235c1SYuval Mintz 				u8 complete_event_flg,
79617b235c1SYuval Mintz 				enum spq_mode comp_mode,
79717b235c1SYuval Mintz 				struct qed_spq_comp_cb *p_comp_data)
79817b235c1SYuval Mintz {
79917b235c1SYuval Mintz 	struct rx_queue_update_ramrod_data *p_ramrod = NULL;
80017b235c1SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
80117b235c1SYuval Mintz 	struct qed_sp_init_data init_data;
8023da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
80317b235c1SYuval Mintz 	int rc = -EINVAL;
80417b235c1SYuval Mintz 	u8 i;
80517b235c1SYuval Mintz 
80617b235c1SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
80717b235c1SYuval Mintz 	init_data.comp_mode = comp_mode;
80817b235c1SYuval Mintz 	init_data.p_comp_data = p_comp_data;
80917b235c1SYuval Mintz 
81017b235c1SYuval Mintz 	for (i = 0; i < num_rxqs; i++) {
8113da7a37aSMintz, Yuval 		p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
81217b235c1SYuval Mintz 
81317b235c1SYuval Mintz 		/* Get SPQ entry */
8143da7a37aSMintz, Yuval 		init_data.cid = p_cid->cid;
8153da7a37aSMintz, Yuval 		init_data.opaque_fid = p_cid->opaque_fid;
81617b235c1SYuval Mintz 
81717b235c1SYuval Mintz 		rc = qed_sp_init_request(p_hwfn, &p_ent,
81817b235c1SYuval Mintz 					 ETH_RAMROD_RX_QUEUE_UPDATE,
81917b235c1SYuval Mintz 					 PROTOCOLID_ETH, &init_data);
82017b235c1SYuval Mintz 		if (rc)
82117b235c1SYuval Mintz 			return rc;
82217b235c1SYuval Mintz 
82317b235c1SYuval Mintz 		p_ramrod = &p_ent->ramrod.rx_queue_update;
8243da7a37aSMintz, Yuval 		p_ramrod->vport_id = p_cid->abs.vport_id;
82517b235c1SYuval Mintz 
8263da7a37aSMintz, Yuval 		p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
82717b235c1SYuval Mintz 		p_ramrod->complete_cqe_flg = complete_cqe_flg;
82817b235c1SYuval Mintz 		p_ramrod->complete_event_flg = complete_event_flg;
82917b235c1SYuval Mintz 
83017b235c1SYuval Mintz 		rc = qed_spq_post(p_hwfn, p_ent, NULL);
83117b235c1SYuval Mintz 		if (rc)
83217b235c1SYuval Mintz 			return rc;
83317b235c1SYuval Mintz 	}
83417b235c1SYuval Mintz 
83517b235c1SYuval Mintz 	return rc;
83617b235c1SYuval Mintz }
83717b235c1SYuval Mintz 
8383da7a37aSMintz, Yuval static int
8393da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
8403da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
8413da7a37aSMintz, Yuval 			 bool b_eq_completion_only, bool b_cqe_completion)
842cee4d264SManish Chopra {
843cee4d264SManish Chopra 	struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
844cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
84506f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
8463da7a37aSMintz, Yuval 	int rc;
847cee4d264SManish Chopra 
84806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
8493da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
8503da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
85106f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
852cee4d264SManish Chopra 
853cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
854cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_STOP,
85506f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
856cee4d264SManish Chopra 	if (rc)
857cee4d264SManish Chopra 		return rc;
858cee4d264SManish Chopra 
859cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_stop;
8603da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
8613da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
862cee4d264SManish Chopra 
863cee4d264SManish Chopra 	/* Cleaning the queue requires the completion to arrive there.
864cee4d264SManish Chopra 	 * In addition, VFs require the answer to come as eqe to PF.
865cee4d264SManish Chopra 	 */
8663da7a37aSMintz, Yuval 	p_ramrod->complete_cqe_flg = (!p_cid->is_vf &&
8673da7a37aSMintz, Yuval 				      !b_eq_completion_only) ||
8683da7a37aSMintz, Yuval 				     b_cqe_completion;
8693da7a37aSMintz, Yuval 	p_ramrod->complete_event_flg = p_cid->is_vf || b_eq_completion_only;
870cee4d264SManish Chopra 
8713da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
872cee4d264SManish Chopra }
873cee4d264SManish Chopra 
8743da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
8753da7a37aSMintz, Yuval 			  void *p_rxq,
8763da7a37aSMintz, Yuval 			  bool eq_completion_only, bool cqe_completion)
8773da7a37aSMintz, Yuval {
8783da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
8793da7a37aSMintz, Yuval 	int rc = -EINVAL;
8803da7a37aSMintz, Yuval 
8813da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
8823da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
8833da7a37aSMintz, Yuval 					      eq_completion_only,
8843da7a37aSMintz, Yuval 					      cqe_completion);
8853da7a37aSMintz, Yuval 	else
8863da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
8873da7a37aSMintz, Yuval 
8883da7a37aSMintz, Yuval 	if (!rc)
8893da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
8903da7a37aSMintz, Yuval 	return rc;
8913da7a37aSMintz, Yuval }
8923da7a37aSMintz, Yuval 
8933da7a37aSMintz, Yuval int
8943da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
8953da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
8963da7a37aSMintz, Yuval 			 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
897cee4d264SManish Chopra {
898cee4d264SManish Chopra 	struct tx_queue_start_ramrod_data *p_ramrod = NULL;
899cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
90006f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
901cee4d264SManish Chopra 	int rc = -EINVAL;
902351a4dedSYuval Mintz 
90306f56b81SYuval Mintz 	/* Get SPQ entry */
90406f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
9053da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
9063da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
90706f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
908cee4d264SManish Chopra 
90906f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
910cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_START,
91106f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
912cee4d264SManish Chopra 	if (rc)
913cee4d264SManish Chopra 		return rc;
914cee4d264SManish Chopra 
915cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.tx_queue_start;
9163da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
917cee4d264SManish Chopra 
9183da7a37aSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
9193da7a37aSMintz, Yuval 	p_ramrod->sb_index = p_cid->abs.sb_idx;
9203da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
921cee4d264SManish Chopra 
9223da7a37aSMintz, Yuval 	p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
9233da7a37aSMintz, Yuval 	p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
9241a635e48SYuval Mintz 
925cee4d264SManish Chopra 	p_ramrod->pbl_size = cpu_to_le16(pbl_size);
92694494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
927cee4d264SManish Chopra 
928cee4d264SManish Chopra 	p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
929cee4d264SManish Chopra 
930cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
931cee4d264SManish Chopra }
932cee4d264SManish Chopra 
933cee4d264SManish Chopra static int
9343da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
9353da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
9363da7a37aSMintz, Yuval 			  u8 tc,
937cee4d264SManish Chopra 			  dma_addr_t pbl_addr,
938dacd88d6SYuval Mintz 			  u16 pbl_size, void __iomem **pp_doorbell)
939cee4d264SManish Chopra {
940cee4d264SManish Chopra 	union qed_qm_pq_params pq_params;
941cee4d264SManish Chopra 	int rc;
942cee4d264SManish Chopra 
943cee4d264SManish Chopra 	memset(&pq_params, 0, sizeof(pq_params));
944cee4d264SManish Chopra 
9453da7a37aSMintz, Yuval 	rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
9463da7a37aSMintz, Yuval 				      pbl_addr, pbl_size,
9473da7a37aSMintz, Yuval 				      qed_get_qm_pq(p_hwfn, PROTOCOLID_ETH,
9483da7a37aSMintz, Yuval 						    &pq_params));
9493da7a37aSMintz, Yuval 	if (rc)
950cee4d264SManish Chopra 		return rc;
9513da7a37aSMintz, Yuval 
9523da7a37aSMintz, Yuval 	/* Provide the caller with the necessary return values */
9533da7a37aSMintz, Yuval 	*pp_doorbell = p_hwfn->doorbells +
9543da7a37aSMintz, Yuval 		       qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
9553da7a37aSMintz, Yuval 
9563da7a37aSMintz, Yuval 	return 0;
957cee4d264SManish Chopra }
958cee4d264SManish Chopra 
9593da7a37aSMintz, Yuval static int
9603da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
9613da7a37aSMintz, Yuval 		       u16 opaque_fid,
9623da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
9633da7a37aSMintz, Yuval 		       u8 tc,
9643da7a37aSMintz, Yuval 		       dma_addr_t pbl_addr,
9653da7a37aSMintz, Yuval 		       u16 pbl_size,
9663da7a37aSMintz, Yuval 		       struct qed_txq_start_ret_params *p_ret_params)
9673da7a37aSMintz, Yuval {
9683da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
9693da7a37aSMintz, Yuval 	int rc;
970cee4d264SManish Chopra 
9713da7a37aSMintz, Yuval 	p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
9723da7a37aSMintz, Yuval 	if (!p_cid)
9733da7a37aSMintz, Yuval 		return -EINVAL;
974cee4d264SManish Chopra 
9753da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
9763da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
9773da7a37aSMintz, Yuval 					       pbl_addr, pbl_size,
9783da7a37aSMintz, Yuval 					       &p_ret_params->p_doorbell);
9793da7a37aSMintz, Yuval 	else
9803da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
9813da7a37aSMintz, Yuval 					 pbl_addr, pbl_size,
9823da7a37aSMintz, Yuval 					 &p_ret_params->p_doorbell);
983cee4d264SManish Chopra 
984cee4d264SManish Chopra 	if (rc)
9853da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
9863da7a37aSMintz, Yuval 	else
9873da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
988cee4d264SManish Chopra 
989cee4d264SManish Chopra 	return rc;
990cee4d264SManish Chopra }
991cee4d264SManish Chopra 
9923da7a37aSMintz, Yuval static int
9933da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
994cee4d264SManish Chopra {
995cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
99606f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
9973da7a37aSMintz, Yuval 	int rc;
998cee4d264SManish Chopra 
99906f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
10003da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
10013da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
100206f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1003cee4d264SManish Chopra 
1004cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1005cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_STOP,
100606f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1007cee4d264SManish Chopra 	if (rc)
1008cee4d264SManish Chopra 		return rc;
1009cee4d264SManish Chopra 
10103da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
10113da7a37aSMintz, Yuval }
1012cee4d264SManish Chopra 
10133da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
10143da7a37aSMintz, Yuval {
10153da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
10163da7a37aSMintz, Yuval 	int rc;
10173da7a37aSMintz, Yuval 
10183da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
10193da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
10203da7a37aSMintz, Yuval 	else
10213da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
10223da7a37aSMintz, Yuval 
10233da7a37aSMintz, Yuval 	if (!rc)
10243da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
10253da7a37aSMintz, Yuval 	return rc;
1026cee4d264SManish Chopra }
1027cee4d264SManish Chopra 
10281a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
1029cee4d264SManish Chopra {
1030cee4d264SManish Chopra 	enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1031cee4d264SManish Chopra 
1032cee4d264SManish Chopra 	switch (opcode) {
1033cee4d264SManish Chopra 	case QED_FILTER_ADD:
1034cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_ADD;
1035cee4d264SManish Chopra 		break;
1036cee4d264SManish Chopra 	case QED_FILTER_REMOVE:
1037cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_REMOVE;
1038cee4d264SManish Chopra 		break;
1039cee4d264SManish Chopra 	case QED_FILTER_FLUSH:
1040fc48b7a6SYuval Mintz 		action = ETH_FILTER_ACTION_REMOVE_ALL;
1041cee4d264SManish Chopra 		break;
1042cee4d264SManish Chopra 	default:
1043cee4d264SManish Chopra 		action = MAX_ETH_FILTER_ACTION;
1044cee4d264SManish Chopra 	}
1045cee4d264SManish Chopra 
1046cee4d264SManish Chopra 	return action;
1047cee4d264SManish Chopra }
1048cee4d264SManish Chopra 
1049cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb,
1050cee4d264SManish Chopra 				__le16 *fw_mid,
1051cee4d264SManish Chopra 				__le16 *fw_lsb,
1052cee4d264SManish Chopra 				u8 *mac)
1053cee4d264SManish Chopra {
1054cee4d264SManish Chopra 	((u8 *)fw_msb)[0] = mac[1];
1055cee4d264SManish Chopra 	((u8 *)fw_msb)[1] = mac[0];
1056cee4d264SManish Chopra 	((u8 *)fw_mid)[0] = mac[3];
1057cee4d264SManish Chopra 	((u8 *)fw_mid)[1] = mac[2];
1058cee4d264SManish Chopra 	((u8 *)fw_lsb)[0] = mac[5];
1059cee4d264SManish Chopra 	((u8 *)fw_lsb)[1] = mac[4];
1060cee4d264SManish Chopra }
1061cee4d264SManish Chopra 
1062cee4d264SManish Chopra static int
1063cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1064cee4d264SManish Chopra 			u16 opaque_fid,
1065cee4d264SManish Chopra 			struct qed_filter_ucast *p_filter_cmd,
1066cee4d264SManish Chopra 			struct vport_filter_update_ramrod_data **pp_ramrod,
1067cee4d264SManish Chopra 			struct qed_spq_entry **pp_ent,
1068cee4d264SManish Chopra 			enum spq_mode comp_mode,
1069cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1070cee4d264SManish Chopra {
1071cee4d264SManish Chopra 	u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1072cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data *p_ramrod;
1073cee4d264SManish Chopra 	struct eth_filter_cmd *p_first_filter;
1074cee4d264SManish Chopra 	struct eth_filter_cmd *p_second_filter;
107506f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1076cee4d264SManish Chopra 	enum eth_filter_action action;
1077cee4d264SManish Chopra 	int rc;
1078cee4d264SManish Chopra 
1079cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1080cee4d264SManish Chopra 			  &vport_to_remove_from);
1081cee4d264SManish Chopra 	if (rc)
1082cee4d264SManish Chopra 		return rc;
1083cee4d264SManish Chopra 
1084cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1085cee4d264SManish Chopra 			  &vport_to_add_to);
1086cee4d264SManish Chopra 	if (rc)
1087cee4d264SManish Chopra 		return rc;
1088cee4d264SManish Chopra 
108906f56b81SYuval Mintz 	/* Get SPQ entry */
109006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
109106f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
109206f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
109306f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
109406f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1095cee4d264SManish Chopra 
1096cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, pp_ent,
1097cee4d264SManish Chopra 				 ETH_RAMROD_FILTERS_UPDATE,
109806f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1099cee4d264SManish Chopra 	if (rc)
1100cee4d264SManish Chopra 		return rc;
1101cee4d264SManish Chopra 
1102cee4d264SManish Chopra 	*pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1103cee4d264SManish Chopra 	p_ramrod = *pp_ramrod;
1104cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1105cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1106cee4d264SManish Chopra 
1107cee4d264SManish Chopra 	switch (p_filter_cmd->opcode) {
1108fc48b7a6SYuval Mintz 	case QED_FILTER_REPLACE:
1109cee4d264SManish Chopra 	case QED_FILTER_MOVE:
1110cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1111cee4d264SManish Chopra 	default:
1112cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1113cee4d264SManish Chopra 	}
1114cee4d264SManish Chopra 
1115cee4d264SManish Chopra 	p_first_filter	= &p_ramrod->filter_cmds[0];
1116cee4d264SManish Chopra 	p_second_filter = &p_ramrod->filter_cmds[1];
1117cee4d264SManish Chopra 
1118cee4d264SManish Chopra 	switch (p_filter_cmd->type) {
1119cee4d264SManish Chopra 	case QED_FILTER_MAC:
1120cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1121cee4d264SManish Chopra 	case QED_FILTER_VLAN:
1122cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1123cee4d264SManish Chopra 	case QED_FILTER_MAC_VLAN:
1124cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1125cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC:
1126cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1127cee4d264SManish Chopra 	case QED_FILTER_INNER_VLAN:
1128cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1129cee4d264SManish Chopra 	case QED_FILTER_INNER_PAIR:
1130cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1131cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC_VNI_PAIR:
1132cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1133cee4d264SManish Chopra 		break;
1134cee4d264SManish Chopra 	case QED_FILTER_MAC_VNI_PAIR:
1135cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1136cee4d264SManish Chopra 	case QED_FILTER_VNI:
1137cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1138cee4d264SManish Chopra 	}
1139cee4d264SManish Chopra 
1140cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1141cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1142cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1143cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1144cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1145cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1146cee4d264SManish Chopra 		qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1147cee4d264SManish Chopra 				    &p_first_filter->mac_mid,
1148cee4d264SManish Chopra 				    &p_first_filter->mac_lsb,
1149cee4d264SManish Chopra 				    (u8 *)p_filter_cmd->mac);
1150cee4d264SManish Chopra 	}
1151cee4d264SManish Chopra 
1152cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1153cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1154cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1155cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1156cee4d264SManish Chopra 		p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1157cee4d264SManish Chopra 
1158cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1159cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1160cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1161cee4d264SManish Chopra 		p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1162cee4d264SManish Chopra 
1163cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1164cee4d264SManish Chopra 		p_second_filter->type = p_first_filter->type;
1165cee4d264SManish Chopra 		p_second_filter->mac_msb = p_first_filter->mac_msb;
1166cee4d264SManish Chopra 		p_second_filter->mac_mid = p_first_filter->mac_mid;
1167cee4d264SManish Chopra 		p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1168cee4d264SManish Chopra 		p_second_filter->vlan_id = p_first_filter->vlan_id;
1169cee4d264SManish Chopra 		p_second_filter->vni = p_first_filter->vni;
1170cee4d264SManish Chopra 
1171cee4d264SManish Chopra 		p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1172cee4d264SManish Chopra 
1173cee4d264SManish Chopra 		p_first_filter->vport_id = vport_to_remove_from;
1174cee4d264SManish Chopra 
1175cee4d264SManish Chopra 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1176cee4d264SManish Chopra 		p_second_filter->vport_id = vport_to_add_to;
1177fc48b7a6SYuval Mintz 	} else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1178fc48b7a6SYuval Mintz 		p_first_filter->vport_id = vport_to_add_to;
1179fc48b7a6SYuval Mintz 		memcpy(p_second_filter, p_first_filter,
1180fc48b7a6SYuval Mintz 		       sizeof(*p_second_filter));
1181fc48b7a6SYuval Mintz 		p_first_filter->action	= ETH_FILTER_ACTION_REMOVE_ALL;
1182fc48b7a6SYuval Mintz 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1183cee4d264SManish Chopra 	} else {
1184cee4d264SManish Chopra 		action = qed_filter_action(p_filter_cmd->opcode);
1185cee4d264SManish Chopra 
1186cee4d264SManish Chopra 		if (action == MAX_ETH_FILTER_ACTION) {
1187cee4d264SManish Chopra 			DP_NOTICE(p_hwfn,
1188cee4d264SManish Chopra 				  "%d is not supported yet\n",
1189cee4d264SManish Chopra 				  p_filter_cmd->opcode);
1190cee4d264SManish Chopra 			return -EINVAL;
1191cee4d264SManish Chopra 		}
1192cee4d264SManish Chopra 
1193cee4d264SManish Chopra 		p_first_filter->action = action;
1194cee4d264SManish Chopra 		p_first_filter->vport_id = (p_filter_cmd->opcode ==
1195cee4d264SManish Chopra 					    QED_FILTER_REMOVE) ?
1196cee4d264SManish Chopra 					   vport_to_remove_from :
1197cee4d264SManish Chopra 					   vport_to_add_to;
1198cee4d264SManish Chopra 	}
1199cee4d264SManish Chopra 
1200cee4d264SManish Chopra 	return 0;
1201cee4d264SManish Chopra }
1202cee4d264SManish Chopra 
1203dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1204cee4d264SManish Chopra 			    u16 opaque_fid,
1205cee4d264SManish Chopra 			    struct qed_filter_ucast *p_filter_cmd,
1206cee4d264SManish Chopra 			    enum spq_mode comp_mode,
1207cee4d264SManish Chopra 			    struct qed_spq_comp_cb *p_comp_data)
1208cee4d264SManish Chopra {
1209cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data	*p_ramrod	= NULL;
1210cee4d264SManish Chopra 	struct qed_spq_entry			*p_ent		= NULL;
1211cee4d264SManish Chopra 	struct eth_filter_cmd_header		*p_header;
1212cee4d264SManish Chopra 	int					rc;
1213cee4d264SManish Chopra 
1214cee4d264SManish Chopra 	rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1215cee4d264SManish Chopra 				     &p_ramrod, &p_ent,
1216cee4d264SManish Chopra 				     comp_mode, p_comp_data);
12171a635e48SYuval Mintz 	if (rc) {
1218cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1219cee4d264SManish Chopra 		return rc;
1220cee4d264SManish Chopra 	}
1221cee4d264SManish Chopra 	p_header = &p_ramrod->filter_cmd_hdr;
1222cee4d264SManish Chopra 	p_header->assert_on_error = p_filter_cmd->assert_on_error;
1223cee4d264SManish Chopra 
1224cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
12251a635e48SYuval Mintz 	if (rc) {
12261a635e48SYuval Mintz 		DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1227cee4d264SManish Chopra 		return rc;
1228cee4d264SManish Chopra 	}
1229cee4d264SManish Chopra 
1230cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1231cee4d264SManish Chopra 		   "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1232cee4d264SManish Chopra 		   (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1233cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1234cee4d264SManish Chopra 		   "REMOVE" :
1235cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1236cee4d264SManish Chopra 		    "MOVE" : "REPLACE")),
1237cee4d264SManish Chopra 		   (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1238cee4d264SManish Chopra 		   ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1239cee4d264SManish Chopra 		    "VLAN" : "MAC & VLAN"),
1240cee4d264SManish Chopra 		   p_ramrod->filter_cmd_hdr.cmd_cnt,
1241cee4d264SManish Chopra 		   p_filter_cmd->is_rx_filter,
1242cee4d264SManish Chopra 		   p_filter_cmd->is_tx_filter);
1243cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1244cee4d264SManish Chopra 		   "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1245cee4d264SManish Chopra 		   p_filter_cmd->vport_to_add_to,
1246cee4d264SManish Chopra 		   p_filter_cmd->vport_to_remove_from,
1247cee4d264SManish Chopra 		   p_filter_cmd->mac[0],
1248cee4d264SManish Chopra 		   p_filter_cmd->mac[1],
1249cee4d264SManish Chopra 		   p_filter_cmd->mac[2],
1250cee4d264SManish Chopra 		   p_filter_cmd->mac[3],
1251cee4d264SManish Chopra 		   p_filter_cmd->mac[4],
1252cee4d264SManish Chopra 		   p_filter_cmd->mac[5],
1253cee4d264SManish Chopra 		   p_filter_cmd->vlan);
1254cee4d264SManish Chopra 
1255cee4d264SManish Chopra 	return 0;
1256cee4d264SManish Chopra }
1257cee4d264SManish Chopra 
1258cee4d264SManish Chopra /*******************************************************************************
1259cee4d264SManish Chopra  * Description:
1260cee4d264SManish Chopra  *         Calculates crc 32 on a buffer
1261cee4d264SManish Chopra  *         Note: crc32_length MUST be aligned to 8
1262cee4d264SManish Chopra  * Return:
1263cee4d264SManish Chopra  ******************************************************************************/
1264cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet,
12651a635e48SYuval Mintz 			   u32 crc32_length, u32 crc32_seed, u8 complement)
1266cee4d264SManish Chopra {
12671a635e48SYuval Mintz 	u32 byte = 0, bit = 0, crc32_result = crc32_seed;
12681a635e48SYuval Mintz 	u8 msb = 0, current_byte = 0;
1269cee4d264SManish Chopra 
1270cee4d264SManish Chopra 	if ((!crc32_packet) ||
1271cee4d264SManish Chopra 	    (crc32_length == 0) ||
1272cee4d264SManish Chopra 	    ((crc32_length % 8) != 0))
1273cee4d264SManish Chopra 		return crc32_result;
1274cee4d264SManish Chopra 	for (byte = 0; byte < crc32_length; byte++) {
1275cee4d264SManish Chopra 		current_byte = crc32_packet[byte];
1276cee4d264SManish Chopra 		for (bit = 0; bit < 8; bit++) {
1277cee4d264SManish Chopra 			msb = (u8)(crc32_result >> 31);
1278cee4d264SManish Chopra 			crc32_result = crc32_result << 1;
1279cee4d264SManish Chopra 			if (msb != (0x1 & (current_byte >> bit))) {
1280cee4d264SManish Chopra 				crc32_result = crc32_result ^ CRC32_POLY;
1281cee4d264SManish Chopra 				crc32_result |= 1; /*crc32_result[0] = 1;*/
1282cee4d264SManish Chopra 			}
1283cee4d264SManish Chopra 		}
1284cee4d264SManish Chopra 	}
1285cee4d264SManish Chopra 	return crc32_result;
1286cee4d264SManish Chopra }
1287cee4d264SManish Chopra 
12881a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
1289cee4d264SManish Chopra {
1290cee4d264SManish Chopra 	u32 packet_buf[2] = { 0 };
1291cee4d264SManish Chopra 
1292cee4d264SManish Chopra 	memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1293cee4d264SManish Chopra 	return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1294cee4d264SManish Chopra }
1295cee4d264SManish Chopra 
1296dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac)
1297cee4d264SManish Chopra {
1298cee4d264SManish Chopra 	u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1299cee4d264SManish Chopra 				mac, ETH_ALEN);
1300cee4d264SManish Chopra 
1301cee4d264SManish Chopra 	return crc & 0xff;
1302cee4d264SManish Chopra }
1303cee4d264SManish Chopra 
1304cee4d264SManish Chopra static int
1305cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1306cee4d264SManish Chopra 			u16 opaque_fid,
1307cee4d264SManish Chopra 			struct qed_filter_mcast *p_filter_cmd,
1308cee4d264SManish Chopra 			enum spq_mode comp_mode,
1309cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1310cee4d264SManish Chopra {
1311cee4d264SManish Chopra 	unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1312cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
1313cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
131406f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1315cee4d264SManish Chopra 	u8 abs_vport_id = 0;
1316cee4d264SManish Chopra 	int rc, i;
1317cee4d264SManish Chopra 
131883aeb933SYuval Mintz 	if (p_filter_cmd->opcode == QED_FILTER_ADD)
1319cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1320cee4d264SManish Chopra 				  &abs_vport_id);
132183aeb933SYuval Mintz 	else
1322cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1323cee4d264SManish Chopra 				  &abs_vport_id);
1324cee4d264SManish Chopra 	if (rc)
1325cee4d264SManish Chopra 		return rc;
1326cee4d264SManish Chopra 
132706f56b81SYuval Mintz 	/* Get SPQ entry */
132806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
132906f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
133006f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
133106f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
133206f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1333cee4d264SManish Chopra 
1334cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1335cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
133606f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1337cee4d264SManish Chopra 	if (rc) {
1338cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1339cee4d264SManish Chopra 		return rc;
1340cee4d264SManish Chopra 	}
1341cee4d264SManish Chopra 
1342cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
1343cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
1344cee4d264SManish Chopra 
1345cee4d264SManish Chopra 	/* explicitly clear out the entire vector */
1346cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
1347cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
1348cee4d264SManish Chopra 	memset(bins, 0, sizeof(unsigned long) *
1349cee4d264SManish Chopra 	       ETH_MULTICAST_MAC_BINS_IN_REGS);
1350cee4d264SManish Chopra 	/* filter ADD op is explicit set op and it removes
1351cee4d264SManish Chopra 	 *  any existing filters for the vport
1352cee4d264SManish Chopra 	 */
1353cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1354cee4d264SManish Chopra 		for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1355cee4d264SManish Chopra 			u32 bit;
1356cee4d264SManish Chopra 
1357cee4d264SManish Chopra 			bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1358cee4d264SManish Chopra 			__set_bit(bit, bins);
1359cee4d264SManish Chopra 		}
1360cee4d264SManish Chopra 
1361cee4d264SManish Chopra 		/* Convert to correct endianity */
1362cee4d264SManish Chopra 		for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
13631a635e48SYuval Mintz 			struct vport_update_ramrod_mcast *p_ramrod_bins;
1364cee4d264SManish Chopra 			u32 *p_bins = (u32 *)bins;
1365cee4d264SManish Chopra 
13661a635e48SYuval Mintz 			p_ramrod_bins = &p_ramrod->approx_mcast;
13671a635e48SYuval Mintz 			p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
1368cee4d264SManish Chopra 		}
1369cee4d264SManish Chopra 	}
1370cee4d264SManish Chopra 
1371cee4d264SManish Chopra 	p_ramrod->common.vport_id = abs_vport_id;
1372cee4d264SManish Chopra 
1373cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1374cee4d264SManish Chopra }
1375cee4d264SManish Chopra 
1376dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1377cee4d264SManish Chopra 				struct qed_filter_mcast *p_filter_cmd,
1378cee4d264SManish Chopra 				enum spq_mode comp_mode,
1379cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1380cee4d264SManish Chopra {
1381cee4d264SManish Chopra 	int rc = 0;
1382cee4d264SManish Chopra 	int i;
1383cee4d264SManish Chopra 
1384cee4d264SManish Chopra 	/* only ADD and REMOVE operations are supported for multi-cast */
1385cee4d264SManish Chopra 	if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1386cee4d264SManish Chopra 	     (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1387cee4d264SManish Chopra 	    (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1388cee4d264SManish Chopra 		return -EINVAL;
1389cee4d264SManish Chopra 
1390cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1391cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1392cee4d264SManish Chopra 
1393cee4d264SManish Chopra 		u16 opaque_fid;
1394cee4d264SManish Chopra 
1395dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1396dacd88d6SYuval Mintz 			qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1397dacd88d6SYuval Mintz 			continue;
1398dacd88d6SYuval Mintz 		}
1399cee4d264SManish Chopra 
1400cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1401cee4d264SManish Chopra 
1402cee4d264SManish Chopra 		rc = qed_sp_eth_filter_mcast(p_hwfn,
1403cee4d264SManish Chopra 					     opaque_fid,
1404cee4d264SManish Chopra 					     p_filter_cmd,
14051a635e48SYuval Mintz 					     comp_mode, p_comp_data);
1406cee4d264SManish Chopra 	}
1407cee4d264SManish Chopra 	return rc;
1408cee4d264SManish Chopra }
1409cee4d264SManish Chopra 
1410cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1411cee4d264SManish Chopra 				struct qed_filter_ucast *p_filter_cmd,
1412cee4d264SManish Chopra 				enum spq_mode comp_mode,
1413cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1414cee4d264SManish Chopra {
1415cee4d264SManish Chopra 	int rc = 0;
1416cee4d264SManish Chopra 	int i;
1417cee4d264SManish Chopra 
1418cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1419cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1420cee4d264SManish Chopra 		u16 opaque_fid;
1421cee4d264SManish Chopra 
1422dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1423dacd88d6SYuval Mintz 			rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1424dacd88d6SYuval Mintz 			continue;
1425dacd88d6SYuval Mintz 		}
1426cee4d264SManish Chopra 
1427cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1428cee4d264SManish Chopra 
1429cee4d264SManish Chopra 		rc = qed_sp_eth_filter_ucast(p_hwfn,
1430cee4d264SManish Chopra 					     opaque_fid,
1431cee4d264SManish Chopra 					     p_filter_cmd,
14321a635e48SYuval Mintz 					     comp_mode, p_comp_data);
14331a635e48SYuval Mintz 		if (rc)
1434dacd88d6SYuval Mintz 			break;
1435cee4d264SManish Chopra 	}
1436cee4d264SManish Chopra 
1437cee4d264SManish Chopra 	return rc;
1438cee4d264SManish Chopra }
1439cee4d264SManish Chopra 
144086622ee7SYuval Mintz /* Statistics related code */
144186622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
144286622ee7SYuval Mintz 					   u32 *p_addr,
1443dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
144486622ee7SYuval Mintz {
1445dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
144686622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_PSDM_RAM +
144786622ee7SYuval Mintz 		    PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
144886622ee7SYuval Mintz 		*p_len = sizeof(struct eth_pstorm_per_queue_stat);
1449dacd88d6SYuval Mintz 	} else {
1450dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1451dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1452dacd88d6SYuval Mintz 
1453dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1454dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.pstats.len;
1455dacd88d6SYuval Mintz 	}
145686622ee7SYuval Mintz }
145786622ee7SYuval Mintz 
145886622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
145986622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
146086622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
146186622ee7SYuval Mintz 				   u16 statistics_bin)
146286622ee7SYuval Mintz {
146386622ee7SYuval Mintz 	struct eth_pstorm_per_queue_stat pstats;
146486622ee7SYuval Mintz 	u32 pstats_addr = 0, pstats_len = 0;
146586622ee7SYuval Mintz 
146686622ee7SYuval Mintz 	__qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
146786622ee7SYuval Mintz 				       statistics_bin);
146886622ee7SYuval Mintz 
146986622ee7SYuval Mintz 	memset(&pstats, 0, sizeof(pstats));
1470dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
147186622ee7SYuval Mintz 
1472dacd88d6SYuval Mintz 	p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1473dacd88d6SYuval Mintz 	p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1474dacd88d6SYuval Mintz 	p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1475dacd88d6SYuval Mintz 	p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1476dacd88d6SYuval Mintz 	p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1477dacd88d6SYuval Mintz 	p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1478dacd88d6SYuval Mintz 	p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
147986622ee7SYuval Mintz }
148086622ee7SYuval Mintz 
148186622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
148286622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
148386622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
148486622ee7SYuval Mintz 				   u16 statistics_bin)
148586622ee7SYuval Mintz {
148686622ee7SYuval Mintz 	struct tstorm_per_port_stat tstats;
1487dacd88d6SYuval Mintz 	u32 tstats_addr, tstats_len;
148886622ee7SYuval Mintz 
1489dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
1490dacd88d6SYuval Mintz 		tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1491dacd88d6SYuval Mintz 		    TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1492dacd88d6SYuval Mintz 		tstats_len = sizeof(struct tstorm_per_port_stat);
1493dacd88d6SYuval Mintz 	} else {
1494dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1495dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1496dacd88d6SYuval Mintz 
1497dacd88d6SYuval Mintz 		tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1498dacd88d6SYuval Mintz 		tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1499dacd88d6SYuval Mintz 	}
150086622ee7SYuval Mintz 
150186622ee7SYuval Mintz 	memset(&tstats, 0, sizeof(tstats));
1502dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
150386622ee7SYuval Mintz 
150486622ee7SYuval Mintz 	p_stats->mftag_filter_discards +=
150586622ee7SYuval Mintz 		HILO_64_REGPAIR(tstats.mftag_filter_discard);
150686622ee7SYuval Mintz 	p_stats->mac_filter_discards +=
150786622ee7SYuval Mintz 		HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
150886622ee7SYuval Mintz }
150986622ee7SYuval Mintz 
151086622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
151186622ee7SYuval Mintz 					   u32 *p_addr,
1512dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
151386622ee7SYuval Mintz {
1514dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
151586622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_USDM_RAM +
151686622ee7SYuval Mintz 		    USTORM_QUEUE_STAT_OFFSET(statistics_bin);
151786622ee7SYuval Mintz 		*p_len = sizeof(struct eth_ustorm_per_queue_stat);
1518dacd88d6SYuval Mintz 	} else {
1519dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1520dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1521dacd88d6SYuval Mintz 
1522dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1523dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.ustats.len;
1524dacd88d6SYuval Mintz 	}
152586622ee7SYuval Mintz }
152686622ee7SYuval Mintz 
152786622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
152886622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
152986622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
153086622ee7SYuval Mintz 				   u16 statistics_bin)
153186622ee7SYuval Mintz {
153286622ee7SYuval Mintz 	struct eth_ustorm_per_queue_stat ustats;
153386622ee7SYuval Mintz 	u32 ustats_addr = 0, ustats_len = 0;
153486622ee7SYuval Mintz 
153586622ee7SYuval Mintz 	__qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
153686622ee7SYuval Mintz 				       statistics_bin);
153786622ee7SYuval Mintz 
153886622ee7SYuval Mintz 	memset(&ustats, 0, sizeof(ustats));
1539dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
154086622ee7SYuval Mintz 
1541dacd88d6SYuval Mintz 	p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1542dacd88d6SYuval Mintz 	p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1543dacd88d6SYuval Mintz 	p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1544dacd88d6SYuval Mintz 	p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1545dacd88d6SYuval Mintz 	p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1546dacd88d6SYuval Mintz 	p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
154786622ee7SYuval Mintz }
154886622ee7SYuval Mintz 
154986622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
155086622ee7SYuval Mintz 					   u32 *p_addr,
1551dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
155286622ee7SYuval Mintz {
1553dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
155486622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_MSDM_RAM +
155586622ee7SYuval Mintz 		    MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
155686622ee7SYuval Mintz 		*p_len = sizeof(struct eth_mstorm_per_queue_stat);
1557dacd88d6SYuval Mintz 	} else {
1558dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1559dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1560dacd88d6SYuval Mintz 
1561dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1562dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.mstats.len;
1563dacd88d6SYuval Mintz 	}
156486622ee7SYuval Mintz }
156586622ee7SYuval Mintz 
156686622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
156786622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
156886622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
156986622ee7SYuval Mintz 				   u16 statistics_bin)
157086622ee7SYuval Mintz {
157186622ee7SYuval Mintz 	struct eth_mstorm_per_queue_stat mstats;
157286622ee7SYuval Mintz 	u32 mstats_addr = 0, mstats_len = 0;
157386622ee7SYuval Mintz 
157486622ee7SYuval Mintz 	__qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
157586622ee7SYuval Mintz 				       statistics_bin);
157686622ee7SYuval Mintz 
157786622ee7SYuval Mintz 	memset(&mstats, 0, sizeof(mstats));
1578dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
157986622ee7SYuval Mintz 
1580dacd88d6SYuval Mintz 	p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
158186622ee7SYuval Mintz 	p_stats->packet_too_big_discard +=
158286622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.packet_too_big_discard);
1583dacd88d6SYuval Mintz 	p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
158486622ee7SYuval Mintz 	p_stats->tpa_coalesced_pkts +=
158586622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
158686622ee7SYuval Mintz 	p_stats->tpa_coalesced_events +=
158786622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1588dacd88d6SYuval Mintz 	p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
158986622ee7SYuval Mintz 	p_stats->tpa_coalesced_bytes +=
159086622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
159186622ee7SYuval Mintz }
159286622ee7SYuval Mintz 
159386622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
159486622ee7SYuval Mintz 				       struct qed_ptt *p_ptt,
159586622ee7SYuval Mintz 				       struct qed_eth_stats *p_stats)
159686622ee7SYuval Mintz {
159786622ee7SYuval Mintz 	struct port_stats port_stats;
159886622ee7SYuval Mintz 	int j;
159986622ee7SYuval Mintz 
160086622ee7SYuval Mintz 	memset(&port_stats, 0, sizeof(port_stats));
160186622ee7SYuval Mintz 
160286622ee7SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
160386622ee7SYuval Mintz 			p_hwfn->mcp_info->port_addr +
160486622ee7SYuval Mintz 			offsetof(struct public_port, stats),
160586622ee7SYuval Mintz 			sizeof(port_stats));
160686622ee7SYuval Mintz 
1607351a4dedSYuval Mintz 	p_stats->rx_64_byte_packets		+= port_stats.eth.r64;
1608351a4dedSYuval Mintz 	p_stats->rx_65_to_127_byte_packets	+= port_stats.eth.r127;
1609351a4dedSYuval Mintz 	p_stats->rx_128_to_255_byte_packets	+= port_stats.eth.r255;
1610351a4dedSYuval Mintz 	p_stats->rx_256_to_511_byte_packets	+= port_stats.eth.r511;
1611351a4dedSYuval Mintz 	p_stats->rx_512_to_1023_byte_packets	+= port_stats.eth.r1023;
1612351a4dedSYuval Mintz 	p_stats->rx_1024_to_1518_byte_packets	+= port_stats.eth.r1518;
1613351a4dedSYuval Mintz 	p_stats->rx_1519_to_1522_byte_packets	+= port_stats.eth.r1522;
1614351a4dedSYuval Mintz 	p_stats->rx_1519_to_2047_byte_packets	+= port_stats.eth.r2047;
1615351a4dedSYuval Mintz 	p_stats->rx_2048_to_4095_byte_packets	+= port_stats.eth.r4095;
1616351a4dedSYuval Mintz 	p_stats->rx_4096_to_9216_byte_packets	+= port_stats.eth.r9216;
1617351a4dedSYuval Mintz 	p_stats->rx_9217_to_16383_byte_packets	+= port_stats.eth.r16383;
1618351a4dedSYuval Mintz 	p_stats->rx_crc_errors			+= port_stats.eth.rfcs;
1619351a4dedSYuval Mintz 	p_stats->rx_mac_crtl_frames		+= port_stats.eth.rxcf;
1620351a4dedSYuval Mintz 	p_stats->rx_pause_frames		+= port_stats.eth.rxpf;
1621351a4dedSYuval Mintz 	p_stats->rx_pfc_frames			+= port_stats.eth.rxpp;
1622351a4dedSYuval Mintz 	p_stats->rx_align_errors		+= port_stats.eth.raln;
1623351a4dedSYuval Mintz 	p_stats->rx_carrier_errors		+= port_stats.eth.rfcr;
1624351a4dedSYuval Mintz 	p_stats->rx_oversize_packets		+= port_stats.eth.rovr;
1625351a4dedSYuval Mintz 	p_stats->rx_jabbers			+= port_stats.eth.rjbr;
1626351a4dedSYuval Mintz 	p_stats->rx_undersize_packets		+= port_stats.eth.rund;
1627351a4dedSYuval Mintz 	p_stats->rx_fragments			+= port_stats.eth.rfrg;
1628351a4dedSYuval Mintz 	p_stats->tx_64_byte_packets		+= port_stats.eth.t64;
1629351a4dedSYuval Mintz 	p_stats->tx_65_to_127_byte_packets	+= port_stats.eth.t127;
1630351a4dedSYuval Mintz 	p_stats->tx_128_to_255_byte_packets	+= port_stats.eth.t255;
1631351a4dedSYuval Mintz 	p_stats->tx_256_to_511_byte_packets	+= port_stats.eth.t511;
1632351a4dedSYuval Mintz 	p_stats->tx_512_to_1023_byte_packets	+= port_stats.eth.t1023;
1633351a4dedSYuval Mintz 	p_stats->tx_1024_to_1518_byte_packets	+= port_stats.eth.t1518;
1634351a4dedSYuval Mintz 	p_stats->tx_1519_to_2047_byte_packets	+= port_stats.eth.t2047;
1635351a4dedSYuval Mintz 	p_stats->tx_2048_to_4095_byte_packets	+= port_stats.eth.t4095;
1636351a4dedSYuval Mintz 	p_stats->tx_4096_to_9216_byte_packets	+= port_stats.eth.t9216;
1637351a4dedSYuval Mintz 	p_stats->tx_9217_to_16383_byte_packets	+= port_stats.eth.t16383;
1638351a4dedSYuval Mintz 	p_stats->tx_pause_frames		+= port_stats.eth.txpf;
1639351a4dedSYuval Mintz 	p_stats->tx_pfc_frames			+= port_stats.eth.txpp;
1640351a4dedSYuval Mintz 	p_stats->tx_lpi_entry_count		+= port_stats.eth.tlpiec;
1641351a4dedSYuval Mintz 	p_stats->tx_total_collisions		+= port_stats.eth.tncl;
1642351a4dedSYuval Mintz 	p_stats->rx_mac_bytes			+= port_stats.eth.rbyte;
1643351a4dedSYuval Mintz 	p_stats->rx_mac_uc_packets		+= port_stats.eth.rxuca;
1644351a4dedSYuval Mintz 	p_stats->rx_mac_mc_packets		+= port_stats.eth.rxmca;
1645351a4dedSYuval Mintz 	p_stats->rx_mac_bc_packets		+= port_stats.eth.rxbca;
1646351a4dedSYuval Mintz 	p_stats->rx_mac_frames_ok		+= port_stats.eth.rxpok;
1647351a4dedSYuval Mintz 	p_stats->tx_mac_bytes			+= port_stats.eth.tbyte;
1648351a4dedSYuval Mintz 	p_stats->tx_mac_uc_packets		+= port_stats.eth.txuca;
1649351a4dedSYuval Mintz 	p_stats->tx_mac_mc_packets		+= port_stats.eth.txmca;
1650351a4dedSYuval Mintz 	p_stats->tx_mac_bc_packets		+= port_stats.eth.txbca;
1651351a4dedSYuval Mintz 	p_stats->tx_mac_ctrl_frames		+= port_stats.eth.txcf;
165286622ee7SYuval Mintz 	for (j = 0; j < 8; j++) {
165386622ee7SYuval Mintz 		p_stats->brb_truncates	+= port_stats.brb.brb_truncate[j];
165486622ee7SYuval Mintz 		p_stats->brb_discards	+= port_stats.brb.brb_discard[j];
165586622ee7SYuval Mintz 	}
165686622ee7SYuval Mintz }
165786622ee7SYuval Mintz 
165886622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
165986622ee7SYuval Mintz 				  struct qed_ptt *p_ptt,
166086622ee7SYuval Mintz 				  struct qed_eth_stats *stats,
1661dacd88d6SYuval Mintz 				  u16 statistics_bin, bool b_get_port_stats)
166286622ee7SYuval Mintz {
166386622ee7SYuval Mintz 	__qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
166486622ee7SYuval Mintz 	__qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
166586622ee7SYuval Mintz 	__qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
166686622ee7SYuval Mintz 	__qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
166786622ee7SYuval Mintz 
1668dacd88d6SYuval Mintz 	if (b_get_port_stats && p_hwfn->mcp_info)
166986622ee7SYuval Mintz 		__qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
167086622ee7SYuval Mintz }
167186622ee7SYuval Mintz 
167286622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev,
167386622ee7SYuval Mintz 				 struct qed_eth_stats *stats)
167486622ee7SYuval Mintz {
167586622ee7SYuval Mintz 	u8 fw_vport = 0;
167686622ee7SYuval Mintz 	int i;
167786622ee7SYuval Mintz 
167886622ee7SYuval Mintz 	memset(stats, 0, sizeof(*stats));
167986622ee7SYuval Mintz 
168086622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
168186622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1682dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1683dacd88d6SYuval Mintz 						    :  NULL;
168486622ee7SYuval Mintz 
1685dacd88d6SYuval Mintz 		if (IS_PF(cdev)) {
168686622ee7SYuval Mintz 			/* The main vport index is relative first */
168786622ee7SYuval Mintz 			if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
168886622ee7SYuval Mintz 				DP_ERR(p_hwfn, "No vport available!\n");
1689dacd88d6SYuval Mintz 				goto out;
1690dacd88d6SYuval Mintz 			}
169186622ee7SYuval Mintz 		}
169286622ee7SYuval Mintz 
1693dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
169486622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
169586622ee7SYuval Mintz 			continue;
169686622ee7SYuval Mintz 		}
169786622ee7SYuval Mintz 
1698dacd88d6SYuval Mintz 		__qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1699dacd88d6SYuval Mintz 				      IS_PF(cdev) ? true : false);
170086622ee7SYuval Mintz 
1701dacd88d6SYuval Mintz out:
1702dacd88d6SYuval Mintz 		if (IS_PF(cdev) && p_ptt)
170386622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
170486622ee7SYuval Mintz 	}
170586622ee7SYuval Mintz }
170686622ee7SYuval Mintz 
17071a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
170886622ee7SYuval Mintz {
170986622ee7SYuval Mintz 	u32 i;
171086622ee7SYuval Mintz 
171186622ee7SYuval Mintz 	if (!cdev) {
171286622ee7SYuval Mintz 		memset(stats, 0, sizeof(*stats));
171386622ee7SYuval Mintz 		return;
171486622ee7SYuval Mintz 	}
171586622ee7SYuval Mintz 
171686622ee7SYuval Mintz 	_qed_get_vport_stats(cdev, stats);
171786622ee7SYuval Mintz 
171886622ee7SYuval Mintz 	if (!cdev->reset_stats)
171986622ee7SYuval Mintz 		return;
172086622ee7SYuval Mintz 
172186622ee7SYuval Mintz 	/* Reduce the statistics baseline */
172286622ee7SYuval Mintz 	for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
172386622ee7SYuval Mintz 		((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
172486622ee7SYuval Mintz }
172586622ee7SYuval Mintz 
172686622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
172786622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev)
172886622ee7SYuval Mintz {
172986622ee7SYuval Mintz 	int i;
173086622ee7SYuval Mintz 
173186622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
173286622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
173386622ee7SYuval Mintz 		struct eth_mstorm_per_queue_stat mstats;
173486622ee7SYuval Mintz 		struct eth_ustorm_per_queue_stat ustats;
173586622ee7SYuval Mintz 		struct eth_pstorm_per_queue_stat pstats;
1736dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1737dacd88d6SYuval Mintz 						    : NULL;
173886622ee7SYuval Mintz 		u32 addr = 0, len = 0;
173986622ee7SYuval Mintz 
1740dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
174186622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
174286622ee7SYuval Mintz 			continue;
174386622ee7SYuval Mintz 		}
174486622ee7SYuval Mintz 
174586622ee7SYuval Mintz 		memset(&mstats, 0, sizeof(mstats));
174686622ee7SYuval Mintz 		__qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
174786622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
174886622ee7SYuval Mintz 
174986622ee7SYuval Mintz 		memset(&ustats, 0, sizeof(ustats));
175086622ee7SYuval Mintz 		__qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
175186622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
175286622ee7SYuval Mintz 
175386622ee7SYuval Mintz 		memset(&pstats, 0, sizeof(pstats));
175486622ee7SYuval Mintz 		__qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
175586622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
175686622ee7SYuval Mintz 
1757dacd88d6SYuval Mintz 		if (IS_PF(cdev))
175886622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
175986622ee7SYuval Mintz 	}
176086622ee7SYuval Mintz 
176186622ee7SYuval Mintz 	/* PORT statistics are not necessarily reset, so we need to
176286622ee7SYuval Mintz 	 * read and create a baseline for future statistics.
176386622ee7SYuval Mintz 	 */
176486622ee7SYuval Mintz 	if (!cdev->reset_stats)
176586622ee7SYuval Mintz 		DP_INFO(cdev, "Reset stats not allocated\n");
176686622ee7SYuval Mintz 	else
176786622ee7SYuval Mintz 		_qed_get_vport_stats(cdev, cdev->reset_stats);
176886622ee7SYuval Mintz }
176986622ee7SYuval Mintz 
177025c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev,
177125c089d7SYuval Mintz 				 struct qed_dev_eth_info *info)
177225c089d7SYuval Mintz {
177325c089d7SYuval Mintz 	int i;
177425c089d7SYuval Mintz 
177525c089d7SYuval Mintz 	memset(info, 0, sizeof(*info));
177625c089d7SYuval Mintz 
177725c089d7SYuval Mintz 	info->num_tc = 1;
177825c089d7SYuval Mintz 
17791408cc1fSYuval Mintz 	if (IS_PF(cdev)) {
178025eb8d46SYuval Mintz 		int max_vf_vlan_filters = 0;
17817b7e70f9SYuval Mintz 		int max_vf_mac_filters = 0;
178225eb8d46SYuval Mintz 
178325c089d7SYuval Mintz 		if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
1784e1d32acbSMintz, Yuval 			u16 num_queues = 0;
1785e1d32acbSMintz, Yuval 
1786e1d32acbSMintz, Yuval 			/* Since the feature controls only queue-zones,
1787e1d32acbSMintz, Yuval 			 * make sure we have the contexts [rx, tx, xdp] to
1788e1d32acbSMintz, Yuval 			 * match.
1789e1d32acbSMintz, Yuval 			 */
1790e1d32acbSMintz, Yuval 			for_each_hwfn(cdev, i) {
1791e1d32acbSMintz, Yuval 				struct qed_hwfn *hwfn = &cdev->hwfns[i];
1792e1d32acbSMintz, Yuval 				u16 l2_queues = (u16)FEAT_NUM(hwfn,
1793e1d32acbSMintz, Yuval 							      QED_PF_L2_QUE);
1794e1d32acbSMintz, Yuval 				u16 cids;
1795e1d32acbSMintz, Yuval 
1796e1d32acbSMintz, Yuval 				cids = hwfn->pf_params.eth_pf_params.num_cons;
1797e1d32acbSMintz, Yuval 				num_queues += min_t(u16, l2_queues, cids / 3);
1798e1d32acbSMintz, Yuval 			}
1799e1d32acbSMintz, Yuval 
1800e1d32acbSMintz, Yuval 			/* queues might theoretically be >256, but interrupts'
1801e1d32acbSMintz, Yuval 			 * upper-limit guarantes that it would fit in a u8.
1802e1d32acbSMintz, Yuval 			 */
1803e1d32acbSMintz, Yuval 			if (cdev->int_params.fp_msix_cnt) {
1804e1d32acbSMintz, Yuval 				u8 irqs = cdev->int_params.fp_msix_cnt;
1805e1d32acbSMintz, Yuval 
1806e1d32acbSMintz, Yuval 				info->num_queues = (u8)min_t(u16,
1807e1d32acbSMintz, Yuval 							     num_queues, irqs);
1808e1d32acbSMintz, Yuval 			}
180925c089d7SYuval Mintz 		} else {
181025c089d7SYuval Mintz 			info->num_queues = cdev->num_hwfns;
181125c089d7SYuval Mintz 		}
181225c089d7SYuval Mintz 
18137b7e70f9SYuval Mintz 		if (IS_QED_SRIOV(cdev)) {
181425eb8d46SYuval Mintz 			max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
181525eb8d46SYuval Mintz 					      QED_ETH_VF_NUM_VLAN_FILTERS;
18167b7e70f9SYuval Mintz 			max_vf_mac_filters = cdev->p_iov_info->total_vfs *
18177b7e70f9SYuval Mintz 					     QED_ETH_VF_NUM_MAC_FILTERS;
18187b7e70f9SYuval Mintz 		}
18197b7e70f9SYuval Mintz 		info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
18207b7e70f9SYuval Mintz 						  QED_VLAN) -
182125eb8d46SYuval Mintz 					 max_vf_vlan_filters;
18227b7e70f9SYuval Mintz 		info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
18237b7e70f9SYuval Mintz 						 QED_MAC) -
18247b7e70f9SYuval Mintz 					max_vf_mac_filters;
182525eb8d46SYuval Mintz 
182625c089d7SYuval Mintz 		ether_addr_copy(info->port_mac,
182725c089d7SYuval Mintz 				cdev->hwfns[0].hw_info.hw_mac_addr);
18281408cc1fSYuval Mintz 	} else {
18291408cc1fSYuval Mintz 		qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
18301408cc1fSYuval Mintz 		if (cdev->num_hwfns > 1) {
18311408cc1fSYuval Mintz 			u8 queues = 0;
18321408cc1fSYuval Mintz 
18331408cc1fSYuval Mintz 			qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
18341408cc1fSYuval Mintz 			info->num_queues += queues;
18351408cc1fSYuval Mintz 		}
18361408cc1fSYuval Mintz 
18371408cc1fSYuval Mintz 		qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
18382edbff8dSTomer Tayar 					    (u8 *)&info->num_vlan_filters);
1839b0fca312SMintz, Yuval 		qed_vf_get_num_mac_filters(&cdev->hwfns[0],
1840b0fca312SMintz, Yuval 					   (u8 *)&info->num_mac_filters);
18411408cc1fSYuval Mintz 		qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
1842d8c2c7e3SYuval Mintz 
1843d8c2c7e3SYuval Mintz 		info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
18441408cc1fSYuval Mintz 	}
184525c089d7SYuval Mintz 
184625c089d7SYuval Mintz 	qed_fill_dev_info(cdev, &info->common);
184725c089d7SYuval Mintz 
18481408cc1fSYuval Mintz 	if (IS_VF(cdev))
18491408cc1fSYuval Mintz 		memset(info->common.hw_mac, 0, ETH_ALEN);
18501408cc1fSYuval Mintz 
185125c089d7SYuval Mintz 	return 0;
185225c089d7SYuval Mintz }
185325c089d7SYuval Mintz 
1854cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev,
18551408cc1fSYuval Mintz 				 struct qed_eth_cb_ops *ops, void *cookie)
1856cc875c2eSYuval Mintz {
1857cc875c2eSYuval Mintz 	cdev->protocol_ops.eth = ops;
1858cc875c2eSYuval Mintz 	cdev->ops_cookie = cookie;
18591408cc1fSYuval Mintz 
18601408cc1fSYuval Mintz 	/* For VF, we start bulletin reading */
18611408cc1fSYuval Mintz 	if (IS_VF(cdev))
18621408cc1fSYuval Mintz 		qed_vf_start_iov_wq(cdev);
1863cc875c2eSYuval Mintz }
1864cc875c2eSYuval Mintz 
1865eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
1866eff16960SYuval Mintz {
1867eff16960SYuval Mintz 	if (IS_PF(cdev))
1868eff16960SYuval Mintz 		return true;
1869eff16960SYuval Mintz 
1870eff16960SYuval Mintz 	return qed_vf_check_mac(&cdev->hwfns[0], mac);
1871eff16960SYuval Mintz }
1872eff16960SYuval Mintz 
1873cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev,
1874088c8618SManish Chopra 			   struct qed_start_vport_params *params)
1875cee4d264SManish Chopra {
1876cee4d264SManish Chopra 	int rc, i;
1877cee4d264SManish Chopra 
1878cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1879088c8618SManish Chopra 		struct qed_sp_vport_start_params start = { 0 };
1880cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1881cee4d264SManish Chopra 
1882088c8618SManish Chopra 		start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1883088c8618SManish Chopra 							QED_TPA_MODE_NONE;
1884088c8618SManish Chopra 		start.remove_inner_vlan = params->remove_inner_vlan;
188508feecd7SYuval Mintz 		start.only_untagged = true;	/* untagged only */
1886088c8618SManish Chopra 		start.drop_ttl0 = params->drop_ttl0;
1887088c8618SManish Chopra 		start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1888088c8618SManish Chopra 		start.concrete_fid = p_hwfn->hw_info.concrete_fid;
1889088c8618SManish Chopra 		start.vport_id = params->vport_id;
1890088c8618SManish Chopra 		start.max_buffers_per_cqe = 16;
1891088c8618SManish Chopra 		start.mtu = params->mtu;
1892cee4d264SManish Chopra 
1893088c8618SManish Chopra 		rc = qed_sp_vport_start(p_hwfn, &start);
1894cee4d264SManish Chopra 		if (rc) {
1895cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to start VPORT\n");
1896cee4d264SManish Chopra 			return rc;
1897cee4d264SManish Chopra 		}
1898cee4d264SManish Chopra 
1899cee4d264SManish Chopra 		qed_hw_start_fastpath(p_hwfn);
1900cee4d264SManish Chopra 
1901cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1902cee4d264SManish Chopra 			   "Started V-PORT %d with MTU %d\n",
1903088c8618SManish Chopra 			   start.vport_id, start.mtu);
1904cee4d264SManish Chopra 	}
1905cee4d264SManish Chopra 
1906a0d26d5aSYuval Mintz 	if (params->clear_stats)
19079df2ed04SManish Chopra 		qed_reset_vport_stats(cdev);
19089df2ed04SManish Chopra 
1909cee4d264SManish Chopra 	return 0;
1910cee4d264SManish Chopra }
1911cee4d264SManish Chopra 
19121a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
1913cee4d264SManish Chopra {
1914cee4d264SManish Chopra 	int rc, i;
1915cee4d264SManish Chopra 
1916cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1917cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1918cee4d264SManish Chopra 
1919cee4d264SManish Chopra 		rc = qed_sp_vport_stop(p_hwfn,
19201a635e48SYuval Mintz 				       p_hwfn->hw_info.opaque_fid, vport_id);
1921cee4d264SManish Chopra 
1922cee4d264SManish Chopra 		if (rc) {
1923cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to stop VPORT\n");
1924cee4d264SManish Chopra 			return rc;
1925cee4d264SManish Chopra 		}
1926cee4d264SManish Chopra 	}
1927cee4d264SManish Chopra 	return 0;
1928cee4d264SManish Chopra }
1929cee4d264SManish Chopra 
1930f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev,
1931f29ffdb6SMintz, Yuval 				struct qed_update_vport_rss_params *input,
1932f29ffdb6SMintz, Yuval 				struct qed_rss_params *rss)
1933f29ffdb6SMintz, Yuval {
1934f29ffdb6SMintz, Yuval 	int i, fn;
1935f29ffdb6SMintz, Yuval 
1936f29ffdb6SMintz, Yuval 	/* Update configuration with what's correct regardless of CMT */
1937f29ffdb6SMintz, Yuval 	rss->update_rss_config = 1;
1938f29ffdb6SMintz, Yuval 	rss->rss_enable = 1;
1939f29ffdb6SMintz, Yuval 	rss->update_rss_capabilities = 1;
1940f29ffdb6SMintz, Yuval 	rss->update_rss_ind_table = 1;
1941f29ffdb6SMintz, Yuval 	rss->update_rss_key = 1;
1942f29ffdb6SMintz, Yuval 	rss->rss_caps = input->rss_caps;
1943f29ffdb6SMintz, Yuval 	memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
1944f29ffdb6SMintz, Yuval 
1945f29ffdb6SMintz, Yuval 	/* In regular scenario, we'd simply need to take input handlers.
1946f29ffdb6SMintz, Yuval 	 * But in CMT, we'd have to split the handlers according to the
1947f29ffdb6SMintz, Yuval 	 * engine they were configured on. We'd then have to understand
1948f29ffdb6SMintz, Yuval 	 * whether RSS is really required, since 2-queues on CMT doesn't
1949f29ffdb6SMintz, Yuval 	 * require RSS.
1950f29ffdb6SMintz, Yuval 	 */
1951f29ffdb6SMintz, Yuval 	if (cdev->num_hwfns == 1) {
1952f29ffdb6SMintz, Yuval 		memcpy(rss->rss_ind_table,
1953f29ffdb6SMintz, Yuval 		       input->rss_ind_table,
1954f29ffdb6SMintz, Yuval 		       QED_RSS_IND_TABLE_SIZE * sizeof(void *));
1955f29ffdb6SMintz, Yuval 		rss->rss_table_size_log = 7;
1956f29ffdb6SMintz, Yuval 		return 0;
1957f29ffdb6SMintz, Yuval 	}
1958f29ffdb6SMintz, Yuval 
1959f29ffdb6SMintz, Yuval 	/* Start by copying the non-spcific information to the 2nd copy */
1960f29ffdb6SMintz, Yuval 	memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
1961f29ffdb6SMintz, Yuval 
1962f29ffdb6SMintz, Yuval 	/* CMT should be round-robin */
1963f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
1964f29ffdb6SMintz, Yuval 		struct qed_queue_cid *cid = input->rss_ind_table[i];
1965f29ffdb6SMintz, Yuval 		struct qed_rss_params *t_rss;
1966f29ffdb6SMintz, Yuval 
1967f29ffdb6SMintz, Yuval 		if (cid->p_owner == QED_LEADING_HWFN(cdev))
1968f29ffdb6SMintz, Yuval 			t_rss = &rss[0];
1969f29ffdb6SMintz, Yuval 		else
1970f29ffdb6SMintz, Yuval 			t_rss = &rss[1];
1971f29ffdb6SMintz, Yuval 
1972f29ffdb6SMintz, Yuval 		t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
1973f29ffdb6SMintz, Yuval 	}
1974f29ffdb6SMintz, Yuval 
1975f29ffdb6SMintz, Yuval 	/* Make sure RSS is actually required */
1976f29ffdb6SMintz, Yuval 	for_each_hwfn(cdev, fn) {
1977f29ffdb6SMintz, Yuval 		for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
1978f29ffdb6SMintz, Yuval 			if (rss[fn].rss_ind_table[i] !=
1979f29ffdb6SMintz, Yuval 			    rss[fn].rss_ind_table[0])
1980f29ffdb6SMintz, Yuval 				break;
1981f29ffdb6SMintz, Yuval 		}
1982f29ffdb6SMintz, Yuval 		if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
1983f29ffdb6SMintz, Yuval 			DP_VERBOSE(cdev, NETIF_MSG_IFUP,
1984f29ffdb6SMintz, Yuval 				   "CMT - 1 queue per-hwfn; Disabling RSS\n");
1985f29ffdb6SMintz, Yuval 			return -EINVAL;
1986f29ffdb6SMintz, Yuval 		}
1987f29ffdb6SMintz, Yuval 		rss[fn].rss_table_size_log = 6;
1988f29ffdb6SMintz, Yuval 	}
1989f29ffdb6SMintz, Yuval 
1990f29ffdb6SMintz, Yuval 	return 0;
1991f29ffdb6SMintz, Yuval }
1992f29ffdb6SMintz, Yuval 
1993cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev,
1994cee4d264SManish Chopra 			    struct qed_update_vport_params *params)
1995cee4d264SManish Chopra {
1996cee4d264SManish Chopra 	struct qed_sp_vport_update_params sp_params;
1997f29ffdb6SMintz, Yuval 	struct qed_rss_params *rss;
1998f29ffdb6SMintz, Yuval 	int rc = 0, i;
1999cee4d264SManish Chopra 
2000cee4d264SManish Chopra 	if (!cdev)
2001cee4d264SManish Chopra 		return -ENODEV;
2002cee4d264SManish Chopra 
2003f29ffdb6SMintz, Yuval 	rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
2004f29ffdb6SMintz, Yuval 	if (!rss)
2005f29ffdb6SMintz, Yuval 		return -ENOMEM;
2006f29ffdb6SMintz, Yuval 
2007cee4d264SManish Chopra 	memset(&sp_params, 0, sizeof(sp_params));
2008cee4d264SManish Chopra 
2009cee4d264SManish Chopra 	/* Translate protocol params into sp params */
2010cee4d264SManish Chopra 	sp_params.vport_id = params->vport_id;
20111a635e48SYuval Mintz 	sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
20121a635e48SYuval Mintz 	sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
2013cee4d264SManish Chopra 	sp_params.vport_active_rx_flg = params->vport_active_flg;
2014cee4d264SManish Chopra 	sp_params.vport_active_tx_flg = params->vport_active_flg;
2015831bfb0eSYuval Mintz 	sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2016831bfb0eSYuval Mintz 	sp_params.tx_switching_flg = params->tx_switching_flg;
20173f9b4a69SYuval Mintz 	sp_params.accept_any_vlan = params->accept_any_vlan;
20183f9b4a69SYuval Mintz 	sp_params.update_accept_any_vlan_flg =
20193f9b4a69SYuval Mintz 		params->update_accept_any_vlan_flg;
2020cee4d264SManish Chopra 
2021f29ffdb6SMintz, Yuval 	/* Prepare the RSS configuration */
2022f29ffdb6SMintz, Yuval 	if (params->update_rss_flg)
2023f29ffdb6SMintz, Yuval 		if (qed_update_vport_rss(cdev, &params->rss_params, rss))
2024cee4d264SManish Chopra 			params->update_rss_flg = 0;
2025cee4d264SManish Chopra 
2026cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2027cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2028cee4d264SManish Chopra 
2029f29ffdb6SMintz, Yuval 		if (params->update_rss_flg)
2030f29ffdb6SMintz, Yuval 			sp_params.rss_params = &rss[i];
2031f29ffdb6SMintz, Yuval 
2032cee4d264SManish Chopra 		sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2033cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &sp_params,
2034cee4d264SManish Chopra 					 QED_SPQ_MODE_EBLOCK,
2035cee4d264SManish Chopra 					 NULL);
2036cee4d264SManish Chopra 		if (rc) {
2037cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to update VPORT\n");
2038f29ffdb6SMintz, Yuval 			goto out;
2039cee4d264SManish Chopra 		}
2040cee4d264SManish Chopra 
2041cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2042cee4d264SManish Chopra 			   "Updated V-PORT %d: active_flag %d [update %d]\n",
2043cee4d264SManish Chopra 			   params->vport_id, params->vport_active_flg,
2044cee4d264SManish Chopra 			   params->update_vport_active_flg);
2045cee4d264SManish Chopra 	}
2046cee4d264SManish Chopra 
2047f29ffdb6SMintz, Yuval out:
2048f29ffdb6SMintz, Yuval 	vfree(rss);
2049f29ffdb6SMintz, Yuval 	return rc;
2050cee4d264SManish Chopra }
2051cee4d264SManish Chopra 
2052cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev,
20533da7a37aSMintz, Yuval 			 u8 rss_num,
20543da7a37aSMintz, Yuval 			 struct qed_queue_start_common_params *p_params,
2055cee4d264SManish Chopra 			 u16 bd_max_bytes,
2056cee4d264SManish Chopra 			 dma_addr_t bd_chain_phys_addr,
2057cee4d264SManish Chopra 			 dma_addr_t cqe_pbl_addr,
2058cee4d264SManish Chopra 			 u16 cqe_pbl_size,
20593da7a37aSMintz, Yuval 			 struct qed_rxq_start_ret_params *ret_params)
2060cee4d264SManish Chopra {
2061cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
20621a635e48SYuval Mintz 	int rc, hwfn_index;
2063cee4d264SManish Chopra 
20643da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2065cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2066cee4d264SManish Chopra 
20673da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
20683da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2069cee4d264SManish Chopra 
20703da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_start(p_hwfn,
2071cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
20723da7a37aSMintz, Yuval 				    p_params,
2073cee4d264SManish Chopra 				    bd_max_bytes,
2074cee4d264SManish Chopra 				    bd_chain_phys_addr,
20753da7a37aSMintz, Yuval 				    cqe_pbl_addr, cqe_pbl_size, ret_params);
2076cee4d264SManish Chopra 	if (rc) {
20773da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
2078cee4d264SManish Chopra 		return rc;
2079cee4d264SManish Chopra 	}
2080cee4d264SManish Chopra 
2081cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
20823da7a37aSMintz, Yuval 		   "Started RX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
20833da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
20843da7a37aSMintz, Yuval 		   p_params->sb);
2085cee4d264SManish Chopra 
2086cee4d264SManish Chopra 	return 0;
2087cee4d264SManish Chopra }
2088cee4d264SManish Chopra 
20893da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
2090cee4d264SManish Chopra {
2091cee4d264SManish Chopra 	int rc, hwfn_index;
2092cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2093cee4d264SManish Chopra 
20943da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2095cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2096cee4d264SManish Chopra 
20973da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
2098cee4d264SManish Chopra 	if (rc) {
20993da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
2100cee4d264SManish Chopra 		return rc;
2101cee4d264SManish Chopra 	}
2102cee4d264SManish Chopra 
2103cee4d264SManish Chopra 	return 0;
2104cee4d264SManish Chopra }
2105cee4d264SManish Chopra 
2106cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev,
21073da7a37aSMintz, Yuval 			 u8 rss_num,
2108cee4d264SManish Chopra 			 struct qed_queue_start_common_params *p_params,
2109cee4d264SManish Chopra 			 dma_addr_t pbl_addr,
2110cee4d264SManish Chopra 			 u16 pbl_size,
21113da7a37aSMintz, Yuval 			 struct qed_txq_start_ret_params *ret_params)
2112cee4d264SManish Chopra {
2113cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2114cee4d264SManish Chopra 	int rc, hwfn_index;
2115cee4d264SManish Chopra 
21163da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2117cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
21183da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
21193da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2120cee4d264SManish Chopra 
21213da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_start(p_hwfn,
2122cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
21233da7a37aSMintz, Yuval 				    p_params, 0,
21243da7a37aSMintz, Yuval 				    pbl_addr, pbl_size, ret_params);
2125cee4d264SManish Chopra 
2126cee4d264SManish Chopra 	if (rc) {
2127cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2128cee4d264SManish Chopra 		return rc;
2129cee4d264SManish Chopra 	}
2130cee4d264SManish Chopra 
2131cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
21323da7a37aSMintz, Yuval 		   "Started TX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
21333da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
2134cee4d264SManish Chopra 		   p_params->sb);
2135cee4d264SManish Chopra 
2136cee4d264SManish Chopra 	return 0;
2137cee4d264SManish Chopra }
2138cee4d264SManish Chopra 
2139cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10)
2140cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev)
2141cee4d264SManish Chopra {
2142cee4d264SManish Chopra 	qed_hw_stop_fastpath(cdev);
2143cee4d264SManish Chopra 
2144cee4d264SManish Chopra 	return 0;
2145cee4d264SManish Chopra }
2146cee4d264SManish Chopra 
21473da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
2148cee4d264SManish Chopra {
2149cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2150cee4d264SManish Chopra 	int rc, hwfn_index;
2151cee4d264SManish Chopra 
21523da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2153cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2154cee4d264SManish Chopra 
21553da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_stop(p_hwfn, handle);
2156cee4d264SManish Chopra 	if (rc) {
21573da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
2158cee4d264SManish Chopra 		return rc;
2159cee4d264SManish Chopra 	}
2160cee4d264SManish Chopra 
2161cee4d264SManish Chopra 	return 0;
2162cee4d264SManish Chopra }
2163cee4d264SManish Chopra 
2164464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev,
2165464f6645SManish Chopra 			      struct qed_tunn_params *tunn_params)
2166464f6645SManish Chopra {
2167464f6645SManish Chopra 	struct qed_tunn_update_params tunn_info;
2168464f6645SManish Chopra 	int i, rc;
2169464f6645SManish Chopra 
21701408cc1fSYuval Mintz 	if (IS_VF(cdev))
21711408cc1fSYuval Mintz 		return 0;
21721408cc1fSYuval Mintz 
2173464f6645SManish Chopra 	memset(&tunn_info, 0, sizeof(tunn_info));
2174464f6645SManish Chopra 	if (tunn_params->update_vxlan_port == 1) {
2175464f6645SManish Chopra 		tunn_info.update_vxlan_udp_port = 1;
2176464f6645SManish Chopra 		tunn_info.vxlan_udp_port = tunn_params->vxlan_port;
2177464f6645SManish Chopra 	}
2178464f6645SManish Chopra 
2179464f6645SManish Chopra 	if (tunn_params->update_geneve_port == 1) {
2180464f6645SManish Chopra 		tunn_info.update_geneve_udp_port = 1;
2181464f6645SManish Chopra 		tunn_info.geneve_udp_port = tunn_params->geneve_port;
2182464f6645SManish Chopra 	}
2183464f6645SManish Chopra 
2184464f6645SManish Chopra 	for_each_hwfn(cdev, i) {
2185464f6645SManish Chopra 		struct qed_hwfn *hwfn = &cdev->hwfns[i];
2186464f6645SManish Chopra 
2187464f6645SManish Chopra 		rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
2188464f6645SManish Chopra 					       QED_SPQ_MODE_EBLOCK, NULL);
2189464f6645SManish Chopra 
2190464f6645SManish Chopra 		if (rc)
2191464f6645SManish Chopra 			return rc;
2192464f6645SManish Chopra 	}
2193464f6645SManish Chopra 
2194464f6645SManish Chopra 	return 0;
2195464f6645SManish Chopra }
2196464f6645SManish Chopra 
2197cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2198cee4d264SManish Chopra 					enum qed_filter_rx_mode_type type)
2199cee4d264SManish Chopra {
2200cee4d264SManish Chopra 	struct qed_filter_accept_flags accept_flags;
2201cee4d264SManish Chopra 
2202cee4d264SManish Chopra 	memset(&accept_flags, 0, sizeof(accept_flags));
2203cee4d264SManish Chopra 
2204cee4d264SManish Chopra 	accept_flags.update_rx_mode_config = 1;
2205cee4d264SManish Chopra 	accept_flags.update_tx_mode_config = 1;
2206cee4d264SManish Chopra 	accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2207cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2208cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2209cee4d264SManish Chopra 	accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2210cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2211cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2212cee4d264SManish Chopra 
2213cee4d264SManish Chopra 	if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
2214cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2215cee4d264SManish Chopra 						 QED_ACCEPT_MCAST_UNMATCHED;
2216cee4d264SManish Chopra 	else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
2217cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2218cee4d264SManish Chopra 
22193f9b4a69SYuval Mintz 	return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
2220cee4d264SManish Chopra 				     QED_SPQ_MODE_CB, NULL);
2221cee4d264SManish Chopra }
2222cee4d264SManish Chopra 
2223cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev,
2224cee4d264SManish Chopra 				      struct qed_filter_ucast_params *params)
2225cee4d264SManish Chopra {
2226cee4d264SManish Chopra 	struct qed_filter_ucast ucast;
2227cee4d264SManish Chopra 
2228cee4d264SManish Chopra 	if (!params->vlan_valid && !params->mac_valid) {
22291a635e48SYuval Mintz 		DP_NOTICE(cdev,
2230cee4d264SManish Chopra 			  "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
2231cee4d264SManish Chopra 		return -EINVAL;
2232cee4d264SManish Chopra 	}
2233cee4d264SManish Chopra 
2234cee4d264SManish Chopra 	memset(&ucast, 0, sizeof(ucast));
2235cee4d264SManish Chopra 	switch (params->type) {
2236cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2237cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_ADD;
2238cee4d264SManish Chopra 		break;
2239cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2240cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REMOVE;
2241cee4d264SManish Chopra 		break;
2242cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_REPLACE:
2243cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REPLACE;
2244cee4d264SManish Chopra 		break;
2245cee4d264SManish Chopra 	default:
2246cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2247cee4d264SManish Chopra 			  params->type);
2248cee4d264SManish Chopra 	}
2249cee4d264SManish Chopra 
2250cee4d264SManish Chopra 	if (params->vlan_valid && params->mac_valid) {
2251cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC_VLAN;
2252cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2253cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2254cee4d264SManish Chopra 	} else if (params->mac_valid) {
2255cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC;
2256cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2257cee4d264SManish Chopra 	} else {
2258cee4d264SManish Chopra 		ucast.type = QED_FILTER_VLAN;
2259cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2260cee4d264SManish Chopra 	}
2261cee4d264SManish Chopra 
2262cee4d264SManish Chopra 	ucast.is_rx_filter = true;
2263cee4d264SManish Chopra 	ucast.is_tx_filter = true;
2264cee4d264SManish Chopra 
2265cee4d264SManish Chopra 	return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2266cee4d264SManish Chopra }
2267cee4d264SManish Chopra 
2268cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev,
2269cee4d264SManish Chopra 				      struct qed_filter_mcast_params *params)
2270cee4d264SManish Chopra {
2271cee4d264SManish Chopra 	struct qed_filter_mcast mcast;
2272cee4d264SManish Chopra 	int i;
2273cee4d264SManish Chopra 
2274cee4d264SManish Chopra 	memset(&mcast, 0, sizeof(mcast));
2275cee4d264SManish Chopra 	switch (params->type) {
2276cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2277cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_ADD;
2278cee4d264SManish Chopra 		break;
2279cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2280cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_REMOVE;
2281cee4d264SManish Chopra 		break;
2282cee4d264SManish Chopra 	default:
2283cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2284cee4d264SManish Chopra 			  params->type);
2285cee4d264SManish Chopra 	}
2286cee4d264SManish Chopra 
2287cee4d264SManish Chopra 	mcast.num_mc_addrs = params->num;
2288cee4d264SManish Chopra 	for (i = 0; i < mcast.num_mc_addrs; i++)
2289cee4d264SManish Chopra 		ether_addr_copy(mcast.mac[i], params->mac[i]);
2290cee4d264SManish Chopra 
22911a635e48SYuval Mintz 	return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
2292cee4d264SManish Chopra }
2293cee4d264SManish Chopra 
2294cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev,
2295cee4d264SManish Chopra 				struct qed_filter_params *params)
2296cee4d264SManish Chopra {
2297cee4d264SManish Chopra 	enum qed_filter_rx_mode_type accept_flags;
2298cee4d264SManish Chopra 
2299cee4d264SManish Chopra 	switch (params->type) {
2300cee4d264SManish Chopra 	case QED_FILTER_TYPE_UCAST:
2301cee4d264SManish Chopra 		return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2302cee4d264SManish Chopra 	case QED_FILTER_TYPE_MCAST:
2303cee4d264SManish Chopra 		return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2304cee4d264SManish Chopra 	case QED_FILTER_TYPE_RX_MODE:
2305cee4d264SManish Chopra 		accept_flags = params->filter.accept_flags;
2306cee4d264SManish Chopra 		return qed_configure_filter_rx_mode(cdev, accept_flags);
2307cee4d264SManish Chopra 	default:
23081a635e48SYuval Mintz 		DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
2309cee4d264SManish Chopra 		return -EINVAL;
2310cee4d264SManish Chopra 	}
2311cee4d264SManish Chopra }
2312cee4d264SManish Chopra 
2313cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev,
23141a635e48SYuval Mintz 				 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
2315cee4d264SManish Chopra {
2316cee4d264SManish Chopra 	return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2317cee4d264SManish Chopra 				      cqe);
2318cee4d264SManish Chopra }
2319cee4d264SManish Chopra 
23200b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
23210b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass;
23220b55e27dSYuval Mintz #endif
23230b55e27dSYuval Mintz 
2324a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2325a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2326a1d8d8a5SSudarsana Reddy Kalluru #endif
2327a1d8d8a5SSudarsana Reddy Kalluru 
232825c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = {
232925c089d7SYuval Mintz 	.common = &qed_common_ops_pass,
23300b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
23310b55e27dSYuval Mintz 	.iov = &qed_iov_ops_pass,
23320b55e27dSYuval Mintz #endif
2333a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2334a1d8d8a5SSudarsana Reddy Kalluru 	.dcb = &qed_dcbnl_ops_pass,
2335a1d8d8a5SSudarsana Reddy Kalluru #endif
233625c089d7SYuval Mintz 	.fill_dev_info = &qed_fill_eth_dev_info,
2337cc875c2eSYuval Mintz 	.register_ops = &qed_register_eth_ops,
2338eff16960SYuval Mintz 	.check_mac = &qed_check_mac,
2339cee4d264SManish Chopra 	.vport_start = &qed_start_vport,
2340cee4d264SManish Chopra 	.vport_stop = &qed_stop_vport,
2341cee4d264SManish Chopra 	.vport_update = &qed_update_vport,
2342cee4d264SManish Chopra 	.q_rx_start = &qed_start_rxq,
2343cee4d264SManish Chopra 	.q_rx_stop = &qed_stop_rxq,
2344cee4d264SManish Chopra 	.q_tx_start = &qed_start_txq,
2345cee4d264SManish Chopra 	.q_tx_stop = &qed_stop_txq,
2346cee4d264SManish Chopra 	.filter_config = &qed_configure_filter,
2347cee4d264SManish Chopra 	.fastpath_stop = &qed_fastpath_stop,
2348cee4d264SManish Chopra 	.eth_cqe_completion = &qed_fp_cqe_completion,
23499df2ed04SManish Chopra 	.get_vport_stats = &qed_get_vport_stats,
2350464f6645SManish Chopra 	.tunn_config = &qed_tunn_configure,
235125c089d7SYuval Mintz };
235225c089d7SYuval Mintz 
235395114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void)
235425c089d7SYuval Mintz {
235525c089d7SYuval Mintz 	return &qed_eth_ops_pass;
235625c089d7SYuval Mintz }
235725c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops);
235825c089d7SYuval Mintz 
235925c089d7SYuval Mintz void qed_put_eth_ops(void)
236025c089d7SYuval Mintz {
236125c089d7SYuval Mintz 	/* TODO - reference count for module? */
236225c089d7SYuval Mintz }
236325c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops);
2364