125c089d7SYuval Mintz /* QLogic qed NIC Driver 225c089d7SYuval Mintz * Copyright (c) 2015 QLogic Corporation 325c089d7SYuval Mintz * 425c089d7SYuval Mintz * This software is available under the terms of the GNU General Public License 525c089d7SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 625c089d7SYuval Mintz * this source tree. 725c089d7SYuval Mintz */ 825c089d7SYuval Mintz 925c089d7SYuval Mintz #include <linux/types.h> 1025c089d7SYuval Mintz #include <asm/byteorder.h> 1125c089d7SYuval Mintz #include <asm/param.h> 1225c089d7SYuval Mintz #include <linux/delay.h> 1325c089d7SYuval Mintz #include <linux/dma-mapping.h> 1425c089d7SYuval Mintz #include <linux/etherdevice.h> 1525c089d7SYuval Mintz #include <linux/interrupt.h> 1625c089d7SYuval Mintz #include <linux/kernel.h> 1725c089d7SYuval Mintz #include <linux/module.h> 1825c089d7SYuval Mintz #include <linux/pci.h> 1925c089d7SYuval Mintz #include <linux/slab.h> 2025c089d7SYuval Mintz #include <linux/stddef.h> 2125c089d7SYuval Mintz #include <linux/string.h> 2225c089d7SYuval Mintz #include <linux/version.h> 2325c089d7SYuval Mintz #include <linux/workqueue.h> 2425c089d7SYuval Mintz #include <linux/bitops.h> 2525c089d7SYuval Mintz #include <linux/bug.h> 2625c089d7SYuval Mintz #include "qed.h" 2725c089d7SYuval Mintz #include <linux/qed/qed_chain.h> 2825c089d7SYuval Mintz #include "qed_cxt.h" 2925c089d7SYuval Mintz #include "qed_dev_api.h" 3025c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h> 3125c089d7SYuval Mintz #include "qed_hsi.h" 3225c089d7SYuval Mintz #include "qed_hw.h" 3325c089d7SYuval Mintz #include "qed_int.h" 3486622ee7SYuval Mintz #include "qed_mcp.h" 3525c089d7SYuval Mintz #include "qed_reg_addr.h" 3625c089d7SYuval Mintz #include "qed_sp.h" 3725c089d7SYuval Mintz 38cee4d264SManish Chopra enum qed_rss_caps { 39cee4d264SManish Chopra QED_RSS_IPV4 = 0x1, 40cee4d264SManish Chopra QED_RSS_IPV6 = 0x2, 41cee4d264SManish Chopra QED_RSS_IPV4_TCP = 0x4, 42cee4d264SManish Chopra QED_RSS_IPV6_TCP = 0x8, 43cee4d264SManish Chopra QED_RSS_IPV4_UDP = 0x10, 44cee4d264SManish Chopra QED_RSS_IPV6_UDP = 0x20, 45cee4d264SManish Chopra }; 46cee4d264SManish Chopra 47cee4d264SManish Chopra /* Should be the same as ETH_RSS_IND_TABLE_ENTRIES_NUM */ 48cee4d264SManish Chopra #define QED_RSS_IND_TABLE_SIZE 128 49cee4d264SManish Chopra #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 50cee4d264SManish Chopra 51cee4d264SManish Chopra struct qed_rss_params { 52cee4d264SManish Chopra u8 update_rss_config; 53cee4d264SManish Chopra u8 rss_enable; 54cee4d264SManish Chopra u8 rss_eng_id; 55cee4d264SManish Chopra u8 update_rss_capabilities; 56cee4d264SManish Chopra u8 update_rss_ind_table; 57cee4d264SManish Chopra u8 update_rss_key; 58cee4d264SManish Chopra u8 rss_caps; 59cee4d264SManish Chopra u8 rss_table_size_log; 60cee4d264SManish Chopra u16 rss_ind_table[QED_RSS_IND_TABLE_SIZE]; 61cee4d264SManish Chopra u32 rss_key[QED_RSS_KEY_SIZE]; 62cee4d264SManish Chopra }; 63cee4d264SManish Chopra 64cee4d264SManish Chopra enum qed_filter_opcode { 65cee4d264SManish Chopra QED_FILTER_ADD, 66cee4d264SManish Chopra QED_FILTER_REMOVE, 67cee4d264SManish Chopra QED_FILTER_MOVE, 68cee4d264SManish Chopra QED_FILTER_REPLACE, /* Delete all MACs and add new one instead */ 69cee4d264SManish Chopra QED_FILTER_FLUSH, /* Removes all filters */ 70cee4d264SManish Chopra }; 71cee4d264SManish Chopra 72cee4d264SManish Chopra enum qed_filter_ucast_type { 73cee4d264SManish Chopra QED_FILTER_MAC, 74cee4d264SManish Chopra QED_FILTER_VLAN, 75cee4d264SManish Chopra QED_FILTER_MAC_VLAN, 76cee4d264SManish Chopra QED_FILTER_INNER_MAC, 77cee4d264SManish Chopra QED_FILTER_INNER_VLAN, 78cee4d264SManish Chopra QED_FILTER_INNER_PAIR, 79cee4d264SManish Chopra QED_FILTER_INNER_MAC_VNI_PAIR, 80cee4d264SManish Chopra QED_FILTER_MAC_VNI_PAIR, 81cee4d264SManish Chopra QED_FILTER_VNI, 82cee4d264SManish Chopra }; 83cee4d264SManish Chopra 84cee4d264SManish Chopra struct qed_filter_ucast { 85cee4d264SManish Chopra enum qed_filter_opcode opcode; 86cee4d264SManish Chopra enum qed_filter_ucast_type type; 87cee4d264SManish Chopra u8 is_rx_filter; 88cee4d264SManish Chopra u8 is_tx_filter; 89cee4d264SManish Chopra u8 vport_to_add_to; 90cee4d264SManish Chopra u8 vport_to_remove_from; 91cee4d264SManish Chopra unsigned char mac[ETH_ALEN]; 92cee4d264SManish Chopra u8 assert_on_error; 93cee4d264SManish Chopra u16 vlan; 94cee4d264SManish Chopra u32 vni; 95cee4d264SManish Chopra }; 96cee4d264SManish Chopra 97cee4d264SManish Chopra struct qed_filter_mcast { 98cee4d264SManish Chopra /* MOVE is not supported for multicast */ 99cee4d264SManish Chopra enum qed_filter_opcode opcode; 100cee4d264SManish Chopra u8 vport_to_add_to; 101cee4d264SManish Chopra u8 vport_to_remove_from; 102cee4d264SManish Chopra u8 num_mc_addrs; 103cee4d264SManish Chopra #define QED_MAX_MC_ADDRS 64 104cee4d264SManish Chopra unsigned char mac[QED_MAX_MC_ADDRS][ETH_ALEN]; 105cee4d264SManish Chopra }; 106cee4d264SManish Chopra 107cee4d264SManish Chopra struct qed_filter_accept_flags { 108cee4d264SManish Chopra u8 update_rx_mode_config; 109cee4d264SManish Chopra u8 update_tx_mode_config; 110cee4d264SManish Chopra u8 rx_accept_filter; 111cee4d264SManish Chopra u8 tx_accept_filter; 112cee4d264SManish Chopra #define QED_ACCEPT_NONE 0x01 113cee4d264SManish Chopra #define QED_ACCEPT_UCAST_MATCHED 0x02 114cee4d264SManish Chopra #define QED_ACCEPT_UCAST_UNMATCHED 0x04 115cee4d264SManish Chopra #define QED_ACCEPT_MCAST_MATCHED 0x08 116cee4d264SManish Chopra #define QED_ACCEPT_MCAST_UNMATCHED 0x10 117cee4d264SManish Chopra #define QED_ACCEPT_BCAST 0x20 118cee4d264SManish Chopra }; 119cee4d264SManish Chopra 120cee4d264SManish Chopra struct qed_sp_vport_update_params { 121cee4d264SManish Chopra u16 opaque_fid; 122cee4d264SManish Chopra u8 vport_id; 123cee4d264SManish Chopra u8 update_vport_active_rx_flg; 124cee4d264SManish Chopra u8 vport_active_rx_flg; 125cee4d264SManish Chopra u8 update_vport_active_tx_flg; 126cee4d264SManish Chopra u8 vport_active_tx_flg; 127cee4d264SManish Chopra u8 update_approx_mcast_flg; 1283f9b4a69SYuval Mintz u8 update_accept_any_vlan_flg; 1293f9b4a69SYuval Mintz u8 accept_any_vlan; 130cee4d264SManish Chopra unsigned long bins[8]; 131cee4d264SManish Chopra struct qed_rss_params *rss_params; 132cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 133cee4d264SManish Chopra }; 134cee4d264SManish Chopra 135088c8618SManish Chopra enum qed_tpa_mode { 136088c8618SManish Chopra QED_TPA_MODE_NONE, 137088c8618SManish Chopra QED_TPA_MODE_UNUSED, 138088c8618SManish Chopra QED_TPA_MODE_GRO, 139088c8618SManish Chopra QED_TPA_MODE_MAX 140088c8618SManish Chopra }; 141088c8618SManish Chopra 142088c8618SManish Chopra struct qed_sp_vport_start_params { 143088c8618SManish Chopra enum qed_tpa_mode tpa_mode; 144088c8618SManish Chopra bool remove_inner_vlan; 145088c8618SManish Chopra bool drop_ttl0; 146088c8618SManish Chopra u8 max_buffers_per_cqe; 147088c8618SManish Chopra u32 concrete_fid; 148088c8618SManish Chopra u16 opaque_fid; 149088c8618SManish Chopra u8 vport_id; 150088c8618SManish Chopra u16 mtu; 151088c8618SManish Chopra }; 152088c8618SManish Chopra 153cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16 154cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41 155cee4d264SManish Chopra 156cee4d264SManish Chopra static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 157088c8618SManish Chopra struct qed_sp_vport_start_params *p_params) 158cee4d264SManish Chopra { 159cee4d264SManish Chopra struct vport_start_ramrod_data *p_ramrod = NULL; 160cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 16106f56b81SYuval Mintz struct qed_sp_init_data init_data; 162cee4d264SManish Chopra int rc = -EINVAL; 163cee4d264SManish Chopra u16 rx_mode = 0; 164cee4d264SManish Chopra u8 abs_vport_id = 0; 165cee4d264SManish Chopra 166088c8618SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 167cee4d264SManish Chopra if (rc != 0) 168cee4d264SManish Chopra return rc; 169cee4d264SManish Chopra 17006f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 17106f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 172088c8618SManish Chopra init_data.opaque_fid = p_params->opaque_fid; 17306f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 174cee4d264SManish Chopra 175cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 176cee4d264SManish Chopra ETH_RAMROD_VPORT_START, 17706f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 178cee4d264SManish Chopra if (rc) 179cee4d264SManish Chopra return rc; 180cee4d264SManish Chopra 181cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_start; 182cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 183cee4d264SManish Chopra 184088c8618SManish Chopra p_ramrod->mtu = cpu_to_le16(p_params->mtu); 185088c8618SManish Chopra p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 186088c8618SManish Chopra p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 187cee4d264SManish Chopra 188cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 189cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 190cee4d264SManish Chopra 191cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 192cee4d264SManish Chopra 193cee4d264SManish Chopra /* TPA related fields */ 194cee4d264SManish Chopra memset(&p_ramrod->tpa_param, 0, 195cee4d264SManish Chopra sizeof(struct eth_vport_tpa_param)); 196cee4d264SManish Chopra 197088c8618SManish Chopra p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; 198088c8618SManish Chopra 199088c8618SManish Chopra switch (p_params->tpa_mode) { 200088c8618SManish Chopra case QED_TPA_MODE_GRO: 201088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 202088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_size = (u16)-1; 203088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; 204088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; 205088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; 206088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; 207088c8618SManish Chopra p_ramrod->tpa_param.tpa_pkt_split_flg = 1; 208088c8618SManish Chopra p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; 209088c8618SManish Chopra break; 210088c8618SManish Chopra default: 211088c8618SManish Chopra break; 212088c8618SManish Chopra } 213088c8618SManish Chopra 214cee4d264SManish Chopra /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 215cee4d264SManish Chopra p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 216088c8618SManish Chopra p_params->concrete_fid); 217cee4d264SManish Chopra 218cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 219cee4d264SManish Chopra } 220cee4d264SManish Chopra 221cee4d264SManish Chopra static int 222cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 223cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 224cee4d264SManish Chopra struct qed_rss_params *p_params) 225cee4d264SManish Chopra { 226cee4d264SManish Chopra struct eth_vport_rss_config *rss = &p_ramrod->rss_config; 227cee4d264SManish Chopra u16 abs_l2_queue = 0, capabilities = 0; 228cee4d264SManish Chopra int rc = 0, i; 229cee4d264SManish Chopra 230cee4d264SManish Chopra if (!p_params) { 231cee4d264SManish Chopra p_ramrod->common.update_rss_flg = 0; 232cee4d264SManish Chopra return rc; 233cee4d264SManish Chopra } 234cee4d264SManish Chopra 235cee4d264SManish Chopra BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != 236cee4d264SManish Chopra ETH_RSS_IND_TABLE_ENTRIES_NUM); 237cee4d264SManish Chopra 238cee4d264SManish Chopra rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id); 239cee4d264SManish Chopra if (rc) 240cee4d264SManish Chopra return rc; 241cee4d264SManish Chopra 242cee4d264SManish Chopra p_ramrod->common.update_rss_flg = p_params->update_rss_config; 243cee4d264SManish Chopra rss->update_rss_capabilities = p_params->update_rss_capabilities; 244cee4d264SManish Chopra rss->update_rss_ind_table = p_params->update_rss_ind_table; 245cee4d264SManish Chopra rss->update_rss_key = p_params->update_rss_key; 246cee4d264SManish Chopra 247cee4d264SManish Chopra rss->rss_mode = p_params->rss_enable ? 248cee4d264SManish Chopra ETH_VPORT_RSS_MODE_REGULAR : 249cee4d264SManish Chopra ETH_VPORT_RSS_MODE_DISABLED; 250cee4d264SManish Chopra 251cee4d264SManish Chopra SET_FIELD(capabilities, 252cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 253cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV4)); 254cee4d264SManish Chopra SET_FIELD(capabilities, 255cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 256cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV6)); 257cee4d264SManish Chopra SET_FIELD(capabilities, 258cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 259cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV4_TCP)); 260cee4d264SManish Chopra SET_FIELD(capabilities, 261cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 262cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV6_TCP)); 263cee4d264SManish Chopra SET_FIELD(capabilities, 264cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 265cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV4_UDP)); 266cee4d264SManish Chopra SET_FIELD(capabilities, 267cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 268cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV6_UDP)); 269cee4d264SManish Chopra rss->tbl_size = p_params->rss_table_size_log; 270cee4d264SManish Chopra 271cee4d264SManish Chopra rss->capabilities = cpu_to_le16(capabilities); 272cee4d264SManish Chopra 273cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 274cee4d264SManish Chopra "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 275cee4d264SManish Chopra p_ramrod->common.update_rss_flg, 276cee4d264SManish Chopra rss->rss_mode, rss->update_rss_capabilities, 277cee4d264SManish Chopra capabilities, rss->update_rss_ind_table, 278cee4d264SManish Chopra rss->update_rss_key); 279cee4d264SManish Chopra 280cee4d264SManish Chopra for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 281cee4d264SManish Chopra rc = qed_fw_l2_queue(p_hwfn, 282cee4d264SManish Chopra (u8)p_params->rss_ind_table[i], 283cee4d264SManish Chopra &abs_l2_queue); 284cee4d264SManish Chopra if (rc) 285cee4d264SManish Chopra return rc; 286cee4d264SManish Chopra 287cee4d264SManish Chopra rss->indirection_table[i] = cpu_to_le16(abs_l2_queue); 288cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n", 289cee4d264SManish Chopra i, rss->indirection_table[i]); 290cee4d264SManish Chopra } 291cee4d264SManish Chopra 292cee4d264SManish Chopra for (i = 0; i < 10; i++) 293cee4d264SManish Chopra rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]); 294cee4d264SManish Chopra 295cee4d264SManish Chopra return rc; 296cee4d264SManish Chopra } 297cee4d264SManish Chopra 298cee4d264SManish Chopra static void 299cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 300cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 301cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags) 302cee4d264SManish Chopra { 303cee4d264SManish Chopra p_ramrod->common.update_rx_mode_flg = 304cee4d264SManish Chopra accept_flags.update_rx_mode_config; 305cee4d264SManish Chopra 306cee4d264SManish Chopra p_ramrod->common.update_tx_mode_flg = 307cee4d264SManish Chopra accept_flags.update_tx_mode_config; 308cee4d264SManish Chopra 309cee4d264SManish Chopra /* Set Rx mode accept flags */ 310cee4d264SManish Chopra if (p_ramrod->common.update_rx_mode_flg) { 311cee4d264SManish Chopra u8 accept_filter = accept_flags.rx_accept_filter; 312cee4d264SManish Chopra u16 state = 0; 313cee4d264SManish Chopra 314cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 315cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 316cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 317cee4d264SManish Chopra 318cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 319cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 320cee4d264SManish Chopra 321cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 322cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 323cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 324cee4d264SManish Chopra 325cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 326cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 327cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 328cee4d264SManish Chopra 329cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 330cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 331cee4d264SManish Chopra 332cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(state); 333cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 334cee4d264SManish Chopra "p_ramrod->rx_mode.state = 0x%x\n", state); 335cee4d264SManish Chopra } 336cee4d264SManish Chopra 337cee4d264SManish Chopra /* Set Tx mode accept flags */ 338cee4d264SManish Chopra if (p_ramrod->common.update_tx_mode_flg) { 339cee4d264SManish Chopra u8 accept_filter = accept_flags.tx_accept_filter; 340cee4d264SManish Chopra u16 state = 0; 341cee4d264SManish Chopra 342cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 343cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 344cee4d264SManish Chopra 345cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL, 346cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) && 347cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 348cee4d264SManish Chopra 349cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 350cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 351cee4d264SManish Chopra 352cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 353cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 354cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 355cee4d264SManish Chopra 356cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 357cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 358cee4d264SManish Chopra 359cee4d264SManish Chopra p_ramrod->tx_mode.state = cpu_to_le16(state); 360cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 361cee4d264SManish Chopra "p_ramrod->tx_mode.state = 0x%x\n", state); 362cee4d264SManish Chopra } 363cee4d264SManish Chopra } 364cee4d264SManish Chopra 365cee4d264SManish Chopra static void 366cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 367cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 368cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params) 369cee4d264SManish Chopra { 370cee4d264SManish Chopra int i; 371cee4d264SManish Chopra 372cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 373cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 374cee4d264SManish Chopra 375cee4d264SManish Chopra if (p_params->update_approx_mcast_flg) { 376cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 377cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 378cee4d264SManish Chopra u32 *p_bins = (u32 *)p_params->bins; 379cee4d264SManish Chopra __le32 val = cpu_to_le32(p_bins[i]); 380cee4d264SManish Chopra 381cee4d264SManish Chopra p_ramrod->approx_mcast.bins[i] = val; 382cee4d264SManish Chopra } 383cee4d264SManish Chopra } 384cee4d264SManish Chopra } 385cee4d264SManish Chopra 386cee4d264SManish Chopra static int 387cee4d264SManish Chopra qed_sp_vport_update(struct qed_hwfn *p_hwfn, 388cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params, 389cee4d264SManish Chopra enum spq_mode comp_mode, 390cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 391cee4d264SManish Chopra { 392cee4d264SManish Chopra struct qed_rss_params *p_rss_params = p_params->rss_params; 393cee4d264SManish Chopra struct vport_update_ramrod_data_cmn *p_cmn; 39406f56b81SYuval Mintz struct qed_sp_init_data init_data; 395cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 396cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 397cee4d264SManish Chopra u8 abs_vport_id = 0; 398cee4d264SManish Chopra int rc = -EINVAL; 399cee4d264SManish Chopra 400cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 401cee4d264SManish Chopra if (rc != 0) 402cee4d264SManish Chopra return rc; 403cee4d264SManish Chopra 40406f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 40506f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 40606f56b81SYuval Mintz init_data.opaque_fid = p_params->opaque_fid; 40706f56b81SYuval Mintz init_data.comp_mode = comp_mode; 40806f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 409cee4d264SManish Chopra 410cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 411cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 41206f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 413cee4d264SManish Chopra if (rc) 414cee4d264SManish Chopra return rc; 415cee4d264SManish Chopra 416cee4d264SManish Chopra /* Copy input params to ramrod according to FW struct */ 417cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 418cee4d264SManish Chopra p_cmn = &p_ramrod->common; 419cee4d264SManish Chopra 420cee4d264SManish Chopra p_cmn->vport_id = abs_vport_id; 421cee4d264SManish Chopra p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 422cee4d264SManish Chopra p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 423cee4d264SManish Chopra p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 424cee4d264SManish Chopra p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 4253f9b4a69SYuval Mintz p_cmn->accept_any_vlan = p_params->accept_any_vlan; 4263f9b4a69SYuval Mintz p_cmn->update_accept_any_vlan_flg = 4273f9b4a69SYuval Mintz p_params->update_accept_any_vlan_flg; 428cee4d264SManish Chopra rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 429cee4d264SManish Chopra if (rc) { 430cee4d264SManish Chopra /* Return spq entry which is taken in qed_sp_init_request()*/ 431cee4d264SManish Chopra qed_spq_return_entry(p_hwfn, p_ent); 432cee4d264SManish Chopra return rc; 433cee4d264SManish Chopra } 434cee4d264SManish Chopra 435cee4d264SManish Chopra /* Update mcast bins for VFs, PF doesn't use this functionality */ 436cee4d264SManish Chopra qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 437cee4d264SManish Chopra 438cee4d264SManish Chopra qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 439cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 440cee4d264SManish Chopra } 441cee4d264SManish Chopra 442cee4d264SManish Chopra static int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, 443cee4d264SManish Chopra u16 opaque_fid, 444cee4d264SManish Chopra u8 vport_id) 445cee4d264SManish Chopra { 446cee4d264SManish Chopra struct vport_stop_ramrod_data *p_ramrod; 44706f56b81SYuval Mintz struct qed_sp_init_data init_data; 448cee4d264SManish Chopra struct qed_spq_entry *p_ent; 449cee4d264SManish Chopra u8 abs_vport_id = 0; 450cee4d264SManish Chopra int rc; 451cee4d264SManish Chopra 452cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 453cee4d264SManish Chopra if (rc != 0) 454cee4d264SManish Chopra return rc; 455cee4d264SManish Chopra 45606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 45706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 45806f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 45906f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 460cee4d264SManish Chopra 461cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 462cee4d264SManish Chopra ETH_RAMROD_VPORT_STOP, 46306f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 464cee4d264SManish Chopra if (rc) 465cee4d264SManish Chopra return rc; 466cee4d264SManish Chopra 467cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_stop; 468cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 469cee4d264SManish Chopra 470cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 471cee4d264SManish Chopra } 472cee4d264SManish Chopra 473cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev, 474cee4d264SManish Chopra u8 vport, 475cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags, 4763f9b4a69SYuval Mintz u8 update_accept_any_vlan, 4773f9b4a69SYuval Mintz u8 accept_any_vlan, 478cee4d264SManish Chopra enum spq_mode comp_mode, 479cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 480cee4d264SManish Chopra { 481cee4d264SManish Chopra struct qed_sp_vport_update_params vport_update_params; 482cee4d264SManish Chopra int i, rc; 483cee4d264SManish Chopra 484cee4d264SManish Chopra /* Prepare and send the vport rx_mode change */ 485cee4d264SManish Chopra memset(&vport_update_params, 0, sizeof(vport_update_params)); 486cee4d264SManish Chopra vport_update_params.vport_id = vport; 487cee4d264SManish Chopra vport_update_params.accept_flags = accept_flags; 4883f9b4a69SYuval Mintz vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 4893f9b4a69SYuval Mintz vport_update_params.accept_any_vlan = accept_any_vlan; 490cee4d264SManish Chopra 491cee4d264SManish Chopra for_each_hwfn(cdev, i) { 492cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 493cee4d264SManish Chopra 494cee4d264SManish Chopra vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 495cee4d264SManish Chopra 496cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 497cee4d264SManish Chopra comp_mode, p_comp_data); 498cee4d264SManish Chopra if (rc != 0) { 499cee4d264SManish Chopra DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 500cee4d264SManish Chopra return rc; 501cee4d264SManish Chopra } 502cee4d264SManish Chopra 503cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 504cee4d264SManish Chopra "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 505cee4d264SManish Chopra accept_flags.rx_accept_filter, 506cee4d264SManish Chopra accept_flags.tx_accept_filter); 5073f9b4a69SYuval Mintz if (update_accept_any_vlan) 5083f9b4a69SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 5093f9b4a69SYuval Mintz "accept_any_vlan=%d configured\n", 5103f9b4a69SYuval Mintz accept_any_vlan); 511cee4d264SManish Chopra } 512cee4d264SManish Chopra 513cee4d264SManish Chopra return 0; 514cee4d264SManish Chopra } 515cee4d264SManish Chopra 516cee4d264SManish Chopra static int qed_sp_release_queue_cid( 517cee4d264SManish Chopra struct qed_hwfn *p_hwfn, 518cee4d264SManish Chopra struct qed_hw_cid_data *p_cid_data) 519cee4d264SManish Chopra { 520cee4d264SManish Chopra if (!p_cid_data->b_cid_allocated) 521cee4d264SManish Chopra return 0; 522cee4d264SManish Chopra 523cee4d264SManish Chopra qed_cxt_release_cid(p_hwfn, p_cid_data->cid); 524cee4d264SManish Chopra 525cee4d264SManish Chopra p_cid_data->b_cid_allocated = false; 526cee4d264SManish Chopra 527cee4d264SManish Chopra return 0; 528cee4d264SManish Chopra } 529cee4d264SManish Chopra 530cee4d264SManish Chopra static int 531cee4d264SManish Chopra qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 532cee4d264SManish Chopra u16 opaque_fid, 533cee4d264SManish Chopra u32 cid, 534cee4d264SManish Chopra struct qed_queue_start_common_params *params, 535cee4d264SManish Chopra u8 stats_id, 536cee4d264SManish Chopra u16 bd_max_bytes, 537cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 538cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 539cee4d264SManish Chopra u16 cqe_pbl_size) 540cee4d264SManish Chopra { 541cee4d264SManish Chopra struct rx_queue_start_ramrod_data *p_ramrod = NULL; 542cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 54306f56b81SYuval Mintz struct qed_sp_init_data init_data; 544cee4d264SManish Chopra struct qed_hw_cid_data *p_rx_cid; 545cee4d264SManish Chopra u16 abs_rx_q_id = 0; 546cee4d264SManish Chopra u8 abs_vport_id = 0; 547cee4d264SManish Chopra int rc = -EINVAL; 548cee4d264SManish Chopra 549cee4d264SManish Chopra /* Store information for the stop */ 550cee4d264SManish Chopra p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 551cee4d264SManish Chopra p_rx_cid->cid = cid; 552cee4d264SManish Chopra p_rx_cid->opaque_fid = opaque_fid; 553cee4d264SManish Chopra p_rx_cid->vport_id = params->vport_id; 554cee4d264SManish Chopra 555cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id); 556cee4d264SManish Chopra if (rc != 0) 557cee4d264SManish Chopra return rc; 558cee4d264SManish Chopra 559cee4d264SManish Chopra rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id); 560cee4d264SManish Chopra if (rc != 0) 561cee4d264SManish Chopra return rc; 562cee4d264SManish Chopra 563cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 564cee4d264SManish Chopra "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 565cee4d264SManish Chopra opaque_fid, cid, params->queue_id, params->vport_id, 566cee4d264SManish Chopra params->sb); 567cee4d264SManish Chopra 56806f56b81SYuval Mintz /* Get SPQ entry */ 56906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 57006f56b81SYuval Mintz init_data.cid = cid; 57106f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 57206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 573cee4d264SManish Chopra 574cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 575cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_START, 57606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 577cee4d264SManish Chopra if (rc) 578cee4d264SManish Chopra return rc; 579cee4d264SManish Chopra 580cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_start; 581cee4d264SManish Chopra 582cee4d264SManish Chopra p_ramrod->sb_id = cpu_to_le16(params->sb); 583cee4d264SManish Chopra p_ramrod->sb_index = params->sb_idx; 584cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 585cee4d264SManish Chopra p_ramrod->stats_counter_id = stats_id; 586cee4d264SManish Chopra p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 587cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 0; 588cee4d264SManish Chopra p_ramrod->complete_event_flg = 1; 589cee4d264SManish Chopra 590cee4d264SManish Chopra p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 59194494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 592cee4d264SManish Chopra 593cee4d264SManish Chopra p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 59494494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 595cee4d264SManish Chopra 596cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 597cee4d264SManish Chopra 598cee4d264SManish Chopra return rc; 599cee4d264SManish Chopra } 600cee4d264SManish Chopra 601cee4d264SManish Chopra static int 602cee4d264SManish Chopra qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 603cee4d264SManish Chopra u16 opaque_fid, 604cee4d264SManish Chopra struct qed_queue_start_common_params *params, 605cee4d264SManish Chopra u16 bd_max_bytes, 606cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 607cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 608cee4d264SManish Chopra u16 cqe_pbl_size, 609cee4d264SManish Chopra void __iomem **pp_prod) 610cee4d264SManish Chopra { 611cee4d264SManish Chopra struct qed_hw_cid_data *p_rx_cid; 612cee4d264SManish Chopra u64 init_prod_val = 0; 613cee4d264SManish Chopra u16 abs_l2_queue = 0; 614cee4d264SManish Chopra u8 abs_stats_id = 0; 615cee4d264SManish Chopra int rc; 616cee4d264SManish Chopra 617cee4d264SManish Chopra rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue); 618cee4d264SManish Chopra if (rc != 0) 619cee4d264SManish Chopra return rc; 620cee4d264SManish Chopra 621cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id); 622cee4d264SManish Chopra if (rc != 0) 623cee4d264SManish Chopra return rc; 624cee4d264SManish Chopra 625cee4d264SManish Chopra *pp_prod = (u8 __iomem *)p_hwfn->regview + 626cee4d264SManish Chopra GTT_BAR0_MAP_REG_MSDM_RAM + 627cee4d264SManish Chopra MSTORM_PRODS_OFFSET(abs_l2_queue); 628cee4d264SManish Chopra 629cee4d264SManish Chopra /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 630cee4d264SManish Chopra __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64), 631cee4d264SManish Chopra (u32 *)(&init_prod_val)); 632cee4d264SManish Chopra 633cee4d264SManish Chopra /* Allocate a CID for the queue */ 634cee4d264SManish Chopra p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 635cee4d264SManish Chopra rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 636cee4d264SManish Chopra &p_rx_cid->cid); 637cee4d264SManish Chopra if (rc) { 638cee4d264SManish Chopra DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 639cee4d264SManish Chopra return rc; 640cee4d264SManish Chopra } 641cee4d264SManish Chopra p_rx_cid->b_cid_allocated = true; 642cee4d264SManish Chopra 643cee4d264SManish Chopra rc = qed_sp_eth_rxq_start_ramrod(p_hwfn, 644cee4d264SManish Chopra opaque_fid, 645cee4d264SManish Chopra p_rx_cid->cid, 646cee4d264SManish Chopra params, 647cee4d264SManish Chopra abs_stats_id, 648cee4d264SManish Chopra bd_max_bytes, 649cee4d264SManish Chopra bd_chain_phys_addr, 650cee4d264SManish Chopra cqe_pbl_addr, 651cee4d264SManish Chopra cqe_pbl_size); 652cee4d264SManish Chopra 653cee4d264SManish Chopra if (rc != 0) 654cee4d264SManish Chopra qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 655cee4d264SManish Chopra 656cee4d264SManish Chopra return rc; 657cee4d264SManish Chopra } 658cee4d264SManish Chopra 659cee4d264SManish Chopra static int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 660cee4d264SManish Chopra u16 rx_queue_id, 661cee4d264SManish Chopra bool eq_completion_only, 662cee4d264SManish Chopra bool cqe_completion) 663cee4d264SManish Chopra { 664cee4d264SManish Chopra struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id]; 665cee4d264SManish Chopra struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 666cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 66706f56b81SYuval Mintz struct qed_sp_init_data init_data; 668cee4d264SManish Chopra u16 abs_rx_q_id = 0; 669cee4d264SManish Chopra int rc = -EINVAL; 670cee4d264SManish Chopra 67106f56b81SYuval Mintz /* Get SPQ entry */ 67206f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 67306f56b81SYuval Mintz init_data.cid = p_rx_cid->cid; 67406f56b81SYuval Mintz init_data.opaque_fid = p_rx_cid->opaque_fid; 67506f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 676cee4d264SManish Chopra 677cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 678cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_STOP, 67906f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 680cee4d264SManish Chopra if (rc) 681cee4d264SManish Chopra return rc; 682cee4d264SManish Chopra 683cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_stop; 684cee4d264SManish Chopra 685cee4d264SManish Chopra qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); 686cee4d264SManish Chopra qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id); 687cee4d264SManish Chopra p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 688cee4d264SManish Chopra 689cee4d264SManish Chopra /* Cleaning the queue requires the completion to arrive there. 690cee4d264SManish Chopra * In addition, VFs require the answer to come as eqe to PF. 691cee4d264SManish Chopra */ 692cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 693cee4d264SManish Chopra (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) && 694cee4d264SManish Chopra !eq_completion_only) || cqe_completion; 695cee4d264SManish Chopra p_ramrod->complete_event_flg = 696cee4d264SManish Chopra !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) || 697cee4d264SManish Chopra eq_completion_only; 698cee4d264SManish Chopra 699cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 700cee4d264SManish Chopra if (rc) 701cee4d264SManish Chopra return rc; 702cee4d264SManish Chopra 703cee4d264SManish Chopra return qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 704cee4d264SManish Chopra } 705cee4d264SManish Chopra 706cee4d264SManish Chopra static int 707cee4d264SManish Chopra qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 708cee4d264SManish Chopra u16 opaque_fid, 709cee4d264SManish Chopra u32 cid, 710cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 711cee4d264SManish Chopra u8 stats_id, 712cee4d264SManish Chopra dma_addr_t pbl_addr, 713cee4d264SManish Chopra u16 pbl_size, 714cee4d264SManish Chopra union qed_qm_pq_params *p_pq_params) 715cee4d264SManish Chopra { 716cee4d264SManish Chopra struct tx_queue_start_ramrod_data *p_ramrod = NULL; 717cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 71806f56b81SYuval Mintz struct qed_sp_init_data init_data; 719cee4d264SManish Chopra struct qed_hw_cid_data *p_tx_cid; 720cee4d264SManish Chopra u8 abs_vport_id; 721cee4d264SManish Chopra int rc = -EINVAL; 722cee4d264SManish Chopra u16 pq_id; 723cee4d264SManish Chopra 724cee4d264SManish Chopra /* Store information for the stop */ 725cee4d264SManish Chopra p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 726cee4d264SManish Chopra p_tx_cid->cid = cid; 727cee4d264SManish Chopra p_tx_cid->opaque_fid = opaque_fid; 728cee4d264SManish Chopra 729cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 730cee4d264SManish Chopra if (rc) 731cee4d264SManish Chopra return rc; 732cee4d264SManish Chopra 73306f56b81SYuval Mintz /* Get SPQ entry */ 73406f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 73506f56b81SYuval Mintz init_data.cid = cid; 73606f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 73706f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 738cee4d264SManish Chopra 73906f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 740cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_START, 74106f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 742cee4d264SManish Chopra if (rc) 743cee4d264SManish Chopra return rc; 744cee4d264SManish Chopra 745cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.tx_queue_start; 746cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 747cee4d264SManish Chopra 748cee4d264SManish Chopra p_ramrod->sb_id = cpu_to_le16(p_params->sb); 749cee4d264SManish Chopra p_ramrod->sb_index = p_params->sb_idx; 750cee4d264SManish Chopra p_ramrod->stats_counter_id = stats_id; 751cee4d264SManish Chopra 752cee4d264SManish Chopra p_ramrod->pbl_size = cpu_to_le16(pbl_size); 75394494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 754cee4d264SManish Chopra 755cee4d264SManish Chopra pq_id = qed_get_qm_pq(p_hwfn, 756cee4d264SManish Chopra PROTOCOLID_ETH, 757cee4d264SManish Chopra p_pq_params); 758cee4d264SManish Chopra p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 759cee4d264SManish Chopra 760cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 761cee4d264SManish Chopra } 762cee4d264SManish Chopra 763cee4d264SManish Chopra static int 764cee4d264SManish Chopra qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 765cee4d264SManish Chopra u16 opaque_fid, 766cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 767cee4d264SManish Chopra dma_addr_t pbl_addr, 768cee4d264SManish Chopra u16 pbl_size, 769cee4d264SManish Chopra void __iomem **pp_doorbell) 770cee4d264SManish Chopra { 771cee4d264SManish Chopra struct qed_hw_cid_data *p_tx_cid; 772cee4d264SManish Chopra union qed_qm_pq_params pq_params; 773cee4d264SManish Chopra u8 abs_stats_id = 0; 774cee4d264SManish Chopra int rc; 775cee4d264SManish Chopra 776cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id); 777cee4d264SManish Chopra if (rc) 778cee4d264SManish Chopra return rc; 779cee4d264SManish Chopra 780cee4d264SManish Chopra p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 781cee4d264SManish Chopra memset(p_tx_cid, 0, sizeof(*p_tx_cid)); 782cee4d264SManish Chopra memset(&pq_params, 0, sizeof(pq_params)); 783cee4d264SManish Chopra 784cee4d264SManish Chopra /* Allocate a CID for the queue */ 785cee4d264SManish Chopra rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 786cee4d264SManish Chopra &p_tx_cid->cid); 787cee4d264SManish Chopra if (rc) { 788cee4d264SManish Chopra DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 789cee4d264SManish Chopra return rc; 790cee4d264SManish Chopra } 791cee4d264SManish Chopra p_tx_cid->b_cid_allocated = true; 792cee4d264SManish Chopra 793cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 794cee4d264SManish Chopra "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 795cee4d264SManish Chopra opaque_fid, p_tx_cid->cid, 796cee4d264SManish Chopra p_params->queue_id, p_params->vport_id, p_params->sb); 797cee4d264SManish Chopra 798cee4d264SManish Chopra rc = qed_sp_eth_txq_start_ramrod(p_hwfn, 799cee4d264SManish Chopra opaque_fid, 800cee4d264SManish Chopra p_tx_cid->cid, 801cee4d264SManish Chopra p_params, 802cee4d264SManish Chopra abs_stats_id, 803cee4d264SManish Chopra pbl_addr, 804cee4d264SManish Chopra pbl_size, 805cee4d264SManish Chopra &pq_params); 806cee4d264SManish Chopra 807cee4d264SManish Chopra *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + 808cee4d264SManish Chopra qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY); 809cee4d264SManish Chopra 810cee4d264SManish Chopra if (rc) 811cee4d264SManish Chopra qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 812cee4d264SManish Chopra 813cee4d264SManish Chopra return rc; 814cee4d264SManish Chopra } 815cee4d264SManish Chopra 816cee4d264SManish Chopra static int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, 817cee4d264SManish Chopra u16 tx_queue_id) 818cee4d264SManish Chopra { 819cee4d264SManish Chopra struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id]; 820cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 82106f56b81SYuval Mintz struct qed_sp_init_data init_data; 822cee4d264SManish Chopra int rc = -EINVAL; 823cee4d264SManish Chopra 82406f56b81SYuval Mintz /* Get SPQ entry */ 82506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 82606f56b81SYuval Mintz init_data.cid = p_tx_cid->cid; 82706f56b81SYuval Mintz init_data.opaque_fid = p_tx_cid->opaque_fid; 82806f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 829cee4d264SManish Chopra 830cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 831cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_STOP, 83206f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 833cee4d264SManish Chopra if (rc) 834cee4d264SManish Chopra return rc; 835cee4d264SManish Chopra 836cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 837cee4d264SManish Chopra if (rc) 838cee4d264SManish Chopra return rc; 839cee4d264SManish Chopra 840cee4d264SManish Chopra return qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 841cee4d264SManish Chopra } 842cee4d264SManish Chopra 843cee4d264SManish Chopra static enum eth_filter_action 844cee4d264SManish Chopra qed_filter_action(enum qed_filter_opcode opcode) 845cee4d264SManish Chopra { 846cee4d264SManish Chopra enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 847cee4d264SManish Chopra 848cee4d264SManish Chopra switch (opcode) { 849cee4d264SManish Chopra case QED_FILTER_ADD: 850cee4d264SManish Chopra action = ETH_FILTER_ACTION_ADD; 851cee4d264SManish Chopra break; 852cee4d264SManish Chopra case QED_FILTER_REMOVE: 853cee4d264SManish Chopra action = ETH_FILTER_ACTION_REMOVE; 854cee4d264SManish Chopra break; 855cee4d264SManish Chopra case QED_FILTER_FLUSH: 856fc48b7a6SYuval Mintz action = ETH_FILTER_ACTION_REMOVE_ALL; 857cee4d264SManish Chopra break; 858cee4d264SManish Chopra default: 859cee4d264SManish Chopra action = MAX_ETH_FILTER_ACTION; 860cee4d264SManish Chopra } 861cee4d264SManish Chopra 862cee4d264SManish Chopra return action; 863cee4d264SManish Chopra } 864cee4d264SManish Chopra 865cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb, 866cee4d264SManish Chopra __le16 *fw_mid, 867cee4d264SManish Chopra __le16 *fw_lsb, 868cee4d264SManish Chopra u8 *mac) 869cee4d264SManish Chopra { 870cee4d264SManish Chopra ((u8 *)fw_msb)[0] = mac[1]; 871cee4d264SManish Chopra ((u8 *)fw_msb)[1] = mac[0]; 872cee4d264SManish Chopra ((u8 *)fw_mid)[0] = mac[3]; 873cee4d264SManish Chopra ((u8 *)fw_mid)[1] = mac[2]; 874cee4d264SManish Chopra ((u8 *)fw_lsb)[0] = mac[5]; 875cee4d264SManish Chopra ((u8 *)fw_lsb)[1] = mac[4]; 876cee4d264SManish Chopra } 877cee4d264SManish Chopra 878cee4d264SManish Chopra static int 879cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 880cee4d264SManish Chopra u16 opaque_fid, 881cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 882cee4d264SManish Chopra struct vport_filter_update_ramrod_data **pp_ramrod, 883cee4d264SManish Chopra struct qed_spq_entry **pp_ent, 884cee4d264SManish Chopra enum spq_mode comp_mode, 885cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 886cee4d264SManish Chopra { 887cee4d264SManish Chopra u8 vport_to_add_to = 0, vport_to_remove_from = 0; 888cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod; 889cee4d264SManish Chopra struct eth_filter_cmd *p_first_filter; 890cee4d264SManish Chopra struct eth_filter_cmd *p_second_filter; 89106f56b81SYuval Mintz struct qed_sp_init_data init_data; 892cee4d264SManish Chopra enum eth_filter_action action; 893cee4d264SManish Chopra int rc; 894cee4d264SManish Chopra 895cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 896cee4d264SManish Chopra &vport_to_remove_from); 897cee4d264SManish Chopra if (rc) 898cee4d264SManish Chopra return rc; 899cee4d264SManish Chopra 900cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 901cee4d264SManish Chopra &vport_to_add_to); 902cee4d264SManish Chopra if (rc) 903cee4d264SManish Chopra return rc; 904cee4d264SManish Chopra 90506f56b81SYuval Mintz /* Get SPQ entry */ 90606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 90706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 90806f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 90906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 91006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 911cee4d264SManish Chopra 912cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, pp_ent, 913cee4d264SManish Chopra ETH_RAMROD_FILTERS_UPDATE, 91406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 915cee4d264SManish Chopra if (rc) 916cee4d264SManish Chopra return rc; 917cee4d264SManish Chopra 918cee4d264SManish Chopra *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 919cee4d264SManish Chopra p_ramrod = *pp_ramrod; 920cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 921cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 922cee4d264SManish Chopra 923cee4d264SManish Chopra switch (p_filter_cmd->opcode) { 924fc48b7a6SYuval Mintz case QED_FILTER_REPLACE: 925cee4d264SManish Chopra case QED_FILTER_MOVE: 926cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 927cee4d264SManish Chopra default: 928cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 929cee4d264SManish Chopra } 930cee4d264SManish Chopra 931cee4d264SManish Chopra p_first_filter = &p_ramrod->filter_cmds[0]; 932cee4d264SManish Chopra p_second_filter = &p_ramrod->filter_cmds[1]; 933cee4d264SManish Chopra 934cee4d264SManish Chopra switch (p_filter_cmd->type) { 935cee4d264SManish Chopra case QED_FILTER_MAC: 936cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 937cee4d264SManish Chopra case QED_FILTER_VLAN: 938cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 939cee4d264SManish Chopra case QED_FILTER_MAC_VLAN: 940cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 941cee4d264SManish Chopra case QED_FILTER_INNER_MAC: 942cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 943cee4d264SManish Chopra case QED_FILTER_INNER_VLAN: 944cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 945cee4d264SManish Chopra case QED_FILTER_INNER_PAIR: 946cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 947cee4d264SManish Chopra case QED_FILTER_INNER_MAC_VNI_PAIR: 948cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 949cee4d264SManish Chopra break; 950cee4d264SManish Chopra case QED_FILTER_MAC_VNI_PAIR: 951cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 952cee4d264SManish Chopra case QED_FILTER_VNI: 953cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 954cee4d264SManish Chopra } 955cee4d264SManish Chopra 956cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 957cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 958cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 959cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 960cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 961cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 962cee4d264SManish Chopra qed_set_fw_mac_addr(&p_first_filter->mac_msb, 963cee4d264SManish Chopra &p_first_filter->mac_mid, 964cee4d264SManish Chopra &p_first_filter->mac_lsb, 965cee4d264SManish Chopra (u8 *)p_filter_cmd->mac); 966cee4d264SManish Chopra } 967cee4d264SManish Chopra 968cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 969cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 970cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 971cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 972cee4d264SManish Chopra p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 973cee4d264SManish Chopra 974cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 975cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 976cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 977cee4d264SManish Chopra p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 978cee4d264SManish Chopra 979cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 980cee4d264SManish Chopra p_second_filter->type = p_first_filter->type; 981cee4d264SManish Chopra p_second_filter->mac_msb = p_first_filter->mac_msb; 982cee4d264SManish Chopra p_second_filter->mac_mid = p_first_filter->mac_mid; 983cee4d264SManish Chopra p_second_filter->mac_lsb = p_first_filter->mac_lsb; 984cee4d264SManish Chopra p_second_filter->vlan_id = p_first_filter->vlan_id; 985cee4d264SManish Chopra p_second_filter->vni = p_first_filter->vni; 986cee4d264SManish Chopra 987cee4d264SManish Chopra p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 988cee4d264SManish Chopra 989cee4d264SManish Chopra p_first_filter->vport_id = vport_to_remove_from; 990cee4d264SManish Chopra 991cee4d264SManish Chopra p_second_filter->action = ETH_FILTER_ACTION_ADD; 992cee4d264SManish Chopra p_second_filter->vport_id = vport_to_add_to; 993fc48b7a6SYuval Mintz } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 994fc48b7a6SYuval Mintz p_first_filter->vport_id = vport_to_add_to; 995fc48b7a6SYuval Mintz memcpy(p_second_filter, p_first_filter, 996fc48b7a6SYuval Mintz sizeof(*p_second_filter)); 997fc48b7a6SYuval Mintz p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 998fc48b7a6SYuval Mintz p_second_filter->action = ETH_FILTER_ACTION_ADD; 999cee4d264SManish Chopra } else { 1000cee4d264SManish Chopra action = qed_filter_action(p_filter_cmd->opcode); 1001cee4d264SManish Chopra 1002cee4d264SManish Chopra if (action == MAX_ETH_FILTER_ACTION) { 1003cee4d264SManish Chopra DP_NOTICE(p_hwfn, 1004cee4d264SManish Chopra "%d is not supported yet\n", 1005cee4d264SManish Chopra p_filter_cmd->opcode); 1006cee4d264SManish Chopra return -EINVAL; 1007cee4d264SManish Chopra } 1008cee4d264SManish Chopra 1009cee4d264SManish Chopra p_first_filter->action = action; 1010cee4d264SManish Chopra p_first_filter->vport_id = (p_filter_cmd->opcode == 1011cee4d264SManish Chopra QED_FILTER_REMOVE) ? 1012cee4d264SManish Chopra vport_to_remove_from : 1013cee4d264SManish Chopra vport_to_add_to; 1014cee4d264SManish Chopra } 1015cee4d264SManish Chopra 1016cee4d264SManish Chopra return 0; 1017cee4d264SManish Chopra } 1018cee4d264SManish Chopra 1019cee4d264SManish Chopra static int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 1020cee4d264SManish Chopra u16 opaque_fid, 1021cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1022cee4d264SManish Chopra enum spq_mode comp_mode, 1023cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1024cee4d264SManish Chopra { 1025cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod = NULL; 1026cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 1027cee4d264SManish Chopra struct eth_filter_cmd_header *p_header; 1028cee4d264SManish Chopra int rc; 1029cee4d264SManish Chopra 1030cee4d264SManish Chopra rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1031cee4d264SManish Chopra &p_ramrod, &p_ent, 1032cee4d264SManish Chopra comp_mode, p_comp_data); 1033cee4d264SManish Chopra if (rc != 0) { 1034cee4d264SManish Chopra DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1035cee4d264SManish Chopra return rc; 1036cee4d264SManish Chopra } 1037cee4d264SManish Chopra p_header = &p_ramrod->filter_cmd_hdr; 1038cee4d264SManish Chopra p_header->assert_on_error = p_filter_cmd->assert_on_error; 1039cee4d264SManish Chopra 1040cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 1041cee4d264SManish Chopra if (rc != 0) { 1042cee4d264SManish Chopra DP_ERR(p_hwfn, 1043cee4d264SManish Chopra "Unicast filter ADD command failed %d\n", 1044cee4d264SManish Chopra rc); 1045cee4d264SManish Chopra return rc; 1046cee4d264SManish Chopra } 1047cee4d264SManish Chopra 1048cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1049cee4d264SManish Chopra "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1050cee4d264SManish Chopra (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1051cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1052cee4d264SManish Chopra "REMOVE" : 1053cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1054cee4d264SManish Chopra "MOVE" : "REPLACE")), 1055cee4d264SManish Chopra (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1056cee4d264SManish Chopra ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1057cee4d264SManish Chopra "VLAN" : "MAC & VLAN"), 1058cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt, 1059cee4d264SManish Chopra p_filter_cmd->is_rx_filter, 1060cee4d264SManish Chopra p_filter_cmd->is_tx_filter); 1061cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1062cee4d264SManish Chopra "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1063cee4d264SManish Chopra p_filter_cmd->vport_to_add_to, 1064cee4d264SManish Chopra p_filter_cmd->vport_to_remove_from, 1065cee4d264SManish Chopra p_filter_cmd->mac[0], 1066cee4d264SManish Chopra p_filter_cmd->mac[1], 1067cee4d264SManish Chopra p_filter_cmd->mac[2], 1068cee4d264SManish Chopra p_filter_cmd->mac[3], 1069cee4d264SManish Chopra p_filter_cmd->mac[4], 1070cee4d264SManish Chopra p_filter_cmd->mac[5], 1071cee4d264SManish Chopra p_filter_cmd->vlan); 1072cee4d264SManish Chopra 1073cee4d264SManish Chopra return 0; 1074cee4d264SManish Chopra } 1075cee4d264SManish Chopra 1076cee4d264SManish Chopra /******************************************************************************* 1077cee4d264SManish Chopra * Description: 1078cee4d264SManish Chopra * Calculates crc 32 on a buffer 1079cee4d264SManish Chopra * Note: crc32_length MUST be aligned to 8 1080cee4d264SManish Chopra * Return: 1081cee4d264SManish Chopra ******************************************************************************/ 1082cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet, 1083cee4d264SManish Chopra u32 crc32_length, 1084cee4d264SManish Chopra u32 crc32_seed, 1085cee4d264SManish Chopra u8 complement) 1086cee4d264SManish Chopra { 1087cee4d264SManish Chopra u32 byte = 0; 1088cee4d264SManish Chopra u32 bit = 0; 1089cee4d264SManish Chopra u8 msb = 0; 1090cee4d264SManish Chopra u8 current_byte = 0; 1091cee4d264SManish Chopra u32 crc32_result = crc32_seed; 1092cee4d264SManish Chopra 1093cee4d264SManish Chopra if ((!crc32_packet) || 1094cee4d264SManish Chopra (crc32_length == 0) || 1095cee4d264SManish Chopra ((crc32_length % 8) != 0)) 1096cee4d264SManish Chopra return crc32_result; 1097cee4d264SManish Chopra for (byte = 0; byte < crc32_length; byte++) { 1098cee4d264SManish Chopra current_byte = crc32_packet[byte]; 1099cee4d264SManish Chopra for (bit = 0; bit < 8; bit++) { 1100cee4d264SManish Chopra msb = (u8)(crc32_result >> 31); 1101cee4d264SManish Chopra crc32_result = crc32_result << 1; 1102cee4d264SManish Chopra if (msb != (0x1 & (current_byte >> bit))) { 1103cee4d264SManish Chopra crc32_result = crc32_result ^ CRC32_POLY; 1104cee4d264SManish Chopra crc32_result |= 1; /*crc32_result[0] = 1;*/ 1105cee4d264SManish Chopra } 1106cee4d264SManish Chopra } 1107cee4d264SManish Chopra } 1108cee4d264SManish Chopra return crc32_result; 1109cee4d264SManish Chopra } 1110cee4d264SManish Chopra 1111cee4d264SManish Chopra static inline u32 qed_crc32c_le(u32 seed, 1112cee4d264SManish Chopra u8 *mac, 1113cee4d264SManish Chopra u32 len) 1114cee4d264SManish Chopra { 1115cee4d264SManish Chopra u32 packet_buf[2] = { 0 }; 1116cee4d264SManish Chopra 1117cee4d264SManish Chopra memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1118cee4d264SManish Chopra return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1119cee4d264SManish Chopra } 1120cee4d264SManish Chopra 1121cee4d264SManish Chopra static u8 qed_mcast_bin_from_mac(u8 *mac) 1122cee4d264SManish Chopra { 1123cee4d264SManish Chopra u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1124cee4d264SManish Chopra mac, ETH_ALEN); 1125cee4d264SManish Chopra 1126cee4d264SManish Chopra return crc & 0xff; 1127cee4d264SManish Chopra } 1128cee4d264SManish Chopra 1129cee4d264SManish Chopra static int 1130cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1131cee4d264SManish Chopra u16 opaque_fid, 1132cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1133cee4d264SManish Chopra enum spq_mode comp_mode, 1134cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1135cee4d264SManish Chopra { 1136cee4d264SManish Chopra unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1137cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 1138cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 113906f56b81SYuval Mintz struct qed_sp_init_data init_data; 1140cee4d264SManish Chopra u8 abs_vport_id = 0; 1141cee4d264SManish Chopra int rc, i; 1142cee4d264SManish Chopra 1143cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1144cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1145cee4d264SManish Chopra &abs_vport_id); 1146cee4d264SManish Chopra if (rc) 1147cee4d264SManish Chopra return rc; 1148cee4d264SManish Chopra } else { 1149cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1150cee4d264SManish Chopra &abs_vport_id); 1151cee4d264SManish Chopra if (rc) 1152cee4d264SManish Chopra return rc; 1153cee4d264SManish Chopra } 1154cee4d264SManish Chopra 115506f56b81SYuval Mintz /* Get SPQ entry */ 115606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 115706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 115806f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 115906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 116006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1161cee4d264SManish Chopra 1162cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1163cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 116406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1165cee4d264SManish Chopra if (rc) { 1166cee4d264SManish Chopra DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1167cee4d264SManish Chopra return rc; 1168cee4d264SManish Chopra } 1169cee4d264SManish Chopra 1170cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 1171cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 1172cee4d264SManish Chopra 1173cee4d264SManish Chopra /* explicitly clear out the entire vector */ 1174cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 1175cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 1176cee4d264SManish Chopra memset(bins, 0, sizeof(unsigned long) * 1177cee4d264SManish Chopra ETH_MULTICAST_MAC_BINS_IN_REGS); 1178cee4d264SManish Chopra /* filter ADD op is explicit set op and it removes 1179cee4d264SManish Chopra * any existing filters for the vport 1180cee4d264SManish Chopra */ 1181cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1182cee4d264SManish Chopra for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 1183cee4d264SManish Chopra u32 bit; 1184cee4d264SManish Chopra 1185cee4d264SManish Chopra bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 1186cee4d264SManish Chopra __set_bit(bit, bins); 1187cee4d264SManish Chopra } 1188cee4d264SManish Chopra 1189cee4d264SManish Chopra /* Convert to correct endianity */ 1190cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 1191cee4d264SManish Chopra u32 *p_bins = (u32 *)bins; 1192cee4d264SManish Chopra struct vport_update_ramrod_mcast *approx_mcast; 1193cee4d264SManish Chopra 1194cee4d264SManish Chopra approx_mcast = &p_ramrod->approx_mcast; 1195cee4d264SManish Chopra approx_mcast->bins[i] = cpu_to_le32(p_bins[i]); 1196cee4d264SManish Chopra } 1197cee4d264SManish Chopra } 1198cee4d264SManish Chopra 1199cee4d264SManish Chopra p_ramrod->common.vport_id = abs_vport_id; 1200cee4d264SManish Chopra 1201cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1202cee4d264SManish Chopra } 1203cee4d264SManish Chopra 1204cee4d264SManish Chopra static int 1205cee4d264SManish Chopra qed_filter_mcast_cmd(struct qed_dev *cdev, 1206cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1207cee4d264SManish Chopra enum spq_mode comp_mode, 1208cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1209cee4d264SManish Chopra { 1210cee4d264SManish Chopra int rc = 0; 1211cee4d264SManish Chopra int i; 1212cee4d264SManish Chopra 1213cee4d264SManish Chopra /* only ADD and REMOVE operations are supported for multi-cast */ 1214cee4d264SManish Chopra if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1215cee4d264SManish Chopra (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1216cee4d264SManish Chopra (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1217cee4d264SManish Chopra return -EINVAL; 1218cee4d264SManish Chopra 1219cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1220cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1221cee4d264SManish Chopra 1222cee4d264SManish Chopra u16 opaque_fid; 1223cee4d264SManish Chopra 1224cee4d264SManish Chopra if (rc != 0) 1225cee4d264SManish Chopra break; 1226cee4d264SManish Chopra 1227cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1228cee4d264SManish Chopra 1229cee4d264SManish Chopra rc = qed_sp_eth_filter_mcast(p_hwfn, 1230cee4d264SManish Chopra opaque_fid, 1231cee4d264SManish Chopra p_filter_cmd, 1232cee4d264SManish Chopra comp_mode, 1233cee4d264SManish Chopra p_comp_data); 1234cee4d264SManish Chopra } 1235cee4d264SManish Chopra return rc; 1236cee4d264SManish Chopra } 1237cee4d264SManish Chopra 1238cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1239cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1240cee4d264SManish Chopra enum spq_mode comp_mode, 1241cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1242cee4d264SManish Chopra { 1243cee4d264SManish Chopra int rc = 0; 1244cee4d264SManish Chopra int i; 1245cee4d264SManish Chopra 1246cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1247cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1248cee4d264SManish Chopra u16 opaque_fid; 1249cee4d264SManish Chopra 1250cee4d264SManish Chopra if (rc != 0) 1251cee4d264SManish Chopra break; 1252cee4d264SManish Chopra 1253cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1254cee4d264SManish Chopra 1255cee4d264SManish Chopra rc = qed_sp_eth_filter_ucast(p_hwfn, 1256cee4d264SManish Chopra opaque_fid, 1257cee4d264SManish Chopra p_filter_cmd, 1258cee4d264SManish Chopra comp_mode, 1259cee4d264SManish Chopra p_comp_data); 1260cee4d264SManish Chopra } 1261cee4d264SManish Chopra 1262cee4d264SManish Chopra return rc; 1263cee4d264SManish Chopra } 1264cee4d264SManish Chopra 126586622ee7SYuval Mintz /* Statistics related code */ 126686622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 126786622ee7SYuval Mintz u32 *p_addr, 126886622ee7SYuval Mintz u32 *p_len, 126986622ee7SYuval Mintz u16 statistics_bin) 127086622ee7SYuval Mintz { 127186622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_PSDM_RAM + 127286622ee7SYuval Mintz PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 127386622ee7SYuval Mintz *p_len = sizeof(struct eth_pstorm_per_queue_stat); 127486622ee7SYuval Mintz } 127586622ee7SYuval Mintz 127686622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 127786622ee7SYuval Mintz struct qed_ptt *p_ptt, 127886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 127986622ee7SYuval Mintz u16 statistics_bin) 128086622ee7SYuval Mintz { 128186622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 128286622ee7SYuval Mintz u32 pstats_addr = 0, pstats_len = 0; 128386622ee7SYuval Mintz 128486622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 128586622ee7SYuval Mintz statistics_bin); 128686622ee7SYuval Mintz 128786622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 128886622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &pstats, 128986622ee7SYuval Mintz pstats_addr, pstats_len); 129086622ee7SYuval Mintz 129186622ee7SYuval Mintz p_stats->tx_ucast_bytes += 129286622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_ucast_bytes); 129386622ee7SYuval Mintz p_stats->tx_mcast_bytes += 129486622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_mcast_bytes); 129586622ee7SYuval Mintz p_stats->tx_bcast_bytes += 129686622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_bcast_bytes); 129786622ee7SYuval Mintz p_stats->tx_ucast_pkts += 129886622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_ucast_pkts); 129986622ee7SYuval Mintz p_stats->tx_mcast_pkts += 130086622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_mcast_pkts); 130186622ee7SYuval Mintz p_stats->tx_bcast_pkts += 130286622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_bcast_pkts); 130386622ee7SYuval Mintz p_stats->tx_err_drop_pkts += 130486622ee7SYuval Mintz HILO_64_REGPAIR(pstats.error_drop_pkts); 130586622ee7SYuval Mintz } 130686622ee7SYuval Mintz 130786622ee7SYuval Mintz static void __qed_get_vport_tstats_addrlen(struct qed_hwfn *p_hwfn, 130886622ee7SYuval Mintz u32 *p_addr, 130986622ee7SYuval Mintz u32 *p_len) 131086622ee7SYuval Mintz { 131186622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_TSDM_RAM + 131286622ee7SYuval Mintz TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 131386622ee7SYuval Mintz *p_len = sizeof(struct tstorm_per_port_stat); 131486622ee7SYuval Mintz } 131586622ee7SYuval Mintz 131686622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 131786622ee7SYuval Mintz struct qed_ptt *p_ptt, 131886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 131986622ee7SYuval Mintz u16 statistics_bin) 132086622ee7SYuval Mintz { 132186622ee7SYuval Mintz u32 tstats_addr = 0, tstats_len = 0; 132286622ee7SYuval Mintz struct tstorm_per_port_stat tstats; 132386622ee7SYuval Mintz 132486622ee7SYuval Mintz __qed_get_vport_tstats_addrlen(p_hwfn, &tstats_addr, &tstats_len); 132586622ee7SYuval Mintz 132686622ee7SYuval Mintz memset(&tstats, 0, sizeof(tstats)); 132786622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &tstats, 132886622ee7SYuval Mintz tstats_addr, tstats_len); 132986622ee7SYuval Mintz 133086622ee7SYuval Mintz p_stats->mftag_filter_discards += 133186622ee7SYuval Mintz HILO_64_REGPAIR(tstats.mftag_filter_discard); 133286622ee7SYuval Mintz p_stats->mac_filter_discards += 133386622ee7SYuval Mintz HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 133486622ee7SYuval Mintz } 133586622ee7SYuval Mintz 133686622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 133786622ee7SYuval Mintz u32 *p_addr, 133886622ee7SYuval Mintz u32 *p_len, 133986622ee7SYuval Mintz u16 statistics_bin) 134086622ee7SYuval Mintz { 134186622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_USDM_RAM + 134286622ee7SYuval Mintz USTORM_QUEUE_STAT_OFFSET(statistics_bin); 134386622ee7SYuval Mintz *p_len = sizeof(struct eth_ustorm_per_queue_stat); 134486622ee7SYuval Mintz } 134586622ee7SYuval Mintz 134686622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 134786622ee7SYuval Mintz struct qed_ptt *p_ptt, 134886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 134986622ee7SYuval Mintz u16 statistics_bin) 135086622ee7SYuval Mintz { 135186622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 135286622ee7SYuval Mintz u32 ustats_addr = 0, ustats_len = 0; 135386622ee7SYuval Mintz 135486622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 135586622ee7SYuval Mintz statistics_bin); 135686622ee7SYuval Mintz 135786622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 135886622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &ustats, 135986622ee7SYuval Mintz ustats_addr, ustats_len); 136086622ee7SYuval Mintz 136186622ee7SYuval Mintz p_stats->rx_ucast_bytes += 136286622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 136386622ee7SYuval Mintz p_stats->rx_mcast_bytes += 136486622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 136586622ee7SYuval Mintz p_stats->rx_bcast_bytes += 136686622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 136786622ee7SYuval Mintz p_stats->rx_ucast_pkts += 136886622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 136986622ee7SYuval Mintz p_stats->rx_mcast_pkts += 137086622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 137186622ee7SYuval Mintz p_stats->rx_bcast_pkts += 137286622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 137386622ee7SYuval Mintz } 137486622ee7SYuval Mintz 137586622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 137686622ee7SYuval Mintz u32 *p_addr, 137786622ee7SYuval Mintz u32 *p_len, 137886622ee7SYuval Mintz u16 statistics_bin) 137986622ee7SYuval Mintz { 138086622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_MSDM_RAM + 138186622ee7SYuval Mintz MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 138286622ee7SYuval Mintz *p_len = sizeof(struct eth_mstorm_per_queue_stat); 138386622ee7SYuval Mintz } 138486622ee7SYuval Mintz 138586622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 138686622ee7SYuval Mintz struct qed_ptt *p_ptt, 138786622ee7SYuval Mintz struct qed_eth_stats *p_stats, 138886622ee7SYuval Mintz u16 statistics_bin) 138986622ee7SYuval Mintz { 139086622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 139186622ee7SYuval Mintz u32 mstats_addr = 0, mstats_len = 0; 139286622ee7SYuval Mintz 139386622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 139486622ee7SYuval Mintz statistics_bin); 139586622ee7SYuval Mintz 139686622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 139786622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &mstats, 139886622ee7SYuval Mintz mstats_addr, mstats_len); 139986622ee7SYuval Mintz 140086622ee7SYuval Mintz p_stats->no_buff_discards += 140186622ee7SYuval Mintz HILO_64_REGPAIR(mstats.no_buff_discard); 140286622ee7SYuval Mintz p_stats->packet_too_big_discard += 140386622ee7SYuval Mintz HILO_64_REGPAIR(mstats.packet_too_big_discard); 140486622ee7SYuval Mintz p_stats->ttl0_discard += 140586622ee7SYuval Mintz HILO_64_REGPAIR(mstats.ttl0_discard); 140686622ee7SYuval Mintz p_stats->tpa_coalesced_pkts += 140786622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 140886622ee7SYuval Mintz p_stats->tpa_coalesced_events += 140986622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_events); 141086622ee7SYuval Mintz p_stats->tpa_aborts_num += 141186622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_aborts_num); 141286622ee7SYuval Mintz p_stats->tpa_coalesced_bytes += 141386622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 141486622ee7SYuval Mintz } 141586622ee7SYuval Mintz 141686622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 141786622ee7SYuval Mintz struct qed_ptt *p_ptt, 141886622ee7SYuval Mintz struct qed_eth_stats *p_stats) 141986622ee7SYuval Mintz { 142086622ee7SYuval Mintz struct port_stats port_stats; 142186622ee7SYuval Mintz int j; 142286622ee7SYuval Mintz 142386622ee7SYuval Mintz memset(&port_stats, 0, sizeof(port_stats)); 142486622ee7SYuval Mintz 142586622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 142686622ee7SYuval Mintz p_hwfn->mcp_info->port_addr + 142786622ee7SYuval Mintz offsetof(struct public_port, stats), 142886622ee7SYuval Mintz sizeof(port_stats)); 142986622ee7SYuval Mintz 143086622ee7SYuval Mintz p_stats->rx_64_byte_packets += port_stats.pmm.r64; 143186622ee7SYuval Mintz p_stats->rx_127_byte_packets += port_stats.pmm.r127; 143286622ee7SYuval Mintz p_stats->rx_255_byte_packets += port_stats.pmm.r255; 143386622ee7SYuval Mintz p_stats->rx_511_byte_packets += port_stats.pmm.r511; 143486622ee7SYuval Mintz p_stats->rx_1023_byte_packets += port_stats.pmm.r1023; 143586622ee7SYuval Mintz p_stats->rx_1518_byte_packets += port_stats.pmm.r1518; 143686622ee7SYuval Mintz p_stats->rx_1522_byte_packets += port_stats.pmm.r1522; 143786622ee7SYuval Mintz p_stats->rx_2047_byte_packets += port_stats.pmm.r2047; 143886622ee7SYuval Mintz p_stats->rx_4095_byte_packets += port_stats.pmm.r4095; 143986622ee7SYuval Mintz p_stats->rx_9216_byte_packets += port_stats.pmm.r9216; 144086622ee7SYuval Mintz p_stats->rx_16383_byte_packets += port_stats.pmm.r16383; 144186622ee7SYuval Mintz p_stats->rx_crc_errors += port_stats.pmm.rfcs; 144286622ee7SYuval Mintz p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf; 144386622ee7SYuval Mintz p_stats->rx_pause_frames += port_stats.pmm.rxpf; 144486622ee7SYuval Mintz p_stats->rx_pfc_frames += port_stats.pmm.rxpp; 144586622ee7SYuval Mintz p_stats->rx_align_errors += port_stats.pmm.raln; 144686622ee7SYuval Mintz p_stats->rx_carrier_errors += port_stats.pmm.rfcr; 144786622ee7SYuval Mintz p_stats->rx_oversize_packets += port_stats.pmm.rovr; 144886622ee7SYuval Mintz p_stats->rx_jabbers += port_stats.pmm.rjbr; 144986622ee7SYuval Mintz p_stats->rx_undersize_packets += port_stats.pmm.rund; 145086622ee7SYuval Mintz p_stats->rx_fragments += port_stats.pmm.rfrg; 145186622ee7SYuval Mintz p_stats->tx_64_byte_packets += port_stats.pmm.t64; 145286622ee7SYuval Mintz p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127; 145386622ee7SYuval Mintz p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255; 145486622ee7SYuval Mintz p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511; 145586622ee7SYuval Mintz p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023; 145686622ee7SYuval Mintz p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518; 145786622ee7SYuval Mintz p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047; 145886622ee7SYuval Mintz p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095; 145986622ee7SYuval Mintz p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216; 146086622ee7SYuval Mintz p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383; 146186622ee7SYuval Mintz p_stats->tx_pause_frames += port_stats.pmm.txpf; 146286622ee7SYuval Mintz p_stats->tx_pfc_frames += port_stats.pmm.txpp; 146386622ee7SYuval Mintz p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec; 146486622ee7SYuval Mintz p_stats->tx_total_collisions += port_stats.pmm.tncl; 146586622ee7SYuval Mintz p_stats->rx_mac_bytes += port_stats.pmm.rbyte; 146686622ee7SYuval Mintz p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca; 146786622ee7SYuval Mintz p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca; 146886622ee7SYuval Mintz p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca; 146986622ee7SYuval Mintz p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok; 147086622ee7SYuval Mintz p_stats->tx_mac_bytes += port_stats.pmm.tbyte; 147186622ee7SYuval Mintz p_stats->tx_mac_uc_packets += port_stats.pmm.txuca; 147286622ee7SYuval Mintz p_stats->tx_mac_mc_packets += port_stats.pmm.txmca; 147386622ee7SYuval Mintz p_stats->tx_mac_bc_packets += port_stats.pmm.txbca; 147486622ee7SYuval Mintz p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf; 147586622ee7SYuval Mintz for (j = 0; j < 8; j++) { 147686622ee7SYuval Mintz p_stats->brb_truncates += port_stats.brb.brb_truncate[j]; 147786622ee7SYuval Mintz p_stats->brb_discards += port_stats.brb.brb_discard[j]; 147886622ee7SYuval Mintz } 147986622ee7SYuval Mintz } 148086622ee7SYuval Mintz 148186622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 148286622ee7SYuval Mintz struct qed_ptt *p_ptt, 148386622ee7SYuval Mintz struct qed_eth_stats *stats, 148486622ee7SYuval Mintz u16 statistics_bin) 148586622ee7SYuval Mintz { 148686622ee7SYuval Mintz __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 148786622ee7SYuval Mintz __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 148886622ee7SYuval Mintz __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 148986622ee7SYuval Mintz __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 149086622ee7SYuval Mintz 149186622ee7SYuval Mintz if (p_hwfn->mcp_info) 149286622ee7SYuval Mintz __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 149386622ee7SYuval Mintz } 149486622ee7SYuval Mintz 149586622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev, 149686622ee7SYuval Mintz struct qed_eth_stats *stats) 149786622ee7SYuval Mintz { 149886622ee7SYuval Mintz u8 fw_vport = 0; 149986622ee7SYuval Mintz int i; 150086622ee7SYuval Mintz 150186622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 150286622ee7SYuval Mintz 150386622ee7SYuval Mintz for_each_hwfn(cdev, i) { 150486622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 150586622ee7SYuval Mintz struct qed_ptt *p_ptt; 150686622ee7SYuval Mintz 150786622ee7SYuval Mintz /* The main vport index is relative first */ 150886622ee7SYuval Mintz if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 150986622ee7SYuval Mintz DP_ERR(p_hwfn, "No vport available!\n"); 151086622ee7SYuval Mintz continue; 151186622ee7SYuval Mintz } 151286622ee7SYuval Mintz 151386622ee7SYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 151486622ee7SYuval Mintz if (!p_ptt) { 151586622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 151686622ee7SYuval Mintz continue; 151786622ee7SYuval Mintz } 151886622ee7SYuval Mintz 151986622ee7SYuval Mintz __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport); 152086622ee7SYuval Mintz 152186622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 152286622ee7SYuval Mintz } 152386622ee7SYuval Mintz } 152486622ee7SYuval Mintz 152586622ee7SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, 152686622ee7SYuval Mintz struct qed_eth_stats *stats) 152786622ee7SYuval Mintz { 152886622ee7SYuval Mintz u32 i; 152986622ee7SYuval Mintz 153086622ee7SYuval Mintz if (!cdev) { 153186622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 153286622ee7SYuval Mintz return; 153386622ee7SYuval Mintz } 153486622ee7SYuval Mintz 153586622ee7SYuval Mintz _qed_get_vport_stats(cdev, stats); 153686622ee7SYuval Mintz 153786622ee7SYuval Mintz if (!cdev->reset_stats) 153886622ee7SYuval Mintz return; 153986622ee7SYuval Mintz 154086622ee7SYuval Mintz /* Reduce the statistics baseline */ 154186622ee7SYuval Mintz for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 154286622ee7SYuval Mintz ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 154386622ee7SYuval Mintz } 154486622ee7SYuval Mintz 154586622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 154686622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev) 154786622ee7SYuval Mintz { 154886622ee7SYuval Mintz int i; 154986622ee7SYuval Mintz 155086622ee7SYuval Mintz for_each_hwfn(cdev, i) { 155186622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 155286622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 155386622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 155486622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 155586622ee7SYuval Mintz struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 155686622ee7SYuval Mintz u32 addr = 0, len = 0; 155786622ee7SYuval Mintz 155886622ee7SYuval Mintz if (!p_ptt) { 155986622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 156086622ee7SYuval Mintz continue; 156186622ee7SYuval Mintz } 156286622ee7SYuval Mintz 156386622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 156486622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 156586622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 156686622ee7SYuval Mintz 156786622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 156886622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 156986622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 157086622ee7SYuval Mintz 157186622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 157286622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 157386622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 157486622ee7SYuval Mintz 157586622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 157686622ee7SYuval Mintz } 157786622ee7SYuval Mintz 157886622ee7SYuval Mintz /* PORT statistics are not necessarily reset, so we need to 157986622ee7SYuval Mintz * read and create a baseline for future statistics. 158086622ee7SYuval Mintz */ 158186622ee7SYuval Mintz if (!cdev->reset_stats) 158286622ee7SYuval Mintz DP_INFO(cdev, "Reset stats not allocated\n"); 158386622ee7SYuval Mintz else 158486622ee7SYuval Mintz _qed_get_vport_stats(cdev, cdev->reset_stats); 158586622ee7SYuval Mintz } 158686622ee7SYuval Mintz 158725c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev, 158825c089d7SYuval Mintz struct qed_dev_eth_info *info) 158925c089d7SYuval Mintz { 159025c089d7SYuval Mintz int i; 159125c089d7SYuval Mintz 159225c089d7SYuval Mintz memset(info, 0, sizeof(*info)); 159325c089d7SYuval Mintz 159425c089d7SYuval Mintz info->num_tc = 1; 159525c089d7SYuval Mintz 159625c089d7SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 159725c089d7SYuval Mintz for_each_hwfn(cdev, i) 159825c089d7SYuval Mintz info->num_queues += FEAT_NUM(&cdev->hwfns[i], 159925c089d7SYuval Mintz QED_PF_L2_QUE); 160025c089d7SYuval Mintz if (cdev->int_params.fp_msix_cnt) 160125c089d7SYuval Mintz info->num_queues = min_t(u8, info->num_queues, 160225c089d7SYuval Mintz cdev->int_params.fp_msix_cnt); 160325c089d7SYuval Mintz } else { 160425c089d7SYuval Mintz info->num_queues = cdev->num_hwfns; 160525c089d7SYuval Mintz } 160625c089d7SYuval Mintz 160725c089d7SYuval Mintz info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN); 160825c089d7SYuval Mintz ether_addr_copy(info->port_mac, 160925c089d7SYuval Mintz cdev->hwfns[0].hw_info.hw_mac_addr); 161025c089d7SYuval Mintz 161125c089d7SYuval Mintz qed_fill_dev_info(cdev, &info->common); 161225c089d7SYuval Mintz 161325c089d7SYuval Mintz return 0; 161425c089d7SYuval Mintz } 161525c089d7SYuval Mintz 1616cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev, 1617cc875c2eSYuval Mintz struct qed_eth_cb_ops *ops, 1618cc875c2eSYuval Mintz void *cookie) 1619cc875c2eSYuval Mintz { 1620cc875c2eSYuval Mintz cdev->protocol_ops.eth = ops; 1621cc875c2eSYuval Mintz cdev->ops_cookie = cookie; 1622cc875c2eSYuval Mintz } 1623cc875c2eSYuval Mintz 1624cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev, 1625088c8618SManish Chopra struct qed_start_vport_params *params) 1626cee4d264SManish Chopra { 1627cee4d264SManish Chopra int rc, i; 1628cee4d264SManish Chopra 1629cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1630088c8618SManish Chopra struct qed_sp_vport_start_params start = { 0 }; 1631cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1632cee4d264SManish Chopra 1633088c8618SManish Chopra start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : 1634088c8618SManish Chopra QED_TPA_MODE_NONE; 1635088c8618SManish Chopra start.remove_inner_vlan = params->remove_inner_vlan; 1636088c8618SManish Chopra start.drop_ttl0 = params->drop_ttl0; 1637088c8618SManish Chopra start.opaque_fid = p_hwfn->hw_info.opaque_fid; 1638088c8618SManish Chopra start.concrete_fid = p_hwfn->hw_info.concrete_fid; 1639088c8618SManish Chopra start.vport_id = params->vport_id; 1640088c8618SManish Chopra start.max_buffers_per_cqe = 16; 1641088c8618SManish Chopra start.mtu = params->mtu; 1642cee4d264SManish Chopra 1643088c8618SManish Chopra rc = qed_sp_vport_start(p_hwfn, &start); 1644cee4d264SManish Chopra if (rc) { 1645cee4d264SManish Chopra DP_ERR(cdev, "Failed to start VPORT\n"); 1646cee4d264SManish Chopra return rc; 1647cee4d264SManish Chopra } 1648cee4d264SManish Chopra 1649cee4d264SManish Chopra qed_hw_start_fastpath(p_hwfn); 1650cee4d264SManish Chopra 1651cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1652cee4d264SManish Chopra "Started V-PORT %d with MTU %d\n", 1653088c8618SManish Chopra start.vport_id, start.mtu); 1654cee4d264SManish Chopra } 1655cee4d264SManish Chopra 16569df2ed04SManish Chopra qed_reset_vport_stats(cdev); 16579df2ed04SManish Chopra 1658cee4d264SManish Chopra return 0; 1659cee4d264SManish Chopra } 1660cee4d264SManish Chopra 1661cee4d264SManish Chopra static int qed_stop_vport(struct qed_dev *cdev, 1662cee4d264SManish Chopra u8 vport_id) 1663cee4d264SManish Chopra { 1664cee4d264SManish Chopra int rc, i; 1665cee4d264SManish Chopra 1666cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1667cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1668cee4d264SManish Chopra 1669cee4d264SManish Chopra rc = qed_sp_vport_stop(p_hwfn, 1670cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 1671cee4d264SManish Chopra vport_id); 1672cee4d264SManish Chopra 1673cee4d264SManish Chopra if (rc) { 1674cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop VPORT\n"); 1675cee4d264SManish Chopra return rc; 1676cee4d264SManish Chopra } 1677cee4d264SManish Chopra } 1678cee4d264SManish Chopra return 0; 1679cee4d264SManish Chopra } 1680cee4d264SManish Chopra 1681cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev, 1682cee4d264SManish Chopra struct qed_update_vport_params *params) 1683cee4d264SManish Chopra { 1684cee4d264SManish Chopra struct qed_sp_vport_update_params sp_params; 1685cee4d264SManish Chopra struct qed_rss_params sp_rss_params; 1686cee4d264SManish Chopra int rc, i; 1687cee4d264SManish Chopra 1688cee4d264SManish Chopra if (!cdev) 1689cee4d264SManish Chopra return -ENODEV; 1690cee4d264SManish Chopra 1691cee4d264SManish Chopra memset(&sp_params, 0, sizeof(sp_params)); 1692cee4d264SManish Chopra memset(&sp_rss_params, 0, sizeof(sp_rss_params)); 1693cee4d264SManish Chopra 1694cee4d264SManish Chopra /* Translate protocol params into sp params */ 1695cee4d264SManish Chopra sp_params.vport_id = params->vport_id; 1696cee4d264SManish Chopra sp_params.update_vport_active_rx_flg = 1697cee4d264SManish Chopra params->update_vport_active_flg; 1698cee4d264SManish Chopra sp_params.update_vport_active_tx_flg = 1699cee4d264SManish Chopra params->update_vport_active_flg; 1700cee4d264SManish Chopra sp_params.vport_active_rx_flg = params->vport_active_flg; 1701cee4d264SManish Chopra sp_params.vport_active_tx_flg = params->vport_active_flg; 17023f9b4a69SYuval Mintz sp_params.accept_any_vlan = params->accept_any_vlan; 17033f9b4a69SYuval Mintz sp_params.update_accept_any_vlan_flg = 17043f9b4a69SYuval Mintz params->update_accept_any_vlan_flg; 1705cee4d264SManish Chopra 1706cee4d264SManish Chopra /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns. 1707cee4d264SManish Chopra * We need to re-fix the rss values per engine for CMT. 1708cee4d264SManish Chopra */ 1709cee4d264SManish Chopra if (cdev->num_hwfns > 1 && params->update_rss_flg) { 1710cee4d264SManish Chopra struct qed_update_vport_rss_params *rss = 1711cee4d264SManish Chopra ¶ms->rss_params; 1712cee4d264SManish Chopra int k, max = 0; 1713cee4d264SManish Chopra 1714cee4d264SManish Chopra /* Find largest entry, since it's possible RSS needs to 1715cee4d264SManish Chopra * be disabled [in case only 1 queue per-hwfn] 1716cee4d264SManish Chopra */ 1717cee4d264SManish Chopra for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1718cee4d264SManish Chopra max = (max > rss->rss_ind_table[k]) ? 1719cee4d264SManish Chopra max : rss->rss_ind_table[k]; 1720cee4d264SManish Chopra 1721cee4d264SManish Chopra /* Either fix RSS values or disable RSS */ 1722cee4d264SManish Chopra if (cdev->num_hwfns < max + 1) { 1723cee4d264SManish Chopra int divisor = (max + cdev->num_hwfns - 1) / 1724cee4d264SManish Chopra cdev->num_hwfns; 1725cee4d264SManish Chopra 1726cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1727cee4d264SManish Chopra "CMT - fixing RSS values (modulo %02x)\n", 1728cee4d264SManish Chopra divisor); 1729cee4d264SManish Chopra 1730cee4d264SManish Chopra for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1731cee4d264SManish Chopra rss->rss_ind_table[k] = 1732cee4d264SManish Chopra rss->rss_ind_table[k] % divisor; 1733cee4d264SManish Chopra } else { 1734cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1735cee4d264SManish Chopra "CMT - 1 queue per-hwfn; Disabling RSS\n"); 1736cee4d264SManish Chopra params->update_rss_flg = 0; 1737cee4d264SManish Chopra } 1738cee4d264SManish Chopra } 1739cee4d264SManish Chopra 1740cee4d264SManish Chopra /* Now, update the RSS configuration for actual configuration */ 1741cee4d264SManish Chopra if (params->update_rss_flg) { 1742cee4d264SManish Chopra sp_rss_params.update_rss_config = 1; 1743cee4d264SManish Chopra sp_rss_params.rss_enable = 1; 1744cee4d264SManish Chopra sp_rss_params.update_rss_capabilities = 1; 1745cee4d264SManish Chopra sp_rss_params.update_rss_ind_table = 1; 1746cee4d264SManish Chopra sp_rss_params.update_rss_key = 1; 1747cee4d264SManish Chopra sp_rss_params.rss_caps = QED_RSS_IPV4 | 1748cee4d264SManish Chopra QED_RSS_IPV6 | 1749cee4d264SManish Chopra QED_RSS_IPV4_TCP | QED_RSS_IPV6_TCP; 1750cee4d264SManish Chopra sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */ 1751cee4d264SManish Chopra memcpy(sp_rss_params.rss_ind_table, 1752cee4d264SManish Chopra params->rss_params.rss_ind_table, 1753cee4d264SManish Chopra QED_RSS_IND_TABLE_SIZE * sizeof(u16)); 1754cee4d264SManish Chopra memcpy(sp_rss_params.rss_key, params->rss_params.rss_key, 1755cee4d264SManish Chopra QED_RSS_KEY_SIZE * sizeof(u32)); 1756cee4d264SManish Chopra } 1757cee4d264SManish Chopra sp_params.rss_params = &sp_rss_params; 1758cee4d264SManish Chopra 1759cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1760cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1761cee4d264SManish Chopra 1762cee4d264SManish Chopra sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1763cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &sp_params, 1764cee4d264SManish Chopra QED_SPQ_MODE_EBLOCK, 1765cee4d264SManish Chopra NULL); 1766cee4d264SManish Chopra if (rc) { 1767cee4d264SManish Chopra DP_ERR(cdev, "Failed to update VPORT\n"); 1768cee4d264SManish Chopra return rc; 1769cee4d264SManish Chopra } 1770cee4d264SManish Chopra 1771cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1772cee4d264SManish Chopra "Updated V-PORT %d: active_flag %d [update %d]\n", 1773cee4d264SManish Chopra params->vport_id, params->vport_active_flg, 1774cee4d264SManish Chopra params->update_vport_active_flg); 1775cee4d264SManish Chopra } 1776cee4d264SManish Chopra 1777cee4d264SManish Chopra return 0; 1778cee4d264SManish Chopra } 1779cee4d264SManish Chopra 1780cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev, 1781cee4d264SManish Chopra struct qed_queue_start_common_params *params, 1782cee4d264SManish Chopra u16 bd_max_bytes, 1783cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 1784cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 1785cee4d264SManish Chopra u16 cqe_pbl_size, 1786cee4d264SManish Chopra void __iomem **pp_prod) 1787cee4d264SManish Chopra { 1788cee4d264SManish Chopra int rc, hwfn_index; 1789cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1790cee4d264SManish Chopra 1791cee4d264SManish Chopra hwfn_index = params->rss_id % cdev->num_hwfns; 1792cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1793cee4d264SManish Chopra 1794cee4d264SManish Chopra /* Fix queue ID in 100g mode */ 1795cee4d264SManish Chopra params->queue_id /= cdev->num_hwfns; 1796cee4d264SManish Chopra 1797cee4d264SManish Chopra rc = qed_sp_eth_rx_queue_start(p_hwfn, 1798cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 1799cee4d264SManish Chopra params, 1800cee4d264SManish Chopra bd_max_bytes, 1801cee4d264SManish Chopra bd_chain_phys_addr, 1802cee4d264SManish Chopra cqe_pbl_addr, 1803cee4d264SManish Chopra cqe_pbl_size, 1804cee4d264SManish Chopra pp_prod); 1805cee4d264SManish Chopra 1806cee4d264SManish Chopra if (rc) { 1807cee4d264SManish Chopra DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id); 1808cee4d264SManish Chopra return rc; 1809cee4d264SManish Chopra } 1810cee4d264SManish Chopra 1811cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1812cee4d264SManish Chopra "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1813cee4d264SManish Chopra params->queue_id, params->rss_id, params->vport_id, 1814cee4d264SManish Chopra params->sb); 1815cee4d264SManish Chopra 1816cee4d264SManish Chopra return 0; 1817cee4d264SManish Chopra } 1818cee4d264SManish Chopra 1819cee4d264SManish Chopra static int qed_stop_rxq(struct qed_dev *cdev, 1820cee4d264SManish Chopra struct qed_stop_rxq_params *params) 1821cee4d264SManish Chopra { 1822cee4d264SManish Chopra int rc, hwfn_index; 1823cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1824cee4d264SManish Chopra 1825cee4d264SManish Chopra hwfn_index = params->rss_id % cdev->num_hwfns; 1826cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1827cee4d264SManish Chopra 1828cee4d264SManish Chopra rc = qed_sp_eth_rx_queue_stop(p_hwfn, 1829cee4d264SManish Chopra params->rx_queue_id / cdev->num_hwfns, 1830cee4d264SManish Chopra params->eq_completion_only, 1831cee4d264SManish Chopra false); 1832cee4d264SManish Chopra if (rc) { 1833cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id); 1834cee4d264SManish Chopra return rc; 1835cee4d264SManish Chopra } 1836cee4d264SManish Chopra 1837cee4d264SManish Chopra return 0; 1838cee4d264SManish Chopra } 1839cee4d264SManish Chopra 1840cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev, 1841cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 1842cee4d264SManish Chopra dma_addr_t pbl_addr, 1843cee4d264SManish Chopra u16 pbl_size, 1844cee4d264SManish Chopra void __iomem **pp_doorbell) 1845cee4d264SManish Chopra { 1846cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1847cee4d264SManish Chopra int rc, hwfn_index; 1848cee4d264SManish Chopra 1849cee4d264SManish Chopra hwfn_index = p_params->rss_id % cdev->num_hwfns; 1850cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1851cee4d264SManish Chopra 1852cee4d264SManish Chopra /* Fix queue ID in 100g mode */ 1853cee4d264SManish Chopra p_params->queue_id /= cdev->num_hwfns; 1854cee4d264SManish Chopra 1855cee4d264SManish Chopra rc = qed_sp_eth_tx_queue_start(p_hwfn, 1856cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 1857cee4d264SManish Chopra p_params, 1858cee4d264SManish Chopra pbl_addr, 1859cee4d264SManish Chopra pbl_size, 1860cee4d264SManish Chopra pp_doorbell); 1861cee4d264SManish Chopra 1862cee4d264SManish Chopra if (rc) { 1863cee4d264SManish Chopra DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 1864cee4d264SManish Chopra return rc; 1865cee4d264SManish Chopra } 1866cee4d264SManish Chopra 1867cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1868cee4d264SManish Chopra "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1869cee4d264SManish Chopra p_params->queue_id, p_params->rss_id, p_params->vport_id, 1870cee4d264SManish Chopra p_params->sb); 1871cee4d264SManish Chopra 1872cee4d264SManish Chopra return 0; 1873cee4d264SManish Chopra } 1874cee4d264SManish Chopra 1875cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10) 1876cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev) 1877cee4d264SManish Chopra { 1878cee4d264SManish Chopra qed_hw_stop_fastpath(cdev); 1879cee4d264SManish Chopra 1880cee4d264SManish Chopra return 0; 1881cee4d264SManish Chopra } 1882cee4d264SManish Chopra 1883cee4d264SManish Chopra static int qed_stop_txq(struct qed_dev *cdev, 1884cee4d264SManish Chopra struct qed_stop_txq_params *params) 1885cee4d264SManish Chopra { 1886cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1887cee4d264SManish Chopra int rc, hwfn_index; 1888cee4d264SManish Chopra 1889cee4d264SManish Chopra hwfn_index = params->rss_id % cdev->num_hwfns; 1890cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1891cee4d264SManish Chopra 1892cee4d264SManish Chopra rc = qed_sp_eth_tx_queue_stop(p_hwfn, 1893cee4d264SManish Chopra params->tx_queue_id / cdev->num_hwfns); 1894cee4d264SManish Chopra if (rc) { 1895cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id); 1896cee4d264SManish Chopra return rc; 1897cee4d264SManish Chopra } 1898cee4d264SManish Chopra 1899cee4d264SManish Chopra return 0; 1900cee4d264SManish Chopra } 1901cee4d264SManish Chopra 1902cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 1903cee4d264SManish Chopra enum qed_filter_rx_mode_type type) 1904cee4d264SManish Chopra { 1905cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 1906cee4d264SManish Chopra 1907cee4d264SManish Chopra memset(&accept_flags, 0, sizeof(accept_flags)); 1908cee4d264SManish Chopra 1909cee4d264SManish Chopra accept_flags.update_rx_mode_config = 1; 1910cee4d264SManish Chopra accept_flags.update_tx_mode_config = 1; 1911cee4d264SManish Chopra accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 1912cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 1913cee4d264SManish Chopra QED_ACCEPT_BCAST; 1914cee4d264SManish Chopra accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 1915cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 1916cee4d264SManish Chopra QED_ACCEPT_BCAST; 1917cee4d264SManish Chopra 1918cee4d264SManish Chopra if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) 1919cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 1920cee4d264SManish Chopra QED_ACCEPT_MCAST_UNMATCHED; 1921cee4d264SManish Chopra else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) 1922cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 1923cee4d264SManish Chopra 19243f9b4a69SYuval Mintz return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 1925cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 1926cee4d264SManish Chopra } 1927cee4d264SManish Chopra 1928cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev, 1929cee4d264SManish Chopra struct qed_filter_ucast_params *params) 1930cee4d264SManish Chopra { 1931cee4d264SManish Chopra struct qed_filter_ucast ucast; 1932cee4d264SManish Chopra 1933cee4d264SManish Chopra if (!params->vlan_valid && !params->mac_valid) { 1934cee4d264SManish Chopra DP_NOTICE( 1935cee4d264SManish Chopra cdev, 1936cee4d264SManish Chopra "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 1937cee4d264SManish Chopra return -EINVAL; 1938cee4d264SManish Chopra } 1939cee4d264SManish Chopra 1940cee4d264SManish Chopra memset(&ucast, 0, sizeof(ucast)); 1941cee4d264SManish Chopra switch (params->type) { 1942cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 1943cee4d264SManish Chopra ucast.opcode = QED_FILTER_ADD; 1944cee4d264SManish Chopra break; 1945cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 1946cee4d264SManish Chopra ucast.opcode = QED_FILTER_REMOVE; 1947cee4d264SManish Chopra break; 1948cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_REPLACE: 1949cee4d264SManish Chopra ucast.opcode = QED_FILTER_REPLACE; 1950cee4d264SManish Chopra break; 1951cee4d264SManish Chopra default: 1952cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 1953cee4d264SManish Chopra params->type); 1954cee4d264SManish Chopra } 1955cee4d264SManish Chopra 1956cee4d264SManish Chopra if (params->vlan_valid && params->mac_valid) { 1957cee4d264SManish Chopra ucast.type = QED_FILTER_MAC_VLAN; 1958cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 1959cee4d264SManish Chopra ucast.vlan = params->vlan; 1960cee4d264SManish Chopra } else if (params->mac_valid) { 1961cee4d264SManish Chopra ucast.type = QED_FILTER_MAC; 1962cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 1963cee4d264SManish Chopra } else { 1964cee4d264SManish Chopra ucast.type = QED_FILTER_VLAN; 1965cee4d264SManish Chopra ucast.vlan = params->vlan; 1966cee4d264SManish Chopra } 1967cee4d264SManish Chopra 1968cee4d264SManish Chopra ucast.is_rx_filter = true; 1969cee4d264SManish Chopra ucast.is_tx_filter = true; 1970cee4d264SManish Chopra 1971cee4d264SManish Chopra return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 1972cee4d264SManish Chopra } 1973cee4d264SManish Chopra 1974cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev, 1975cee4d264SManish Chopra struct qed_filter_mcast_params *params) 1976cee4d264SManish Chopra { 1977cee4d264SManish Chopra struct qed_filter_mcast mcast; 1978cee4d264SManish Chopra int i; 1979cee4d264SManish Chopra 1980cee4d264SManish Chopra memset(&mcast, 0, sizeof(mcast)); 1981cee4d264SManish Chopra switch (params->type) { 1982cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 1983cee4d264SManish Chopra mcast.opcode = QED_FILTER_ADD; 1984cee4d264SManish Chopra break; 1985cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 1986cee4d264SManish Chopra mcast.opcode = QED_FILTER_REMOVE; 1987cee4d264SManish Chopra break; 1988cee4d264SManish Chopra default: 1989cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 1990cee4d264SManish Chopra params->type); 1991cee4d264SManish Chopra } 1992cee4d264SManish Chopra 1993cee4d264SManish Chopra mcast.num_mc_addrs = params->num; 1994cee4d264SManish Chopra for (i = 0; i < mcast.num_mc_addrs; i++) 1995cee4d264SManish Chopra ether_addr_copy(mcast.mac[i], params->mac[i]); 1996cee4d264SManish Chopra 1997cee4d264SManish Chopra return qed_filter_mcast_cmd(cdev, &mcast, 1998cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 1999cee4d264SManish Chopra } 2000cee4d264SManish Chopra 2001cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev, 2002cee4d264SManish Chopra struct qed_filter_params *params) 2003cee4d264SManish Chopra { 2004cee4d264SManish Chopra enum qed_filter_rx_mode_type accept_flags; 2005cee4d264SManish Chopra 2006cee4d264SManish Chopra switch (params->type) { 2007cee4d264SManish Chopra case QED_FILTER_TYPE_UCAST: 2008cee4d264SManish Chopra return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 2009cee4d264SManish Chopra case QED_FILTER_TYPE_MCAST: 2010cee4d264SManish Chopra return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 2011cee4d264SManish Chopra case QED_FILTER_TYPE_RX_MODE: 2012cee4d264SManish Chopra accept_flags = params->filter.accept_flags; 2013cee4d264SManish Chopra return qed_configure_filter_rx_mode(cdev, accept_flags); 2014cee4d264SManish Chopra default: 2015cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown filter type %d\n", 2016cee4d264SManish Chopra (int)params->type); 2017cee4d264SManish Chopra return -EINVAL; 2018cee4d264SManish Chopra } 2019cee4d264SManish Chopra } 2020cee4d264SManish Chopra 2021cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev, 2022cee4d264SManish Chopra u8 rss_id, 2023cee4d264SManish Chopra struct eth_slow_path_rx_cqe *cqe) 2024cee4d264SManish Chopra { 2025cee4d264SManish Chopra return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 2026cee4d264SManish Chopra cqe); 2027cee4d264SManish Chopra } 2028cee4d264SManish Chopra 202925c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = { 203025c089d7SYuval Mintz .common = &qed_common_ops_pass, 203125c089d7SYuval Mintz .fill_dev_info = &qed_fill_eth_dev_info, 2032cc875c2eSYuval Mintz .register_ops = &qed_register_eth_ops, 2033cee4d264SManish Chopra .vport_start = &qed_start_vport, 2034cee4d264SManish Chopra .vport_stop = &qed_stop_vport, 2035cee4d264SManish Chopra .vport_update = &qed_update_vport, 2036cee4d264SManish Chopra .q_rx_start = &qed_start_rxq, 2037cee4d264SManish Chopra .q_rx_stop = &qed_stop_rxq, 2038cee4d264SManish Chopra .q_tx_start = &qed_start_txq, 2039cee4d264SManish Chopra .q_tx_stop = &qed_stop_txq, 2040cee4d264SManish Chopra .filter_config = &qed_configure_filter, 2041cee4d264SManish Chopra .fastpath_stop = &qed_fastpath_stop, 2042cee4d264SManish Chopra .eth_cqe_completion = &qed_fp_cqe_completion, 20439df2ed04SManish Chopra .get_vport_stats = &qed_get_vport_stats, 204425c089d7SYuval Mintz }; 204525c089d7SYuval Mintz 204695114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void) 204725c089d7SYuval Mintz { 204825c089d7SYuval Mintz return &qed_eth_ops_pass; 204925c089d7SYuval Mintz } 205025c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops); 205125c089d7SYuval Mintz 205225c089d7SYuval Mintz void qed_put_eth_ops(void) 205325c089d7SYuval Mintz { 205425c089d7SYuval Mintz /* TODO - reference count for module? */ 205525c089d7SYuval Mintz } 205625c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops); 2057