125c089d7SYuval Mintz /* QLogic qed NIC Driver 225c089d7SYuval Mintz * Copyright (c) 2015 QLogic Corporation 325c089d7SYuval Mintz * 425c089d7SYuval Mintz * This software is available under the terms of the GNU General Public License 525c089d7SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 625c089d7SYuval Mintz * this source tree. 725c089d7SYuval Mintz */ 825c089d7SYuval Mintz 925c089d7SYuval Mintz #include <linux/types.h> 1025c089d7SYuval Mintz #include <asm/byteorder.h> 1125c089d7SYuval Mintz #include <asm/param.h> 1225c089d7SYuval Mintz #include <linux/delay.h> 1325c089d7SYuval Mintz #include <linux/dma-mapping.h> 1425c089d7SYuval Mintz #include <linux/etherdevice.h> 1525c089d7SYuval Mintz #include <linux/interrupt.h> 1625c089d7SYuval Mintz #include <linux/kernel.h> 1725c089d7SYuval Mintz #include <linux/module.h> 1825c089d7SYuval Mintz #include <linux/pci.h> 1925c089d7SYuval Mintz #include <linux/slab.h> 2025c089d7SYuval Mintz #include <linux/stddef.h> 2125c089d7SYuval Mintz #include <linux/string.h> 2225c089d7SYuval Mintz #include <linux/version.h> 2325c089d7SYuval Mintz #include <linux/workqueue.h> 2425c089d7SYuval Mintz #include <linux/bitops.h> 2525c089d7SYuval Mintz #include <linux/bug.h> 2625c089d7SYuval Mintz #include "qed.h" 2725c089d7SYuval Mintz #include <linux/qed/qed_chain.h> 2825c089d7SYuval Mintz #include "qed_cxt.h" 2925c089d7SYuval Mintz #include "qed_dev_api.h" 3025c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h> 3125c089d7SYuval Mintz #include "qed_hsi.h" 3225c089d7SYuval Mintz #include "qed_hw.h" 3325c089d7SYuval Mintz #include "qed_int.h" 3486622ee7SYuval Mintz #include "qed_mcp.h" 3525c089d7SYuval Mintz #include "qed_reg_addr.h" 3625c089d7SYuval Mintz #include "qed_sp.h" 3725c089d7SYuval Mintz 38cee4d264SManish Chopra enum qed_rss_caps { 39cee4d264SManish Chopra QED_RSS_IPV4 = 0x1, 40cee4d264SManish Chopra QED_RSS_IPV6 = 0x2, 41cee4d264SManish Chopra QED_RSS_IPV4_TCP = 0x4, 42cee4d264SManish Chopra QED_RSS_IPV6_TCP = 0x8, 43cee4d264SManish Chopra QED_RSS_IPV4_UDP = 0x10, 44cee4d264SManish Chopra QED_RSS_IPV6_UDP = 0x20, 45cee4d264SManish Chopra }; 46cee4d264SManish Chopra 47cee4d264SManish Chopra /* Should be the same as ETH_RSS_IND_TABLE_ENTRIES_NUM */ 48cee4d264SManish Chopra #define QED_RSS_IND_TABLE_SIZE 128 49cee4d264SManish Chopra #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ 50cee4d264SManish Chopra 51cee4d264SManish Chopra struct qed_rss_params { 52cee4d264SManish Chopra u8 update_rss_config; 53cee4d264SManish Chopra u8 rss_enable; 54cee4d264SManish Chopra u8 rss_eng_id; 55cee4d264SManish Chopra u8 update_rss_capabilities; 56cee4d264SManish Chopra u8 update_rss_ind_table; 57cee4d264SManish Chopra u8 update_rss_key; 58cee4d264SManish Chopra u8 rss_caps; 59cee4d264SManish Chopra u8 rss_table_size_log; 60cee4d264SManish Chopra u16 rss_ind_table[QED_RSS_IND_TABLE_SIZE]; 61cee4d264SManish Chopra u32 rss_key[QED_RSS_KEY_SIZE]; 62cee4d264SManish Chopra }; 63cee4d264SManish Chopra 64cee4d264SManish Chopra enum qed_filter_opcode { 65cee4d264SManish Chopra QED_FILTER_ADD, 66cee4d264SManish Chopra QED_FILTER_REMOVE, 67cee4d264SManish Chopra QED_FILTER_MOVE, 68cee4d264SManish Chopra QED_FILTER_REPLACE, /* Delete all MACs and add new one instead */ 69cee4d264SManish Chopra QED_FILTER_FLUSH, /* Removes all filters */ 70cee4d264SManish Chopra }; 71cee4d264SManish Chopra 72cee4d264SManish Chopra enum qed_filter_ucast_type { 73cee4d264SManish Chopra QED_FILTER_MAC, 74cee4d264SManish Chopra QED_FILTER_VLAN, 75cee4d264SManish Chopra QED_FILTER_MAC_VLAN, 76cee4d264SManish Chopra QED_FILTER_INNER_MAC, 77cee4d264SManish Chopra QED_FILTER_INNER_VLAN, 78cee4d264SManish Chopra QED_FILTER_INNER_PAIR, 79cee4d264SManish Chopra QED_FILTER_INNER_MAC_VNI_PAIR, 80cee4d264SManish Chopra QED_FILTER_MAC_VNI_PAIR, 81cee4d264SManish Chopra QED_FILTER_VNI, 82cee4d264SManish Chopra }; 83cee4d264SManish Chopra 84cee4d264SManish Chopra struct qed_filter_ucast { 85cee4d264SManish Chopra enum qed_filter_opcode opcode; 86cee4d264SManish Chopra enum qed_filter_ucast_type type; 87cee4d264SManish Chopra u8 is_rx_filter; 88cee4d264SManish Chopra u8 is_tx_filter; 89cee4d264SManish Chopra u8 vport_to_add_to; 90cee4d264SManish Chopra u8 vport_to_remove_from; 91cee4d264SManish Chopra unsigned char mac[ETH_ALEN]; 92cee4d264SManish Chopra u8 assert_on_error; 93cee4d264SManish Chopra u16 vlan; 94cee4d264SManish Chopra u32 vni; 95cee4d264SManish Chopra }; 96cee4d264SManish Chopra 97cee4d264SManish Chopra struct qed_filter_mcast { 98cee4d264SManish Chopra /* MOVE is not supported for multicast */ 99cee4d264SManish Chopra enum qed_filter_opcode opcode; 100cee4d264SManish Chopra u8 vport_to_add_to; 101cee4d264SManish Chopra u8 vport_to_remove_from; 102cee4d264SManish Chopra u8 num_mc_addrs; 103cee4d264SManish Chopra #define QED_MAX_MC_ADDRS 64 104cee4d264SManish Chopra unsigned char mac[QED_MAX_MC_ADDRS][ETH_ALEN]; 105cee4d264SManish Chopra }; 106cee4d264SManish Chopra 107cee4d264SManish Chopra struct qed_filter_accept_flags { 108cee4d264SManish Chopra u8 update_rx_mode_config; 109cee4d264SManish Chopra u8 update_tx_mode_config; 110cee4d264SManish Chopra u8 rx_accept_filter; 111cee4d264SManish Chopra u8 tx_accept_filter; 112cee4d264SManish Chopra #define QED_ACCEPT_NONE 0x01 113cee4d264SManish Chopra #define QED_ACCEPT_UCAST_MATCHED 0x02 114cee4d264SManish Chopra #define QED_ACCEPT_UCAST_UNMATCHED 0x04 115cee4d264SManish Chopra #define QED_ACCEPT_MCAST_MATCHED 0x08 116cee4d264SManish Chopra #define QED_ACCEPT_MCAST_UNMATCHED 0x10 117cee4d264SManish Chopra #define QED_ACCEPT_BCAST 0x20 118cee4d264SManish Chopra }; 119cee4d264SManish Chopra 120cee4d264SManish Chopra struct qed_sp_vport_update_params { 121cee4d264SManish Chopra u16 opaque_fid; 122cee4d264SManish Chopra u8 vport_id; 123cee4d264SManish Chopra u8 update_vport_active_rx_flg; 124cee4d264SManish Chopra u8 vport_active_rx_flg; 125cee4d264SManish Chopra u8 update_vport_active_tx_flg; 126cee4d264SManish Chopra u8 vport_active_tx_flg; 127cee4d264SManish Chopra u8 update_approx_mcast_flg; 1283f9b4a69SYuval Mintz u8 update_accept_any_vlan_flg; 1293f9b4a69SYuval Mintz u8 accept_any_vlan; 130cee4d264SManish Chopra unsigned long bins[8]; 131cee4d264SManish Chopra struct qed_rss_params *rss_params; 132cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 133cee4d264SManish Chopra }; 134cee4d264SManish Chopra 135cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16 136cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41 137cee4d264SManish Chopra 138cee4d264SManish Chopra static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 139cee4d264SManish Chopra u32 concrete_fid, 140cee4d264SManish Chopra u16 opaque_fid, 141cee4d264SManish Chopra u8 vport_id, 142cee4d264SManish Chopra u16 mtu, 143cee4d264SManish Chopra u8 drop_ttl0_flg, 144cee4d264SManish Chopra u8 inner_vlan_removal_en_flg) 145cee4d264SManish Chopra { 146cee4d264SManish Chopra struct vport_start_ramrod_data *p_ramrod = NULL; 147cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 14806f56b81SYuval Mintz struct qed_sp_init_data init_data; 149cee4d264SManish Chopra int rc = -EINVAL; 150cee4d264SManish Chopra u16 rx_mode = 0; 151cee4d264SManish Chopra u8 abs_vport_id = 0; 152cee4d264SManish Chopra 153cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 154cee4d264SManish Chopra if (rc != 0) 155cee4d264SManish Chopra return rc; 156cee4d264SManish Chopra 15706f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 15806f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 15906f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 16006f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 161cee4d264SManish Chopra 162cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 163cee4d264SManish Chopra ETH_RAMROD_VPORT_START, 16406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 165cee4d264SManish Chopra if (rc) 166cee4d264SManish Chopra return rc; 167cee4d264SManish Chopra 168cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_start; 169cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 170cee4d264SManish Chopra 171cee4d264SManish Chopra p_ramrod->mtu = cpu_to_le16(mtu); 172cee4d264SManish Chopra p_ramrod->inner_vlan_removal_en = inner_vlan_removal_en_flg; 173cee4d264SManish Chopra p_ramrod->drop_ttl0_en = drop_ttl0_flg; 174cee4d264SManish Chopra 175cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 176cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 177cee4d264SManish Chopra 178cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 179cee4d264SManish Chopra 180cee4d264SManish Chopra /* TPA related fields */ 181cee4d264SManish Chopra memset(&p_ramrod->tpa_param, 0, 182cee4d264SManish Chopra sizeof(struct eth_vport_tpa_param)); 183cee4d264SManish Chopra 184cee4d264SManish Chopra /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 185cee4d264SManish Chopra p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 186cee4d264SManish Chopra concrete_fid); 187cee4d264SManish Chopra 188cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 189cee4d264SManish Chopra } 190cee4d264SManish Chopra 191cee4d264SManish Chopra static int 192cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 193cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 194cee4d264SManish Chopra struct qed_rss_params *p_params) 195cee4d264SManish Chopra { 196cee4d264SManish Chopra struct eth_vport_rss_config *rss = &p_ramrod->rss_config; 197cee4d264SManish Chopra u16 abs_l2_queue = 0, capabilities = 0; 198cee4d264SManish Chopra int rc = 0, i; 199cee4d264SManish Chopra 200cee4d264SManish Chopra if (!p_params) { 201cee4d264SManish Chopra p_ramrod->common.update_rss_flg = 0; 202cee4d264SManish Chopra return rc; 203cee4d264SManish Chopra } 204cee4d264SManish Chopra 205cee4d264SManish Chopra BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != 206cee4d264SManish Chopra ETH_RSS_IND_TABLE_ENTRIES_NUM); 207cee4d264SManish Chopra 208cee4d264SManish Chopra rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id); 209cee4d264SManish Chopra if (rc) 210cee4d264SManish Chopra return rc; 211cee4d264SManish Chopra 212cee4d264SManish Chopra p_ramrod->common.update_rss_flg = p_params->update_rss_config; 213cee4d264SManish Chopra rss->update_rss_capabilities = p_params->update_rss_capabilities; 214cee4d264SManish Chopra rss->update_rss_ind_table = p_params->update_rss_ind_table; 215cee4d264SManish Chopra rss->update_rss_key = p_params->update_rss_key; 216cee4d264SManish Chopra 217cee4d264SManish Chopra rss->rss_mode = p_params->rss_enable ? 218cee4d264SManish Chopra ETH_VPORT_RSS_MODE_REGULAR : 219cee4d264SManish Chopra ETH_VPORT_RSS_MODE_DISABLED; 220cee4d264SManish Chopra 221cee4d264SManish Chopra SET_FIELD(capabilities, 222cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 223cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV4)); 224cee4d264SManish Chopra SET_FIELD(capabilities, 225cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 226cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV6)); 227cee4d264SManish Chopra SET_FIELD(capabilities, 228cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 229cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV4_TCP)); 230cee4d264SManish Chopra SET_FIELD(capabilities, 231cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 232cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV6_TCP)); 233cee4d264SManish Chopra SET_FIELD(capabilities, 234cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 235cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV4_UDP)); 236cee4d264SManish Chopra SET_FIELD(capabilities, 237cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 238cee4d264SManish Chopra !!(p_params->rss_caps & QED_RSS_IPV6_UDP)); 239cee4d264SManish Chopra rss->tbl_size = p_params->rss_table_size_log; 240cee4d264SManish Chopra 241cee4d264SManish Chopra rss->capabilities = cpu_to_le16(capabilities); 242cee4d264SManish Chopra 243cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 244cee4d264SManish Chopra "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 245cee4d264SManish Chopra p_ramrod->common.update_rss_flg, 246cee4d264SManish Chopra rss->rss_mode, rss->update_rss_capabilities, 247cee4d264SManish Chopra capabilities, rss->update_rss_ind_table, 248cee4d264SManish Chopra rss->update_rss_key); 249cee4d264SManish Chopra 250cee4d264SManish Chopra for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 251cee4d264SManish Chopra rc = qed_fw_l2_queue(p_hwfn, 252cee4d264SManish Chopra (u8)p_params->rss_ind_table[i], 253cee4d264SManish Chopra &abs_l2_queue); 254cee4d264SManish Chopra if (rc) 255cee4d264SManish Chopra return rc; 256cee4d264SManish Chopra 257cee4d264SManish Chopra rss->indirection_table[i] = cpu_to_le16(abs_l2_queue); 258cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n", 259cee4d264SManish Chopra i, rss->indirection_table[i]); 260cee4d264SManish Chopra } 261cee4d264SManish Chopra 262cee4d264SManish Chopra for (i = 0; i < 10; i++) 263cee4d264SManish Chopra rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]); 264cee4d264SManish Chopra 265cee4d264SManish Chopra return rc; 266cee4d264SManish Chopra } 267cee4d264SManish Chopra 268cee4d264SManish Chopra static void 269cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 270cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 271cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags) 272cee4d264SManish Chopra { 273cee4d264SManish Chopra p_ramrod->common.update_rx_mode_flg = 274cee4d264SManish Chopra accept_flags.update_rx_mode_config; 275cee4d264SManish Chopra 276cee4d264SManish Chopra p_ramrod->common.update_tx_mode_flg = 277cee4d264SManish Chopra accept_flags.update_tx_mode_config; 278cee4d264SManish Chopra 279cee4d264SManish Chopra /* Set Rx mode accept flags */ 280cee4d264SManish Chopra if (p_ramrod->common.update_rx_mode_flg) { 281cee4d264SManish Chopra u8 accept_filter = accept_flags.rx_accept_filter; 282cee4d264SManish Chopra u16 state = 0; 283cee4d264SManish Chopra 284cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 285cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 286cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 287cee4d264SManish Chopra 288cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 289cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 290cee4d264SManish Chopra 291cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 292cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 293cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 294cee4d264SManish Chopra 295cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 296cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 297cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 298cee4d264SManish Chopra 299cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 300cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 301cee4d264SManish Chopra 302cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(state); 303cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 304cee4d264SManish Chopra "p_ramrod->rx_mode.state = 0x%x\n", state); 305cee4d264SManish Chopra } 306cee4d264SManish Chopra 307cee4d264SManish Chopra /* Set Tx mode accept flags */ 308cee4d264SManish Chopra if (p_ramrod->common.update_tx_mode_flg) { 309cee4d264SManish Chopra u8 accept_filter = accept_flags.tx_accept_filter; 310cee4d264SManish Chopra u16 state = 0; 311cee4d264SManish Chopra 312cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 313cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 314cee4d264SManish Chopra 315cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL, 316cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) && 317cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 318cee4d264SManish Chopra 319cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 320cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 321cee4d264SManish Chopra 322cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 323cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 324cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 325cee4d264SManish Chopra 326cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 327cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 328cee4d264SManish Chopra 329cee4d264SManish Chopra p_ramrod->tx_mode.state = cpu_to_le16(state); 330cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 331cee4d264SManish Chopra "p_ramrod->tx_mode.state = 0x%x\n", state); 332cee4d264SManish Chopra } 333cee4d264SManish Chopra } 334cee4d264SManish Chopra 335cee4d264SManish Chopra static void 336cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 337cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 338cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params) 339cee4d264SManish Chopra { 340cee4d264SManish Chopra int i; 341cee4d264SManish Chopra 342cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 343cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 344cee4d264SManish Chopra 345cee4d264SManish Chopra if (p_params->update_approx_mcast_flg) { 346cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 347cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 348cee4d264SManish Chopra u32 *p_bins = (u32 *)p_params->bins; 349cee4d264SManish Chopra __le32 val = cpu_to_le32(p_bins[i]); 350cee4d264SManish Chopra 351cee4d264SManish Chopra p_ramrod->approx_mcast.bins[i] = val; 352cee4d264SManish Chopra } 353cee4d264SManish Chopra } 354cee4d264SManish Chopra } 355cee4d264SManish Chopra 356cee4d264SManish Chopra static int 357cee4d264SManish Chopra qed_sp_vport_update(struct qed_hwfn *p_hwfn, 358cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params, 359cee4d264SManish Chopra enum spq_mode comp_mode, 360cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 361cee4d264SManish Chopra { 362cee4d264SManish Chopra struct qed_rss_params *p_rss_params = p_params->rss_params; 363cee4d264SManish Chopra struct vport_update_ramrod_data_cmn *p_cmn; 36406f56b81SYuval Mintz struct qed_sp_init_data init_data; 365cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 366cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 367cee4d264SManish Chopra u8 abs_vport_id = 0; 368cee4d264SManish Chopra int rc = -EINVAL; 369cee4d264SManish Chopra 370cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 371cee4d264SManish Chopra if (rc != 0) 372cee4d264SManish Chopra return rc; 373cee4d264SManish Chopra 37406f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 37506f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 37606f56b81SYuval Mintz init_data.opaque_fid = p_params->opaque_fid; 37706f56b81SYuval Mintz init_data.comp_mode = comp_mode; 37806f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 379cee4d264SManish Chopra 380cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 381cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 38206f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 383cee4d264SManish Chopra if (rc) 384cee4d264SManish Chopra return rc; 385cee4d264SManish Chopra 386cee4d264SManish Chopra /* Copy input params to ramrod according to FW struct */ 387cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 388cee4d264SManish Chopra p_cmn = &p_ramrod->common; 389cee4d264SManish Chopra 390cee4d264SManish Chopra p_cmn->vport_id = abs_vport_id; 391cee4d264SManish Chopra p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 392cee4d264SManish Chopra p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 393cee4d264SManish Chopra p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 394cee4d264SManish Chopra p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 3953f9b4a69SYuval Mintz p_cmn->accept_any_vlan = p_params->accept_any_vlan; 3963f9b4a69SYuval Mintz p_cmn->update_accept_any_vlan_flg = 3973f9b4a69SYuval Mintz p_params->update_accept_any_vlan_flg; 398cee4d264SManish Chopra rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 399cee4d264SManish Chopra if (rc) { 400cee4d264SManish Chopra /* Return spq entry which is taken in qed_sp_init_request()*/ 401cee4d264SManish Chopra qed_spq_return_entry(p_hwfn, p_ent); 402cee4d264SManish Chopra return rc; 403cee4d264SManish Chopra } 404cee4d264SManish Chopra 405cee4d264SManish Chopra /* Update mcast bins for VFs, PF doesn't use this functionality */ 406cee4d264SManish Chopra qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 407cee4d264SManish Chopra 408cee4d264SManish Chopra qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 409cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 410cee4d264SManish Chopra } 411cee4d264SManish Chopra 412cee4d264SManish Chopra static int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, 413cee4d264SManish Chopra u16 opaque_fid, 414cee4d264SManish Chopra u8 vport_id) 415cee4d264SManish Chopra { 416cee4d264SManish Chopra struct vport_stop_ramrod_data *p_ramrod; 41706f56b81SYuval Mintz struct qed_sp_init_data init_data; 418cee4d264SManish Chopra struct qed_spq_entry *p_ent; 419cee4d264SManish Chopra u8 abs_vport_id = 0; 420cee4d264SManish Chopra int rc; 421cee4d264SManish Chopra 422cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 423cee4d264SManish Chopra if (rc != 0) 424cee4d264SManish Chopra return rc; 425cee4d264SManish Chopra 42606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 42706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 42806f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 42906f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 430cee4d264SManish Chopra 431cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 432cee4d264SManish Chopra ETH_RAMROD_VPORT_STOP, 43306f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 434cee4d264SManish Chopra if (rc) 435cee4d264SManish Chopra return rc; 436cee4d264SManish Chopra 437cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_stop; 438cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 439cee4d264SManish Chopra 440cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 441cee4d264SManish Chopra } 442cee4d264SManish Chopra 443cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev, 444cee4d264SManish Chopra u8 vport, 445cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags, 4463f9b4a69SYuval Mintz u8 update_accept_any_vlan, 4473f9b4a69SYuval Mintz u8 accept_any_vlan, 448cee4d264SManish Chopra enum spq_mode comp_mode, 449cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 450cee4d264SManish Chopra { 451cee4d264SManish Chopra struct qed_sp_vport_update_params vport_update_params; 452cee4d264SManish Chopra int i, rc; 453cee4d264SManish Chopra 454cee4d264SManish Chopra /* Prepare and send the vport rx_mode change */ 455cee4d264SManish Chopra memset(&vport_update_params, 0, sizeof(vport_update_params)); 456cee4d264SManish Chopra vport_update_params.vport_id = vport; 457cee4d264SManish Chopra vport_update_params.accept_flags = accept_flags; 4583f9b4a69SYuval Mintz vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 4593f9b4a69SYuval Mintz vport_update_params.accept_any_vlan = accept_any_vlan; 460cee4d264SManish Chopra 461cee4d264SManish Chopra for_each_hwfn(cdev, i) { 462cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 463cee4d264SManish Chopra 464cee4d264SManish Chopra vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 465cee4d264SManish Chopra 466cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 467cee4d264SManish Chopra comp_mode, p_comp_data); 468cee4d264SManish Chopra if (rc != 0) { 469cee4d264SManish Chopra DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 470cee4d264SManish Chopra return rc; 471cee4d264SManish Chopra } 472cee4d264SManish Chopra 473cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 474cee4d264SManish Chopra "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 475cee4d264SManish Chopra accept_flags.rx_accept_filter, 476cee4d264SManish Chopra accept_flags.tx_accept_filter); 4773f9b4a69SYuval Mintz if (update_accept_any_vlan) 4783f9b4a69SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 4793f9b4a69SYuval Mintz "accept_any_vlan=%d configured\n", 4803f9b4a69SYuval Mintz accept_any_vlan); 481cee4d264SManish Chopra } 482cee4d264SManish Chopra 483cee4d264SManish Chopra return 0; 484cee4d264SManish Chopra } 485cee4d264SManish Chopra 486cee4d264SManish Chopra static int qed_sp_release_queue_cid( 487cee4d264SManish Chopra struct qed_hwfn *p_hwfn, 488cee4d264SManish Chopra struct qed_hw_cid_data *p_cid_data) 489cee4d264SManish Chopra { 490cee4d264SManish Chopra if (!p_cid_data->b_cid_allocated) 491cee4d264SManish Chopra return 0; 492cee4d264SManish Chopra 493cee4d264SManish Chopra qed_cxt_release_cid(p_hwfn, p_cid_data->cid); 494cee4d264SManish Chopra 495cee4d264SManish Chopra p_cid_data->b_cid_allocated = false; 496cee4d264SManish Chopra 497cee4d264SManish Chopra return 0; 498cee4d264SManish Chopra } 499cee4d264SManish Chopra 500cee4d264SManish Chopra static int 501cee4d264SManish Chopra qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 502cee4d264SManish Chopra u16 opaque_fid, 503cee4d264SManish Chopra u32 cid, 504cee4d264SManish Chopra struct qed_queue_start_common_params *params, 505cee4d264SManish Chopra u8 stats_id, 506cee4d264SManish Chopra u16 bd_max_bytes, 507cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 508cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 509cee4d264SManish Chopra u16 cqe_pbl_size) 510cee4d264SManish Chopra { 511cee4d264SManish Chopra struct rx_queue_start_ramrod_data *p_ramrod = NULL; 512cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 51306f56b81SYuval Mintz struct qed_sp_init_data init_data; 514cee4d264SManish Chopra struct qed_hw_cid_data *p_rx_cid; 515cee4d264SManish Chopra u16 abs_rx_q_id = 0; 516cee4d264SManish Chopra u8 abs_vport_id = 0; 517cee4d264SManish Chopra int rc = -EINVAL; 518cee4d264SManish Chopra 519cee4d264SManish Chopra /* Store information for the stop */ 520cee4d264SManish Chopra p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 521cee4d264SManish Chopra p_rx_cid->cid = cid; 522cee4d264SManish Chopra p_rx_cid->opaque_fid = opaque_fid; 523cee4d264SManish Chopra p_rx_cid->vport_id = params->vport_id; 524cee4d264SManish Chopra 525cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id); 526cee4d264SManish Chopra if (rc != 0) 527cee4d264SManish Chopra return rc; 528cee4d264SManish Chopra 529cee4d264SManish Chopra rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id); 530cee4d264SManish Chopra if (rc != 0) 531cee4d264SManish Chopra return rc; 532cee4d264SManish Chopra 533cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 534cee4d264SManish Chopra "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 535cee4d264SManish Chopra opaque_fid, cid, params->queue_id, params->vport_id, 536cee4d264SManish Chopra params->sb); 537cee4d264SManish Chopra 53806f56b81SYuval Mintz /* Get SPQ entry */ 53906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 54006f56b81SYuval Mintz init_data.cid = cid; 54106f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 54206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 543cee4d264SManish Chopra 544cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 545cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_START, 54606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 547cee4d264SManish Chopra if (rc) 548cee4d264SManish Chopra return rc; 549cee4d264SManish Chopra 550cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_start; 551cee4d264SManish Chopra 552cee4d264SManish Chopra p_ramrod->sb_id = cpu_to_le16(params->sb); 553cee4d264SManish Chopra p_ramrod->sb_index = params->sb_idx; 554cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 555cee4d264SManish Chopra p_ramrod->stats_counter_id = stats_id; 556cee4d264SManish Chopra p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 557cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 0; 558cee4d264SManish Chopra p_ramrod->complete_event_flg = 1; 559cee4d264SManish Chopra 560cee4d264SManish Chopra p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 56194494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 562cee4d264SManish Chopra 563cee4d264SManish Chopra p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 56494494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 565cee4d264SManish Chopra 566cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 567cee4d264SManish Chopra 568cee4d264SManish Chopra return rc; 569cee4d264SManish Chopra } 570cee4d264SManish Chopra 571cee4d264SManish Chopra static int 572cee4d264SManish Chopra qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 573cee4d264SManish Chopra u16 opaque_fid, 574cee4d264SManish Chopra struct qed_queue_start_common_params *params, 575cee4d264SManish Chopra u16 bd_max_bytes, 576cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 577cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 578cee4d264SManish Chopra u16 cqe_pbl_size, 579cee4d264SManish Chopra void __iomem **pp_prod) 580cee4d264SManish Chopra { 581cee4d264SManish Chopra struct qed_hw_cid_data *p_rx_cid; 582cee4d264SManish Chopra u64 init_prod_val = 0; 583cee4d264SManish Chopra u16 abs_l2_queue = 0; 584cee4d264SManish Chopra u8 abs_stats_id = 0; 585cee4d264SManish Chopra int rc; 586cee4d264SManish Chopra 587cee4d264SManish Chopra rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue); 588cee4d264SManish Chopra if (rc != 0) 589cee4d264SManish Chopra return rc; 590cee4d264SManish Chopra 591cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id); 592cee4d264SManish Chopra if (rc != 0) 593cee4d264SManish Chopra return rc; 594cee4d264SManish Chopra 595cee4d264SManish Chopra *pp_prod = (u8 __iomem *)p_hwfn->regview + 596cee4d264SManish Chopra GTT_BAR0_MAP_REG_MSDM_RAM + 597cee4d264SManish Chopra MSTORM_PRODS_OFFSET(abs_l2_queue); 598cee4d264SManish Chopra 599cee4d264SManish Chopra /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 600cee4d264SManish Chopra __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64), 601cee4d264SManish Chopra (u32 *)(&init_prod_val)); 602cee4d264SManish Chopra 603cee4d264SManish Chopra /* Allocate a CID for the queue */ 604cee4d264SManish Chopra p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id]; 605cee4d264SManish Chopra rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 606cee4d264SManish Chopra &p_rx_cid->cid); 607cee4d264SManish Chopra if (rc) { 608cee4d264SManish Chopra DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 609cee4d264SManish Chopra return rc; 610cee4d264SManish Chopra } 611cee4d264SManish Chopra p_rx_cid->b_cid_allocated = true; 612cee4d264SManish Chopra 613cee4d264SManish Chopra rc = qed_sp_eth_rxq_start_ramrod(p_hwfn, 614cee4d264SManish Chopra opaque_fid, 615cee4d264SManish Chopra p_rx_cid->cid, 616cee4d264SManish Chopra params, 617cee4d264SManish Chopra abs_stats_id, 618cee4d264SManish Chopra bd_max_bytes, 619cee4d264SManish Chopra bd_chain_phys_addr, 620cee4d264SManish Chopra cqe_pbl_addr, 621cee4d264SManish Chopra cqe_pbl_size); 622cee4d264SManish Chopra 623cee4d264SManish Chopra if (rc != 0) 624cee4d264SManish Chopra qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 625cee4d264SManish Chopra 626cee4d264SManish Chopra return rc; 627cee4d264SManish Chopra } 628cee4d264SManish Chopra 629cee4d264SManish Chopra static int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 630cee4d264SManish Chopra u16 rx_queue_id, 631cee4d264SManish Chopra bool eq_completion_only, 632cee4d264SManish Chopra bool cqe_completion) 633cee4d264SManish Chopra { 634cee4d264SManish Chopra struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id]; 635cee4d264SManish Chopra struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 636cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 63706f56b81SYuval Mintz struct qed_sp_init_data init_data; 638cee4d264SManish Chopra u16 abs_rx_q_id = 0; 639cee4d264SManish Chopra int rc = -EINVAL; 640cee4d264SManish Chopra 64106f56b81SYuval Mintz /* Get SPQ entry */ 64206f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 64306f56b81SYuval Mintz init_data.cid = p_rx_cid->cid; 64406f56b81SYuval Mintz init_data.opaque_fid = p_rx_cid->opaque_fid; 64506f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 646cee4d264SManish Chopra 647cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 648cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_STOP, 64906f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 650cee4d264SManish Chopra if (rc) 651cee4d264SManish Chopra return rc; 652cee4d264SManish Chopra 653cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_stop; 654cee4d264SManish Chopra 655cee4d264SManish Chopra qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); 656cee4d264SManish Chopra qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id); 657cee4d264SManish Chopra p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); 658cee4d264SManish Chopra 659cee4d264SManish Chopra /* Cleaning the queue requires the completion to arrive there. 660cee4d264SManish Chopra * In addition, VFs require the answer to come as eqe to PF. 661cee4d264SManish Chopra */ 662cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 663cee4d264SManish Chopra (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) && 664cee4d264SManish Chopra !eq_completion_only) || cqe_completion; 665cee4d264SManish Chopra p_ramrod->complete_event_flg = 666cee4d264SManish Chopra !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) || 667cee4d264SManish Chopra eq_completion_only; 668cee4d264SManish Chopra 669cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 670cee4d264SManish Chopra if (rc) 671cee4d264SManish Chopra return rc; 672cee4d264SManish Chopra 673cee4d264SManish Chopra return qed_sp_release_queue_cid(p_hwfn, p_rx_cid); 674cee4d264SManish Chopra } 675cee4d264SManish Chopra 676cee4d264SManish Chopra static int 677cee4d264SManish Chopra qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 678cee4d264SManish Chopra u16 opaque_fid, 679cee4d264SManish Chopra u32 cid, 680cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 681cee4d264SManish Chopra u8 stats_id, 682cee4d264SManish Chopra dma_addr_t pbl_addr, 683cee4d264SManish Chopra u16 pbl_size, 684cee4d264SManish Chopra union qed_qm_pq_params *p_pq_params) 685cee4d264SManish Chopra { 686cee4d264SManish Chopra struct tx_queue_start_ramrod_data *p_ramrod = NULL; 687cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 68806f56b81SYuval Mintz struct qed_sp_init_data init_data; 689cee4d264SManish Chopra struct qed_hw_cid_data *p_tx_cid; 690cee4d264SManish Chopra u8 abs_vport_id; 691cee4d264SManish Chopra int rc = -EINVAL; 692cee4d264SManish Chopra u16 pq_id; 693cee4d264SManish Chopra 694cee4d264SManish Chopra /* Store information for the stop */ 695cee4d264SManish Chopra p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 696cee4d264SManish Chopra p_tx_cid->cid = cid; 697cee4d264SManish Chopra p_tx_cid->opaque_fid = opaque_fid; 698cee4d264SManish Chopra 699cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 700cee4d264SManish Chopra if (rc) 701cee4d264SManish Chopra return rc; 702cee4d264SManish Chopra 70306f56b81SYuval Mintz /* Get SPQ entry */ 70406f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 70506f56b81SYuval Mintz init_data.cid = cid; 70606f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 70706f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 708cee4d264SManish Chopra 70906f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 710cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_START, 71106f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 712cee4d264SManish Chopra if (rc) 713cee4d264SManish Chopra return rc; 714cee4d264SManish Chopra 715cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.tx_queue_start; 716cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 717cee4d264SManish Chopra 718cee4d264SManish Chopra p_ramrod->sb_id = cpu_to_le16(p_params->sb); 719cee4d264SManish Chopra p_ramrod->sb_index = p_params->sb_idx; 720cee4d264SManish Chopra p_ramrod->stats_counter_id = stats_id; 721cee4d264SManish Chopra 722cee4d264SManish Chopra p_ramrod->pbl_size = cpu_to_le16(pbl_size); 72394494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 724cee4d264SManish Chopra 725cee4d264SManish Chopra pq_id = qed_get_qm_pq(p_hwfn, 726cee4d264SManish Chopra PROTOCOLID_ETH, 727cee4d264SManish Chopra p_pq_params); 728cee4d264SManish Chopra p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 729cee4d264SManish Chopra 730cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 731cee4d264SManish Chopra } 732cee4d264SManish Chopra 733cee4d264SManish Chopra static int 734cee4d264SManish Chopra qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 735cee4d264SManish Chopra u16 opaque_fid, 736cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 737cee4d264SManish Chopra dma_addr_t pbl_addr, 738cee4d264SManish Chopra u16 pbl_size, 739cee4d264SManish Chopra void __iomem **pp_doorbell) 740cee4d264SManish Chopra { 741cee4d264SManish Chopra struct qed_hw_cid_data *p_tx_cid; 742cee4d264SManish Chopra union qed_qm_pq_params pq_params; 743cee4d264SManish Chopra u8 abs_stats_id = 0; 744cee4d264SManish Chopra int rc; 745cee4d264SManish Chopra 746cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id); 747cee4d264SManish Chopra if (rc) 748cee4d264SManish Chopra return rc; 749cee4d264SManish Chopra 750cee4d264SManish Chopra p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; 751cee4d264SManish Chopra memset(p_tx_cid, 0, sizeof(*p_tx_cid)); 752cee4d264SManish Chopra memset(&pq_params, 0, sizeof(pq_params)); 753cee4d264SManish Chopra 754cee4d264SManish Chopra /* Allocate a CID for the queue */ 755cee4d264SManish Chopra rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 756cee4d264SManish Chopra &p_tx_cid->cid); 757cee4d264SManish Chopra if (rc) { 758cee4d264SManish Chopra DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 759cee4d264SManish Chopra return rc; 760cee4d264SManish Chopra } 761cee4d264SManish Chopra p_tx_cid->b_cid_allocated = true; 762cee4d264SManish Chopra 763cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 764cee4d264SManish Chopra "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", 765cee4d264SManish Chopra opaque_fid, p_tx_cid->cid, 766cee4d264SManish Chopra p_params->queue_id, p_params->vport_id, p_params->sb); 767cee4d264SManish Chopra 768cee4d264SManish Chopra rc = qed_sp_eth_txq_start_ramrod(p_hwfn, 769cee4d264SManish Chopra opaque_fid, 770cee4d264SManish Chopra p_tx_cid->cid, 771cee4d264SManish Chopra p_params, 772cee4d264SManish Chopra abs_stats_id, 773cee4d264SManish Chopra pbl_addr, 774cee4d264SManish Chopra pbl_size, 775cee4d264SManish Chopra &pq_params); 776cee4d264SManish Chopra 777cee4d264SManish Chopra *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + 778cee4d264SManish Chopra qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY); 779cee4d264SManish Chopra 780cee4d264SManish Chopra if (rc) 781cee4d264SManish Chopra qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 782cee4d264SManish Chopra 783cee4d264SManish Chopra return rc; 784cee4d264SManish Chopra } 785cee4d264SManish Chopra 786cee4d264SManish Chopra static int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, 787cee4d264SManish Chopra u16 tx_queue_id) 788cee4d264SManish Chopra { 789cee4d264SManish Chopra struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id]; 790cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 79106f56b81SYuval Mintz struct qed_sp_init_data init_data; 792cee4d264SManish Chopra int rc = -EINVAL; 793cee4d264SManish Chopra 79406f56b81SYuval Mintz /* Get SPQ entry */ 79506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 79606f56b81SYuval Mintz init_data.cid = p_tx_cid->cid; 79706f56b81SYuval Mintz init_data.opaque_fid = p_tx_cid->opaque_fid; 79806f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 799cee4d264SManish Chopra 800cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 801cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_STOP, 80206f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 803cee4d264SManish Chopra if (rc) 804cee4d264SManish Chopra return rc; 805cee4d264SManish Chopra 806cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 807cee4d264SManish Chopra if (rc) 808cee4d264SManish Chopra return rc; 809cee4d264SManish Chopra 810cee4d264SManish Chopra return qed_sp_release_queue_cid(p_hwfn, p_tx_cid); 811cee4d264SManish Chopra } 812cee4d264SManish Chopra 813cee4d264SManish Chopra static enum eth_filter_action 814cee4d264SManish Chopra qed_filter_action(enum qed_filter_opcode opcode) 815cee4d264SManish Chopra { 816cee4d264SManish Chopra enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 817cee4d264SManish Chopra 818cee4d264SManish Chopra switch (opcode) { 819cee4d264SManish Chopra case QED_FILTER_ADD: 820cee4d264SManish Chopra action = ETH_FILTER_ACTION_ADD; 821cee4d264SManish Chopra break; 822cee4d264SManish Chopra case QED_FILTER_REMOVE: 823cee4d264SManish Chopra action = ETH_FILTER_ACTION_REMOVE; 824cee4d264SManish Chopra break; 825cee4d264SManish Chopra case QED_FILTER_FLUSH: 826fc48b7a6SYuval Mintz action = ETH_FILTER_ACTION_REMOVE_ALL; 827cee4d264SManish Chopra break; 828cee4d264SManish Chopra default: 829cee4d264SManish Chopra action = MAX_ETH_FILTER_ACTION; 830cee4d264SManish Chopra } 831cee4d264SManish Chopra 832cee4d264SManish Chopra return action; 833cee4d264SManish Chopra } 834cee4d264SManish Chopra 835cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb, 836cee4d264SManish Chopra __le16 *fw_mid, 837cee4d264SManish Chopra __le16 *fw_lsb, 838cee4d264SManish Chopra u8 *mac) 839cee4d264SManish Chopra { 840cee4d264SManish Chopra ((u8 *)fw_msb)[0] = mac[1]; 841cee4d264SManish Chopra ((u8 *)fw_msb)[1] = mac[0]; 842cee4d264SManish Chopra ((u8 *)fw_mid)[0] = mac[3]; 843cee4d264SManish Chopra ((u8 *)fw_mid)[1] = mac[2]; 844cee4d264SManish Chopra ((u8 *)fw_lsb)[0] = mac[5]; 845cee4d264SManish Chopra ((u8 *)fw_lsb)[1] = mac[4]; 846cee4d264SManish Chopra } 847cee4d264SManish Chopra 848cee4d264SManish Chopra static int 849cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 850cee4d264SManish Chopra u16 opaque_fid, 851cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 852cee4d264SManish Chopra struct vport_filter_update_ramrod_data **pp_ramrod, 853cee4d264SManish Chopra struct qed_spq_entry **pp_ent, 854cee4d264SManish Chopra enum spq_mode comp_mode, 855cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 856cee4d264SManish Chopra { 857cee4d264SManish Chopra u8 vport_to_add_to = 0, vport_to_remove_from = 0; 858cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod; 859cee4d264SManish Chopra struct eth_filter_cmd *p_first_filter; 860cee4d264SManish Chopra struct eth_filter_cmd *p_second_filter; 86106f56b81SYuval Mintz struct qed_sp_init_data init_data; 862cee4d264SManish Chopra enum eth_filter_action action; 863cee4d264SManish Chopra int rc; 864cee4d264SManish Chopra 865cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 866cee4d264SManish Chopra &vport_to_remove_from); 867cee4d264SManish Chopra if (rc) 868cee4d264SManish Chopra return rc; 869cee4d264SManish Chopra 870cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 871cee4d264SManish Chopra &vport_to_add_to); 872cee4d264SManish Chopra if (rc) 873cee4d264SManish Chopra return rc; 874cee4d264SManish Chopra 87506f56b81SYuval Mintz /* Get SPQ entry */ 87606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 87706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 87806f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 87906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 88006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 881cee4d264SManish Chopra 882cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, pp_ent, 883cee4d264SManish Chopra ETH_RAMROD_FILTERS_UPDATE, 88406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 885cee4d264SManish Chopra if (rc) 886cee4d264SManish Chopra return rc; 887cee4d264SManish Chopra 888cee4d264SManish Chopra *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 889cee4d264SManish Chopra p_ramrod = *pp_ramrod; 890cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 891cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 892cee4d264SManish Chopra 893cee4d264SManish Chopra switch (p_filter_cmd->opcode) { 894fc48b7a6SYuval Mintz case QED_FILTER_REPLACE: 895cee4d264SManish Chopra case QED_FILTER_MOVE: 896cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 897cee4d264SManish Chopra default: 898cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 899cee4d264SManish Chopra } 900cee4d264SManish Chopra 901cee4d264SManish Chopra p_first_filter = &p_ramrod->filter_cmds[0]; 902cee4d264SManish Chopra p_second_filter = &p_ramrod->filter_cmds[1]; 903cee4d264SManish Chopra 904cee4d264SManish Chopra switch (p_filter_cmd->type) { 905cee4d264SManish Chopra case QED_FILTER_MAC: 906cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 907cee4d264SManish Chopra case QED_FILTER_VLAN: 908cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 909cee4d264SManish Chopra case QED_FILTER_MAC_VLAN: 910cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 911cee4d264SManish Chopra case QED_FILTER_INNER_MAC: 912cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 913cee4d264SManish Chopra case QED_FILTER_INNER_VLAN: 914cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 915cee4d264SManish Chopra case QED_FILTER_INNER_PAIR: 916cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 917cee4d264SManish Chopra case QED_FILTER_INNER_MAC_VNI_PAIR: 918cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 919cee4d264SManish Chopra break; 920cee4d264SManish Chopra case QED_FILTER_MAC_VNI_PAIR: 921cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 922cee4d264SManish Chopra case QED_FILTER_VNI: 923cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 924cee4d264SManish Chopra } 925cee4d264SManish Chopra 926cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 927cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 928cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 929cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 930cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 931cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 932cee4d264SManish Chopra qed_set_fw_mac_addr(&p_first_filter->mac_msb, 933cee4d264SManish Chopra &p_first_filter->mac_mid, 934cee4d264SManish Chopra &p_first_filter->mac_lsb, 935cee4d264SManish Chopra (u8 *)p_filter_cmd->mac); 936cee4d264SManish Chopra } 937cee4d264SManish Chopra 938cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 939cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 940cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 941cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 942cee4d264SManish Chopra p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 943cee4d264SManish Chopra 944cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 945cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 946cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 947cee4d264SManish Chopra p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 948cee4d264SManish Chopra 949cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 950cee4d264SManish Chopra p_second_filter->type = p_first_filter->type; 951cee4d264SManish Chopra p_second_filter->mac_msb = p_first_filter->mac_msb; 952cee4d264SManish Chopra p_second_filter->mac_mid = p_first_filter->mac_mid; 953cee4d264SManish Chopra p_second_filter->mac_lsb = p_first_filter->mac_lsb; 954cee4d264SManish Chopra p_second_filter->vlan_id = p_first_filter->vlan_id; 955cee4d264SManish Chopra p_second_filter->vni = p_first_filter->vni; 956cee4d264SManish Chopra 957cee4d264SManish Chopra p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 958cee4d264SManish Chopra 959cee4d264SManish Chopra p_first_filter->vport_id = vport_to_remove_from; 960cee4d264SManish Chopra 961cee4d264SManish Chopra p_second_filter->action = ETH_FILTER_ACTION_ADD; 962cee4d264SManish Chopra p_second_filter->vport_id = vport_to_add_to; 963fc48b7a6SYuval Mintz } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 964fc48b7a6SYuval Mintz p_first_filter->vport_id = vport_to_add_to; 965fc48b7a6SYuval Mintz memcpy(p_second_filter, p_first_filter, 966fc48b7a6SYuval Mintz sizeof(*p_second_filter)); 967fc48b7a6SYuval Mintz p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 968fc48b7a6SYuval Mintz p_second_filter->action = ETH_FILTER_ACTION_ADD; 969cee4d264SManish Chopra } else { 970cee4d264SManish Chopra action = qed_filter_action(p_filter_cmd->opcode); 971cee4d264SManish Chopra 972cee4d264SManish Chopra if (action == MAX_ETH_FILTER_ACTION) { 973cee4d264SManish Chopra DP_NOTICE(p_hwfn, 974cee4d264SManish Chopra "%d is not supported yet\n", 975cee4d264SManish Chopra p_filter_cmd->opcode); 976cee4d264SManish Chopra return -EINVAL; 977cee4d264SManish Chopra } 978cee4d264SManish Chopra 979cee4d264SManish Chopra p_first_filter->action = action; 980cee4d264SManish Chopra p_first_filter->vport_id = (p_filter_cmd->opcode == 981cee4d264SManish Chopra QED_FILTER_REMOVE) ? 982cee4d264SManish Chopra vport_to_remove_from : 983cee4d264SManish Chopra vport_to_add_to; 984cee4d264SManish Chopra } 985cee4d264SManish Chopra 986cee4d264SManish Chopra return 0; 987cee4d264SManish Chopra } 988cee4d264SManish Chopra 989cee4d264SManish Chopra static int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 990cee4d264SManish Chopra u16 opaque_fid, 991cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 992cee4d264SManish Chopra enum spq_mode comp_mode, 993cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 994cee4d264SManish Chopra { 995cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod = NULL; 996cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 997cee4d264SManish Chopra struct eth_filter_cmd_header *p_header; 998cee4d264SManish Chopra int rc; 999cee4d264SManish Chopra 1000cee4d264SManish Chopra rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1001cee4d264SManish Chopra &p_ramrod, &p_ent, 1002cee4d264SManish Chopra comp_mode, p_comp_data); 1003cee4d264SManish Chopra if (rc != 0) { 1004cee4d264SManish Chopra DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1005cee4d264SManish Chopra return rc; 1006cee4d264SManish Chopra } 1007cee4d264SManish Chopra p_header = &p_ramrod->filter_cmd_hdr; 1008cee4d264SManish Chopra p_header->assert_on_error = p_filter_cmd->assert_on_error; 1009cee4d264SManish Chopra 1010cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 1011cee4d264SManish Chopra if (rc != 0) { 1012cee4d264SManish Chopra DP_ERR(p_hwfn, 1013cee4d264SManish Chopra "Unicast filter ADD command failed %d\n", 1014cee4d264SManish Chopra rc); 1015cee4d264SManish Chopra return rc; 1016cee4d264SManish Chopra } 1017cee4d264SManish Chopra 1018cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1019cee4d264SManish Chopra "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1020cee4d264SManish Chopra (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1021cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1022cee4d264SManish Chopra "REMOVE" : 1023cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1024cee4d264SManish Chopra "MOVE" : "REPLACE")), 1025cee4d264SManish Chopra (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1026cee4d264SManish Chopra ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1027cee4d264SManish Chopra "VLAN" : "MAC & VLAN"), 1028cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt, 1029cee4d264SManish Chopra p_filter_cmd->is_rx_filter, 1030cee4d264SManish Chopra p_filter_cmd->is_tx_filter); 1031cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1032cee4d264SManish Chopra "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1033cee4d264SManish Chopra p_filter_cmd->vport_to_add_to, 1034cee4d264SManish Chopra p_filter_cmd->vport_to_remove_from, 1035cee4d264SManish Chopra p_filter_cmd->mac[0], 1036cee4d264SManish Chopra p_filter_cmd->mac[1], 1037cee4d264SManish Chopra p_filter_cmd->mac[2], 1038cee4d264SManish Chopra p_filter_cmd->mac[3], 1039cee4d264SManish Chopra p_filter_cmd->mac[4], 1040cee4d264SManish Chopra p_filter_cmd->mac[5], 1041cee4d264SManish Chopra p_filter_cmd->vlan); 1042cee4d264SManish Chopra 1043cee4d264SManish Chopra return 0; 1044cee4d264SManish Chopra } 1045cee4d264SManish Chopra 1046cee4d264SManish Chopra /******************************************************************************* 1047cee4d264SManish Chopra * Description: 1048cee4d264SManish Chopra * Calculates crc 32 on a buffer 1049cee4d264SManish Chopra * Note: crc32_length MUST be aligned to 8 1050cee4d264SManish Chopra * Return: 1051cee4d264SManish Chopra ******************************************************************************/ 1052cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet, 1053cee4d264SManish Chopra u32 crc32_length, 1054cee4d264SManish Chopra u32 crc32_seed, 1055cee4d264SManish Chopra u8 complement) 1056cee4d264SManish Chopra { 1057cee4d264SManish Chopra u32 byte = 0; 1058cee4d264SManish Chopra u32 bit = 0; 1059cee4d264SManish Chopra u8 msb = 0; 1060cee4d264SManish Chopra u8 current_byte = 0; 1061cee4d264SManish Chopra u32 crc32_result = crc32_seed; 1062cee4d264SManish Chopra 1063cee4d264SManish Chopra if ((!crc32_packet) || 1064cee4d264SManish Chopra (crc32_length == 0) || 1065cee4d264SManish Chopra ((crc32_length % 8) != 0)) 1066cee4d264SManish Chopra return crc32_result; 1067cee4d264SManish Chopra for (byte = 0; byte < crc32_length; byte++) { 1068cee4d264SManish Chopra current_byte = crc32_packet[byte]; 1069cee4d264SManish Chopra for (bit = 0; bit < 8; bit++) { 1070cee4d264SManish Chopra msb = (u8)(crc32_result >> 31); 1071cee4d264SManish Chopra crc32_result = crc32_result << 1; 1072cee4d264SManish Chopra if (msb != (0x1 & (current_byte >> bit))) { 1073cee4d264SManish Chopra crc32_result = crc32_result ^ CRC32_POLY; 1074cee4d264SManish Chopra crc32_result |= 1; /*crc32_result[0] = 1;*/ 1075cee4d264SManish Chopra } 1076cee4d264SManish Chopra } 1077cee4d264SManish Chopra } 1078cee4d264SManish Chopra return crc32_result; 1079cee4d264SManish Chopra } 1080cee4d264SManish Chopra 1081cee4d264SManish Chopra static inline u32 qed_crc32c_le(u32 seed, 1082cee4d264SManish Chopra u8 *mac, 1083cee4d264SManish Chopra u32 len) 1084cee4d264SManish Chopra { 1085cee4d264SManish Chopra u32 packet_buf[2] = { 0 }; 1086cee4d264SManish Chopra 1087cee4d264SManish Chopra memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1088cee4d264SManish Chopra return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1089cee4d264SManish Chopra } 1090cee4d264SManish Chopra 1091cee4d264SManish Chopra static u8 qed_mcast_bin_from_mac(u8 *mac) 1092cee4d264SManish Chopra { 1093cee4d264SManish Chopra u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1094cee4d264SManish Chopra mac, ETH_ALEN); 1095cee4d264SManish Chopra 1096cee4d264SManish Chopra return crc & 0xff; 1097cee4d264SManish Chopra } 1098cee4d264SManish Chopra 1099cee4d264SManish Chopra static int 1100cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1101cee4d264SManish Chopra u16 opaque_fid, 1102cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1103cee4d264SManish Chopra enum spq_mode comp_mode, 1104cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1105cee4d264SManish Chopra { 1106cee4d264SManish Chopra unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1107cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 1108cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 110906f56b81SYuval Mintz struct qed_sp_init_data init_data; 1110cee4d264SManish Chopra u8 abs_vport_id = 0; 1111cee4d264SManish Chopra int rc, i; 1112cee4d264SManish Chopra 1113cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1114cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1115cee4d264SManish Chopra &abs_vport_id); 1116cee4d264SManish Chopra if (rc) 1117cee4d264SManish Chopra return rc; 1118cee4d264SManish Chopra } else { 1119cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1120cee4d264SManish Chopra &abs_vport_id); 1121cee4d264SManish Chopra if (rc) 1122cee4d264SManish Chopra return rc; 1123cee4d264SManish Chopra } 1124cee4d264SManish Chopra 112506f56b81SYuval Mintz /* Get SPQ entry */ 112606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 112706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 112806f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 112906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 113006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1131cee4d264SManish Chopra 1132cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1133cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 113406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1135cee4d264SManish Chopra if (rc) { 1136cee4d264SManish Chopra DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1137cee4d264SManish Chopra return rc; 1138cee4d264SManish Chopra } 1139cee4d264SManish Chopra 1140cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 1141cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 1142cee4d264SManish Chopra 1143cee4d264SManish Chopra /* explicitly clear out the entire vector */ 1144cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 1145cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 1146cee4d264SManish Chopra memset(bins, 0, sizeof(unsigned long) * 1147cee4d264SManish Chopra ETH_MULTICAST_MAC_BINS_IN_REGS); 1148cee4d264SManish Chopra /* filter ADD op is explicit set op and it removes 1149cee4d264SManish Chopra * any existing filters for the vport 1150cee4d264SManish Chopra */ 1151cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1152cee4d264SManish Chopra for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 1153cee4d264SManish Chopra u32 bit; 1154cee4d264SManish Chopra 1155cee4d264SManish Chopra bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 1156cee4d264SManish Chopra __set_bit(bit, bins); 1157cee4d264SManish Chopra } 1158cee4d264SManish Chopra 1159cee4d264SManish Chopra /* Convert to correct endianity */ 1160cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 1161cee4d264SManish Chopra u32 *p_bins = (u32 *)bins; 1162cee4d264SManish Chopra struct vport_update_ramrod_mcast *approx_mcast; 1163cee4d264SManish Chopra 1164cee4d264SManish Chopra approx_mcast = &p_ramrod->approx_mcast; 1165cee4d264SManish Chopra approx_mcast->bins[i] = cpu_to_le32(p_bins[i]); 1166cee4d264SManish Chopra } 1167cee4d264SManish Chopra } 1168cee4d264SManish Chopra 1169cee4d264SManish Chopra p_ramrod->common.vport_id = abs_vport_id; 1170cee4d264SManish Chopra 1171cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1172cee4d264SManish Chopra } 1173cee4d264SManish Chopra 1174cee4d264SManish Chopra static int 1175cee4d264SManish Chopra qed_filter_mcast_cmd(struct qed_dev *cdev, 1176cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1177cee4d264SManish Chopra enum spq_mode comp_mode, 1178cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1179cee4d264SManish Chopra { 1180cee4d264SManish Chopra int rc = 0; 1181cee4d264SManish Chopra int i; 1182cee4d264SManish Chopra 1183cee4d264SManish Chopra /* only ADD and REMOVE operations are supported for multi-cast */ 1184cee4d264SManish Chopra if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1185cee4d264SManish Chopra (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1186cee4d264SManish Chopra (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1187cee4d264SManish Chopra return -EINVAL; 1188cee4d264SManish Chopra 1189cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1190cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1191cee4d264SManish Chopra 1192cee4d264SManish Chopra u16 opaque_fid; 1193cee4d264SManish Chopra 1194cee4d264SManish Chopra if (rc != 0) 1195cee4d264SManish Chopra break; 1196cee4d264SManish Chopra 1197cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1198cee4d264SManish Chopra 1199cee4d264SManish Chopra rc = qed_sp_eth_filter_mcast(p_hwfn, 1200cee4d264SManish Chopra opaque_fid, 1201cee4d264SManish Chopra p_filter_cmd, 1202cee4d264SManish Chopra comp_mode, 1203cee4d264SManish Chopra p_comp_data); 1204cee4d264SManish Chopra } 1205cee4d264SManish Chopra return rc; 1206cee4d264SManish Chopra } 1207cee4d264SManish Chopra 1208cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1209cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1210cee4d264SManish Chopra enum spq_mode comp_mode, 1211cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1212cee4d264SManish Chopra { 1213cee4d264SManish Chopra int rc = 0; 1214cee4d264SManish Chopra int i; 1215cee4d264SManish Chopra 1216cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1217cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1218cee4d264SManish Chopra u16 opaque_fid; 1219cee4d264SManish Chopra 1220cee4d264SManish Chopra if (rc != 0) 1221cee4d264SManish Chopra break; 1222cee4d264SManish Chopra 1223cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1224cee4d264SManish Chopra 1225cee4d264SManish Chopra rc = qed_sp_eth_filter_ucast(p_hwfn, 1226cee4d264SManish Chopra opaque_fid, 1227cee4d264SManish Chopra p_filter_cmd, 1228cee4d264SManish Chopra comp_mode, 1229cee4d264SManish Chopra p_comp_data); 1230cee4d264SManish Chopra } 1231cee4d264SManish Chopra 1232cee4d264SManish Chopra return rc; 1233cee4d264SManish Chopra } 1234cee4d264SManish Chopra 123586622ee7SYuval Mintz /* Statistics related code */ 123686622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 123786622ee7SYuval Mintz u32 *p_addr, 123886622ee7SYuval Mintz u32 *p_len, 123986622ee7SYuval Mintz u16 statistics_bin) 124086622ee7SYuval Mintz { 124186622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_PSDM_RAM + 124286622ee7SYuval Mintz PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 124386622ee7SYuval Mintz *p_len = sizeof(struct eth_pstorm_per_queue_stat); 124486622ee7SYuval Mintz } 124586622ee7SYuval Mintz 124686622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 124786622ee7SYuval Mintz struct qed_ptt *p_ptt, 124886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 124986622ee7SYuval Mintz u16 statistics_bin) 125086622ee7SYuval Mintz { 125186622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 125286622ee7SYuval Mintz u32 pstats_addr = 0, pstats_len = 0; 125386622ee7SYuval Mintz 125486622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 125586622ee7SYuval Mintz statistics_bin); 125686622ee7SYuval Mintz 125786622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 125886622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &pstats, 125986622ee7SYuval Mintz pstats_addr, pstats_len); 126086622ee7SYuval Mintz 126186622ee7SYuval Mintz p_stats->tx_ucast_bytes += 126286622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_ucast_bytes); 126386622ee7SYuval Mintz p_stats->tx_mcast_bytes += 126486622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_mcast_bytes); 126586622ee7SYuval Mintz p_stats->tx_bcast_bytes += 126686622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_bcast_bytes); 126786622ee7SYuval Mintz p_stats->tx_ucast_pkts += 126886622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_ucast_pkts); 126986622ee7SYuval Mintz p_stats->tx_mcast_pkts += 127086622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_mcast_pkts); 127186622ee7SYuval Mintz p_stats->tx_bcast_pkts += 127286622ee7SYuval Mintz HILO_64_REGPAIR(pstats.sent_bcast_pkts); 127386622ee7SYuval Mintz p_stats->tx_err_drop_pkts += 127486622ee7SYuval Mintz HILO_64_REGPAIR(pstats.error_drop_pkts); 127586622ee7SYuval Mintz } 127686622ee7SYuval Mintz 127786622ee7SYuval Mintz static void __qed_get_vport_tstats_addrlen(struct qed_hwfn *p_hwfn, 127886622ee7SYuval Mintz u32 *p_addr, 127986622ee7SYuval Mintz u32 *p_len) 128086622ee7SYuval Mintz { 128186622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_TSDM_RAM + 128286622ee7SYuval Mintz TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 128386622ee7SYuval Mintz *p_len = sizeof(struct tstorm_per_port_stat); 128486622ee7SYuval Mintz } 128586622ee7SYuval Mintz 128686622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 128786622ee7SYuval Mintz struct qed_ptt *p_ptt, 128886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 128986622ee7SYuval Mintz u16 statistics_bin) 129086622ee7SYuval Mintz { 129186622ee7SYuval Mintz u32 tstats_addr = 0, tstats_len = 0; 129286622ee7SYuval Mintz struct tstorm_per_port_stat tstats; 129386622ee7SYuval Mintz 129486622ee7SYuval Mintz __qed_get_vport_tstats_addrlen(p_hwfn, &tstats_addr, &tstats_len); 129586622ee7SYuval Mintz 129686622ee7SYuval Mintz memset(&tstats, 0, sizeof(tstats)); 129786622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &tstats, 129886622ee7SYuval Mintz tstats_addr, tstats_len); 129986622ee7SYuval Mintz 130086622ee7SYuval Mintz p_stats->mftag_filter_discards += 130186622ee7SYuval Mintz HILO_64_REGPAIR(tstats.mftag_filter_discard); 130286622ee7SYuval Mintz p_stats->mac_filter_discards += 130386622ee7SYuval Mintz HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 130486622ee7SYuval Mintz } 130586622ee7SYuval Mintz 130686622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 130786622ee7SYuval Mintz u32 *p_addr, 130886622ee7SYuval Mintz u32 *p_len, 130986622ee7SYuval Mintz u16 statistics_bin) 131086622ee7SYuval Mintz { 131186622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_USDM_RAM + 131286622ee7SYuval Mintz USTORM_QUEUE_STAT_OFFSET(statistics_bin); 131386622ee7SYuval Mintz *p_len = sizeof(struct eth_ustorm_per_queue_stat); 131486622ee7SYuval Mintz } 131586622ee7SYuval Mintz 131686622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 131786622ee7SYuval Mintz struct qed_ptt *p_ptt, 131886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 131986622ee7SYuval Mintz u16 statistics_bin) 132086622ee7SYuval Mintz { 132186622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 132286622ee7SYuval Mintz u32 ustats_addr = 0, ustats_len = 0; 132386622ee7SYuval Mintz 132486622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 132586622ee7SYuval Mintz statistics_bin); 132686622ee7SYuval Mintz 132786622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 132886622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &ustats, 132986622ee7SYuval Mintz ustats_addr, ustats_len); 133086622ee7SYuval Mintz 133186622ee7SYuval Mintz p_stats->rx_ucast_bytes += 133286622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 133386622ee7SYuval Mintz p_stats->rx_mcast_bytes += 133486622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 133586622ee7SYuval Mintz p_stats->rx_bcast_bytes += 133686622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 133786622ee7SYuval Mintz p_stats->rx_ucast_pkts += 133886622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 133986622ee7SYuval Mintz p_stats->rx_mcast_pkts += 134086622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 134186622ee7SYuval Mintz p_stats->rx_bcast_pkts += 134286622ee7SYuval Mintz HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 134386622ee7SYuval Mintz } 134486622ee7SYuval Mintz 134586622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 134686622ee7SYuval Mintz u32 *p_addr, 134786622ee7SYuval Mintz u32 *p_len, 134886622ee7SYuval Mintz u16 statistics_bin) 134986622ee7SYuval Mintz { 135086622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_MSDM_RAM + 135186622ee7SYuval Mintz MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 135286622ee7SYuval Mintz *p_len = sizeof(struct eth_mstorm_per_queue_stat); 135386622ee7SYuval Mintz } 135486622ee7SYuval Mintz 135586622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 135686622ee7SYuval Mintz struct qed_ptt *p_ptt, 135786622ee7SYuval Mintz struct qed_eth_stats *p_stats, 135886622ee7SYuval Mintz u16 statistics_bin) 135986622ee7SYuval Mintz { 136086622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 136186622ee7SYuval Mintz u32 mstats_addr = 0, mstats_len = 0; 136286622ee7SYuval Mintz 136386622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 136486622ee7SYuval Mintz statistics_bin); 136586622ee7SYuval Mintz 136686622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 136786622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &mstats, 136886622ee7SYuval Mintz mstats_addr, mstats_len); 136986622ee7SYuval Mintz 137086622ee7SYuval Mintz p_stats->no_buff_discards += 137186622ee7SYuval Mintz HILO_64_REGPAIR(mstats.no_buff_discard); 137286622ee7SYuval Mintz p_stats->packet_too_big_discard += 137386622ee7SYuval Mintz HILO_64_REGPAIR(mstats.packet_too_big_discard); 137486622ee7SYuval Mintz p_stats->ttl0_discard += 137586622ee7SYuval Mintz HILO_64_REGPAIR(mstats.ttl0_discard); 137686622ee7SYuval Mintz p_stats->tpa_coalesced_pkts += 137786622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 137886622ee7SYuval Mintz p_stats->tpa_coalesced_events += 137986622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_events); 138086622ee7SYuval Mintz p_stats->tpa_aborts_num += 138186622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_aborts_num); 138286622ee7SYuval Mintz p_stats->tpa_coalesced_bytes += 138386622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 138486622ee7SYuval Mintz } 138586622ee7SYuval Mintz 138686622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 138786622ee7SYuval Mintz struct qed_ptt *p_ptt, 138886622ee7SYuval Mintz struct qed_eth_stats *p_stats) 138986622ee7SYuval Mintz { 139086622ee7SYuval Mintz struct port_stats port_stats; 139186622ee7SYuval Mintz int j; 139286622ee7SYuval Mintz 139386622ee7SYuval Mintz memset(&port_stats, 0, sizeof(port_stats)); 139486622ee7SYuval Mintz 139586622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 139686622ee7SYuval Mintz p_hwfn->mcp_info->port_addr + 139786622ee7SYuval Mintz offsetof(struct public_port, stats), 139886622ee7SYuval Mintz sizeof(port_stats)); 139986622ee7SYuval Mintz 140086622ee7SYuval Mintz p_stats->rx_64_byte_packets += port_stats.pmm.r64; 140186622ee7SYuval Mintz p_stats->rx_127_byte_packets += port_stats.pmm.r127; 140286622ee7SYuval Mintz p_stats->rx_255_byte_packets += port_stats.pmm.r255; 140386622ee7SYuval Mintz p_stats->rx_511_byte_packets += port_stats.pmm.r511; 140486622ee7SYuval Mintz p_stats->rx_1023_byte_packets += port_stats.pmm.r1023; 140586622ee7SYuval Mintz p_stats->rx_1518_byte_packets += port_stats.pmm.r1518; 140686622ee7SYuval Mintz p_stats->rx_1522_byte_packets += port_stats.pmm.r1522; 140786622ee7SYuval Mintz p_stats->rx_2047_byte_packets += port_stats.pmm.r2047; 140886622ee7SYuval Mintz p_stats->rx_4095_byte_packets += port_stats.pmm.r4095; 140986622ee7SYuval Mintz p_stats->rx_9216_byte_packets += port_stats.pmm.r9216; 141086622ee7SYuval Mintz p_stats->rx_16383_byte_packets += port_stats.pmm.r16383; 141186622ee7SYuval Mintz p_stats->rx_crc_errors += port_stats.pmm.rfcs; 141286622ee7SYuval Mintz p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf; 141386622ee7SYuval Mintz p_stats->rx_pause_frames += port_stats.pmm.rxpf; 141486622ee7SYuval Mintz p_stats->rx_pfc_frames += port_stats.pmm.rxpp; 141586622ee7SYuval Mintz p_stats->rx_align_errors += port_stats.pmm.raln; 141686622ee7SYuval Mintz p_stats->rx_carrier_errors += port_stats.pmm.rfcr; 141786622ee7SYuval Mintz p_stats->rx_oversize_packets += port_stats.pmm.rovr; 141886622ee7SYuval Mintz p_stats->rx_jabbers += port_stats.pmm.rjbr; 141986622ee7SYuval Mintz p_stats->rx_undersize_packets += port_stats.pmm.rund; 142086622ee7SYuval Mintz p_stats->rx_fragments += port_stats.pmm.rfrg; 142186622ee7SYuval Mintz p_stats->tx_64_byte_packets += port_stats.pmm.t64; 142286622ee7SYuval Mintz p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127; 142386622ee7SYuval Mintz p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255; 142486622ee7SYuval Mintz p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511; 142586622ee7SYuval Mintz p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023; 142686622ee7SYuval Mintz p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518; 142786622ee7SYuval Mintz p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047; 142886622ee7SYuval Mintz p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095; 142986622ee7SYuval Mintz p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216; 143086622ee7SYuval Mintz p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383; 143186622ee7SYuval Mintz p_stats->tx_pause_frames += port_stats.pmm.txpf; 143286622ee7SYuval Mintz p_stats->tx_pfc_frames += port_stats.pmm.txpp; 143386622ee7SYuval Mintz p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec; 143486622ee7SYuval Mintz p_stats->tx_total_collisions += port_stats.pmm.tncl; 143586622ee7SYuval Mintz p_stats->rx_mac_bytes += port_stats.pmm.rbyte; 143686622ee7SYuval Mintz p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca; 143786622ee7SYuval Mintz p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca; 143886622ee7SYuval Mintz p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca; 143986622ee7SYuval Mintz p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok; 144086622ee7SYuval Mintz p_stats->tx_mac_bytes += port_stats.pmm.tbyte; 144186622ee7SYuval Mintz p_stats->tx_mac_uc_packets += port_stats.pmm.txuca; 144286622ee7SYuval Mintz p_stats->tx_mac_mc_packets += port_stats.pmm.txmca; 144386622ee7SYuval Mintz p_stats->tx_mac_bc_packets += port_stats.pmm.txbca; 144486622ee7SYuval Mintz p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf; 144586622ee7SYuval Mintz for (j = 0; j < 8; j++) { 144686622ee7SYuval Mintz p_stats->brb_truncates += port_stats.brb.brb_truncate[j]; 144786622ee7SYuval Mintz p_stats->brb_discards += port_stats.brb.brb_discard[j]; 144886622ee7SYuval Mintz } 144986622ee7SYuval Mintz } 145086622ee7SYuval Mintz 145186622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 145286622ee7SYuval Mintz struct qed_ptt *p_ptt, 145386622ee7SYuval Mintz struct qed_eth_stats *stats, 145486622ee7SYuval Mintz u16 statistics_bin) 145586622ee7SYuval Mintz { 145686622ee7SYuval Mintz __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 145786622ee7SYuval Mintz __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 145886622ee7SYuval Mintz __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 145986622ee7SYuval Mintz __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 146086622ee7SYuval Mintz 146186622ee7SYuval Mintz if (p_hwfn->mcp_info) 146286622ee7SYuval Mintz __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 146386622ee7SYuval Mintz } 146486622ee7SYuval Mintz 146586622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev, 146686622ee7SYuval Mintz struct qed_eth_stats *stats) 146786622ee7SYuval Mintz { 146886622ee7SYuval Mintz u8 fw_vport = 0; 146986622ee7SYuval Mintz int i; 147086622ee7SYuval Mintz 147186622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 147286622ee7SYuval Mintz 147386622ee7SYuval Mintz for_each_hwfn(cdev, i) { 147486622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 147586622ee7SYuval Mintz struct qed_ptt *p_ptt; 147686622ee7SYuval Mintz 147786622ee7SYuval Mintz /* The main vport index is relative first */ 147886622ee7SYuval Mintz if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 147986622ee7SYuval Mintz DP_ERR(p_hwfn, "No vport available!\n"); 148086622ee7SYuval Mintz continue; 148186622ee7SYuval Mintz } 148286622ee7SYuval Mintz 148386622ee7SYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 148486622ee7SYuval Mintz if (!p_ptt) { 148586622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 148686622ee7SYuval Mintz continue; 148786622ee7SYuval Mintz } 148886622ee7SYuval Mintz 148986622ee7SYuval Mintz __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport); 149086622ee7SYuval Mintz 149186622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 149286622ee7SYuval Mintz } 149386622ee7SYuval Mintz } 149486622ee7SYuval Mintz 149586622ee7SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, 149686622ee7SYuval Mintz struct qed_eth_stats *stats) 149786622ee7SYuval Mintz { 149886622ee7SYuval Mintz u32 i; 149986622ee7SYuval Mintz 150086622ee7SYuval Mintz if (!cdev) { 150186622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 150286622ee7SYuval Mintz return; 150386622ee7SYuval Mintz } 150486622ee7SYuval Mintz 150586622ee7SYuval Mintz _qed_get_vport_stats(cdev, stats); 150686622ee7SYuval Mintz 150786622ee7SYuval Mintz if (!cdev->reset_stats) 150886622ee7SYuval Mintz return; 150986622ee7SYuval Mintz 151086622ee7SYuval Mintz /* Reduce the statistics baseline */ 151186622ee7SYuval Mintz for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 151286622ee7SYuval Mintz ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 151386622ee7SYuval Mintz } 151486622ee7SYuval Mintz 151586622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 151686622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev) 151786622ee7SYuval Mintz { 151886622ee7SYuval Mintz int i; 151986622ee7SYuval Mintz 152086622ee7SYuval Mintz for_each_hwfn(cdev, i) { 152186622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 152286622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 152386622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 152486622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 152586622ee7SYuval Mintz struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 152686622ee7SYuval Mintz u32 addr = 0, len = 0; 152786622ee7SYuval Mintz 152886622ee7SYuval Mintz if (!p_ptt) { 152986622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 153086622ee7SYuval Mintz continue; 153186622ee7SYuval Mintz } 153286622ee7SYuval Mintz 153386622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 153486622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 153586622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 153686622ee7SYuval Mintz 153786622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 153886622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 153986622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 154086622ee7SYuval Mintz 154186622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 154286622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 154386622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 154486622ee7SYuval Mintz 154586622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 154686622ee7SYuval Mintz } 154786622ee7SYuval Mintz 154886622ee7SYuval Mintz /* PORT statistics are not necessarily reset, so we need to 154986622ee7SYuval Mintz * read and create a baseline for future statistics. 155086622ee7SYuval Mintz */ 155186622ee7SYuval Mintz if (!cdev->reset_stats) 155286622ee7SYuval Mintz DP_INFO(cdev, "Reset stats not allocated\n"); 155386622ee7SYuval Mintz else 155486622ee7SYuval Mintz _qed_get_vport_stats(cdev, cdev->reset_stats); 155586622ee7SYuval Mintz } 155686622ee7SYuval Mintz 155725c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev, 155825c089d7SYuval Mintz struct qed_dev_eth_info *info) 155925c089d7SYuval Mintz { 156025c089d7SYuval Mintz int i; 156125c089d7SYuval Mintz 156225c089d7SYuval Mintz memset(info, 0, sizeof(*info)); 156325c089d7SYuval Mintz 156425c089d7SYuval Mintz info->num_tc = 1; 156525c089d7SYuval Mintz 156625c089d7SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 156725c089d7SYuval Mintz for_each_hwfn(cdev, i) 156825c089d7SYuval Mintz info->num_queues += FEAT_NUM(&cdev->hwfns[i], 156925c089d7SYuval Mintz QED_PF_L2_QUE); 157025c089d7SYuval Mintz if (cdev->int_params.fp_msix_cnt) 157125c089d7SYuval Mintz info->num_queues = min_t(u8, info->num_queues, 157225c089d7SYuval Mintz cdev->int_params.fp_msix_cnt); 157325c089d7SYuval Mintz } else { 157425c089d7SYuval Mintz info->num_queues = cdev->num_hwfns; 157525c089d7SYuval Mintz } 157625c089d7SYuval Mintz 157725c089d7SYuval Mintz info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN); 157825c089d7SYuval Mintz ether_addr_copy(info->port_mac, 157925c089d7SYuval Mintz cdev->hwfns[0].hw_info.hw_mac_addr); 158025c089d7SYuval Mintz 158125c089d7SYuval Mintz qed_fill_dev_info(cdev, &info->common); 158225c089d7SYuval Mintz 158325c089d7SYuval Mintz return 0; 158425c089d7SYuval Mintz } 158525c089d7SYuval Mintz 1586cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev, 1587cc875c2eSYuval Mintz struct qed_eth_cb_ops *ops, 1588cc875c2eSYuval Mintz void *cookie) 1589cc875c2eSYuval Mintz { 1590cc875c2eSYuval Mintz cdev->protocol_ops.eth = ops; 1591cc875c2eSYuval Mintz cdev->ops_cookie = cookie; 1592cc875c2eSYuval Mintz } 1593cc875c2eSYuval Mintz 1594cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev, 1595cee4d264SManish Chopra u8 vport_id, 1596cee4d264SManish Chopra u16 mtu, 1597cee4d264SManish Chopra u8 drop_ttl0_flg, 1598cee4d264SManish Chopra u8 inner_vlan_removal_en_flg) 1599cee4d264SManish Chopra { 1600cee4d264SManish Chopra int rc, i; 1601cee4d264SManish Chopra 1602cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1603cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1604cee4d264SManish Chopra 1605cee4d264SManish Chopra rc = qed_sp_vport_start(p_hwfn, 1606cee4d264SManish Chopra p_hwfn->hw_info.concrete_fid, 1607cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 1608cee4d264SManish Chopra vport_id, 1609cee4d264SManish Chopra mtu, 1610cee4d264SManish Chopra drop_ttl0_flg, 1611cee4d264SManish Chopra inner_vlan_removal_en_flg); 1612cee4d264SManish Chopra 1613cee4d264SManish Chopra if (rc) { 1614cee4d264SManish Chopra DP_ERR(cdev, "Failed to start VPORT\n"); 1615cee4d264SManish Chopra return rc; 1616cee4d264SManish Chopra } 1617cee4d264SManish Chopra 1618cee4d264SManish Chopra qed_hw_start_fastpath(p_hwfn); 1619cee4d264SManish Chopra 1620cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1621cee4d264SManish Chopra "Started V-PORT %d with MTU %d\n", 1622cee4d264SManish Chopra vport_id, mtu); 1623cee4d264SManish Chopra } 1624cee4d264SManish Chopra 16259df2ed04SManish Chopra qed_reset_vport_stats(cdev); 16269df2ed04SManish Chopra 1627cee4d264SManish Chopra return 0; 1628cee4d264SManish Chopra } 1629cee4d264SManish Chopra 1630cee4d264SManish Chopra static int qed_stop_vport(struct qed_dev *cdev, 1631cee4d264SManish Chopra u8 vport_id) 1632cee4d264SManish Chopra { 1633cee4d264SManish Chopra int rc, i; 1634cee4d264SManish Chopra 1635cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1636cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1637cee4d264SManish Chopra 1638cee4d264SManish Chopra rc = qed_sp_vport_stop(p_hwfn, 1639cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 1640cee4d264SManish Chopra vport_id); 1641cee4d264SManish Chopra 1642cee4d264SManish Chopra if (rc) { 1643cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop VPORT\n"); 1644cee4d264SManish Chopra return rc; 1645cee4d264SManish Chopra } 1646cee4d264SManish Chopra } 1647cee4d264SManish Chopra return 0; 1648cee4d264SManish Chopra } 1649cee4d264SManish Chopra 1650cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev, 1651cee4d264SManish Chopra struct qed_update_vport_params *params) 1652cee4d264SManish Chopra { 1653cee4d264SManish Chopra struct qed_sp_vport_update_params sp_params; 1654cee4d264SManish Chopra struct qed_rss_params sp_rss_params; 1655cee4d264SManish Chopra int rc, i; 1656cee4d264SManish Chopra 1657cee4d264SManish Chopra if (!cdev) 1658cee4d264SManish Chopra return -ENODEV; 1659cee4d264SManish Chopra 1660cee4d264SManish Chopra memset(&sp_params, 0, sizeof(sp_params)); 1661cee4d264SManish Chopra memset(&sp_rss_params, 0, sizeof(sp_rss_params)); 1662cee4d264SManish Chopra 1663cee4d264SManish Chopra /* Translate protocol params into sp params */ 1664cee4d264SManish Chopra sp_params.vport_id = params->vport_id; 1665cee4d264SManish Chopra sp_params.update_vport_active_rx_flg = 1666cee4d264SManish Chopra params->update_vport_active_flg; 1667cee4d264SManish Chopra sp_params.update_vport_active_tx_flg = 1668cee4d264SManish Chopra params->update_vport_active_flg; 1669cee4d264SManish Chopra sp_params.vport_active_rx_flg = params->vport_active_flg; 1670cee4d264SManish Chopra sp_params.vport_active_tx_flg = params->vport_active_flg; 16713f9b4a69SYuval Mintz sp_params.accept_any_vlan = params->accept_any_vlan; 16723f9b4a69SYuval Mintz sp_params.update_accept_any_vlan_flg = 16733f9b4a69SYuval Mintz params->update_accept_any_vlan_flg; 1674cee4d264SManish Chopra 1675cee4d264SManish Chopra /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns. 1676cee4d264SManish Chopra * We need to re-fix the rss values per engine for CMT. 1677cee4d264SManish Chopra */ 1678cee4d264SManish Chopra if (cdev->num_hwfns > 1 && params->update_rss_flg) { 1679cee4d264SManish Chopra struct qed_update_vport_rss_params *rss = 1680cee4d264SManish Chopra ¶ms->rss_params; 1681cee4d264SManish Chopra int k, max = 0; 1682cee4d264SManish Chopra 1683cee4d264SManish Chopra /* Find largest entry, since it's possible RSS needs to 1684cee4d264SManish Chopra * be disabled [in case only 1 queue per-hwfn] 1685cee4d264SManish Chopra */ 1686cee4d264SManish Chopra for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1687cee4d264SManish Chopra max = (max > rss->rss_ind_table[k]) ? 1688cee4d264SManish Chopra max : rss->rss_ind_table[k]; 1689cee4d264SManish Chopra 1690cee4d264SManish Chopra /* Either fix RSS values or disable RSS */ 1691cee4d264SManish Chopra if (cdev->num_hwfns < max + 1) { 1692cee4d264SManish Chopra int divisor = (max + cdev->num_hwfns - 1) / 1693cee4d264SManish Chopra cdev->num_hwfns; 1694cee4d264SManish Chopra 1695cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1696cee4d264SManish Chopra "CMT - fixing RSS values (modulo %02x)\n", 1697cee4d264SManish Chopra divisor); 1698cee4d264SManish Chopra 1699cee4d264SManish Chopra for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) 1700cee4d264SManish Chopra rss->rss_ind_table[k] = 1701cee4d264SManish Chopra rss->rss_ind_table[k] % divisor; 1702cee4d264SManish Chopra } else { 1703cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1704cee4d264SManish Chopra "CMT - 1 queue per-hwfn; Disabling RSS\n"); 1705cee4d264SManish Chopra params->update_rss_flg = 0; 1706cee4d264SManish Chopra } 1707cee4d264SManish Chopra } 1708cee4d264SManish Chopra 1709cee4d264SManish Chopra /* Now, update the RSS configuration for actual configuration */ 1710cee4d264SManish Chopra if (params->update_rss_flg) { 1711cee4d264SManish Chopra sp_rss_params.update_rss_config = 1; 1712cee4d264SManish Chopra sp_rss_params.rss_enable = 1; 1713cee4d264SManish Chopra sp_rss_params.update_rss_capabilities = 1; 1714cee4d264SManish Chopra sp_rss_params.update_rss_ind_table = 1; 1715cee4d264SManish Chopra sp_rss_params.update_rss_key = 1; 1716cee4d264SManish Chopra sp_rss_params.rss_caps = QED_RSS_IPV4 | 1717cee4d264SManish Chopra QED_RSS_IPV6 | 1718cee4d264SManish Chopra QED_RSS_IPV4_TCP | QED_RSS_IPV6_TCP; 1719cee4d264SManish Chopra sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */ 1720cee4d264SManish Chopra memcpy(sp_rss_params.rss_ind_table, 1721cee4d264SManish Chopra params->rss_params.rss_ind_table, 1722cee4d264SManish Chopra QED_RSS_IND_TABLE_SIZE * sizeof(u16)); 1723cee4d264SManish Chopra memcpy(sp_rss_params.rss_key, params->rss_params.rss_key, 1724cee4d264SManish Chopra QED_RSS_KEY_SIZE * sizeof(u32)); 1725cee4d264SManish Chopra } 1726cee4d264SManish Chopra sp_params.rss_params = &sp_rss_params; 1727cee4d264SManish Chopra 1728cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1729cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1730cee4d264SManish Chopra 1731cee4d264SManish Chopra sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1732cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &sp_params, 1733cee4d264SManish Chopra QED_SPQ_MODE_EBLOCK, 1734cee4d264SManish Chopra NULL); 1735cee4d264SManish Chopra if (rc) { 1736cee4d264SManish Chopra DP_ERR(cdev, "Failed to update VPORT\n"); 1737cee4d264SManish Chopra return rc; 1738cee4d264SManish Chopra } 1739cee4d264SManish Chopra 1740cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1741cee4d264SManish Chopra "Updated V-PORT %d: active_flag %d [update %d]\n", 1742cee4d264SManish Chopra params->vport_id, params->vport_active_flg, 1743cee4d264SManish Chopra params->update_vport_active_flg); 1744cee4d264SManish Chopra } 1745cee4d264SManish Chopra 1746cee4d264SManish Chopra return 0; 1747cee4d264SManish Chopra } 1748cee4d264SManish Chopra 1749cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev, 1750cee4d264SManish Chopra struct qed_queue_start_common_params *params, 1751cee4d264SManish Chopra u16 bd_max_bytes, 1752cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 1753cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 1754cee4d264SManish Chopra u16 cqe_pbl_size, 1755cee4d264SManish Chopra void __iomem **pp_prod) 1756cee4d264SManish Chopra { 1757cee4d264SManish Chopra int rc, hwfn_index; 1758cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1759cee4d264SManish Chopra 1760cee4d264SManish Chopra hwfn_index = params->rss_id % cdev->num_hwfns; 1761cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1762cee4d264SManish Chopra 1763cee4d264SManish Chopra /* Fix queue ID in 100g mode */ 1764cee4d264SManish Chopra params->queue_id /= cdev->num_hwfns; 1765cee4d264SManish Chopra 1766cee4d264SManish Chopra rc = qed_sp_eth_rx_queue_start(p_hwfn, 1767cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 1768cee4d264SManish Chopra params, 1769cee4d264SManish Chopra bd_max_bytes, 1770cee4d264SManish Chopra bd_chain_phys_addr, 1771cee4d264SManish Chopra cqe_pbl_addr, 1772cee4d264SManish Chopra cqe_pbl_size, 1773cee4d264SManish Chopra pp_prod); 1774cee4d264SManish Chopra 1775cee4d264SManish Chopra if (rc) { 1776cee4d264SManish Chopra DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id); 1777cee4d264SManish Chopra return rc; 1778cee4d264SManish Chopra } 1779cee4d264SManish Chopra 1780cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1781cee4d264SManish Chopra "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1782cee4d264SManish Chopra params->queue_id, params->rss_id, params->vport_id, 1783cee4d264SManish Chopra params->sb); 1784cee4d264SManish Chopra 1785cee4d264SManish Chopra return 0; 1786cee4d264SManish Chopra } 1787cee4d264SManish Chopra 1788cee4d264SManish Chopra static int qed_stop_rxq(struct qed_dev *cdev, 1789cee4d264SManish Chopra struct qed_stop_rxq_params *params) 1790cee4d264SManish Chopra { 1791cee4d264SManish Chopra int rc, hwfn_index; 1792cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1793cee4d264SManish Chopra 1794cee4d264SManish Chopra hwfn_index = params->rss_id % cdev->num_hwfns; 1795cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1796cee4d264SManish Chopra 1797cee4d264SManish Chopra rc = qed_sp_eth_rx_queue_stop(p_hwfn, 1798cee4d264SManish Chopra params->rx_queue_id / cdev->num_hwfns, 1799cee4d264SManish Chopra params->eq_completion_only, 1800cee4d264SManish Chopra false); 1801cee4d264SManish Chopra if (rc) { 1802cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id); 1803cee4d264SManish Chopra return rc; 1804cee4d264SManish Chopra } 1805cee4d264SManish Chopra 1806cee4d264SManish Chopra return 0; 1807cee4d264SManish Chopra } 1808cee4d264SManish Chopra 1809cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev, 1810cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 1811cee4d264SManish Chopra dma_addr_t pbl_addr, 1812cee4d264SManish Chopra u16 pbl_size, 1813cee4d264SManish Chopra void __iomem **pp_doorbell) 1814cee4d264SManish Chopra { 1815cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1816cee4d264SManish Chopra int rc, hwfn_index; 1817cee4d264SManish Chopra 1818cee4d264SManish Chopra hwfn_index = p_params->rss_id % cdev->num_hwfns; 1819cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1820cee4d264SManish Chopra 1821cee4d264SManish Chopra /* Fix queue ID in 100g mode */ 1822cee4d264SManish Chopra p_params->queue_id /= cdev->num_hwfns; 1823cee4d264SManish Chopra 1824cee4d264SManish Chopra rc = qed_sp_eth_tx_queue_start(p_hwfn, 1825cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 1826cee4d264SManish Chopra p_params, 1827cee4d264SManish Chopra pbl_addr, 1828cee4d264SManish Chopra pbl_size, 1829cee4d264SManish Chopra pp_doorbell); 1830cee4d264SManish Chopra 1831cee4d264SManish Chopra if (rc) { 1832cee4d264SManish Chopra DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 1833cee4d264SManish Chopra return rc; 1834cee4d264SManish Chopra } 1835cee4d264SManish Chopra 1836cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 1837cee4d264SManish Chopra "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n", 1838cee4d264SManish Chopra p_params->queue_id, p_params->rss_id, p_params->vport_id, 1839cee4d264SManish Chopra p_params->sb); 1840cee4d264SManish Chopra 1841cee4d264SManish Chopra return 0; 1842cee4d264SManish Chopra } 1843cee4d264SManish Chopra 1844cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10) 1845cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev) 1846cee4d264SManish Chopra { 1847cee4d264SManish Chopra qed_hw_stop_fastpath(cdev); 1848cee4d264SManish Chopra 1849cee4d264SManish Chopra return 0; 1850cee4d264SManish Chopra } 1851cee4d264SManish Chopra 1852cee4d264SManish Chopra static int qed_stop_txq(struct qed_dev *cdev, 1853cee4d264SManish Chopra struct qed_stop_txq_params *params) 1854cee4d264SManish Chopra { 1855cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 1856cee4d264SManish Chopra int rc, hwfn_index; 1857cee4d264SManish Chopra 1858cee4d264SManish Chopra hwfn_index = params->rss_id % cdev->num_hwfns; 1859cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 1860cee4d264SManish Chopra 1861cee4d264SManish Chopra rc = qed_sp_eth_tx_queue_stop(p_hwfn, 1862cee4d264SManish Chopra params->tx_queue_id / cdev->num_hwfns); 1863cee4d264SManish Chopra if (rc) { 1864cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id); 1865cee4d264SManish Chopra return rc; 1866cee4d264SManish Chopra } 1867cee4d264SManish Chopra 1868cee4d264SManish Chopra return 0; 1869cee4d264SManish Chopra } 1870cee4d264SManish Chopra 1871cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 1872cee4d264SManish Chopra enum qed_filter_rx_mode_type type) 1873cee4d264SManish Chopra { 1874cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 1875cee4d264SManish Chopra 1876cee4d264SManish Chopra memset(&accept_flags, 0, sizeof(accept_flags)); 1877cee4d264SManish Chopra 1878cee4d264SManish Chopra accept_flags.update_rx_mode_config = 1; 1879cee4d264SManish Chopra accept_flags.update_tx_mode_config = 1; 1880cee4d264SManish Chopra accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 1881cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 1882cee4d264SManish Chopra QED_ACCEPT_BCAST; 1883cee4d264SManish Chopra accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 1884cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 1885cee4d264SManish Chopra QED_ACCEPT_BCAST; 1886cee4d264SManish Chopra 1887cee4d264SManish Chopra if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) 1888cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 1889cee4d264SManish Chopra QED_ACCEPT_MCAST_UNMATCHED; 1890cee4d264SManish Chopra else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) 1891cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 1892cee4d264SManish Chopra 18933f9b4a69SYuval Mintz return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 1894cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 1895cee4d264SManish Chopra } 1896cee4d264SManish Chopra 1897cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev, 1898cee4d264SManish Chopra struct qed_filter_ucast_params *params) 1899cee4d264SManish Chopra { 1900cee4d264SManish Chopra struct qed_filter_ucast ucast; 1901cee4d264SManish Chopra 1902cee4d264SManish Chopra if (!params->vlan_valid && !params->mac_valid) { 1903cee4d264SManish Chopra DP_NOTICE( 1904cee4d264SManish Chopra cdev, 1905cee4d264SManish Chopra "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 1906cee4d264SManish Chopra return -EINVAL; 1907cee4d264SManish Chopra } 1908cee4d264SManish Chopra 1909cee4d264SManish Chopra memset(&ucast, 0, sizeof(ucast)); 1910cee4d264SManish Chopra switch (params->type) { 1911cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 1912cee4d264SManish Chopra ucast.opcode = QED_FILTER_ADD; 1913cee4d264SManish Chopra break; 1914cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 1915cee4d264SManish Chopra ucast.opcode = QED_FILTER_REMOVE; 1916cee4d264SManish Chopra break; 1917cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_REPLACE: 1918cee4d264SManish Chopra ucast.opcode = QED_FILTER_REPLACE; 1919cee4d264SManish Chopra break; 1920cee4d264SManish Chopra default: 1921cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 1922cee4d264SManish Chopra params->type); 1923cee4d264SManish Chopra } 1924cee4d264SManish Chopra 1925cee4d264SManish Chopra if (params->vlan_valid && params->mac_valid) { 1926cee4d264SManish Chopra ucast.type = QED_FILTER_MAC_VLAN; 1927cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 1928cee4d264SManish Chopra ucast.vlan = params->vlan; 1929cee4d264SManish Chopra } else if (params->mac_valid) { 1930cee4d264SManish Chopra ucast.type = QED_FILTER_MAC; 1931cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 1932cee4d264SManish Chopra } else { 1933cee4d264SManish Chopra ucast.type = QED_FILTER_VLAN; 1934cee4d264SManish Chopra ucast.vlan = params->vlan; 1935cee4d264SManish Chopra } 1936cee4d264SManish Chopra 1937cee4d264SManish Chopra ucast.is_rx_filter = true; 1938cee4d264SManish Chopra ucast.is_tx_filter = true; 1939cee4d264SManish Chopra 1940cee4d264SManish Chopra return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 1941cee4d264SManish Chopra } 1942cee4d264SManish Chopra 1943cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev, 1944cee4d264SManish Chopra struct qed_filter_mcast_params *params) 1945cee4d264SManish Chopra { 1946cee4d264SManish Chopra struct qed_filter_mcast mcast; 1947cee4d264SManish Chopra int i; 1948cee4d264SManish Chopra 1949cee4d264SManish Chopra memset(&mcast, 0, sizeof(mcast)); 1950cee4d264SManish Chopra switch (params->type) { 1951cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 1952cee4d264SManish Chopra mcast.opcode = QED_FILTER_ADD; 1953cee4d264SManish Chopra break; 1954cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 1955cee4d264SManish Chopra mcast.opcode = QED_FILTER_REMOVE; 1956cee4d264SManish Chopra break; 1957cee4d264SManish Chopra default: 1958cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 1959cee4d264SManish Chopra params->type); 1960cee4d264SManish Chopra } 1961cee4d264SManish Chopra 1962cee4d264SManish Chopra mcast.num_mc_addrs = params->num; 1963cee4d264SManish Chopra for (i = 0; i < mcast.num_mc_addrs; i++) 1964cee4d264SManish Chopra ether_addr_copy(mcast.mac[i], params->mac[i]); 1965cee4d264SManish Chopra 1966cee4d264SManish Chopra return qed_filter_mcast_cmd(cdev, &mcast, 1967cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 1968cee4d264SManish Chopra } 1969cee4d264SManish Chopra 1970cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev, 1971cee4d264SManish Chopra struct qed_filter_params *params) 1972cee4d264SManish Chopra { 1973cee4d264SManish Chopra enum qed_filter_rx_mode_type accept_flags; 1974cee4d264SManish Chopra 1975cee4d264SManish Chopra switch (params->type) { 1976cee4d264SManish Chopra case QED_FILTER_TYPE_UCAST: 1977cee4d264SManish Chopra return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 1978cee4d264SManish Chopra case QED_FILTER_TYPE_MCAST: 1979cee4d264SManish Chopra return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 1980cee4d264SManish Chopra case QED_FILTER_TYPE_RX_MODE: 1981cee4d264SManish Chopra accept_flags = params->filter.accept_flags; 1982cee4d264SManish Chopra return qed_configure_filter_rx_mode(cdev, accept_flags); 1983cee4d264SManish Chopra default: 1984cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown filter type %d\n", 1985cee4d264SManish Chopra (int)params->type); 1986cee4d264SManish Chopra return -EINVAL; 1987cee4d264SManish Chopra } 1988cee4d264SManish Chopra } 1989cee4d264SManish Chopra 1990cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev, 1991cee4d264SManish Chopra u8 rss_id, 1992cee4d264SManish Chopra struct eth_slow_path_rx_cqe *cqe) 1993cee4d264SManish Chopra { 1994cee4d264SManish Chopra return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 1995cee4d264SManish Chopra cqe); 1996cee4d264SManish Chopra } 1997cee4d264SManish Chopra 199825c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = { 199925c089d7SYuval Mintz .common = &qed_common_ops_pass, 200025c089d7SYuval Mintz .fill_dev_info = &qed_fill_eth_dev_info, 2001cc875c2eSYuval Mintz .register_ops = &qed_register_eth_ops, 2002cee4d264SManish Chopra .vport_start = &qed_start_vport, 2003cee4d264SManish Chopra .vport_stop = &qed_stop_vport, 2004cee4d264SManish Chopra .vport_update = &qed_update_vport, 2005cee4d264SManish Chopra .q_rx_start = &qed_start_rxq, 2006cee4d264SManish Chopra .q_rx_stop = &qed_stop_rxq, 2007cee4d264SManish Chopra .q_tx_start = &qed_start_txq, 2008cee4d264SManish Chopra .q_tx_stop = &qed_stop_txq, 2009cee4d264SManish Chopra .filter_config = &qed_configure_filter, 2010cee4d264SManish Chopra .fastpath_stop = &qed_fastpath_stop, 2011cee4d264SManish Chopra .eth_cqe_completion = &qed_fp_cqe_completion, 20129df2ed04SManish Chopra .get_vport_stats = &qed_get_vport_stats, 201325c089d7SYuval Mintz }; 201425c089d7SYuval Mintz 201525c089d7SYuval Mintz const struct qed_eth_ops *qed_get_eth_ops(u32 version) 201625c089d7SYuval Mintz { 201725c089d7SYuval Mintz if (version != QED_ETH_INTERFACE_VERSION) { 201825c089d7SYuval Mintz pr_notice("Cannot supply ethtool operations [%08x != %08x]\n", 201925c089d7SYuval Mintz version, QED_ETH_INTERFACE_VERSION); 202025c089d7SYuval Mintz return NULL; 202125c089d7SYuval Mintz } 202225c089d7SYuval Mintz 202325c089d7SYuval Mintz return &qed_eth_ops_pass; 202425c089d7SYuval Mintz } 202525c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops); 202625c089d7SYuval Mintz 202725c089d7SYuval Mintz void qed_put_eth_ops(void) 202825c089d7SYuval Mintz { 202925c089d7SYuval Mintz /* TODO - reference count for module? */ 203025c089d7SYuval Mintz } 203125c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops); 2032