125c089d7SYuval Mintz /* QLogic qed NIC Driver
225c089d7SYuval Mintz  * Copyright (c) 2015 QLogic Corporation
325c089d7SYuval Mintz  *
425c089d7SYuval Mintz  * This software is available under the terms of the GNU General Public License
525c089d7SYuval Mintz  * (GPL) Version 2, available from the file COPYING in the main directory of
625c089d7SYuval Mintz  * this source tree.
725c089d7SYuval Mintz  */
825c089d7SYuval Mintz 
925c089d7SYuval Mintz #include <linux/types.h>
1025c089d7SYuval Mintz #include <asm/byteorder.h>
1125c089d7SYuval Mintz #include <asm/param.h>
1225c089d7SYuval Mintz #include <linux/delay.h>
1325c089d7SYuval Mintz #include <linux/dma-mapping.h>
1425c089d7SYuval Mintz #include <linux/etherdevice.h>
1525c089d7SYuval Mintz #include <linux/interrupt.h>
1625c089d7SYuval Mintz #include <linux/kernel.h>
1725c089d7SYuval Mintz #include <linux/module.h>
1825c089d7SYuval Mintz #include <linux/pci.h>
1925c089d7SYuval Mintz #include <linux/slab.h>
2025c089d7SYuval Mintz #include <linux/stddef.h>
2125c089d7SYuval Mintz #include <linux/string.h>
2225c089d7SYuval Mintz #include <linux/version.h>
2325c089d7SYuval Mintz #include <linux/workqueue.h>
2425c089d7SYuval Mintz #include <linux/bitops.h>
2525c089d7SYuval Mintz #include <linux/bug.h>
2625c089d7SYuval Mintz #include "qed.h"
2725c089d7SYuval Mintz #include <linux/qed/qed_chain.h>
2825c089d7SYuval Mintz #include "qed_cxt.h"
2925c089d7SYuval Mintz #include "qed_dev_api.h"
3025c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h>
3125c089d7SYuval Mintz #include "qed_hsi.h"
3225c089d7SYuval Mintz #include "qed_hw.h"
3325c089d7SYuval Mintz #include "qed_int.h"
34dacd88d6SYuval Mintz #include "qed_l2.h"
3586622ee7SYuval Mintz #include "qed_mcp.h"
3625c089d7SYuval Mintz #include "qed_reg_addr.h"
3725c089d7SYuval Mintz #include "qed_sp.h"
381408cc1fSYuval Mintz #include "qed_sriov.h"
3925c089d7SYuval Mintz 
40088c8618SManish Chopra 
41cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16
42cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41
43cee4d264SManish Chopra 
44dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
45088c8618SManish Chopra 			   struct qed_sp_vport_start_params *p_params)
46cee4d264SManish Chopra {
47cee4d264SManish Chopra 	struct vport_start_ramrod_data *p_ramrod = NULL;
48cee4d264SManish Chopra 	struct qed_spq_entry *p_ent =  NULL;
4906f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
50dacd88d6SYuval Mintz 	u8 abs_vport_id = 0;
51cee4d264SManish Chopra 	int rc = -EINVAL;
52cee4d264SManish Chopra 	u16 rx_mode = 0;
53cee4d264SManish Chopra 
54088c8618SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
551a635e48SYuval Mintz 	if (rc)
56cee4d264SManish Chopra 		return rc;
57cee4d264SManish Chopra 
5806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
5906f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
60088c8618SManish Chopra 	init_data.opaque_fid = p_params->opaque_fid;
6106f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
62cee4d264SManish Chopra 
63cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
64cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_START,
6506f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
66cee4d264SManish Chopra 	if (rc)
67cee4d264SManish Chopra 		return rc;
68cee4d264SManish Chopra 
69cee4d264SManish Chopra 	p_ramrod		= &p_ent->ramrod.vport_start;
70cee4d264SManish Chopra 	p_ramrod->vport_id	= abs_vport_id;
71cee4d264SManish Chopra 
72088c8618SManish Chopra 	p_ramrod->mtu			= cpu_to_le16(p_params->mtu);
73088c8618SManish Chopra 	p_ramrod->inner_vlan_removal_en	= p_params->remove_inner_vlan;
74088c8618SManish Chopra 	p_ramrod->drop_ttl0_en		= p_params->drop_ttl0;
75e6bd8923SYuval Mintz 	p_ramrod->untagged		= p_params->only_untagged;
76cee4d264SManish Chopra 
77cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
78cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
79cee4d264SManish Chopra 
80cee4d264SManish Chopra 	p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
81cee4d264SManish Chopra 
82cee4d264SManish Chopra 	/* TPA related fields */
831a635e48SYuval Mintz 	memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
84cee4d264SManish Chopra 
85088c8618SManish Chopra 	p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
86088c8618SManish Chopra 
87088c8618SManish Chopra 	switch (p_params->tpa_mode) {
88088c8618SManish Chopra 	case QED_TPA_MODE_GRO:
89088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
90088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_size = (u16)-1;
91088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
92088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
93088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
94088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
95088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
96088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
97088c8618SManish Chopra 		break;
98088c8618SManish Chopra 	default:
99088c8618SManish Chopra 		break;
100088c8618SManish Chopra 	}
101088c8618SManish Chopra 
102831bfb0eSYuval Mintz 	p_ramrod->tx_switching_en = p_params->tx_switching;
103831bfb0eSYuval Mintz 
104cee4d264SManish Chopra 	/* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
105cee4d264SManish Chopra 	p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
106088c8618SManish Chopra 						  p_params->concrete_fid);
107cee4d264SManish Chopra 
108cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
109cee4d264SManish Chopra }
110cee4d264SManish Chopra 
111dacd88d6SYuval Mintz int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
112dacd88d6SYuval Mintz 		       struct qed_sp_vport_start_params *p_params)
113dacd88d6SYuval Mintz {
114dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
115dacd88d6SYuval Mintz 		return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
116dacd88d6SYuval Mintz 					     p_params->mtu,
117dacd88d6SYuval Mintz 					     p_params->remove_inner_vlan,
118dacd88d6SYuval Mintz 					     p_params->tpa_mode,
11908feecd7SYuval Mintz 					     p_params->max_buffers_per_cqe,
12008feecd7SYuval Mintz 					     p_params->only_untagged);
121dacd88d6SYuval Mintz 	}
122dacd88d6SYuval Mintz 
123dacd88d6SYuval Mintz 	return qed_sp_eth_vport_start(p_hwfn, p_params);
124dacd88d6SYuval Mintz }
125dacd88d6SYuval Mintz 
126cee4d264SManish Chopra static int
127cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
128cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
129cee4d264SManish Chopra 			struct qed_rss_params *p_params)
130cee4d264SManish Chopra {
131cee4d264SManish Chopra 	struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
132cee4d264SManish Chopra 	u16 abs_l2_queue = 0, capabilities = 0;
133cee4d264SManish Chopra 	int rc = 0, i;
134cee4d264SManish Chopra 
135cee4d264SManish Chopra 	if (!p_params) {
136cee4d264SManish Chopra 		p_ramrod->common.update_rss_flg = 0;
137cee4d264SManish Chopra 		return rc;
138cee4d264SManish Chopra 	}
139cee4d264SManish Chopra 
140cee4d264SManish Chopra 	BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
141cee4d264SManish Chopra 		     ETH_RSS_IND_TABLE_ENTRIES_NUM);
142cee4d264SManish Chopra 
143cee4d264SManish Chopra 	rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
144cee4d264SManish Chopra 	if (rc)
145cee4d264SManish Chopra 		return rc;
146cee4d264SManish Chopra 
147cee4d264SManish Chopra 	p_ramrod->common.update_rss_flg = p_params->update_rss_config;
148cee4d264SManish Chopra 	rss->update_rss_capabilities = p_params->update_rss_capabilities;
149cee4d264SManish Chopra 	rss->update_rss_ind_table = p_params->update_rss_ind_table;
150cee4d264SManish Chopra 	rss->update_rss_key = p_params->update_rss_key;
151cee4d264SManish Chopra 
152cee4d264SManish Chopra 	rss->rss_mode = p_params->rss_enable ?
153cee4d264SManish Chopra 			ETH_VPORT_RSS_MODE_REGULAR :
154cee4d264SManish Chopra 			ETH_VPORT_RSS_MODE_DISABLED;
155cee4d264SManish Chopra 
156cee4d264SManish Chopra 	SET_FIELD(capabilities,
157cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
158cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV4));
159cee4d264SManish Chopra 	SET_FIELD(capabilities,
160cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
161cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV6));
162cee4d264SManish Chopra 	SET_FIELD(capabilities,
163cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
164cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
165cee4d264SManish Chopra 	SET_FIELD(capabilities,
166cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
167cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
168cee4d264SManish Chopra 	SET_FIELD(capabilities,
169cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
170cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
171cee4d264SManish Chopra 	SET_FIELD(capabilities,
172cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
173cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
174cee4d264SManish Chopra 	rss->tbl_size = p_params->rss_table_size_log;
175cee4d264SManish Chopra 
176cee4d264SManish Chopra 	rss->capabilities = cpu_to_le16(capabilities);
177cee4d264SManish Chopra 
178cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
179cee4d264SManish Chopra 		   "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
180cee4d264SManish Chopra 		   p_ramrod->common.update_rss_flg,
181cee4d264SManish Chopra 		   rss->rss_mode, rss->update_rss_capabilities,
182cee4d264SManish Chopra 		   capabilities, rss->update_rss_ind_table,
183cee4d264SManish Chopra 		   rss->update_rss_key);
184cee4d264SManish Chopra 
185cee4d264SManish Chopra 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
186cee4d264SManish Chopra 		rc = qed_fw_l2_queue(p_hwfn,
187cee4d264SManish Chopra 				     (u8)p_params->rss_ind_table[i],
188cee4d264SManish Chopra 				     &abs_l2_queue);
189cee4d264SManish Chopra 		if (rc)
190cee4d264SManish Chopra 			return rc;
191cee4d264SManish Chopra 
192cee4d264SManish Chopra 		rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
193cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
194cee4d264SManish Chopra 			   i, rss->indirection_table[i]);
195cee4d264SManish Chopra 	}
196cee4d264SManish Chopra 
197cee4d264SManish Chopra 	for (i = 0; i < 10; i++)
198cee4d264SManish Chopra 		rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
199cee4d264SManish Chopra 
200cee4d264SManish Chopra 	return rc;
201cee4d264SManish Chopra }
202cee4d264SManish Chopra 
203cee4d264SManish Chopra static void
204cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
205cee4d264SManish Chopra 			  struct vport_update_ramrod_data *p_ramrod,
206cee4d264SManish Chopra 			  struct qed_filter_accept_flags accept_flags)
207cee4d264SManish Chopra {
208cee4d264SManish Chopra 	p_ramrod->common.update_rx_mode_flg =
209cee4d264SManish Chopra 		accept_flags.update_rx_mode_config;
210cee4d264SManish Chopra 
211cee4d264SManish Chopra 	p_ramrod->common.update_tx_mode_flg =
212cee4d264SManish Chopra 		accept_flags.update_tx_mode_config;
213cee4d264SManish Chopra 
214cee4d264SManish Chopra 	/* Set Rx mode accept flags */
215cee4d264SManish Chopra 	if (p_ramrod->common.update_rx_mode_flg) {
216cee4d264SManish Chopra 		u8 accept_filter = accept_flags.rx_accept_filter;
217cee4d264SManish Chopra 		u16 state = 0;
218cee4d264SManish Chopra 
219cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
220cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
221cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
222cee4d264SManish Chopra 
223cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
224cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
225cee4d264SManish Chopra 
226cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
227cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
228cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
229cee4d264SManish Chopra 
230cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
231cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
232cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
233cee4d264SManish Chopra 
234cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
235cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
236cee4d264SManish Chopra 
237cee4d264SManish Chopra 		p_ramrod->rx_mode.state = cpu_to_le16(state);
238cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
239cee4d264SManish Chopra 			   "p_ramrod->rx_mode.state = 0x%x\n", state);
240cee4d264SManish Chopra 	}
241cee4d264SManish Chopra 
242cee4d264SManish Chopra 	/* Set Tx mode accept flags */
243cee4d264SManish Chopra 	if (p_ramrod->common.update_tx_mode_flg) {
244cee4d264SManish Chopra 		u8 accept_filter = accept_flags.tx_accept_filter;
245cee4d264SManish Chopra 		u16 state = 0;
246cee4d264SManish Chopra 
247cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
248cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
249cee4d264SManish Chopra 
250cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
251cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
252cee4d264SManish Chopra 
253cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
254cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
255cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
256cee4d264SManish Chopra 
257cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
258cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
259cee4d264SManish Chopra 
260cee4d264SManish Chopra 		p_ramrod->tx_mode.state = cpu_to_le16(state);
261cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
262cee4d264SManish Chopra 			   "p_ramrod->tx_mode.state = 0x%x\n", state);
263cee4d264SManish Chopra 	}
264cee4d264SManish Chopra }
265cee4d264SManish Chopra 
266cee4d264SManish Chopra static void
26717b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
26817b235c1SYuval Mintz 			    struct vport_update_ramrod_data *p_ramrod,
26917b235c1SYuval Mintz 			    struct qed_sge_tpa_params *p_params)
27017b235c1SYuval Mintz {
27117b235c1SYuval Mintz 	struct eth_vport_tpa_param *p_tpa;
27217b235c1SYuval Mintz 
27317b235c1SYuval Mintz 	if (!p_params) {
27417b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
27517b235c1SYuval Mintz 		p_ramrod->common.update_tpa_en_flg = 0;
27617b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
27717b235c1SYuval Mintz 		return;
27817b235c1SYuval Mintz 	}
27917b235c1SYuval Mintz 
28017b235c1SYuval Mintz 	p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
28117b235c1SYuval Mintz 	p_tpa = &p_ramrod->tpa_param;
28217b235c1SYuval Mintz 	p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
28317b235c1SYuval Mintz 	p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
28417b235c1SYuval Mintz 	p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
28517b235c1SYuval Mintz 	p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
28617b235c1SYuval Mintz 
28717b235c1SYuval Mintz 	p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
28817b235c1SYuval Mintz 	p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
28917b235c1SYuval Mintz 	p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
29017b235c1SYuval Mintz 	p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
29117b235c1SYuval Mintz 	p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
29217b235c1SYuval Mintz 	p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
29317b235c1SYuval Mintz 	p_tpa->tpa_max_size = p_params->tpa_max_size;
29417b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
29517b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
29617b235c1SYuval Mintz }
29717b235c1SYuval Mintz 
29817b235c1SYuval Mintz static void
299cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
300cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
301cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params)
302cee4d264SManish Chopra {
303cee4d264SManish Chopra 	int i;
304cee4d264SManish Chopra 
305cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
306cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
307cee4d264SManish Chopra 
30883aeb933SYuval Mintz 	if (!p_params->update_approx_mcast_flg)
30983aeb933SYuval Mintz 		return;
31083aeb933SYuval Mintz 
311cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
312cee4d264SManish Chopra 	for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
313cee4d264SManish Chopra 		u32 *p_bins = (u32 *)p_params->bins;
314cee4d264SManish Chopra 
31583aeb933SYuval Mintz 		p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
316cee4d264SManish Chopra 	}
317cee4d264SManish Chopra }
318cee4d264SManish Chopra 
319dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
320cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params,
321cee4d264SManish Chopra 			enum spq_mode comp_mode,
322cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
323cee4d264SManish Chopra {
324cee4d264SManish Chopra 	struct qed_rss_params *p_rss_params = p_params->rss_params;
325cee4d264SManish Chopra 	struct vport_update_ramrod_data_cmn *p_cmn;
32606f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
327cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
328cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
32917b235c1SYuval Mintz 	u8 abs_vport_id = 0, val;
330cee4d264SManish Chopra 	int rc = -EINVAL;
331cee4d264SManish Chopra 
332dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
333dacd88d6SYuval Mintz 		rc = qed_vf_pf_vport_update(p_hwfn, p_params);
334dacd88d6SYuval Mintz 		return rc;
335dacd88d6SYuval Mintz 	}
336dacd88d6SYuval Mintz 
337cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
3381a635e48SYuval Mintz 	if (rc)
339cee4d264SManish Chopra 		return rc;
340cee4d264SManish Chopra 
34106f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
34206f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
34306f56b81SYuval Mintz 	init_data.opaque_fid = p_params->opaque_fid;
34406f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
34506f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
346cee4d264SManish Chopra 
347cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
348cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
34906f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
350cee4d264SManish Chopra 	if (rc)
351cee4d264SManish Chopra 		return rc;
352cee4d264SManish Chopra 
353cee4d264SManish Chopra 	/* Copy input params to ramrod according to FW struct */
354cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
355cee4d264SManish Chopra 	p_cmn = &p_ramrod->common;
356cee4d264SManish Chopra 
357cee4d264SManish Chopra 	p_cmn->vport_id = abs_vport_id;
358cee4d264SManish Chopra 	p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
359cee4d264SManish Chopra 	p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
360cee4d264SManish Chopra 	p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
361cee4d264SManish Chopra 	p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3623f9b4a69SYuval Mintz 	p_cmn->accept_any_vlan = p_params->accept_any_vlan;
36383aeb933SYuval Mintz 	val = p_params->update_accept_any_vlan_flg;
36483aeb933SYuval Mintz 	p_cmn->update_accept_any_vlan_flg = val;
36517b235c1SYuval Mintz 
36617b235c1SYuval Mintz 	p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
36717b235c1SYuval Mintz 	val = p_params->update_inner_vlan_removal_flg;
36817b235c1SYuval Mintz 	p_cmn->update_inner_vlan_removal_en_flg = val;
36908feecd7SYuval Mintz 
37008feecd7SYuval Mintz 	p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
37108feecd7SYuval Mintz 	val = p_params->update_default_vlan_enable_flg;
37208feecd7SYuval Mintz 	p_cmn->update_default_vlan_en_flg = val;
37308feecd7SYuval Mintz 
37408feecd7SYuval Mintz 	p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
37508feecd7SYuval Mintz 	p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
37608feecd7SYuval Mintz 
37708feecd7SYuval Mintz 	p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
37808feecd7SYuval Mintz 
37917b235c1SYuval Mintz 	p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
38017b235c1SYuval Mintz 	p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
38117b235c1SYuval Mintz 
3826ddc7608SYuval Mintz 	p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
3836ddc7608SYuval Mintz 	val = p_params->update_anti_spoofing_en_flg;
3846ddc7608SYuval Mintz 	p_ramrod->common.update_anti_spoofing_en_flg = val;
3856ddc7608SYuval Mintz 
386cee4d264SManish Chopra 	rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
387cee4d264SManish Chopra 	if (rc) {
388cee4d264SManish Chopra 		/* Return spq entry which is taken in qed_sp_init_request()*/
389cee4d264SManish Chopra 		qed_spq_return_entry(p_hwfn, p_ent);
390cee4d264SManish Chopra 		return rc;
391cee4d264SManish Chopra 	}
392cee4d264SManish Chopra 
393cee4d264SManish Chopra 	/* Update mcast bins for VFs, PF doesn't use this functionality */
394cee4d264SManish Chopra 	qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
395cee4d264SManish Chopra 
396cee4d264SManish Chopra 	qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
39717b235c1SYuval Mintz 	qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
398cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
399cee4d264SManish Chopra }
400cee4d264SManish Chopra 
401dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
402cee4d264SManish Chopra {
403cee4d264SManish Chopra 	struct vport_stop_ramrod_data *p_ramrod;
40406f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
405cee4d264SManish Chopra 	struct qed_spq_entry *p_ent;
406cee4d264SManish Chopra 	u8 abs_vport_id = 0;
407cee4d264SManish Chopra 	int rc;
408cee4d264SManish Chopra 
409dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
410dacd88d6SYuval Mintz 		return qed_vf_pf_vport_stop(p_hwfn);
411dacd88d6SYuval Mintz 
412cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
4131a635e48SYuval Mintz 	if (rc)
414cee4d264SManish Chopra 		return rc;
415cee4d264SManish Chopra 
41606f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
41706f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
41806f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
41906f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
420cee4d264SManish Chopra 
421cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
422cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_STOP,
42306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
424cee4d264SManish Chopra 	if (rc)
425cee4d264SManish Chopra 		return rc;
426cee4d264SManish Chopra 
427cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_stop;
428cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
429cee4d264SManish Chopra 
430cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
431cee4d264SManish Chopra }
432cee4d264SManish Chopra 
433dacd88d6SYuval Mintz static int
434dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
435dacd88d6SYuval Mintz 		       struct qed_filter_accept_flags *p_accept_flags)
436dacd88d6SYuval Mintz {
437dacd88d6SYuval Mintz 	struct qed_sp_vport_update_params s_params;
438dacd88d6SYuval Mintz 
439dacd88d6SYuval Mintz 	memset(&s_params, 0, sizeof(s_params));
440dacd88d6SYuval Mintz 	memcpy(&s_params.accept_flags, p_accept_flags,
441dacd88d6SYuval Mintz 	       sizeof(struct qed_filter_accept_flags));
442dacd88d6SYuval Mintz 
443dacd88d6SYuval Mintz 	return qed_vf_pf_vport_update(p_hwfn, &s_params);
444dacd88d6SYuval Mintz }
445dacd88d6SYuval Mintz 
446cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev,
447cee4d264SManish Chopra 				 u8 vport,
448cee4d264SManish Chopra 				 struct qed_filter_accept_flags accept_flags,
4493f9b4a69SYuval Mintz 				 u8 update_accept_any_vlan,
4503f9b4a69SYuval Mintz 				 u8 accept_any_vlan,
451cee4d264SManish Chopra 				 enum spq_mode comp_mode,
452cee4d264SManish Chopra 				 struct qed_spq_comp_cb *p_comp_data)
453cee4d264SManish Chopra {
454cee4d264SManish Chopra 	struct qed_sp_vport_update_params vport_update_params;
455cee4d264SManish Chopra 	int i, rc;
456cee4d264SManish Chopra 
457cee4d264SManish Chopra 	/* Prepare and send the vport rx_mode change */
458cee4d264SManish Chopra 	memset(&vport_update_params, 0, sizeof(vport_update_params));
459cee4d264SManish Chopra 	vport_update_params.vport_id = vport;
460cee4d264SManish Chopra 	vport_update_params.accept_flags = accept_flags;
4613f9b4a69SYuval Mintz 	vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
4623f9b4a69SYuval Mintz 	vport_update_params.accept_any_vlan = accept_any_vlan;
463cee4d264SManish Chopra 
464cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
465cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
466cee4d264SManish Chopra 
467cee4d264SManish Chopra 		vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
468cee4d264SManish Chopra 
469dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
470dacd88d6SYuval Mintz 			rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
471dacd88d6SYuval Mintz 			if (rc)
472dacd88d6SYuval Mintz 				return rc;
473dacd88d6SYuval Mintz 			continue;
474dacd88d6SYuval Mintz 		}
475dacd88d6SYuval Mintz 
476cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
477cee4d264SManish Chopra 					 comp_mode, p_comp_data);
4781a635e48SYuval Mintz 		if (rc) {
479cee4d264SManish Chopra 			DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
480cee4d264SManish Chopra 			return rc;
481cee4d264SManish Chopra 		}
482cee4d264SManish Chopra 
483cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
484cee4d264SManish Chopra 			   "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
485cee4d264SManish Chopra 			   accept_flags.rx_accept_filter,
486cee4d264SManish Chopra 			   accept_flags.tx_accept_filter);
4873f9b4a69SYuval Mintz 		if (update_accept_any_vlan)
4883f9b4a69SYuval Mintz 			DP_VERBOSE(p_hwfn, QED_MSG_SP,
4893f9b4a69SYuval Mintz 				   "accept_any_vlan=%d configured\n",
4903f9b4a69SYuval Mintz 				   accept_any_vlan);
491cee4d264SManish Chopra 	}
492cee4d264SManish Chopra 
493cee4d264SManish Chopra 	return 0;
494cee4d264SManish Chopra }
495cee4d264SManish Chopra 
496cee4d264SManish Chopra static int qed_sp_release_queue_cid(
497cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn,
498cee4d264SManish Chopra 	struct qed_hw_cid_data *p_cid_data)
499cee4d264SManish Chopra {
500cee4d264SManish Chopra 	if (!p_cid_data->b_cid_allocated)
501cee4d264SManish Chopra 		return 0;
502cee4d264SManish Chopra 
503cee4d264SManish Chopra 	qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
504cee4d264SManish Chopra 
505cee4d264SManish Chopra 	p_cid_data->b_cid_allocated = false;
506cee4d264SManish Chopra 
507cee4d264SManish Chopra 	return 0;
508cee4d264SManish Chopra }
509cee4d264SManish Chopra 
510dacd88d6SYuval Mintz int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
511cee4d264SManish Chopra 				u16 opaque_fid,
512cee4d264SManish Chopra 				u32 cid,
5131a635e48SYuval Mintz 				struct qed_queue_start_common_params *p_params,
514cee4d264SManish Chopra 				u8 stats_id,
515cee4d264SManish Chopra 				u16 bd_max_bytes,
516cee4d264SManish Chopra 				dma_addr_t bd_chain_phys_addr,
517dacd88d6SYuval Mintz 				dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
518cee4d264SManish Chopra {
519cee4d264SManish Chopra 	struct rx_queue_start_ramrod_data *p_ramrod = NULL;
520cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
52106f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
522cee4d264SManish Chopra 	struct qed_hw_cid_data *p_rx_cid;
523cee4d264SManish Chopra 	u16 abs_rx_q_id = 0;
524cee4d264SManish Chopra 	u8 abs_vport_id = 0;
525cee4d264SManish Chopra 	int rc = -EINVAL;
526cee4d264SManish Chopra 
527cee4d264SManish Chopra 	/* Store information for the stop */
5281a635e48SYuval Mintz 	p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
529cee4d264SManish Chopra 	p_rx_cid->cid = cid;
530cee4d264SManish Chopra 	p_rx_cid->opaque_fid = opaque_fid;
5311a635e48SYuval Mintz 	p_rx_cid->vport_id = p_params->vport_id;
532cee4d264SManish Chopra 
5331a635e48SYuval Mintz 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
5341a635e48SYuval Mintz 	if (rc)
535cee4d264SManish Chopra 		return rc;
536cee4d264SManish Chopra 
5371a635e48SYuval Mintz 	rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_rx_q_id);
5381a635e48SYuval Mintz 	if (rc)
539cee4d264SManish Chopra 		return rc;
540cee4d264SManish Chopra 
541cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
542cee4d264SManish Chopra 		   "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
5431a635e48SYuval Mintz 		   opaque_fid,
5441a635e48SYuval Mintz 		   cid, p_params->queue_id, p_params->vport_id, p_params->sb);
545cee4d264SManish Chopra 
54606f56b81SYuval Mintz 	/* Get SPQ entry */
54706f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
54806f56b81SYuval Mintz 	init_data.cid = cid;
54906f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
55006f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
551cee4d264SManish Chopra 
552cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
553cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_START,
55406f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
555cee4d264SManish Chopra 	if (rc)
556cee4d264SManish Chopra 		return rc;
557cee4d264SManish Chopra 
558cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_start;
559cee4d264SManish Chopra 
5601a635e48SYuval Mintz 	p_ramrod->sb_id = cpu_to_le16(p_params->sb);
5611a635e48SYuval Mintz 	p_ramrod->sb_index = p_params->sb_idx;
562cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
563cee4d264SManish Chopra 	p_ramrod->stats_counter_id = stats_id;
564cee4d264SManish Chopra 	p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
565cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg = 0;
566cee4d264SManish Chopra 	p_ramrod->complete_event_flg = 1;
567cee4d264SManish Chopra 
568cee4d264SManish Chopra 	p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
56994494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
570cee4d264SManish Chopra 
571cee4d264SManish Chopra 	p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
57294494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
573cee4d264SManish Chopra 
5741a635e48SYuval Mintz 	p_ramrod->vf_rx_prod_index = p_params->vf_qid;
5751a635e48SYuval Mintz 	if (p_params->vf_qid)
576351a4dedSYuval Mintz 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
5771a635e48SYuval Mintz 			   "Queue is meant for VF rxq[%04x]\n",
5781a635e48SYuval Mintz 			   p_params->vf_qid);
579cee4d264SManish Chopra 
580351a4dedSYuval Mintz 	return qed_spq_post(p_hwfn, p_ent, NULL);
581cee4d264SManish Chopra }
582cee4d264SManish Chopra 
583cee4d264SManish Chopra static int
584cee4d264SManish Chopra qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
585cee4d264SManish Chopra 			  u16 opaque_fid,
5861a635e48SYuval Mintz 			  struct qed_queue_start_common_params *p_params,
587cee4d264SManish Chopra 			  u16 bd_max_bytes,
588cee4d264SManish Chopra 			  dma_addr_t bd_chain_phys_addr,
589cee4d264SManish Chopra 			  dma_addr_t cqe_pbl_addr,
590dacd88d6SYuval Mintz 			  u16 cqe_pbl_size, void __iomem **pp_prod)
591cee4d264SManish Chopra {
592cee4d264SManish Chopra 	struct qed_hw_cid_data *p_rx_cid;
593b21290b7SYuval Mintz 	u32 init_prod_val = 0;
594cee4d264SManish Chopra 	u16 abs_l2_queue = 0;
595cee4d264SManish Chopra 	u8 abs_stats_id = 0;
596cee4d264SManish Chopra 	int rc;
597cee4d264SManish Chopra 
598dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
599dacd88d6SYuval Mintz 		return qed_vf_pf_rxq_start(p_hwfn,
6001a635e48SYuval Mintz 					   p_params->queue_id,
6011a635e48SYuval Mintz 					   p_params->sb,
6021a635e48SYuval Mintz 					   (u8)p_params->sb_idx,
603dacd88d6SYuval Mintz 					   bd_max_bytes,
604dacd88d6SYuval Mintz 					   bd_chain_phys_addr,
605dacd88d6SYuval Mintz 					   cqe_pbl_addr, cqe_pbl_size, pp_prod);
606dacd88d6SYuval Mintz 	}
607dacd88d6SYuval Mintz 
6081a635e48SYuval Mintz 	rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_l2_queue);
6091a635e48SYuval Mintz 	if (rc)
610cee4d264SManish Chopra 		return rc;
611cee4d264SManish Chopra 
6121a635e48SYuval Mintz 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
6131a635e48SYuval Mintz 	if (rc)
614cee4d264SManish Chopra 		return rc;
615cee4d264SManish Chopra 
616cee4d264SManish Chopra 	*pp_prod = (u8 __iomem *)p_hwfn->regview +
617cee4d264SManish Chopra 				 GTT_BAR0_MAP_REG_MSDM_RAM +
618351a4dedSYuval Mintz 				 MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
619cee4d264SManish Chopra 
620cee4d264SManish Chopra 	/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
621b21290b7SYuval Mintz 	__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
622cee4d264SManish Chopra 			  (u32 *)(&init_prod_val));
623cee4d264SManish Chopra 
624cee4d264SManish Chopra 	/* Allocate a CID for the queue */
6251a635e48SYuval Mintz 	p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
6261a635e48SYuval Mintz 	rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_rx_cid->cid);
627cee4d264SManish Chopra 	if (rc) {
628cee4d264SManish Chopra 		DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
629cee4d264SManish Chopra 		return rc;
630cee4d264SManish Chopra 	}
631cee4d264SManish Chopra 	p_rx_cid->b_cid_allocated = true;
632cee4d264SManish Chopra 
633cee4d264SManish Chopra 	rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
634cee4d264SManish Chopra 					 opaque_fid,
635cee4d264SManish Chopra 					 p_rx_cid->cid,
6361a635e48SYuval Mintz 					 p_params,
637cee4d264SManish Chopra 					 abs_stats_id,
638cee4d264SManish Chopra 					 bd_max_bytes,
639cee4d264SManish Chopra 					 bd_chain_phys_addr,
640cee4d264SManish Chopra 					 cqe_pbl_addr,
641cee4d264SManish Chopra 					 cqe_pbl_size);
642cee4d264SManish Chopra 
6431a635e48SYuval Mintz 	if (rc)
644cee4d264SManish Chopra 		qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
645cee4d264SManish Chopra 
646cee4d264SManish Chopra 	return rc;
647cee4d264SManish Chopra }
648cee4d264SManish Chopra 
64917b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
65017b235c1SYuval Mintz 				u16 rx_queue_id,
65117b235c1SYuval Mintz 				u8 num_rxqs,
65217b235c1SYuval Mintz 				u8 complete_cqe_flg,
65317b235c1SYuval Mintz 				u8 complete_event_flg,
65417b235c1SYuval Mintz 				enum spq_mode comp_mode,
65517b235c1SYuval Mintz 				struct qed_spq_comp_cb *p_comp_data)
65617b235c1SYuval Mintz {
65717b235c1SYuval Mintz 	struct rx_queue_update_ramrod_data *p_ramrod = NULL;
65817b235c1SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
65917b235c1SYuval Mintz 	struct qed_sp_init_data init_data;
66017b235c1SYuval Mintz 	struct qed_hw_cid_data *p_rx_cid;
66117b235c1SYuval Mintz 	u16 qid, abs_rx_q_id = 0;
66217b235c1SYuval Mintz 	int rc = -EINVAL;
66317b235c1SYuval Mintz 	u8 i;
66417b235c1SYuval Mintz 
66517b235c1SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
66617b235c1SYuval Mintz 	init_data.comp_mode = comp_mode;
66717b235c1SYuval Mintz 	init_data.p_comp_data = p_comp_data;
66817b235c1SYuval Mintz 
66917b235c1SYuval Mintz 	for (i = 0; i < num_rxqs; i++) {
67017b235c1SYuval Mintz 		qid = rx_queue_id + i;
67117b235c1SYuval Mintz 		p_rx_cid = &p_hwfn->p_rx_cids[qid];
67217b235c1SYuval Mintz 
67317b235c1SYuval Mintz 		/* Get SPQ entry */
67417b235c1SYuval Mintz 		init_data.cid = p_rx_cid->cid;
67517b235c1SYuval Mintz 		init_data.opaque_fid = p_rx_cid->opaque_fid;
67617b235c1SYuval Mintz 
67717b235c1SYuval Mintz 		rc = qed_sp_init_request(p_hwfn, &p_ent,
67817b235c1SYuval Mintz 					 ETH_RAMROD_RX_QUEUE_UPDATE,
67917b235c1SYuval Mintz 					 PROTOCOLID_ETH, &init_data);
68017b235c1SYuval Mintz 		if (rc)
68117b235c1SYuval Mintz 			return rc;
68217b235c1SYuval Mintz 
68317b235c1SYuval Mintz 		p_ramrod = &p_ent->ramrod.rx_queue_update;
68417b235c1SYuval Mintz 
68517b235c1SYuval Mintz 		qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
68617b235c1SYuval Mintz 		qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
68717b235c1SYuval Mintz 		p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
68817b235c1SYuval Mintz 		p_ramrod->complete_cqe_flg = complete_cqe_flg;
68917b235c1SYuval Mintz 		p_ramrod->complete_event_flg = complete_event_flg;
69017b235c1SYuval Mintz 
69117b235c1SYuval Mintz 		rc = qed_spq_post(p_hwfn, p_ent, NULL);
69217b235c1SYuval Mintz 		if (rc)
69317b235c1SYuval Mintz 			return rc;
69417b235c1SYuval Mintz 	}
69517b235c1SYuval Mintz 
69617b235c1SYuval Mintz 	return rc;
69717b235c1SYuval Mintz }
69817b235c1SYuval Mintz 
699dacd88d6SYuval Mintz int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
700cee4d264SManish Chopra 			     u16 rx_queue_id,
701dacd88d6SYuval Mintz 			     bool eq_completion_only, bool cqe_completion)
702cee4d264SManish Chopra {
703cee4d264SManish Chopra 	struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
704cee4d264SManish Chopra 	struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
705cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
70606f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
707cee4d264SManish Chopra 	u16 abs_rx_q_id = 0;
708cee4d264SManish Chopra 	int rc = -EINVAL;
709cee4d264SManish Chopra 
710dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
711dacd88d6SYuval Mintz 		return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion);
712dacd88d6SYuval Mintz 
71306f56b81SYuval Mintz 	/* Get SPQ entry */
71406f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
71506f56b81SYuval Mintz 	init_data.cid = p_rx_cid->cid;
71606f56b81SYuval Mintz 	init_data.opaque_fid = p_rx_cid->opaque_fid;
71706f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
718cee4d264SManish Chopra 
719cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
720cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_STOP,
72106f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
722cee4d264SManish Chopra 	if (rc)
723cee4d264SManish Chopra 		return rc;
724cee4d264SManish Chopra 
725cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_stop;
726cee4d264SManish Chopra 
727cee4d264SManish Chopra 	qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
728cee4d264SManish Chopra 	qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
729cee4d264SManish Chopra 	p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
730cee4d264SManish Chopra 
731cee4d264SManish Chopra 	/* Cleaning the queue requires the completion to arrive there.
732cee4d264SManish Chopra 	 * In addition, VFs require the answer to come as eqe to PF.
733cee4d264SManish Chopra 	 */
734cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg =
735cee4d264SManish Chopra 		(!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
736cee4d264SManish Chopra 		 !eq_completion_only) || cqe_completion;
737cee4d264SManish Chopra 	p_ramrod->complete_event_flg =
738cee4d264SManish Chopra 		!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
739cee4d264SManish Chopra 		eq_completion_only;
740cee4d264SManish Chopra 
741cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
742cee4d264SManish Chopra 	if (rc)
743cee4d264SManish Chopra 		return rc;
744cee4d264SManish Chopra 
745cee4d264SManish Chopra 	return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
746cee4d264SManish Chopra }
747cee4d264SManish Chopra 
748dacd88d6SYuval Mintz int qed_sp_eth_txq_start_ramrod(struct qed_hwfn  *p_hwfn,
749cee4d264SManish Chopra 				u16  opaque_fid,
750cee4d264SManish Chopra 				u32  cid,
751cee4d264SManish Chopra 				struct qed_queue_start_common_params *p_params,
752cee4d264SManish Chopra 				u8  stats_id,
753cee4d264SManish Chopra 				dma_addr_t pbl_addr,
754cee4d264SManish Chopra 				u16 pbl_size,
755cee4d264SManish Chopra 				union qed_qm_pq_params *p_pq_params)
756cee4d264SManish Chopra {
757cee4d264SManish Chopra 	struct tx_queue_start_ramrod_data *p_ramrod = NULL;
758cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
75906f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
760cee4d264SManish Chopra 	struct qed_hw_cid_data *p_tx_cid;
761351a4dedSYuval Mintz 	u16 pq_id, abs_tx_q_id = 0;
762cee4d264SManish Chopra 	int rc = -EINVAL;
763351a4dedSYuval Mintz 	u8 abs_vport_id;
764cee4d264SManish Chopra 
765cee4d264SManish Chopra 	/* Store information for the stop */
766cee4d264SManish Chopra 	p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
767cee4d264SManish Chopra 	p_tx_cid->cid		= cid;
768cee4d264SManish Chopra 	p_tx_cid->opaque_fid	= opaque_fid;
769cee4d264SManish Chopra 
770cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
771cee4d264SManish Chopra 	if (rc)
772cee4d264SManish Chopra 		return rc;
773cee4d264SManish Chopra 
774351a4dedSYuval Mintz 	rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_tx_q_id);
775351a4dedSYuval Mintz 	if (rc)
776351a4dedSYuval Mintz 		return rc;
777351a4dedSYuval Mintz 
77806f56b81SYuval Mintz 	/* Get SPQ entry */
77906f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
78006f56b81SYuval Mintz 	init_data.cid = cid;
78106f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
78206f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
783cee4d264SManish Chopra 
78406f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
785cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_START,
78606f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
787cee4d264SManish Chopra 	if (rc)
788cee4d264SManish Chopra 		return rc;
789cee4d264SManish Chopra 
790cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.tx_queue_start;
791cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
792cee4d264SManish Chopra 
793cee4d264SManish Chopra 	p_ramrod->sb_id = cpu_to_le16(p_params->sb);
794cee4d264SManish Chopra 	p_ramrod->sb_index = p_params->sb_idx;
795cee4d264SManish Chopra 	p_ramrod->stats_counter_id = stats_id;
796cee4d264SManish Chopra 
797351a4dedSYuval Mintz 	p_ramrod->queue_zone_id = cpu_to_le16(abs_tx_q_id);
7981a635e48SYuval Mintz 
799cee4d264SManish Chopra 	p_ramrod->pbl_size = cpu_to_le16(pbl_size);
80094494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
801cee4d264SManish Chopra 
8021a635e48SYuval Mintz 	pq_id = qed_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
803cee4d264SManish Chopra 	p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
804cee4d264SManish Chopra 
805cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
806cee4d264SManish Chopra }
807cee4d264SManish Chopra 
808cee4d264SManish Chopra static int
809cee4d264SManish Chopra qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
810cee4d264SManish Chopra 			  u16 opaque_fid,
811cee4d264SManish Chopra 			  struct qed_queue_start_common_params *p_params,
812cee4d264SManish Chopra 			  dma_addr_t pbl_addr,
813dacd88d6SYuval Mintz 			  u16 pbl_size, void __iomem **pp_doorbell)
814cee4d264SManish Chopra {
815cee4d264SManish Chopra 	struct qed_hw_cid_data *p_tx_cid;
816cee4d264SManish Chopra 	union qed_qm_pq_params pq_params;
817cee4d264SManish Chopra 	u8 abs_stats_id = 0;
818cee4d264SManish Chopra 	int rc;
819cee4d264SManish Chopra 
820dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
821dacd88d6SYuval Mintz 		return qed_vf_pf_txq_start(p_hwfn,
822dacd88d6SYuval Mintz 					   p_params->queue_id,
823dacd88d6SYuval Mintz 					   p_params->sb,
824dacd88d6SYuval Mintz 					   p_params->sb_idx,
825dacd88d6SYuval Mintz 					   pbl_addr, pbl_size, pp_doorbell);
826dacd88d6SYuval Mintz 	}
827dacd88d6SYuval Mintz 
828cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
829cee4d264SManish Chopra 	if (rc)
830cee4d264SManish Chopra 		return rc;
831cee4d264SManish Chopra 
832cee4d264SManish Chopra 	p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
833cee4d264SManish Chopra 	memset(p_tx_cid, 0, sizeof(*p_tx_cid));
834cee4d264SManish Chopra 	memset(&pq_params, 0, sizeof(pq_params));
835cee4d264SManish Chopra 
836cee4d264SManish Chopra 	/* Allocate a CID for the queue */
8371a635e48SYuval Mintz 	rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
838cee4d264SManish Chopra 	if (rc) {
839cee4d264SManish Chopra 		DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
840cee4d264SManish Chopra 		return rc;
841cee4d264SManish Chopra 	}
842cee4d264SManish Chopra 	p_tx_cid->b_cid_allocated = true;
843cee4d264SManish Chopra 
844cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
845cee4d264SManish Chopra 		   "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
846cee4d264SManish Chopra 		   opaque_fid, p_tx_cid->cid,
847cee4d264SManish Chopra 		   p_params->queue_id, p_params->vport_id, p_params->sb);
848cee4d264SManish Chopra 
849cee4d264SManish Chopra 	rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
850cee4d264SManish Chopra 					 opaque_fid,
851cee4d264SManish Chopra 					 p_tx_cid->cid,
852cee4d264SManish Chopra 					 p_params,
853cee4d264SManish Chopra 					 abs_stats_id,
854cee4d264SManish Chopra 					 pbl_addr,
855cee4d264SManish Chopra 					 pbl_size,
856cee4d264SManish Chopra 					 &pq_params);
857cee4d264SManish Chopra 
858cee4d264SManish Chopra 	*pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
859cee4d264SManish Chopra 				     qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
860cee4d264SManish Chopra 
861cee4d264SManish Chopra 	if (rc)
862cee4d264SManish Chopra 		qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
863cee4d264SManish Chopra 
864cee4d264SManish Chopra 	return rc;
865cee4d264SManish Chopra }
866cee4d264SManish Chopra 
867dacd88d6SYuval Mintz int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id)
868cee4d264SManish Chopra {
869cee4d264SManish Chopra 	struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
870cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
87106f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
872cee4d264SManish Chopra 	int rc = -EINVAL;
873cee4d264SManish Chopra 
874dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
875dacd88d6SYuval Mintz 		return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id);
876dacd88d6SYuval Mintz 
87706f56b81SYuval Mintz 	/* Get SPQ entry */
87806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
87906f56b81SYuval Mintz 	init_data.cid = p_tx_cid->cid;
88006f56b81SYuval Mintz 	init_data.opaque_fid = p_tx_cid->opaque_fid;
88106f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
882cee4d264SManish Chopra 
883cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
884cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_STOP,
88506f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
886cee4d264SManish Chopra 	if (rc)
887cee4d264SManish Chopra 		return rc;
888cee4d264SManish Chopra 
889cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
890cee4d264SManish Chopra 	if (rc)
891cee4d264SManish Chopra 		return rc;
892cee4d264SManish Chopra 
893cee4d264SManish Chopra 	return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
894cee4d264SManish Chopra }
895cee4d264SManish Chopra 
8961a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
897cee4d264SManish Chopra {
898cee4d264SManish Chopra 	enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
899cee4d264SManish Chopra 
900cee4d264SManish Chopra 	switch (opcode) {
901cee4d264SManish Chopra 	case QED_FILTER_ADD:
902cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_ADD;
903cee4d264SManish Chopra 		break;
904cee4d264SManish Chopra 	case QED_FILTER_REMOVE:
905cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_REMOVE;
906cee4d264SManish Chopra 		break;
907cee4d264SManish Chopra 	case QED_FILTER_FLUSH:
908fc48b7a6SYuval Mintz 		action = ETH_FILTER_ACTION_REMOVE_ALL;
909cee4d264SManish Chopra 		break;
910cee4d264SManish Chopra 	default:
911cee4d264SManish Chopra 		action = MAX_ETH_FILTER_ACTION;
912cee4d264SManish Chopra 	}
913cee4d264SManish Chopra 
914cee4d264SManish Chopra 	return action;
915cee4d264SManish Chopra }
916cee4d264SManish Chopra 
917cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb,
918cee4d264SManish Chopra 				__le16 *fw_mid,
919cee4d264SManish Chopra 				__le16 *fw_lsb,
920cee4d264SManish Chopra 				u8 *mac)
921cee4d264SManish Chopra {
922cee4d264SManish Chopra 	((u8 *)fw_msb)[0] = mac[1];
923cee4d264SManish Chopra 	((u8 *)fw_msb)[1] = mac[0];
924cee4d264SManish Chopra 	((u8 *)fw_mid)[0] = mac[3];
925cee4d264SManish Chopra 	((u8 *)fw_mid)[1] = mac[2];
926cee4d264SManish Chopra 	((u8 *)fw_lsb)[0] = mac[5];
927cee4d264SManish Chopra 	((u8 *)fw_lsb)[1] = mac[4];
928cee4d264SManish Chopra }
929cee4d264SManish Chopra 
930cee4d264SManish Chopra static int
931cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
932cee4d264SManish Chopra 			u16 opaque_fid,
933cee4d264SManish Chopra 			struct qed_filter_ucast *p_filter_cmd,
934cee4d264SManish Chopra 			struct vport_filter_update_ramrod_data **pp_ramrod,
935cee4d264SManish Chopra 			struct qed_spq_entry **pp_ent,
936cee4d264SManish Chopra 			enum spq_mode comp_mode,
937cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
938cee4d264SManish Chopra {
939cee4d264SManish Chopra 	u8 vport_to_add_to = 0, vport_to_remove_from = 0;
940cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data *p_ramrod;
941cee4d264SManish Chopra 	struct eth_filter_cmd *p_first_filter;
942cee4d264SManish Chopra 	struct eth_filter_cmd *p_second_filter;
94306f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
944cee4d264SManish Chopra 	enum eth_filter_action action;
945cee4d264SManish Chopra 	int rc;
946cee4d264SManish Chopra 
947cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
948cee4d264SManish Chopra 			  &vport_to_remove_from);
949cee4d264SManish Chopra 	if (rc)
950cee4d264SManish Chopra 		return rc;
951cee4d264SManish Chopra 
952cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
953cee4d264SManish Chopra 			  &vport_to_add_to);
954cee4d264SManish Chopra 	if (rc)
955cee4d264SManish Chopra 		return rc;
956cee4d264SManish Chopra 
95706f56b81SYuval Mintz 	/* Get SPQ entry */
95806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
95906f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
96006f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
96106f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
96206f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
963cee4d264SManish Chopra 
964cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, pp_ent,
965cee4d264SManish Chopra 				 ETH_RAMROD_FILTERS_UPDATE,
96606f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
967cee4d264SManish Chopra 	if (rc)
968cee4d264SManish Chopra 		return rc;
969cee4d264SManish Chopra 
970cee4d264SManish Chopra 	*pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
971cee4d264SManish Chopra 	p_ramrod = *pp_ramrod;
972cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
973cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
974cee4d264SManish Chopra 
975cee4d264SManish Chopra 	switch (p_filter_cmd->opcode) {
976fc48b7a6SYuval Mintz 	case QED_FILTER_REPLACE:
977cee4d264SManish Chopra 	case QED_FILTER_MOVE:
978cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
979cee4d264SManish Chopra 	default:
980cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
981cee4d264SManish Chopra 	}
982cee4d264SManish Chopra 
983cee4d264SManish Chopra 	p_first_filter	= &p_ramrod->filter_cmds[0];
984cee4d264SManish Chopra 	p_second_filter = &p_ramrod->filter_cmds[1];
985cee4d264SManish Chopra 
986cee4d264SManish Chopra 	switch (p_filter_cmd->type) {
987cee4d264SManish Chopra 	case QED_FILTER_MAC:
988cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
989cee4d264SManish Chopra 	case QED_FILTER_VLAN:
990cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
991cee4d264SManish Chopra 	case QED_FILTER_MAC_VLAN:
992cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
993cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC:
994cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
995cee4d264SManish Chopra 	case QED_FILTER_INNER_VLAN:
996cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
997cee4d264SManish Chopra 	case QED_FILTER_INNER_PAIR:
998cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
999cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC_VNI_PAIR:
1000cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1001cee4d264SManish Chopra 		break;
1002cee4d264SManish Chopra 	case QED_FILTER_MAC_VNI_PAIR:
1003cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1004cee4d264SManish Chopra 	case QED_FILTER_VNI:
1005cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1006cee4d264SManish Chopra 	}
1007cee4d264SManish Chopra 
1008cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1009cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1010cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1011cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1012cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1013cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1014cee4d264SManish Chopra 		qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1015cee4d264SManish Chopra 				    &p_first_filter->mac_mid,
1016cee4d264SManish Chopra 				    &p_first_filter->mac_lsb,
1017cee4d264SManish Chopra 				    (u8 *)p_filter_cmd->mac);
1018cee4d264SManish Chopra 	}
1019cee4d264SManish Chopra 
1020cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1021cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1022cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1023cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1024cee4d264SManish Chopra 		p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1025cee4d264SManish Chopra 
1026cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1027cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1028cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1029cee4d264SManish Chopra 		p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1030cee4d264SManish Chopra 
1031cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1032cee4d264SManish Chopra 		p_second_filter->type = p_first_filter->type;
1033cee4d264SManish Chopra 		p_second_filter->mac_msb = p_first_filter->mac_msb;
1034cee4d264SManish Chopra 		p_second_filter->mac_mid = p_first_filter->mac_mid;
1035cee4d264SManish Chopra 		p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1036cee4d264SManish Chopra 		p_second_filter->vlan_id = p_first_filter->vlan_id;
1037cee4d264SManish Chopra 		p_second_filter->vni = p_first_filter->vni;
1038cee4d264SManish Chopra 
1039cee4d264SManish Chopra 		p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1040cee4d264SManish Chopra 
1041cee4d264SManish Chopra 		p_first_filter->vport_id = vport_to_remove_from;
1042cee4d264SManish Chopra 
1043cee4d264SManish Chopra 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1044cee4d264SManish Chopra 		p_second_filter->vport_id = vport_to_add_to;
1045fc48b7a6SYuval Mintz 	} else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1046fc48b7a6SYuval Mintz 		p_first_filter->vport_id = vport_to_add_to;
1047fc48b7a6SYuval Mintz 		memcpy(p_second_filter, p_first_filter,
1048fc48b7a6SYuval Mintz 		       sizeof(*p_second_filter));
1049fc48b7a6SYuval Mintz 		p_first_filter->action	= ETH_FILTER_ACTION_REMOVE_ALL;
1050fc48b7a6SYuval Mintz 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1051cee4d264SManish Chopra 	} else {
1052cee4d264SManish Chopra 		action = qed_filter_action(p_filter_cmd->opcode);
1053cee4d264SManish Chopra 
1054cee4d264SManish Chopra 		if (action == MAX_ETH_FILTER_ACTION) {
1055cee4d264SManish Chopra 			DP_NOTICE(p_hwfn,
1056cee4d264SManish Chopra 				  "%d is not supported yet\n",
1057cee4d264SManish Chopra 				  p_filter_cmd->opcode);
1058cee4d264SManish Chopra 			return -EINVAL;
1059cee4d264SManish Chopra 		}
1060cee4d264SManish Chopra 
1061cee4d264SManish Chopra 		p_first_filter->action = action;
1062cee4d264SManish Chopra 		p_first_filter->vport_id = (p_filter_cmd->opcode ==
1063cee4d264SManish Chopra 					    QED_FILTER_REMOVE) ?
1064cee4d264SManish Chopra 					   vport_to_remove_from :
1065cee4d264SManish Chopra 					   vport_to_add_to;
1066cee4d264SManish Chopra 	}
1067cee4d264SManish Chopra 
1068cee4d264SManish Chopra 	return 0;
1069cee4d264SManish Chopra }
1070cee4d264SManish Chopra 
1071dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1072cee4d264SManish Chopra 			    u16 opaque_fid,
1073cee4d264SManish Chopra 			    struct qed_filter_ucast *p_filter_cmd,
1074cee4d264SManish Chopra 			    enum spq_mode comp_mode,
1075cee4d264SManish Chopra 			    struct qed_spq_comp_cb *p_comp_data)
1076cee4d264SManish Chopra {
1077cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data	*p_ramrod	= NULL;
1078cee4d264SManish Chopra 	struct qed_spq_entry			*p_ent		= NULL;
1079cee4d264SManish Chopra 	struct eth_filter_cmd_header		*p_header;
1080cee4d264SManish Chopra 	int					rc;
1081cee4d264SManish Chopra 
1082cee4d264SManish Chopra 	rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1083cee4d264SManish Chopra 				     &p_ramrod, &p_ent,
1084cee4d264SManish Chopra 				     comp_mode, p_comp_data);
10851a635e48SYuval Mintz 	if (rc) {
1086cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1087cee4d264SManish Chopra 		return rc;
1088cee4d264SManish Chopra 	}
1089cee4d264SManish Chopra 	p_header = &p_ramrod->filter_cmd_hdr;
1090cee4d264SManish Chopra 	p_header->assert_on_error = p_filter_cmd->assert_on_error;
1091cee4d264SManish Chopra 
1092cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
10931a635e48SYuval Mintz 	if (rc) {
10941a635e48SYuval Mintz 		DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1095cee4d264SManish Chopra 		return rc;
1096cee4d264SManish Chopra 	}
1097cee4d264SManish Chopra 
1098cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1099cee4d264SManish Chopra 		   "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1100cee4d264SManish Chopra 		   (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1101cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1102cee4d264SManish Chopra 		   "REMOVE" :
1103cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1104cee4d264SManish Chopra 		    "MOVE" : "REPLACE")),
1105cee4d264SManish Chopra 		   (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1106cee4d264SManish Chopra 		   ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1107cee4d264SManish Chopra 		    "VLAN" : "MAC & VLAN"),
1108cee4d264SManish Chopra 		   p_ramrod->filter_cmd_hdr.cmd_cnt,
1109cee4d264SManish Chopra 		   p_filter_cmd->is_rx_filter,
1110cee4d264SManish Chopra 		   p_filter_cmd->is_tx_filter);
1111cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1112cee4d264SManish Chopra 		   "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1113cee4d264SManish Chopra 		   p_filter_cmd->vport_to_add_to,
1114cee4d264SManish Chopra 		   p_filter_cmd->vport_to_remove_from,
1115cee4d264SManish Chopra 		   p_filter_cmd->mac[0],
1116cee4d264SManish Chopra 		   p_filter_cmd->mac[1],
1117cee4d264SManish Chopra 		   p_filter_cmd->mac[2],
1118cee4d264SManish Chopra 		   p_filter_cmd->mac[3],
1119cee4d264SManish Chopra 		   p_filter_cmd->mac[4],
1120cee4d264SManish Chopra 		   p_filter_cmd->mac[5],
1121cee4d264SManish Chopra 		   p_filter_cmd->vlan);
1122cee4d264SManish Chopra 
1123cee4d264SManish Chopra 	return 0;
1124cee4d264SManish Chopra }
1125cee4d264SManish Chopra 
1126cee4d264SManish Chopra /*******************************************************************************
1127cee4d264SManish Chopra  * Description:
1128cee4d264SManish Chopra  *         Calculates crc 32 on a buffer
1129cee4d264SManish Chopra  *         Note: crc32_length MUST be aligned to 8
1130cee4d264SManish Chopra  * Return:
1131cee4d264SManish Chopra  ******************************************************************************/
1132cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet,
11331a635e48SYuval Mintz 			   u32 crc32_length, u32 crc32_seed, u8 complement)
1134cee4d264SManish Chopra {
11351a635e48SYuval Mintz 	u32 byte = 0, bit = 0, crc32_result = crc32_seed;
11361a635e48SYuval Mintz 	u8 msb = 0, current_byte = 0;
1137cee4d264SManish Chopra 
1138cee4d264SManish Chopra 	if ((!crc32_packet) ||
1139cee4d264SManish Chopra 	    (crc32_length == 0) ||
1140cee4d264SManish Chopra 	    ((crc32_length % 8) != 0))
1141cee4d264SManish Chopra 		return crc32_result;
1142cee4d264SManish Chopra 	for (byte = 0; byte < crc32_length; byte++) {
1143cee4d264SManish Chopra 		current_byte = crc32_packet[byte];
1144cee4d264SManish Chopra 		for (bit = 0; bit < 8; bit++) {
1145cee4d264SManish Chopra 			msb = (u8)(crc32_result >> 31);
1146cee4d264SManish Chopra 			crc32_result = crc32_result << 1;
1147cee4d264SManish Chopra 			if (msb != (0x1 & (current_byte >> bit))) {
1148cee4d264SManish Chopra 				crc32_result = crc32_result ^ CRC32_POLY;
1149cee4d264SManish Chopra 				crc32_result |= 1; /*crc32_result[0] = 1;*/
1150cee4d264SManish Chopra 			}
1151cee4d264SManish Chopra 		}
1152cee4d264SManish Chopra 	}
1153cee4d264SManish Chopra 	return crc32_result;
1154cee4d264SManish Chopra }
1155cee4d264SManish Chopra 
11561a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
1157cee4d264SManish Chopra {
1158cee4d264SManish Chopra 	u32 packet_buf[2] = { 0 };
1159cee4d264SManish Chopra 
1160cee4d264SManish Chopra 	memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1161cee4d264SManish Chopra 	return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1162cee4d264SManish Chopra }
1163cee4d264SManish Chopra 
1164dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac)
1165cee4d264SManish Chopra {
1166cee4d264SManish Chopra 	u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1167cee4d264SManish Chopra 				mac, ETH_ALEN);
1168cee4d264SManish Chopra 
1169cee4d264SManish Chopra 	return crc & 0xff;
1170cee4d264SManish Chopra }
1171cee4d264SManish Chopra 
1172cee4d264SManish Chopra static int
1173cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1174cee4d264SManish Chopra 			u16 opaque_fid,
1175cee4d264SManish Chopra 			struct qed_filter_mcast *p_filter_cmd,
1176cee4d264SManish Chopra 			enum spq_mode comp_mode,
1177cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1178cee4d264SManish Chopra {
1179cee4d264SManish Chopra 	unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1180cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
1181cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
118206f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1183cee4d264SManish Chopra 	u8 abs_vport_id = 0;
1184cee4d264SManish Chopra 	int rc, i;
1185cee4d264SManish Chopra 
118683aeb933SYuval Mintz 	if (p_filter_cmd->opcode == QED_FILTER_ADD)
1187cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1188cee4d264SManish Chopra 				  &abs_vport_id);
118983aeb933SYuval Mintz 	else
1190cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1191cee4d264SManish Chopra 				  &abs_vport_id);
1192cee4d264SManish Chopra 	if (rc)
1193cee4d264SManish Chopra 		return rc;
1194cee4d264SManish Chopra 
119506f56b81SYuval Mintz 	/* Get SPQ entry */
119606f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
119706f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
119806f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
119906f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
120006f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1201cee4d264SManish Chopra 
1202cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1203cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
120406f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1205cee4d264SManish Chopra 	if (rc) {
1206cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1207cee4d264SManish Chopra 		return rc;
1208cee4d264SManish Chopra 	}
1209cee4d264SManish Chopra 
1210cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
1211cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
1212cee4d264SManish Chopra 
1213cee4d264SManish Chopra 	/* explicitly clear out the entire vector */
1214cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
1215cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
1216cee4d264SManish Chopra 	memset(bins, 0, sizeof(unsigned long) *
1217cee4d264SManish Chopra 	       ETH_MULTICAST_MAC_BINS_IN_REGS);
1218cee4d264SManish Chopra 	/* filter ADD op is explicit set op and it removes
1219cee4d264SManish Chopra 	 *  any existing filters for the vport
1220cee4d264SManish Chopra 	 */
1221cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1222cee4d264SManish Chopra 		for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1223cee4d264SManish Chopra 			u32 bit;
1224cee4d264SManish Chopra 
1225cee4d264SManish Chopra 			bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1226cee4d264SManish Chopra 			__set_bit(bit, bins);
1227cee4d264SManish Chopra 		}
1228cee4d264SManish Chopra 
1229cee4d264SManish Chopra 		/* Convert to correct endianity */
1230cee4d264SManish Chopra 		for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
12311a635e48SYuval Mintz 			struct vport_update_ramrod_mcast *p_ramrod_bins;
1232cee4d264SManish Chopra 			u32 *p_bins = (u32 *)bins;
1233cee4d264SManish Chopra 
12341a635e48SYuval Mintz 			p_ramrod_bins = &p_ramrod->approx_mcast;
12351a635e48SYuval Mintz 			p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
1236cee4d264SManish Chopra 		}
1237cee4d264SManish Chopra 	}
1238cee4d264SManish Chopra 
1239cee4d264SManish Chopra 	p_ramrod->common.vport_id = abs_vport_id;
1240cee4d264SManish Chopra 
1241cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1242cee4d264SManish Chopra }
1243cee4d264SManish Chopra 
1244dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1245cee4d264SManish Chopra 				struct qed_filter_mcast *p_filter_cmd,
1246cee4d264SManish Chopra 				enum spq_mode comp_mode,
1247cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1248cee4d264SManish Chopra {
1249cee4d264SManish Chopra 	int rc = 0;
1250cee4d264SManish Chopra 	int i;
1251cee4d264SManish Chopra 
1252cee4d264SManish Chopra 	/* only ADD and REMOVE operations are supported for multi-cast */
1253cee4d264SManish Chopra 	if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1254cee4d264SManish Chopra 	     (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1255cee4d264SManish Chopra 	    (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1256cee4d264SManish Chopra 		return -EINVAL;
1257cee4d264SManish Chopra 
1258cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1259cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1260cee4d264SManish Chopra 
1261cee4d264SManish Chopra 		u16 opaque_fid;
1262cee4d264SManish Chopra 
1263dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1264dacd88d6SYuval Mintz 			qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1265dacd88d6SYuval Mintz 			continue;
1266dacd88d6SYuval Mintz 		}
1267cee4d264SManish Chopra 
1268cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1269cee4d264SManish Chopra 
1270cee4d264SManish Chopra 		rc = qed_sp_eth_filter_mcast(p_hwfn,
1271cee4d264SManish Chopra 					     opaque_fid,
1272cee4d264SManish Chopra 					     p_filter_cmd,
12731a635e48SYuval Mintz 					     comp_mode, p_comp_data);
1274cee4d264SManish Chopra 	}
1275cee4d264SManish Chopra 	return rc;
1276cee4d264SManish Chopra }
1277cee4d264SManish Chopra 
1278cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1279cee4d264SManish Chopra 				struct qed_filter_ucast *p_filter_cmd,
1280cee4d264SManish Chopra 				enum spq_mode comp_mode,
1281cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1282cee4d264SManish Chopra {
1283cee4d264SManish Chopra 	int rc = 0;
1284cee4d264SManish Chopra 	int i;
1285cee4d264SManish Chopra 
1286cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1287cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1288cee4d264SManish Chopra 		u16 opaque_fid;
1289cee4d264SManish Chopra 
1290dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1291dacd88d6SYuval Mintz 			rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1292dacd88d6SYuval Mintz 			continue;
1293dacd88d6SYuval Mintz 		}
1294cee4d264SManish Chopra 
1295cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1296cee4d264SManish Chopra 
1297cee4d264SManish Chopra 		rc = qed_sp_eth_filter_ucast(p_hwfn,
1298cee4d264SManish Chopra 					     opaque_fid,
1299cee4d264SManish Chopra 					     p_filter_cmd,
13001a635e48SYuval Mintz 					     comp_mode, p_comp_data);
13011a635e48SYuval Mintz 		if (rc)
1302dacd88d6SYuval Mintz 			break;
1303cee4d264SManish Chopra 	}
1304cee4d264SManish Chopra 
1305cee4d264SManish Chopra 	return rc;
1306cee4d264SManish Chopra }
1307cee4d264SManish Chopra 
130886622ee7SYuval Mintz /* Statistics related code */
130986622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
131086622ee7SYuval Mintz 					   u32 *p_addr,
1311dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
131286622ee7SYuval Mintz {
1313dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
131486622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_PSDM_RAM +
131586622ee7SYuval Mintz 		    PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
131686622ee7SYuval Mintz 		*p_len = sizeof(struct eth_pstorm_per_queue_stat);
1317dacd88d6SYuval Mintz 	} else {
1318dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1319dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1320dacd88d6SYuval Mintz 
1321dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1322dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.pstats.len;
1323dacd88d6SYuval Mintz 	}
132486622ee7SYuval Mintz }
132586622ee7SYuval Mintz 
132686622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
132786622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
132886622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
132986622ee7SYuval Mintz 				   u16 statistics_bin)
133086622ee7SYuval Mintz {
133186622ee7SYuval Mintz 	struct eth_pstorm_per_queue_stat pstats;
133286622ee7SYuval Mintz 	u32 pstats_addr = 0, pstats_len = 0;
133386622ee7SYuval Mintz 
133486622ee7SYuval Mintz 	__qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
133586622ee7SYuval Mintz 				       statistics_bin);
133686622ee7SYuval Mintz 
133786622ee7SYuval Mintz 	memset(&pstats, 0, sizeof(pstats));
1338dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
133986622ee7SYuval Mintz 
1340dacd88d6SYuval Mintz 	p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1341dacd88d6SYuval Mintz 	p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1342dacd88d6SYuval Mintz 	p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1343dacd88d6SYuval Mintz 	p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1344dacd88d6SYuval Mintz 	p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1345dacd88d6SYuval Mintz 	p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1346dacd88d6SYuval Mintz 	p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
134786622ee7SYuval Mintz }
134886622ee7SYuval Mintz 
134986622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
135086622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
135186622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
135286622ee7SYuval Mintz 				   u16 statistics_bin)
135386622ee7SYuval Mintz {
135486622ee7SYuval Mintz 	struct tstorm_per_port_stat tstats;
1355dacd88d6SYuval Mintz 	u32 tstats_addr, tstats_len;
135686622ee7SYuval Mintz 
1357dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
1358dacd88d6SYuval Mintz 		tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1359dacd88d6SYuval Mintz 		    TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1360dacd88d6SYuval Mintz 		tstats_len = sizeof(struct tstorm_per_port_stat);
1361dacd88d6SYuval Mintz 	} else {
1362dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1363dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1364dacd88d6SYuval Mintz 
1365dacd88d6SYuval Mintz 		tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1366dacd88d6SYuval Mintz 		tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1367dacd88d6SYuval Mintz 	}
136886622ee7SYuval Mintz 
136986622ee7SYuval Mintz 	memset(&tstats, 0, sizeof(tstats));
1370dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
137186622ee7SYuval Mintz 
137286622ee7SYuval Mintz 	p_stats->mftag_filter_discards +=
137386622ee7SYuval Mintz 		HILO_64_REGPAIR(tstats.mftag_filter_discard);
137486622ee7SYuval Mintz 	p_stats->mac_filter_discards +=
137586622ee7SYuval Mintz 		HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
137686622ee7SYuval Mintz }
137786622ee7SYuval Mintz 
137886622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
137986622ee7SYuval Mintz 					   u32 *p_addr,
1380dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
138186622ee7SYuval Mintz {
1382dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
138386622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_USDM_RAM +
138486622ee7SYuval Mintz 		    USTORM_QUEUE_STAT_OFFSET(statistics_bin);
138586622ee7SYuval Mintz 		*p_len = sizeof(struct eth_ustorm_per_queue_stat);
1386dacd88d6SYuval Mintz 	} else {
1387dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1388dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1389dacd88d6SYuval Mintz 
1390dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1391dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.ustats.len;
1392dacd88d6SYuval Mintz 	}
139386622ee7SYuval Mintz }
139486622ee7SYuval Mintz 
139586622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
139686622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
139786622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
139886622ee7SYuval Mintz 				   u16 statistics_bin)
139986622ee7SYuval Mintz {
140086622ee7SYuval Mintz 	struct eth_ustorm_per_queue_stat ustats;
140186622ee7SYuval Mintz 	u32 ustats_addr = 0, ustats_len = 0;
140286622ee7SYuval Mintz 
140386622ee7SYuval Mintz 	__qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
140486622ee7SYuval Mintz 				       statistics_bin);
140586622ee7SYuval Mintz 
140686622ee7SYuval Mintz 	memset(&ustats, 0, sizeof(ustats));
1407dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
140886622ee7SYuval Mintz 
1409dacd88d6SYuval Mintz 	p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1410dacd88d6SYuval Mintz 	p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1411dacd88d6SYuval Mintz 	p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1412dacd88d6SYuval Mintz 	p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1413dacd88d6SYuval Mintz 	p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1414dacd88d6SYuval Mintz 	p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
141586622ee7SYuval Mintz }
141686622ee7SYuval Mintz 
141786622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
141886622ee7SYuval Mintz 					   u32 *p_addr,
1419dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
142086622ee7SYuval Mintz {
1421dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
142286622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_MSDM_RAM +
142386622ee7SYuval Mintz 		    MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
142486622ee7SYuval Mintz 		*p_len = sizeof(struct eth_mstorm_per_queue_stat);
1425dacd88d6SYuval Mintz 	} else {
1426dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1427dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1428dacd88d6SYuval Mintz 
1429dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1430dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.mstats.len;
1431dacd88d6SYuval Mintz 	}
143286622ee7SYuval Mintz }
143386622ee7SYuval Mintz 
143486622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
143586622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
143686622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
143786622ee7SYuval Mintz 				   u16 statistics_bin)
143886622ee7SYuval Mintz {
143986622ee7SYuval Mintz 	struct eth_mstorm_per_queue_stat mstats;
144086622ee7SYuval Mintz 	u32 mstats_addr = 0, mstats_len = 0;
144186622ee7SYuval Mintz 
144286622ee7SYuval Mintz 	__qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
144386622ee7SYuval Mintz 				       statistics_bin);
144486622ee7SYuval Mintz 
144586622ee7SYuval Mintz 	memset(&mstats, 0, sizeof(mstats));
1446dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
144786622ee7SYuval Mintz 
1448dacd88d6SYuval Mintz 	p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
144986622ee7SYuval Mintz 	p_stats->packet_too_big_discard +=
145086622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.packet_too_big_discard);
1451dacd88d6SYuval Mintz 	p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
145286622ee7SYuval Mintz 	p_stats->tpa_coalesced_pkts +=
145386622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
145486622ee7SYuval Mintz 	p_stats->tpa_coalesced_events +=
145586622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1456dacd88d6SYuval Mintz 	p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
145786622ee7SYuval Mintz 	p_stats->tpa_coalesced_bytes +=
145886622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
145986622ee7SYuval Mintz }
146086622ee7SYuval Mintz 
146186622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
146286622ee7SYuval Mintz 				       struct qed_ptt *p_ptt,
146386622ee7SYuval Mintz 				       struct qed_eth_stats *p_stats)
146486622ee7SYuval Mintz {
146586622ee7SYuval Mintz 	struct port_stats port_stats;
146686622ee7SYuval Mintz 	int j;
146786622ee7SYuval Mintz 
146886622ee7SYuval Mintz 	memset(&port_stats, 0, sizeof(port_stats));
146986622ee7SYuval Mintz 
147086622ee7SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
147186622ee7SYuval Mintz 			p_hwfn->mcp_info->port_addr +
147286622ee7SYuval Mintz 			offsetof(struct public_port, stats),
147386622ee7SYuval Mintz 			sizeof(port_stats));
147486622ee7SYuval Mintz 
1475351a4dedSYuval Mintz 	p_stats->rx_64_byte_packets		+= port_stats.eth.r64;
1476351a4dedSYuval Mintz 	p_stats->rx_65_to_127_byte_packets	+= port_stats.eth.r127;
1477351a4dedSYuval Mintz 	p_stats->rx_128_to_255_byte_packets	+= port_stats.eth.r255;
1478351a4dedSYuval Mintz 	p_stats->rx_256_to_511_byte_packets	+= port_stats.eth.r511;
1479351a4dedSYuval Mintz 	p_stats->rx_512_to_1023_byte_packets	+= port_stats.eth.r1023;
1480351a4dedSYuval Mintz 	p_stats->rx_1024_to_1518_byte_packets	+= port_stats.eth.r1518;
1481351a4dedSYuval Mintz 	p_stats->rx_1519_to_1522_byte_packets	+= port_stats.eth.r1522;
1482351a4dedSYuval Mintz 	p_stats->rx_1519_to_2047_byte_packets	+= port_stats.eth.r2047;
1483351a4dedSYuval Mintz 	p_stats->rx_2048_to_4095_byte_packets	+= port_stats.eth.r4095;
1484351a4dedSYuval Mintz 	p_stats->rx_4096_to_9216_byte_packets	+= port_stats.eth.r9216;
1485351a4dedSYuval Mintz 	p_stats->rx_9217_to_16383_byte_packets	+= port_stats.eth.r16383;
1486351a4dedSYuval Mintz 	p_stats->rx_crc_errors			+= port_stats.eth.rfcs;
1487351a4dedSYuval Mintz 	p_stats->rx_mac_crtl_frames		+= port_stats.eth.rxcf;
1488351a4dedSYuval Mintz 	p_stats->rx_pause_frames		+= port_stats.eth.rxpf;
1489351a4dedSYuval Mintz 	p_stats->rx_pfc_frames			+= port_stats.eth.rxpp;
1490351a4dedSYuval Mintz 	p_stats->rx_align_errors		+= port_stats.eth.raln;
1491351a4dedSYuval Mintz 	p_stats->rx_carrier_errors		+= port_stats.eth.rfcr;
1492351a4dedSYuval Mintz 	p_stats->rx_oversize_packets		+= port_stats.eth.rovr;
1493351a4dedSYuval Mintz 	p_stats->rx_jabbers			+= port_stats.eth.rjbr;
1494351a4dedSYuval Mintz 	p_stats->rx_undersize_packets		+= port_stats.eth.rund;
1495351a4dedSYuval Mintz 	p_stats->rx_fragments			+= port_stats.eth.rfrg;
1496351a4dedSYuval Mintz 	p_stats->tx_64_byte_packets		+= port_stats.eth.t64;
1497351a4dedSYuval Mintz 	p_stats->tx_65_to_127_byte_packets	+= port_stats.eth.t127;
1498351a4dedSYuval Mintz 	p_stats->tx_128_to_255_byte_packets	+= port_stats.eth.t255;
1499351a4dedSYuval Mintz 	p_stats->tx_256_to_511_byte_packets	+= port_stats.eth.t511;
1500351a4dedSYuval Mintz 	p_stats->tx_512_to_1023_byte_packets	+= port_stats.eth.t1023;
1501351a4dedSYuval Mintz 	p_stats->tx_1024_to_1518_byte_packets	+= port_stats.eth.t1518;
1502351a4dedSYuval Mintz 	p_stats->tx_1519_to_2047_byte_packets	+= port_stats.eth.t2047;
1503351a4dedSYuval Mintz 	p_stats->tx_2048_to_4095_byte_packets	+= port_stats.eth.t4095;
1504351a4dedSYuval Mintz 	p_stats->tx_4096_to_9216_byte_packets	+= port_stats.eth.t9216;
1505351a4dedSYuval Mintz 	p_stats->tx_9217_to_16383_byte_packets	+= port_stats.eth.t16383;
1506351a4dedSYuval Mintz 	p_stats->tx_pause_frames		+= port_stats.eth.txpf;
1507351a4dedSYuval Mintz 	p_stats->tx_pfc_frames			+= port_stats.eth.txpp;
1508351a4dedSYuval Mintz 	p_stats->tx_lpi_entry_count		+= port_stats.eth.tlpiec;
1509351a4dedSYuval Mintz 	p_stats->tx_total_collisions		+= port_stats.eth.tncl;
1510351a4dedSYuval Mintz 	p_stats->rx_mac_bytes			+= port_stats.eth.rbyte;
1511351a4dedSYuval Mintz 	p_stats->rx_mac_uc_packets		+= port_stats.eth.rxuca;
1512351a4dedSYuval Mintz 	p_stats->rx_mac_mc_packets		+= port_stats.eth.rxmca;
1513351a4dedSYuval Mintz 	p_stats->rx_mac_bc_packets		+= port_stats.eth.rxbca;
1514351a4dedSYuval Mintz 	p_stats->rx_mac_frames_ok		+= port_stats.eth.rxpok;
1515351a4dedSYuval Mintz 	p_stats->tx_mac_bytes			+= port_stats.eth.tbyte;
1516351a4dedSYuval Mintz 	p_stats->tx_mac_uc_packets		+= port_stats.eth.txuca;
1517351a4dedSYuval Mintz 	p_stats->tx_mac_mc_packets		+= port_stats.eth.txmca;
1518351a4dedSYuval Mintz 	p_stats->tx_mac_bc_packets		+= port_stats.eth.txbca;
1519351a4dedSYuval Mintz 	p_stats->tx_mac_ctrl_frames		+= port_stats.eth.txcf;
152086622ee7SYuval Mintz 	for (j = 0; j < 8; j++) {
152186622ee7SYuval Mintz 		p_stats->brb_truncates	+= port_stats.brb.brb_truncate[j];
152286622ee7SYuval Mintz 		p_stats->brb_discards	+= port_stats.brb.brb_discard[j];
152386622ee7SYuval Mintz 	}
152486622ee7SYuval Mintz }
152586622ee7SYuval Mintz 
152686622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
152786622ee7SYuval Mintz 				  struct qed_ptt *p_ptt,
152886622ee7SYuval Mintz 				  struct qed_eth_stats *stats,
1529dacd88d6SYuval Mintz 				  u16 statistics_bin, bool b_get_port_stats)
153086622ee7SYuval Mintz {
153186622ee7SYuval Mintz 	__qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
153286622ee7SYuval Mintz 	__qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
153386622ee7SYuval Mintz 	__qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
153486622ee7SYuval Mintz 	__qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
153586622ee7SYuval Mintz 
1536dacd88d6SYuval Mintz 	if (b_get_port_stats && p_hwfn->mcp_info)
153786622ee7SYuval Mintz 		__qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
153886622ee7SYuval Mintz }
153986622ee7SYuval Mintz 
154086622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev,
154186622ee7SYuval Mintz 				 struct qed_eth_stats *stats)
154286622ee7SYuval Mintz {
154386622ee7SYuval Mintz 	u8 fw_vport = 0;
154486622ee7SYuval Mintz 	int i;
154586622ee7SYuval Mintz 
154686622ee7SYuval Mintz 	memset(stats, 0, sizeof(*stats));
154786622ee7SYuval Mintz 
154886622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
154986622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1550dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1551dacd88d6SYuval Mintz 						    :  NULL;
155286622ee7SYuval Mintz 
1553dacd88d6SYuval Mintz 		if (IS_PF(cdev)) {
155486622ee7SYuval Mintz 			/* The main vport index is relative first */
155586622ee7SYuval Mintz 			if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
155686622ee7SYuval Mintz 				DP_ERR(p_hwfn, "No vport available!\n");
1557dacd88d6SYuval Mintz 				goto out;
1558dacd88d6SYuval Mintz 			}
155986622ee7SYuval Mintz 		}
156086622ee7SYuval Mintz 
1561dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
156286622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
156386622ee7SYuval Mintz 			continue;
156486622ee7SYuval Mintz 		}
156586622ee7SYuval Mintz 
1566dacd88d6SYuval Mintz 		__qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1567dacd88d6SYuval Mintz 				      IS_PF(cdev) ? true : false);
156886622ee7SYuval Mintz 
1569dacd88d6SYuval Mintz out:
1570dacd88d6SYuval Mintz 		if (IS_PF(cdev) && p_ptt)
157186622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
157286622ee7SYuval Mintz 	}
157386622ee7SYuval Mintz }
157486622ee7SYuval Mintz 
15751a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
157686622ee7SYuval Mintz {
157786622ee7SYuval Mintz 	u32 i;
157886622ee7SYuval Mintz 
157986622ee7SYuval Mintz 	if (!cdev) {
158086622ee7SYuval Mintz 		memset(stats, 0, sizeof(*stats));
158186622ee7SYuval Mintz 		return;
158286622ee7SYuval Mintz 	}
158386622ee7SYuval Mintz 
158486622ee7SYuval Mintz 	_qed_get_vport_stats(cdev, stats);
158586622ee7SYuval Mintz 
158686622ee7SYuval Mintz 	if (!cdev->reset_stats)
158786622ee7SYuval Mintz 		return;
158886622ee7SYuval Mintz 
158986622ee7SYuval Mintz 	/* Reduce the statistics baseline */
159086622ee7SYuval Mintz 	for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
159186622ee7SYuval Mintz 		((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
159286622ee7SYuval Mintz }
159386622ee7SYuval Mintz 
159486622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
159586622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev)
159686622ee7SYuval Mintz {
159786622ee7SYuval Mintz 	int i;
159886622ee7SYuval Mintz 
159986622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
160086622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
160186622ee7SYuval Mintz 		struct eth_mstorm_per_queue_stat mstats;
160286622ee7SYuval Mintz 		struct eth_ustorm_per_queue_stat ustats;
160386622ee7SYuval Mintz 		struct eth_pstorm_per_queue_stat pstats;
1604dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1605dacd88d6SYuval Mintz 						    : NULL;
160686622ee7SYuval Mintz 		u32 addr = 0, len = 0;
160786622ee7SYuval Mintz 
1608dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
160986622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
161086622ee7SYuval Mintz 			continue;
161186622ee7SYuval Mintz 		}
161286622ee7SYuval Mintz 
161386622ee7SYuval Mintz 		memset(&mstats, 0, sizeof(mstats));
161486622ee7SYuval Mintz 		__qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
161586622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
161686622ee7SYuval Mintz 
161786622ee7SYuval Mintz 		memset(&ustats, 0, sizeof(ustats));
161886622ee7SYuval Mintz 		__qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
161986622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
162086622ee7SYuval Mintz 
162186622ee7SYuval Mintz 		memset(&pstats, 0, sizeof(pstats));
162286622ee7SYuval Mintz 		__qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
162386622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
162486622ee7SYuval Mintz 
1625dacd88d6SYuval Mintz 		if (IS_PF(cdev))
162686622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
162786622ee7SYuval Mintz 	}
162886622ee7SYuval Mintz 
162986622ee7SYuval Mintz 	/* PORT statistics are not necessarily reset, so we need to
163086622ee7SYuval Mintz 	 * read and create a baseline for future statistics.
163186622ee7SYuval Mintz 	 */
163286622ee7SYuval Mintz 	if (!cdev->reset_stats)
163386622ee7SYuval Mintz 		DP_INFO(cdev, "Reset stats not allocated\n");
163486622ee7SYuval Mintz 	else
163586622ee7SYuval Mintz 		_qed_get_vport_stats(cdev, cdev->reset_stats);
163686622ee7SYuval Mintz }
163786622ee7SYuval Mintz 
163825c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev,
163925c089d7SYuval Mintz 				 struct qed_dev_eth_info *info)
164025c089d7SYuval Mintz {
164125c089d7SYuval Mintz 	int i;
164225c089d7SYuval Mintz 
164325c089d7SYuval Mintz 	memset(info, 0, sizeof(*info));
164425c089d7SYuval Mintz 
164525c089d7SYuval Mintz 	info->num_tc = 1;
164625c089d7SYuval Mintz 
16471408cc1fSYuval Mintz 	if (IS_PF(cdev)) {
164825eb8d46SYuval Mintz 		int max_vf_vlan_filters = 0;
164925eb8d46SYuval Mintz 
165025c089d7SYuval Mintz 		if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
165125c089d7SYuval Mintz 			for_each_hwfn(cdev, i)
16521408cc1fSYuval Mintz 			    info->num_queues +=
16531408cc1fSYuval Mintz 			    FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
165425c089d7SYuval Mintz 			if (cdev->int_params.fp_msix_cnt)
16551408cc1fSYuval Mintz 				info->num_queues =
16561408cc1fSYuval Mintz 				    min_t(u8, info->num_queues,
165725c089d7SYuval Mintz 					  cdev->int_params.fp_msix_cnt);
165825c089d7SYuval Mintz 		} else {
165925c089d7SYuval Mintz 			info->num_queues = cdev->num_hwfns;
166025c089d7SYuval Mintz 		}
166125c089d7SYuval Mintz 
166225eb8d46SYuval Mintz 		if (IS_QED_SRIOV(cdev))
166325eb8d46SYuval Mintz 			max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
166425eb8d46SYuval Mintz 					      QED_ETH_VF_NUM_VLAN_FILTERS;
166525eb8d46SYuval Mintz 		info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN) -
166625eb8d46SYuval Mintz 					 max_vf_vlan_filters;
166725eb8d46SYuval Mintz 
166825c089d7SYuval Mintz 		ether_addr_copy(info->port_mac,
166925c089d7SYuval Mintz 				cdev->hwfns[0].hw_info.hw_mac_addr);
16701408cc1fSYuval Mintz 	} else {
16711408cc1fSYuval Mintz 		qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
16721408cc1fSYuval Mintz 		if (cdev->num_hwfns > 1) {
16731408cc1fSYuval Mintz 			u8 queues = 0;
16741408cc1fSYuval Mintz 
16751408cc1fSYuval Mintz 			qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
16761408cc1fSYuval Mintz 			info->num_queues += queues;
16771408cc1fSYuval Mintz 		}
16781408cc1fSYuval Mintz 
16791408cc1fSYuval Mintz 		qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
16801408cc1fSYuval Mintz 					    &info->num_vlan_filters);
16811408cc1fSYuval Mintz 		qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
16821408cc1fSYuval Mintz 	}
168325c089d7SYuval Mintz 
168425c089d7SYuval Mintz 	qed_fill_dev_info(cdev, &info->common);
168525c089d7SYuval Mintz 
16861408cc1fSYuval Mintz 	if (IS_VF(cdev))
16871408cc1fSYuval Mintz 		memset(info->common.hw_mac, 0, ETH_ALEN);
16881408cc1fSYuval Mintz 
168925c089d7SYuval Mintz 	return 0;
169025c089d7SYuval Mintz }
169125c089d7SYuval Mintz 
1692cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev,
16931408cc1fSYuval Mintz 				 struct qed_eth_cb_ops *ops, void *cookie)
1694cc875c2eSYuval Mintz {
1695cc875c2eSYuval Mintz 	cdev->protocol_ops.eth = ops;
1696cc875c2eSYuval Mintz 	cdev->ops_cookie = cookie;
16971408cc1fSYuval Mintz 
16981408cc1fSYuval Mintz 	/* For VF, we start bulletin reading */
16991408cc1fSYuval Mintz 	if (IS_VF(cdev))
17001408cc1fSYuval Mintz 		qed_vf_start_iov_wq(cdev);
1701cc875c2eSYuval Mintz }
1702cc875c2eSYuval Mintz 
1703eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
1704eff16960SYuval Mintz {
1705eff16960SYuval Mintz 	if (IS_PF(cdev))
1706eff16960SYuval Mintz 		return true;
1707eff16960SYuval Mintz 
1708eff16960SYuval Mintz 	return qed_vf_check_mac(&cdev->hwfns[0], mac);
1709eff16960SYuval Mintz }
1710eff16960SYuval Mintz 
1711cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev,
1712088c8618SManish Chopra 			   struct qed_start_vport_params *params)
1713cee4d264SManish Chopra {
1714cee4d264SManish Chopra 	int rc, i;
1715cee4d264SManish Chopra 
1716cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1717088c8618SManish Chopra 		struct qed_sp_vport_start_params start = { 0 };
1718cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1719cee4d264SManish Chopra 
1720088c8618SManish Chopra 		start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1721088c8618SManish Chopra 							QED_TPA_MODE_NONE;
1722088c8618SManish Chopra 		start.remove_inner_vlan = params->remove_inner_vlan;
172308feecd7SYuval Mintz 		start.only_untagged = true;	/* untagged only */
1724088c8618SManish Chopra 		start.drop_ttl0 = params->drop_ttl0;
1725088c8618SManish Chopra 		start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1726088c8618SManish Chopra 		start.concrete_fid = p_hwfn->hw_info.concrete_fid;
1727088c8618SManish Chopra 		start.vport_id = params->vport_id;
1728088c8618SManish Chopra 		start.max_buffers_per_cqe = 16;
1729088c8618SManish Chopra 		start.mtu = params->mtu;
1730cee4d264SManish Chopra 
1731088c8618SManish Chopra 		rc = qed_sp_vport_start(p_hwfn, &start);
1732cee4d264SManish Chopra 		if (rc) {
1733cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to start VPORT\n");
1734cee4d264SManish Chopra 			return rc;
1735cee4d264SManish Chopra 		}
1736cee4d264SManish Chopra 
1737cee4d264SManish Chopra 		qed_hw_start_fastpath(p_hwfn);
1738cee4d264SManish Chopra 
1739cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1740cee4d264SManish Chopra 			   "Started V-PORT %d with MTU %d\n",
1741088c8618SManish Chopra 			   start.vport_id, start.mtu);
1742cee4d264SManish Chopra 	}
1743cee4d264SManish Chopra 
1744a0d26d5aSYuval Mintz 	if (params->clear_stats)
17459df2ed04SManish Chopra 		qed_reset_vport_stats(cdev);
17469df2ed04SManish Chopra 
1747cee4d264SManish Chopra 	return 0;
1748cee4d264SManish Chopra }
1749cee4d264SManish Chopra 
17501a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
1751cee4d264SManish Chopra {
1752cee4d264SManish Chopra 	int rc, i;
1753cee4d264SManish Chopra 
1754cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1755cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1756cee4d264SManish Chopra 
1757cee4d264SManish Chopra 		rc = qed_sp_vport_stop(p_hwfn,
17581a635e48SYuval Mintz 				       p_hwfn->hw_info.opaque_fid, vport_id);
1759cee4d264SManish Chopra 
1760cee4d264SManish Chopra 		if (rc) {
1761cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to stop VPORT\n");
1762cee4d264SManish Chopra 			return rc;
1763cee4d264SManish Chopra 		}
1764cee4d264SManish Chopra 	}
1765cee4d264SManish Chopra 	return 0;
1766cee4d264SManish Chopra }
1767cee4d264SManish Chopra 
1768cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev,
1769cee4d264SManish Chopra 			    struct qed_update_vport_params *params)
1770cee4d264SManish Chopra {
1771cee4d264SManish Chopra 	struct qed_sp_vport_update_params sp_params;
1772cee4d264SManish Chopra 	struct qed_rss_params sp_rss_params;
1773cee4d264SManish Chopra 	int rc, i;
1774cee4d264SManish Chopra 
1775cee4d264SManish Chopra 	if (!cdev)
1776cee4d264SManish Chopra 		return -ENODEV;
1777cee4d264SManish Chopra 
1778cee4d264SManish Chopra 	memset(&sp_params, 0, sizeof(sp_params));
1779cee4d264SManish Chopra 	memset(&sp_rss_params, 0, sizeof(sp_rss_params));
1780cee4d264SManish Chopra 
1781cee4d264SManish Chopra 	/* Translate protocol params into sp params */
1782cee4d264SManish Chopra 	sp_params.vport_id = params->vport_id;
17831a635e48SYuval Mintz 	sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
17841a635e48SYuval Mintz 	sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
1785cee4d264SManish Chopra 	sp_params.vport_active_rx_flg = params->vport_active_flg;
1786cee4d264SManish Chopra 	sp_params.vport_active_tx_flg = params->vport_active_flg;
1787831bfb0eSYuval Mintz 	sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
1788831bfb0eSYuval Mintz 	sp_params.tx_switching_flg = params->tx_switching_flg;
17893f9b4a69SYuval Mintz 	sp_params.accept_any_vlan = params->accept_any_vlan;
17903f9b4a69SYuval Mintz 	sp_params.update_accept_any_vlan_flg =
17913f9b4a69SYuval Mintz 		params->update_accept_any_vlan_flg;
1792cee4d264SManish Chopra 
1793cee4d264SManish Chopra 	/* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
1794cee4d264SManish Chopra 	 * We need to re-fix the rss values per engine for CMT.
1795cee4d264SManish Chopra 	 */
1796cee4d264SManish Chopra 	if (cdev->num_hwfns > 1 && params->update_rss_flg) {
17971a635e48SYuval Mintz 		struct qed_update_vport_rss_params *rss = &params->rss_params;
1798cee4d264SManish Chopra 		int k, max = 0;
1799cee4d264SManish Chopra 
1800cee4d264SManish Chopra 		/* Find largest entry, since it's possible RSS needs to
1801cee4d264SManish Chopra 		 * be disabled [in case only 1 queue per-hwfn]
1802cee4d264SManish Chopra 		 */
1803cee4d264SManish Chopra 		for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1804cee4d264SManish Chopra 			max = (max > rss->rss_ind_table[k]) ?
1805cee4d264SManish Chopra 				max : rss->rss_ind_table[k];
1806cee4d264SManish Chopra 
1807cee4d264SManish Chopra 		/* Either fix RSS values or disable RSS */
1808cee4d264SManish Chopra 		if (cdev->num_hwfns < max + 1) {
1809cee4d264SManish Chopra 			int divisor = (max + cdev->num_hwfns - 1) /
1810cee4d264SManish Chopra 				cdev->num_hwfns;
1811cee4d264SManish Chopra 
1812cee4d264SManish Chopra 			DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1813cee4d264SManish Chopra 				   "CMT - fixing RSS values (modulo %02x)\n",
1814cee4d264SManish Chopra 				   divisor);
1815cee4d264SManish Chopra 
1816cee4d264SManish Chopra 			for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1817cee4d264SManish Chopra 				rss->rss_ind_table[k] =
1818cee4d264SManish Chopra 					rss->rss_ind_table[k] % divisor;
1819cee4d264SManish Chopra 		} else {
1820cee4d264SManish Chopra 			DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1821cee4d264SManish Chopra 				   "CMT - 1 queue per-hwfn; Disabling RSS\n");
1822cee4d264SManish Chopra 			params->update_rss_flg = 0;
1823cee4d264SManish Chopra 		}
1824cee4d264SManish Chopra 	}
1825cee4d264SManish Chopra 
1826cee4d264SManish Chopra 	/* Now, update the RSS configuration for actual configuration */
1827cee4d264SManish Chopra 	if (params->update_rss_flg) {
1828cee4d264SManish Chopra 		sp_rss_params.update_rss_config = 1;
1829cee4d264SManish Chopra 		sp_rss_params.rss_enable = 1;
1830cee4d264SManish Chopra 		sp_rss_params.update_rss_capabilities = 1;
1831cee4d264SManish Chopra 		sp_rss_params.update_rss_ind_table = 1;
1832cee4d264SManish Chopra 		sp_rss_params.update_rss_key = 1;
18338c5ebd0cSSudarsana Reddy Kalluru 		sp_rss_params.rss_caps = params->rss_params.rss_caps;
1834cee4d264SManish Chopra 		sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
1835cee4d264SManish Chopra 		memcpy(sp_rss_params.rss_ind_table,
1836cee4d264SManish Chopra 		       params->rss_params.rss_ind_table,
1837cee4d264SManish Chopra 		       QED_RSS_IND_TABLE_SIZE * sizeof(u16));
1838cee4d264SManish Chopra 		memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
1839cee4d264SManish Chopra 		       QED_RSS_KEY_SIZE * sizeof(u32));
1840cee4d264SManish Chopra 		sp_params.rss_params = &sp_rss_params;
184183aeb933SYuval Mintz 	}
1842cee4d264SManish Chopra 
1843cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1844cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1845cee4d264SManish Chopra 
1846cee4d264SManish Chopra 		sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1847cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &sp_params,
1848cee4d264SManish Chopra 					 QED_SPQ_MODE_EBLOCK,
1849cee4d264SManish Chopra 					 NULL);
1850cee4d264SManish Chopra 		if (rc) {
1851cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to update VPORT\n");
1852cee4d264SManish Chopra 			return rc;
1853cee4d264SManish Chopra 		}
1854cee4d264SManish Chopra 
1855cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1856cee4d264SManish Chopra 			   "Updated V-PORT %d: active_flag %d [update %d]\n",
1857cee4d264SManish Chopra 			   params->vport_id, params->vport_active_flg,
1858cee4d264SManish Chopra 			   params->update_vport_active_flg);
1859cee4d264SManish Chopra 	}
1860cee4d264SManish Chopra 
1861cee4d264SManish Chopra 	return 0;
1862cee4d264SManish Chopra }
1863cee4d264SManish Chopra 
1864cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev,
1865cee4d264SManish Chopra 			 struct qed_queue_start_common_params *params,
1866cee4d264SManish Chopra 			 u16 bd_max_bytes,
1867cee4d264SManish Chopra 			 dma_addr_t bd_chain_phys_addr,
1868cee4d264SManish Chopra 			 dma_addr_t cqe_pbl_addr,
1869cee4d264SManish Chopra 			 u16 cqe_pbl_size,
1870cee4d264SManish Chopra 			 void __iomem **pp_prod)
1871cee4d264SManish Chopra {
1872cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
18731a635e48SYuval Mintz 	int rc, hwfn_index;
1874cee4d264SManish Chopra 
1875cee4d264SManish Chopra 	hwfn_index = params->rss_id % cdev->num_hwfns;
1876cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
1877cee4d264SManish Chopra 
1878cee4d264SManish Chopra 	/* Fix queue ID in 100g mode */
1879cee4d264SManish Chopra 	params->queue_id /= cdev->num_hwfns;
1880cee4d264SManish Chopra 
1881cee4d264SManish Chopra 	rc = qed_sp_eth_rx_queue_start(p_hwfn,
1882cee4d264SManish Chopra 				       p_hwfn->hw_info.opaque_fid,
1883cee4d264SManish Chopra 				       params,
1884cee4d264SManish Chopra 				       bd_max_bytes,
1885cee4d264SManish Chopra 				       bd_chain_phys_addr,
1886cee4d264SManish Chopra 				       cqe_pbl_addr,
1887cee4d264SManish Chopra 				       cqe_pbl_size,
1888cee4d264SManish Chopra 				       pp_prod);
1889cee4d264SManish Chopra 
1890cee4d264SManish Chopra 	if (rc) {
1891cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
1892cee4d264SManish Chopra 		return rc;
1893cee4d264SManish Chopra 	}
1894cee4d264SManish Chopra 
1895cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1896cee4d264SManish Chopra 		   "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1897cee4d264SManish Chopra 		   params->queue_id, params->rss_id, params->vport_id,
1898cee4d264SManish Chopra 		   params->sb);
1899cee4d264SManish Chopra 
1900cee4d264SManish Chopra 	return 0;
1901cee4d264SManish Chopra }
1902cee4d264SManish Chopra 
1903cee4d264SManish Chopra static int qed_stop_rxq(struct qed_dev *cdev,
1904cee4d264SManish Chopra 			struct qed_stop_rxq_params *params)
1905cee4d264SManish Chopra {
1906cee4d264SManish Chopra 	int rc, hwfn_index;
1907cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
1908cee4d264SManish Chopra 
1909cee4d264SManish Chopra 	hwfn_index	= params->rss_id % cdev->num_hwfns;
1910cee4d264SManish Chopra 	p_hwfn		= &cdev->hwfns[hwfn_index];
1911cee4d264SManish Chopra 
1912cee4d264SManish Chopra 	rc = qed_sp_eth_rx_queue_stop(p_hwfn,
1913cee4d264SManish Chopra 				      params->rx_queue_id / cdev->num_hwfns,
19141a635e48SYuval Mintz 				      params->eq_completion_only, false);
1915cee4d264SManish Chopra 	if (rc) {
1916cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
1917cee4d264SManish Chopra 		return rc;
1918cee4d264SManish Chopra 	}
1919cee4d264SManish Chopra 
1920cee4d264SManish Chopra 	return 0;
1921cee4d264SManish Chopra }
1922cee4d264SManish Chopra 
1923cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev,
1924cee4d264SManish Chopra 			 struct qed_queue_start_common_params *p_params,
1925cee4d264SManish Chopra 			 dma_addr_t pbl_addr,
1926cee4d264SManish Chopra 			 u16 pbl_size,
1927cee4d264SManish Chopra 			 void __iomem **pp_doorbell)
1928cee4d264SManish Chopra {
1929cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
1930cee4d264SManish Chopra 	int rc, hwfn_index;
1931cee4d264SManish Chopra 
1932cee4d264SManish Chopra 	hwfn_index	= p_params->rss_id % cdev->num_hwfns;
1933cee4d264SManish Chopra 	p_hwfn		= &cdev->hwfns[hwfn_index];
1934cee4d264SManish Chopra 
1935cee4d264SManish Chopra 	/* Fix queue ID in 100g mode */
1936cee4d264SManish Chopra 	p_params->queue_id /= cdev->num_hwfns;
1937cee4d264SManish Chopra 
1938cee4d264SManish Chopra 	rc = qed_sp_eth_tx_queue_start(p_hwfn,
1939cee4d264SManish Chopra 				       p_hwfn->hw_info.opaque_fid,
1940cee4d264SManish Chopra 				       p_params,
1941cee4d264SManish Chopra 				       pbl_addr,
1942cee4d264SManish Chopra 				       pbl_size,
1943cee4d264SManish Chopra 				       pp_doorbell);
1944cee4d264SManish Chopra 
1945cee4d264SManish Chopra 	if (rc) {
1946cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
1947cee4d264SManish Chopra 		return rc;
1948cee4d264SManish Chopra 	}
1949cee4d264SManish Chopra 
1950cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1951cee4d264SManish Chopra 		   "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1952cee4d264SManish Chopra 		   p_params->queue_id, p_params->rss_id, p_params->vport_id,
1953cee4d264SManish Chopra 		   p_params->sb);
1954cee4d264SManish Chopra 
1955cee4d264SManish Chopra 	return 0;
1956cee4d264SManish Chopra }
1957cee4d264SManish Chopra 
1958cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10)
1959cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev)
1960cee4d264SManish Chopra {
1961cee4d264SManish Chopra 	qed_hw_stop_fastpath(cdev);
1962cee4d264SManish Chopra 
1963cee4d264SManish Chopra 	return 0;
1964cee4d264SManish Chopra }
1965cee4d264SManish Chopra 
1966cee4d264SManish Chopra static int qed_stop_txq(struct qed_dev *cdev,
1967cee4d264SManish Chopra 			struct qed_stop_txq_params *params)
1968cee4d264SManish Chopra {
1969cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
1970cee4d264SManish Chopra 	int rc, hwfn_index;
1971cee4d264SManish Chopra 
1972cee4d264SManish Chopra 	hwfn_index	= params->rss_id % cdev->num_hwfns;
1973cee4d264SManish Chopra 	p_hwfn		= &cdev->hwfns[hwfn_index];
1974cee4d264SManish Chopra 
1975cee4d264SManish Chopra 	rc = qed_sp_eth_tx_queue_stop(p_hwfn,
1976cee4d264SManish Chopra 				      params->tx_queue_id / cdev->num_hwfns);
1977cee4d264SManish Chopra 	if (rc) {
1978cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
1979cee4d264SManish Chopra 		return rc;
1980cee4d264SManish Chopra 	}
1981cee4d264SManish Chopra 
1982cee4d264SManish Chopra 	return 0;
1983cee4d264SManish Chopra }
1984cee4d264SManish Chopra 
1985464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev,
1986464f6645SManish Chopra 			      struct qed_tunn_params *tunn_params)
1987464f6645SManish Chopra {
1988464f6645SManish Chopra 	struct qed_tunn_update_params tunn_info;
1989464f6645SManish Chopra 	int i, rc;
1990464f6645SManish Chopra 
19911408cc1fSYuval Mintz 	if (IS_VF(cdev))
19921408cc1fSYuval Mintz 		return 0;
19931408cc1fSYuval Mintz 
1994464f6645SManish Chopra 	memset(&tunn_info, 0, sizeof(tunn_info));
1995464f6645SManish Chopra 	if (tunn_params->update_vxlan_port == 1) {
1996464f6645SManish Chopra 		tunn_info.update_vxlan_udp_port = 1;
1997464f6645SManish Chopra 		tunn_info.vxlan_udp_port = tunn_params->vxlan_port;
1998464f6645SManish Chopra 	}
1999464f6645SManish Chopra 
2000464f6645SManish Chopra 	if (tunn_params->update_geneve_port == 1) {
2001464f6645SManish Chopra 		tunn_info.update_geneve_udp_port = 1;
2002464f6645SManish Chopra 		tunn_info.geneve_udp_port = tunn_params->geneve_port;
2003464f6645SManish Chopra 	}
2004464f6645SManish Chopra 
2005464f6645SManish Chopra 	for_each_hwfn(cdev, i) {
2006464f6645SManish Chopra 		struct qed_hwfn *hwfn = &cdev->hwfns[i];
2007464f6645SManish Chopra 
2008464f6645SManish Chopra 		rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
2009464f6645SManish Chopra 					       QED_SPQ_MODE_EBLOCK, NULL);
2010464f6645SManish Chopra 
2011464f6645SManish Chopra 		if (rc)
2012464f6645SManish Chopra 			return rc;
2013464f6645SManish Chopra 	}
2014464f6645SManish Chopra 
2015464f6645SManish Chopra 	return 0;
2016464f6645SManish Chopra }
2017464f6645SManish Chopra 
2018cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2019cee4d264SManish Chopra 					enum qed_filter_rx_mode_type type)
2020cee4d264SManish Chopra {
2021cee4d264SManish Chopra 	struct qed_filter_accept_flags accept_flags;
2022cee4d264SManish Chopra 
2023cee4d264SManish Chopra 	memset(&accept_flags, 0, sizeof(accept_flags));
2024cee4d264SManish Chopra 
2025cee4d264SManish Chopra 	accept_flags.update_rx_mode_config = 1;
2026cee4d264SManish Chopra 	accept_flags.update_tx_mode_config = 1;
2027cee4d264SManish Chopra 	accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2028cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2029cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2030cee4d264SManish Chopra 	accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2031cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2032cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2033cee4d264SManish Chopra 
2034cee4d264SManish Chopra 	if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
2035cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2036cee4d264SManish Chopra 						 QED_ACCEPT_MCAST_UNMATCHED;
2037cee4d264SManish Chopra 	else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
2038cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2039cee4d264SManish Chopra 
20403f9b4a69SYuval Mintz 	return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
2041cee4d264SManish Chopra 				     QED_SPQ_MODE_CB, NULL);
2042cee4d264SManish Chopra }
2043cee4d264SManish Chopra 
2044cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev,
2045cee4d264SManish Chopra 				      struct qed_filter_ucast_params *params)
2046cee4d264SManish Chopra {
2047cee4d264SManish Chopra 	struct qed_filter_ucast ucast;
2048cee4d264SManish Chopra 
2049cee4d264SManish Chopra 	if (!params->vlan_valid && !params->mac_valid) {
20501a635e48SYuval Mintz 		DP_NOTICE(cdev,
2051cee4d264SManish Chopra 			  "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
2052cee4d264SManish Chopra 		return -EINVAL;
2053cee4d264SManish Chopra 	}
2054cee4d264SManish Chopra 
2055cee4d264SManish Chopra 	memset(&ucast, 0, sizeof(ucast));
2056cee4d264SManish Chopra 	switch (params->type) {
2057cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2058cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_ADD;
2059cee4d264SManish Chopra 		break;
2060cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2061cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REMOVE;
2062cee4d264SManish Chopra 		break;
2063cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_REPLACE:
2064cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REPLACE;
2065cee4d264SManish Chopra 		break;
2066cee4d264SManish Chopra 	default:
2067cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2068cee4d264SManish Chopra 			  params->type);
2069cee4d264SManish Chopra 	}
2070cee4d264SManish Chopra 
2071cee4d264SManish Chopra 	if (params->vlan_valid && params->mac_valid) {
2072cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC_VLAN;
2073cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2074cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2075cee4d264SManish Chopra 	} else if (params->mac_valid) {
2076cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC;
2077cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2078cee4d264SManish Chopra 	} else {
2079cee4d264SManish Chopra 		ucast.type = QED_FILTER_VLAN;
2080cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2081cee4d264SManish Chopra 	}
2082cee4d264SManish Chopra 
2083cee4d264SManish Chopra 	ucast.is_rx_filter = true;
2084cee4d264SManish Chopra 	ucast.is_tx_filter = true;
2085cee4d264SManish Chopra 
2086cee4d264SManish Chopra 	return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2087cee4d264SManish Chopra }
2088cee4d264SManish Chopra 
2089cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev,
2090cee4d264SManish Chopra 				      struct qed_filter_mcast_params *params)
2091cee4d264SManish Chopra {
2092cee4d264SManish Chopra 	struct qed_filter_mcast mcast;
2093cee4d264SManish Chopra 	int i;
2094cee4d264SManish Chopra 
2095cee4d264SManish Chopra 	memset(&mcast, 0, sizeof(mcast));
2096cee4d264SManish Chopra 	switch (params->type) {
2097cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2098cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_ADD;
2099cee4d264SManish Chopra 		break;
2100cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2101cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_REMOVE;
2102cee4d264SManish Chopra 		break;
2103cee4d264SManish Chopra 	default:
2104cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2105cee4d264SManish Chopra 			  params->type);
2106cee4d264SManish Chopra 	}
2107cee4d264SManish Chopra 
2108cee4d264SManish Chopra 	mcast.num_mc_addrs = params->num;
2109cee4d264SManish Chopra 	for (i = 0; i < mcast.num_mc_addrs; i++)
2110cee4d264SManish Chopra 		ether_addr_copy(mcast.mac[i], params->mac[i]);
2111cee4d264SManish Chopra 
21121a635e48SYuval Mintz 	return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
2113cee4d264SManish Chopra }
2114cee4d264SManish Chopra 
2115cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev,
2116cee4d264SManish Chopra 				struct qed_filter_params *params)
2117cee4d264SManish Chopra {
2118cee4d264SManish Chopra 	enum qed_filter_rx_mode_type accept_flags;
2119cee4d264SManish Chopra 
2120cee4d264SManish Chopra 	switch (params->type) {
2121cee4d264SManish Chopra 	case QED_FILTER_TYPE_UCAST:
2122cee4d264SManish Chopra 		return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2123cee4d264SManish Chopra 	case QED_FILTER_TYPE_MCAST:
2124cee4d264SManish Chopra 		return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2125cee4d264SManish Chopra 	case QED_FILTER_TYPE_RX_MODE:
2126cee4d264SManish Chopra 		accept_flags = params->filter.accept_flags;
2127cee4d264SManish Chopra 		return qed_configure_filter_rx_mode(cdev, accept_flags);
2128cee4d264SManish Chopra 	default:
21291a635e48SYuval Mintz 		DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
2130cee4d264SManish Chopra 		return -EINVAL;
2131cee4d264SManish Chopra 	}
2132cee4d264SManish Chopra }
2133cee4d264SManish Chopra 
2134cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev,
21351a635e48SYuval Mintz 				 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
2136cee4d264SManish Chopra {
2137cee4d264SManish Chopra 	return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2138cee4d264SManish Chopra 				      cqe);
2139cee4d264SManish Chopra }
2140cee4d264SManish Chopra 
21410b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
21420b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass;
21430b55e27dSYuval Mintz #endif
21440b55e27dSYuval Mintz 
2145a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2146a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2147a1d8d8a5SSudarsana Reddy Kalluru #endif
2148a1d8d8a5SSudarsana Reddy Kalluru 
214925c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = {
215025c089d7SYuval Mintz 	.common = &qed_common_ops_pass,
21510b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
21520b55e27dSYuval Mintz 	.iov = &qed_iov_ops_pass,
21530b55e27dSYuval Mintz #endif
2154a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2155a1d8d8a5SSudarsana Reddy Kalluru 	.dcb = &qed_dcbnl_ops_pass,
2156a1d8d8a5SSudarsana Reddy Kalluru #endif
215725c089d7SYuval Mintz 	.fill_dev_info = &qed_fill_eth_dev_info,
2158cc875c2eSYuval Mintz 	.register_ops = &qed_register_eth_ops,
2159eff16960SYuval Mintz 	.check_mac = &qed_check_mac,
2160cee4d264SManish Chopra 	.vport_start = &qed_start_vport,
2161cee4d264SManish Chopra 	.vport_stop = &qed_stop_vport,
2162cee4d264SManish Chopra 	.vport_update = &qed_update_vport,
2163cee4d264SManish Chopra 	.q_rx_start = &qed_start_rxq,
2164cee4d264SManish Chopra 	.q_rx_stop = &qed_stop_rxq,
2165cee4d264SManish Chopra 	.q_tx_start = &qed_start_txq,
2166cee4d264SManish Chopra 	.q_tx_stop = &qed_stop_txq,
2167cee4d264SManish Chopra 	.filter_config = &qed_configure_filter,
2168cee4d264SManish Chopra 	.fastpath_stop = &qed_fastpath_stop,
2169cee4d264SManish Chopra 	.eth_cqe_completion = &qed_fp_cqe_completion,
21709df2ed04SManish Chopra 	.get_vport_stats = &qed_get_vport_stats,
2171464f6645SManish Chopra 	.tunn_config = &qed_tunn_configure,
217225c089d7SYuval Mintz };
217325c089d7SYuval Mintz 
217495114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void)
217525c089d7SYuval Mintz {
217625c089d7SYuval Mintz 	return &qed_eth_ops_pass;
217725c089d7SYuval Mintz }
217825c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops);
217925c089d7SYuval Mintz 
218025c089d7SYuval Mintz void qed_put_eth_ops(void)
218125c089d7SYuval Mintz {
218225c089d7SYuval Mintz 	/* TODO - reference count for module? */
218325c089d7SYuval Mintz }
218425c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops);
2185