125c089d7SYuval Mintz /* QLogic qed NIC Driver
2e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
325c089d7SYuval Mintz  *
4e8f1cb50SMintz, Yuval  * This software is available to you under a choice of one of two
5e8f1cb50SMintz, Yuval  * licenses.  You may choose to be licensed under the terms of the GNU
6e8f1cb50SMintz, Yuval  * General Public License (GPL) Version 2, available from the file
7e8f1cb50SMintz, Yuval  * COPYING in the main directory of this source tree, or the
8e8f1cb50SMintz, Yuval  * OpenIB.org BSD license below:
9e8f1cb50SMintz, Yuval  *
10e8f1cb50SMintz, Yuval  *     Redistribution and use in source and binary forms, with or
11e8f1cb50SMintz, Yuval  *     without modification, are permitted provided that the following
12e8f1cb50SMintz, Yuval  *     conditions are met:
13e8f1cb50SMintz, Yuval  *
14e8f1cb50SMintz, Yuval  *      - Redistributions of source code must retain the above
15e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
16e8f1cb50SMintz, Yuval  *        disclaimer.
17e8f1cb50SMintz, Yuval  *
18e8f1cb50SMintz, Yuval  *      - Redistributions in binary form must reproduce the above
19e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
20e8f1cb50SMintz, Yuval  *        disclaimer in the documentation and /or other materials
21e8f1cb50SMintz, Yuval  *        provided with the distribution.
22e8f1cb50SMintz, Yuval  *
23e8f1cb50SMintz, Yuval  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24e8f1cb50SMintz, Yuval  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25e8f1cb50SMintz, Yuval  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26e8f1cb50SMintz, Yuval  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27e8f1cb50SMintz, Yuval  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28e8f1cb50SMintz, Yuval  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29e8f1cb50SMintz, Yuval  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30e8f1cb50SMintz, Yuval  * SOFTWARE.
3125c089d7SYuval Mintz  */
3225c089d7SYuval Mintz 
3325c089d7SYuval Mintz #include <linux/types.h>
3425c089d7SYuval Mintz #include <asm/byteorder.h>
3525c089d7SYuval Mintz #include <asm/param.h>
3625c089d7SYuval Mintz #include <linux/delay.h>
3725c089d7SYuval Mintz #include <linux/dma-mapping.h>
3825c089d7SYuval Mintz #include <linux/etherdevice.h>
3925c089d7SYuval Mintz #include <linux/interrupt.h>
4025c089d7SYuval Mintz #include <linux/kernel.h>
4125c089d7SYuval Mintz #include <linux/module.h>
4225c089d7SYuval Mintz #include <linux/pci.h>
4325c089d7SYuval Mintz #include <linux/slab.h>
4425c089d7SYuval Mintz #include <linux/stddef.h>
4525c089d7SYuval Mintz #include <linux/string.h>
4625c089d7SYuval Mintz #include <linux/workqueue.h>
4725c089d7SYuval Mintz #include <linux/bitops.h>
4825c089d7SYuval Mintz #include <linux/bug.h>
493da7a37aSMintz, Yuval #include <linux/vmalloc.h>
5025c089d7SYuval Mintz #include "qed.h"
5125c089d7SYuval Mintz #include <linux/qed/qed_chain.h>
5225c089d7SYuval Mintz #include "qed_cxt.h"
5325c089d7SYuval Mintz #include "qed_dev_api.h"
5425c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h>
5525c089d7SYuval Mintz #include "qed_hsi.h"
5625c089d7SYuval Mintz #include "qed_hw.h"
5725c089d7SYuval Mintz #include "qed_int.h"
58dacd88d6SYuval Mintz #include "qed_l2.h"
5986622ee7SYuval Mintz #include "qed_mcp.h"
6025c089d7SYuval Mintz #include "qed_reg_addr.h"
6125c089d7SYuval Mintz #include "qed_sp.h"
621408cc1fSYuval Mintz #include "qed_sriov.h"
6325c089d7SYuval Mintz 
64088c8618SManish Chopra 
65cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16
66cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41
67cee4d264SManish Chopra 
683da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
693da7a37aSMintz, Yuval 			       struct qed_queue_cid *p_cid)
703da7a37aSMintz, Yuval {
713da7a37aSMintz, Yuval 	/* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */
723da7a37aSMintz, Yuval 	if (!p_cid->is_vf && IS_PF(p_hwfn->cdev))
733da7a37aSMintz, Yuval 		qed_cxt_release_cid(p_hwfn, p_cid->cid);
743da7a37aSMintz, Yuval 	vfree(p_cid);
753da7a37aSMintz, Yuval }
763da7a37aSMintz, Yuval 
773da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs
783da7a37aSMintz, Yuval  * for their VFs.
793da7a37aSMintz, Yuval  */
803da7a37aSMintz, Yuval struct qed_queue_cid *
813da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
823da7a37aSMintz, Yuval 		      u16 opaque_fid,
833da7a37aSMintz, Yuval 		      u32 cid,
843da7a37aSMintz, Yuval 		      u8 vf_qid,
853da7a37aSMintz, Yuval 		      struct qed_queue_start_common_params *p_params)
863da7a37aSMintz, Yuval {
873da7a37aSMintz, Yuval 	bool b_is_same = (p_hwfn->hw_info.opaque_fid == opaque_fid);
883da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
893da7a37aSMintz, Yuval 	int rc;
903da7a37aSMintz, Yuval 
913da7a37aSMintz, Yuval 	p_cid = vmalloc(sizeof(*p_cid));
923da7a37aSMintz, Yuval 	if (!p_cid)
933da7a37aSMintz, Yuval 		return NULL;
943da7a37aSMintz, Yuval 	memset(p_cid, 0, sizeof(*p_cid));
953da7a37aSMintz, Yuval 
963da7a37aSMintz, Yuval 	p_cid->opaque_fid = opaque_fid;
973da7a37aSMintz, Yuval 	p_cid->cid = cid;
983da7a37aSMintz, Yuval 	p_cid->vf_qid = vf_qid;
993da7a37aSMintz, Yuval 	p_cid->rel = *p_params;
100f29ffdb6SMintz, Yuval 	p_cid->p_owner = p_hwfn;
1013da7a37aSMintz, Yuval 
1023da7a37aSMintz, Yuval 	/* Don't try calculating the absolute indices for VFs */
1033da7a37aSMintz, Yuval 	if (IS_VF(p_hwfn->cdev)) {
1043da7a37aSMintz, Yuval 		p_cid->abs = p_cid->rel;
1053da7a37aSMintz, Yuval 		goto out;
1063da7a37aSMintz, Yuval 	}
1073da7a37aSMintz, Yuval 
1083da7a37aSMintz, Yuval 	/* Calculate the engine-absolute indices of the resources.
1093da7a37aSMintz, Yuval 	 * This would guarantee they're valid later on.
1103da7a37aSMintz, Yuval 	 * In some cases [SBs] we already have the right values.
1113da7a37aSMintz, Yuval 	 */
1123da7a37aSMintz, Yuval 	rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
1133da7a37aSMintz, Yuval 	if (rc)
1143da7a37aSMintz, Yuval 		goto fail;
1153da7a37aSMintz, Yuval 
1163da7a37aSMintz, Yuval 	rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
1173da7a37aSMintz, Yuval 	if (rc)
1183da7a37aSMintz, Yuval 		goto fail;
1193da7a37aSMintz, Yuval 
1203da7a37aSMintz, Yuval 	/* In case of a PF configuring its VF's queues, the stats-id is already
1213da7a37aSMintz, Yuval 	 * absolute [since there's a single index that's suitable per-VF].
1223da7a37aSMintz, Yuval 	 */
1233da7a37aSMintz, Yuval 	if (b_is_same) {
1243da7a37aSMintz, Yuval 		rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
1253da7a37aSMintz, Yuval 				  &p_cid->abs.stats_id);
1263da7a37aSMintz, Yuval 		if (rc)
1273da7a37aSMintz, Yuval 			goto fail;
1283da7a37aSMintz, Yuval 	} else {
1293da7a37aSMintz, Yuval 		p_cid->abs.stats_id = p_cid->rel.stats_id;
1303da7a37aSMintz, Yuval 	}
1313da7a37aSMintz, Yuval 
1323da7a37aSMintz, Yuval 	/* SBs relevant information was already provided as absolute */
1333da7a37aSMintz, Yuval 	p_cid->abs.sb = p_cid->rel.sb;
1343da7a37aSMintz, Yuval 	p_cid->abs.sb_idx = p_cid->rel.sb_idx;
1353da7a37aSMintz, Yuval 
1363da7a37aSMintz, Yuval 	/* This is tricky - we're actually interested in whehter this is a PF
1373da7a37aSMintz, Yuval 	 * entry meant for the VF.
1383da7a37aSMintz, Yuval 	 */
1393da7a37aSMintz, Yuval 	if (!b_is_same)
1403da7a37aSMintz, Yuval 		p_cid->is_vf = true;
1413da7a37aSMintz, Yuval out:
1423da7a37aSMintz, Yuval 	DP_VERBOSE(p_hwfn,
1433da7a37aSMintz, Yuval 		   QED_MSG_SP,
1443da7a37aSMintz, Yuval 		   "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
1453da7a37aSMintz, Yuval 		   p_cid->opaque_fid,
1463da7a37aSMintz, Yuval 		   p_cid->cid,
1473da7a37aSMintz, Yuval 		   p_cid->rel.vport_id,
1483da7a37aSMintz, Yuval 		   p_cid->abs.vport_id,
1493da7a37aSMintz, Yuval 		   p_cid->rel.queue_id,
1503da7a37aSMintz, Yuval 		   p_cid->abs.queue_id,
1513da7a37aSMintz, Yuval 		   p_cid->rel.stats_id,
1523da7a37aSMintz, Yuval 		   p_cid->abs.stats_id, p_cid->abs.sb, p_cid->abs.sb_idx);
1533da7a37aSMintz, Yuval 
1543da7a37aSMintz, Yuval 	return p_cid;
1553da7a37aSMintz, Yuval 
1563da7a37aSMintz, Yuval fail:
1573da7a37aSMintz, Yuval 	vfree(p_cid);
1583da7a37aSMintz, Yuval 	return NULL;
1593da7a37aSMintz, Yuval }
1603da7a37aSMintz, Yuval 
1613da7a37aSMintz, Yuval static struct qed_queue_cid *qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
1623da7a37aSMintz, Yuval 						  u16 opaque_fid, struct
1633da7a37aSMintz, Yuval 						  qed_queue_start_common_params
1643da7a37aSMintz, Yuval 						  *p_params)
1653da7a37aSMintz, Yuval {
1663da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
1673da7a37aSMintz, Yuval 	u32 cid = 0;
1683da7a37aSMintz, Yuval 
1693da7a37aSMintz, Yuval 	/* Get a unique firmware CID for this queue, in case it's a PF.
1703da7a37aSMintz, Yuval 	 * VF's don't need a CID as the queue configuration will be done
1713da7a37aSMintz, Yuval 	 * by PF.
1723da7a37aSMintz, Yuval 	 */
1733da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
1743da7a37aSMintz, Yuval 		if (qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &cid)) {
1753da7a37aSMintz, Yuval 			DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
1763da7a37aSMintz, Yuval 			return NULL;
1773da7a37aSMintz, Yuval 		}
1783da7a37aSMintz, Yuval 	}
1793da7a37aSMintz, Yuval 
1803da7a37aSMintz, Yuval 	p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 0, p_params);
1813da7a37aSMintz, Yuval 	if (!p_cid && IS_PF(p_hwfn->cdev))
1823da7a37aSMintz, Yuval 		qed_cxt_release_cid(p_hwfn, cid);
1833da7a37aSMintz, Yuval 
1843da7a37aSMintz, Yuval 	return p_cid;
1853da7a37aSMintz, Yuval }
1863da7a37aSMintz, Yuval 
187dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
188088c8618SManish Chopra 			   struct qed_sp_vport_start_params *p_params)
189cee4d264SManish Chopra {
190cee4d264SManish Chopra 	struct vport_start_ramrod_data *p_ramrod = NULL;
191cee4d264SManish Chopra 	struct qed_spq_entry *p_ent =  NULL;
19206f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
193dacd88d6SYuval Mintz 	u8 abs_vport_id = 0;
194cee4d264SManish Chopra 	int rc = -EINVAL;
195cee4d264SManish Chopra 	u16 rx_mode = 0;
196cee4d264SManish Chopra 
197088c8618SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1981a635e48SYuval Mintz 	if (rc)
199cee4d264SManish Chopra 		return rc;
200cee4d264SManish Chopra 
20106f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
20206f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
203088c8618SManish Chopra 	init_data.opaque_fid = p_params->opaque_fid;
20406f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
205cee4d264SManish Chopra 
206cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
207cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_START,
20806f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
209cee4d264SManish Chopra 	if (rc)
210cee4d264SManish Chopra 		return rc;
211cee4d264SManish Chopra 
212cee4d264SManish Chopra 	p_ramrod		= &p_ent->ramrod.vport_start;
213cee4d264SManish Chopra 	p_ramrod->vport_id	= abs_vport_id;
214cee4d264SManish Chopra 
215088c8618SManish Chopra 	p_ramrod->mtu			= cpu_to_le16(p_params->mtu);
216c78c70faSSudarsana Reddy Kalluru 	p_ramrod->handle_ptp_pkts	= p_params->handle_ptp_pkts;
217088c8618SManish Chopra 	p_ramrod->inner_vlan_removal_en	= p_params->remove_inner_vlan;
218088c8618SManish Chopra 	p_ramrod->drop_ttl0_en		= p_params->drop_ttl0;
219e6bd8923SYuval Mintz 	p_ramrod->untagged		= p_params->only_untagged;
220cee4d264SManish Chopra 
221cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
222cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
223cee4d264SManish Chopra 
224cee4d264SManish Chopra 	p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
225cee4d264SManish Chopra 
226cee4d264SManish Chopra 	/* TPA related fields */
2271a635e48SYuval Mintz 	memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
228cee4d264SManish Chopra 
229088c8618SManish Chopra 	p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
230088c8618SManish Chopra 
231088c8618SManish Chopra 	switch (p_params->tpa_mode) {
232088c8618SManish Chopra 	case QED_TPA_MODE_GRO:
233088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
234088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_size = (u16)-1;
235088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
236088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
237088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
238088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
239088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
240088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
241088c8618SManish Chopra 		break;
242088c8618SManish Chopra 	default:
243088c8618SManish Chopra 		break;
244088c8618SManish Chopra 	}
245088c8618SManish Chopra 
246831bfb0eSYuval Mintz 	p_ramrod->tx_switching_en = p_params->tx_switching;
247831bfb0eSYuval Mintz 
24811a85d75SYuval Mintz 	p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
24911a85d75SYuval Mintz 	p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
25011a85d75SYuval Mintz 
251cee4d264SManish Chopra 	/* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
252cee4d264SManish Chopra 	p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
253088c8618SManish Chopra 						  p_params->concrete_fid);
254cee4d264SManish Chopra 
255cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
256cee4d264SManish Chopra }
257cee4d264SManish Chopra 
258ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
259dacd88d6SYuval Mintz 			      struct qed_sp_vport_start_params *p_params)
260dacd88d6SYuval Mintz {
261dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
262dacd88d6SYuval Mintz 		return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
263dacd88d6SYuval Mintz 					     p_params->mtu,
264dacd88d6SYuval Mintz 					     p_params->remove_inner_vlan,
265dacd88d6SYuval Mintz 					     p_params->tpa_mode,
26608feecd7SYuval Mintz 					     p_params->max_buffers_per_cqe,
26708feecd7SYuval Mintz 					     p_params->only_untagged);
268dacd88d6SYuval Mintz 	}
269dacd88d6SYuval Mintz 
270dacd88d6SYuval Mintz 	return qed_sp_eth_vport_start(p_hwfn, p_params);
271dacd88d6SYuval Mintz }
272dacd88d6SYuval Mintz 
273cee4d264SManish Chopra static int
274cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
275cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
276f29ffdb6SMintz, Yuval 			struct qed_rss_params *p_rss)
277cee4d264SManish Chopra {
278f29ffdb6SMintz, Yuval 	struct eth_vport_rss_config *p_config;
279f29ffdb6SMintz, Yuval 	u16 capabilities = 0;
280f29ffdb6SMintz, Yuval 	int i, table_size;
281f29ffdb6SMintz, Yuval 	int rc = 0;
282cee4d264SManish Chopra 
283f29ffdb6SMintz, Yuval 	if (!p_rss) {
284cee4d264SManish Chopra 		p_ramrod->common.update_rss_flg = 0;
285cee4d264SManish Chopra 		return rc;
286cee4d264SManish Chopra 	}
287f29ffdb6SMintz, Yuval 	p_config = &p_ramrod->rss_config;
288cee4d264SManish Chopra 
289f29ffdb6SMintz, Yuval 	BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
290cee4d264SManish Chopra 
291f29ffdb6SMintz, Yuval 	rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
292cee4d264SManish Chopra 	if (rc)
293cee4d264SManish Chopra 		return rc;
294cee4d264SManish Chopra 
295f29ffdb6SMintz, Yuval 	p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
296f29ffdb6SMintz, Yuval 	p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
297f29ffdb6SMintz, Yuval 	p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
298f29ffdb6SMintz, Yuval 	p_config->update_rss_key = p_rss->update_rss_key;
299cee4d264SManish Chopra 
300f29ffdb6SMintz, Yuval 	p_config->rss_mode = p_rss->rss_enable ?
301cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_REGULAR :
302cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_DISABLED;
303cee4d264SManish Chopra 
304cee4d264SManish Chopra 	SET_FIELD(capabilities,
305cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
306f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4));
307cee4d264SManish Chopra 	SET_FIELD(capabilities,
308cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
309f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6));
310cee4d264SManish Chopra 	SET_FIELD(capabilities,
311cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
312f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
313cee4d264SManish Chopra 	SET_FIELD(capabilities,
314cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
315f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
316cee4d264SManish Chopra 	SET_FIELD(capabilities,
317cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
318f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
319cee4d264SManish Chopra 	SET_FIELD(capabilities,
320cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
321f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
322f29ffdb6SMintz, Yuval 	p_config->tbl_size = p_rss->rss_table_size_log;
323cee4d264SManish Chopra 
324f29ffdb6SMintz, Yuval 	p_config->capabilities = cpu_to_le16(capabilities);
325cee4d264SManish Chopra 
326cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
327cee4d264SManish Chopra 		   "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
328cee4d264SManish Chopra 		   p_ramrod->common.update_rss_flg,
329f29ffdb6SMintz, Yuval 		   p_config->rss_mode,
330f29ffdb6SMintz, Yuval 		   p_config->update_rss_capabilities,
331f29ffdb6SMintz, Yuval 		   p_config->capabilities,
332f29ffdb6SMintz, Yuval 		   p_config->update_rss_ind_table, p_config->update_rss_key);
333cee4d264SManish Chopra 
334f29ffdb6SMintz, Yuval 	table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
335f29ffdb6SMintz, Yuval 			   1 << p_config->tbl_size);
336f29ffdb6SMintz, Yuval 	for (i = 0; i < table_size; i++) {
337f29ffdb6SMintz, Yuval 		struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
338cee4d264SManish Chopra 
339f29ffdb6SMintz, Yuval 		if (!p_queue)
340f29ffdb6SMintz, Yuval 			return -EINVAL;
341f29ffdb6SMintz, Yuval 
342f29ffdb6SMintz, Yuval 		p_config->indirection_table[i] =
343f29ffdb6SMintz, Yuval 		    cpu_to_le16(p_queue->abs.queue_id);
344f29ffdb6SMintz, Yuval 	}
345f29ffdb6SMintz, Yuval 
346f29ffdb6SMintz, Yuval 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
347f29ffdb6SMintz, Yuval 		   "Configured RSS indirection table [%d entries]:\n",
348f29ffdb6SMintz, Yuval 		   table_size);
349f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
350f29ffdb6SMintz, Yuval 		DP_VERBOSE(p_hwfn,
351f29ffdb6SMintz, Yuval 			   NETIF_MSG_IFUP,
352f29ffdb6SMintz, Yuval 			   "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
353f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i]),
354f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 1]),
355f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 2]),
356f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 3]),
357f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 4]),
358f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 5]),
359f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 6]),
360f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 7]),
361f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 8]),
362f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 9]),
363f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 10]),
364f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 11]),
365f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 12]),
366f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 13]),
367f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 14]),
368f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 15]));
369cee4d264SManish Chopra 	}
370cee4d264SManish Chopra 
371cee4d264SManish Chopra 	for (i = 0; i < 10; i++)
372f29ffdb6SMintz, Yuval 		p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
373cee4d264SManish Chopra 
374cee4d264SManish Chopra 	return rc;
375cee4d264SManish Chopra }
376cee4d264SManish Chopra 
377cee4d264SManish Chopra static void
378cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
379cee4d264SManish Chopra 			  struct vport_update_ramrod_data *p_ramrod,
380cee4d264SManish Chopra 			  struct qed_filter_accept_flags accept_flags)
381cee4d264SManish Chopra {
382cee4d264SManish Chopra 	p_ramrod->common.update_rx_mode_flg =
383cee4d264SManish Chopra 		accept_flags.update_rx_mode_config;
384cee4d264SManish Chopra 
385cee4d264SManish Chopra 	p_ramrod->common.update_tx_mode_flg =
386cee4d264SManish Chopra 		accept_flags.update_tx_mode_config;
387cee4d264SManish Chopra 
388cee4d264SManish Chopra 	/* Set Rx mode accept flags */
389cee4d264SManish Chopra 	if (p_ramrod->common.update_rx_mode_flg) {
390cee4d264SManish Chopra 		u8 accept_filter = accept_flags.rx_accept_filter;
391cee4d264SManish Chopra 		u16 state = 0;
392cee4d264SManish Chopra 
393cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
394cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
395cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
396cee4d264SManish Chopra 
397cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
398cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
399cee4d264SManish Chopra 
400cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
401cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
402cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
403cee4d264SManish Chopra 
404cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
405cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
406cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
407cee4d264SManish Chopra 
408cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
409cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
410cee4d264SManish Chopra 
411cee4d264SManish Chopra 		p_ramrod->rx_mode.state = cpu_to_le16(state);
412cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
413cee4d264SManish Chopra 			   "p_ramrod->rx_mode.state = 0x%x\n", state);
414cee4d264SManish Chopra 	}
415cee4d264SManish Chopra 
416cee4d264SManish Chopra 	/* Set Tx mode accept flags */
417cee4d264SManish Chopra 	if (p_ramrod->common.update_tx_mode_flg) {
418cee4d264SManish Chopra 		u8 accept_filter = accept_flags.tx_accept_filter;
419cee4d264SManish Chopra 		u16 state = 0;
420cee4d264SManish Chopra 
421cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
422cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
423cee4d264SManish Chopra 
424cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
425cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
426cee4d264SManish Chopra 
427cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
428cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
429cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
430cee4d264SManish Chopra 
431cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
432cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
433cee4d264SManish Chopra 
434cee4d264SManish Chopra 		p_ramrod->tx_mode.state = cpu_to_le16(state);
435cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
436cee4d264SManish Chopra 			   "p_ramrod->tx_mode.state = 0x%x\n", state);
437cee4d264SManish Chopra 	}
438cee4d264SManish Chopra }
439cee4d264SManish Chopra 
440cee4d264SManish Chopra static void
44117b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
44217b235c1SYuval Mintz 			    struct vport_update_ramrod_data *p_ramrod,
44317b235c1SYuval Mintz 			    struct qed_sge_tpa_params *p_params)
44417b235c1SYuval Mintz {
44517b235c1SYuval Mintz 	struct eth_vport_tpa_param *p_tpa;
44617b235c1SYuval Mintz 
44717b235c1SYuval Mintz 	if (!p_params) {
44817b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
44917b235c1SYuval Mintz 		p_ramrod->common.update_tpa_en_flg = 0;
45017b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
45117b235c1SYuval Mintz 		return;
45217b235c1SYuval Mintz 	}
45317b235c1SYuval Mintz 
45417b235c1SYuval Mintz 	p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
45517b235c1SYuval Mintz 	p_tpa = &p_ramrod->tpa_param;
45617b235c1SYuval Mintz 	p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
45717b235c1SYuval Mintz 	p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
45817b235c1SYuval Mintz 	p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
45917b235c1SYuval Mintz 	p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
46017b235c1SYuval Mintz 
46117b235c1SYuval Mintz 	p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
46217b235c1SYuval Mintz 	p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
46317b235c1SYuval Mintz 	p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
46417b235c1SYuval Mintz 	p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
46517b235c1SYuval Mintz 	p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
46617b235c1SYuval Mintz 	p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
46717b235c1SYuval Mintz 	p_tpa->tpa_max_size = p_params->tpa_max_size;
46817b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
46917b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
47017b235c1SYuval Mintz }
47117b235c1SYuval Mintz 
47217b235c1SYuval Mintz static void
473cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
474cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
475cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params)
476cee4d264SManish Chopra {
477cee4d264SManish Chopra 	int i;
478cee4d264SManish Chopra 
479cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
480cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
481cee4d264SManish Chopra 
48283aeb933SYuval Mintz 	if (!p_params->update_approx_mcast_flg)
48383aeb933SYuval Mintz 		return;
48483aeb933SYuval Mintz 
485cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
486cee4d264SManish Chopra 	for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
487cee4d264SManish Chopra 		u32 *p_bins = (u32 *)p_params->bins;
488cee4d264SManish Chopra 
48983aeb933SYuval Mintz 		p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
490cee4d264SManish Chopra 	}
491cee4d264SManish Chopra }
492cee4d264SManish Chopra 
493dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
494cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params,
495cee4d264SManish Chopra 			enum spq_mode comp_mode,
496cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
497cee4d264SManish Chopra {
498cee4d264SManish Chopra 	struct qed_rss_params *p_rss_params = p_params->rss_params;
499cee4d264SManish Chopra 	struct vport_update_ramrod_data_cmn *p_cmn;
50006f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
501cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
502cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
50317b235c1SYuval Mintz 	u8 abs_vport_id = 0, val;
504cee4d264SManish Chopra 	int rc = -EINVAL;
505cee4d264SManish Chopra 
506dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
507dacd88d6SYuval Mintz 		rc = qed_vf_pf_vport_update(p_hwfn, p_params);
508dacd88d6SYuval Mintz 		return rc;
509dacd88d6SYuval Mintz 	}
510dacd88d6SYuval Mintz 
511cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
5121a635e48SYuval Mintz 	if (rc)
513cee4d264SManish Chopra 		return rc;
514cee4d264SManish Chopra 
51506f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
51606f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
51706f56b81SYuval Mintz 	init_data.opaque_fid = p_params->opaque_fid;
51806f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
51906f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
520cee4d264SManish Chopra 
521cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
522cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
52306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
524cee4d264SManish Chopra 	if (rc)
525cee4d264SManish Chopra 		return rc;
526cee4d264SManish Chopra 
527cee4d264SManish Chopra 	/* Copy input params to ramrod according to FW struct */
528cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
529cee4d264SManish Chopra 	p_cmn = &p_ramrod->common;
530cee4d264SManish Chopra 
531cee4d264SManish Chopra 	p_cmn->vport_id = abs_vport_id;
532cee4d264SManish Chopra 	p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
533cee4d264SManish Chopra 	p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
534cee4d264SManish Chopra 	p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
535cee4d264SManish Chopra 	p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
5363f9b4a69SYuval Mintz 	p_cmn->accept_any_vlan = p_params->accept_any_vlan;
53783aeb933SYuval Mintz 	val = p_params->update_accept_any_vlan_flg;
53883aeb933SYuval Mintz 	p_cmn->update_accept_any_vlan_flg = val;
53917b235c1SYuval Mintz 
54017b235c1SYuval Mintz 	p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
54117b235c1SYuval Mintz 	val = p_params->update_inner_vlan_removal_flg;
54217b235c1SYuval Mintz 	p_cmn->update_inner_vlan_removal_en_flg = val;
54308feecd7SYuval Mintz 
54408feecd7SYuval Mintz 	p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
54508feecd7SYuval Mintz 	val = p_params->update_default_vlan_enable_flg;
54608feecd7SYuval Mintz 	p_cmn->update_default_vlan_en_flg = val;
54708feecd7SYuval Mintz 
54808feecd7SYuval Mintz 	p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
54908feecd7SYuval Mintz 	p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
55008feecd7SYuval Mintz 
55108feecd7SYuval Mintz 	p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
55208feecd7SYuval Mintz 
55317b235c1SYuval Mintz 	p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
55417b235c1SYuval Mintz 	p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
55517b235c1SYuval Mintz 
5566ddc7608SYuval Mintz 	p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
5576ddc7608SYuval Mintz 	val = p_params->update_anti_spoofing_en_flg;
5586ddc7608SYuval Mintz 	p_ramrod->common.update_anti_spoofing_en_flg = val;
5596ddc7608SYuval Mintz 
560cee4d264SManish Chopra 	rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
561cee4d264SManish Chopra 	if (rc) {
562cee4d264SManish Chopra 		/* Return spq entry which is taken in qed_sp_init_request()*/
563cee4d264SManish Chopra 		qed_spq_return_entry(p_hwfn, p_ent);
564cee4d264SManish Chopra 		return rc;
565cee4d264SManish Chopra 	}
566cee4d264SManish Chopra 
567cee4d264SManish Chopra 	/* Update mcast bins for VFs, PF doesn't use this functionality */
568cee4d264SManish Chopra 	qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
569cee4d264SManish Chopra 
570cee4d264SManish Chopra 	qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
57117b235c1SYuval Mintz 	qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
572cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
573cee4d264SManish Chopra }
574cee4d264SManish Chopra 
575dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
576cee4d264SManish Chopra {
577cee4d264SManish Chopra 	struct vport_stop_ramrod_data *p_ramrod;
57806f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
579cee4d264SManish Chopra 	struct qed_spq_entry *p_ent;
580cee4d264SManish Chopra 	u8 abs_vport_id = 0;
581cee4d264SManish Chopra 	int rc;
582cee4d264SManish Chopra 
583dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
584dacd88d6SYuval Mintz 		return qed_vf_pf_vport_stop(p_hwfn);
585dacd88d6SYuval Mintz 
586cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
5871a635e48SYuval Mintz 	if (rc)
588cee4d264SManish Chopra 		return rc;
589cee4d264SManish Chopra 
59006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
59106f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
59206f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
59306f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
594cee4d264SManish Chopra 
595cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
596cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_STOP,
59706f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
598cee4d264SManish Chopra 	if (rc)
599cee4d264SManish Chopra 		return rc;
600cee4d264SManish Chopra 
601cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_stop;
602cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
603cee4d264SManish Chopra 
604cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
605cee4d264SManish Chopra }
606cee4d264SManish Chopra 
607dacd88d6SYuval Mintz static int
608dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
609dacd88d6SYuval Mintz 		       struct qed_filter_accept_flags *p_accept_flags)
610dacd88d6SYuval Mintz {
611dacd88d6SYuval Mintz 	struct qed_sp_vport_update_params s_params;
612dacd88d6SYuval Mintz 
613dacd88d6SYuval Mintz 	memset(&s_params, 0, sizeof(s_params));
614dacd88d6SYuval Mintz 	memcpy(&s_params.accept_flags, p_accept_flags,
615dacd88d6SYuval Mintz 	       sizeof(struct qed_filter_accept_flags));
616dacd88d6SYuval Mintz 
617dacd88d6SYuval Mintz 	return qed_vf_pf_vport_update(p_hwfn, &s_params);
618dacd88d6SYuval Mintz }
619dacd88d6SYuval Mintz 
620cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev,
621cee4d264SManish Chopra 				 u8 vport,
622cee4d264SManish Chopra 				 struct qed_filter_accept_flags accept_flags,
6233f9b4a69SYuval Mintz 				 u8 update_accept_any_vlan,
6243f9b4a69SYuval Mintz 				 u8 accept_any_vlan,
625cee4d264SManish Chopra 				 enum spq_mode comp_mode,
626cee4d264SManish Chopra 				 struct qed_spq_comp_cb *p_comp_data)
627cee4d264SManish Chopra {
628cee4d264SManish Chopra 	struct qed_sp_vport_update_params vport_update_params;
629cee4d264SManish Chopra 	int i, rc;
630cee4d264SManish Chopra 
631cee4d264SManish Chopra 	/* Prepare and send the vport rx_mode change */
632cee4d264SManish Chopra 	memset(&vport_update_params, 0, sizeof(vport_update_params));
633cee4d264SManish Chopra 	vport_update_params.vport_id = vport;
634cee4d264SManish Chopra 	vport_update_params.accept_flags = accept_flags;
6353f9b4a69SYuval Mintz 	vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
6363f9b4a69SYuval Mintz 	vport_update_params.accept_any_vlan = accept_any_vlan;
637cee4d264SManish Chopra 
638cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
639cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
640cee4d264SManish Chopra 
641cee4d264SManish Chopra 		vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
642cee4d264SManish Chopra 
643dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
644dacd88d6SYuval Mintz 			rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
645dacd88d6SYuval Mintz 			if (rc)
646dacd88d6SYuval Mintz 				return rc;
647dacd88d6SYuval Mintz 			continue;
648dacd88d6SYuval Mintz 		}
649dacd88d6SYuval Mintz 
650cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
651cee4d264SManish Chopra 					 comp_mode, p_comp_data);
6521a635e48SYuval Mintz 		if (rc) {
653cee4d264SManish Chopra 			DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
654cee4d264SManish Chopra 			return rc;
655cee4d264SManish Chopra 		}
656cee4d264SManish Chopra 
657cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
658cee4d264SManish Chopra 			   "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
659cee4d264SManish Chopra 			   accept_flags.rx_accept_filter,
660cee4d264SManish Chopra 			   accept_flags.tx_accept_filter);
6613f9b4a69SYuval Mintz 		if (update_accept_any_vlan)
6623f9b4a69SYuval Mintz 			DP_VERBOSE(p_hwfn, QED_MSG_SP,
6633f9b4a69SYuval Mintz 				   "accept_any_vlan=%d configured\n",
6643f9b4a69SYuval Mintz 				   accept_any_vlan);
665cee4d264SManish Chopra 	}
666cee4d264SManish Chopra 
667cee4d264SManish Chopra 	return 0;
668cee4d264SManish Chopra }
669cee4d264SManish Chopra 
6703da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
6713da7a37aSMintz, Yuval 			     struct qed_queue_cid *p_cid,
672cee4d264SManish Chopra 			     u16 bd_max_bytes,
673cee4d264SManish Chopra 			     dma_addr_t bd_chain_phys_addr,
6743da7a37aSMintz, Yuval 			     dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
675cee4d264SManish Chopra {
676cee4d264SManish Chopra 	struct rx_queue_start_ramrod_data *p_ramrod = NULL;
677cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
67806f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
679cee4d264SManish Chopra 	int rc = -EINVAL;
680cee4d264SManish Chopra 
681cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
6823da7a37aSMintz, Yuval 		   "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
6833da7a37aSMintz, Yuval 		   p_cid->opaque_fid, p_cid->cid,
6843da7a37aSMintz, Yuval 		   p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->abs.sb);
685cee4d264SManish Chopra 
68606f56b81SYuval Mintz 	/* Get SPQ entry */
68706f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
6883da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
6893da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
69006f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
691cee4d264SManish Chopra 
692cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
693cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_START,
69406f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
695cee4d264SManish Chopra 	if (rc)
696cee4d264SManish Chopra 		return rc;
697cee4d264SManish Chopra 
698cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_start;
699cee4d264SManish Chopra 
7003da7a37aSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
7013da7a37aSMintz, Yuval 	p_ramrod->sb_index = p_cid->abs.sb_idx;
7023da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
7033da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
7043da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
705cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg = 0;
706cee4d264SManish Chopra 	p_ramrod->complete_event_flg = 1;
707cee4d264SManish Chopra 
708cee4d264SManish Chopra 	p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
70994494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
710cee4d264SManish Chopra 
711cee4d264SManish Chopra 	p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
71294494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
713cee4d264SManish Chopra 
7143da7a37aSMintz, Yuval 	if (p_cid->is_vf) {
7153da7a37aSMintz, Yuval 		p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
716351a4dedSYuval Mintz 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
717a044df83SYuval Mintz 			   "Queue%s is meant for VF rxq[%02x]\n",
7183da7a37aSMintz, Yuval 			   !!p_cid->b_legacy_vf ? " [legacy]" : "",
7193da7a37aSMintz, Yuval 			   p_cid->vf_qid);
7203da7a37aSMintz, Yuval 		p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf;
721a044df83SYuval Mintz 	}
722cee4d264SManish Chopra 
723351a4dedSYuval Mintz 	return qed_spq_post(p_hwfn, p_ent, NULL);
724cee4d264SManish Chopra }
725cee4d264SManish Chopra 
726cee4d264SManish Chopra static int
7273da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
7283da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
729cee4d264SManish Chopra 			  u16 bd_max_bytes,
730cee4d264SManish Chopra 			  dma_addr_t bd_chain_phys_addr,
731cee4d264SManish Chopra 			  dma_addr_t cqe_pbl_addr,
732dacd88d6SYuval Mintz 			  u16 cqe_pbl_size, void __iomem **pp_prod)
733cee4d264SManish Chopra {
734b21290b7SYuval Mintz 	u32 init_prod_val = 0;
735cee4d264SManish Chopra 
7363da7a37aSMintz, Yuval 	*pp_prod = p_hwfn->regview +
737cee4d264SManish Chopra 		   GTT_BAR0_MAP_REG_MSDM_RAM +
7383da7a37aSMintz, Yuval 		    MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
739cee4d264SManish Chopra 
740cee4d264SManish Chopra 	/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
741b21290b7SYuval Mintz 	__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
742cee4d264SManish Chopra 			  (u32 *)(&init_prod_val));
743cee4d264SManish Chopra 
7443da7a37aSMintz, Yuval 	return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
745cee4d264SManish Chopra 					bd_max_bytes,
746cee4d264SManish Chopra 					bd_chain_phys_addr,
7473da7a37aSMintz, Yuval 					cqe_pbl_addr, cqe_pbl_size);
7483da7a37aSMintz, Yuval }
749cee4d264SManish Chopra 
7503da7a37aSMintz, Yuval static int
7513da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
7523da7a37aSMintz, Yuval 		       u16 opaque_fid,
7533da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
7543da7a37aSMintz, Yuval 		       u16 bd_max_bytes,
7553da7a37aSMintz, Yuval 		       dma_addr_t bd_chain_phys_addr,
7563da7a37aSMintz, Yuval 		       dma_addr_t cqe_pbl_addr,
7573da7a37aSMintz, Yuval 		       u16 cqe_pbl_size,
7583da7a37aSMintz, Yuval 		       struct qed_rxq_start_ret_params *p_ret_params)
7593da7a37aSMintz, Yuval {
7603da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
7613da7a37aSMintz, Yuval 	int rc;
7623da7a37aSMintz, Yuval 
7633da7a37aSMintz, Yuval 	/* Allocate a CID for the queue */
7643da7a37aSMintz, Yuval 	p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
7653da7a37aSMintz, Yuval 	if (!p_cid)
7663da7a37aSMintz, Yuval 		return -ENOMEM;
7673da7a37aSMintz, Yuval 
7683da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
7693da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
7703da7a37aSMintz, Yuval 					       bd_max_bytes,
7713da7a37aSMintz, Yuval 					       bd_chain_phys_addr,
7723da7a37aSMintz, Yuval 					       cqe_pbl_addr, cqe_pbl_size,
7733da7a37aSMintz, Yuval 					       &p_ret_params->p_prod);
7743da7a37aSMintz, Yuval 	} else {
7753da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
7763da7a37aSMintz, Yuval 					 bd_max_bytes,
7773da7a37aSMintz, Yuval 					 bd_chain_phys_addr,
7783da7a37aSMintz, Yuval 					 cqe_pbl_addr,
7793da7a37aSMintz, Yuval 					 cqe_pbl_size, &p_ret_params->p_prod);
7803da7a37aSMintz, Yuval 	}
7813da7a37aSMintz, Yuval 
7823da7a37aSMintz, Yuval 	/* Provide the caller with a reference to as handler */
7831a635e48SYuval Mintz 	if (rc)
7843da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
7853da7a37aSMintz, Yuval 	else
7863da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
787cee4d264SManish Chopra 
788cee4d264SManish Chopra 	return rc;
789cee4d264SManish Chopra }
790cee4d264SManish Chopra 
79117b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
7923da7a37aSMintz, Yuval 				void **pp_rxq_handles,
79317b235c1SYuval Mintz 				u8 num_rxqs,
79417b235c1SYuval Mintz 				u8 complete_cqe_flg,
79517b235c1SYuval Mintz 				u8 complete_event_flg,
79617b235c1SYuval Mintz 				enum spq_mode comp_mode,
79717b235c1SYuval Mintz 				struct qed_spq_comp_cb *p_comp_data)
79817b235c1SYuval Mintz {
79917b235c1SYuval Mintz 	struct rx_queue_update_ramrod_data *p_ramrod = NULL;
80017b235c1SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
80117b235c1SYuval Mintz 	struct qed_sp_init_data init_data;
8023da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
80317b235c1SYuval Mintz 	int rc = -EINVAL;
80417b235c1SYuval Mintz 	u8 i;
80517b235c1SYuval Mintz 
80617b235c1SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
80717b235c1SYuval Mintz 	init_data.comp_mode = comp_mode;
80817b235c1SYuval Mintz 	init_data.p_comp_data = p_comp_data;
80917b235c1SYuval Mintz 
81017b235c1SYuval Mintz 	for (i = 0; i < num_rxqs; i++) {
8113da7a37aSMintz, Yuval 		p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
81217b235c1SYuval Mintz 
81317b235c1SYuval Mintz 		/* Get SPQ entry */
8143da7a37aSMintz, Yuval 		init_data.cid = p_cid->cid;
8153da7a37aSMintz, Yuval 		init_data.opaque_fid = p_cid->opaque_fid;
81617b235c1SYuval Mintz 
81717b235c1SYuval Mintz 		rc = qed_sp_init_request(p_hwfn, &p_ent,
81817b235c1SYuval Mintz 					 ETH_RAMROD_RX_QUEUE_UPDATE,
81917b235c1SYuval Mintz 					 PROTOCOLID_ETH, &init_data);
82017b235c1SYuval Mintz 		if (rc)
82117b235c1SYuval Mintz 			return rc;
82217b235c1SYuval Mintz 
82317b235c1SYuval Mintz 		p_ramrod = &p_ent->ramrod.rx_queue_update;
8243da7a37aSMintz, Yuval 		p_ramrod->vport_id = p_cid->abs.vport_id;
82517b235c1SYuval Mintz 
8263da7a37aSMintz, Yuval 		p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
82717b235c1SYuval Mintz 		p_ramrod->complete_cqe_flg = complete_cqe_flg;
82817b235c1SYuval Mintz 		p_ramrod->complete_event_flg = complete_event_flg;
82917b235c1SYuval Mintz 
83017b235c1SYuval Mintz 		rc = qed_spq_post(p_hwfn, p_ent, NULL);
83117b235c1SYuval Mintz 		if (rc)
83217b235c1SYuval Mintz 			return rc;
83317b235c1SYuval Mintz 	}
83417b235c1SYuval Mintz 
83517b235c1SYuval Mintz 	return rc;
83617b235c1SYuval Mintz }
83717b235c1SYuval Mintz 
8383da7a37aSMintz, Yuval static int
8393da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
8403da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
8413da7a37aSMintz, Yuval 			 bool b_eq_completion_only, bool b_cqe_completion)
842cee4d264SManish Chopra {
843cee4d264SManish Chopra 	struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
844cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
84506f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
8463da7a37aSMintz, Yuval 	int rc;
847cee4d264SManish Chopra 
84806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
8493da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
8503da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
85106f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
852cee4d264SManish Chopra 
853cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
854cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_STOP,
85506f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
856cee4d264SManish Chopra 	if (rc)
857cee4d264SManish Chopra 		return rc;
858cee4d264SManish Chopra 
859cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_stop;
8603da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
8613da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
862cee4d264SManish Chopra 
863cee4d264SManish Chopra 	/* Cleaning the queue requires the completion to arrive there.
864cee4d264SManish Chopra 	 * In addition, VFs require the answer to come as eqe to PF.
865cee4d264SManish Chopra 	 */
8663da7a37aSMintz, Yuval 	p_ramrod->complete_cqe_flg = (!p_cid->is_vf &&
8673da7a37aSMintz, Yuval 				      !b_eq_completion_only) ||
8683da7a37aSMintz, Yuval 				     b_cqe_completion;
8693da7a37aSMintz, Yuval 	p_ramrod->complete_event_flg = p_cid->is_vf || b_eq_completion_only;
870cee4d264SManish Chopra 
8713da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
872cee4d264SManish Chopra }
873cee4d264SManish Chopra 
8743da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
8753da7a37aSMintz, Yuval 			  void *p_rxq,
8763da7a37aSMintz, Yuval 			  bool eq_completion_only, bool cqe_completion)
8773da7a37aSMintz, Yuval {
8783da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
8793da7a37aSMintz, Yuval 	int rc = -EINVAL;
8803da7a37aSMintz, Yuval 
8813da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
8823da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
8833da7a37aSMintz, Yuval 					      eq_completion_only,
8843da7a37aSMintz, Yuval 					      cqe_completion);
8853da7a37aSMintz, Yuval 	else
8863da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
8873da7a37aSMintz, Yuval 
8883da7a37aSMintz, Yuval 	if (!rc)
8893da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
8903da7a37aSMintz, Yuval 	return rc;
8913da7a37aSMintz, Yuval }
8923da7a37aSMintz, Yuval 
8933da7a37aSMintz, Yuval int
8943da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
8953da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
8963da7a37aSMintz, Yuval 			 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
897cee4d264SManish Chopra {
898cee4d264SManish Chopra 	struct tx_queue_start_ramrod_data *p_ramrod = NULL;
899cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
90006f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
901cee4d264SManish Chopra 	int rc = -EINVAL;
902351a4dedSYuval Mintz 
90306f56b81SYuval Mintz 	/* Get SPQ entry */
90406f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
9053da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
9063da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
90706f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
908cee4d264SManish Chopra 
90906f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
910cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_START,
91106f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
912cee4d264SManish Chopra 	if (rc)
913cee4d264SManish Chopra 		return rc;
914cee4d264SManish Chopra 
915cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.tx_queue_start;
9163da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
917cee4d264SManish Chopra 
9183da7a37aSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
9193da7a37aSMintz, Yuval 	p_ramrod->sb_index = p_cid->abs.sb_idx;
9203da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
921cee4d264SManish Chopra 
9223da7a37aSMintz, Yuval 	p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
9233da7a37aSMintz, Yuval 	p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
9241a635e48SYuval Mintz 
925cee4d264SManish Chopra 	p_ramrod->pbl_size = cpu_to_le16(pbl_size);
92694494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
927cee4d264SManish Chopra 
928cee4d264SManish Chopra 	p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
929cee4d264SManish Chopra 
930cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
931cee4d264SManish Chopra }
932cee4d264SManish Chopra 
933cee4d264SManish Chopra static int
9343da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
9353da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
9363da7a37aSMintz, Yuval 			  u8 tc,
937cee4d264SManish Chopra 			  dma_addr_t pbl_addr,
938dacd88d6SYuval Mintz 			  u16 pbl_size, void __iomem **pp_doorbell)
939cee4d264SManish Chopra {
940cee4d264SManish Chopra 	int rc;
941cee4d264SManish Chopra 
942cee4d264SManish Chopra 
9433da7a37aSMintz, Yuval 	rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
9443da7a37aSMintz, Yuval 				      pbl_addr, pbl_size,
945b5a9ee7cSAriel Elior 				      qed_get_cm_pq_idx_mcos(p_hwfn, tc));
9463da7a37aSMintz, Yuval 	if (rc)
947cee4d264SManish Chopra 		return rc;
9483da7a37aSMintz, Yuval 
9493da7a37aSMintz, Yuval 	/* Provide the caller with the necessary return values */
9503da7a37aSMintz, Yuval 	*pp_doorbell = p_hwfn->doorbells +
9513da7a37aSMintz, Yuval 		       qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
9523da7a37aSMintz, Yuval 
9533da7a37aSMintz, Yuval 	return 0;
954cee4d264SManish Chopra }
955cee4d264SManish Chopra 
9563da7a37aSMintz, Yuval static int
9573da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
9583da7a37aSMintz, Yuval 		       u16 opaque_fid,
9593da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
9603da7a37aSMintz, Yuval 		       u8 tc,
9613da7a37aSMintz, Yuval 		       dma_addr_t pbl_addr,
9623da7a37aSMintz, Yuval 		       u16 pbl_size,
9633da7a37aSMintz, Yuval 		       struct qed_txq_start_ret_params *p_ret_params)
9643da7a37aSMintz, Yuval {
9653da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
9663da7a37aSMintz, Yuval 	int rc;
967cee4d264SManish Chopra 
9683da7a37aSMintz, Yuval 	p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
9693da7a37aSMintz, Yuval 	if (!p_cid)
9703da7a37aSMintz, Yuval 		return -EINVAL;
971cee4d264SManish Chopra 
9723da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
9733da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
9743da7a37aSMintz, Yuval 					       pbl_addr, pbl_size,
9753da7a37aSMintz, Yuval 					       &p_ret_params->p_doorbell);
9763da7a37aSMintz, Yuval 	else
9773da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
9783da7a37aSMintz, Yuval 					 pbl_addr, pbl_size,
9793da7a37aSMintz, Yuval 					 &p_ret_params->p_doorbell);
980cee4d264SManish Chopra 
981cee4d264SManish Chopra 	if (rc)
9823da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
9833da7a37aSMintz, Yuval 	else
9843da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
985cee4d264SManish Chopra 
986cee4d264SManish Chopra 	return rc;
987cee4d264SManish Chopra }
988cee4d264SManish Chopra 
9893da7a37aSMintz, Yuval static int
9903da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
991cee4d264SManish Chopra {
992cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
99306f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
9943da7a37aSMintz, Yuval 	int rc;
995cee4d264SManish Chopra 
99606f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
9973da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
9983da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
99906f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1000cee4d264SManish Chopra 
1001cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1002cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_STOP,
100306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1004cee4d264SManish Chopra 	if (rc)
1005cee4d264SManish Chopra 		return rc;
1006cee4d264SManish Chopra 
10073da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
10083da7a37aSMintz, Yuval }
1009cee4d264SManish Chopra 
10103da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
10113da7a37aSMintz, Yuval {
10123da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
10133da7a37aSMintz, Yuval 	int rc;
10143da7a37aSMintz, Yuval 
10153da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
10163da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
10173da7a37aSMintz, Yuval 	else
10183da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
10193da7a37aSMintz, Yuval 
10203da7a37aSMintz, Yuval 	if (!rc)
10213da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
10223da7a37aSMintz, Yuval 	return rc;
1023cee4d264SManish Chopra }
1024cee4d264SManish Chopra 
10251a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
1026cee4d264SManish Chopra {
1027cee4d264SManish Chopra 	enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1028cee4d264SManish Chopra 
1029cee4d264SManish Chopra 	switch (opcode) {
1030cee4d264SManish Chopra 	case QED_FILTER_ADD:
1031cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_ADD;
1032cee4d264SManish Chopra 		break;
1033cee4d264SManish Chopra 	case QED_FILTER_REMOVE:
1034cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_REMOVE;
1035cee4d264SManish Chopra 		break;
1036cee4d264SManish Chopra 	case QED_FILTER_FLUSH:
1037fc48b7a6SYuval Mintz 		action = ETH_FILTER_ACTION_REMOVE_ALL;
1038cee4d264SManish Chopra 		break;
1039cee4d264SManish Chopra 	default:
1040cee4d264SManish Chopra 		action = MAX_ETH_FILTER_ACTION;
1041cee4d264SManish Chopra 	}
1042cee4d264SManish Chopra 
1043cee4d264SManish Chopra 	return action;
1044cee4d264SManish Chopra }
1045cee4d264SManish Chopra 
1046cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb,
1047cee4d264SManish Chopra 				__le16 *fw_mid,
1048cee4d264SManish Chopra 				__le16 *fw_lsb,
1049cee4d264SManish Chopra 				u8 *mac)
1050cee4d264SManish Chopra {
1051cee4d264SManish Chopra 	((u8 *)fw_msb)[0] = mac[1];
1052cee4d264SManish Chopra 	((u8 *)fw_msb)[1] = mac[0];
1053cee4d264SManish Chopra 	((u8 *)fw_mid)[0] = mac[3];
1054cee4d264SManish Chopra 	((u8 *)fw_mid)[1] = mac[2];
1055cee4d264SManish Chopra 	((u8 *)fw_lsb)[0] = mac[5];
1056cee4d264SManish Chopra 	((u8 *)fw_lsb)[1] = mac[4];
1057cee4d264SManish Chopra }
1058cee4d264SManish Chopra 
1059cee4d264SManish Chopra static int
1060cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1061cee4d264SManish Chopra 			u16 opaque_fid,
1062cee4d264SManish Chopra 			struct qed_filter_ucast *p_filter_cmd,
1063cee4d264SManish Chopra 			struct vport_filter_update_ramrod_data **pp_ramrod,
1064cee4d264SManish Chopra 			struct qed_spq_entry **pp_ent,
1065cee4d264SManish Chopra 			enum spq_mode comp_mode,
1066cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1067cee4d264SManish Chopra {
1068cee4d264SManish Chopra 	u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1069cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data *p_ramrod;
1070cee4d264SManish Chopra 	struct eth_filter_cmd *p_first_filter;
1071cee4d264SManish Chopra 	struct eth_filter_cmd *p_second_filter;
107206f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1073cee4d264SManish Chopra 	enum eth_filter_action action;
1074cee4d264SManish Chopra 	int rc;
1075cee4d264SManish Chopra 
1076cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1077cee4d264SManish Chopra 			  &vport_to_remove_from);
1078cee4d264SManish Chopra 	if (rc)
1079cee4d264SManish Chopra 		return rc;
1080cee4d264SManish Chopra 
1081cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1082cee4d264SManish Chopra 			  &vport_to_add_to);
1083cee4d264SManish Chopra 	if (rc)
1084cee4d264SManish Chopra 		return rc;
1085cee4d264SManish Chopra 
108606f56b81SYuval Mintz 	/* Get SPQ entry */
108706f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
108806f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
108906f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
109006f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
109106f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1092cee4d264SManish Chopra 
1093cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, pp_ent,
1094cee4d264SManish Chopra 				 ETH_RAMROD_FILTERS_UPDATE,
109506f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1096cee4d264SManish Chopra 	if (rc)
1097cee4d264SManish Chopra 		return rc;
1098cee4d264SManish Chopra 
1099cee4d264SManish Chopra 	*pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1100cee4d264SManish Chopra 	p_ramrod = *pp_ramrod;
1101cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1102cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1103cee4d264SManish Chopra 
1104cee4d264SManish Chopra 	switch (p_filter_cmd->opcode) {
1105fc48b7a6SYuval Mintz 	case QED_FILTER_REPLACE:
1106cee4d264SManish Chopra 	case QED_FILTER_MOVE:
1107cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1108cee4d264SManish Chopra 	default:
1109cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1110cee4d264SManish Chopra 	}
1111cee4d264SManish Chopra 
1112cee4d264SManish Chopra 	p_first_filter	= &p_ramrod->filter_cmds[0];
1113cee4d264SManish Chopra 	p_second_filter = &p_ramrod->filter_cmds[1];
1114cee4d264SManish Chopra 
1115cee4d264SManish Chopra 	switch (p_filter_cmd->type) {
1116cee4d264SManish Chopra 	case QED_FILTER_MAC:
1117cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1118cee4d264SManish Chopra 	case QED_FILTER_VLAN:
1119cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1120cee4d264SManish Chopra 	case QED_FILTER_MAC_VLAN:
1121cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1122cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC:
1123cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1124cee4d264SManish Chopra 	case QED_FILTER_INNER_VLAN:
1125cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1126cee4d264SManish Chopra 	case QED_FILTER_INNER_PAIR:
1127cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1128cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC_VNI_PAIR:
1129cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1130cee4d264SManish Chopra 		break;
1131cee4d264SManish Chopra 	case QED_FILTER_MAC_VNI_PAIR:
1132cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1133cee4d264SManish Chopra 	case QED_FILTER_VNI:
1134cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1135cee4d264SManish Chopra 	}
1136cee4d264SManish Chopra 
1137cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1138cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1139cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1140cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1141cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1142cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1143cee4d264SManish Chopra 		qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1144cee4d264SManish Chopra 				    &p_first_filter->mac_mid,
1145cee4d264SManish Chopra 				    &p_first_filter->mac_lsb,
1146cee4d264SManish Chopra 				    (u8 *)p_filter_cmd->mac);
1147cee4d264SManish Chopra 	}
1148cee4d264SManish Chopra 
1149cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1150cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1151cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1152cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1153cee4d264SManish Chopra 		p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1154cee4d264SManish Chopra 
1155cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1156cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1157cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1158cee4d264SManish Chopra 		p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1159cee4d264SManish Chopra 
1160cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1161cee4d264SManish Chopra 		p_second_filter->type = p_first_filter->type;
1162cee4d264SManish Chopra 		p_second_filter->mac_msb = p_first_filter->mac_msb;
1163cee4d264SManish Chopra 		p_second_filter->mac_mid = p_first_filter->mac_mid;
1164cee4d264SManish Chopra 		p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1165cee4d264SManish Chopra 		p_second_filter->vlan_id = p_first_filter->vlan_id;
1166cee4d264SManish Chopra 		p_second_filter->vni = p_first_filter->vni;
1167cee4d264SManish Chopra 
1168cee4d264SManish Chopra 		p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1169cee4d264SManish Chopra 
1170cee4d264SManish Chopra 		p_first_filter->vport_id = vport_to_remove_from;
1171cee4d264SManish Chopra 
1172cee4d264SManish Chopra 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1173cee4d264SManish Chopra 		p_second_filter->vport_id = vport_to_add_to;
1174fc48b7a6SYuval Mintz 	} else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1175fc48b7a6SYuval Mintz 		p_first_filter->vport_id = vport_to_add_to;
1176fc48b7a6SYuval Mintz 		memcpy(p_second_filter, p_first_filter,
1177fc48b7a6SYuval Mintz 		       sizeof(*p_second_filter));
1178fc48b7a6SYuval Mintz 		p_first_filter->action	= ETH_FILTER_ACTION_REMOVE_ALL;
1179fc48b7a6SYuval Mintz 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1180cee4d264SManish Chopra 	} else {
1181cee4d264SManish Chopra 		action = qed_filter_action(p_filter_cmd->opcode);
1182cee4d264SManish Chopra 
1183cee4d264SManish Chopra 		if (action == MAX_ETH_FILTER_ACTION) {
1184cee4d264SManish Chopra 			DP_NOTICE(p_hwfn,
1185cee4d264SManish Chopra 				  "%d is not supported yet\n",
1186cee4d264SManish Chopra 				  p_filter_cmd->opcode);
1187cee4d264SManish Chopra 			return -EINVAL;
1188cee4d264SManish Chopra 		}
1189cee4d264SManish Chopra 
1190cee4d264SManish Chopra 		p_first_filter->action = action;
1191cee4d264SManish Chopra 		p_first_filter->vport_id = (p_filter_cmd->opcode ==
1192cee4d264SManish Chopra 					    QED_FILTER_REMOVE) ?
1193cee4d264SManish Chopra 					   vport_to_remove_from :
1194cee4d264SManish Chopra 					   vport_to_add_to;
1195cee4d264SManish Chopra 	}
1196cee4d264SManish Chopra 
1197cee4d264SManish Chopra 	return 0;
1198cee4d264SManish Chopra }
1199cee4d264SManish Chopra 
1200dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1201cee4d264SManish Chopra 			    u16 opaque_fid,
1202cee4d264SManish Chopra 			    struct qed_filter_ucast *p_filter_cmd,
1203cee4d264SManish Chopra 			    enum spq_mode comp_mode,
1204cee4d264SManish Chopra 			    struct qed_spq_comp_cb *p_comp_data)
1205cee4d264SManish Chopra {
1206cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data	*p_ramrod	= NULL;
1207cee4d264SManish Chopra 	struct qed_spq_entry			*p_ent		= NULL;
1208cee4d264SManish Chopra 	struct eth_filter_cmd_header		*p_header;
1209cee4d264SManish Chopra 	int					rc;
1210cee4d264SManish Chopra 
1211cee4d264SManish Chopra 	rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1212cee4d264SManish Chopra 				     &p_ramrod, &p_ent,
1213cee4d264SManish Chopra 				     comp_mode, p_comp_data);
12141a635e48SYuval Mintz 	if (rc) {
1215cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1216cee4d264SManish Chopra 		return rc;
1217cee4d264SManish Chopra 	}
1218cee4d264SManish Chopra 	p_header = &p_ramrod->filter_cmd_hdr;
1219cee4d264SManish Chopra 	p_header->assert_on_error = p_filter_cmd->assert_on_error;
1220cee4d264SManish Chopra 
1221cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
12221a635e48SYuval Mintz 	if (rc) {
12231a635e48SYuval Mintz 		DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1224cee4d264SManish Chopra 		return rc;
1225cee4d264SManish Chopra 	}
1226cee4d264SManish Chopra 
1227cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1228cee4d264SManish Chopra 		   "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1229cee4d264SManish Chopra 		   (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1230cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1231cee4d264SManish Chopra 		   "REMOVE" :
1232cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1233cee4d264SManish Chopra 		    "MOVE" : "REPLACE")),
1234cee4d264SManish Chopra 		   (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1235cee4d264SManish Chopra 		   ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1236cee4d264SManish Chopra 		    "VLAN" : "MAC & VLAN"),
1237cee4d264SManish Chopra 		   p_ramrod->filter_cmd_hdr.cmd_cnt,
1238cee4d264SManish Chopra 		   p_filter_cmd->is_rx_filter,
1239cee4d264SManish Chopra 		   p_filter_cmd->is_tx_filter);
1240cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1241cee4d264SManish Chopra 		   "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1242cee4d264SManish Chopra 		   p_filter_cmd->vport_to_add_to,
1243cee4d264SManish Chopra 		   p_filter_cmd->vport_to_remove_from,
1244cee4d264SManish Chopra 		   p_filter_cmd->mac[0],
1245cee4d264SManish Chopra 		   p_filter_cmd->mac[1],
1246cee4d264SManish Chopra 		   p_filter_cmd->mac[2],
1247cee4d264SManish Chopra 		   p_filter_cmd->mac[3],
1248cee4d264SManish Chopra 		   p_filter_cmd->mac[4],
1249cee4d264SManish Chopra 		   p_filter_cmd->mac[5],
1250cee4d264SManish Chopra 		   p_filter_cmd->vlan);
1251cee4d264SManish Chopra 
1252cee4d264SManish Chopra 	return 0;
1253cee4d264SManish Chopra }
1254cee4d264SManish Chopra 
1255cee4d264SManish Chopra /*******************************************************************************
1256cee4d264SManish Chopra  * Description:
1257cee4d264SManish Chopra  *         Calculates crc 32 on a buffer
1258cee4d264SManish Chopra  *         Note: crc32_length MUST be aligned to 8
1259cee4d264SManish Chopra  * Return:
1260cee4d264SManish Chopra  ******************************************************************************/
1261cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet,
12621a635e48SYuval Mintz 			   u32 crc32_length, u32 crc32_seed, u8 complement)
1263cee4d264SManish Chopra {
12641a635e48SYuval Mintz 	u32 byte = 0, bit = 0, crc32_result = crc32_seed;
12651a635e48SYuval Mintz 	u8 msb = 0, current_byte = 0;
1266cee4d264SManish Chopra 
1267cee4d264SManish Chopra 	if ((!crc32_packet) ||
1268cee4d264SManish Chopra 	    (crc32_length == 0) ||
1269cee4d264SManish Chopra 	    ((crc32_length % 8) != 0))
1270cee4d264SManish Chopra 		return crc32_result;
1271cee4d264SManish Chopra 	for (byte = 0; byte < crc32_length; byte++) {
1272cee4d264SManish Chopra 		current_byte = crc32_packet[byte];
1273cee4d264SManish Chopra 		for (bit = 0; bit < 8; bit++) {
1274cee4d264SManish Chopra 			msb = (u8)(crc32_result >> 31);
1275cee4d264SManish Chopra 			crc32_result = crc32_result << 1;
1276cee4d264SManish Chopra 			if (msb != (0x1 & (current_byte >> bit))) {
1277cee4d264SManish Chopra 				crc32_result = crc32_result ^ CRC32_POLY;
1278cee4d264SManish Chopra 				crc32_result |= 1; /*crc32_result[0] = 1;*/
1279cee4d264SManish Chopra 			}
1280cee4d264SManish Chopra 		}
1281cee4d264SManish Chopra 	}
1282cee4d264SManish Chopra 	return crc32_result;
1283cee4d264SManish Chopra }
1284cee4d264SManish Chopra 
12851a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
1286cee4d264SManish Chopra {
1287cee4d264SManish Chopra 	u32 packet_buf[2] = { 0 };
1288cee4d264SManish Chopra 
1289cee4d264SManish Chopra 	memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1290cee4d264SManish Chopra 	return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1291cee4d264SManish Chopra }
1292cee4d264SManish Chopra 
1293dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac)
1294cee4d264SManish Chopra {
1295cee4d264SManish Chopra 	u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1296cee4d264SManish Chopra 				mac, ETH_ALEN);
1297cee4d264SManish Chopra 
1298cee4d264SManish Chopra 	return crc & 0xff;
1299cee4d264SManish Chopra }
1300cee4d264SManish Chopra 
1301cee4d264SManish Chopra static int
1302cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1303cee4d264SManish Chopra 			u16 opaque_fid,
1304cee4d264SManish Chopra 			struct qed_filter_mcast *p_filter_cmd,
1305cee4d264SManish Chopra 			enum spq_mode comp_mode,
1306cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1307cee4d264SManish Chopra {
1308cee4d264SManish Chopra 	unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1309cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
1310cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
131106f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1312cee4d264SManish Chopra 	u8 abs_vport_id = 0;
1313cee4d264SManish Chopra 	int rc, i;
1314cee4d264SManish Chopra 
131583aeb933SYuval Mintz 	if (p_filter_cmd->opcode == QED_FILTER_ADD)
1316cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1317cee4d264SManish Chopra 				  &abs_vport_id);
131883aeb933SYuval Mintz 	else
1319cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1320cee4d264SManish Chopra 				  &abs_vport_id);
1321cee4d264SManish Chopra 	if (rc)
1322cee4d264SManish Chopra 		return rc;
1323cee4d264SManish Chopra 
132406f56b81SYuval Mintz 	/* Get SPQ entry */
132506f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
132606f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
132706f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
132806f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
132906f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1330cee4d264SManish Chopra 
1331cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1332cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
133306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1334cee4d264SManish Chopra 	if (rc) {
1335cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1336cee4d264SManish Chopra 		return rc;
1337cee4d264SManish Chopra 	}
1338cee4d264SManish Chopra 
1339cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
1340cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
1341cee4d264SManish Chopra 
1342cee4d264SManish Chopra 	/* explicitly clear out the entire vector */
1343cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
1344cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
1345cee4d264SManish Chopra 	memset(bins, 0, sizeof(unsigned long) *
1346cee4d264SManish Chopra 	       ETH_MULTICAST_MAC_BINS_IN_REGS);
1347cee4d264SManish Chopra 	/* filter ADD op is explicit set op and it removes
1348cee4d264SManish Chopra 	 *  any existing filters for the vport
1349cee4d264SManish Chopra 	 */
1350cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1351cee4d264SManish Chopra 		for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1352cee4d264SManish Chopra 			u32 bit;
1353cee4d264SManish Chopra 
1354cee4d264SManish Chopra 			bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1355cee4d264SManish Chopra 			__set_bit(bit, bins);
1356cee4d264SManish Chopra 		}
1357cee4d264SManish Chopra 
1358cee4d264SManish Chopra 		/* Convert to correct endianity */
1359cee4d264SManish Chopra 		for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
13601a635e48SYuval Mintz 			struct vport_update_ramrod_mcast *p_ramrod_bins;
1361cee4d264SManish Chopra 			u32 *p_bins = (u32 *)bins;
1362cee4d264SManish Chopra 
13631a635e48SYuval Mintz 			p_ramrod_bins = &p_ramrod->approx_mcast;
13641a635e48SYuval Mintz 			p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
1365cee4d264SManish Chopra 		}
1366cee4d264SManish Chopra 	}
1367cee4d264SManish Chopra 
1368cee4d264SManish Chopra 	p_ramrod->common.vport_id = abs_vport_id;
1369cee4d264SManish Chopra 
1370cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1371cee4d264SManish Chopra }
1372cee4d264SManish Chopra 
1373dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1374cee4d264SManish Chopra 				struct qed_filter_mcast *p_filter_cmd,
1375cee4d264SManish Chopra 				enum spq_mode comp_mode,
1376cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1377cee4d264SManish Chopra {
1378cee4d264SManish Chopra 	int rc = 0;
1379cee4d264SManish Chopra 	int i;
1380cee4d264SManish Chopra 
1381cee4d264SManish Chopra 	/* only ADD and REMOVE operations are supported for multi-cast */
1382cee4d264SManish Chopra 	if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1383cee4d264SManish Chopra 	     (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1384cee4d264SManish Chopra 	    (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1385cee4d264SManish Chopra 		return -EINVAL;
1386cee4d264SManish Chopra 
1387cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1388cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1389cee4d264SManish Chopra 
1390cee4d264SManish Chopra 		u16 opaque_fid;
1391cee4d264SManish Chopra 
1392dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1393dacd88d6SYuval Mintz 			qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1394dacd88d6SYuval Mintz 			continue;
1395dacd88d6SYuval Mintz 		}
1396cee4d264SManish Chopra 
1397cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1398cee4d264SManish Chopra 
1399cee4d264SManish Chopra 		rc = qed_sp_eth_filter_mcast(p_hwfn,
1400cee4d264SManish Chopra 					     opaque_fid,
1401cee4d264SManish Chopra 					     p_filter_cmd,
14021a635e48SYuval Mintz 					     comp_mode, p_comp_data);
1403cee4d264SManish Chopra 	}
1404cee4d264SManish Chopra 	return rc;
1405cee4d264SManish Chopra }
1406cee4d264SManish Chopra 
1407cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1408cee4d264SManish Chopra 				struct qed_filter_ucast *p_filter_cmd,
1409cee4d264SManish Chopra 				enum spq_mode comp_mode,
1410cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1411cee4d264SManish Chopra {
1412cee4d264SManish Chopra 	int rc = 0;
1413cee4d264SManish Chopra 	int i;
1414cee4d264SManish Chopra 
1415cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1416cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1417cee4d264SManish Chopra 		u16 opaque_fid;
1418cee4d264SManish Chopra 
1419dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1420dacd88d6SYuval Mintz 			rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1421dacd88d6SYuval Mintz 			continue;
1422dacd88d6SYuval Mintz 		}
1423cee4d264SManish Chopra 
1424cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1425cee4d264SManish Chopra 
1426cee4d264SManish Chopra 		rc = qed_sp_eth_filter_ucast(p_hwfn,
1427cee4d264SManish Chopra 					     opaque_fid,
1428cee4d264SManish Chopra 					     p_filter_cmd,
14291a635e48SYuval Mintz 					     comp_mode, p_comp_data);
14301a635e48SYuval Mintz 		if (rc)
1431dacd88d6SYuval Mintz 			break;
1432cee4d264SManish Chopra 	}
1433cee4d264SManish Chopra 
1434cee4d264SManish Chopra 	return rc;
1435cee4d264SManish Chopra }
1436cee4d264SManish Chopra 
143786622ee7SYuval Mintz /* Statistics related code */
143886622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
143986622ee7SYuval Mintz 					   u32 *p_addr,
1440dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
144186622ee7SYuval Mintz {
1442dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
144386622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_PSDM_RAM +
144486622ee7SYuval Mintz 		    PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
144586622ee7SYuval Mintz 		*p_len = sizeof(struct eth_pstorm_per_queue_stat);
1446dacd88d6SYuval Mintz 	} else {
1447dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1448dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1449dacd88d6SYuval Mintz 
1450dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1451dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.pstats.len;
1452dacd88d6SYuval Mintz 	}
145386622ee7SYuval Mintz }
145486622ee7SYuval Mintz 
145586622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
145686622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
145786622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
145886622ee7SYuval Mintz 				   u16 statistics_bin)
145986622ee7SYuval Mintz {
146086622ee7SYuval Mintz 	struct eth_pstorm_per_queue_stat pstats;
146186622ee7SYuval Mintz 	u32 pstats_addr = 0, pstats_len = 0;
146286622ee7SYuval Mintz 
146386622ee7SYuval Mintz 	__qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
146486622ee7SYuval Mintz 				       statistics_bin);
146586622ee7SYuval Mintz 
146686622ee7SYuval Mintz 	memset(&pstats, 0, sizeof(pstats));
1467dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
146886622ee7SYuval Mintz 
14699c79ddaaSMintz, Yuval 	p_stats->common.tx_ucast_bytes +=
14709c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_ucast_bytes);
14719c79ddaaSMintz, Yuval 	p_stats->common.tx_mcast_bytes +=
14729c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_mcast_bytes);
14739c79ddaaSMintz, Yuval 	p_stats->common.tx_bcast_bytes +=
14749c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_bcast_bytes);
14759c79ddaaSMintz, Yuval 	p_stats->common.tx_ucast_pkts +=
14769c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_ucast_pkts);
14779c79ddaaSMintz, Yuval 	p_stats->common.tx_mcast_pkts +=
14789c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_mcast_pkts);
14799c79ddaaSMintz, Yuval 	p_stats->common.tx_bcast_pkts +=
14809c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_bcast_pkts);
14819c79ddaaSMintz, Yuval 	p_stats->common.tx_err_drop_pkts +=
14829c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.error_drop_pkts);
148386622ee7SYuval Mintz }
148486622ee7SYuval Mintz 
148586622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
148686622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
148786622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
148886622ee7SYuval Mintz 				   u16 statistics_bin)
148986622ee7SYuval Mintz {
149086622ee7SYuval Mintz 	struct tstorm_per_port_stat tstats;
1491dacd88d6SYuval Mintz 	u32 tstats_addr, tstats_len;
149286622ee7SYuval Mintz 
1493dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
1494dacd88d6SYuval Mintz 		tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1495dacd88d6SYuval Mintz 		    TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1496dacd88d6SYuval Mintz 		tstats_len = sizeof(struct tstorm_per_port_stat);
1497dacd88d6SYuval Mintz 	} else {
1498dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1499dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1500dacd88d6SYuval Mintz 
1501dacd88d6SYuval Mintz 		tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1502dacd88d6SYuval Mintz 		tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1503dacd88d6SYuval Mintz 	}
150486622ee7SYuval Mintz 
150586622ee7SYuval Mintz 	memset(&tstats, 0, sizeof(tstats));
1506dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
150786622ee7SYuval Mintz 
15089c79ddaaSMintz, Yuval 	p_stats->common.mftag_filter_discards +=
150986622ee7SYuval Mintz 	    HILO_64_REGPAIR(tstats.mftag_filter_discard);
15109c79ddaaSMintz, Yuval 	p_stats->common.mac_filter_discards +=
151186622ee7SYuval Mintz 	    HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
151286622ee7SYuval Mintz }
151386622ee7SYuval Mintz 
151486622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
151586622ee7SYuval Mintz 					   u32 *p_addr,
1516dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
151786622ee7SYuval Mintz {
1518dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
151986622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_USDM_RAM +
152086622ee7SYuval Mintz 		    USTORM_QUEUE_STAT_OFFSET(statistics_bin);
152186622ee7SYuval Mintz 		*p_len = sizeof(struct eth_ustorm_per_queue_stat);
1522dacd88d6SYuval Mintz 	} else {
1523dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1524dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1525dacd88d6SYuval Mintz 
1526dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1527dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.ustats.len;
1528dacd88d6SYuval Mintz 	}
152986622ee7SYuval Mintz }
153086622ee7SYuval Mintz 
153186622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
153286622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
153386622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
153486622ee7SYuval Mintz 				   u16 statistics_bin)
153586622ee7SYuval Mintz {
153686622ee7SYuval Mintz 	struct eth_ustorm_per_queue_stat ustats;
153786622ee7SYuval Mintz 	u32 ustats_addr = 0, ustats_len = 0;
153886622ee7SYuval Mintz 
153986622ee7SYuval Mintz 	__qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
154086622ee7SYuval Mintz 				       statistics_bin);
154186622ee7SYuval Mintz 
154286622ee7SYuval Mintz 	memset(&ustats, 0, sizeof(ustats));
1543dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
154486622ee7SYuval Mintz 
15459c79ddaaSMintz, Yuval 	p_stats->common.rx_ucast_bytes +=
15469c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
15479c79ddaaSMintz, Yuval 	p_stats->common.rx_mcast_bytes +=
15489c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
15499c79ddaaSMintz, Yuval 	p_stats->common.rx_bcast_bytes +=
15509c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
15519c79ddaaSMintz, Yuval 	p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
15529c79ddaaSMintz, Yuval 	p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
15539c79ddaaSMintz, Yuval 	p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
155486622ee7SYuval Mintz }
155586622ee7SYuval Mintz 
155686622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
155786622ee7SYuval Mintz 					   u32 *p_addr,
1558dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
155986622ee7SYuval Mintz {
1560dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
156186622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_MSDM_RAM +
156286622ee7SYuval Mintz 		    MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
156386622ee7SYuval Mintz 		*p_len = sizeof(struct eth_mstorm_per_queue_stat);
1564dacd88d6SYuval Mintz 	} else {
1565dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1566dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1567dacd88d6SYuval Mintz 
1568dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1569dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.mstats.len;
1570dacd88d6SYuval Mintz 	}
157186622ee7SYuval Mintz }
157286622ee7SYuval Mintz 
157386622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
157486622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
157586622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
157686622ee7SYuval Mintz 				   u16 statistics_bin)
157786622ee7SYuval Mintz {
157886622ee7SYuval Mintz 	struct eth_mstorm_per_queue_stat mstats;
157986622ee7SYuval Mintz 	u32 mstats_addr = 0, mstats_len = 0;
158086622ee7SYuval Mintz 
158186622ee7SYuval Mintz 	__qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
158286622ee7SYuval Mintz 				       statistics_bin);
158386622ee7SYuval Mintz 
158486622ee7SYuval Mintz 	memset(&mstats, 0, sizeof(mstats));
1585dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
158686622ee7SYuval Mintz 
15879c79ddaaSMintz, Yuval 	p_stats->common.no_buff_discards +=
15889c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(mstats.no_buff_discard);
15899c79ddaaSMintz, Yuval 	p_stats->common.packet_too_big_discard +=
159086622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.packet_too_big_discard);
15919c79ddaaSMintz, Yuval 	p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
15929c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_pkts +=
159386622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
15949c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_events +=
159586622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_events);
15969c79ddaaSMintz, Yuval 	p_stats->common.tpa_aborts_num +=
15979c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(mstats.tpa_aborts_num);
15989c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_bytes +=
159986622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
160086622ee7SYuval Mintz }
160186622ee7SYuval Mintz 
160286622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
160386622ee7SYuval Mintz 				       struct qed_ptt *p_ptt,
160486622ee7SYuval Mintz 				       struct qed_eth_stats *p_stats)
160586622ee7SYuval Mintz {
16069c79ddaaSMintz, Yuval 	struct qed_eth_stats_common *p_common = &p_stats->common;
160786622ee7SYuval Mintz 	struct port_stats port_stats;
160886622ee7SYuval Mintz 	int j;
160986622ee7SYuval Mintz 
161086622ee7SYuval Mintz 	memset(&port_stats, 0, sizeof(port_stats));
161186622ee7SYuval Mintz 
161286622ee7SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
161386622ee7SYuval Mintz 			p_hwfn->mcp_info->port_addr +
161486622ee7SYuval Mintz 			offsetof(struct public_port, stats),
161586622ee7SYuval Mintz 			sizeof(port_stats));
161686622ee7SYuval Mintz 
16179c79ddaaSMintz, Yuval 	p_common->rx_64_byte_packets += port_stats.eth.r64;
16189c79ddaaSMintz, Yuval 	p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
16199c79ddaaSMintz, Yuval 	p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
16209c79ddaaSMintz, Yuval 	p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
16219c79ddaaSMintz, Yuval 	p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
16229c79ddaaSMintz, Yuval 	p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
16239c79ddaaSMintz, Yuval 	p_common->rx_crc_errors += port_stats.eth.rfcs;
16249c79ddaaSMintz, Yuval 	p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
16259c79ddaaSMintz, Yuval 	p_common->rx_pause_frames += port_stats.eth.rxpf;
16269c79ddaaSMintz, Yuval 	p_common->rx_pfc_frames += port_stats.eth.rxpp;
16279c79ddaaSMintz, Yuval 	p_common->rx_align_errors += port_stats.eth.raln;
16289c79ddaaSMintz, Yuval 	p_common->rx_carrier_errors += port_stats.eth.rfcr;
16299c79ddaaSMintz, Yuval 	p_common->rx_oversize_packets += port_stats.eth.rovr;
16309c79ddaaSMintz, Yuval 	p_common->rx_jabbers += port_stats.eth.rjbr;
16319c79ddaaSMintz, Yuval 	p_common->rx_undersize_packets += port_stats.eth.rund;
16329c79ddaaSMintz, Yuval 	p_common->rx_fragments += port_stats.eth.rfrg;
16339c79ddaaSMintz, Yuval 	p_common->tx_64_byte_packets += port_stats.eth.t64;
16349c79ddaaSMintz, Yuval 	p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
16359c79ddaaSMintz, Yuval 	p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
16369c79ddaaSMintz, Yuval 	p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
16379c79ddaaSMintz, Yuval 	p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
16389c79ddaaSMintz, Yuval 	p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
16399c79ddaaSMintz, Yuval 	p_common->tx_pause_frames += port_stats.eth.txpf;
16409c79ddaaSMintz, Yuval 	p_common->tx_pfc_frames += port_stats.eth.txpp;
16419c79ddaaSMintz, Yuval 	p_common->rx_mac_bytes += port_stats.eth.rbyte;
16429c79ddaaSMintz, Yuval 	p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
16439c79ddaaSMintz, Yuval 	p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
16449c79ddaaSMintz, Yuval 	p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
16459c79ddaaSMintz, Yuval 	p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
16469c79ddaaSMintz, Yuval 	p_common->tx_mac_bytes += port_stats.eth.tbyte;
16479c79ddaaSMintz, Yuval 	p_common->tx_mac_uc_packets += port_stats.eth.txuca;
16489c79ddaaSMintz, Yuval 	p_common->tx_mac_mc_packets += port_stats.eth.txmca;
16499c79ddaaSMintz, Yuval 	p_common->tx_mac_bc_packets += port_stats.eth.txbca;
16509c79ddaaSMintz, Yuval 	p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
165186622ee7SYuval Mintz 	for (j = 0; j < 8; j++) {
16529c79ddaaSMintz, Yuval 		p_common->brb_truncates += port_stats.brb.brb_truncate[j];
16539c79ddaaSMintz, Yuval 		p_common->brb_discards += port_stats.brb.brb_discard[j];
16549c79ddaaSMintz, Yuval 	}
16559c79ddaaSMintz, Yuval 
16569c79ddaaSMintz, Yuval 	if (QED_IS_BB(p_hwfn->cdev)) {
16579c79ddaaSMintz, Yuval 		struct qed_eth_stats_bb *p_bb = &p_stats->bb;
16589c79ddaaSMintz, Yuval 
16599c79ddaaSMintz, Yuval 		p_bb->rx_1519_to_1522_byte_packets +=
16609c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r1522;
16619c79ddaaSMintz, Yuval 		p_bb->rx_1519_to_2047_byte_packets +=
16629c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r2047;
16639c79ddaaSMintz, Yuval 		p_bb->rx_2048_to_4095_byte_packets +=
16649c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r4095;
16659c79ddaaSMintz, Yuval 		p_bb->rx_4096_to_9216_byte_packets +=
16669c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r9216;
16679c79ddaaSMintz, Yuval 		p_bb->rx_9217_to_16383_byte_packets +=
16689c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r16383;
16699c79ddaaSMintz, Yuval 		p_bb->tx_1519_to_2047_byte_packets +=
16709c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t2047;
16719c79ddaaSMintz, Yuval 		p_bb->tx_2048_to_4095_byte_packets +=
16729c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t4095;
16739c79ddaaSMintz, Yuval 		p_bb->tx_4096_to_9216_byte_packets +=
16749c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t9216;
16759c79ddaaSMintz, Yuval 		p_bb->tx_9217_to_16383_byte_packets +=
16769c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t16383;
16779c79ddaaSMintz, Yuval 		p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
16789c79ddaaSMintz, Yuval 		p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
16799c79ddaaSMintz, Yuval 	} else {
16809c79ddaaSMintz, Yuval 		struct qed_eth_stats_ah *p_ah = &p_stats->ah;
16819c79ddaaSMintz, Yuval 
16829c79ddaaSMintz, Yuval 		p_ah->rx_1519_to_max_byte_packets +=
16839c79ddaaSMintz, Yuval 		    port_stats.eth.u0.ah0.r1519_to_max;
16849c79ddaaSMintz, Yuval 		p_ah->tx_1519_to_max_byte_packets =
16859c79ddaaSMintz, Yuval 		    port_stats.eth.u1.ah1.t1519_to_max;
168686622ee7SYuval Mintz 	}
168786622ee7SYuval Mintz }
168886622ee7SYuval Mintz 
168986622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
169086622ee7SYuval Mintz 				  struct qed_ptt *p_ptt,
169186622ee7SYuval Mintz 				  struct qed_eth_stats *stats,
1692dacd88d6SYuval Mintz 				  u16 statistics_bin, bool b_get_port_stats)
169386622ee7SYuval Mintz {
169486622ee7SYuval Mintz 	__qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
169586622ee7SYuval Mintz 	__qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
169686622ee7SYuval Mintz 	__qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
169786622ee7SYuval Mintz 	__qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
169886622ee7SYuval Mintz 
1699dacd88d6SYuval Mintz 	if (b_get_port_stats && p_hwfn->mcp_info)
170086622ee7SYuval Mintz 		__qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
170186622ee7SYuval Mintz }
170286622ee7SYuval Mintz 
170386622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev,
170486622ee7SYuval Mintz 				 struct qed_eth_stats *stats)
170586622ee7SYuval Mintz {
170686622ee7SYuval Mintz 	u8 fw_vport = 0;
170786622ee7SYuval Mintz 	int i;
170886622ee7SYuval Mintz 
170986622ee7SYuval Mintz 	memset(stats, 0, sizeof(*stats));
171086622ee7SYuval Mintz 
171186622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
171286622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1713dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1714dacd88d6SYuval Mintz 						    :  NULL;
171586622ee7SYuval Mintz 
1716dacd88d6SYuval Mintz 		if (IS_PF(cdev)) {
171786622ee7SYuval Mintz 			/* The main vport index is relative first */
171886622ee7SYuval Mintz 			if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
171986622ee7SYuval Mintz 				DP_ERR(p_hwfn, "No vport available!\n");
1720dacd88d6SYuval Mintz 				goto out;
1721dacd88d6SYuval Mintz 			}
172286622ee7SYuval Mintz 		}
172386622ee7SYuval Mintz 
1724dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
172586622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
172686622ee7SYuval Mintz 			continue;
172786622ee7SYuval Mintz 		}
172886622ee7SYuval Mintz 
1729dacd88d6SYuval Mintz 		__qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1730dacd88d6SYuval Mintz 				      IS_PF(cdev) ? true : false);
173186622ee7SYuval Mintz 
1732dacd88d6SYuval Mintz out:
1733dacd88d6SYuval Mintz 		if (IS_PF(cdev) && p_ptt)
173486622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
173586622ee7SYuval Mintz 	}
173686622ee7SYuval Mintz }
173786622ee7SYuval Mintz 
17381a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
173986622ee7SYuval Mintz {
174086622ee7SYuval Mintz 	u32 i;
174186622ee7SYuval Mintz 
174286622ee7SYuval Mintz 	if (!cdev) {
174386622ee7SYuval Mintz 		memset(stats, 0, sizeof(*stats));
174486622ee7SYuval Mintz 		return;
174586622ee7SYuval Mintz 	}
174686622ee7SYuval Mintz 
174786622ee7SYuval Mintz 	_qed_get_vport_stats(cdev, stats);
174886622ee7SYuval Mintz 
174986622ee7SYuval Mintz 	if (!cdev->reset_stats)
175086622ee7SYuval Mintz 		return;
175186622ee7SYuval Mintz 
175286622ee7SYuval Mintz 	/* Reduce the statistics baseline */
175386622ee7SYuval Mintz 	for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
175486622ee7SYuval Mintz 		((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
175586622ee7SYuval Mintz }
175686622ee7SYuval Mintz 
175786622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
175886622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev)
175986622ee7SYuval Mintz {
176086622ee7SYuval Mintz 	int i;
176186622ee7SYuval Mintz 
176286622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
176386622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
176486622ee7SYuval Mintz 		struct eth_mstorm_per_queue_stat mstats;
176586622ee7SYuval Mintz 		struct eth_ustorm_per_queue_stat ustats;
176686622ee7SYuval Mintz 		struct eth_pstorm_per_queue_stat pstats;
1767dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1768dacd88d6SYuval Mintz 						    : NULL;
176986622ee7SYuval Mintz 		u32 addr = 0, len = 0;
177086622ee7SYuval Mintz 
1771dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
177286622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
177386622ee7SYuval Mintz 			continue;
177486622ee7SYuval Mintz 		}
177586622ee7SYuval Mintz 
177686622ee7SYuval Mintz 		memset(&mstats, 0, sizeof(mstats));
177786622ee7SYuval Mintz 		__qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
177886622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
177986622ee7SYuval Mintz 
178086622ee7SYuval Mintz 		memset(&ustats, 0, sizeof(ustats));
178186622ee7SYuval Mintz 		__qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
178286622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
178386622ee7SYuval Mintz 
178486622ee7SYuval Mintz 		memset(&pstats, 0, sizeof(pstats));
178586622ee7SYuval Mintz 		__qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
178686622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
178786622ee7SYuval Mintz 
1788dacd88d6SYuval Mintz 		if (IS_PF(cdev))
178986622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
179086622ee7SYuval Mintz 	}
179186622ee7SYuval Mintz 
179286622ee7SYuval Mintz 	/* PORT statistics are not necessarily reset, so we need to
179386622ee7SYuval Mintz 	 * read and create a baseline for future statistics.
179486622ee7SYuval Mintz 	 */
179586622ee7SYuval Mintz 	if (!cdev->reset_stats)
179686622ee7SYuval Mintz 		DP_INFO(cdev, "Reset stats not allocated\n");
179786622ee7SYuval Mintz 	else
179886622ee7SYuval Mintz 		_qed_get_vport_stats(cdev, cdev->reset_stats);
179986622ee7SYuval Mintz }
180086622ee7SYuval Mintz 
1801d51e4af5SChopra, Manish static void
1802d51e4af5SChopra, Manish qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1803d51e4af5SChopra, Manish 			struct qed_arfs_config_params *p_cfg_params)
1804d51e4af5SChopra, Manish {
1805d51e4af5SChopra, Manish 	if (p_cfg_params->arfs_enable) {
1806d51e4af5SChopra, Manish 		qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1807d51e4af5SChopra, Manish 					p_cfg_params->tcp, p_cfg_params->udp,
1808d51e4af5SChopra, Manish 					p_cfg_params->ipv4, p_cfg_params->ipv6);
1809d51e4af5SChopra, Manish 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
1810d51e4af5SChopra, Manish 			   "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
1811d51e4af5SChopra, Manish 			   p_cfg_params->tcp ? "Enable" : "Disable",
1812d51e4af5SChopra, Manish 			   p_cfg_params->udp ? "Enable" : "Disable",
1813d51e4af5SChopra, Manish 			   p_cfg_params->ipv4 ? "Enable" : "Disable",
1814d51e4af5SChopra, Manish 			   p_cfg_params->ipv6 ? "Enable" : "Disable");
1815d51e4af5SChopra, Manish 	} else {
1816d51e4af5SChopra, Manish 		qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1817d51e4af5SChopra, Manish 	}
1818d51e4af5SChopra, Manish 
1819d51e4af5SChopra, Manish 	DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
1820d51e4af5SChopra, Manish 		   p_cfg_params->arfs_enable ? "Enable" : "Disable");
1821d51e4af5SChopra, Manish }
1822d51e4af5SChopra, Manish 
1823d51e4af5SChopra, Manish static int
1824d51e4af5SChopra, Manish qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1825d51e4af5SChopra, Manish 				struct qed_spq_comp_cb *p_cb,
1826d51e4af5SChopra, Manish 				dma_addr_t p_addr, u16 length, u16 qid,
1827d51e4af5SChopra, Manish 				u8 vport_id, bool b_is_add)
1828d51e4af5SChopra, Manish {
1829d51e4af5SChopra, Manish 	struct rx_update_gft_filter_data *p_ramrod = NULL;
1830d51e4af5SChopra, Manish 	struct qed_spq_entry *p_ent = NULL;
1831d51e4af5SChopra, Manish 	struct qed_sp_init_data init_data;
1832d51e4af5SChopra, Manish 	u16 abs_rx_q_id = 0;
1833d51e4af5SChopra, Manish 	u8 abs_vport_id = 0;
1834d51e4af5SChopra, Manish 	int rc = -EINVAL;
1835d51e4af5SChopra, Manish 
1836d51e4af5SChopra, Manish 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
1837d51e4af5SChopra, Manish 	if (rc)
1838d51e4af5SChopra, Manish 		return rc;
1839d51e4af5SChopra, Manish 
1840d51e4af5SChopra, Manish 	rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
1841d51e4af5SChopra, Manish 	if (rc)
1842d51e4af5SChopra, Manish 		return rc;
1843d51e4af5SChopra, Manish 
1844d51e4af5SChopra, Manish 	/* Get SPQ entry */
1845d51e4af5SChopra, Manish 	memset(&init_data, 0, sizeof(init_data));
1846d51e4af5SChopra, Manish 	init_data.cid = qed_spq_get_cid(p_hwfn);
1847d51e4af5SChopra, Manish 
1848d51e4af5SChopra, Manish 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1849d51e4af5SChopra, Manish 
1850d51e4af5SChopra, Manish 	if (p_cb) {
1851d51e4af5SChopra, Manish 		init_data.comp_mode = QED_SPQ_MODE_CB;
1852d51e4af5SChopra, Manish 		init_data.p_comp_data = p_cb;
1853d51e4af5SChopra, Manish 	} else {
1854d51e4af5SChopra, Manish 		init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1855d51e4af5SChopra, Manish 	}
1856d51e4af5SChopra, Manish 
1857d51e4af5SChopra, Manish 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1858d51e4af5SChopra, Manish 				 ETH_RAMROD_GFT_UPDATE_FILTER,
1859d51e4af5SChopra, Manish 				 PROTOCOLID_ETH, &init_data);
1860d51e4af5SChopra, Manish 	if (rc)
1861d51e4af5SChopra, Manish 		return rc;
1862d51e4af5SChopra, Manish 
1863d51e4af5SChopra, Manish 	p_ramrod = &p_ent->ramrod.rx_update_gft;
1864d51e4af5SChopra, Manish 	DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
1865d51e4af5SChopra, Manish 	p_ramrod->pkt_hdr_length = cpu_to_le16(length);
1866d51e4af5SChopra, Manish 	p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
1867d51e4af5SChopra, Manish 	p_ramrod->vport_id = abs_vport_id;
1868d51e4af5SChopra, Manish 	p_ramrod->filter_type = RFS_FILTER_TYPE;
1869d51e4af5SChopra, Manish 	p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
1870d51e4af5SChopra, Manish 
1871d51e4af5SChopra, Manish 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1872d51e4af5SChopra, Manish 		   "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
1873d51e4af5SChopra, Manish 		   abs_vport_id, abs_rx_q_id,
1874d51e4af5SChopra, Manish 		   b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
1875d51e4af5SChopra, Manish 
1876d51e4af5SChopra, Manish 	return qed_spq_post(p_hwfn, p_ent, NULL);
1877d51e4af5SChopra, Manish }
1878d51e4af5SChopra, Manish 
187925c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev,
188025c089d7SYuval Mintz 				 struct qed_dev_eth_info *info)
188125c089d7SYuval Mintz {
188225c089d7SYuval Mintz 	int i;
188325c089d7SYuval Mintz 
188425c089d7SYuval Mintz 	memset(info, 0, sizeof(*info));
188525c089d7SYuval Mintz 
188625c089d7SYuval Mintz 	info->num_tc = 1;
188725c089d7SYuval Mintz 
18881408cc1fSYuval Mintz 	if (IS_PF(cdev)) {
188925eb8d46SYuval Mintz 		int max_vf_vlan_filters = 0;
18907b7e70f9SYuval Mintz 		int max_vf_mac_filters = 0;
189125eb8d46SYuval Mintz 
189225c089d7SYuval Mintz 		if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
1893e1d32acbSMintz, Yuval 			u16 num_queues = 0;
1894e1d32acbSMintz, Yuval 
1895e1d32acbSMintz, Yuval 			/* Since the feature controls only queue-zones,
1896e1d32acbSMintz, Yuval 			 * make sure we have the contexts [rx, tx, xdp] to
1897e1d32acbSMintz, Yuval 			 * match.
1898e1d32acbSMintz, Yuval 			 */
1899e1d32acbSMintz, Yuval 			for_each_hwfn(cdev, i) {
1900e1d32acbSMintz, Yuval 				struct qed_hwfn *hwfn = &cdev->hwfns[i];
1901e1d32acbSMintz, Yuval 				u16 l2_queues = (u16)FEAT_NUM(hwfn,
1902e1d32acbSMintz, Yuval 							      QED_PF_L2_QUE);
1903e1d32acbSMintz, Yuval 				u16 cids;
1904e1d32acbSMintz, Yuval 
1905e1d32acbSMintz, Yuval 				cids = hwfn->pf_params.eth_pf_params.num_cons;
1906e1d32acbSMintz, Yuval 				num_queues += min_t(u16, l2_queues, cids / 3);
1907e1d32acbSMintz, Yuval 			}
1908e1d32acbSMintz, Yuval 
1909e1d32acbSMintz, Yuval 			/* queues might theoretically be >256, but interrupts'
1910e1d32acbSMintz, Yuval 			 * upper-limit guarantes that it would fit in a u8.
1911e1d32acbSMintz, Yuval 			 */
1912e1d32acbSMintz, Yuval 			if (cdev->int_params.fp_msix_cnt) {
1913e1d32acbSMintz, Yuval 				u8 irqs = cdev->int_params.fp_msix_cnt;
1914e1d32acbSMintz, Yuval 
1915e1d32acbSMintz, Yuval 				info->num_queues = (u8)min_t(u16,
1916e1d32acbSMintz, Yuval 							     num_queues, irqs);
1917e1d32acbSMintz, Yuval 			}
191825c089d7SYuval Mintz 		} else {
191925c089d7SYuval Mintz 			info->num_queues = cdev->num_hwfns;
192025c089d7SYuval Mintz 		}
192125c089d7SYuval Mintz 
19227b7e70f9SYuval Mintz 		if (IS_QED_SRIOV(cdev)) {
192325eb8d46SYuval Mintz 			max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
192425eb8d46SYuval Mintz 					      QED_ETH_VF_NUM_VLAN_FILTERS;
19257b7e70f9SYuval Mintz 			max_vf_mac_filters = cdev->p_iov_info->total_vfs *
19267b7e70f9SYuval Mintz 					     QED_ETH_VF_NUM_MAC_FILTERS;
19277b7e70f9SYuval Mintz 		}
19287b7e70f9SYuval Mintz 		info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
19297b7e70f9SYuval Mintz 						  QED_VLAN) -
193025eb8d46SYuval Mintz 					 max_vf_vlan_filters;
19317b7e70f9SYuval Mintz 		info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
19327b7e70f9SYuval Mintz 						 QED_MAC) -
19337b7e70f9SYuval Mintz 					max_vf_mac_filters;
193425eb8d46SYuval Mintz 
193525c089d7SYuval Mintz 		ether_addr_copy(info->port_mac,
193625c089d7SYuval Mintz 				cdev->hwfns[0].hw_info.hw_mac_addr);
19371408cc1fSYuval Mintz 	} else {
19381408cc1fSYuval Mintz 		qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
19391408cc1fSYuval Mintz 		if (cdev->num_hwfns > 1) {
19401408cc1fSYuval Mintz 			u8 queues = 0;
19411408cc1fSYuval Mintz 
19421408cc1fSYuval Mintz 			qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
19431408cc1fSYuval Mintz 			info->num_queues += queues;
19441408cc1fSYuval Mintz 		}
19451408cc1fSYuval Mintz 
19461408cc1fSYuval Mintz 		qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
19472edbff8dSTomer Tayar 					    (u8 *)&info->num_vlan_filters);
1948b0fca312SMintz, Yuval 		qed_vf_get_num_mac_filters(&cdev->hwfns[0],
1949b0fca312SMintz, Yuval 					   (u8 *)&info->num_mac_filters);
19501408cc1fSYuval Mintz 		qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
1951d8c2c7e3SYuval Mintz 
1952d8c2c7e3SYuval Mintz 		info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
19531408cc1fSYuval Mintz 	}
195425c089d7SYuval Mintz 
195525c089d7SYuval Mintz 	qed_fill_dev_info(cdev, &info->common);
195625c089d7SYuval Mintz 
19571408cc1fSYuval Mintz 	if (IS_VF(cdev))
19580ee28e31SShyam Saini 		eth_zero_addr(info->common.hw_mac);
19591408cc1fSYuval Mintz 
196025c089d7SYuval Mintz 	return 0;
196125c089d7SYuval Mintz }
196225c089d7SYuval Mintz 
1963cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev,
19641408cc1fSYuval Mintz 				 struct qed_eth_cb_ops *ops, void *cookie)
1965cc875c2eSYuval Mintz {
1966cc875c2eSYuval Mintz 	cdev->protocol_ops.eth = ops;
1967cc875c2eSYuval Mintz 	cdev->ops_cookie = cookie;
19681408cc1fSYuval Mintz 
19691408cc1fSYuval Mintz 	/* For VF, we start bulletin reading */
19701408cc1fSYuval Mintz 	if (IS_VF(cdev))
19711408cc1fSYuval Mintz 		qed_vf_start_iov_wq(cdev);
1972cc875c2eSYuval Mintz }
1973cc875c2eSYuval Mintz 
1974eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
1975eff16960SYuval Mintz {
1976eff16960SYuval Mintz 	if (IS_PF(cdev))
1977eff16960SYuval Mintz 		return true;
1978eff16960SYuval Mintz 
1979eff16960SYuval Mintz 	return qed_vf_check_mac(&cdev->hwfns[0], mac);
1980eff16960SYuval Mintz }
1981eff16960SYuval Mintz 
1982cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev,
1983088c8618SManish Chopra 			   struct qed_start_vport_params *params)
1984cee4d264SManish Chopra {
1985cee4d264SManish Chopra 	int rc, i;
1986cee4d264SManish Chopra 
1987cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1988088c8618SManish Chopra 		struct qed_sp_vport_start_params start = { 0 };
1989cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1990cee4d264SManish Chopra 
1991088c8618SManish Chopra 		start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1992088c8618SManish Chopra 							QED_TPA_MODE_NONE;
1993088c8618SManish Chopra 		start.remove_inner_vlan = params->remove_inner_vlan;
199408feecd7SYuval Mintz 		start.only_untagged = true;	/* untagged only */
1995088c8618SManish Chopra 		start.drop_ttl0 = params->drop_ttl0;
1996088c8618SManish Chopra 		start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1997088c8618SManish Chopra 		start.concrete_fid = p_hwfn->hw_info.concrete_fid;
1998c78c70faSSudarsana Reddy Kalluru 		start.handle_ptp_pkts = params->handle_ptp_pkts;
1999088c8618SManish Chopra 		start.vport_id = params->vport_id;
2000088c8618SManish Chopra 		start.max_buffers_per_cqe = 16;
2001088c8618SManish Chopra 		start.mtu = params->mtu;
2002cee4d264SManish Chopra 
2003088c8618SManish Chopra 		rc = qed_sp_vport_start(p_hwfn, &start);
2004cee4d264SManish Chopra 		if (rc) {
2005cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to start VPORT\n");
2006cee4d264SManish Chopra 			return rc;
2007cee4d264SManish Chopra 		}
2008cee4d264SManish Chopra 
200915582962SRahul Verma 		rc = qed_hw_start_fastpath(p_hwfn);
201015582962SRahul Verma 		if (rc) {
201115582962SRahul Verma 			DP_ERR(cdev, "Failed to start VPORT fastpath\n");
201215582962SRahul Verma 			return rc;
201315582962SRahul Verma 		}
2014cee4d264SManish Chopra 
2015cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2016cee4d264SManish Chopra 			   "Started V-PORT %d with MTU %d\n",
2017088c8618SManish Chopra 			   start.vport_id, start.mtu);
2018cee4d264SManish Chopra 	}
2019cee4d264SManish Chopra 
2020a0d26d5aSYuval Mintz 	if (params->clear_stats)
20219df2ed04SManish Chopra 		qed_reset_vport_stats(cdev);
20229df2ed04SManish Chopra 
2023cee4d264SManish Chopra 	return 0;
2024cee4d264SManish Chopra }
2025cee4d264SManish Chopra 
20261a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
2027cee4d264SManish Chopra {
2028cee4d264SManish Chopra 	int rc, i;
2029cee4d264SManish Chopra 
2030cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2031cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2032cee4d264SManish Chopra 
2033cee4d264SManish Chopra 		rc = qed_sp_vport_stop(p_hwfn,
20341a635e48SYuval Mintz 				       p_hwfn->hw_info.opaque_fid, vport_id);
2035cee4d264SManish Chopra 
2036cee4d264SManish Chopra 		if (rc) {
2037cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to stop VPORT\n");
2038cee4d264SManish Chopra 			return rc;
2039cee4d264SManish Chopra 		}
2040cee4d264SManish Chopra 	}
2041cee4d264SManish Chopra 	return 0;
2042cee4d264SManish Chopra }
2043cee4d264SManish Chopra 
2044f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev,
2045f29ffdb6SMintz, Yuval 				struct qed_update_vport_rss_params *input,
2046f29ffdb6SMintz, Yuval 				struct qed_rss_params *rss)
2047f29ffdb6SMintz, Yuval {
2048f29ffdb6SMintz, Yuval 	int i, fn;
2049f29ffdb6SMintz, Yuval 
2050f29ffdb6SMintz, Yuval 	/* Update configuration with what's correct regardless of CMT */
2051f29ffdb6SMintz, Yuval 	rss->update_rss_config = 1;
2052f29ffdb6SMintz, Yuval 	rss->rss_enable = 1;
2053f29ffdb6SMintz, Yuval 	rss->update_rss_capabilities = 1;
2054f29ffdb6SMintz, Yuval 	rss->update_rss_ind_table = 1;
2055f29ffdb6SMintz, Yuval 	rss->update_rss_key = 1;
2056f29ffdb6SMintz, Yuval 	rss->rss_caps = input->rss_caps;
2057f29ffdb6SMintz, Yuval 	memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
2058f29ffdb6SMintz, Yuval 
2059f29ffdb6SMintz, Yuval 	/* In regular scenario, we'd simply need to take input handlers.
2060f29ffdb6SMintz, Yuval 	 * But in CMT, we'd have to split the handlers according to the
2061f29ffdb6SMintz, Yuval 	 * engine they were configured on. We'd then have to understand
2062f29ffdb6SMintz, Yuval 	 * whether RSS is really required, since 2-queues on CMT doesn't
2063f29ffdb6SMintz, Yuval 	 * require RSS.
2064f29ffdb6SMintz, Yuval 	 */
2065f29ffdb6SMintz, Yuval 	if (cdev->num_hwfns == 1) {
2066f29ffdb6SMintz, Yuval 		memcpy(rss->rss_ind_table,
2067f29ffdb6SMintz, Yuval 		       input->rss_ind_table,
2068f29ffdb6SMintz, Yuval 		       QED_RSS_IND_TABLE_SIZE * sizeof(void *));
2069f29ffdb6SMintz, Yuval 		rss->rss_table_size_log = 7;
2070f29ffdb6SMintz, Yuval 		return 0;
2071f29ffdb6SMintz, Yuval 	}
2072f29ffdb6SMintz, Yuval 
2073f29ffdb6SMintz, Yuval 	/* Start by copying the non-spcific information to the 2nd copy */
2074f29ffdb6SMintz, Yuval 	memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
2075f29ffdb6SMintz, Yuval 
2076f29ffdb6SMintz, Yuval 	/* CMT should be round-robin */
2077f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
2078f29ffdb6SMintz, Yuval 		struct qed_queue_cid *cid = input->rss_ind_table[i];
2079f29ffdb6SMintz, Yuval 		struct qed_rss_params *t_rss;
2080f29ffdb6SMintz, Yuval 
2081f29ffdb6SMintz, Yuval 		if (cid->p_owner == QED_LEADING_HWFN(cdev))
2082f29ffdb6SMintz, Yuval 			t_rss = &rss[0];
2083f29ffdb6SMintz, Yuval 		else
2084f29ffdb6SMintz, Yuval 			t_rss = &rss[1];
2085f29ffdb6SMintz, Yuval 
2086f29ffdb6SMintz, Yuval 		t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
2087f29ffdb6SMintz, Yuval 	}
2088f29ffdb6SMintz, Yuval 
2089f29ffdb6SMintz, Yuval 	/* Make sure RSS is actually required */
2090f29ffdb6SMintz, Yuval 	for_each_hwfn(cdev, fn) {
2091f29ffdb6SMintz, Yuval 		for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
2092f29ffdb6SMintz, Yuval 			if (rss[fn].rss_ind_table[i] !=
2093f29ffdb6SMintz, Yuval 			    rss[fn].rss_ind_table[0])
2094f29ffdb6SMintz, Yuval 				break;
2095f29ffdb6SMintz, Yuval 		}
2096f29ffdb6SMintz, Yuval 		if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
2097f29ffdb6SMintz, Yuval 			DP_VERBOSE(cdev, NETIF_MSG_IFUP,
2098f29ffdb6SMintz, Yuval 				   "CMT - 1 queue per-hwfn; Disabling RSS\n");
2099f29ffdb6SMintz, Yuval 			return -EINVAL;
2100f29ffdb6SMintz, Yuval 		}
2101f29ffdb6SMintz, Yuval 		rss[fn].rss_table_size_log = 6;
2102f29ffdb6SMintz, Yuval 	}
2103f29ffdb6SMintz, Yuval 
2104f29ffdb6SMintz, Yuval 	return 0;
2105f29ffdb6SMintz, Yuval }
2106f29ffdb6SMintz, Yuval 
2107cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev,
2108cee4d264SManish Chopra 			    struct qed_update_vport_params *params)
2109cee4d264SManish Chopra {
2110cee4d264SManish Chopra 	struct qed_sp_vport_update_params sp_params;
2111f29ffdb6SMintz, Yuval 	struct qed_rss_params *rss;
2112f29ffdb6SMintz, Yuval 	int rc = 0, i;
2113cee4d264SManish Chopra 
2114cee4d264SManish Chopra 	if (!cdev)
2115cee4d264SManish Chopra 		return -ENODEV;
2116cee4d264SManish Chopra 
2117f29ffdb6SMintz, Yuval 	rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
2118f29ffdb6SMintz, Yuval 	if (!rss)
2119f29ffdb6SMintz, Yuval 		return -ENOMEM;
2120f29ffdb6SMintz, Yuval 
2121cee4d264SManish Chopra 	memset(&sp_params, 0, sizeof(sp_params));
2122cee4d264SManish Chopra 
2123cee4d264SManish Chopra 	/* Translate protocol params into sp params */
2124cee4d264SManish Chopra 	sp_params.vport_id = params->vport_id;
21251a635e48SYuval Mintz 	sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
21261a635e48SYuval Mintz 	sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
2127cee4d264SManish Chopra 	sp_params.vport_active_rx_flg = params->vport_active_flg;
2128cee4d264SManish Chopra 	sp_params.vport_active_tx_flg = params->vport_active_flg;
2129831bfb0eSYuval Mintz 	sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2130831bfb0eSYuval Mintz 	sp_params.tx_switching_flg = params->tx_switching_flg;
21313f9b4a69SYuval Mintz 	sp_params.accept_any_vlan = params->accept_any_vlan;
21323f9b4a69SYuval Mintz 	sp_params.update_accept_any_vlan_flg =
21333f9b4a69SYuval Mintz 		params->update_accept_any_vlan_flg;
2134cee4d264SManish Chopra 
2135f29ffdb6SMintz, Yuval 	/* Prepare the RSS configuration */
2136f29ffdb6SMintz, Yuval 	if (params->update_rss_flg)
2137f29ffdb6SMintz, Yuval 		if (qed_update_vport_rss(cdev, &params->rss_params, rss))
2138cee4d264SManish Chopra 			params->update_rss_flg = 0;
2139cee4d264SManish Chopra 
2140cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2141cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2142cee4d264SManish Chopra 
2143f29ffdb6SMintz, Yuval 		if (params->update_rss_flg)
2144f29ffdb6SMintz, Yuval 			sp_params.rss_params = &rss[i];
2145f29ffdb6SMintz, Yuval 
2146cee4d264SManish Chopra 		sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2147cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &sp_params,
2148cee4d264SManish Chopra 					 QED_SPQ_MODE_EBLOCK,
2149cee4d264SManish Chopra 					 NULL);
2150cee4d264SManish Chopra 		if (rc) {
2151cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to update VPORT\n");
2152f29ffdb6SMintz, Yuval 			goto out;
2153cee4d264SManish Chopra 		}
2154cee4d264SManish Chopra 
2155cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2156cee4d264SManish Chopra 			   "Updated V-PORT %d: active_flag %d [update %d]\n",
2157cee4d264SManish Chopra 			   params->vport_id, params->vport_active_flg,
2158cee4d264SManish Chopra 			   params->update_vport_active_flg);
2159cee4d264SManish Chopra 	}
2160cee4d264SManish Chopra 
2161f29ffdb6SMintz, Yuval out:
2162f29ffdb6SMintz, Yuval 	vfree(rss);
2163f29ffdb6SMintz, Yuval 	return rc;
2164cee4d264SManish Chopra }
2165cee4d264SManish Chopra 
2166cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev,
21673da7a37aSMintz, Yuval 			 u8 rss_num,
21683da7a37aSMintz, Yuval 			 struct qed_queue_start_common_params *p_params,
2169cee4d264SManish Chopra 			 u16 bd_max_bytes,
2170cee4d264SManish Chopra 			 dma_addr_t bd_chain_phys_addr,
2171cee4d264SManish Chopra 			 dma_addr_t cqe_pbl_addr,
2172cee4d264SManish Chopra 			 u16 cqe_pbl_size,
21733da7a37aSMintz, Yuval 			 struct qed_rxq_start_ret_params *ret_params)
2174cee4d264SManish Chopra {
2175cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
21761a635e48SYuval Mintz 	int rc, hwfn_index;
2177cee4d264SManish Chopra 
21783da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2179cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2180cee4d264SManish Chopra 
21813da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
21823da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2183cee4d264SManish Chopra 
21843da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_start(p_hwfn,
2185cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
21863da7a37aSMintz, Yuval 				    p_params,
2187cee4d264SManish Chopra 				    bd_max_bytes,
2188cee4d264SManish Chopra 				    bd_chain_phys_addr,
21893da7a37aSMintz, Yuval 				    cqe_pbl_addr, cqe_pbl_size, ret_params);
2190cee4d264SManish Chopra 	if (rc) {
21913da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
2192cee4d264SManish Chopra 		return rc;
2193cee4d264SManish Chopra 	}
2194cee4d264SManish Chopra 
2195cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
21963da7a37aSMintz, Yuval 		   "Started RX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
21973da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
21983da7a37aSMintz, Yuval 		   p_params->sb);
2199cee4d264SManish Chopra 
2200cee4d264SManish Chopra 	return 0;
2201cee4d264SManish Chopra }
2202cee4d264SManish Chopra 
22033da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
2204cee4d264SManish Chopra {
2205cee4d264SManish Chopra 	int rc, hwfn_index;
2206cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2207cee4d264SManish Chopra 
22083da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2209cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2210cee4d264SManish Chopra 
22113da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
2212cee4d264SManish Chopra 	if (rc) {
22133da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
2214cee4d264SManish Chopra 		return rc;
2215cee4d264SManish Chopra 	}
2216cee4d264SManish Chopra 
2217cee4d264SManish Chopra 	return 0;
2218cee4d264SManish Chopra }
2219cee4d264SManish Chopra 
2220cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev,
22213da7a37aSMintz, Yuval 			 u8 rss_num,
2222cee4d264SManish Chopra 			 struct qed_queue_start_common_params *p_params,
2223cee4d264SManish Chopra 			 dma_addr_t pbl_addr,
2224cee4d264SManish Chopra 			 u16 pbl_size,
22253da7a37aSMintz, Yuval 			 struct qed_txq_start_ret_params *ret_params)
2226cee4d264SManish Chopra {
2227cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2228cee4d264SManish Chopra 	int rc, hwfn_index;
2229cee4d264SManish Chopra 
22303da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2231cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
22323da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
22333da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2234cee4d264SManish Chopra 
22353da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_start(p_hwfn,
2236cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
22373da7a37aSMintz, Yuval 				    p_params, 0,
22383da7a37aSMintz, Yuval 				    pbl_addr, pbl_size, ret_params);
2239cee4d264SManish Chopra 
2240cee4d264SManish Chopra 	if (rc) {
2241cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2242cee4d264SManish Chopra 		return rc;
2243cee4d264SManish Chopra 	}
2244cee4d264SManish Chopra 
2245cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
22463da7a37aSMintz, Yuval 		   "Started TX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
22473da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
2248cee4d264SManish Chopra 		   p_params->sb);
2249cee4d264SManish Chopra 
2250cee4d264SManish Chopra 	return 0;
2251cee4d264SManish Chopra }
2252cee4d264SManish Chopra 
2253cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10)
2254cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev)
2255cee4d264SManish Chopra {
225615582962SRahul Verma 	int rc;
225715582962SRahul Verma 
225815582962SRahul Verma 	rc = qed_hw_stop_fastpath(cdev);
225915582962SRahul Verma 	if (rc) {
226015582962SRahul Verma 		DP_ERR(cdev, "Failed to stop Fastpath\n");
226115582962SRahul Verma 		return rc;
226215582962SRahul Verma 	}
2263cee4d264SManish Chopra 
2264cee4d264SManish Chopra 	return 0;
2265cee4d264SManish Chopra }
2266cee4d264SManish Chopra 
22673da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
2268cee4d264SManish Chopra {
2269cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2270cee4d264SManish Chopra 	int rc, hwfn_index;
2271cee4d264SManish Chopra 
22723da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2273cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2274cee4d264SManish Chopra 
22753da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_stop(p_hwfn, handle);
2276cee4d264SManish Chopra 	if (rc) {
22773da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
2278cee4d264SManish Chopra 		return rc;
2279cee4d264SManish Chopra 	}
2280cee4d264SManish Chopra 
2281cee4d264SManish Chopra 	return 0;
2282cee4d264SManish Chopra }
2283cee4d264SManish Chopra 
2284464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev,
2285464f6645SManish Chopra 			      struct qed_tunn_params *tunn_params)
2286464f6645SManish Chopra {
228719968430SChopra, Manish 	struct qed_tunnel_info tunn_info;
2288464f6645SManish Chopra 	int i, rc;
2289464f6645SManish Chopra 
2290464f6645SManish Chopra 	memset(&tunn_info, 0, sizeof(tunn_info));
229119968430SChopra, Manish 	if (tunn_params->update_vxlan_port) {
229219968430SChopra, Manish 		tunn_info.vxlan_port.b_update_port = true;
229319968430SChopra, Manish 		tunn_info.vxlan_port.port = tunn_params->vxlan_port;
2294464f6645SManish Chopra 	}
2295464f6645SManish Chopra 
229619968430SChopra, Manish 	if (tunn_params->update_geneve_port) {
229719968430SChopra, Manish 		tunn_info.geneve_port.b_update_port = true;
229819968430SChopra, Manish 		tunn_info.geneve_port.port = tunn_params->geneve_port;
2299464f6645SManish Chopra 	}
2300464f6645SManish Chopra 
2301464f6645SManish Chopra 	for_each_hwfn(cdev, i) {
2302464f6645SManish Chopra 		struct qed_hwfn *hwfn = &cdev->hwfns[i];
23034f64675fSManish Chopra 		struct qed_ptt *p_ptt;
230497379f15SChopra, Manish 		struct qed_tunnel_info *tun;
230597379f15SChopra, Manish 
230697379f15SChopra, Manish 		tun = &hwfn->cdev->tunnel;
23074f64675fSManish Chopra 		if (IS_PF(cdev)) {
23084f64675fSManish Chopra 			p_ptt = qed_ptt_acquire(hwfn);
23094f64675fSManish Chopra 			if (!p_ptt)
23104f64675fSManish Chopra 				return -EAGAIN;
23114f64675fSManish Chopra 		} else {
23124f64675fSManish Chopra 			p_ptt = NULL;
23134f64675fSManish Chopra 		}
2314464f6645SManish Chopra 
23154f64675fSManish Chopra 		rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
2316464f6645SManish Chopra 					       QED_SPQ_MODE_EBLOCK, NULL);
23174f64675fSManish Chopra 		if (rc) {
23184f64675fSManish Chopra 			if (IS_PF(cdev))
23194f64675fSManish Chopra 				qed_ptt_release(hwfn, p_ptt);
2320464f6645SManish Chopra 			return rc;
23214f64675fSManish Chopra 		}
232297379f15SChopra, Manish 
232397379f15SChopra, Manish 		if (IS_PF_SRIOV(hwfn)) {
232497379f15SChopra, Manish 			u16 vxlan_port, geneve_port;
232597379f15SChopra, Manish 			int j;
232697379f15SChopra, Manish 
232797379f15SChopra, Manish 			vxlan_port = tun->vxlan_port.port;
232897379f15SChopra, Manish 			geneve_port = tun->geneve_port.port;
232997379f15SChopra, Manish 
233097379f15SChopra, Manish 			qed_for_each_vf(hwfn, j) {
233197379f15SChopra, Manish 				qed_iov_bulletin_set_udp_ports(hwfn, j,
233297379f15SChopra, Manish 							       vxlan_port,
233397379f15SChopra, Manish 							       geneve_port);
233497379f15SChopra, Manish 			}
233597379f15SChopra, Manish 
233697379f15SChopra, Manish 			qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
233797379f15SChopra, Manish 		}
23384f64675fSManish Chopra 		if (IS_PF(cdev))
23394f64675fSManish Chopra 			qed_ptt_release(hwfn, p_ptt);
2340464f6645SManish Chopra 	}
2341464f6645SManish Chopra 
2342464f6645SManish Chopra 	return 0;
2343464f6645SManish Chopra }
2344464f6645SManish Chopra 
2345cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2346cee4d264SManish Chopra 					enum qed_filter_rx_mode_type type)
2347cee4d264SManish Chopra {
2348cee4d264SManish Chopra 	struct qed_filter_accept_flags accept_flags;
2349cee4d264SManish Chopra 
2350cee4d264SManish Chopra 	memset(&accept_flags, 0, sizeof(accept_flags));
2351cee4d264SManish Chopra 
2352cee4d264SManish Chopra 	accept_flags.update_rx_mode_config = 1;
2353cee4d264SManish Chopra 	accept_flags.update_tx_mode_config = 1;
2354cee4d264SManish Chopra 	accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2355cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2356cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2357cee4d264SManish Chopra 	accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2358cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2359cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2360cee4d264SManish Chopra 
236188067876SMintz, Yuval 	if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
2362cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2363cee4d264SManish Chopra 						 QED_ACCEPT_MCAST_UNMATCHED;
236488067876SMintz, Yuval 		accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
236588067876SMintz, Yuval 	} else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
2366cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
236788067876SMintz, Yuval 		accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
236888067876SMintz, Yuval 	}
2369cee4d264SManish Chopra 
23703f9b4a69SYuval Mintz 	return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
2371cee4d264SManish Chopra 				     QED_SPQ_MODE_CB, NULL);
2372cee4d264SManish Chopra }
2373cee4d264SManish Chopra 
2374cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev,
2375cee4d264SManish Chopra 				      struct qed_filter_ucast_params *params)
2376cee4d264SManish Chopra {
2377cee4d264SManish Chopra 	struct qed_filter_ucast ucast;
2378cee4d264SManish Chopra 
2379cee4d264SManish Chopra 	if (!params->vlan_valid && !params->mac_valid) {
23801a635e48SYuval Mintz 		DP_NOTICE(cdev,
2381cee4d264SManish Chopra 			  "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
2382cee4d264SManish Chopra 		return -EINVAL;
2383cee4d264SManish Chopra 	}
2384cee4d264SManish Chopra 
2385cee4d264SManish Chopra 	memset(&ucast, 0, sizeof(ucast));
2386cee4d264SManish Chopra 	switch (params->type) {
2387cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2388cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_ADD;
2389cee4d264SManish Chopra 		break;
2390cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2391cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REMOVE;
2392cee4d264SManish Chopra 		break;
2393cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_REPLACE:
2394cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REPLACE;
2395cee4d264SManish Chopra 		break;
2396cee4d264SManish Chopra 	default:
2397cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2398cee4d264SManish Chopra 			  params->type);
2399cee4d264SManish Chopra 	}
2400cee4d264SManish Chopra 
2401cee4d264SManish Chopra 	if (params->vlan_valid && params->mac_valid) {
2402cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC_VLAN;
2403cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2404cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2405cee4d264SManish Chopra 	} else if (params->mac_valid) {
2406cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC;
2407cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2408cee4d264SManish Chopra 	} else {
2409cee4d264SManish Chopra 		ucast.type = QED_FILTER_VLAN;
2410cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2411cee4d264SManish Chopra 	}
2412cee4d264SManish Chopra 
2413cee4d264SManish Chopra 	ucast.is_rx_filter = true;
2414cee4d264SManish Chopra 	ucast.is_tx_filter = true;
2415cee4d264SManish Chopra 
2416cee4d264SManish Chopra 	return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2417cee4d264SManish Chopra }
2418cee4d264SManish Chopra 
2419cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev,
2420cee4d264SManish Chopra 				      struct qed_filter_mcast_params *params)
2421cee4d264SManish Chopra {
2422cee4d264SManish Chopra 	struct qed_filter_mcast mcast;
2423cee4d264SManish Chopra 	int i;
2424cee4d264SManish Chopra 
2425cee4d264SManish Chopra 	memset(&mcast, 0, sizeof(mcast));
2426cee4d264SManish Chopra 	switch (params->type) {
2427cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2428cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_ADD;
2429cee4d264SManish Chopra 		break;
2430cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2431cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_REMOVE;
2432cee4d264SManish Chopra 		break;
2433cee4d264SManish Chopra 	default:
2434cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2435cee4d264SManish Chopra 			  params->type);
2436cee4d264SManish Chopra 	}
2437cee4d264SManish Chopra 
2438cee4d264SManish Chopra 	mcast.num_mc_addrs = params->num;
2439cee4d264SManish Chopra 	for (i = 0; i < mcast.num_mc_addrs; i++)
2440cee4d264SManish Chopra 		ether_addr_copy(mcast.mac[i], params->mac[i]);
2441cee4d264SManish Chopra 
24421a635e48SYuval Mintz 	return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
2443cee4d264SManish Chopra }
2444cee4d264SManish Chopra 
2445cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev,
2446cee4d264SManish Chopra 				struct qed_filter_params *params)
2447cee4d264SManish Chopra {
2448cee4d264SManish Chopra 	enum qed_filter_rx_mode_type accept_flags;
2449cee4d264SManish Chopra 
2450cee4d264SManish Chopra 	switch (params->type) {
2451cee4d264SManish Chopra 	case QED_FILTER_TYPE_UCAST:
2452cee4d264SManish Chopra 		return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2453cee4d264SManish Chopra 	case QED_FILTER_TYPE_MCAST:
2454cee4d264SManish Chopra 		return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2455cee4d264SManish Chopra 	case QED_FILTER_TYPE_RX_MODE:
2456cee4d264SManish Chopra 		accept_flags = params->filter.accept_flags;
2457cee4d264SManish Chopra 		return qed_configure_filter_rx_mode(cdev, accept_flags);
2458cee4d264SManish Chopra 	default:
24591a635e48SYuval Mintz 		DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
2460cee4d264SManish Chopra 		return -EINVAL;
2461cee4d264SManish Chopra 	}
2462cee4d264SManish Chopra }
2463cee4d264SManish Chopra 
2464d51e4af5SChopra, Manish static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
2465d51e4af5SChopra, Manish {
2466d51e4af5SChopra, Manish 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2467d51e4af5SChopra, Manish 	struct qed_arfs_config_params arfs_config_params;
2468d51e4af5SChopra, Manish 
2469d51e4af5SChopra, Manish 	memset(&arfs_config_params, 0, sizeof(arfs_config_params));
2470d51e4af5SChopra, Manish 	arfs_config_params.tcp = true;
2471d51e4af5SChopra, Manish 	arfs_config_params.udp = true;
2472d51e4af5SChopra, Manish 	arfs_config_params.ipv4 = true;
2473d51e4af5SChopra, Manish 	arfs_config_params.ipv6 = true;
2474d51e4af5SChopra, Manish 	arfs_config_params.arfs_enable = en_searcher;
2475d51e4af5SChopra, Manish 
2476d51e4af5SChopra, Manish 	qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
2477d51e4af5SChopra, Manish 				&arfs_config_params);
2478d51e4af5SChopra, Manish 	return 0;
2479d51e4af5SChopra, Manish }
2480d51e4af5SChopra, Manish 
2481d51e4af5SChopra, Manish static void
2482d51e4af5SChopra, Manish qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
2483d51e4af5SChopra, Manish 			     void *cookie, union event_ring_data *data,
2484d51e4af5SChopra, Manish 			     u8 fw_return_code)
2485d51e4af5SChopra, Manish {
2486d51e4af5SChopra, Manish 	struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
2487d51e4af5SChopra, Manish 	void *dev = p_hwfn->cdev->ops_cookie;
2488d51e4af5SChopra, Manish 
2489d51e4af5SChopra, Manish 	op->arfs_filter_op(dev, cookie, fw_return_code);
2490d51e4af5SChopra, Manish }
2491d51e4af5SChopra, Manish 
2492d51e4af5SChopra, Manish static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
2493d51e4af5SChopra, Manish 					 dma_addr_t mapping, u16 length,
2494d51e4af5SChopra, Manish 					 u16 vport_id, u16 rx_queue_id,
2495d51e4af5SChopra, Manish 					 bool add_filter)
2496d51e4af5SChopra, Manish {
2497d51e4af5SChopra, Manish 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2498d51e4af5SChopra, Manish 	struct qed_spq_comp_cb cb;
2499d51e4af5SChopra, Manish 	int rc = -EINVAL;
2500d51e4af5SChopra, Manish 
2501d51e4af5SChopra, Manish 	cb.function = qed_arfs_sp_response_handler;
2502d51e4af5SChopra, Manish 	cb.cookie = cookie;
2503d51e4af5SChopra, Manish 
2504d51e4af5SChopra, Manish 	rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
2505d51e4af5SChopra, Manish 					     &cb, mapping, length, rx_queue_id,
2506d51e4af5SChopra, Manish 					     vport_id, add_filter);
2507d51e4af5SChopra, Manish 	if (rc)
2508d51e4af5SChopra, Manish 		DP_NOTICE(p_hwfn,
2509d51e4af5SChopra, Manish 			  "Failed to issue a-RFS filter configuration\n");
2510d51e4af5SChopra, Manish 	else
2511d51e4af5SChopra, Manish 		DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
2512d51e4af5SChopra, Manish 			   "Successfully issued a-RFS filter configuration\n");
2513d51e4af5SChopra, Manish 
2514d51e4af5SChopra, Manish 	return rc;
2515d51e4af5SChopra, Manish }
2516d51e4af5SChopra, Manish 
2517cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev,
25181a635e48SYuval Mintz 				 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
2519cee4d264SManish Chopra {
2520cee4d264SManish Chopra 	return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2521cee4d264SManish Chopra 				      cqe);
2522cee4d264SManish Chopra }
2523cee4d264SManish Chopra 
25240b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
25250b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass;
25260b55e27dSYuval Mintz #endif
25270b55e27dSYuval Mintz 
2528a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2529a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2530a1d8d8a5SSudarsana Reddy Kalluru #endif
2531a1d8d8a5SSudarsana Reddy Kalluru 
2532c78c70faSSudarsana Reddy Kalluru extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
2533c78c70faSSudarsana Reddy Kalluru 
253425c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = {
253525c089d7SYuval Mintz 	.common = &qed_common_ops_pass,
25360b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
25370b55e27dSYuval Mintz 	.iov = &qed_iov_ops_pass,
25380b55e27dSYuval Mintz #endif
2539a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2540a1d8d8a5SSudarsana Reddy Kalluru 	.dcb = &qed_dcbnl_ops_pass,
2541a1d8d8a5SSudarsana Reddy Kalluru #endif
2542c78c70faSSudarsana Reddy Kalluru 	.ptp = &qed_ptp_ops_pass,
254325c089d7SYuval Mintz 	.fill_dev_info = &qed_fill_eth_dev_info,
2544cc875c2eSYuval Mintz 	.register_ops = &qed_register_eth_ops,
2545eff16960SYuval Mintz 	.check_mac = &qed_check_mac,
2546cee4d264SManish Chopra 	.vport_start = &qed_start_vport,
2547cee4d264SManish Chopra 	.vport_stop = &qed_stop_vport,
2548cee4d264SManish Chopra 	.vport_update = &qed_update_vport,
2549cee4d264SManish Chopra 	.q_rx_start = &qed_start_rxq,
2550cee4d264SManish Chopra 	.q_rx_stop = &qed_stop_rxq,
2551cee4d264SManish Chopra 	.q_tx_start = &qed_start_txq,
2552cee4d264SManish Chopra 	.q_tx_stop = &qed_stop_txq,
2553cee4d264SManish Chopra 	.filter_config = &qed_configure_filter,
2554cee4d264SManish Chopra 	.fastpath_stop = &qed_fastpath_stop,
2555cee4d264SManish Chopra 	.eth_cqe_completion = &qed_fp_cqe_completion,
25569df2ed04SManish Chopra 	.get_vport_stats = &qed_get_vport_stats,
2557464f6645SManish Chopra 	.tunn_config = &qed_tunn_configure,
2558d51e4af5SChopra, Manish 	.ntuple_filter_config = &qed_ntuple_arfs_filter_config,
2559d51e4af5SChopra, Manish 	.configure_arfs_searcher = &qed_configure_arfs_searcher,
256025c089d7SYuval Mintz };
256125c089d7SYuval Mintz 
256295114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void)
256325c089d7SYuval Mintz {
256425c089d7SYuval Mintz 	return &qed_eth_ops_pass;
256525c089d7SYuval Mintz }
256625c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops);
256725c089d7SYuval Mintz 
256825c089d7SYuval Mintz void qed_put_eth_ops(void)
256925c089d7SYuval Mintz {
257025c089d7SYuval Mintz 	/* TODO - reference count for module? */
257125c089d7SYuval Mintz }
257225c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops);
2573