125c089d7SYuval Mintz /* QLogic qed NIC Driver
2e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
325c089d7SYuval Mintz  *
4e8f1cb50SMintz, Yuval  * This software is available to you under a choice of one of two
5e8f1cb50SMintz, Yuval  * licenses.  You may choose to be licensed under the terms of the GNU
6e8f1cb50SMintz, Yuval  * General Public License (GPL) Version 2, available from the file
7e8f1cb50SMintz, Yuval  * COPYING in the main directory of this source tree, or the
8e8f1cb50SMintz, Yuval  * OpenIB.org BSD license below:
9e8f1cb50SMintz, Yuval  *
10e8f1cb50SMintz, Yuval  *     Redistribution and use in source and binary forms, with or
11e8f1cb50SMintz, Yuval  *     without modification, are permitted provided that the following
12e8f1cb50SMintz, Yuval  *     conditions are met:
13e8f1cb50SMintz, Yuval  *
14e8f1cb50SMintz, Yuval  *      - Redistributions of source code must retain the above
15e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
16e8f1cb50SMintz, Yuval  *        disclaimer.
17e8f1cb50SMintz, Yuval  *
18e8f1cb50SMintz, Yuval  *      - Redistributions in binary form must reproduce the above
19e8f1cb50SMintz, Yuval  *        copyright notice, this list of conditions and the following
20e8f1cb50SMintz, Yuval  *        disclaimer in the documentation and /or other materials
21e8f1cb50SMintz, Yuval  *        provided with the distribution.
22e8f1cb50SMintz, Yuval  *
23e8f1cb50SMintz, Yuval  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24e8f1cb50SMintz, Yuval  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25e8f1cb50SMintz, Yuval  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26e8f1cb50SMintz, Yuval  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27e8f1cb50SMintz, Yuval  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28e8f1cb50SMintz, Yuval  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29e8f1cb50SMintz, Yuval  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30e8f1cb50SMintz, Yuval  * SOFTWARE.
3125c089d7SYuval Mintz  */
3225c089d7SYuval Mintz 
3325c089d7SYuval Mintz #include <linux/types.h>
3425c089d7SYuval Mintz #include <asm/byteorder.h>
3525c089d7SYuval Mintz #include <asm/param.h>
3625c089d7SYuval Mintz #include <linux/delay.h>
3725c089d7SYuval Mintz #include <linux/dma-mapping.h>
3825c089d7SYuval Mintz #include <linux/etherdevice.h>
3925c089d7SYuval Mintz #include <linux/interrupt.h>
4025c089d7SYuval Mintz #include <linux/kernel.h>
4125c089d7SYuval Mintz #include <linux/module.h>
4225c089d7SYuval Mintz #include <linux/pci.h>
4325c089d7SYuval Mintz #include <linux/slab.h>
4425c089d7SYuval Mintz #include <linux/stddef.h>
4525c089d7SYuval Mintz #include <linux/string.h>
4625c089d7SYuval Mintz #include <linux/workqueue.h>
4725c089d7SYuval Mintz #include <linux/bitops.h>
4825c089d7SYuval Mintz #include <linux/bug.h>
493da7a37aSMintz, Yuval #include <linux/vmalloc.h>
5025c089d7SYuval Mintz #include "qed.h"
5125c089d7SYuval Mintz #include <linux/qed/qed_chain.h>
5225c089d7SYuval Mintz #include "qed_cxt.h"
5325c089d7SYuval Mintz #include "qed_dev_api.h"
5425c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h>
5525c089d7SYuval Mintz #include "qed_hsi.h"
5625c089d7SYuval Mintz #include "qed_hw.h"
5725c089d7SYuval Mintz #include "qed_int.h"
58dacd88d6SYuval Mintz #include "qed_l2.h"
5986622ee7SYuval Mintz #include "qed_mcp.h"
6025c089d7SYuval Mintz #include "qed_reg_addr.h"
6125c089d7SYuval Mintz #include "qed_sp.h"
621408cc1fSYuval Mintz #include "qed_sriov.h"
6325c089d7SYuval Mintz 
64088c8618SManish Chopra 
65cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16
66cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41
67cee4d264SManish Chopra 
680db711bbSMintz, Yuval struct qed_l2_info {
690db711bbSMintz, Yuval 	u32 queues;
700db711bbSMintz, Yuval 	unsigned long **pp_qid_usage;
710db711bbSMintz, Yuval 
720db711bbSMintz, Yuval 	/* The lock is meant to synchronize access to the qid usage */
730db711bbSMintz, Yuval 	struct mutex lock;
740db711bbSMintz, Yuval };
750db711bbSMintz, Yuval 
760db711bbSMintz, Yuval int qed_l2_alloc(struct qed_hwfn *p_hwfn)
770db711bbSMintz, Yuval {
780db711bbSMintz, Yuval 	struct qed_l2_info *p_l2_info;
790db711bbSMintz, Yuval 	unsigned long **pp_qids;
800db711bbSMintz, Yuval 	u32 i;
810db711bbSMintz, Yuval 
820db711bbSMintz, Yuval 	if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
830db711bbSMintz, Yuval 	    p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
840db711bbSMintz, Yuval 		return 0;
850db711bbSMintz, Yuval 
860db711bbSMintz, Yuval 	p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL);
870db711bbSMintz, Yuval 	if (!p_l2_info)
880db711bbSMintz, Yuval 		return -ENOMEM;
890db711bbSMintz, Yuval 	p_hwfn->p_l2_info = p_l2_info;
900db711bbSMintz, Yuval 
910db711bbSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
920db711bbSMintz, Yuval 		p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE);
930db711bbSMintz, Yuval 	} else {
940db711bbSMintz, Yuval 		u8 rx = 0, tx = 0;
950db711bbSMintz, Yuval 
960db711bbSMintz, Yuval 		qed_vf_get_num_rxqs(p_hwfn, &rx);
970db711bbSMintz, Yuval 		qed_vf_get_num_txqs(p_hwfn, &tx);
980db711bbSMintz, Yuval 
990db711bbSMintz, Yuval 		p_l2_info->queues = max_t(u8, rx, tx);
1000db711bbSMintz, Yuval 	}
1010db711bbSMintz, Yuval 
1020db711bbSMintz, Yuval 	pp_qids = kzalloc(sizeof(unsigned long *) * p_l2_info->queues,
1030db711bbSMintz, Yuval 			  GFP_KERNEL);
1040db711bbSMintz, Yuval 	if (!pp_qids)
1050db711bbSMintz, Yuval 		return -ENOMEM;
1060db711bbSMintz, Yuval 	p_l2_info->pp_qid_usage = pp_qids;
1070db711bbSMintz, Yuval 
1080db711bbSMintz, Yuval 	for (i = 0; i < p_l2_info->queues; i++) {
1090db711bbSMintz, Yuval 		pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL);
1100db711bbSMintz, Yuval 		if (!pp_qids[i])
1110db711bbSMintz, Yuval 			return -ENOMEM;
1120db711bbSMintz, Yuval 	}
1130db711bbSMintz, Yuval 
1140db711bbSMintz, Yuval 	return 0;
1150db711bbSMintz, Yuval }
1160db711bbSMintz, Yuval 
1170db711bbSMintz, Yuval void qed_l2_setup(struct qed_hwfn *p_hwfn)
1180db711bbSMintz, Yuval {
1190db711bbSMintz, Yuval 	if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
1200db711bbSMintz, Yuval 	    p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
1210db711bbSMintz, Yuval 		return;
1220db711bbSMintz, Yuval 
1230db711bbSMintz, Yuval 	mutex_init(&p_hwfn->p_l2_info->lock);
1240db711bbSMintz, Yuval }
1250db711bbSMintz, Yuval 
1260db711bbSMintz, Yuval void qed_l2_free(struct qed_hwfn *p_hwfn)
1270db711bbSMintz, Yuval {
1280db711bbSMintz, Yuval 	u32 i;
1290db711bbSMintz, Yuval 
1300db711bbSMintz, Yuval 	if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
1310db711bbSMintz, Yuval 	    p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
1320db711bbSMintz, Yuval 		return;
1330db711bbSMintz, Yuval 
1340db711bbSMintz, Yuval 	if (!p_hwfn->p_l2_info)
1350db711bbSMintz, Yuval 		return;
1360db711bbSMintz, Yuval 
1370db711bbSMintz, Yuval 	if (!p_hwfn->p_l2_info->pp_qid_usage)
1380db711bbSMintz, Yuval 		goto out_l2_info;
1390db711bbSMintz, Yuval 
1400db711bbSMintz, Yuval 	/* Free until hit first uninitialized entry */
1410db711bbSMintz, Yuval 	for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
1420db711bbSMintz, Yuval 		if (!p_hwfn->p_l2_info->pp_qid_usage[i])
1430db711bbSMintz, Yuval 			break;
1440db711bbSMintz, Yuval 		kfree(p_hwfn->p_l2_info->pp_qid_usage[i]);
1450db711bbSMintz, Yuval 	}
1460db711bbSMintz, Yuval 
1470db711bbSMintz, Yuval 	kfree(p_hwfn->p_l2_info->pp_qid_usage);
1480db711bbSMintz, Yuval 
1490db711bbSMintz, Yuval out_l2_info:
1500db711bbSMintz, Yuval 	kfree(p_hwfn->p_l2_info);
1510db711bbSMintz, Yuval 	p_hwfn->p_l2_info = NULL;
1520db711bbSMintz, Yuval }
1530db711bbSMintz, Yuval 
1543da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
1553da7a37aSMintz, Yuval 			       struct qed_queue_cid *p_cid)
1563da7a37aSMintz, Yuval {
1573da7a37aSMintz, Yuval 	/* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */
1583946497aSMintz, Yuval 	if ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
1593946497aSMintz, Yuval 	    IS_PF(p_hwfn->cdev))
1603da7a37aSMintz, Yuval 		qed_cxt_release_cid(p_hwfn, p_cid->cid);
1613da7a37aSMintz, Yuval 	vfree(p_cid);
1623da7a37aSMintz, Yuval }
1633da7a37aSMintz, Yuval 
1643da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs
1653da7a37aSMintz, Yuval  * for their VFs.
1663da7a37aSMintz, Yuval  */
1673946497aSMintz, Yuval static struct qed_queue_cid *
1683da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
1693da7a37aSMintz, Yuval 		      u16 opaque_fid,
1703da7a37aSMintz, Yuval 		      u32 cid,
1713946497aSMintz, Yuval 		      struct qed_queue_start_common_params *p_params,
1723946497aSMintz, Yuval 		      struct qed_queue_cid_vf_params *p_vf_params)
1733da7a37aSMintz, Yuval {
1743da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
1753da7a37aSMintz, Yuval 	int rc;
1763da7a37aSMintz, Yuval 
1773da7a37aSMintz, Yuval 	p_cid = vmalloc(sizeof(*p_cid));
1783da7a37aSMintz, Yuval 	if (!p_cid)
1793da7a37aSMintz, Yuval 		return NULL;
1803da7a37aSMintz, Yuval 	memset(p_cid, 0, sizeof(*p_cid));
1813da7a37aSMintz, Yuval 
1823da7a37aSMintz, Yuval 	p_cid->opaque_fid = opaque_fid;
1833da7a37aSMintz, Yuval 	p_cid->cid = cid;
184f29ffdb6SMintz, Yuval 	p_cid->p_owner = p_hwfn;
1853da7a37aSMintz, Yuval 
186f604b17dSMintz, Yuval 	/* Fill in parameters */
187f604b17dSMintz, Yuval 	p_cid->rel.vport_id = p_params->vport_id;
188f604b17dSMintz, Yuval 	p_cid->rel.queue_id = p_params->queue_id;
189f604b17dSMintz, Yuval 	p_cid->rel.stats_id = p_params->stats_id;
190f604b17dSMintz, Yuval 	p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
191f604b17dSMintz, Yuval 	p_cid->sb_idx = p_params->sb_idx;
192f604b17dSMintz, Yuval 
1933946497aSMintz, Yuval 	/* Fill-in bits related to VFs' queues if information was provided */
1943946497aSMintz, Yuval 	if (p_vf_params) {
1953946497aSMintz, Yuval 		p_cid->vfid = p_vf_params->vfid;
1963946497aSMintz, Yuval 		p_cid->vf_qid = p_vf_params->vf_qid;
1973946497aSMintz, Yuval 		p_cid->b_legacy_vf = p_vf_params->vf_legacy;
1983946497aSMintz, Yuval 	} else {
1993946497aSMintz, Yuval 		p_cid->vfid = QED_QUEUE_CID_SELF;
2003946497aSMintz, Yuval 	}
2013946497aSMintz, Yuval 
2023da7a37aSMintz, Yuval 	/* Don't try calculating the absolute indices for VFs */
2033da7a37aSMintz, Yuval 	if (IS_VF(p_hwfn->cdev)) {
2043da7a37aSMintz, Yuval 		p_cid->abs = p_cid->rel;
2053da7a37aSMintz, Yuval 		goto out;
2063da7a37aSMintz, Yuval 	}
2073da7a37aSMintz, Yuval 
2083da7a37aSMintz, Yuval 	/* Calculate the engine-absolute indices of the resources.
2093da7a37aSMintz, Yuval 	 * This would guarantee they're valid later on.
2103da7a37aSMintz, Yuval 	 * In some cases [SBs] we already have the right values.
2113da7a37aSMintz, Yuval 	 */
2123da7a37aSMintz, Yuval 	rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
2133da7a37aSMintz, Yuval 	if (rc)
2143da7a37aSMintz, Yuval 		goto fail;
2153da7a37aSMintz, Yuval 
2163da7a37aSMintz, Yuval 	rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
2173da7a37aSMintz, Yuval 	if (rc)
2183da7a37aSMintz, Yuval 		goto fail;
2193da7a37aSMintz, Yuval 
2203da7a37aSMintz, Yuval 	/* In case of a PF configuring its VF's queues, the stats-id is already
2213da7a37aSMintz, Yuval 	 * absolute [since there's a single index that's suitable per-VF].
2223da7a37aSMintz, Yuval 	 */
2233946497aSMintz, Yuval 	if (p_cid->vfid == QED_QUEUE_CID_SELF) {
2243da7a37aSMintz, Yuval 		rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
2253da7a37aSMintz, Yuval 				  &p_cid->abs.stats_id);
2263da7a37aSMintz, Yuval 		if (rc)
2273da7a37aSMintz, Yuval 			goto fail;
2283da7a37aSMintz, Yuval 	} else {
2293da7a37aSMintz, Yuval 		p_cid->abs.stats_id = p_cid->rel.stats_id;
2303da7a37aSMintz, Yuval 	}
2313da7a37aSMintz, Yuval 
2323da7a37aSMintz, Yuval out:
2333da7a37aSMintz, Yuval 	DP_VERBOSE(p_hwfn,
2343da7a37aSMintz, Yuval 		   QED_MSG_SP,
2353da7a37aSMintz, Yuval 		   "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
2363da7a37aSMintz, Yuval 		   p_cid->opaque_fid,
2373da7a37aSMintz, Yuval 		   p_cid->cid,
2383da7a37aSMintz, Yuval 		   p_cid->rel.vport_id,
2393da7a37aSMintz, Yuval 		   p_cid->abs.vport_id,
2403da7a37aSMintz, Yuval 		   p_cid->rel.queue_id,
2413da7a37aSMintz, Yuval 		   p_cid->abs.queue_id,
2423da7a37aSMintz, Yuval 		   p_cid->rel.stats_id,
243f604b17dSMintz, Yuval 		   p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx);
2443da7a37aSMintz, Yuval 
2453da7a37aSMintz, Yuval 	return p_cid;
2463da7a37aSMintz, Yuval 
2473da7a37aSMintz, Yuval fail:
2483da7a37aSMintz, Yuval 	vfree(p_cid);
2493da7a37aSMintz, Yuval 	return NULL;
2503da7a37aSMintz, Yuval }
2513da7a37aSMintz, Yuval 
2523946497aSMintz, Yuval struct qed_queue_cid *
2533946497aSMintz, Yuval qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
2543946497aSMintz, Yuval 		     u16 opaque_fid,
2553946497aSMintz, Yuval 		     struct qed_queue_start_common_params *p_params,
2563946497aSMintz, Yuval 		     struct qed_queue_cid_vf_params *p_vf_params)
2573da7a37aSMintz, Yuval {
2583da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
2593946497aSMintz, Yuval 	bool b_legacy_vf = false;
2603da7a37aSMintz, Yuval 	u32 cid = 0;
2613da7a37aSMintz, Yuval 
2623946497aSMintz, Yuval 	/* Currently, PF doesn't need to allocate CIDs for any VF */
2633946497aSMintz, Yuval 	if (p_vf_params)
2643946497aSMintz, Yuval 		b_legacy_vf = true;
2653da7a37aSMintz, Yuval 	/* Get a unique firmware CID for this queue, in case it's a PF.
2663da7a37aSMintz, Yuval 	 * VF's don't need a CID as the queue configuration will be done
2673da7a37aSMintz, Yuval 	 * by PF.
2683da7a37aSMintz, Yuval 	 */
2693946497aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) {
2703da7a37aSMintz, Yuval 		if (qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &cid)) {
2713da7a37aSMintz, Yuval 			DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
2723da7a37aSMintz, Yuval 			return NULL;
2733da7a37aSMintz, Yuval 		}
2743da7a37aSMintz, Yuval 	}
2753da7a37aSMintz, Yuval 
2763946497aSMintz, Yuval 	p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
2773946497aSMintz, Yuval 				      p_params, p_vf_params);
2783946497aSMintz, Yuval 	if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf)
2793da7a37aSMintz, Yuval 		qed_cxt_release_cid(p_hwfn, cid);
2803da7a37aSMintz, Yuval 
2813da7a37aSMintz, Yuval 	return p_cid;
2823da7a37aSMintz, Yuval }
2833da7a37aSMintz, Yuval 
2843946497aSMintz, Yuval static struct qed_queue_cid *
2853946497aSMintz, Yuval qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn,
2863946497aSMintz, Yuval 			u16 opaque_fid,
2873946497aSMintz, Yuval 			struct qed_queue_start_common_params *p_params)
2883946497aSMintz, Yuval {
2893946497aSMintz, Yuval 	return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params,
2903946497aSMintz, Yuval 				    NULL);
2913946497aSMintz, Yuval }
2923946497aSMintz, Yuval 
293dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
294088c8618SManish Chopra 			   struct qed_sp_vport_start_params *p_params)
295cee4d264SManish Chopra {
296cee4d264SManish Chopra 	struct vport_start_ramrod_data *p_ramrod = NULL;
297cee4d264SManish Chopra 	struct qed_spq_entry *p_ent =  NULL;
29806f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
299dacd88d6SYuval Mintz 	u8 abs_vport_id = 0;
300cee4d264SManish Chopra 	int rc = -EINVAL;
301cee4d264SManish Chopra 	u16 rx_mode = 0;
302cee4d264SManish Chopra 
303088c8618SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
3041a635e48SYuval Mintz 	if (rc)
305cee4d264SManish Chopra 		return rc;
306cee4d264SManish Chopra 
30706f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
30806f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
309088c8618SManish Chopra 	init_data.opaque_fid = p_params->opaque_fid;
31006f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
311cee4d264SManish Chopra 
312cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
313cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_START,
31406f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
315cee4d264SManish Chopra 	if (rc)
316cee4d264SManish Chopra 		return rc;
317cee4d264SManish Chopra 
318cee4d264SManish Chopra 	p_ramrod		= &p_ent->ramrod.vport_start;
319cee4d264SManish Chopra 	p_ramrod->vport_id	= abs_vport_id;
320cee4d264SManish Chopra 
321088c8618SManish Chopra 	p_ramrod->mtu			= cpu_to_le16(p_params->mtu);
322c78c70faSSudarsana Reddy Kalluru 	p_ramrod->handle_ptp_pkts	= p_params->handle_ptp_pkts;
323088c8618SManish Chopra 	p_ramrod->inner_vlan_removal_en	= p_params->remove_inner_vlan;
324088c8618SManish Chopra 	p_ramrod->drop_ttl0_en		= p_params->drop_ttl0;
325e6bd8923SYuval Mintz 	p_ramrod->untagged		= p_params->only_untagged;
326cee4d264SManish Chopra 
327cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
328cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
329cee4d264SManish Chopra 
330cee4d264SManish Chopra 	p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
331cee4d264SManish Chopra 
332cee4d264SManish Chopra 	/* TPA related fields */
3331a635e48SYuval Mintz 	memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
334cee4d264SManish Chopra 
335088c8618SManish Chopra 	p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
336088c8618SManish Chopra 
337088c8618SManish Chopra 	switch (p_params->tpa_mode) {
338088c8618SManish Chopra 	case QED_TPA_MODE_GRO:
339088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
340088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_size = (u16)-1;
341088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
342088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
343088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
344088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
345088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
346088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
347088c8618SManish Chopra 		break;
348088c8618SManish Chopra 	default:
349088c8618SManish Chopra 		break;
350088c8618SManish Chopra 	}
351088c8618SManish Chopra 
352831bfb0eSYuval Mintz 	p_ramrod->tx_switching_en = p_params->tx_switching;
353831bfb0eSYuval Mintz 
35411a85d75SYuval Mintz 	p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
35511a85d75SYuval Mintz 	p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
35611a85d75SYuval Mintz 
357cee4d264SManish Chopra 	/* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
358cee4d264SManish Chopra 	p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
359088c8618SManish Chopra 						  p_params->concrete_fid);
360cee4d264SManish Chopra 
361cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
362cee4d264SManish Chopra }
363cee4d264SManish Chopra 
364ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
365dacd88d6SYuval Mintz 			      struct qed_sp_vport_start_params *p_params)
366dacd88d6SYuval Mintz {
367dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
368dacd88d6SYuval Mintz 		return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
369dacd88d6SYuval Mintz 					     p_params->mtu,
370dacd88d6SYuval Mintz 					     p_params->remove_inner_vlan,
371dacd88d6SYuval Mintz 					     p_params->tpa_mode,
37208feecd7SYuval Mintz 					     p_params->max_buffers_per_cqe,
37308feecd7SYuval Mintz 					     p_params->only_untagged);
374dacd88d6SYuval Mintz 	}
375dacd88d6SYuval Mintz 
376dacd88d6SYuval Mintz 	return qed_sp_eth_vport_start(p_hwfn, p_params);
377dacd88d6SYuval Mintz }
378dacd88d6SYuval Mintz 
379cee4d264SManish Chopra static int
380cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
381cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
382f29ffdb6SMintz, Yuval 			struct qed_rss_params *p_rss)
383cee4d264SManish Chopra {
384f29ffdb6SMintz, Yuval 	struct eth_vport_rss_config *p_config;
385f29ffdb6SMintz, Yuval 	u16 capabilities = 0;
386f29ffdb6SMintz, Yuval 	int i, table_size;
387f29ffdb6SMintz, Yuval 	int rc = 0;
388cee4d264SManish Chopra 
389f29ffdb6SMintz, Yuval 	if (!p_rss) {
390cee4d264SManish Chopra 		p_ramrod->common.update_rss_flg = 0;
391cee4d264SManish Chopra 		return rc;
392cee4d264SManish Chopra 	}
393f29ffdb6SMintz, Yuval 	p_config = &p_ramrod->rss_config;
394cee4d264SManish Chopra 
395f29ffdb6SMintz, Yuval 	BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
396cee4d264SManish Chopra 
397f29ffdb6SMintz, Yuval 	rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
398cee4d264SManish Chopra 	if (rc)
399cee4d264SManish Chopra 		return rc;
400cee4d264SManish Chopra 
401f29ffdb6SMintz, Yuval 	p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
402f29ffdb6SMintz, Yuval 	p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
403f29ffdb6SMintz, Yuval 	p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
404f29ffdb6SMintz, Yuval 	p_config->update_rss_key = p_rss->update_rss_key;
405cee4d264SManish Chopra 
406f29ffdb6SMintz, Yuval 	p_config->rss_mode = p_rss->rss_enable ?
407cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_REGULAR :
408cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_DISABLED;
409cee4d264SManish Chopra 
410cee4d264SManish Chopra 	SET_FIELD(capabilities,
411cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
412f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4));
413cee4d264SManish Chopra 	SET_FIELD(capabilities,
414cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
415f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6));
416cee4d264SManish Chopra 	SET_FIELD(capabilities,
417cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
418f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
419cee4d264SManish Chopra 	SET_FIELD(capabilities,
420cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
421f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
422cee4d264SManish Chopra 	SET_FIELD(capabilities,
423cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
424f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
425cee4d264SManish Chopra 	SET_FIELD(capabilities,
426cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
427f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
428f29ffdb6SMintz, Yuval 	p_config->tbl_size = p_rss->rss_table_size_log;
429cee4d264SManish Chopra 
430f29ffdb6SMintz, Yuval 	p_config->capabilities = cpu_to_le16(capabilities);
431cee4d264SManish Chopra 
432cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
433cee4d264SManish Chopra 		   "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
434cee4d264SManish Chopra 		   p_ramrod->common.update_rss_flg,
435f29ffdb6SMintz, Yuval 		   p_config->rss_mode,
436f29ffdb6SMintz, Yuval 		   p_config->update_rss_capabilities,
437f29ffdb6SMintz, Yuval 		   p_config->capabilities,
438f29ffdb6SMintz, Yuval 		   p_config->update_rss_ind_table, p_config->update_rss_key);
439cee4d264SManish Chopra 
440f29ffdb6SMintz, Yuval 	table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
441f29ffdb6SMintz, Yuval 			   1 << p_config->tbl_size);
442f29ffdb6SMintz, Yuval 	for (i = 0; i < table_size; i++) {
443f29ffdb6SMintz, Yuval 		struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
444cee4d264SManish Chopra 
445f29ffdb6SMintz, Yuval 		if (!p_queue)
446f29ffdb6SMintz, Yuval 			return -EINVAL;
447f29ffdb6SMintz, Yuval 
448f29ffdb6SMintz, Yuval 		p_config->indirection_table[i] =
449f29ffdb6SMintz, Yuval 		    cpu_to_le16(p_queue->abs.queue_id);
450f29ffdb6SMintz, Yuval 	}
451f29ffdb6SMintz, Yuval 
452f29ffdb6SMintz, Yuval 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
453f29ffdb6SMintz, Yuval 		   "Configured RSS indirection table [%d entries]:\n",
454f29ffdb6SMintz, Yuval 		   table_size);
455f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
456f29ffdb6SMintz, Yuval 		DP_VERBOSE(p_hwfn,
457f29ffdb6SMintz, Yuval 			   NETIF_MSG_IFUP,
458f29ffdb6SMintz, Yuval 			   "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
459f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i]),
460f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 1]),
461f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 2]),
462f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 3]),
463f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 4]),
464f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 5]),
465f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 6]),
466f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 7]),
467f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 8]),
468f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 9]),
469f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 10]),
470f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 11]),
471f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 12]),
472f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 13]),
473f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 14]),
474f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 15]));
475cee4d264SManish Chopra 	}
476cee4d264SManish Chopra 
477cee4d264SManish Chopra 	for (i = 0; i < 10; i++)
478f29ffdb6SMintz, Yuval 		p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
479cee4d264SManish Chopra 
480cee4d264SManish Chopra 	return rc;
481cee4d264SManish Chopra }
482cee4d264SManish Chopra 
483cee4d264SManish Chopra static void
484cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
485cee4d264SManish Chopra 			  struct vport_update_ramrod_data *p_ramrod,
486cee4d264SManish Chopra 			  struct qed_filter_accept_flags accept_flags)
487cee4d264SManish Chopra {
488cee4d264SManish Chopra 	p_ramrod->common.update_rx_mode_flg =
489cee4d264SManish Chopra 		accept_flags.update_rx_mode_config;
490cee4d264SManish Chopra 
491cee4d264SManish Chopra 	p_ramrod->common.update_tx_mode_flg =
492cee4d264SManish Chopra 		accept_flags.update_tx_mode_config;
493cee4d264SManish Chopra 
494cee4d264SManish Chopra 	/* Set Rx mode accept flags */
495cee4d264SManish Chopra 	if (p_ramrod->common.update_rx_mode_flg) {
496cee4d264SManish Chopra 		u8 accept_filter = accept_flags.rx_accept_filter;
497cee4d264SManish Chopra 		u16 state = 0;
498cee4d264SManish Chopra 
499cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
500cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
501cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
502cee4d264SManish Chopra 
503cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
504cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
505cee4d264SManish Chopra 
506cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
507cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
508cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
509cee4d264SManish Chopra 
510cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
511cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
512cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
513cee4d264SManish Chopra 
514cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
515cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
516cee4d264SManish Chopra 
517cee4d264SManish Chopra 		p_ramrod->rx_mode.state = cpu_to_le16(state);
518cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
519cee4d264SManish Chopra 			   "p_ramrod->rx_mode.state = 0x%x\n", state);
520cee4d264SManish Chopra 	}
521cee4d264SManish Chopra 
522cee4d264SManish Chopra 	/* Set Tx mode accept flags */
523cee4d264SManish Chopra 	if (p_ramrod->common.update_tx_mode_flg) {
524cee4d264SManish Chopra 		u8 accept_filter = accept_flags.tx_accept_filter;
525cee4d264SManish Chopra 		u16 state = 0;
526cee4d264SManish Chopra 
527cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
528cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
529cee4d264SManish Chopra 
530cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
531cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
532cee4d264SManish Chopra 
533cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
534cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
535cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
536cee4d264SManish Chopra 
537cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
538cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
539cee4d264SManish Chopra 
540cee4d264SManish Chopra 		p_ramrod->tx_mode.state = cpu_to_le16(state);
541cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
542cee4d264SManish Chopra 			   "p_ramrod->tx_mode.state = 0x%x\n", state);
543cee4d264SManish Chopra 	}
544cee4d264SManish Chopra }
545cee4d264SManish Chopra 
546cee4d264SManish Chopra static void
54717b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
54817b235c1SYuval Mintz 			    struct vport_update_ramrod_data *p_ramrod,
54917b235c1SYuval Mintz 			    struct qed_sge_tpa_params *p_params)
55017b235c1SYuval Mintz {
55117b235c1SYuval Mintz 	struct eth_vport_tpa_param *p_tpa;
55217b235c1SYuval Mintz 
55317b235c1SYuval Mintz 	if (!p_params) {
55417b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
55517b235c1SYuval Mintz 		p_ramrod->common.update_tpa_en_flg = 0;
55617b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
55717b235c1SYuval Mintz 		return;
55817b235c1SYuval Mintz 	}
55917b235c1SYuval Mintz 
56017b235c1SYuval Mintz 	p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
56117b235c1SYuval Mintz 	p_tpa = &p_ramrod->tpa_param;
56217b235c1SYuval Mintz 	p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
56317b235c1SYuval Mintz 	p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
56417b235c1SYuval Mintz 	p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
56517b235c1SYuval Mintz 	p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
56617b235c1SYuval Mintz 
56717b235c1SYuval Mintz 	p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
56817b235c1SYuval Mintz 	p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
56917b235c1SYuval Mintz 	p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
57017b235c1SYuval Mintz 	p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
57117b235c1SYuval Mintz 	p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
57217b235c1SYuval Mintz 	p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
57317b235c1SYuval Mintz 	p_tpa->tpa_max_size = p_params->tpa_max_size;
57417b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
57517b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
57617b235c1SYuval Mintz }
57717b235c1SYuval Mintz 
57817b235c1SYuval Mintz static void
579cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
580cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
581cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params)
582cee4d264SManish Chopra {
583cee4d264SManish Chopra 	int i;
584cee4d264SManish Chopra 
585cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
586cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
587cee4d264SManish Chopra 
58883aeb933SYuval Mintz 	if (!p_params->update_approx_mcast_flg)
58983aeb933SYuval Mintz 		return;
59083aeb933SYuval Mintz 
591cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
592cee4d264SManish Chopra 	for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
593cee4d264SManish Chopra 		u32 *p_bins = (u32 *)p_params->bins;
594cee4d264SManish Chopra 
59583aeb933SYuval Mintz 		p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
596cee4d264SManish Chopra 	}
597cee4d264SManish Chopra }
598cee4d264SManish Chopra 
599dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
600cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params,
601cee4d264SManish Chopra 			enum spq_mode comp_mode,
602cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
603cee4d264SManish Chopra {
604cee4d264SManish Chopra 	struct qed_rss_params *p_rss_params = p_params->rss_params;
605cee4d264SManish Chopra 	struct vport_update_ramrod_data_cmn *p_cmn;
60606f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
607cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
608cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
60917b235c1SYuval Mintz 	u8 abs_vport_id = 0, val;
610cee4d264SManish Chopra 	int rc = -EINVAL;
611cee4d264SManish Chopra 
612dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
613dacd88d6SYuval Mintz 		rc = qed_vf_pf_vport_update(p_hwfn, p_params);
614dacd88d6SYuval Mintz 		return rc;
615dacd88d6SYuval Mintz 	}
616dacd88d6SYuval Mintz 
617cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
6181a635e48SYuval Mintz 	if (rc)
619cee4d264SManish Chopra 		return rc;
620cee4d264SManish Chopra 
62106f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
62206f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
62306f56b81SYuval Mintz 	init_data.opaque_fid = p_params->opaque_fid;
62406f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
62506f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
626cee4d264SManish Chopra 
627cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
628cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
62906f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
630cee4d264SManish Chopra 	if (rc)
631cee4d264SManish Chopra 		return rc;
632cee4d264SManish Chopra 
633cee4d264SManish Chopra 	/* Copy input params to ramrod according to FW struct */
634cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
635cee4d264SManish Chopra 	p_cmn = &p_ramrod->common;
636cee4d264SManish Chopra 
637cee4d264SManish Chopra 	p_cmn->vport_id = abs_vport_id;
638cee4d264SManish Chopra 	p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
639cee4d264SManish Chopra 	p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
640cee4d264SManish Chopra 	p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
641cee4d264SManish Chopra 	p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
6423f9b4a69SYuval Mintz 	p_cmn->accept_any_vlan = p_params->accept_any_vlan;
64383aeb933SYuval Mintz 	val = p_params->update_accept_any_vlan_flg;
64483aeb933SYuval Mintz 	p_cmn->update_accept_any_vlan_flg = val;
64517b235c1SYuval Mintz 
64617b235c1SYuval Mintz 	p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
64717b235c1SYuval Mintz 	val = p_params->update_inner_vlan_removal_flg;
64817b235c1SYuval Mintz 	p_cmn->update_inner_vlan_removal_en_flg = val;
64908feecd7SYuval Mintz 
65008feecd7SYuval Mintz 	p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
65108feecd7SYuval Mintz 	val = p_params->update_default_vlan_enable_flg;
65208feecd7SYuval Mintz 	p_cmn->update_default_vlan_en_flg = val;
65308feecd7SYuval Mintz 
65408feecd7SYuval Mintz 	p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
65508feecd7SYuval Mintz 	p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
65608feecd7SYuval Mintz 
65708feecd7SYuval Mintz 	p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
65808feecd7SYuval Mintz 
65917b235c1SYuval Mintz 	p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
66017b235c1SYuval Mintz 	p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
66117b235c1SYuval Mintz 
6626ddc7608SYuval Mintz 	p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
6636ddc7608SYuval Mintz 	val = p_params->update_anti_spoofing_en_flg;
6646ddc7608SYuval Mintz 	p_ramrod->common.update_anti_spoofing_en_flg = val;
6656ddc7608SYuval Mintz 
666cee4d264SManish Chopra 	rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
667cee4d264SManish Chopra 	if (rc) {
668cee4d264SManish Chopra 		/* Return spq entry which is taken in qed_sp_init_request()*/
669cee4d264SManish Chopra 		qed_spq_return_entry(p_hwfn, p_ent);
670cee4d264SManish Chopra 		return rc;
671cee4d264SManish Chopra 	}
672cee4d264SManish Chopra 
673cee4d264SManish Chopra 	/* Update mcast bins for VFs, PF doesn't use this functionality */
674cee4d264SManish Chopra 	qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
675cee4d264SManish Chopra 
676cee4d264SManish Chopra 	qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
67717b235c1SYuval Mintz 	qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
678cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
679cee4d264SManish Chopra }
680cee4d264SManish Chopra 
681dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
682cee4d264SManish Chopra {
683cee4d264SManish Chopra 	struct vport_stop_ramrod_data *p_ramrod;
68406f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
685cee4d264SManish Chopra 	struct qed_spq_entry *p_ent;
686cee4d264SManish Chopra 	u8 abs_vport_id = 0;
687cee4d264SManish Chopra 	int rc;
688cee4d264SManish Chopra 
689dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
690dacd88d6SYuval Mintz 		return qed_vf_pf_vport_stop(p_hwfn);
691dacd88d6SYuval Mintz 
692cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
6931a635e48SYuval Mintz 	if (rc)
694cee4d264SManish Chopra 		return rc;
695cee4d264SManish Chopra 
69606f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
69706f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
69806f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
69906f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
700cee4d264SManish Chopra 
701cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
702cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_STOP,
70306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
704cee4d264SManish Chopra 	if (rc)
705cee4d264SManish Chopra 		return rc;
706cee4d264SManish Chopra 
707cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_stop;
708cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
709cee4d264SManish Chopra 
710cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
711cee4d264SManish Chopra }
712cee4d264SManish Chopra 
713dacd88d6SYuval Mintz static int
714dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
715dacd88d6SYuval Mintz 		       struct qed_filter_accept_flags *p_accept_flags)
716dacd88d6SYuval Mintz {
717dacd88d6SYuval Mintz 	struct qed_sp_vport_update_params s_params;
718dacd88d6SYuval Mintz 
719dacd88d6SYuval Mintz 	memset(&s_params, 0, sizeof(s_params));
720dacd88d6SYuval Mintz 	memcpy(&s_params.accept_flags, p_accept_flags,
721dacd88d6SYuval Mintz 	       sizeof(struct qed_filter_accept_flags));
722dacd88d6SYuval Mintz 
723dacd88d6SYuval Mintz 	return qed_vf_pf_vport_update(p_hwfn, &s_params);
724dacd88d6SYuval Mintz }
725dacd88d6SYuval Mintz 
726cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev,
727cee4d264SManish Chopra 				 u8 vport,
728cee4d264SManish Chopra 				 struct qed_filter_accept_flags accept_flags,
7293f9b4a69SYuval Mintz 				 u8 update_accept_any_vlan,
7303f9b4a69SYuval Mintz 				 u8 accept_any_vlan,
731cee4d264SManish Chopra 				 enum spq_mode comp_mode,
732cee4d264SManish Chopra 				 struct qed_spq_comp_cb *p_comp_data)
733cee4d264SManish Chopra {
734cee4d264SManish Chopra 	struct qed_sp_vport_update_params vport_update_params;
735cee4d264SManish Chopra 	int i, rc;
736cee4d264SManish Chopra 
737cee4d264SManish Chopra 	/* Prepare and send the vport rx_mode change */
738cee4d264SManish Chopra 	memset(&vport_update_params, 0, sizeof(vport_update_params));
739cee4d264SManish Chopra 	vport_update_params.vport_id = vport;
740cee4d264SManish Chopra 	vport_update_params.accept_flags = accept_flags;
7413f9b4a69SYuval Mintz 	vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
7423f9b4a69SYuval Mintz 	vport_update_params.accept_any_vlan = accept_any_vlan;
743cee4d264SManish Chopra 
744cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
745cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
746cee4d264SManish Chopra 
747cee4d264SManish Chopra 		vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
748cee4d264SManish Chopra 
749dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
750dacd88d6SYuval Mintz 			rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
751dacd88d6SYuval Mintz 			if (rc)
752dacd88d6SYuval Mintz 				return rc;
753dacd88d6SYuval Mintz 			continue;
754dacd88d6SYuval Mintz 		}
755dacd88d6SYuval Mintz 
756cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
757cee4d264SManish Chopra 					 comp_mode, p_comp_data);
7581a635e48SYuval Mintz 		if (rc) {
759cee4d264SManish Chopra 			DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
760cee4d264SManish Chopra 			return rc;
761cee4d264SManish Chopra 		}
762cee4d264SManish Chopra 
763cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
764cee4d264SManish Chopra 			   "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
765cee4d264SManish Chopra 			   accept_flags.rx_accept_filter,
766cee4d264SManish Chopra 			   accept_flags.tx_accept_filter);
7673f9b4a69SYuval Mintz 		if (update_accept_any_vlan)
7683f9b4a69SYuval Mintz 			DP_VERBOSE(p_hwfn, QED_MSG_SP,
7693f9b4a69SYuval Mintz 				   "accept_any_vlan=%d configured\n",
7703f9b4a69SYuval Mintz 				   accept_any_vlan);
771cee4d264SManish Chopra 	}
772cee4d264SManish Chopra 
773cee4d264SManish Chopra 	return 0;
774cee4d264SManish Chopra }
775cee4d264SManish Chopra 
7763da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
7773da7a37aSMintz, Yuval 			     struct qed_queue_cid *p_cid,
778cee4d264SManish Chopra 			     u16 bd_max_bytes,
779cee4d264SManish Chopra 			     dma_addr_t bd_chain_phys_addr,
7803da7a37aSMintz, Yuval 			     dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
781cee4d264SManish Chopra {
782cee4d264SManish Chopra 	struct rx_queue_start_ramrod_data *p_ramrod = NULL;
783cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
78406f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
785cee4d264SManish Chopra 	int rc = -EINVAL;
786cee4d264SManish Chopra 
787cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
7883da7a37aSMintz, Yuval 		   "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
7893da7a37aSMintz, Yuval 		   p_cid->opaque_fid, p_cid->cid,
790f604b17dSMintz, Yuval 		   p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id);
791cee4d264SManish Chopra 
79206f56b81SYuval Mintz 	/* Get SPQ entry */
79306f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
7943da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
7953da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
79606f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
797cee4d264SManish Chopra 
798cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
799cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_START,
80006f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
801cee4d264SManish Chopra 	if (rc)
802cee4d264SManish Chopra 		return rc;
803cee4d264SManish Chopra 
804cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_start;
805cee4d264SManish Chopra 
806f604b17dSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
807f604b17dSMintz, Yuval 	p_ramrod->sb_index = p_cid->sb_idx;
8083da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
8093da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
8103da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
811cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg = 0;
812cee4d264SManish Chopra 	p_ramrod->complete_event_flg = 1;
813cee4d264SManish Chopra 
814cee4d264SManish Chopra 	p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
81594494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
816cee4d264SManish Chopra 
817cee4d264SManish Chopra 	p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
81894494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
819cee4d264SManish Chopra 
8203946497aSMintz, Yuval 	if (p_cid->vfid != QED_QUEUE_CID_SELF) {
8213da7a37aSMintz, Yuval 		p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
822351a4dedSYuval Mintz 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
823a044df83SYuval Mintz 			   "Queue%s is meant for VF rxq[%02x]\n",
8243da7a37aSMintz, Yuval 			   !!p_cid->b_legacy_vf ? " [legacy]" : "",
8253da7a37aSMintz, Yuval 			   p_cid->vf_qid);
8263da7a37aSMintz, Yuval 		p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf;
827a044df83SYuval Mintz 	}
828cee4d264SManish Chopra 
829351a4dedSYuval Mintz 	return qed_spq_post(p_hwfn, p_ent, NULL);
830cee4d264SManish Chopra }
831cee4d264SManish Chopra 
832cee4d264SManish Chopra static int
8333da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
8343da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
835cee4d264SManish Chopra 			  u16 bd_max_bytes,
836cee4d264SManish Chopra 			  dma_addr_t bd_chain_phys_addr,
837cee4d264SManish Chopra 			  dma_addr_t cqe_pbl_addr,
838dacd88d6SYuval Mintz 			  u16 cqe_pbl_size, void __iomem **pp_prod)
839cee4d264SManish Chopra {
840b21290b7SYuval Mintz 	u32 init_prod_val = 0;
841cee4d264SManish Chopra 
8423da7a37aSMintz, Yuval 	*pp_prod = p_hwfn->regview +
843cee4d264SManish Chopra 		   GTT_BAR0_MAP_REG_MSDM_RAM +
8443da7a37aSMintz, Yuval 		    MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
845cee4d264SManish Chopra 
846cee4d264SManish Chopra 	/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
847b21290b7SYuval Mintz 	__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
848cee4d264SManish Chopra 			  (u32 *)(&init_prod_val));
849cee4d264SManish Chopra 
8503da7a37aSMintz, Yuval 	return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
851cee4d264SManish Chopra 					bd_max_bytes,
852cee4d264SManish Chopra 					bd_chain_phys_addr,
8533da7a37aSMintz, Yuval 					cqe_pbl_addr, cqe_pbl_size);
8543da7a37aSMintz, Yuval }
855cee4d264SManish Chopra 
8563da7a37aSMintz, Yuval static int
8573da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
8583da7a37aSMintz, Yuval 		       u16 opaque_fid,
8593da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
8603da7a37aSMintz, Yuval 		       u16 bd_max_bytes,
8613da7a37aSMintz, Yuval 		       dma_addr_t bd_chain_phys_addr,
8623da7a37aSMintz, Yuval 		       dma_addr_t cqe_pbl_addr,
8633da7a37aSMintz, Yuval 		       u16 cqe_pbl_size,
8643da7a37aSMintz, Yuval 		       struct qed_rxq_start_ret_params *p_ret_params)
8653da7a37aSMintz, Yuval {
8663da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
8673da7a37aSMintz, Yuval 	int rc;
8683da7a37aSMintz, Yuval 
8693da7a37aSMintz, Yuval 	/* Allocate a CID for the queue */
8703946497aSMintz, Yuval 	p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
8713da7a37aSMintz, Yuval 	if (!p_cid)
8723da7a37aSMintz, Yuval 		return -ENOMEM;
8733da7a37aSMintz, Yuval 
8743da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
8753da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
8763da7a37aSMintz, Yuval 					       bd_max_bytes,
8773da7a37aSMintz, Yuval 					       bd_chain_phys_addr,
8783da7a37aSMintz, Yuval 					       cqe_pbl_addr, cqe_pbl_size,
8793da7a37aSMintz, Yuval 					       &p_ret_params->p_prod);
8803da7a37aSMintz, Yuval 	} else {
8813da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
8823da7a37aSMintz, Yuval 					 bd_max_bytes,
8833da7a37aSMintz, Yuval 					 bd_chain_phys_addr,
8843da7a37aSMintz, Yuval 					 cqe_pbl_addr,
8853da7a37aSMintz, Yuval 					 cqe_pbl_size, &p_ret_params->p_prod);
8863da7a37aSMintz, Yuval 	}
8873da7a37aSMintz, Yuval 
8883da7a37aSMintz, Yuval 	/* Provide the caller with a reference to as handler */
8891a635e48SYuval Mintz 	if (rc)
8903da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
8913da7a37aSMintz, Yuval 	else
8923da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
893cee4d264SManish Chopra 
894cee4d264SManish Chopra 	return rc;
895cee4d264SManish Chopra }
896cee4d264SManish Chopra 
89717b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
8983da7a37aSMintz, Yuval 				void **pp_rxq_handles,
89917b235c1SYuval Mintz 				u8 num_rxqs,
90017b235c1SYuval Mintz 				u8 complete_cqe_flg,
90117b235c1SYuval Mintz 				u8 complete_event_flg,
90217b235c1SYuval Mintz 				enum spq_mode comp_mode,
90317b235c1SYuval Mintz 				struct qed_spq_comp_cb *p_comp_data)
90417b235c1SYuval Mintz {
90517b235c1SYuval Mintz 	struct rx_queue_update_ramrod_data *p_ramrod = NULL;
90617b235c1SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
90717b235c1SYuval Mintz 	struct qed_sp_init_data init_data;
9083da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
90917b235c1SYuval Mintz 	int rc = -EINVAL;
91017b235c1SYuval Mintz 	u8 i;
91117b235c1SYuval Mintz 
91217b235c1SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
91317b235c1SYuval Mintz 	init_data.comp_mode = comp_mode;
91417b235c1SYuval Mintz 	init_data.p_comp_data = p_comp_data;
91517b235c1SYuval Mintz 
91617b235c1SYuval Mintz 	for (i = 0; i < num_rxqs; i++) {
9173da7a37aSMintz, Yuval 		p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
91817b235c1SYuval Mintz 
91917b235c1SYuval Mintz 		/* Get SPQ entry */
9203da7a37aSMintz, Yuval 		init_data.cid = p_cid->cid;
9213da7a37aSMintz, Yuval 		init_data.opaque_fid = p_cid->opaque_fid;
92217b235c1SYuval Mintz 
92317b235c1SYuval Mintz 		rc = qed_sp_init_request(p_hwfn, &p_ent,
92417b235c1SYuval Mintz 					 ETH_RAMROD_RX_QUEUE_UPDATE,
92517b235c1SYuval Mintz 					 PROTOCOLID_ETH, &init_data);
92617b235c1SYuval Mintz 		if (rc)
92717b235c1SYuval Mintz 			return rc;
92817b235c1SYuval Mintz 
92917b235c1SYuval Mintz 		p_ramrod = &p_ent->ramrod.rx_queue_update;
9303da7a37aSMintz, Yuval 		p_ramrod->vport_id = p_cid->abs.vport_id;
93117b235c1SYuval Mintz 
9323da7a37aSMintz, Yuval 		p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
93317b235c1SYuval Mintz 		p_ramrod->complete_cqe_flg = complete_cqe_flg;
93417b235c1SYuval Mintz 		p_ramrod->complete_event_flg = complete_event_flg;
93517b235c1SYuval Mintz 
93617b235c1SYuval Mintz 		rc = qed_spq_post(p_hwfn, p_ent, NULL);
93717b235c1SYuval Mintz 		if (rc)
93817b235c1SYuval Mintz 			return rc;
93917b235c1SYuval Mintz 	}
94017b235c1SYuval Mintz 
94117b235c1SYuval Mintz 	return rc;
94217b235c1SYuval Mintz }
94317b235c1SYuval Mintz 
9443da7a37aSMintz, Yuval static int
9453da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
9463da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
9473da7a37aSMintz, Yuval 			 bool b_eq_completion_only, bool b_cqe_completion)
948cee4d264SManish Chopra {
949cee4d264SManish Chopra 	struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
950cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
95106f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
9523da7a37aSMintz, Yuval 	int rc;
953cee4d264SManish Chopra 
95406f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
9553da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
9563da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
95706f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
958cee4d264SManish Chopra 
959cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
960cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_STOP,
96106f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
962cee4d264SManish Chopra 	if (rc)
963cee4d264SManish Chopra 		return rc;
964cee4d264SManish Chopra 
965cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_stop;
9663da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
9673da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
968cee4d264SManish Chopra 
969cee4d264SManish Chopra 	/* Cleaning the queue requires the completion to arrive there.
970cee4d264SManish Chopra 	 * In addition, VFs require the answer to come as eqe to PF.
971cee4d264SManish Chopra 	 */
9723946497aSMintz, Yuval 	p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
9733da7a37aSMintz, Yuval 				      !b_eq_completion_only) ||
9743da7a37aSMintz, Yuval 				     b_cqe_completion;
9753946497aSMintz, Yuval 	p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) ||
9763946497aSMintz, Yuval 				       b_eq_completion_only;
977cee4d264SManish Chopra 
9783da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
979cee4d264SManish Chopra }
980cee4d264SManish Chopra 
9813da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
9823da7a37aSMintz, Yuval 			  void *p_rxq,
9833da7a37aSMintz, Yuval 			  bool eq_completion_only, bool cqe_completion)
9843da7a37aSMintz, Yuval {
9853da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
9863da7a37aSMintz, Yuval 	int rc = -EINVAL;
9873da7a37aSMintz, Yuval 
9883da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
9893da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
9903da7a37aSMintz, Yuval 					      eq_completion_only,
9913da7a37aSMintz, Yuval 					      cqe_completion);
9923da7a37aSMintz, Yuval 	else
9933da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
9943da7a37aSMintz, Yuval 
9953da7a37aSMintz, Yuval 	if (!rc)
9963da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
9973da7a37aSMintz, Yuval 	return rc;
9983da7a37aSMintz, Yuval }
9993da7a37aSMintz, Yuval 
10003da7a37aSMintz, Yuval int
10013da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
10023da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
10033da7a37aSMintz, Yuval 			 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
1004cee4d264SManish Chopra {
1005cee4d264SManish Chopra 	struct tx_queue_start_ramrod_data *p_ramrod = NULL;
1006cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
100706f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1008cee4d264SManish Chopra 	int rc = -EINVAL;
1009351a4dedSYuval Mintz 
101006f56b81SYuval Mintz 	/* Get SPQ entry */
101106f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
10123da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
10133da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
101406f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1015cee4d264SManish Chopra 
101606f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1017cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_START,
101806f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1019cee4d264SManish Chopra 	if (rc)
1020cee4d264SManish Chopra 		return rc;
1021cee4d264SManish Chopra 
1022cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.tx_queue_start;
10233da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
1024cee4d264SManish Chopra 
1025f604b17dSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
1026f604b17dSMintz, Yuval 	p_ramrod->sb_index = p_cid->sb_idx;
10273da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
1028cee4d264SManish Chopra 
10293da7a37aSMintz, Yuval 	p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
10303da7a37aSMintz, Yuval 	p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
10311a635e48SYuval Mintz 
1032cee4d264SManish Chopra 	p_ramrod->pbl_size = cpu_to_le16(pbl_size);
103394494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
1034cee4d264SManish Chopra 
1035cee4d264SManish Chopra 	p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
1036cee4d264SManish Chopra 
1037cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1038cee4d264SManish Chopra }
1039cee4d264SManish Chopra 
1040cee4d264SManish Chopra static int
10413da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
10423da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
10433da7a37aSMintz, Yuval 			  u8 tc,
1044cee4d264SManish Chopra 			  dma_addr_t pbl_addr,
1045dacd88d6SYuval Mintz 			  u16 pbl_size, void __iomem **pp_doorbell)
1046cee4d264SManish Chopra {
1047cee4d264SManish Chopra 	int rc;
1048cee4d264SManish Chopra 
1049cee4d264SManish Chopra 
10503da7a37aSMintz, Yuval 	rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
10513da7a37aSMintz, Yuval 				      pbl_addr, pbl_size,
1052b5a9ee7cSAriel Elior 				      qed_get_cm_pq_idx_mcos(p_hwfn, tc));
10533da7a37aSMintz, Yuval 	if (rc)
1054cee4d264SManish Chopra 		return rc;
10553da7a37aSMintz, Yuval 
10563da7a37aSMintz, Yuval 	/* Provide the caller with the necessary return values */
10573da7a37aSMintz, Yuval 	*pp_doorbell = p_hwfn->doorbells +
10583da7a37aSMintz, Yuval 		       qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
10593da7a37aSMintz, Yuval 
10603da7a37aSMintz, Yuval 	return 0;
1061cee4d264SManish Chopra }
1062cee4d264SManish Chopra 
10633da7a37aSMintz, Yuval static int
10643da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
10653da7a37aSMintz, Yuval 		       u16 opaque_fid,
10663da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
10673da7a37aSMintz, Yuval 		       u8 tc,
10683da7a37aSMintz, Yuval 		       dma_addr_t pbl_addr,
10693da7a37aSMintz, Yuval 		       u16 pbl_size,
10703da7a37aSMintz, Yuval 		       struct qed_txq_start_ret_params *p_ret_params)
10713da7a37aSMintz, Yuval {
10723da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
10733da7a37aSMintz, Yuval 	int rc;
1074cee4d264SManish Chopra 
10753946497aSMintz, Yuval 	p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
10763da7a37aSMintz, Yuval 	if (!p_cid)
10773da7a37aSMintz, Yuval 		return -EINVAL;
1078cee4d264SManish Chopra 
10793da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
10803da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
10813da7a37aSMintz, Yuval 					       pbl_addr, pbl_size,
10823da7a37aSMintz, Yuval 					       &p_ret_params->p_doorbell);
10833da7a37aSMintz, Yuval 	else
10843da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
10853da7a37aSMintz, Yuval 					 pbl_addr, pbl_size,
10863da7a37aSMintz, Yuval 					 &p_ret_params->p_doorbell);
1087cee4d264SManish Chopra 
1088cee4d264SManish Chopra 	if (rc)
10893da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
10903da7a37aSMintz, Yuval 	else
10913da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
1092cee4d264SManish Chopra 
1093cee4d264SManish Chopra 	return rc;
1094cee4d264SManish Chopra }
1095cee4d264SManish Chopra 
10963da7a37aSMintz, Yuval static int
10973da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
1098cee4d264SManish Chopra {
1099cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
110006f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
11013da7a37aSMintz, Yuval 	int rc;
1102cee4d264SManish Chopra 
110306f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
11043da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
11053da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
110606f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1107cee4d264SManish Chopra 
1108cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1109cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_STOP,
111006f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1111cee4d264SManish Chopra 	if (rc)
1112cee4d264SManish Chopra 		return rc;
1113cee4d264SManish Chopra 
11143da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
11153da7a37aSMintz, Yuval }
1116cee4d264SManish Chopra 
11173da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
11183da7a37aSMintz, Yuval {
11193da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
11203da7a37aSMintz, Yuval 	int rc;
11213da7a37aSMintz, Yuval 
11223da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
11233da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
11243da7a37aSMintz, Yuval 	else
11253da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
11263da7a37aSMintz, Yuval 
11273da7a37aSMintz, Yuval 	if (!rc)
11283da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
11293da7a37aSMintz, Yuval 	return rc;
1130cee4d264SManish Chopra }
1131cee4d264SManish Chopra 
11321a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
1133cee4d264SManish Chopra {
1134cee4d264SManish Chopra 	enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1135cee4d264SManish Chopra 
1136cee4d264SManish Chopra 	switch (opcode) {
1137cee4d264SManish Chopra 	case QED_FILTER_ADD:
1138cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_ADD;
1139cee4d264SManish Chopra 		break;
1140cee4d264SManish Chopra 	case QED_FILTER_REMOVE:
1141cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_REMOVE;
1142cee4d264SManish Chopra 		break;
1143cee4d264SManish Chopra 	case QED_FILTER_FLUSH:
1144fc48b7a6SYuval Mintz 		action = ETH_FILTER_ACTION_REMOVE_ALL;
1145cee4d264SManish Chopra 		break;
1146cee4d264SManish Chopra 	default:
1147cee4d264SManish Chopra 		action = MAX_ETH_FILTER_ACTION;
1148cee4d264SManish Chopra 	}
1149cee4d264SManish Chopra 
1150cee4d264SManish Chopra 	return action;
1151cee4d264SManish Chopra }
1152cee4d264SManish Chopra 
1153cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb,
1154cee4d264SManish Chopra 				__le16 *fw_mid,
1155cee4d264SManish Chopra 				__le16 *fw_lsb,
1156cee4d264SManish Chopra 				u8 *mac)
1157cee4d264SManish Chopra {
1158cee4d264SManish Chopra 	((u8 *)fw_msb)[0] = mac[1];
1159cee4d264SManish Chopra 	((u8 *)fw_msb)[1] = mac[0];
1160cee4d264SManish Chopra 	((u8 *)fw_mid)[0] = mac[3];
1161cee4d264SManish Chopra 	((u8 *)fw_mid)[1] = mac[2];
1162cee4d264SManish Chopra 	((u8 *)fw_lsb)[0] = mac[5];
1163cee4d264SManish Chopra 	((u8 *)fw_lsb)[1] = mac[4];
1164cee4d264SManish Chopra }
1165cee4d264SManish Chopra 
1166cee4d264SManish Chopra static int
1167cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1168cee4d264SManish Chopra 			u16 opaque_fid,
1169cee4d264SManish Chopra 			struct qed_filter_ucast *p_filter_cmd,
1170cee4d264SManish Chopra 			struct vport_filter_update_ramrod_data **pp_ramrod,
1171cee4d264SManish Chopra 			struct qed_spq_entry **pp_ent,
1172cee4d264SManish Chopra 			enum spq_mode comp_mode,
1173cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1174cee4d264SManish Chopra {
1175cee4d264SManish Chopra 	u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1176cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data *p_ramrod;
1177cee4d264SManish Chopra 	struct eth_filter_cmd *p_first_filter;
1178cee4d264SManish Chopra 	struct eth_filter_cmd *p_second_filter;
117906f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1180cee4d264SManish Chopra 	enum eth_filter_action action;
1181cee4d264SManish Chopra 	int rc;
1182cee4d264SManish Chopra 
1183cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1184cee4d264SManish Chopra 			  &vport_to_remove_from);
1185cee4d264SManish Chopra 	if (rc)
1186cee4d264SManish Chopra 		return rc;
1187cee4d264SManish Chopra 
1188cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1189cee4d264SManish Chopra 			  &vport_to_add_to);
1190cee4d264SManish Chopra 	if (rc)
1191cee4d264SManish Chopra 		return rc;
1192cee4d264SManish Chopra 
119306f56b81SYuval Mintz 	/* Get SPQ entry */
119406f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
119506f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
119606f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
119706f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
119806f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1199cee4d264SManish Chopra 
1200cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, pp_ent,
1201cee4d264SManish Chopra 				 ETH_RAMROD_FILTERS_UPDATE,
120206f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1203cee4d264SManish Chopra 	if (rc)
1204cee4d264SManish Chopra 		return rc;
1205cee4d264SManish Chopra 
1206cee4d264SManish Chopra 	*pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1207cee4d264SManish Chopra 	p_ramrod = *pp_ramrod;
1208cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1209cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1210cee4d264SManish Chopra 
1211cee4d264SManish Chopra 	switch (p_filter_cmd->opcode) {
1212fc48b7a6SYuval Mintz 	case QED_FILTER_REPLACE:
1213cee4d264SManish Chopra 	case QED_FILTER_MOVE:
1214cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1215cee4d264SManish Chopra 	default:
1216cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1217cee4d264SManish Chopra 	}
1218cee4d264SManish Chopra 
1219cee4d264SManish Chopra 	p_first_filter	= &p_ramrod->filter_cmds[0];
1220cee4d264SManish Chopra 	p_second_filter = &p_ramrod->filter_cmds[1];
1221cee4d264SManish Chopra 
1222cee4d264SManish Chopra 	switch (p_filter_cmd->type) {
1223cee4d264SManish Chopra 	case QED_FILTER_MAC:
1224cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1225cee4d264SManish Chopra 	case QED_FILTER_VLAN:
1226cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1227cee4d264SManish Chopra 	case QED_FILTER_MAC_VLAN:
1228cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1229cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC:
1230cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1231cee4d264SManish Chopra 	case QED_FILTER_INNER_VLAN:
1232cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1233cee4d264SManish Chopra 	case QED_FILTER_INNER_PAIR:
1234cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1235cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC_VNI_PAIR:
1236cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1237cee4d264SManish Chopra 		break;
1238cee4d264SManish Chopra 	case QED_FILTER_MAC_VNI_PAIR:
1239cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1240cee4d264SManish Chopra 	case QED_FILTER_VNI:
1241cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1242cee4d264SManish Chopra 	}
1243cee4d264SManish Chopra 
1244cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1245cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1246cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1247cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1248cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1249cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1250cee4d264SManish Chopra 		qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1251cee4d264SManish Chopra 				    &p_first_filter->mac_mid,
1252cee4d264SManish Chopra 				    &p_first_filter->mac_lsb,
1253cee4d264SManish Chopra 				    (u8 *)p_filter_cmd->mac);
1254cee4d264SManish Chopra 	}
1255cee4d264SManish Chopra 
1256cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1257cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1258cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1259cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1260cee4d264SManish Chopra 		p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1261cee4d264SManish Chopra 
1262cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1263cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1264cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1265cee4d264SManish Chopra 		p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1266cee4d264SManish Chopra 
1267cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1268cee4d264SManish Chopra 		p_second_filter->type = p_first_filter->type;
1269cee4d264SManish Chopra 		p_second_filter->mac_msb = p_first_filter->mac_msb;
1270cee4d264SManish Chopra 		p_second_filter->mac_mid = p_first_filter->mac_mid;
1271cee4d264SManish Chopra 		p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1272cee4d264SManish Chopra 		p_second_filter->vlan_id = p_first_filter->vlan_id;
1273cee4d264SManish Chopra 		p_second_filter->vni = p_first_filter->vni;
1274cee4d264SManish Chopra 
1275cee4d264SManish Chopra 		p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1276cee4d264SManish Chopra 
1277cee4d264SManish Chopra 		p_first_filter->vport_id = vport_to_remove_from;
1278cee4d264SManish Chopra 
1279cee4d264SManish Chopra 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1280cee4d264SManish Chopra 		p_second_filter->vport_id = vport_to_add_to;
1281fc48b7a6SYuval Mintz 	} else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1282fc48b7a6SYuval Mintz 		p_first_filter->vport_id = vport_to_add_to;
1283fc48b7a6SYuval Mintz 		memcpy(p_second_filter, p_first_filter,
1284fc48b7a6SYuval Mintz 		       sizeof(*p_second_filter));
1285fc48b7a6SYuval Mintz 		p_first_filter->action	= ETH_FILTER_ACTION_REMOVE_ALL;
1286fc48b7a6SYuval Mintz 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1287cee4d264SManish Chopra 	} else {
1288cee4d264SManish Chopra 		action = qed_filter_action(p_filter_cmd->opcode);
1289cee4d264SManish Chopra 
1290cee4d264SManish Chopra 		if (action == MAX_ETH_FILTER_ACTION) {
1291cee4d264SManish Chopra 			DP_NOTICE(p_hwfn,
1292cee4d264SManish Chopra 				  "%d is not supported yet\n",
1293cee4d264SManish Chopra 				  p_filter_cmd->opcode);
1294cee4d264SManish Chopra 			return -EINVAL;
1295cee4d264SManish Chopra 		}
1296cee4d264SManish Chopra 
1297cee4d264SManish Chopra 		p_first_filter->action = action;
1298cee4d264SManish Chopra 		p_first_filter->vport_id = (p_filter_cmd->opcode ==
1299cee4d264SManish Chopra 					    QED_FILTER_REMOVE) ?
1300cee4d264SManish Chopra 					   vport_to_remove_from :
1301cee4d264SManish Chopra 					   vport_to_add_to;
1302cee4d264SManish Chopra 	}
1303cee4d264SManish Chopra 
1304cee4d264SManish Chopra 	return 0;
1305cee4d264SManish Chopra }
1306cee4d264SManish Chopra 
1307dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1308cee4d264SManish Chopra 			    u16 opaque_fid,
1309cee4d264SManish Chopra 			    struct qed_filter_ucast *p_filter_cmd,
1310cee4d264SManish Chopra 			    enum spq_mode comp_mode,
1311cee4d264SManish Chopra 			    struct qed_spq_comp_cb *p_comp_data)
1312cee4d264SManish Chopra {
1313cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data	*p_ramrod	= NULL;
1314cee4d264SManish Chopra 	struct qed_spq_entry			*p_ent		= NULL;
1315cee4d264SManish Chopra 	struct eth_filter_cmd_header		*p_header;
1316cee4d264SManish Chopra 	int					rc;
1317cee4d264SManish Chopra 
1318cee4d264SManish Chopra 	rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1319cee4d264SManish Chopra 				     &p_ramrod, &p_ent,
1320cee4d264SManish Chopra 				     comp_mode, p_comp_data);
13211a635e48SYuval Mintz 	if (rc) {
1322cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1323cee4d264SManish Chopra 		return rc;
1324cee4d264SManish Chopra 	}
1325cee4d264SManish Chopra 	p_header = &p_ramrod->filter_cmd_hdr;
1326cee4d264SManish Chopra 	p_header->assert_on_error = p_filter_cmd->assert_on_error;
1327cee4d264SManish Chopra 
1328cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
13291a635e48SYuval Mintz 	if (rc) {
13301a635e48SYuval Mintz 		DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1331cee4d264SManish Chopra 		return rc;
1332cee4d264SManish Chopra 	}
1333cee4d264SManish Chopra 
1334cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1335cee4d264SManish Chopra 		   "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1336cee4d264SManish Chopra 		   (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1337cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1338cee4d264SManish Chopra 		   "REMOVE" :
1339cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1340cee4d264SManish Chopra 		    "MOVE" : "REPLACE")),
1341cee4d264SManish Chopra 		   (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1342cee4d264SManish Chopra 		   ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1343cee4d264SManish Chopra 		    "VLAN" : "MAC & VLAN"),
1344cee4d264SManish Chopra 		   p_ramrod->filter_cmd_hdr.cmd_cnt,
1345cee4d264SManish Chopra 		   p_filter_cmd->is_rx_filter,
1346cee4d264SManish Chopra 		   p_filter_cmd->is_tx_filter);
1347cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1348cee4d264SManish Chopra 		   "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1349cee4d264SManish Chopra 		   p_filter_cmd->vport_to_add_to,
1350cee4d264SManish Chopra 		   p_filter_cmd->vport_to_remove_from,
1351cee4d264SManish Chopra 		   p_filter_cmd->mac[0],
1352cee4d264SManish Chopra 		   p_filter_cmd->mac[1],
1353cee4d264SManish Chopra 		   p_filter_cmd->mac[2],
1354cee4d264SManish Chopra 		   p_filter_cmd->mac[3],
1355cee4d264SManish Chopra 		   p_filter_cmd->mac[4],
1356cee4d264SManish Chopra 		   p_filter_cmd->mac[5],
1357cee4d264SManish Chopra 		   p_filter_cmd->vlan);
1358cee4d264SManish Chopra 
1359cee4d264SManish Chopra 	return 0;
1360cee4d264SManish Chopra }
1361cee4d264SManish Chopra 
1362cee4d264SManish Chopra /*******************************************************************************
1363cee4d264SManish Chopra  * Description:
1364cee4d264SManish Chopra  *         Calculates crc 32 on a buffer
1365cee4d264SManish Chopra  *         Note: crc32_length MUST be aligned to 8
1366cee4d264SManish Chopra  * Return:
1367cee4d264SManish Chopra  ******************************************************************************/
1368cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet,
13691a635e48SYuval Mintz 			   u32 crc32_length, u32 crc32_seed, u8 complement)
1370cee4d264SManish Chopra {
13711a635e48SYuval Mintz 	u32 byte = 0, bit = 0, crc32_result = crc32_seed;
13721a635e48SYuval Mintz 	u8 msb = 0, current_byte = 0;
1373cee4d264SManish Chopra 
1374cee4d264SManish Chopra 	if ((!crc32_packet) ||
1375cee4d264SManish Chopra 	    (crc32_length == 0) ||
1376cee4d264SManish Chopra 	    ((crc32_length % 8) != 0))
1377cee4d264SManish Chopra 		return crc32_result;
1378cee4d264SManish Chopra 	for (byte = 0; byte < crc32_length; byte++) {
1379cee4d264SManish Chopra 		current_byte = crc32_packet[byte];
1380cee4d264SManish Chopra 		for (bit = 0; bit < 8; bit++) {
1381cee4d264SManish Chopra 			msb = (u8)(crc32_result >> 31);
1382cee4d264SManish Chopra 			crc32_result = crc32_result << 1;
1383cee4d264SManish Chopra 			if (msb != (0x1 & (current_byte >> bit))) {
1384cee4d264SManish Chopra 				crc32_result = crc32_result ^ CRC32_POLY;
1385cee4d264SManish Chopra 				crc32_result |= 1; /*crc32_result[0] = 1;*/
1386cee4d264SManish Chopra 			}
1387cee4d264SManish Chopra 		}
1388cee4d264SManish Chopra 	}
1389cee4d264SManish Chopra 	return crc32_result;
1390cee4d264SManish Chopra }
1391cee4d264SManish Chopra 
13921a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
1393cee4d264SManish Chopra {
1394cee4d264SManish Chopra 	u32 packet_buf[2] = { 0 };
1395cee4d264SManish Chopra 
1396cee4d264SManish Chopra 	memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1397cee4d264SManish Chopra 	return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1398cee4d264SManish Chopra }
1399cee4d264SManish Chopra 
1400dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac)
1401cee4d264SManish Chopra {
1402cee4d264SManish Chopra 	u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1403cee4d264SManish Chopra 				mac, ETH_ALEN);
1404cee4d264SManish Chopra 
1405cee4d264SManish Chopra 	return crc & 0xff;
1406cee4d264SManish Chopra }
1407cee4d264SManish Chopra 
1408cee4d264SManish Chopra static int
1409cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1410cee4d264SManish Chopra 			u16 opaque_fid,
1411cee4d264SManish Chopra 			struct qed_filter_mcast *p_filter_cmd,
1412cee4d264SManish Chopra 			enum spq_mode comp_mode,
1413cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1414cee4d264SManish Chopra {
1415cee4d264SManish Chopra 	unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1416cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
1417cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
141806f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1419cee4d264SManish Chopra 	u8 abs_vport_id = 0;
1420cee4d264SManish Chopra 	int rc, i;
1421cee4d264SManish Chopra 
142283aeb933SYuval Mintz 	if (p_filter_cmd->opcode == QED_FILTER_ADD)
1423cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1424cee4d264SManish Chopra 				  &abs_vport_id);
142583aeb933SYuval Mintz 	else
1426cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1427cee4d264SManish Chopra 				  &abs_vport_id);
1428cee4d264SManish Chopra 	if (rc)
1429cee4d264SManish Chopra 		return rc;
1430cee4d264SManish Chopra 
143106f56b81SYuval Mintz 	/* Get SPQ entry */
143206f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
143306f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
143406f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
143506f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
143606f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1437cee4d264SManish Chopra 
1438cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1439cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
144006f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1441cee4d264SManish Chopra 	if (rc) {
1442cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1443cee4d264SManish Chopra 		return rc;
1444cee4d264SManish Chopra 	}
1445cee4d264SManish Chopra 
1446cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
1447cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
1448cee4d264SManish Chopra 
1449cee4d264SManish Chopra 	/* explicitly clear out the entire vector */
1450cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
1451cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
1452cee4d264SManish Chopra 	memset(bins, 0, sizeof(unsigned long) *
1453cee4d264SManish Chopra 	       ETH_MULTICAST_MAC_BINS_IN_REGS);
1454cee4d264SManish Chopra 	/* filter ADD op is explicit set op and it removes
1455cee4d264SManish Chopra 	 *  any existing filters for the vport
1456cee4d264SManish Chopra 	 */
1457cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1458cee4d264SManish Chopra 		for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1459cee4d264SManish Chopra 			u32 bit;
1460cee4d264SManish Chopra 
1461cee4d264SManish Chopra 			bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1462cee4d264SManish Chopra 			__set_bit(bit, bins);
1463cee4d264SManish Chopra 		}
1464cee4d264SManish Chopra 
1465cee4d264SManish Chopra 		/* Convert to correct endianity */
1466cee4d264SManish Chopra 		for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
14671a635e48SYuval Mintz 			struct vport_update_ramrod_mcast *p_ramrod_bins;
1468cee4d264SManish Chopra 			u32 *p_bins = (u32 *)bins;
1469cee4d264SManish Chopra 
14701a635e48SYuval Mintz 			p_ramrod_bins = &p_ramrod->approx_mcast;
14711a635e48SYuval Mintz 			p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
1472cee4d264SManish Chopra 		}
1473cee4d264SManish Chopra 	}
1474cee4d264SManish Chopra 
1475cee4d264SManish Chopra 	p_ramrod->common.vport_id = abs_vport_id;
1476cee4d264SManish Chopra 
1477cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1478cee4d264SManish Chopra }
1479cee4d264SManish Chopra 
1480dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1481cee4d264SManish Chopra 				struct qed_filter_mcast *p_filter_cmd,
1482cee4d264SManish Chopra 				enum spq_mode comp_mode,
1483cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1484cee4d264SManish Chopra {
1485cee4d264SManish Chopra 	int rc = 0;
1486cee4d264SManish Chopra 	int i;
1487cee4d264SManish Chopra 
1488cee4d264SManish Chopra 	/* only ADD and REMOVE operations are supported for multi-cast */
1489cee4d264SManish Chopra 	if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1490cee4d264SManish Chopra 	     (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1491cee4d264SManish Chopra 	    (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1492cee4d264SManish Chopra 		return -EINVAL;
1493cee4d264SManish Chopra 
1494cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1495cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1496cee4d264SManish Chopra 
1497cee4d264SManish Chopra 		u16 opaque_fid;
1498cee4d264SManish Chopra 
1499dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1500dacd88d6SYuval Mintz 			qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1501dacd88d6SYuval Mintz 			continue;
1502dacd88d6SYuval Mintz 		}
1503cee4d264SManish Chopra 
1504cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1505cee4d264SManish Chopra 
1506cee4d264SManish Chopra 		rc = qed_sp_eth_filter_mcast(p_hwfn,
1507cee4d264SManish Chopra 					     opaque_fid,
1508cee4d264SManish Chopra 					     p_filter_cmd,
15091a635e48SYuval Mintz 					     comp_mode, p_comp_data);
1510cee4d264SManish Chopra 	}
1511cee4d264SManish Chopra 	return rc;
1512cee4d264SManish Chopra }
1513cee4d264SManish Chopra 
1514cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1515cee4d264SManish Chopra 				struct qed_filter_ucast *p_filter_cmd,
1516cee4d264SManish Chopra 				enum spq_mode comp_mode,
1517cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1518cee4d264SManish Chopra {
1519cee4d264SManish Chopra 	int rc = 0;
1520cee4d264SManish Chopra 	int i;
1521cee4d264SManish Chopra 
1522cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1523cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1524cee4d264SManish Chopra 		u16 opaque_fid;
1525cee4d264SManish Chopra 
1526dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1527dacd88d6SYuval Mintz 			rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1528dacd88d6SYuval Mintz 			continue;
1529dacd88d6SYuval Mintz 		}
1530cee4d264SManish Chopra 
1531cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1532cee4d264SManish Chopra 
1533cee4d264SManish Chopra 		rc = qed_sp_eth_filter_ucast(p_hwfn,
1534cee4d264SManish Chopra 					     opaque_fid,
1535cee4d264SManish Chopra 					     p_filter_cmd,
15361a635e48SYuval Mintz 					     comp_mode, p_comp_data);
15371a635e48SYuval Mintz 		if (rc)
1538dacd88d6SYuval Mintz 			break;
1539cee4d264SManish Chopra 	}
1540cee4d264SManish Chopra 
1541cee4d264SManish Chopra 	return rc;
1542cee4d264SManish Chopra }
1543cee4d264SManish Chopra 
154486622ee7SYuval Mintz /* Statistics related code */
154586622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
154686622ee7SYuval Mintz 					   u32 *p_addr,
1547dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
154886622ee7SYuval Mintz {
1549dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
155086622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_PSDM_RAM +
155186622ee7SYuval Mintz 		    PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
155286622ee7SYuval Mintz 		*p_len = sizeof(struct eth_pstorm_per_queue_stat);
1553dacd88d6SYuval Mintz 	} else {
1554dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1555dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1556dacd88d6SYuval Mintz 
1557dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1558dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.pstats.len;
1559dacd88d6SYuval Mintz 	}
156086622ee7SYuval Mintz }
156186622ee7SYuval Mintz 
156286622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
156386622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
156486622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
156586622ee7SYuval Mintz 				   u16 statistics_bin)
156686622ee7SYuval Mintz {
156786622ee7SYuval Mintz 	struct eth_pstorm_per_queue_stat pstats;
156886622ee7SYuval Mintz 	u32 pstats_addr = 0, pstats_len = 0;
156986622ee7SYuval Mintz 
157086622ee7SYuval Mintz 	__qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
157186622ee7SYuval Mintz 				       statistics_bin);
157286622ee7SYuval Mintz 
157386622ee7SYuval Mintz 	memset(&pstats, 0, sizeof(pstats));
1574dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
157586622ee7SYuval Mintz 
15769c79ddaaSMintz, Yuval 	p_stats->common.tx_ucast_bytes +=
15779c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_ucast_bytes);
15789c79ddaaSMintz, Yuval 	p_stats->common.tx_mcast_bytes +=
15799c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_mcast_bytes);
15809c79ddaaSMintz, Yuval 	p_stats->common.tx_bcast_bytes +=
15819c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_bcast_bytes);
15829c79ddaaSMintz, Yuval 	p_stats->common.tx_ucast_pkts +=
15839c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_ucast_pkts);
15849c79ddaaSMintz, Yuval 	p_stats->common.tx_mcast_pkts +=
15859c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_mcast_pkts);
15869c79ddaaSMintz, Yuval 	p_stats->common.tx_bcast_pkts +=
15879c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_bcast_pkts);
15889c79ddaaSMintz, Yuval 	p_stats->common.tx_err_drop_pkts +=
15899c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.error_drop_pkts);
159086622ee7SYuval Mintz }
159186622ee7SYuval Mintz 
159286622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
159386622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
159486622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
159586622ee7SYuval Mintz 				   u16 statistics_bin)
159686622ee7SYuval Mintz {
159786622ee7SYuval Mintz 	struct tstorm_per_port_stat tstats;
1598dacd88d6SYuval Mintz 	u32 tstats_addr, tstats_len;
159986622ee7SYuval Mintz 
1600dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
1601dacd88d6SYuval Mintz 		tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1602dacd88d6SYuval Mintz 		    TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1603dacd88d6SYuval Mintz 		tstats_len = sizeof(struct tstorm_per_port_stat);
1604dacd88d6SYuval Mintz 	} else {
1605dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1606dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1607dacd88d6SYuval Mintz 
1608dacd88d6SYuval Mintz 		tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1609dacd88d6SYuval Mintz 		tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1610dacd88d6SYuval Mintz 	}
161186622ee7SYuval Mintz 
161286622ee7SYuval Mintz 	memset(&tstats, 0, sizeof(tstats));
1613dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
161486622ee7SYuval Mintz 
16159c79ddaaSMintz, Yuval 	p_stats->common.mftag_filter_discards +=
161686622ee7SYuval Mintz 	    HILO_64_REGPAIR(tstats.mftag_filter_discard);
16179c79ddaaSMintz, Yuval 	p_stats->common.mac_filter_discards +=
161886622ee7SYuval Mintz 	    HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
161986622ee7SYuval Mintz }
162086622ee7SYuval Mintz 
162186622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
162286622ee7SYuval Mintz 					   u32 *p_addr,
1623dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
162486622ee7SYuval Mintz {
1625dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
162686622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_USDM_RAM +
162786622ee7SYuval Mintz 		    USTORM_QUEUE_STAT_OFFSET(statistics_bin);
162886622ee7SYuval Mintz 		*p_len = sizeof(struct eth_ustorm_per_queue_stat);
1629dacd88d6SYuval Mintz 	} else {
1630dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1631dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1632dacd88d6SYuval Mintz 
1633dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1634dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.ustats.len;
1635dacd88d6SYuval Mintz 	}
163686622ee7SYuval Mintz }
163786622ee7SYuval Mintz 
163886622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
163986622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
164086622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
164186622ee7SYuval Mintz 				   u16 statistics_bin)
164286622ee7SYuval Mintz {
164386622ee7SYuval Mintz 	struct eth_ustorm_per_queue_stat ustats;
164486622ee7SYuval Mintz 	u32 ustats_addr = 0, ustats_len = 0;
164586622ee7SYuval Mintz 
164686622ee7SYuval Mintz 	__qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
164786622ee7SYuval Mintz 				       statistics_bin);
164886622ee7SYuval Mintz 
164986622ee7SYuval Mintz 	memset(&ustats, 0, sizeof(ustats));
1650dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
165186622ee7SYuval Mintz 
16529c79ddaaSMintz, Yuval 	p_stats->common.rx_ucast_bytes +=
16539c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
16549c79ddaaSMintz, Yuval 	p_stats->common.rx_mcast_bytes +=
16559c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
16569c79ddaaSMintz, Yuval 	p_stats->common.rx_bcast_bytes +=
16579c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
16589c79ddaaSMintz, Yuval 	p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
16599c79ddaaSMintz, Yuval 	p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
16609c79ddaaSMintz, Yuval 	p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
166186622ee7SYuval Mintz }
166286622ee7SYuval Mintz 
166386622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
166486622ee7SYuval Mintz 					   u32 *p_addr,
1665dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
166686622ee7SYuval Mintz {
1667dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
166886622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_MSDM_RAM +
166986622ee7SYuval Mintz 		    MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
167086622ee7SYuval Mintz 		*p_len = sizeof(struct eth_mstorm_per_queue_stat);
1671dacd88d6SYuval Mintz 	} else {
1672dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1673dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1674dacd88d6SYuval Mintz 
1675dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1676dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.mstats.len;
1677dacd88d6SYuval Mintz 	}
167886622ee7SYuval Mintz }
167986622ee7SYuval Mintz 
168086622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
168186622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
168286622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
168386622ee7SYuval Mintz 				   u16 statistics_bin)
168486622ee7SYuval Mintz {
168586622ee7SYuval Mintz 	struct eth_mstorm_per_queue_stat mstats;
168686622ee7SYuval Mintz 	u32 mstats_addr = 0, mstats_len = 0;
168786622ee7SYuval Mintz 
168886622ee7SYuval Mintz 	__qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
168986622ee7SYuval Mintz 				       statistics_bin);
169086622ee7SYuval Mintz 
169186622ee7SYuval Mintz 	memset(&mstats, 0, sizeof(mstats));
1692dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
169386622ee7SYuval Mintz 
16949c79ddaaSMintz, Yuval 	p_stats->common.no_buff_discards +=
16959c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(mstats.no_buff_discard);
16969c79ddaaSMintz, Yuval 	p_stats->common.packet_too_big_discard +=
169786622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.packet_too_big_discard);
16989c79ddaaSMintz, Yuval 	p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
16999c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_pkts +=
170086622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
17019c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_events +=
170286622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_events);
17039c79ddaaSMintz, Yuval 	p_stats->common.tpa_aborts_num +=
17049c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(mstats.tpa_aborts_num);
17059c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_bytes +=
170686622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
170786622ee7SYuval Mintz }
170886622ee7SYuval Mintz 
170986622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
171086622ee7SYuval Mintz 				       struct qed_ptt *p_ptt,
171186622ee7SYuval Mintz 				       struct qed_eth_stats *p_stats)
171286622ee7SYuval Mintz {
17139c79ddaaSMintz, Yuval 	struct qed_eth_stats_common *p_common = &p_stats->common;
171486622ee7SYuval Mintz 	struct port_stats port_stats;
171586622ee7SYuval Mintz 	int j;
171686622ee7SYuval Mintz 
171786622ee7SYuval Mintz 	memset(&port_stats, 0, sizeof(port_stats));
171886622ee7SYuval Mintz 
171986622ee7SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
172086622ee7SYuval Mintz 			p_hwfn->mcp_info->port_addr +
172186622ee7SYuval Mintz 			offsetof(struct public_port, stats),
172286622ee7SYuval Mintz 			sizeof(port_stats));
172386622ee7SYuval Mintz 
17249c79ddaaSMintz, Yuval 	p_common->rx_64_byte_packets += port_stats.eth.r64;
17259c79ddaaSMintz, Yuval 	p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
17269c79ddaaSMintz, Yuval 	p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
17279c79ddaaSMintz, Yuval 	p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
17289c79ddaaSMintz, Yuval 	p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
17299c79ddaaSMintz, Yuval 	p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
17309c79ddaaSMintz, Yuval 	p_common->rx_crc_errors += port_stats.eth.rfcs;
17319c79ddaaSMintz, Yuval 	p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
17329c79ddaaSMintz, Yuval 	p_common->rx_pause_frames += port_stats.eth.rxpf;
17339c79ddaaSMintz, Yuval 	p_common->rx_pfc_frames += port_stats.eth.rxpp;
17349c79ddaaSMintz, Yuval 	p_common->rx_align_errors += port_stats.eth.raln;
17359c79ddaaSMintz, Yuval 	p_common->rx_carrier_errors += port_stats.eth.rfcr;
17369c79ddaaSMintz, Yuval 	p_common->rx_oversize_packets += port_stats.eth.rovr;
17379c79ddaaSMintz, Yuval 	p_common->rx_jabbers += port_stats.eth.rjbr;
17389c79ddaaSMintz, Yuval 	p_common->rx_undersize_packets += port_stats.eth.rund;
17399c79ddaaSMintz, Yuval 	p_common->rx_fragments += port_stats.eth.rfrg;
17409c79ddaaSMintz, Yuval 	p_common->tx_64_byte_packets += port_stats.eth.t64;
17419c79ddaaSMintz, Yuval 	p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
17429c79ddaaSMintz, Yuval 	p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
17439c79ddaaSMintz, Yuval 	p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
17449c79ddaaSMintz, Yuval 	p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
17459c79ddaaSMintz, Yuval 	p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
17469c79ddaaSMintz, Yuval 	p_common->tx_pause_frames += port_stats.eth.txpf;
17479c79ddaaSMintz, Yuval 	p_common->tx_pfc_frames += port_stats.eth.txpp;
17489c79ddaaSMintz, Yuval 	p_common->rx_mac_bytes += port_stats.eth.rbyte;
17499c79ddaaSMintz, Yuval 	p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
17509c79ddaaSMintz, Yuval 	p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
17519c79ddaaSMintz, Yuval 	p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
17529c79ddaaSMintz, Yuval 	p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
17539c79ddaaSMintz, Yuval 	p_common->tx_mac_bytes += port_stats.eth.tbyte;
17549c79ddaaSMintz, Yuval 	p_common->tx_mac_uc_packets += port_stats.eth.txuca;
17559c79ddaaSMintz, Yuval 	p_common->tx_mac_mc_packets += port_stats.eth.txmca;
17569c79ddaaSMintz, Yuval 	p_common->tx_mac_bc_packets += port_stats.eth.txbca;
17579c79ddaaSMintz, Yuval 	p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
175886622ee7SYuval Mintz 	for (j = 0; j < 8; j++) {
17599c79ddaaSMintz, Yuval 		p_common->brb_truncates += port_stats.brb.brb_truncate[j];
17609c79ddaaSMintz, Yuval 		p_common->brb_discards += port_stats.brb.brb_discard[j];
17619c79ddaaSMintz, Yuval 	}
17629c79ddaaSMintz, Yuval 
17639c79ddaaSMintz, Yuval 	if (QED_IS_BB(p_hwfn->cdev)) {
17649c79ddaaSMintz, Yuval 		struct qed_eth_stats_bb *p_bb = &p_stats->bb;
17659c79ddaaSMintz, Yuval 
17669c79ddaaSMintz, Yuval 		p_bb->rx_1519_to_1522_byte_packets +=
17679c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r1522;
17689c79ddaaSMintz, Yuval 		p_bb->rx_1519_to_2047_byte_packets +=
17699c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r2047;
17709c79ddaaSMintz, Yuval 		p_bb->rx_2048_to_4095_byte_packets +=
17719c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r4095;
17729c79ddaaSMintz, Yuval 		p_bb->rx_4096_to_9216_byte_packets +=
17739c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r9216;
17749c79ddaaSMintz, Yuval 		p_bb->rx_9217_to_16383_byte_packets +=
17759c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r16383;
17769c79ddaaSMintz, Yuval 		p_bb->tx_1519_to_2047_byte_packets +=
17779c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t2047;
17789c79ddaaSMintz, Yuval 		p_bb->tx_2048_to_4095_byte_packets +=
17799c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t4095;
17809c79ddaaSMintz, Yuval 		p_bb->tx_4096_to_9216_byte_packets +=
17819c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t9216;
17829c79ddaaSMintz, Yuval 		p_bb->tx_9217_to_16383_byte_packets +=
17839c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t16383;
17849c79ddaaSMintz, Yuval 		p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
17859c79ddaaSMintz, Yuval 		p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
17869c79ddaaSMintz, Yuval 	} else {
17879c79ddaaSMintz, Yuval 		struct qed_eth_stats_ah *p_ah = &p_stats->ah;
17889c79ddaaSMintz, Yuval 
17899c79ddaaSMintz, Yuval 		p_ah->rx_1519_to_max_byte_packets +=
17909c79ddaaSMintz, Yuval 		    port_stats.eth.u0.ah0.r1519_to_max;
17919c79ddaaSMintz, Yuval 		p_ah->tx_1519_to_max_byte_packets =
17929c79ddaaSMintz, Yuval 		    port_stats.eth.u1.ah1.t1519_to_max;
179386622ee7SYuval Mintz 	}
179486622ee7SYuval Mintz }
179586622ee7SYuval Mintz 
179686622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
179786622ee7SYuval Mintz 				  struct qed_ptt *p_ptt,
179886622ee7SYuval Mintz 				  struct qed_eth_stats *stats,
1799dacd88d6SYuval Mintz 				  u16 statistics_bin, bool b_get_port_stats)
180086622ee7SYuval Mintz {
180186622ee7SYuval Mintz 	__qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
180286622ee7SYuval Mintz 	__qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
180386622ee7SYuval Mintz 	__qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
180486622ee7SYuval Mintz 	__qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
180586622ee7SYuval Mintz 
1806dacd88d6SYuval Mintz 	if (b_get_port_stats && p_hwfn->mcp_info)
180786622ee7SYuval Mintz 		__qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
180886622ee7SYuval Mintz }
180986622ee7SYuval Mintz 
181086622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev,
181186622ee7SYuval Mintz 				 struct qed_eth_stats *stats)
181286622ee7SYuval Mintz {
181386622ee7SYuval Mintz 	u8 fw_vport = 0;
181486622ee7SYuval Mintz 	int i;
181586622ee7SYuval Mintz 
181686622ee7SYuval Mintz 	memset(stats, 0, sizeof(*stats));
181786622ee7SYuval Mintz 
181886622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
181986622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1820dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1821dacd88d6SYuval Mintz 						    :  NULL;
182286622ee7SYuval Mintz 
1823dacd88d6SYuval Mintz 		if (IS_PF(cdev)) {
182486622ee7SYuval Mintz 			/* The main vport index is relative first */
182586622ee7SYuval Mintz 			if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
182686622ee7SYuval Mintz 				DP_ERR(p_hwfn, "No vport available!\n");
1827dacd88d6SYuval Mintz 				goto out;
1828dacd88d6SYuval Mintz 			}
182986622ee7SYuval Mintz 		}
183086622ee7SYuval Mintz 
1831dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
183286622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
183386622ee7SYuval Mintz 			continue;
183486622ee7SYuval Mintz 		}
183586622ee7SYuval Mintz 
1836dacd88d6SYuval Mintz 		__qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1837dacd88d6SYuval Mintz 				      IS_PF(cdev) ? true : false);
183886622ee7SYuval Mintz 
1839dacd88d6SYuval Mintz out:
1840dacd88d6SYuval Mintz 		if (IS_PF(cdev) && p_ptt)
184186622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
184286622ee7SYuval Mintz 	}
184386622ee7SYuval Mintz }
184486622ee7SYuval Mintz 
18451a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
184686622ee7SYuval Mintz {
184786622ee7SYuval Mintz 	u32 i;
184886622ee7SYuval Mintz 
184986622ee7SYuval Mintz 	if (!cdev) {
185086622ee7SYuval Mintz 		memset(stats, 0, sizeof(*stats));
185186622ee7SYuval Mintz 		return;
185286622ee7SYuval Mintz 	}
185386622ee7SYuval Mintz 
185486622ee7SYuval Mintz 	_qed_get_vport_stats(cdev, stats);
185586622ee7SYuval Mintz 
185686622ee7SYuval Mintz 	if (!cdev->reset_stats)
185786622ee7SYuval Mintz 		return;
185886622ee7SYuval Mintz 
185986622ee7SYuval Mintz 	/* Reduce the statistics baseline */
186086622ee7SYuval Mintz 	for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
186186622ee7SYuval Mintz 		((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
186286622ee7SYuval Mintz }
186386622ee7SYuval Mintz 
186486622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
186586622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev)
186686622ee7SYuval Mintz {
186786622ee7SYuval Mintz 	int i;
186886622ee7SYuval Mintz 
186986622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
187086622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
187186622ee7SYuval Mintz 		struct eth_mstorm_per_queue_stat mstats;
187286622ee7SYuval Mintz 		struct eth_ustorm_per_queue_stat ustats;
187386622ee7SYuval Mintz 		struct eth_pstorm_per_queue_stat pstats;
1874dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1875dacd88d6SYuval Mintz 						    : NULL;
187686622ee7SYuval Mintz 		u32 addr = 0, len = 0;
187786622ee7SYuval Mintz 
1878dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
187986622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
188086622ee7SYuval Mintz 			continue;
188186622ee7SYuval Mintz 		}
188286622ee7SYuval Mintz 
188386622ee7SYuval Mintz 		memset(&mstats, 0, sizeof(mstats));
188486622ee7SYuval Mintz 		__qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
188586622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
188686622ee7SYuval Mintz 
188786622ee7SYuval Mintz 		memset(&ustats, 0, sizeof(ustats));
188886622ee7SYuval Mintz 		__qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
188986622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
189086622ee7SYuval Mintz 
189186622ee7SYuval Mintz 		memset(&pstats, 0, sizeof(pstats));
189286622ee7SYuval Mintz 		__qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
189386622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
189486622ee7SYuval Mintz 
1895dacd88d6SYuval Mintz 		if (IS_PF(cdev))
189686622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
189786622ee7SYuval Mintz 	}
189886622ee7SYuval Mintz 
189986622ee7SYuval Mintz 	/* PORT statistics are not necessarily reset, so we need to
190086622ee7SYuval Mintz 	 * read and create a baseline for future statistics.
190186622ee7SYuval Mintz 	 */
190286622ee7SYuval Mintz 	if (!cdev->reset_stats)
190386622ee7SYuval Mintz 		DP_INFO(cdev, "Reset stats not allocated\n");
190486622ee7SYuval Mintz 	else
190586622ee7SYuval Mintz 		_qed_get_vport_stats(cdev, cdev->reset_stats);
190686622ee7SYuval Mintz }
190786622ee7SYuval Mintz 
1908d51e4af5SChopra, Manish static void
1909d51e4af5SChopra, Manish qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1910d51e4af5SChopra, Manish 			struct qed_arfs_config_params *p_cfg_params)
1911d51e4af5SChopra, Manish {
1912d51e4af5SChopra, Manish 	if (p_cfg_params->arfs_enable) {
1913d51e4af5SChopra, Manish 		qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1914d51e4af5SChopra, Manish 					p_cfg_params->tcp, p_cfg_params->udp,
1915d51e4af5SChopra, Manish 					p_cfg_params->ipv4, p_cfg_params->ipv6);
1916d51e4af5SChopra, Manish 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
1917d51e4af5SChopra, Manish 			   "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
1918d51e4af5SChopra, Manish 			   p_cfg_params->tcp ? "Enable" : "Disable",
1919d51e4af5SChopra, Manish 			   p_cfg_params->udp ? "Enable" : "Disable",
1920d51e4af5SChopra, Manish 			   p_cfg_params->ipv4 ? "Enable" : "Disable",
1921d51e4af5SChopra, Manish 			   p_cfg_params->ipv6 ? "Enable" : "Disable");
1922d51e4af5SChopra, Manish 	} else {
1923d51e4af5SChopra, Manish 		qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1924d51e4af5SChopra, Manish 	}
1925d51e4af5SChopra, Manish 
1926d51e4af5SChopra, Manish 	DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
1927d51e4af5SChopra, Manish 		   p_cfg_params->arfs_enable ? "Enable" : "Disable");
1928d51e4af5SChopra, Manish }
1929d51e4af5SChopra, Manish 
1930d51e4af5SChopra, Manish static int
1931d51e4af5SChopra, Manish qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1932d51e4af5SChopra, Manish 				struct qed_spq_comp_cb *p_cb,
1933d51e4af5SChopra, Manish 				dma_addr_t p_addr, u16 length, u16 qid,
1934d51e4af5SChopra, Manish 				u8 vport_id, bool b_is_add)
1935d51e4af5SChopra, Manish {
1936d51e4af5SChopra, Manish 	struct rx_update_gft_filter_data *p_ramrod = NULL;
1937d51e4af5SChopra, Manish 	struct qed_spq_entry *p_ent = NULL;
1938d51e4af5SChopra, Manish 	struct qed_sp_init_data init_data;
1939d51e4af5SChopra, Manish 	u16 abs_rx_q_id = 0;
1940d51e4af5SChopra, Manish 	u8 abs_vport_id = 0;
1941d51e4af5SChopra, Manish 	int rc = -EINVAL;
1942d51e4af5SChopra, Manish 
1943d51e4af5SChopra, Manish 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
1944d51e4af5SChopra, Manish 	if (rc)
1945d51e4af5SChopra, Manish 		return rc;
1946d51e4af5SChopra, Manish 
1947d51e4af5SChopra, Manish 	rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
1948d51e4af5SChopra, Manish 	if (rc)
1949d51e4af5SChopra, Manish 		return rc;
1950d51e4af5SChopra, Manish 
1951d51e4af5SChopra, Manish 	/* Get SPQ entry */
1952d51e4af5SChopra, Manish 	memset(&init_data, 0, sizeof(init_data));
1953d51e4af5SChopra, Manish 	init_data.cid = qed_spq_get_cid(p_hwfn);
1954d51e4af5SChopra, Manish 
1955d51e4af5SChopra, Manish 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1956d51e4af5SChopra, Manish 
1957d51e4af5SChopra, Manish 	if (p_cb) {
1958d51e4af5SChopra, Manish 		init_data.comp_mode = QED_SPQ_MODE_CB;
1959d51e4af5SChopra, Manish 		init_data.p_comp_data = p_cb;
1960d51e4af5SChopra, Manish 	} else {
1961d51e4af5SChopra, Manish 		init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1962d51e4af5SChopra, Manish 	}
1963d51e4af5SChopra, Manish 
1964d51e4af5SChopra, Manish 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1965d51e4af5SChopra, Manish 				 ETH_RAMROD_GFT_UPDATE_FILTER,
1966d51e4af5SChopra, Manish 				 PROTOCOLID_ETH, &init_data);
1967d51e4af5SChopra, Manish 	if (rc)
1968d51e4af5SChopra, Manish 		return rc;
1969d51e4af5SChopra, Manish 
1970d51e4af5SChopra, Manish 	p_ramrod = &p_ent->ramrod.rx_update_gft;
1971d51e4af5SChopra, Manish 	DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
1972d51e4af5SChopra, Manish 	p_ramrod->pkt_hdr_length = cpu_to_le16(length);
1973d51e4af5SChopra, Manish 	p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
1974d51e4af5SChopra, Manish 	p_ramrod->vport_id = abs_vport_id;
1975d51e4af5SChopra, Manish 	p_ramrod->filter_type = RFS_FILTER_TYPE;
1976d51e4af5SChopra, Manish 	p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
1977d51e4af5SChopra, Manish 
1978d51e4af5SChopra, Manish 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1979d51e4af5SChopra, Manish 		   "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
1980d51e4af5SChopra, Manish 		   abs_vport_id, abs_rx_q_id,
1981d51e4af5SChopra, Manish 		   b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
1982d51e4af5SChopra, Manish 
1983d51e4af5SChopra, Manish 	return qed_spq_post(p_hwfn, p_ent, NULL);
1984d51e4af5SChopra, Manish }
1985d51e4af5SChopra, Manish 
198625c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev,
198725c089d7SYuval Mintz 				 struct qed_dev_eth_info *info)
198825c089d7SYuval Mintz {
198925c089d7SYuval Mintz 	int i;
199025c089d7SYuval Mintz 
199125c089d7SYuval Mintz 	memset(info, 0, sizeof(*info));
199225c089d7SYuval Mintz 
199325c089d7SYuval Mintz 	info->num_tc = 1;
199425c089d7SYuval Mintz 
19951408cc1fSYuval Mintz 	if (IS_PF(cdev)) {
199625eb8d46SYuval Mintz 		int max_vf_vlan_filters = 0;
19977b7e70f9SYuval Mintz 		int max_vf_mac_filters = 0;
199825eb8d46SYuval Mintz 
199925c089d7SYuval Mintz 		if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
2000e1d32acbSMintz, Yuval 			u16 num_queues = 0;
2001e1d32acbSMintz, Yuval 
2002e1d32acbSMintz, Yuval 			/* Since the feature controls only queue-zones,
2003e1d32acbSMintz, Yuval 			 * make sure we have the contexts [rx, tx, xdp] to
2004e1d32acbSMintz, Yuval 			 * match.
2005e1d32acbSMintz, Yuval 			 */
2006e1d32acbSMintz, Yuval 			for_each_hwfn(cdev, i) {
2007e1d32acbSMintz, Yuval 				struct qed_hwfn *hwfn = &cdev->hwfns[i];
2008e1d32acbSMintz, Yuval 				u16 l2_queues = (u16)FEAT_NUM(hwfn,
2009e1d32acbSMintz, Yuval 							      QED_PF_L2_QUE);
2010e1d32acbSMintz, Yuval 				u16 cids;
2011e1d32acbSMintz, Yuval 
2012e1d32acbSMintz, Yuval 				cids = hwfn->pf_params.eth_pf_params.num_cons;
2013e1d32acbSMintz, Yuval 				num_queues += min_t(u16, l2_queues, cids / 3);
2014e1d32acbSMintz, Yuval 			}
2015e1d32acbSMintz, Yuval 
2016e1d32acbSMintz, Yuval 			/* queues might theoretically be >256, but interrupts'
2017e1d32acbSMintz, Yuval 			 * upper-limit guarantes that it would fit in a u8.
2018e1d32acbSMintz, Yuval 			 */
2019e1d32acbSMintz, Yuval 			if (cdev->int_params.fp_msix_cnt) {
2020e1d32acbSMintz, Yuval 				u8 irqs = cdev->int_params.fp_msix_cnt;
2021e1d32acbSMintz, Yuval 
2022e1d32acbSMintz, Yuval 				info->num_queues = (u8)min_t(u16,
2023e1d32acbSMintz, Yuval 							     num_queues, irqs);
2024e1d32acbSMintz, Yuval 			}
202525c089d7SYuval Mintz 		} else {
202625c089d7SYuval Mintz 			info->num_queues = cdev->num_hwfns;
202725c089d7SYuval Mintz 		}
202825c089d7SYuval Mintz 
20297b7e70f9SYuval Mintz 		if (IS_QED_SRIOV(cdev)) {
203025eb8d46SYuval Mintz 			max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
203125eb8d46SYuval Mintz 					      QED_ETH_VF_NUM_VLAN_FILTERS;
20327b7e70f9SYuval Mintz 			max_vf_mac_filters = cdev->p_iov_info->total_vfs *
20337b7e70f9SYuval Mintz 					     QED_ETH_VF_NUM_MAC_FILTERS;
20347b7e70f9SYuval Mintz 		}
20357b7e70f9SYuval Mintz 		info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
20367b7e70f9SYuval Mintz 						  QED_VLAN) -
203725eb8d46SYuval Mintz 					 max_vf_vlan_filters;
20387b7e70f9SYuval Mintz 		info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
20397b7e70f9SYuval Mintz 						 QED_MAC) -
20407b7e70f9SYuval Mintz 					max_vf_mac_filters;
204125eb8d46SYuval Mintz 
204225c089d7SYuval Mintz 		ether_addr_copy(info->port_mac,
204325c089d7SYuval Mintz 				cdev->hwfns[0].hw_info.hw_mac_addr);
20441408cc1fSYuval Mintz 	} else {
20451408cc1fSYuval Mintz 		qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
20461408cc1fSYuval Mintz 		if (cdev->num_hwfns > 1) {
20471408cc1fSYuval Mintz 			u8 queues = 0;
20481408cc1fSYuval Mintz 
20491408cc1fSYuval Mintz 			qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
20501408cc1fSYuval Mintz 			info->num_queues += queues;
20511408cc1fSYuval Mintz 		}
20521408cc1fSYuval Mintz 
20531408cc1fSYuval Mintz 		qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
20542edbff8dSTomer Tayar 					    (u8 *)&info->num_vlan_filters);
2055b0fca312SMintz, Yuval 		qed_vf_get_num_mac_filters(&cdev->hwfns[0],
2056b0fca312SMintz, Yuval 					   (u8 *)&info->num_mac_filters);
20571408cc1fSYuval Mintz 		qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
2058d8c2c7e3SYuval Mintz 
2059d8c2c7e3SYuval Mintz 		info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
20601408cc1fSYuval Mintz 	}
206125c089d7SYuval Mintz 
206225c089d7SYuval Mintz 	qed_fill_dev_info(cdev, &info->common);
206325c089d7SYuval Mintz 
20641408cc1fSYuval Mintz 	if (IS_VF(cdev))
20650ee28e31SShyam Saini 		eth_zero_addr(info->common.hw_mac);
20661408cc1fSYuval Mintz 
206725c089d7SYuval Mintz 	return 0;
206825c089d7SYuval Mintz }
206925c089d7SYuval Mintz 
2070cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev,
20711408cc1fSYuval Mintz 				 struct qed_eth_cb_ops *ops, void *cookie)
2072cc875c2eSYuval Mintz {
2073cc875c2eSYuval Mintz 	cdev->protocol_ops.eth = ops;
2074cc875c2eSYuval Mintz 	cdev->ops_cookie = cookie;
20751408cc1fSYuval Mintz 
20761408cc1fSYuval Mintz 	/* For VF, we start bulletin reading */
20771408cc1fSYuval Mintz 	if (IS_VF(cdev))
20781408cc1fSYuval Mintz 		qed_vf_start_iov_wq(cdev);
2079cc875c2eSYuval Mintz }
2080cc875c2eSYuval Mintz 
2081eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
2082eff16960SYuval Mintz {
2083eff16960SYuval Mintz 	if (IS_PF(cdev))
2084eff16960SYuval Mintz 		return true;
2085eff16960SYuval Mintz 
2086eff16960SYuval Mintz 	return qed_vf_check_mac(&cdev->hwfns[0], mac);
2087eff16960SYuval Mintz }
2088eff16960SYuval Mintz 
2089cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev,
2090088c8618SManish Chopra 			   struct qed_start_vport_params *params)
2091cee4d264SManish Chopra {
2092cee4d264SManish Chopra 	int rc, i;
2093cee4d264SManish Chopra 
2094cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2095088c8618SManish Chopra 		struct qed_sp_vport_start_params start = { 0 };
2096cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2097cee4d264SManish Chopra 
2098088c8618SManish Chopra 		start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
2099088c8618SManish Chopra 							QED_TPA_MODE_NONE;
2100088c8618SManish Chopra 		start.remove_inner_vlan = params->remove_inner_vlan;
210108feecd7SYuval Mintz 		start.only_untagged = true;	/* untagged only */
2102088c8618SManish Chopra 		start.drop_ttl0 = params->drop_ttl0;
2103088c8618SManish Chopra 		start.opaque_fid = p_hwfn->hw_info.opaque_fid;
2104088c8618SManish Chopra 		start.concrete_fid = p_hwfn->hw_info.concrete_fid;
2105c78c70faSSudarsana Reddy Kalluru 		start.handle_ptp_pkts = params->handle_ptp_pkts;
2106088c8618SManish Chopra 		start.vport_id = params->vport_id;
2107088c8618SManish Chopra 		start.max_buffers_per_cqe = 16;
2108088c8618SManish Chopra 		start.mtu = params->mtu;
2109cee4d264SManish Chopra 
2110088c8618SManish Chopra 		rc = qed_sp_vport_start(p_hwfn, &start);
2111cee4d264SManish Chopra 		if (rc) {
2112cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to start VPORT\n");
2113cee4d264SManish Chopra 			return rc;
2114cee4d264SManish Chopra 		}
2115cee4d264SManish Chopra 
211615582962SRahul Verma 		rc = qed_hw_start_fastpath(p_hwfn);
211715582962SRahul Verma 		if (rc) {
211815582962SRahul Verma 			DP_ERR(cdev, "Failed to start VPORT fastpath\n");
211915582962SRahul Verma 			return rc;
212015582962SRahul Verma 		}
2121cee4d264SManish Chopra 
2122cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2123cee4d264SManish Chopra 			   "Started V-PORT %d with MTU %d\n",
2124088c8618SManish Chopra 			   start.vport_id, start.mtu);
2125cee4d264SManish Chopra 	}
2126cee4d264SManish Chopra 
2127a0d26d5aSYuval Mintz 	if (params->clear_stats)
21289df2ed04SManish Chopra 		qed_reset_vport_stats(cdev);
21299df2ed04SManish Chopra 
2130cee4d264SManish Chopra 	return 0;
2131cee4d264SManish Chopra }
2132cee4d264SManish Chopra 
21331a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
2134cee4d264SManish Chopra {
2135cee4d264SManish Chopra 	int rc, i;
2136cee4d264SManish Chopra 
2137cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2138cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2139cee4d264SManish Chopra 
2140cee4d264SManish Chopra 		rc = qed_sp_vport_stop(p_hwfn,
21411a635e48SYuval Mintz 				       p_hwfn->hw_info.opaque_fid, vport_id);
2142cee4d264SManish Chopra 
2143cee4d264SManish Chopra 		if (rc) {
2144cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to stop VPORT\n");
2145cee4d264SManish Chopra 			return rc;
2146cee4d264SManish Chopra 		}
2147cee4d264SManish Chopra 	}
2148cee4d264SManish Chopra 	return 0;
2149cee4d264SManish Chopra }
2150cee4d264SManish Chopra 
2151f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev,
2152f29ffdb6SMintz, Yuval 				struct qed_update_vport_rss_params *input,
2153f29ffdb6SMintz, Yuval 				struct qed_rss_params *rss)
2154f29ffdb6SMintz, Yuval {
2155f29ffdb6SMintz, Yuval 	int i, fn;
2156f29ffdb6SMintz, Yuval 
2157f29ffdb6SMintz, Yuval 	/* Update configuration with what's correct regardless of CMT */
2158f29ffdb6SMintz, Yuval 	rss->update_rss_config = 1;
2159f29ffdb6SMintz, Yuval 	rss->rss_enable = 1;
2160f29ffdb6SMintz, Yuval 	rss->update_rss_capabilities = 1;
2161f29ffdb6SMintz, Yuval 	rss->update_rss_ind_table = 1;
2162f29ffdb6SMintz, Yuval 	rss->update_rss_key = 1;
2163f29ffdb6SMintz, Yuval 	rss->rss_caps = input->rss_caps;
2164f29ffdb6SMintz, Yuval 	memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
2165f29ffdb6SMintz, Yuval 
2166f29ffdb6SMintz, Yuval 	/* In regular scenario, we'd simply need to take input handlers.
2167f29ffdb6SMintz, Yuval 	 * But in CMT, we'd have to split the handlers according to the
2168f29ffdb6SMintz, Yuval 	 * engine they were configured on. We'd then have to understand
2169f29ffdb6SMintz, Yuval 	 * whether RSS is really required, since 2-queues on CMT doesn't
2170f29ffdb6SMintz, Yuval 	 * require RSS.
2171f29ffdb6SMintz, Yuval 	 */
2172f29ffdb6SMintz, Yuval 	if (cdev->num_hwfns == 1) {
2173f29ffdb6SMintz, Yuval 		memcpy(rss->rss_ind_table,
2174f29ffdb6SMintz, Yuval 		       input->rss_ind_table,
2175f29ffdb6SMintz, Yuval 		       QED_RSS_IND_TABLE_SIZE * sizeof(void *));
2176f29ffdb6SMintz, Yuval 		rss->rss_table_size_log = 7;
2177f29ffdb6SMintz, Yuval 		return 0;
2178f29ffdb6SMintz, Yuval 	}
2179f29ffdb6SMintz, Yuval 
2180f29ffdb6SMintz, Yuval 	/* Start by copying the non-spcific information to the 2nd copy */
2181f29ffdb6SMintz, Yuval 	memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
2182f29ffdb6SMintz, Yuval 
2183f29ffdb6SMintz, Yuval 	/* CMT should be round-robin */
2184f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
2185f29ffdb6SMintz, Yuval 		struct qed_queue_cid *cid = input->rss_ind_table[i];
2186f29ffdb6SMintz, Yuval 		struct qed_rss_params *t_rss;
2187f29ffdb6SMintz, Yuval 
2188f29ffdb6SMintz, Yuval 		if (cid->p_owner == QED_LEADING_HWFN(cdev))
2189f29ffdb6SMintz, Yuval 			t_rss = &rss[0];
2190f29ffdb6SMintz, Yuval 		else
2191f29ffdb6SMintz, Yuval 			t_rss = &rss[1];
2192f29ffdb6SMintz, Yuval 
2193f29ffdb6SMintz, Yuval 		t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
2194f29ffdb6SMintz, Yuval 	}
2195f29ffdb6SMintz, Yuval 
2196f29ffdb6SMintz, Yuval 	/* Make sure RSS is actually required */
2197f29ffdb6SMintz, Yuval 	for_each_hwfn(cdev, fn) {
2198f29ffdb6SMintz, Yuval 		for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
2199f29ffdb6SMintz, Yuval 			if (rss[fn].rss_ind_table[i] !=
2200f29ffdb6SMintz, Yuval 			    rss[fn].rss_ind_table[0])
2201f29ffdb6SMintz, Yuval 				break;
2202f29ffdb6SMintz, Yuval 		}
2203f29ffdb6SMintz, Yuval 		if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
2204f29ffdb6SMintz, Yuval 			DP_VERBOSE(cdev, NETIF_MSG_IFUP,
2205f29ffdb6SMintz, Yuval 				   "CMT - 1 queue per-hwfn; Disabling RSS\n");
2206f29ffdb6SMintz, Yuval 			return -EINVAL;
2207f29ffdb6SMintz, Yuval 		}
2208f29ffdb6SMintz, Yuval 		rss[fn].rss_table_size_log = 6;
2209f29ffdb6SMintz, Yuval 	}
2210f29ffdb6SMintz, Yuval 
2211f29ffdb6SMintz, Yuval 	return 0;
2212f29ffdb6SMintz, Yuval }
2213f29ffdb6SMintz, Yuval 
2214cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev,
2215cee4d264SManish Chopra 			    struct qed_update_vport_params *params)
2216cee4d264SManish Chopra {
2217cee4d264SManish Chopra 	struct qed_sp_vport_update_params sp_params;
2218f29ffdb6SMintz, Yuval 	struct qed_rss_params *rss;
2219f29ffdb6SMintz, Yuval 	int rc = 0, i;
2220cee4d264SManish Chopra 
2221cee4d264SManish Chopra 	if (!cdev)
2222cee4d264SManish Chopra 		return -ENODEV;
2223cee4d264SManish Chopra 
2224f29ffdb6SMintz, Yuval 	rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
2225f29ffdb6SMintz, Yuval 	if (!rss)
2226f29ffdb6SMintz, Yuval 		return -ENOMEM;
2227f29ffdb6SMintz, Yuval 
2228cee4d264SManish Chopra 	memset(&sp_params, 0, sizeof(sp_params));
2229cee4d264SManish Chopra 
2230cee4d264SManish Chopra 	/* Translate protocol params into sp params */
2231cee4d264SManish Chopra 	sp_params.vport_id = params->vport_id;
22321a635e48SYuval Mintz 	sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
22331a635e48SYuval Mintz 	sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
2234cee4d264SManish Chopra 	sp_params.vport_active_rx_flg = params->vport_active_flg;
2235cee4d264SManish Chopra 	sp_params.vport_active_tx_flg = params->vport_active_flg;
2236831bfb0eSYuval Mintz 	sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2237831bfb0eSYuval Mintz 	sp_params.tx_switching_flg = params->tx_switching_flg;
22383f9b4a69SYuval Mintz 	sp_params.accept_any_vlan = params->accept_any_vlan;
22393f9b4a69SYuval Mintz 	sp_params.update_accept_any_vlan_flg =
22403f9b4a69SYuval Mintz 		params->update_accept_any_vlan_flg;
2241cee4d264SManish Chopra 
2242f29ffdb6SMintz, Yuval 	/* Prepare the RSS configuration */
2243f29ffdb6SMintz, Yuval 	if (params->update_rss_flg)
2244f29ffdb6SMintz, Yuval 		if (qed_update_vport_rss(cdev, &params->rss_params, rss))
2245cee4d264SManish Chopra 			params->update_rss_flg = 0;
2246cee4d264SManish Chopra 
2247cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2248cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2249cee4d264SManish Chopra 
2250f29ffdb6SMintz, Yuval 		if (params->update_rss_flg)
2251f29ffdb6SMintz, Yuval 			sp_params.rss_params = &rss[i];
2252f29ffdb6SMintz, Yuval 
2253cee4d264SManish Chopra 		sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2254cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &sp_params,
2255cee4d264SManish Chopra 					 QED_SPQ_MODE_EBLOCK,
2256cee4d264SManish Chopra 					 NULL);
2257cee4d264SManish Chopra 		if (rc) {
2258cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to update VPORT\n");
2259f29ffdb6SMintz, Yuval 			goto out;
2260cee4d264SManish Chopra 		}
2261cee4d264SManish Chopra 
2262cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2263cee4d264SManish Chopra 			   "Updated V-PORT %d: active_flag %d [update %d]\n",
2264cee4d264SManish Chopra 			   params->vport_id, params->vport_active_flg,
2265cee4d264SManish Chopra 			   params->update_vport_active_flg);
2266cee4d264SManish Chopra 	}
2267cee4d264SManish Chopra 
2268f29ffdb6SMintz, Yuval out:
2269f29ffdb6SMintz, Yuval 	vfree(rss);
2270f29ffdb6SMintz, Yuval 	return rc;
2271cee4d264SManish Chopra }
2272cee4d264SManish Chopra 
2273cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev,
22743da7a37aSMintz, Yuval 			 u8 rss_num,
22753da7a37aSMintz, Yuval 			 struct qed_queue_start_common_params *p_params,
2276cee4d264SManish Chopra 			 u16 bd_max_bytes,
2277cee4d264SManish Chopra 			 dma_addr_t bd_chain_phys_addr,
2278cee4d264SManish Chopra 			 dma_addr_t cqe_pbl_addr,
2279cee4d264SManish Chopra 			 u16 cqe_pbl_size,
22803da7a37aSMintz, Yuval 			 struct qed_rxq_start_ret_params *ret_params)
2281cee4d264SManish Chopra {
2282cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
22831a635e48SYuval Mintz 	int rc, hwfn_index;
2284cee4d264SManish Chopra 
22853da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2286cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2287cee4d264SManish Chopra 
22883da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
22893da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2290cee4d264SManish Chopra 
22913da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_start(p_hwfn,
2292cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
22933da7a37aSMintz, Yuval 				    p_params,
2294cee4d264SManish Chopra 				    bd_max_bytes,
2295cee4d264SManish Chopra 				    bd_chain_phys_addr,
22963da7a37aSMintz, Yuval 				    cqe_pbl_addr, cqe_pbl_size, ret_params);
2297cee4d264SManish Chopra 	if (rc) {
22983da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
2299cee4d264SManish Chopra 		return rc;
2300cee4d264SManish Chopra 	}
2301cee4d264SManish Chopra 
2302cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2303f604b17dSMintz, Yuval 		   "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
23043da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
2305f604b17dSMintz, Yuval 		   p_params->p_sb->igu_sb_id);
2306cee4d264SManish Chopra 
2307cee4d264SManish Chopra 	return 0;
2308cee4d264SManish Chopra }
2309cee4d264SManish Chopra 
23103da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
2311cee4d264SManish Chopra {
2312cee4d264SManish Chopra 	int rc, hwfn_index;
2313cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2314cee4d264SManish Chopra 
23153da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2316cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2317cee4d264SManish Chopra 
23183da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
2319cee4d264SManish Chopra 	if (rc) {
23203da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
2321cee4d264SManish Chopra 		return rc;
2322cee4d264SManish Chopra 	}
2323cee4d264SManish Chopra 
2324cee4d264SManish Chopra 	return 0;
2325cee4d264SManish Chopra }
2326cee4d264SManish Chopra 
2327cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev,
23283da7a37aSMintz, Yuval 			 u8 rss_num,
2329cee4d264SManish Chopra 			 struct qed_queue_start_common_params *p_params,
2330cee4d264SManish Chopra 			 dma_addr_t pbl_addr,
2331cee4d264SManish Chopra 			 u16 pbl_size,
23323da7a37aSMintz, Yuval 			 struct qed_txq_start_ret_params *ret_params)
2333cee4d264SManish Chopra {
2334cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2335cee4d264SManish Chopra 	int rc, hwfn_index;
2336cee4d264SManish Chopra 
23373da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2338cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
23393da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
23403da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2341cee4d264SManish Chopra 
23423da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_start(p_hwfn,
2343cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
23443da7a37aSMintz, Yuval 				    p_params, 0,
23453da7a37aSMintz, Yuval 				    pbl_addr, pbl_size, ret_params);
2346cee4d264SManish Chopra 
2347cee4d264SManish Chopra 	if (rc) {
2348cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2349cee4d264SManish Chopra 		return rc;
2350cee4d264SManish Chopra 	}
2351cee4d264SManish Chopra 
2352cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2353f604b17dSMintz, Yuval 		   "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
23543da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
2355f604b17dSMintz, Yuval 		   p_params->p_sb->igu_sb_id);
2356cee4d264SManish Chopra 
2357cee4d264SManish Chopra 	return 0;
2358cee4d264SManish Chopra }
2359cee4d264SManish Chopra 
2360cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10)
2361cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev)
2362cee4d264SManish Chopra {
236315582962SRahul Verma 	int rc;
236415582962SRahul Verma 
236515582962SRahul Verma 	rc = qed_hw_stop_fastpath(cdev);
236615582962SRahul Verma 	if (rc) {
236715582962SRahul Verma 		DP_ERR(cdev, "Failed to stop Fastpath\n");
236815582962SRahul Verma 		return rc;
236915582962SRahul Verma 	}
2370cee4d264SManish Chopra 
2371cee4d264SManish Chopra 	return 0;
2372cee4d264SManish Chopra }
2373cee4d264SManish Chopra 
23743da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
2375cee4d264SManish Chopra {
2376cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2377cee4d264SManish Chopra 	int rc, hwfn_index;
2378cee4d264SManish Chopra 
23793da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2380cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2381cee4d264SManish Chopra 
23823da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_stop(p_hwfn, handle);
2383cee4d264SManish Chopra 	if (rc) {
23843da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
2385cee4d264SManish Chopra 		return rc;
2386cee4d264SManish Chopra 	}
2387cee4d264SManish Chopra 
2388cee4d264SManish Chopra 	return 0;
2389cee4d264SManish Chopra }
2390cee4d264SManish Chopra 
2391464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev,
2392464f6645SManish Chopra 			      struct qed_tunn_params *tunn_params)
2393464f6645SManish Chopra {
239419968430SChopra, Manish 	struct qed_tunnel_info tunn_info;
2395464f6645SManish Chopra 	int i, rc;
2396464f6645SManish Chopra 
2397464f6645SManish Chopra 	memset(&tunn_info, 0, sizeof(tunn_info));
239819968430SChopra, Manish 	if (tunn_params->update_vxlan_port) {
239919968430SChopra, Manish 		tunn_info.vxlan_port.b_update_port = true;
240019968430SChopra, Manish 		tunn_info.vxlan_port.port = tunn_params->vxlan_port;
2401464f6645SManish Chopra 	}
2402464f6645SManish Chopra 
240319968430SChopra, Manish 	if (tunn_params->update_geneve_port) {
240419968430SChopra, Manish 		tunn_info.geneve_port.b_update_port = true;
240519968430SChopra, Manish 		tunn_info.geneve_port.port = tunn_params->geneve_port;
2406464f6645SManish Chopra 	}
2407464f6645SManish Chopra 
2408464f6645SManish Chopra 	for_each_hwfn(cdev, i) {
2409464f6645SManish Chopra 		struct qed_hwfn *hwfn = &cdev->hwfns[i];
24104f64675fSManish Chopra 		struct qed_ptt *p_ptt;
241197379f15SChopra, Manish 		struct qed_tunnel_info *tun;
241297379f15SChopra, Manish 
241397379f15SChopra, Manish 		tun = &hwfn->cdev->tunnel;
24144f64675fSManish Chopra 		if (IS_PF(cdev)) {
24154f64675fSManish Chopra 			p_ptt = qed_ptt_acquire(hwfn);
24164f64675fSManish Chopra 			if (!p_ptt)
24174f64675fSManish Chopra 				return -EAGAIN;
24184f64675fSManish Chopra 		} else {
24194f64675fSManish Chopra 			p_ptt = NULL;
24204f64675fSManish Chopra 		}
2421464f6645SManish Chopra 
24224f64675fSManish Chopra 		rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
2423464f6645SManish Chopra 					       QED_SPQ_MODE_EBLOCK, NULL);
24244f64675fSManish Chopra 		if (rc) {
24254f64675fSManish Chopra 			if (IS_PF(cdev))
24264f64675fSManish Chopra 				qed_ptt_release(hwfn, p_ptt);
2427464f6645SManish Chopra 			return rc;
24284f64675fSManish Chopra 		}
242997379f15SChopra, Manish 
243097379f15SChopra, Manish 		if (IS_PF_SRIOV(hwfn)) {
243197379f15SChopra, Manish 			u16 vxlan_port, geneve_port;
243297379f15SChopra, Manish 			int j;
243397379f15SChopra, Manish 
243497379f15SChopra, Manish 			vxlan_port = tun->vxlan_port.port;
243597379f15SChopra, Manish 			geneve_port = tun->geneve_port.port;
243697379f15SChopra, Manish 
243797379f15SChopra, Manish 			qed_for_each_vf(hwfn, j) {
243897379f15SChopra, Manish 				qed_iov_bulletin_set_udp_ports(hwfn, j,
243997379f15SChopra, Manish 							       vxlan_port,
244097379f15SChopra, Manish 							       geneve_port);
244197379f15SChopra, Manish 			}
244297379f15SChopra, Manish 
244397379f15SChopra, Manish 			qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
244497379f15SChopra, Manish 		}
24454f64675fSManish Chopra 		if (IS_PF(cdev))
24464f64675fSManish Chopra 			qed_ptt_release(hwfn, p_ptt);
2447464f6645SManish Chopra 	}
2448464f6645SManish Chopra 
2449464f6645SManish Chopra 	return 0;
2450464f6645SManish Chopra }
2451464f6645SManish Chopra 
2452cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2453cee4d264SManish Chopra 					enum qed_filter_rx_mode_type type)
2454cee4d264SManish Chopra {
2455cee4d264SManish Chopra 	struct qed_filter_accept_flags accept_flags;
2456cee4d264SManish Chopra 
2457cee4d264SManish Chopra 	memset(&accept_flags, 0, sizeof(accept_flags));
2458cee4d264SManish Chopra 
2459cee4d264SManish Chopra 	accept_flags.update_rx_mode_config = 1;
2460cee4d264SManish Chopra 	accept_flags.update_tx_mode_config = 1;
2461cee4d264SManish Chopra 	accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2462cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2463cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2464cee4d264SManish Chopra 	accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2465cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2466cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2467cee4d264SManish Chopra 
246888067876SMintz, Yuval 	if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
2469cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2470cee4d264SManish Chopra 						 QED_ACCEPT_MCAST_UNMATCHED;
247188067876SMintz, Yuval 		accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
247288067876SMintz, Yuval 	} else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
2473cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
247488067876SMintz, Yuval 		accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
247588067876SMintz, Yuval 	}
2476cee4d264SManish Chopra 
24773f9b4a69SYuval Mintz 	return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
2478cee4d264SManish Chopra 				     QED_SPQ_MODE_CB, NULL);
2479cee4d264SManish Chopra }
2480cee4d264SManish Chopra 
2481cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev,
2482cee4d264SManish Chopra 				      struct qed_filter_ucast_params *params)
2483cee4d264SManish Chopra {
2484cee4d264SManish Chopra 	struct qed_filter_ucast ucast;
2485cee4d264SManish Chopra 
2486cee4d264SManish Chopra 	if (!params->vlan_valid && !params->mac_valid) {
24871a635e48SYuval Mintz 		DP_NOTICE(cdev,
2488cee4d264SManish Chopra 			  "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
2489cee4d264SManish Chopra 		return -EINVAL;
2490cee4d264SManish Chopra 	}
2491cee4d264SManish Chopra 
2492cee4d264SManish Chopra 	memset(&ucast, 0, sizeof(ucast));
2493cee4d264SManish Chopra 	switch (params->type) {
2494cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2495cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_ADD;
2496cee4d264SManish Chopra 		break;
2497cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2498cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REMOVE;
2499cee4d264SManish Chopra 		break;
2500cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_REPLACE:
2501cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REPLACE;
2502cee4d264SManish Chopra 		break;
2503cee4d264SManish Chopra 	default:
2504cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2505cee4d264SManish Chopra 			  params->type);
2506cee4d264SManish Chopra 	}
2507cee4d264SManish Chopra 
2508cee4d264SManish Chopra 	if (params->vlan_valid && params->mac_valid) {
2509cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC_VLAN;
2510cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2511cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2512cee4d264SManish Chopra 	} else if (params->mac_valid) {
2513cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC;
2514cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2515cee4d264SManish Chopra 	} else {
2516cee4d264SManish Chopra 		ucast.type = QED_FILTER_VLAN;
2517cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2518cee4d264SManish Chopra 	}
2519cee4d264SManish Chopra 
2520cee4d264SManish Chopra 	ucast.is_rx_filter = true;
2521cee4d264SManish Chopra 	ucast.is_tx_filter = true;
2522cee4d264SManish Chopra 
2523cee4d264SManish Chopra 	return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2524cee4d264SManish Chopra }
2525cee4d264SManish Chopra 
2526cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev,
2527cee4d264SManish Chopra 				      struct qed_filter_mcast_params *params)
2528cee4d264SManish Chopra {
2529cee4d264SManish Chopra 	struct qed_filter_mcast mcast;
2530cee4d264SManish Chopra 	int i;
2531cee4d264SManish Chopra 
2532cee4d264SManish Chopra 	memset(&mcast, 0, sizeof(mcast));
2533cee4d264SManish Chopra 	switch (params->type) {
2534cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2535cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_ADD;
2536cee4d264SManish Chopra 		break;
2537cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2538cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_REMOVE;
2539cee4d264SManish Chopra 		break;
2540cee4d264SManish Chopra 	default:
2541cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2542cee4d264SManish Chopra 			  params->type);
2543cee4d264SManish Chopra 	}
2544cee4d264SManish Chopra 
2545cee4d264SManish Chopra 	mcast.num_mc_addrs = params->num;
2546cee4d264SManish Chopra 	for (i = 0; i < mcast.num_mc_addrs; i++)
2547cee4d264SManish Chopra 		ether_addr_copy(mcast.mac[i], params->mac[i]);
2548cee4d264SManish Chopra 
25491a635e48SYuval Mintz 	return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
2550cee4d264SManish Chopra }
2551cee4d264SManish Chopra 
2552cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev,
2553cee4d264SManish Chopra 				struct qed_filter_params *params)
2554cee4d264SManish Chopra {
2555cee4d264SManish Chopra 	enum qed_filter_rx_mode_type accept_flags;
2556cee4d264SManish Chopra 
2557cee4d264SManish Chopra 	switch (params->type) {
2558cee4d264SManish Chopra 	case QED_FILTER_TYPE_UCAST:
2559cee4d264SManish Chopra 		return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2560cee4d264SManish Chopra 	case QED_FILTER_TYPE_MCAST:
2561cee4d264SManish Chopra 		return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2562cee4d264SManish Chopra 	case QED_FILTER_TYPE_RX_MODE:
2563cee4d264SManish Chopra 		accept_flags = params->filter.accept_flags;
2564cee4d264SManish Chopra 		return qed_configure_filter_rx_mode(cdev, accept_flags);
2565cee4d264SManish Chopra 	default:
25661a635e48SYuval Mintz 		DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
2567cee4d264SManish Chopra 		return -EINVAL;
2568cee4d264SManish Chopra 	}
2569cee4d264SManish Chopra }
2570cee4d264SManish Chopra 
2571d51e4af5SChopra, Manish static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
2572d51e4af5SChopra, Manish {
2573d51e4af5SChopra, Manish 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2574d51e4af5SChopra, Manish 	struct qed_arfs_config_params arfs_config_params;
2575d51e4af5SChopra, Manish 
2576d51e4af5SChopra, Manish 	memset(&arfs_config_params, 0, sizeof(arfs_config_params));
2577d51e4af5SChopra, Manish 	arfs_config_params.tcp = true;
2578d51e4af5SChopra, Manish 	arfs_config_params.udp = true;
2579d51e4af5SChopra, Manish 	arfs_config_params.ipv4 = true;
2580d51e4af5SChopra, Manish 	arfs_config_params.ipv6 = true;
2581d51e4af5SChopra, Manish 	arfs_config_params.arfs_enable = en_searcher;
2582d51e4af5SChopra, Manish 
2583d51e4af5SChopra, Manish 	qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
2584d51e4af5SChopra, Manish 				&arfs_config_params);
2585d51e4af5SChopra, Manish 	return 0;
2586d51e4af5SChopra, Manish }
2587d51e4af5SChopra, Manish 
2588d51e4af5SChopra, Manish static void
2589d51e4af5SChopra, Manish qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
2590d51e4af5SChopra, Manish 			     void *cookie, union event_ring_data *data,
2591d51e4af5SChopra, Manish 			     u8 fw_return_code)
2592d51e4af5SChopra, Manish {
2593d51e4af5SChopra, Manish 	struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
2594d51e4af5SChopra, Manish 	void *dev = p_hwfn->cdev->ops_cookie;
2595d51e4af5SChopra, Manish 
2596d51e4af5SChopra, Manish 	op->arfs_filter_op(dev, cookie, fw_return_code);
2597d51e4af5SChopra, Manish }
2598d51e4af5SChopra, Manish 
2599d51e4af5SChopra, Manish static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
2600d51e4af5SChopra, Manish 					 dma_addr_t mapping, u16 length,
2601d51e4af5SChopra, Manish 					 u16 vport_id, u16 rx_queue_id,
2602d51e4af5SChopra, Manish 					 bool add_filter)
2603d51e4af5SChopra, Manish {
2604d51e4af5SChopra, Manish 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2605d51e4af5SChopra, Manish 	struct qed_spq_comp_cb cb;
2606d51e4af5SChopra, Manish 	int rc = -EINVAL;
2607d51e4af5SChopra, Manish 
2608d51e4af5SChopra, Manish 	cb.function = qed_arfs_sp_response_handler;
2609d51e4af5SChopra, Manish 	cb.cookie = cookie;
2610d51e4af5SChopra, Manish 
2611d51e4af5SChopra, Manish 	rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
2612d51e4af5SChopra, Manish 					     &cb, mapping, length, rx_queue_id,
2613d51e4af5SChopra, Manish 					     vport_id, add_filter);
2614d51e4af5SChopra, Manish 	if (rc)
2615d51e4af5SChopra, Manish 		DP_NOTICE(p_hwfn,
2616d51e4af5SChopra, Manish 			  "Failed to issue a-RFS filter configuration\n");
2617d51e4af5SChopra, Manish 	else
2618d51e4af5SChopra, Manish 		DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
2619d51e4af5SChopra, Manish 			   "Successfully issued a-RFS filter configuration\n");
2620d51e4af5SChopra, Manish 
2621d51e4af5SChopra, Manish 	return rc;
2622d51e4af5SChopra, Manish }
2623d51e4af5SChopra, Manish 
2624cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev,
26251a635e48SYuval Mintz 				 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
2626cee4d264SManish Chopra {
2627cee4d264SManish Chopra 	return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2628cee4d264SManish Chopra 				      cqe);
2629cee4d264SManish Chopra }
2630cee4d264SManish Chopra 
26310b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
26320b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass;
26330b55e27dSYuval Mintz #endif
26340b55e27dSYuval Mintz 
2635a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2636a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2637a1d8d8a5SSudarsana Reddy Kalluru #endif
2638a1d8d8a5SSudarsana Reddy Kalluru 
2639c78c70faSSudarsana Reddy Kalluru extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
2640c78c70faSSudarsana Reddy Kalluru 
264125c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = {
264225c089d7SYuval Mintz 	.common = &qed_common_ops_pass,
26430b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
26440b55e27dSYuval Mintz 	.iov = &qed_iov_ops_pass,
26450b55e27dSYuval Mintz #endif
2646a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2647a1d8d8a5SSudarsana Reddy Kalluru 	.dcb = &qed_dcbnl_ops_pass,
2648a1d8d8a5SSudarsana Reddy Kalluru #endif
2649c78c70faSSudarsana Reddy Kalluru 	.ptp = &qed_ptp_ops_pass,
265025c089d7SYuval Mintz 	.fill_dev_info = &qed_fill_eth_dev_info,
2651cc875c2eSYuval Mintz 	.register_ops = &qed_register_eth_ops,
2652eff16960SYuval Mintz 	.check_mac = &qed_check_mac,
2653cee4d264SManish Chopra 	.vport_start = &qed_start_vport,
2654cee4d264SManish Chopra 	.vport_stop = &qed_stop_vport,
2655cee4d264SManish Chopra 	.vport_update = &qed_update_vport,
2656cee4d264SManish Chopra 	.q_rx_start = &qed_start_rxq,
2657cee4d264SManish Chopra 	.q_rx_stop = &qed_stop_rxq,
2658cee4d264SManish Chopra 	.q_tx_start = &qed_start_txq,
2659cee4d264SManish Chopra 	.q_tx_stop = &qed_stop_txq,
2660cee4d264SManish Chopra 	.filter_config = &qed_configure_filter,
2661cee4d264SManish Chopra 	.fastpath_stop = &qed_fastpath_stop,
2662cee4d264SManish Chopra 	.eth_cqe_completion = &qed_fp_cqe_completion,
26639df2ed04SManish Chopra 	.get_vport_stats = &qed_get_vport_stats,
2664464f6645SManish Chopra 	.tunn_config = &qed_tunn_configure,
2665d51e4af5SChopra, Manish 	.ntuple_filter_config = &qed_ntuple_arfs_filter_config,
2666d51e4af5SChopra, Manish 	.configure_arfs_searcher = &qed_configure_arfs_searcher,
266725c089d7SYuval Mintz };
266825c089d7SYuval Mintz 
266995114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void)
267025c089d7SYuval Mintz {
267125c089d7SYuval Mintz 	return &qed_eth_ops_pass;
267225c089d7SYuval Mintz }
267325c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops);
267425c089d7SYuval Mintz 
267525c089d7SYuval Mintz void qed_put_eth_ops(void)
267625c089d7SYuval Mintz {
267725c089d7SYuval Mintz 	/* TODO - reference count for module? */
267825c089d7SYuval Mintz }
267925c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops);
2680