125c089d7SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 325c089d7SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 3125c089d7SYuval Mintz */ 3225c089d7SYuval Mintz 3325c089d7SYuval Mintz #include <linux/types.h> 3425c089d7SYuval Mintz #include <asm/byteorder.h> 3525c089d7SYuval Mintz #include <asm/param.h> 3625c089d7SYuval Mintz #include <linux/delay.h> 3725c089d7SYuval Mintz #include <linux/dma-mapping.h> 3825c089d7SYuval Mintz #include <linux/etherdevice.h> 3925c089d7SYuval Mintz #include <linux/interrupt.h> 4025c089d7SYuval Mintz #include <linux/kernel.h> 4125c089d7SYuval Mintz #include <linux/module.h> 4225c089d7SYuval Mintz #include <linux/pci.h> 4325c089d7SYuval Mintz #include <linux/slab.h> 4425c089d7SYuval Mintz #include <linux/stddef.h> 4525c089d7SYuval Mintz #include <linux/string.h> 4625c089d7SYuval Mintz #include <linux/workqueue.h> 4725c089d7SYuval Mintz #include <linux/bitops.h> 4825c089d7SYuval Mintz #include <linux/bug.h> 493da7a37aSMintz, Yuval #include <linux/vmalloc.h> 5025c089d7SYuval Mintz #include "qed.h" 5125c089d7SYuval Mintz #include <linux/qed/qed_chain.h> 5225c089d7SYuval Mintz #include "qed_cxt.h" 5325c089d7SYuval Mintz #include "qed_dev_api.h" 5425c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h> 5525c089d7SYuval Mintz #include "qed_hsi.h" 5625c089d7SYuval Mintz #include "qed_hw.h" 5725c089d7SYuval Mintz #include "qed_int.h" 58dacd88d6SYuval Mintz #include "qed_l2.h" 5986622ee7SYuval Mintz #include "qed_mcp.h" 6025c089d7SYuval Mintz #include "qed_reg_addr.h" 6125c089d7SYuval Mintz #include "qed_sp.h" 621408cc1fSYuval Mintz #include "qed_sriov.h" 6325c089d7SYuval Mintz 64088c8618SManish Chopra 65cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16 66cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41 67cee4d264SManish Chopra 680db711bbSMintz, Yuval struct qed_l2_info { 690db711bbSMintz, Yuval u32 queues; 700db711bbSMintz, Yuval unsigned long **pp_qid_usage; 710db711bbSMintz, Yuval 720db711bbSMintz, Yuval /* The lock is meant to synchronize access to the qid usage */ 730db711bbSMintz, Yuval struct mutex lock; 740db711bbSMintz, Yuval }; 750db711bbSMintz, Yuval 760db711bbSMintz, Yuval int qed_l2_alloc(struct qed_hwfn *p_hwfn) 770db711bbSMintz, Yuval { 780db711bbSMintz, Yuval struct qed_l2_info *p_l2_info; 790db711bbSMintz, Yuval unsigned long **pp_qids; 800db711bbSMintz, Yuval u32 i; 810db711bbSMintz, Yuval 82c851a9dcSKalderon, Michal if (!QED_IS_L2_PERSONALITY(p_hwfn)) 830db711bbSMintz, Yuval return 0; 840db711bbSMintz, Yuval 850db711bbSMintz, Yuval p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL); 860db711bbSMintz, Yuval if (!p_l2_info) 870db711bbSMintz, Yuval return -ENOMEM; 880db711bbSMintz, Yuval p_hwfn->p_l2_info = p_l2_info; 890db711bbSMintz, Yuval 900db711bbSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 910db711bbSMintz, Yuval p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE); 920db711bbSMintz, Yuval } else { 930db711bbSMintz, Yuval u8 rx = 0, tx = 0; 940db711bbSMintz, Yuval 950db711bbSMintz, Yuval qed_vf_get_num_rxqs(p_hwfn, &rx); 960db711bbSMintz, Yuval qed_vf_get_num_txqs(p_hwfn, &tx); 970db711bbSMintz, Yuval 980db711bbSMintz, Yuval p_l2_info->queues = max_t(u8, rx, tx); 990db711bbSMintz, Yuval } 1000db711bbSMintz, Yuval 1016396bb22SKees Cook pp_qids = kcalloc(p_l2_info->queues, sizeof(unsigned long *), 1020db711bbSMintz, Yuval GFP_KERNEL); 1030db711bbSMintz, Yuval if (!pp_qids) 1040db711bbSMintz, Yuval return -ENOMEM; 1050db711bbSMintz, Yuval p_l2_info->pp_qid_usage = pp_qids; 1060db711bbSMintz, Yuval 1070db711bbSMintz, Yuval for (i = 0; i < p_l2_info->queues; i++) { 1080db711bbSMintz, Yuval pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL); 1090db711bbSMintz, Yuval if (!pp_qids[i]) 1100db711bbSMintz, Yuval return -ENOMEM; 1110db711bbSMintz, Yuval } 1120db711bbSMintz, Yuval 1130db711bbSMintz, Yuval return 0; 1140db711bbSMintz, Yuval } 1150db711bbSMintz, Yuval 1160db711bbSMintz, Yuval void qed_l2_setup(struct qed_hwfn *p_hwfn) 1170db711bbSMintz, Yuval { 118af6858eeSMichal Kalderon if (!QED_IS_L2_PERSONALITY(p_hwfn)) 1190db711bbSMintz, Yuval return; 1200db711bbSMintz, Yuval 1210db711bbSMintz, Yuval mutex_init(&p_hwfn->p_l2_info->lock); 1220db711bbSMintz, Yuval } 1230db711bbSMintz, Yuval 1240db711bbSMintz, Yuval void qed_l2_free(struct qed_hwfn *p_hwfn) 1250db711bbSMintz, Yuval { 1260db711bbSMintz, Yuval u32 i; 1270db711bbSMintz, Yuval 128af6858eeSMichal Kalderon if (!QED_IS_L2_PERSONALITY(p_hwfn)) 1290db711bbSMintz, Yuval return; 1300db711bbSMintz, Yuval 1310db711bbSMintz, Yuval if (!p_hwfn->p_l2_info) 1320db711bbSMintz, Yuval return; 1330db711bbSMintz, Yuval 1340db711bbSMintz, Yuval if (!p_hwfn->p_l2_info->pp_qid_usage) 1350db711bbSMintz, Yuval goto out_l2_info; 1360db711bbSMintz, Yuval 1370db711bbSMintz, Yuval /* Free until hit first uninitialized entry */ 1380db711bbSMintz, Yuval for (i = 0; i < p_hwfn->p_l2_info->queues; i++) { 1390db711bbSMintz, Yuval if (!p_hwfn->p_l2_info->pp_qid_usage[i]) 1400db711bbSMintz, Yuval break; 1410db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info->pp_qid_usage[i]); 1420db711bbSMintz, Yuval } 1430db711bbSMintz, Yuval 1440db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info->pp_qid_usage); 1450db711bbSMintz, Yuval 1460db711bbSMintz, Yuval out_l2_info: 1470db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info); 1480db711bbSMintz, Yuval p_hwfn->p_l2_info = NULL; 1490db711bbSMintz, Yuval } 1500db711bbSMintz, Yuval 151bbe3f233SMintz, Yuval static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn, 152bbe3f233SMintz, Yuval struct qed_queue_cid *p_cid) 153bbe3f233SMintz, Yuval { 154bbe3f233SMintz, Yuval struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info; 155bbe3f233SMintz, Yuval u16 queue_id = p_cid->rel.queue_id; 156bbe3f233SMintz, Yuval bool b_rc = true; 157bbe3f233SMintz, Yuval u8 first; 158bbe3f233SMintz, Yuval 159bbe3f233SMintz, Yuval mutex_lock(&p_l2_info->lock); 160bbe3f233SMintz, Yuval 1610331402aSDan Carpenter if (queue_id >= p_l2_info->queues) { 162bbe3f233SMintz, Yuval DP_NOTICE(p_hwfn, 163bbe3f233SMintz, Yuval "Requested to increase usage for qzone %04x out of %08x\n", 164bbe3f233SMintz, Yuval queue_id, p_l2_info->queues); 165bbe3f233SMintz, Yuval b_rc = false; 166bbe3f233SMintz, Yuval goto out; 167bbe3f233SMintz, Yuval } 168bbe3f233SMintz, Yuval 169bbe3f233SMintz, Yuval first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id], 170bbe3f233SMintz, Yuval MAX_QUEUES_PER_QZONE); 171bbe3f233SMintz, Yuval if (first >= MAX_QUEUES_PER_QZONE) { 172bbe3f233SMintz, Yuval b_rc = false; 173bbe3f233SMintz, Yuval goto out; 174bbe3f233SMintz, Yuval } 175bbe3f233SMintz, Yuval 176bbe3f233SMintz, Yuval __set_bit(first, p_l2_info->pp_qid_usage[queue_id]); 177bbe3f233SMintz, Yuval p_cid->qid_usage_idx = first; 178bbe3f233SMintz, Yuval 179bbe3f233SMintz, Yuval out: 180bbe3f233SMintz, Yuval mutex_unlock(&p_l2_info->lock); 181bbe3f233SMintz, Yuval return b_rc; 182bbe3f233SMintz, Yuval } 183bbe3f233SMintz, Yuval 184bbe3f233SMintz, Yuval static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn, 185bbe3f233SMintz, Yuval struct qed_queue_cid *p_cid) 186bbe3f233SMintz, Yuval { 187bbe3f233SMintz, Yuval mutex_lock(&p_hwfn->p_l2_info->lock); 188bbe3f233SMintz, Yuval 189bbe3f233SMintz, Yuval clear_bit(p_cid->qid_usage_idx, 190bbe3f233SMintz, Yuval p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]); 191bbe3f233SMintz, Yuval 192bbe3f233SMintz, Yuval mutex_unlock(&p_hwfn->p_l2_info->lock); 193bbe3f233SMintz, Yuval } 194bbe3f233SMintz, Yuval 1953da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn, 1963da7a37aSMintz, Yuval struct qed_queue_cid *p_cid) 1973da7a37aSMintz, Yuval { 19808bc8f15SMintz, Yuval bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID); 19908bc8f15SMintz, Yuval 20008bc8f15SMintz, Yuval if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) 20108bc8f15SMintz, Yuval _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid); 202bbe3f233SMintz, Yuval 203bbe3f233SMintz, Yuval /* For PF's VFs we maintain the index inside queue-zone in IOV */ 204bbe3f233SMintz, Yuval if (p_cid->vfid == QED_QUEUE_CID_SELF) 205bbe3f233SMintz, Yuval qed_eth_queue_qid_usage_del(p_hwfn, p_cid); 206bbe3f233SMintz, Yuval 2073da7a37aSMintz, Yuval vfree(p_cid); 2083da7a37aSMintz, Yuval } 2093da7a37aSMintz, Yuval 2103da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs 2113da7a37aSMintz, Yuval * for their VFs. 2123da7a37aSMintz, Yuval */ 2133946497aSMintz, Yuval static struct qed_queue_cid * 2143da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 2153da7a37aSMintz, Yuval u16 opaque_fid, 2163da7a37aSMintz, Yuval u32 cid, 2173946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 218007bc371SMintz, Yuval bool b_is_rx, 2193946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params) 2203da7a37aSMintz, Yuval { 2213da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 2223da7a37aSMintz, Yuval int rc; 2233da7a37aSMintz, Yuval 2245f58dff9SHimanshu Jha p_cid = vzalloc(sizeof(*p_cid)); 2253da7a37aSMintz, Yuval if (!p_cid) 2263da7a37aSMintz, Yuval return NULL; 2273da7a37aSMintz, Yuval 2283da7a37aSMintz, Yuval p_cid->opaque_fid = opaque_fid; 2293da7a37aSMintz, Yuval p_cid->cid = cid; 230f29ffdb6SMintz, Yuval p_cid->p_owner = p_hwfn; 2313da7a37aSMintz, Yuval 232f604b17dSMintz, Yuval /* Fill in parameters */ 233f604b17dSMintz, Yuval p_cid->rel.vport_id = p_params->vport_id; 234f604b17dSMintz, Yuval p_cid->rel.queue_id = p_params->queue_id; 235f604b17dSMintz, Yuval p_cid->rel.stats_id = p_params->stats_id; 236f604b17dSMintz, Yuval p_cid->sb_igu_id = p_params->p_sb->igu_sb_id; 237007bc371SMintz, Yuval p_cid->b_is_rx = b_is_rx; 238f604b17dSMintz, Yuval p_cid->sb_idx = p_params->sb_idx; 239f604b17dSMintz, Yuval 2403946497aSMintz, Yuval /* Fill-in bits related to VFs' queues if information was provided */ 2413946497aSMintz, Yuval if (p_vf_params) { 2423946497aSMintz, Yuval p_cid->vfid = p_vf_params->vfid; 2433946497aSMintz, Yuval p_cid->vf_qid = p_vf_params->vf_qid; 2443b19f478SMintz, Yuval p_cid->vf_legacy = p_vf_params->vf_legacy; 2453946497aSMintz, Yuval } else { 2463946497aSMintz, Yuval p_cid->vfid = QED_QUEUE_CID_SELF; 2473946497aSMintz, Yuval } 2483946497aSMintz, Yuval 2493da7a37aSMintz, Yuval /* Don't try calculating the absolute indices for VFs */ 2503da7a37aSMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 2513da7a37aSMintz, Yuval p_cid->abs = p_cid->rel; 2523da7a37aSMintz, Yuval goto out; 2533da7a37aSMintz, Yuval } 2543da7a37aSMintz, Yuval 2553da7a37aSMintz, Yuval /* Calculate the engine-absolute indices of the resources. 2563da7a37aSMintz, Yuval * This would guarantee they're valid later on. 2573da7a37aSMintz, Yuval * In some cases [SBs] we already have the right values. 2583da7a37aSMintz, Yuval */ 2593da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id); 2603da7a37aSMintz, Yuval if (rc) 2613da7a37aSMintz, Yuval goto fail; 2623da7a37aSMintz, Yuval 2633da7a37aSMintz, Yuval rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id); 2643da7a37aSMintz, Yuval if (rc) 2653da7a37aSMintz, Yuval goto fail; 2663da7a37aSMintz, Yuval 2673da7a37aSMintz, Yuval /* In case of a PF configuring its VF's queues, the stats-id is already 2683da7a37aSMintz, Yuval * absolute [since there's a single index that's suitable per-VF]. 2693da7a37aSMintz, Yuval */ 2703946497aSMintz, Yuval if (p_cid->vfid == QED_QUEUE_CID_SELF) { 2713da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id, 2723da7a37aSMintz, Yuval &p_cid->abs.stats_id); 2733da7a37aSMintz, Yuval if (rc) 2743da7a37aSMintz, Yuval goto fail; 2753da7a37aSMintz, Yuval } else { 2763da7a37aSMintz, Yuval p_cid->abs.stats_id = p_cid->rel.stats_id; 2773da7a37aSMintz, Yuval } 2783da7a37aSMintz, Yuval 2793da7a37aSMintz, Yuval out: 280bbe3f233SMintz, Yuval /* VF-images have provided the qid_usage_idx on their own. 281bbe3f233SMintz, Yuval * Otherwise, we need to allocate a unique one. 282bbe3f233SMintz, Yuval */ 283bbe3f233SMintz, Yuval if (!p_vf_params) { 284bbe3f233SMintz, Yuval if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid)) 285bbe3f233SMintz, Yuval goto fail; 286bbe3f233SMintz, Yuval } else { 287bbe3f233SMintz, Yuval p_cid->qid_usage_idx = p_vf_params->qid_usage_idx; 288bbe3f233SMintz, Yuval } 289bbe3f233SMintz, Yuval 2903da7a37aSMintz, Yuval DP_VERBOSE(p_hwfn, 2913da7a37aSMintz, Yuval QED_MSG_SP, 292bbe3f233SMintz, Yuval "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n", 2933da7a37aSMintz, Yuval p_cid->opaque_fid, 2943da7a37aSMintz, Yuval p_cid->cid, 2953da7a37aSMintz, Yuval p_cid->rel.vport_id, 2963da7a37aSMintz, Yuval p_cid->abs.vport_id, 2973da7a37aSMintz, Yuval p_cid->rel.queue_id, 298bbe3f233SMintz, Yuval p_cid->qid_usage_idx, 2993da7a37aSMintz, Yuval p_cid->abs.queue_id, 3003da7a37aSMintz, Yuval p_cid->rel.stats_id, 301f604b17dSMintz, Yuval p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx); 3023da7a37aSMintz, Yuval 3033da7a37aSMintz, Yuval return p_cid; 3043da7a37aSMintz, Yuval 3053da7a37aSMintz, Yuval fail: 3063da7a37aSMintz, Yuval vfree(p_cid); 3073da7a37aSMintz, Yuval return NULL; 3083da7a37aSMintz, Yuval } 3093da7a37aSMintz, Yuval 3103946497aSMintz, Yuval struct qed_queue_cid * 3113946497aSMintz, Yuval qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 3123946497aSMintz, Yuval u16 opaque_fid, 3133946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 314007bc371SMintz, Yuval bool b_is_rx, 3153946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params) 3163da7a37aSMintz, Yuval { 3173da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 31808bc8f15SMintz, Yuval u8 vfid = QED_CXT_PF_CID; 3193946497aSMintz, Yuval bool b_legacy_vf = false; 3203da7a37aSMintz, Yuval u32 cid = 0; 3213da7a37aSMintz, Yuval 32208bc8f15SMintz, Yuval /* In case of legacy VFs, The CID can be derived from the additional 32308bc8f15SMintz, Yuval * VF parameters - the VF assumes queue X uses CID X, so we can simply 32408bc8f15SMintz, Yuval * use the vf_qid for this purpose as well. 32508bc8f15SMintz, Yuval */ 32608bc8f15SMintz, Yuval if (p_vf_params) { 32708bc8f15SMintz, Yuval vfid = p_vf_params->vfid; 32808bc8f15SMintz, Yuval 32908bc8f15SMintz, Yuval if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) { 3303946497aSMintz, Yuval b_legacy_vf = true; 33108bc8f15SMintz, Yuval cid = p_vf_params->vf_qid; 33208bc8f15SMintz, Yuval } 33308bc8f15SMintz, Yuval } 33408bc8f15SMintz, Yuval 3353da7a37aSMintz, Yuval /* Get a unique firmware CID for this queue, in case it's a PF. 3363da7a37aSMintz, Yuval * VF's don't need a CID as the queue configuration will be done 3373da7a37aSMintz, Yuval * by PF. 3383da7a37aSMintz, Yuval */ 3393946497aSMintz, Yuval if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) { 34008bc8f15SMintz, Yuval if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 34108bc8f15SMintz, Yuval &cid, vfid)) { 3423da7a37aSMintz, Yuval DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 3433da7a37aSMintz, Yuval return NULL; 3443da7a37aSMintz, Yuval } 3453da7a37aSMintz, Yuval } 3463da7a37aSMintz, Yuval 3473946497aSMintz, Yuval p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 348007bc371SMintz, Yuval p_params, b_is_rx, p_vf_params); 3493946497aSMintz, Yuval if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf) 35008bc8f15SMintz, Yuval _qed_cxt_release_cid(p_hwfn, cid, vfid); 3513da7a37aSMintz, Yuval 3523da7a37aSMintz, Yuval return p_cid; 3533da7a37aSMintz, Yuval } 3543da7a37aSMintz, Yuval 3553946497aSMintz, Yuval static struct qed_queue_cid * 3563946497aSMintz, Yuval qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn, 3573946497aSMintz, Yuval u16 opaque_fid, 358007bc371SMintz, Yuval bool b_is_rx, 3593946497aSMintz, Yuval struct qed_queue_start_common_params *p_params) 3603946497aSMintz, Yuval { 361007bc371SMintz, Yuval return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx, 3623946497aSMintz, Yuval NULL); 3633946497aSMintz, Yuval } 3643946497aSMintz, Yuval 365dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 366088c8618SManish Chopra struct qed_sp_vport_start_params *p_params) 367cee4d264SManish Chopra { 368cee4d264SManish Chopra struct vport_start_ramrod_data *p_ramrod = NULL; 369cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 37006f56b81SYuval Mintz struct qed_sp_init_data init_data; 371dacd88d6SYuval Mintz u8 abs_vport_id = 0; 372cee4d264SManish Chopra int rc = -EINVAL; 373cee4d264SManish Chopra u16 rx_mode = 0; 374cee4d264SManish Chopra 375088c8618SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 3761a635e48SYuval Mintz if (rc) 377cee4d264SManish Chopra return rc; 378cee4d264SManish Chopra 37906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 38006f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 381088c8618SManish Chopra init_data.opaque_fid = p_params->opaque_fid; 38206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 383cee4d264SManish Chopra 384cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 385cee4d264SManish Chopra ETH_RAMROD_VPORT_START, 38606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 387cee4d264SManish Chopra if (rc) 388cee4d264SManish Chopra return rc; 389cee4d264SManish Chopra 390cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_start; 391cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 392cee4d264SManish Chopra 393088c8618SManish Chopra p_ramrod->mtu = cpu_to_le16(p_params->mtu); 394c78c70faSSudarsana Reddy Kalluru p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts; 395088c8618SManish Chopra p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 396088c8618SManish Chopra p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 397e6bd8923SYuval Mintz p_ramrod->untagged = p_params->only_untagged; 398cee4d264SManish Chopra 399cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 400cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 401cee4d264SManish Chopra 402cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 403cee4d264SManish Chopra 404cee4d264SManish Chopra /* TPA related fields */ 4051a635e48SYuval Mintz memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param)); 406cee4d264SManish Chopra 407088c8618SManish Chopra p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; 408088c8618SManish Chopra 409088c8618SManish Chopra switch (p_params->tpa_mode) { 410088c8618SManish Chopra case QED_TPA_MODE_GRO: 411088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 412088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_size = (u16)-1; 413088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; 414088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; 415088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; 416088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; 417088c8618SManish Chopra p_ramrod->tpa_param.tpa_pkt_split_flg = 1; 418088c8618SManish Chopra p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; 419088c8618SManish Chopra break; 420088c8618SManish Chopra default: 421088c8618SManish Chopra break; 422088c8618SManish Chopra } 423088c8618SManish Chopra 424831bfb0eSYuval Mintz p_ramrod->tx_switching_en = p_params->tx_switching; 425831bfb0eSYuval Mintz 42611a85d75SYuval Mintz p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac; 42711a85d75SYuval Mintz p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype; 42811a85d75SYuval Mintz 429cee4d264SManish Chopra /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 430cee4d264SManish Chopra p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 431088c8618SManish Chopra p_params->concrete_fid); 432cee4d264SManish Chopra 433cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 434cee4d264SManish Chopra } 435cee4d264SManish Chopra 436ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 437dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params) 438dacd88d6SYuval Mintz { 439dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 440dacd88d6SYuval Mintz return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, 441dacd88d6SYuval Mintz p_params->mtu, 442dacd88d6SYuval Mintz p_params->remove_inner_vlan, 443dacd88d6SYuval Mintz p_params->tpa_mode, 44408feecd7SYuval Mintz p_params->max_buffers_per_cqe, 44508feecd7SYuval Mintz p_params->only_untagged); 446dacd88d6SYuval Mintz } 447dacd88d6SYuval Mintz 448dacd88d6SYuval Mintz return qed_sp_eth_vport_start(p_hwfn, p_params); 449dacd88d6SYuval Mintz } 450dacd88d6SYuval Mintz 451cee4d264SManish Chopra static int 452cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 453cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 454f29ffdb6SMintz, Yuval struct qed_rss_params *p_rss) 455cee4d264SManish Chopra { 456f29ffdb6SMintz, Yuval struct eth_vport_rss_config *p_config; 457f29ffdb6SMintz, Yuval u16 capabilities = 0; 458f29ffdb6SMintz, Yuval int i, table_size; 459f29ffdb6SMintz, Yuval int rc = 0; 460cee4d264SManish Chopra 461f29ffdb6SMintz, Yuval if (!p_rss) { 462cee4d264SManish Chopra p_ramrod->common.update_rss_flg = 0; 463cee4d264SManish Chopra return rc; 464cee4d264SManish Chopra } 465f29ffdb6SMintz, Yuval p_config = &p_ramrod->rss_config; 466cee4d264SManish Chopra 467f29ffdb6SMintz, Yuval BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM); 468cee4d264SManish Chopra 469f29ffdb6SMintz, Yuval rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id); 470cee4d264SManish Chopra if (rc) 471cee4d264SManish Chopra return rc; 472cee4d264SManish Chopra 473f29ffdb6SMintz, Yuval p_ramrod->common.update_rss_flg = p_rss->update_rss_config; 474f29ffdb6SMintz, Yuval p_config->update_rss_capabilities = p_rss->update_rss_capabilities; 475f29ffdb6SMintz, Yuval p_config->update_rss_ind_table = p_rss->update_rss_ind_table; 476f29ffdb6SMintz, Yuval p_config->update_rss_key = p_rss->update_rss_key; 477cee4d264SManish Chopra 478f29ffdb6SMintz, Yuval p_config->rss_mode = p_rss->rss_enable ? 479cee4d264SManish Chopra ETH_VPORT_RSS_MODE_REGULAR : 480cee4d264SManish Chopra ETH_VPORT_RSS_MODE_DISABLED; 481cee4d264SManish Chopra 482cee4d264SManish Chopra SET_FIELD(capabilities, 483cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 484f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4)); 485cee4d264SManish Chopra SET_FIELD(capabilities, 486cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 487f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6)); 488cee4d264SManish Chopra SET_FIELD(capabilities, 489cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 490f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_TCP)); 491cee4d264SManish Chopra SET_FIELD(capabilities, 492cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 493f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_TCP)); 494cee4d264SManish Chopra SET_FIELD(capabilities, 495cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 496f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_UDP)); 497cee4d264SManish Chopra SET_FIELD(capabilities, 498cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 499f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_UDP)); 500f29ffdb6SMintz, Yuval p_config->tbl_size = p_rss->rss_table_size_log; 501cee4d264SManish Chopra 502f29ffdb6SMintz, Yuval p_config->capabilities = cpu_to_le16(capabilities); 503cee4d264SManish Chopra 504cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 505cee4d264SManish Chopra "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 506cee4d264SManish Chopra p_ramrod->common.update_rss_flg, 507f29ffdb6SMintz, Yuval p_config->rss_mode, 508f29ffdb6SMintz, Yuval p_config->update_rss_capabilities, 509f29ffdb6SMintz, Yuval p_config->capabilities, 510f29ffdb6SMintz, Yuval p_config->update_rss_ind_table, p_config->update_rss_key); 511cee4d264SManish Chopra 512f29ffdb6SMintz, Yuval table_size = min_t(int, QED_RSS_IND_TABLE_SIZE, 513f29ffdb6SMintz, Yuval 1 << p_config->tbl_size); 514f29ffdb6SMintz, Yuval for (i = 0; i < table_size; i++) { 515f29ffdb6SMintz, Yuval struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i]; 516cee4d264SManish Chopra 517f29ffdb6SMintz, Yuval if (!p_queue) 518f29ffdb6SMintz, Yuval return -EINVAL; 519f29ffdb6SMintz, Yuval 520f29ffdb6SMintz, Yuval p_config->indirection_table[i] = 521f29ffdb6SMintz, Yuval cpu_to_le16(p_queue->abs.queue_id); 522f29ffdb6SMintz, Yuval } 523f29ffdb6SMintz, Yuval 524f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 525f29ffdb6SMintz, Yuval "Configured RSS indirection table [%d entries]:\n", 526f29ffdb6SMintz, Yuval table_size); 527f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) { 528f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, 529f29ffdb6SMintz, Yuval NETIF_MSG_IFUP, 530f29ffdb6SMintz, Yuval "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", 531f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i]), 532f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 1]), 533f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 2]), 534f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 3]), 535f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 4]), 536f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 5]), 537f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 6]), 538f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 7]), 539f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 8]), 540f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 9]), 541f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 10]), 542f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 11]), 543f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 12]), 544f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 13]), 545f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 14]), 546f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 15])); 547cee4d264SManish Chopra } 548cee4d264SManish Chopra 549cee4d264SManish Chopra for (i = 0; i < 10; i++) 550f29ffdb6SMintz, Yuval p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]); 551cee4d264SManish Chopra 552cee4d264SManish Chopra return rc; 553cee4d264SManish Chopra } 554cee4d264SManish Chopra 555cee4d264SManish Chopra static void 556cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 557cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 558cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags) 559cee4d264SManish Chopra { 560cee4d264SManish Chopra p_ramrod->common.update_rx_mode_flg = 561cee4d264SManish Chopra accept_flags.update_rx_mode_config; 562cee4d264SManish Chopra 563cee4d264SManish Chopra p_ramrod->common.update_tx_mode_flg = 564cee4d264SManish Chopra accept_flags.update_tx_mode_config; 565cee4d264SManish Chopra 566cee4d264SManish Chopra /* Set Rx mode accept flags */ 567cee4d264SManish Chopra if (p_ramrod->common.update_rx_mode_flg) { 568cee4d264SManish Chopra u8 accept_filter = accept_flags.rx_accept_filter; 569cee4d264SManish Chopra u16 state = 0; 570cee4d264SManish Chopra 571cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 572cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 573cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 574cee4d264SManish Chopra 575cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 576cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 577cee4d264SManish Chopra 578cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 579cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 580cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 581cee4d264SManish Chopra 582cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 583cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 584cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 585cee4d264SManish Chopra 586cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 587cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 588cee4d264SManish Chopra 589d52c89f1SMichal Kalderon SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI, 590d52c89f1SMichal Kalderon !!(accept_filter & QED_ACCEPT_ANY_VNI)); 591d52c89f1SMichal Kalderon 592cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(state); 593cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 594cee4d264SManish Chopra "p_ramrod->rx_mode.state = 0x%x\n", state); 595cee4d264SManish Chopra } 596cee4d264SManish Chopra 597cee4d264SManish Chopra /* Set Tx mode accept flags */ 598cee4d264SManish Chopra if (p_ramrod->common.update_tx_mode_flg) { 599cee4d264SManish Chopra u8 accept_filter = accept_flags.tx_accept_filter; 600cee4d264SManish Chopra u16 state = 0; 601cee4d264SManish Chopra 602cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 603cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 604cee4d264SManish Chopra 605cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 606cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 607cee4d264SManish Chopra 608cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 609cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 610cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 611cee4d264SManish Chopra 612cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 613cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 614cee4d264SManish Chopra 615cee4d264SManish Chopra p_ramrod->tx_mode.state = cpu_to_le16(state); 616cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 617cee4d264SManish Chopra "p_ramrod->tx_mode.state = 0x%x\n", state); 618cee4d264SManish Chopra } 619cee4d264SManish Chopra } 620cee4d264SManish Chopra 621cee4d264SManish Chopra static void 62217b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, 62317b235c1SYuval Mintz struct vport_update_ramrod_data *p_ramrod, 62417b235c1SYuval Mintz struct qed_sge_tpa_params *p_params) 62517b235c1SYuval Mintz { 62617b235c1SYuval Mintz struct eth_vport_tpa_param *p_tpa; 62717b235c1SYuval Mintz 62817b235c1SYuval Mintz if (!p_params) { 62917b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 63017b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = 0; 63117b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 63217b235c1SYuval Mintz return; 63317b235c1SYuval Mintz } 63417b235c1SYuval Mintz 63517b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; 63617b235c1SYuval Mintz p_tpa = &p_ramrod->tpa_param; 63717b235c1SYuval Mintz p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; 63817b235c1SYuval Mintz p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; 63917b235c1SYuval Mintz p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; 64017b235c1SYuval Mintz p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; 64117b235c1SYuval Mintz 64217b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; 64317b235c1SYuval Mintz p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 64417b235c1SYuval Mintz p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; 64517b235c1SYuval Mintz p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; 64617b235c1SYuval Mintz p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; 64717b235c1SYuval Mintz p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; 64817b235c1SYuval Mintz p_tpa->tpa_max_size = p_params->tpa_max_size; 64917b235c1SYuval Mintz p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; 65017b235c1SYuval Mintz p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; 65117b235c1SYuval Mintz } 65217b235c1SYuval Mintz 65317b235c1SYuval Mintz static void 654cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 655cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 656cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params) 657cee4d264SManish Chopra { 658cee4d264SManish Chopra int i; 659cee4d264SManish Chopra 660cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 661cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 662cee4d264SManish Chopra 66383aeb933SYuval Mintz if (!p_params->update_approx_mcast_flg) 66483aeb933SYuval Mintz return; 66583aeb933SYuval Mintz 666cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 667cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 66825c020a9SSudarsana Reddy Kalluru u32 *p_bins = p_params->bins; 669cee4d264SManish Chopra 67083aeb933SYuval Mintz p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]); 671cee4d264SManish Chopra } 672cee4d264SManish Chopra } 673cee4d264SManish Chopra 674dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 675cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params, 676cee4d264SManish Chopra enum spq_mode comp_mode, 677cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 678cee4d264SManish Chopra { 679cee4d264SManish Chopra struct qed_rss_params *p_rss_params = p_params->rss_params; 680cee4d264SManish Chopra struct vport_update_ramrod_data_cmn *p_cmn; 68106f56b81SYuval Mintz struct qed_sp_init_data init_data; 682cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 683cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 68417b235c1SYuval Mintz u8 abs_vport_id = 0, val; 685cee4d264SManish Chopra int rc = -EINVAL; 686cee4d264SManish Chopra 687dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 688dacd88d6SYuval Mintz rc = qed_vf_pf_vport_update(p_hwfn, p_params); 689dacd88d6SYuval Mintz return rc; 690dacd88d6SYuval Mintz } 691dacd88d6SYuval Mintz 692cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 6931a635e48SYuval Mintz if (rc) 694cee4d264SManish Chopra return rc; 695cee4d264SManish Chopra 69606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 69706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 69806f56b81SYuval Mintz init_data.opaque_fid = p_params->opaque_fid; 69906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 70006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 701cee4d264SManish Chopra 702cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 703cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 70406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 705cee4d264SManish Chopra if (rc) 706cee4d264SManish Chopra return rc; 707cee4d264SManish Chopra 708cee4d264SManish Chopra /* Copy input params to ramrod according to FW struct */ 709cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 710cee4d264SManish Chopra p_cmn = &p_ramrod->common; 711cee4d264SManish Chopra 712cee4d264SManish Chopra p_cmn->vport_id = abs_vport_id; 713cee4d264SManish Chopra p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 714cee4d264SManish Chopra p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 715cee4d264SManish Chopra p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 716cee4d264SManish Chopra p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 7173f9b4a69SYuval Mintz p_cmn->accept_any_vlan = p_params->accept_any_vlan; 71883aeb933SYuval Mintz val = p_params->update_accept_any_vlan_flg; 71983aeb933SYuval Mintz p_cmn->update_accept_any_vlan_flg = val; 72017b235c1SYuval Mintz 72117b235c1SYuval Mintz p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; 72217b235c1SYuval Mintz val = p_params->update_inner_vlan_removal_flg; 72317b235c1SYuval Mintz p_cmn->update_inner_vlan_removal_en_flg = val; 72408feecd7SYuval Mintz 72508feecd7SYuval Mintz p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; 72608feecd7SYuval Mintz val = p_params->update_default_vlan_enable_flg; 72708feecd7SYuval Mintz p_cmn->update_default_vlan_en_flg = val; 72808feecd7SYuval Mintz 72908feecd7SYuval Mintz p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); 73008feecd7SYuval Mintz p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; 73108feecd7SYuval Mintz 73208feecd7SYuval Mintz p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; 73308feecd7SYuval Mintz 73417b235c1SYuval Mintz p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; 73517b235c1SYuval Mintz p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; 73617b235c1SYuval Mintz 7376ddc7608SYuval Mintz p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; 7386ddc7608SYuval Mintz val = p_params->update_anti_spoofing_en_flg; 7396ddc7608SYuval Mintz p_ramrod->common.update_anti_spoofing_en_flg = val; 7406ddc7608SYuval Mintz 741cee4d264SManish Chopra rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 742cee4d264SManish Chopra if (rc) { 743cee4d264SManish Chopra /* Return spq entry which is taken in qed_sp_init_request()*/ 744cee4d264SManish Chopra qed_spq_return_entry(p_hwfn, p_ent); 745cee4d264SManish Chopra return rc; 746cee4d264SManish Chopra } 747cee4d264SManish Chopra 748cee4d264SManish Chopra /* Update mcast bins for VFs, PF doesn't use this functionality */ 749cee4d264SManish Chopra qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 750cee4d264SManish Chopra 751cee4d264SManish Chopra qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 75217b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); 753cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 754cee4d264SManish Chopra } 755cee4d264SManish Chopra 756dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) 757cee4d264SManish Chopra { 758cee4d264SManish Chopra struct vport_stop_ramrod_data *p_ramrod; 75906f56b81SYuval Mintz struct qed_sp_init_data init_data; 760cee4d264SManish Chopra struct qed_spq_entry *p_ent; 761cee4d264SManish Chopra u8 abs_vport_id = 0; 762cee4d264SManish Chopra int rc; 763cee4d264SManish Chopra 764dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 765dacd88d6SYuval Mintz return qed_vf_pf_vport_stop(p_hwfn); 766dacd88d6SYuval Mintz 767cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 7681a635e48SYuval Mintz if (rc) 769cee4d264SManish Chopra return rc; 770cee4d264SManish Chopra 77106f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 77206f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 77306f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 77406f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 775cee4d264SManish Chopra 776cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 777cee4d264SManish Chopra ETH_RAMROD_VPORT_STOP, 77806f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 779cee4d264SManish Chopra if (rc) 780cee4d264SManish Chopra return rc; 781cee4d264SManish Chopra 782cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_stop; 783cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 784cee4d264SManish Chopra 785cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 786cee4d264SManish Chopra } 787cee4d264SManish Chopra 788dacd88d6SYuval Mintz static int 789dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, 790dacd88d6SYuval Mintz struct qed_filter_accept_flags *p_accept_flags) 791dacd88d6SYuval Mintz { 792dacd88d6SYuval Mintz struct qed_sp_vport_update_params s_params; 793dacd88d6SYuval Mintz 794dacd88d6SYuval Mintz memset(&s_params, 0, sizeof(s_params)); 795dacd88d6SYuval Mintz memcpy(&s_params.accept_flags, p_accept_flags, 796dacd88d6SYuval Mintz sizeof(struct qed_filter_accept_flags)); 797dacd88d6SYuval Mintz 798dacd88d6SYuval Mintz return qed_vf_pf_vport_update(p_hwfn, &s_params); 799dacd88d6SYuval Mintz } 800dacd88d6SYuval Mintz 801cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev, 802cee4d264SManish Chopra u8 vport, 803cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags, 8043f9b4a69SYuval Mintz u8 update_accept_any_vlan, 8053f9b4a69SYuval Mintz u8 accept_any_vlan, 806cee4d264SManish Chopra enum spq_mode comp_mode, 807cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 808cee4d264SManish Chopra { 809cee4d264SManish Chopra struct qed_sp_vport_update_params vport_update_params; 810cee4d264SManish Chopra int i, rc; 811cee4d264SManish Chopra 812cee4d264SManish Chopra /* Prepare and send the vport rx_mode change */ 813cee4d264SManish Chopra memset(&vport_update_params, 0, sizeof(vport_update_params)); 814cee4d264SManish Chopra vport_update_params.vport_id = vport; 815cee4d264SManish Chopra vport_update_params.accept_flags = accept_flags; 8163f9b4a69SYuval Mintz vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 8173f9b4a69SYuval Mintz vport_update_params.accept_any_vlan = accept_any_vlan; 818cee4d264SManish Chopra 819cee4d264SManish Chopra for_each_hwfn(cdev, i) { 820cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 821cee4d264SManish Chopra 822cee4d264SManish Chopra vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 823cee4d264SManish Chopra 824dacd88d6SYuval Mintz if (IS_VF(cdev)) { 825dacd88d6SYuval Mintz rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); 826dacd88d6SYuval Mintz if (rc) 827dacd88d6SYuval Mintz return rc; 828dacd88d6SYuval Mintz continue; 829dacd88d6SYuval Mintz } 830dacd88d6SYuval Mintz 831cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 832cee4d264SManish Chopra comp_mode, p_comp_data); 8331a635e48SYuval Mintz if (rc) { 834cee4d264SManish Chopra DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 835cee4d264SManish Chopra return rc; 836cee4d264SManish Chopra } 837cee4d264SManish Chopra 838cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 839cee4d264SManish Chopra "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 840cee4d264SManish Chopra accept_flags.rx_accept_filter, 841cee4d264SManish Chopra accept_flags.tx_accept_filter); 8423f9b4a69SYuval Mintz if (update_accept_any_vlan) 8433f9b4a69SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 8443f9b4a69SYuval Mintz "accept_any_vlan=%d configured\n", 8453f9b4a69SYuval Mintz accept_any_vlan); 846cee4d264SManish Chopra } 847cee4d264SManish Chopra 848cee4d264SManish Chopra return 0; 849cee4d264SManish Chopra } 850cee4d264SManish Chopra 8513da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 8523da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 853cee4d264SManish Chopra u16 bd_max_bytes, 854cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 8553da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size) 856cee4d264SManish Chopra { 857cee4d264SManish Chopra struct rx_queue_start_ramrod_data *p_ramrod = NULL; 858cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 85906f56b81SYuval Mintz struct qed_sp_init_data init_data; 860cee4d264SManish Chopra int rc = -EINVAL; 861cee4d264SManish Chopra 862cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 8633da7a37aSMintz, Yuval "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n", 8643da7a37aSMintz, Yuval p_cid->opaque_fid, p_cid->cid, 865f604b17dSMintz, Yuval p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id); 866cee4d264SManish Chopra 86706f56b81SYuval Mintz /* Get SPQ entry */ 86806f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 8693da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 8703da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 87106f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 872cee4d264SManish Chopra 873cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 874cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_START, 87506f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 876cee4d264SManish Chopra if (rc) 877cee4d264SManish Chopra return rc; 878cee4d264SManish Chopra 879cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_start; 880cee4d264SManish Chopra 881f604b17dSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); 882f604b17dSMintz, Yuval p_ramrod->sb_index = p_cid->sb_idx; 8833da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 8843da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 8853da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 886cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 0; 887cee4d264SManish Chopra p_ramrod->complete_event_flg = 1; 888cee4d264SManish Chopra 889cee4d264SManish Chopra p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 89094494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 891cee4d264SManish Chopra 892cee4d264SManish Chopra p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 89394494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 894cee4d264SManish Chopra 8953946497aSMintz, Yuval if (p_cid->vfid != QED_QUEUE_CID_SELF) { 8963b19f478SMintz, Yuval bool b_legacy_vf = !!(p_cid->vf_legacy & 8973b19f478SMintz, Yuval QED_QCID_LEGACY_VF_RX_PROD); 8983b19f478SMintz, Yuval 8993da7a37aSMintz, Yuval p_ramrod->vf_rx_prod_index = p_cid->vf_qid; 900351a4dedSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 901a044df83SYuval Mintz "Queue%s is meant for VF rxq[%02x]\n", 9023b19f478SMintz, Yuval b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid); 9033b19f478SMintz, Yuval p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf; 904a044df83SYuval Mintz } 905cee4d264SManish Chopra 906351a4dedSYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 907cee4d264SManish Chopra } 908cee4d264SManish Chopra 909cee4d264SManish Chopra static int 9103da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn, 9113da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 912cee4d264SManish Chopra u16 bd_max_bytes, 913cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 914cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 915dacd88d6SYuval Mintz u16 cqe_pbl_size, void __iomem **pp_prod) 916cee4d264SManish Chopra { 917b21290b7SYuval Mintz u32 init_prod_val = 0; 918cee4d264SManish Chopra 9193da7a37aSMintz, Yuval *pp_prod = p_hwfn->regview + 920cee4d264SManish Chopra GTT_BAR0_MAP_REG_MSDM_RAM + 9213da7a37aSMintz, Yuval MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); 922cee4d264SManish Chopra 923cee4d264SManish Chopra /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 924b21290b7SYuval Mintz __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), 925cee4d264SManish Chopra (u32 *)(&init_prod_val)); 926cee4d264SManish Chopra 9273da7a37aSMintz, Yuval return qed_eth_rxq_start_ramrod(p_hwfn, p_cid, 928cee4d264SManish Chopra bd_max_bytes, 929cee4d264SManish Chopra bd_chain_phys_addr, 9303da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size); 9313da7a37aSMintz, Yuval } 932cee4d264SManish Chopra 9333da7a37aSMintz, Yuval static int 9343da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 9353da7a37aSMintz, Yuval u16 opaque_fid, 9363da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 9373da7a37aSMintz, Yuval u16 bd_max_bytes, 9383da7a37aSMintz, Yuval dma_addr_t bd_chain_phys_addr, 9393da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, 9403da7a37aSMintz, Yuval u16 cqe_pbl_size, 9413da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *p_ret_params) 9423da7a37aSMintz, Yuval { 9433da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 9443da7a37aSMintz, Yuval int rc; 9453da7a37aSMintz, Yuval 9463da7a37aSMintz, Yuval /* Allocate a CID for the queue */ 947007bc371SMintz, Yuval p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params); 9483da7a37aSMintz, Yuval if (!p_cid) 9493da7a37aSMintz, Yuval return -ENOMEM; 9503da7a37aSMintz, Yuval 9513da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 9523da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid, 9533da7a37aSMintz, Yuval bd_max_bytes, 9543da7a37aSMintz, Yuval bd_chain_phys_addr, 9553da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, 9563da7a37aSMintz, Yuval &p_ret_params->p_prod); 9573da7a37aSMintz, Yuval } else { 9583da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_start(p_hwfn, p_cid, 9593da7a37aSMintz, Yuval bd_max_bytes, 9603da7a37aSMintz, Yuval bd_chain_phys_addr, 9613da7a37aSMintz, Yuval cqe_pbl_addr, 9623da7a37aSMintz, Yuval cqe_pbl_size, &p_ret_params->p_prod); 9633da7a37aSMintz, Yuval } 9643da7a37aSMintz, Yuval 9653da7a37aSMintz, Yuval /* Provide the caller with a reference to as handler */ 9661a635e48SYuval Mintz if (rc) 9673da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 9683da7a37aSMintz, Yuval else 9693da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 970cee4d264SManish Chopra 971cee4d264SManish Chopra return rc; 972cee4d264SManish Chopra } 973cee4d264SManish Chopra 97417b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 9753da7a37aSMintz, Yuval void **pp_rxq_handles, 97617b235c1SYuval Mintz u8 num_rxqs, 97717b235c1SYuval Mintz u8 complete_cqe_flg, 97817b235c1SYuval Mintz u8 complete_event_flg, 97917b235c1SYuval Mintz enum spq_mode comp_mode, 98017b235c1SYuval Mintz struct qed_spq_comp_cb *p_comp_data) 98117b235c1SYuval Mintz { 98217b235c1SYuval Mintz struct rx_queue_update_ramrod_data *p_ramrod = NULL; 98317b235c1SYuval Mintz struct qed_spq_entry *p_ent = NULL; 98417b235c1SYuval Mintz struct qed_sp_init_data init_data; 9853da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 98617b235c1SYuval Mintz int rc = -EINVAL; 98717b235c1SYuval Mintz u8 i; 98817b235c1SYuval Mintz 98917b235c1SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 99017b235c1SYuval Mintz init_data.comp_mode = comp_mode; 99117b235c1SYuval Mintz init_data.p_comp_data = p_comp_data; 99217b235c1SYuval Mintz 99317b235c1SYuval Mintz for (i = 0; i < num_rxqs; i++) { 9943da7a37aSMintz, Yuval p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i]; 99517b235c1SYuval Mintz 99617b235c1SYuval Mintz /* Get SPQ entry */ 9973da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 9983da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 99917b235c1SYuval Mintz 100017b235c1SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 100117b235c1SYuval Mintz ETH_RAMROD_RX_QUEUE_UPDATE, 100217b235c1SYuval Mintz PROTOCOLID_ETH, &init_data); 100317b235c1SYuval Mintz if (rc) 100417b235c1SYuval Mintz return rc; 100517b235c1SYuval Mintz 100617b235c1SYuval Mintz p_ramrod = &p_ent->ramrod.rx_queue_update; 10073da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 100817b235c1SYuval Mintz 10093da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 101017b235c1SYuval Mintz p_ramrod->complete_cqe_flg = complete_cqe_flg; 101117b235c1SYuval Mintz p_ramrod->complete_event_flg = complete_event_flg; 101217b235c1SYuval Mintz 101317b235c1SYuval Mintz rc = qed_spq_post(p_hwfn, p_ent, NULL); 101417b235c1SYuval Mintz if (rc) 101517b235c1SYuval Mintz return rc; 101617b235c1SYuval Mintz } 101717b235c1SYuval Mintz 101817b235c1SYuval Mintz return rc; 101917b235c1SYuval Mintz } 102017b235c1SYuval Mintz 10213da7a37aSMintz, Yuval static int 10223da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn, 10233da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 10243da7a37aSMintz, Yuval bool b_eq_completion_only, bool b_cqe_completion) 1025cee4d264SManish Chopra { 1026cee4d264SManish Chopra struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 1027cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 102806f56b81SYuval Mintz struct qed_sp_init_data init_data; 10293da7a37aSMintz, Yuval int rc; 1030cee4d264SManish Chopra 103106f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 10323da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 10333da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 103406f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1035cee4d264SManish Chopra 1036cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1037cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_STOP, 103806f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1039cee4d264SManish Chopra if (rc) 1040cee4d264SManish Chopra return rc; 1041cee4d264SManish Chopra 1042cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_stop; 10433da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 10443da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 1045cee4d264SManish Chopra 1046cee4d264SManish Chopra /* Cleaning the queue requires the completion to arrive there. 1047cee4d264SManish Chopra * In addition, VFs require the answer to come as eqe to PF. 1048cee4d264SManish Chopra */ 10493946497aSMintz, Yuval p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) && 10503da7a37aSMintz, Yuval !b_eq_completion_only) || 10513da7a37aSMintz, Yuval b_cqe_completion; 10523946497aSMintz, Yuval p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) || 10533946497aSMintz, Yuval b_eq_completion_only; 1054cee4d264SManish Chopra 10553da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 1056cee4d264SManish Chopra } 1057cee4d264SManish Chopra 10583da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 10593da7a37aSMintz, Yuval void *p_rxq, 10603da7a37aSMintz, Yuval bool eq_completion_only, bool cqe_completion) 10613da7a37aSMintz, Yuval { 10623da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq; 10633da7a37aSMintz, Yuval int rc = -EINVAL; 10643da7a37aSMintz, Yuval 10653da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 10663da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid, 10673da7a37aSMintz, Yuval eq_completion_only, 10683da7a37aSMintz, Yuval cqe_completion); 10693da7a37aSMintz, Yuval else 10703da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion); 10713da7a37aSMintz, Yuval 10723da7a37aSMintz, Yuval if (!rc) 10733da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 10743da7a37aSMintz, Yuval return rc; 10753da7a37aSMintz, Yuval } 10763da7a37aSMintz, Yuval 10773da7a37aSMintz, Yuval int 10783da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 10793da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 10803da7a37aSMintz, Yuval dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id) 1081cee4d264SManish Chopra { 1082cee4d264SManish Chopra struct tx_queue_start_ramrod_data *p_ramrod = NULL; 1083cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 108406f56b81SYuval Mintz struct qed_sp_init_data init_data; 1085cee4d264SManish Chopra int rc = -EINVAL; 1086351a4dedSYuval Mintz 108706f56b81SYuval Mintz /* Get SPQ entry */ 108806f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 10893da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 10903da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 109106f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1092cee4d264SManish Chopra 109306f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 1094cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_START, 109506f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1096cee4d264SManish Chopra if (rc) 1097cee4d264SManish Chopra return rc; 1098cee4d264SManish Chopra 1099cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.tx_queue_start; 11003da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 1101cee4d264SManish Chopra 1102f604b17dSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); 1103f604b17dSMintz, Yuval p_ramrod->sb_index = p_cid->sb_idx; 11043da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 1105cee4d264SManish Chopra 11063da7a37aSMintz, Yuval p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id); 11073da7a37aSMintz, Yuval p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id); 11081a635e48SYuval Mintz 1109cee4d264SManish Chopra p_ramrod->pbl_size = cpu_to_le16(pbl_size); 111094494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 1111cee4d264SManish Chopra 1112cee4d264SManish Chopra p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 1113cee4d264SManish Chopra 1114cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1115cee4d264SManish Chopra } 1116cee4d264SManish Chopra 1117cee4d264SManish Chopra static int 11183da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn, 11193da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 11203da7a37aSMintz, Yuval u8 tc, 1121cee4d264SManish Chopra dma_addr_t pbl_addr, 1122dacd88d6SYuval Mintz u16 pbl_size, void __iomem **pp_doorbell) 1123cee4d264SManish Chopra { 1124cee4d264SManish Chopra int rc; 1125cee4d264SManish Chopra 1126cee4d264SManish Chopra 11273da7a37aSMintz, Yuval rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid, 11283da7a37aSMintz, Yuval pbl_addr, pbl_size, 1129b5a9ee7cSAriel Elior qed_get_cm_pq_idx_mcos(p_hwfn, tc)); 11303da7a37aSMintz, Yuval if (rc) 1131cee4d264SManish Chopra return rc; 11323da7a37aSMintz, Yuval 11333da7a37aSMintz, Yuval /* Provide the caller with the necessary return values */ 11343da7a37aSMintz, Yuval *pp_doorbell = p_hwfn->doorbells + 11353da7a37aSMintz, Yuval qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY); 11363da7a37aSMintz, Yuval 11373da7a37aSMintz, Yuval return 0; 1138cee4d264SManish Chopra } 1139cee4d264SManish Chopra 11403da7a37aSMintz, Yuval static int 11413da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 11423da7a37aSMintz, Yuval u16 opaque_fid, 11433da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 11443da7a37aSMintz, Yuval u8 tc, 11453da7a37aSMintz, Yuval dma_addr_t pbl_addr, 11463da7a37aSMintz, Yuval u16 pbl_size, 11473da7a37aSMintz, Yuval struct qed_txq_start_ret_params *p_ret_params) 11483da7a37aSMintz, Yuval { 11493da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 11503da7a37aSMintz, Yuval int rc; 1151cee4d264SManish Chopra 1152007bc371SMintz, Yuval p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params); 11533da7a37aSMintz, Yuval if (!p_cid) 11543da7a37aSMintz, Yuval return -EINVAL; 1155cee4d264SManish Chopra 11563da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 11573da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc, 11583da7a37aSMintz, Yuval pbl_addr, pbl_size, 11593da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 11603da7a37aSMintz, Yuval else 11613da7a37aSMintz, Yuval rc = qed_vf_pf_txq_start(p_hwfn, p_cid, 11623da7a37aSMintz, Yuval pbl_addr, pbl_size, 11633da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 1164cee4d264SManish Chopra 1165cee4d264SManish Chopra if (rc) 11663da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 11673da7a37aSMintz, Yuval else 11683da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 1169cee4d264SManish Chopra 1170cee4d264SManish Chopra return rc; 1171cee4d264SManish Chopra } 1172cee4d264SManish Chopra 11733da7a37aSMintz, Yuval static int 11743da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid) 1175cee4d264SManish Chopra { 1176cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 117706f56b81SYuval Mintz struct qed_sp_init_data init_data; 11783da7a37aSMintz, Yuval int rc; 1179cee4d264SManish Chopra 118006f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 11813da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 11823da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 118306f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1184cee4d264SManish Chopra 1185cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1186cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_STOP, 118706f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1188cee4d264SManish Chopra if (rc) 1189cee4d264SManish Chopra return rc; 1190cee4d264SManish Chopra 11913da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 11923da7a37aSMintz, Yuval } 1193cee4d264SManish Chopra 11943da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle) 11953da7a37aSMintz, Yuval { 11963da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle; 11973da7a37aSMintz, Yuval int rc; 11983da7a37aSMintz, Yuval 11993da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 12003da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid); 12013da7a37aSMintz, Yuval else 12023da7a37aSMintz, Yuval rc = qed_vf_pf_txq_stop(p_hwfn, p_cid); 12033da7a37aSMintz, Yuval 12043da7a37aSMintz, Yuval if (!rc) 12053da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 12063da7a37aSMintz, Yuval return rc; 1207cee4d264SManish Chopra } 1208cee4d264SManish Chopra 12091a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode) 1210cee4d264SManish Chopra { 1211cee4d264SManish Chopra enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 1212cee4d264SManish Chopra 1213cee4d264SManish Chopra switch (opcode) { 1214cee4d264SManish Chopra case QED_FILTER_ADD: 1215cee4d264SManish Chopra action = ETH_FILTER_ACTION_ADD; 1216cee4d264SManish Chopra break; 1217cee4d264SManish Chopra case QED_FILTER_REMOVE: 1218cee4d264SManish Chopra action = ETH_FILTER_ACTION_REMOVE; 1219cee4d264SManish Chopra break; 1220cee4d264SManish Chopra case QED_FILTER_FLUSH: 1221fc48b7a6SYuval Mintz action = ETH_FILTER_ACTION_REMOVE_ALL; 1222cee4d264SManish Chopra break; 1223cee4d264SManish Chopra default: 1224cee4d264SManish Chopra action = MAX_ETH_FILTER_ACTION; 1225cee4d264SManish Chopra } 1226cee4d264SManish Chopra 1227cee4d264SManish Chopra return action; 1228cee4d264SManish Chopra } 1229cee4d264SManish Chopra 1230cee4d264SManish Chopra static int 1231cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 1232cee4d264SManish Chopra u16 opaque_fid, 1233cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1234cee4d264SManish Chopra struct vport_filter_update_ramrod_data **pp_ramrod, 1235cee4d264SManish Chopra struct qed_spq_entry **pp_ent, 1236cee4d264SManish Chopra enum spq_mode comp_mode, 1237cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1238cee4d264SManish Chopra { 1239cee4d264SManish Chopra u8 vport_to_add_to = 0, vport_to_remove_from = 0; 1240cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod; 1241cee4d264SManish Chopra struct eth_filter_cmd *p_first_filter; 1242cee4d264SManish Chopra struct eth_filter_cmd *p_second_filter; 124306f56b81SYuval Mintz struct qed_sp_init_data init_data; 1244cee4d264SManish Chopra enum eth_filter_action action; 1245cee4d264SManish Chopra int rc; 1246cee4d264SManish Chopra 1247cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1248cee4d264SManish Chopra &vport_to_remove_from); 1249cee4d264SManish Chopra if (rc) 1250cee4d264SManish Chopra return rc; 1251cee4d264SManish Chopra 1252cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1253cee4d264SManish Chopra &vport_to_add_to); 1254cee4d264SManish Chopra if (rc) 1255cee4d264SManish Chopra return rc; 1256cee4d264SManish Chopra 125706f56b81SYuval Mintz /* Get SPQ entry */ 125806f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 125906f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 126006f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 126106f56b81SYuval Mintz init_data.comp_mode = comp_mode; 126206f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1263cee4d264SManish Chopra 1264cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, pp_ent, 1265cee4d264SManish Chopra ETH_RAMROD_FILTERS_UPDATE, 126606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1267cee4d264SManish Chopra if (rc) 1268cee4d264SManish Chopra return rc; 1269cee4d264SManish Chopra 1270cee4d264SManish Chopra *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 1271cee4d264SManish Chopra p_ramrod = *pp_ramrod; 1272cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 1273cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 1274cee4d264SManish Chopra 1275cee4d264SManish Chopra switch (p_filter_cmd->opcode) { 1276fc48b7a6SYuval Mintz case QED_FILTER_REPLACE: 1277cee4d264SManish Chopra case QED_FILTER_MOVE: 1278cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 1279cee4d264SManish Chopra default: 1280cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 1281cee4d264SManish Chopra } 1282cee4d264SManish Chopra 1283cee4d264SManish Chopra p_first_filter = &p_ramrod->filter_cmds[0]; 1284cee4d264SManish Chopra p_second_filter = &p_ramrod->filter_cmds[1]; 1285cee4d264SManish Chopra 1286cee4d264SManish Chopra switch (p_filter_cmd->type) { 1287cee4d264SManish Chopra case QED_FILTER_MAC: 1288cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 1289cee4d264SManish Chopra case QED_FILTER_VLAN: 1290cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 1291cee4d264SManish Chopra case QED_FILTER_MAC_VLAN: 1292cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 1293cee4d264SManish Chopra case QED_FILTER_INNER_MAC: 1294cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 1295cee4d264SManish Chopra case QED_FILTER_INNER_VLAN: 1296cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 1297cee4d264SManish Chopra case QED_FILTER_INNER_PAIR: 1298cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 1299cee4d264SManish Chopra case QED_FILTER_INNER_MAC_VNI_PAIR: 1300cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 1301cee4d264SManish Chopra break; 1302cee4d264SManish Chopra case QED_FILTER_MAC_VNI_PAIR: 1303cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 1304cee4d264SManish Chopra case QED_FILTER_VNI: 1305cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 1306cee4d264SManish Chopra } 1307cee4d264SManish Chopra 1308cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 1309cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1310cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 1311cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 1312cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1313cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 1314cee4d264SManish Chopra qed_set_fw_mac_addr(&p_first_filter->mac_msb, 1315cee4d264SManish Chopra &p_first_filter->mac_mid, 1316cee4d264SManish Chopra &p_first_filter->mac_lsb, 1317cee4d264SManish Chopra (u8 *)p_filter_cmd->mac); 1318cee4d264SManish Chopra } 1319cee4d264SManish Chopra 1320cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 1321cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1322cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 1323cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 1324cee4d264SManish Chopra p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 1325cee4d264SManish Chopra 1326cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1327cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 1328cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 1329cee4d264SManish Chopra p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 1330cee4d264SManish Chopra 1331cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 1332cee4d264SManish Chopra p_second_filter->type = p_first_filter->type; 1333cee4d264SManish Chopra p_second_filter->mac_msb = p_first_filter->mac_msb; 1334cee4d264SManish Chopra p_second_filter->mac_mid = p_first_filter->mac_mid; 1335cee4d264SManish Chopra p_second_filter->mac_lsb = p_first_filter->mac_lsb; 1336cee4d264SManish Chopra p_second_filter->vlan_id = p_first_filter->vlan_id; 1337cee4d264SManish Chopra p_second_filter->vni = p_first_filter->vni; 1338cee4d264SManish Chopra 1339cee4d264SManish Chopra p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 1340cee4d264SManish Chopra 1341cee4d264SManish Chopra p_first_filter->vport_id = vport_to_remove_from; 1342cee4d264SManish Chopra 1343cee4d264SManish Chopra p_second_filter->action = ETH_FILTER_ACTION_ADD; 1344cee4d264SManish Chopra p_second_filter->vport_id = vport_to_add_to; 1345fc48b7a6SYuval Mintz } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 1346fc48b7a6SYuval Mintz p_first_filter->vport_id = vport_to_add_to; 1347fc48b7a6SYuval Mintz memcpy(p_second_filter, p_first_filter, 1348fc48b7a6SYuval Mintz sizeof(*p_second_filter)); 1349fc48b7a6SYuval Mintz p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 1350fc48b7a6SYuval Mintz p_second_filter->action = ETH_FILTER_ACTION_ADD; 1351cee4d264SManish Chopra } else { 1352cee4d264SManish Chopra action = qed_filter_action(p_filter_cmd->opcode); 1353cee4d264SManish Chopra 1354cee4d264SManish Chopra if (action == MAX_ETH_FILTER_ACTION) { 1355cee4d264SManish Chopra DP_NOTICE(p_hwfn, 1356cee4d264SManish Chopra "%d is not supported yet\n", 1357cee4d264SManish Chopra p_filter_cmd->opcode); 1358cee4d264SManish Chopra return -EINVAL; 1359cee4d264SManish Chopra } 1360cee4d264SManish Chopra 1361cee4d264SManish Chopra p_first_filter->action = action; 1362cee4d264SManish Chopra p_first_filter->vport_id = (p_filter_cmd->opcode == 1363cee4d264SManish Chopra QED_FILTER_REMOVE) ? 1364cee4d264SManish Chopra vport_to_remove_from : 1365cee4d264SManish Chopra vport_to_add_to; 1366cee4d264SManish Chopra } 1367cee4d264SManish Chopra 1368cee4d264SManish Chopra return 0; 1369cee4d264SManish Chopra } 1370cee4d264SManish Chopra 1371dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 1372cee4d264SManish Chopra u16 opaque_fid, 1373cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1374cee4d264SManish Chopra enum spq_mode comp_mode, 1375cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1376cee4d264SManish Chopra { 1377cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod = NULL; 1378cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 1379cee4d264SManish Chopra struct eth_filter_cmd_header *p_header; 1380cee4d264SManish Chopra int rc; 1381cee4d264SManish Chopra 1382cee4d264SManish Chopra rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1383cee4d264SManish Chopra &p_ramrod, &p_ent, 1384cee4d264SManish Chopra comp_mode, p_comp_data); 13851a635e48SYuval Mintz if (rc) { 1386cee4d264SManish Chopra DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1387cee4d264SManish Chopra return rc; 1388cee4d264SManish Chopra } 1389cee4d264SManish Chopra p_header = &p_ramrod->filter_cmd_hdr; 1390cee4d264SManish Chopra p_header->assert_on_error = p_filter_cmd->assert_on_error; 1391cee4d264SManish Chopra 1392cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 13931a635e48SYuval Mintz if (rc) { 13941a635e48SYuval Mintz DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc); 1395cee4d264SManish Chopra return rc; 1396cee4d264SManish Chopra } 1397cee4d264SManish Chopra 1398cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1399cee4d264SManish Chopra "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1400cee4d264SManish Chopra (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1401cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1402cee4d264SManish Chopra "REMOVE" : 1403cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1404cee4d264SManish Chopra "MOVE" : "REPLACE")), 1405cee4d264SManish Chopra (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1406cee4d264SManish Chopra ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1407cee4d264SManish Chopra "VLAN" : "MAC & VLAN"), 1408cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt, 1409cee4d264SManish Chopra p_filter_cmd->is_rx_filter, 1410cee4d264SManish Chopra p_filter_cmd->is_tx_filter); 1411cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1412cee4d264SManish Chopra "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1413cee4d264SManish Chopra p_filter_cmd->vport_to_add_to, 1414cee4d264SManish Chopra p_filter_cmd->vport_to_remove_from, 1415cee4d264SManish Chopra p_filter_cmd->mac[0], 1416cee4d264SManish Chopra p_filter_cmd->mac[1], 1417cee4d264SManish Chopra p_filter_cmd->mac[2], 1418cee4d264SManish Chopra p_filter_cmd->mac[3], 1419cee4d264SManish Chopra p_filter_cmd->mac[4], 1420cee4d264SManish Chopra p_filter_cmd->mac[5], 1421cee4d264SManish Chopra p_filter_cmd->vlan); 1422cee4d264SManish Chopra 1423cee4d264SManish Chopra return 0; 1424cee4d264SManish Chopra } 1425cee4d264SManish Chopra 1426cee4d264SManish Chopra /******************************************************************************* 1427cee4d264SManish Chopra * Description: 1428cee4d264SManish Chopra * Calculates crc 32 on a buffer 1429cee4d264SManish Chopra * Note: crc32_length MUST be aligned to 8 1430cee4d264SManish Chopra * Return: 1431cee4d264SManish Chopra ******************************************************************************/ 1432cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet, 14331a635e48SYuval Mintz u32 crc32_length, u32 crc32_seed, u8 complement) 1434cee4d264SManish Chopra { 14351a635e48SYuval Mintz u32 byte = 0, bit = 0, crc32_result = crc32_seed; 14361a635e48SYuval Mintz u8 msb = 0, current_byte = 0; 1437cee4d264SManish Chopra 1438cee4d264SManish Chopra if ((!crc32_packet) || 1439cee4d264SManish Chopra (crc32_length == 0) || 1440cee4d264SManish Chopra ((crc32_length % 8) != 0)) 1441cee4d264SManish Chopra return crc32_result; 1442cee4d264SManish Chopra for (byte = 0; byte < crc32_length; byte++) { 1443cee4d264SManish Chopra current_byte = crc32_packet[byte]; 1444cee4d264SManish Chopra for (bit = 0; bit < 8; bit++) { 1445cee4d264SManish Chopra msb = (u8)(crc32_result >> 31); 1446cee4d264SManish Chopra crc32_result = crc32_result << 1; 1447cee4d264SManish Chopra if (msb != (0x1 & (current_byte >> bit))) { 1448cee4d264SManish Chopra crc32_result = crc32_result ^ CRC32_POLY; 1449cee4d264SManish Chopra crc32_result |= 1; /*crc32_result[0] = 1;*/ 1450cee4d264SManish Chopra } 1451cee4d264SManish Chopra } 1452cee4d264SManish Chopra } 1453cee4d264SManish Chopra return crc32_result; 1454cee4d264SManish Chopra } 1455cee4d264SManish Chopra 14561a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len) 1457cee4d264SManish Chopra { 1458cee4d264SManish Chopra u32 packet_buf[2] = { 0 }; 1459cee4d264SManish Chopra 1460cee4d264SManish Chopra memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1461cee4d264SManish Chopra return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1462cee4d264SManish Chopra } 1463cee4d264SManish Chopra 1464dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac) 1465cee4d264SManish Chopra { 1466cee4d264SManish Chopra u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1467cee4d264SManish Chopra mac, ETH_ALEN); 1468cee4d264SManish Chopra 1469cee4d264SManish Chopra return crc & 0xff; 1470cee4d264SManish Chopra } 1471cee4d264SManish Chopra 1472cee4d264SManish Chopra static int 1473cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1474cee4d264SManish Chopra u16 opaque_fid, 1475cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1476cee4d264SManish Chopra enum spq_mode comp_mode, 1477cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1478cee4d264SManish Chopra { 1479cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 148025c020a9SSudarsana Reddy Kalluru u32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1481cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 148206f56b81SYuval Mintz struct qed_sp_init_data init_data; 1483cee4d264SManish Chopra u8 abs_vport_id = 0; 1484cee4d264SManish Chopra int rc, i; 1485cee4d264SManish Chopra 148683aeb933SYuval Mintz if (p_filter_cmd->opcode == QED_FILTER_ADD) 1487cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1488cee4d264SManish Chopra &abs_vport_id); 148983aeb933SYuval Mintz else 1490cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1491cee4d264SManish Chopra &abs_vport_id); 1492cee4d264SManish Chopra if (rc) 1493cee4d264SManish Chopra return rc; 1494cee4d264SManish Chopra 149506f56b81SYuval Mintz /* Get SPQ entry */ 149606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 149706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 149806f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 149906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 150006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1501cee4d264SManish Chopra 1502cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1503cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 150406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1505cee4d264SManish Chopra if (rc) { 1506cee4d264SManish Chopra DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1507cee4d264SManish Chopra return rc; 1508cee4d264SManish Chopra } 1509cee4d264SManish Chopra 1510cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 1511cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 1512cee4d264SManish Chopra 1513cee4d264SManish Chopra /* explicitly clear out the entire vector */ 1514cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 1515cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 151625c020a9SSudarsana Reddy Kalluru memset(bins, 0, sizeof(bins)); 1517cee4d264SManish Chopra /* filter ADD op is explicit set op and it removes 1518cee4d264SManish Chopra * any existing filters for the vport 1519cee4d264SManish Chopra */ 1520cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1521cee4d264SManish Chopra for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 152225c020a9SSudarsana Reddy Kalluru u32 bit, nbits; 1523cee4d264SManish Chopra 1524cee4d264SManish Chopra bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 152525c020a9SSudarsana Reddy Kalluru nbits = sizeof(u32) * BITS_PER_BYTE; 152625c020a9SSudarsana Reddy Kalluru bins[bit / nbits] |= 1 << (bit % nbits); 1527cee4d264SManish Chopra } 1528cee4d264SManish Chopra 1529cee4d264SManish Chopra /* Convert to correct endianity */ 1530cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 15311a635e48SYuval Mintz struct vport_update_ramrod_mcast *p_ramrod_bins; 1532cee4d264SManish Chopra 15331a635e48SYuval Mintz p_ramrod_bins = &p_ramrod->approx_mcast; 153425c020a9SSudarsana Reddy Kalluru p_ramrod_bins->bins[i] = cpu_to_le32(bins[i]); 1535cee4d264SManish Chopra } 1536cee4d264SManish Chopra } 1537cee4d264SManish Chopra 1538cee4d264SManish Chopra p_ramrod->common.vport_id = abs_vport_id; 1539cee4d264SManish Chopra 1540cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1541cee4d264SManish Chopra } 1542cee4d264SManish Chopra 1543dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev, 1544cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1545cee4d264SManish Chopra enum spq_mode comp_mode, 1546cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1547cee4d264SManish Chopra { 1548cee4d264SManish Chopra int rc = 0; 1549cee4d264SManish Chopra int i; 1550cee4d264SManish Chopra 1551cee4d264SManish Chopra /* only ADD and REMOVE operations are supported for multi-cast */ 1552cee4d264SManish Chopra if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1553cee4d264SManish Chopra (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1554cee4d264SManish Chopra (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1555cee4d264SManish Chopra return -EINVAL; 1556cee4d264SManish Chopra 1557cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1558cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1559cee4d264SManish Chopra 1560cee4d264SManish Chopra u16 opaque_fid; 1561cee4d264SManish Chopra 1562dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1563dacd88d6SYuval Mintz qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); 1564dacd88d6SYuval Mintz continue; 1565dacd88d6SYuval Mintz } 1566cee4d264SManish Chopra 1567cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1568cee4d264SManish Chopra 1569cee4d264SManish Chopra rc = qed_sp_eth_filter_mcast(p_hwfn, 1570cee4d264SManish Chopra opaque_fid, 1571cee4d264SManish Chopra p_filter_cmd, 15721a635e48SYuval Mintz comp_mode, p_comp_data); 1573cee4d264SManish Chopra } 1574cee4d264SManish Chopra return rc; 1575cee4d264SManish Chopra } 1576cee4d264SManish Chopra 1577cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1578cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1579cee4d264SManish Chopra enum spq_mode comp_mode, 1580cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1581cee4d264SManish Chopra { 1582cee4d264SManish Chopra int rc = 0; 1583cee4d264SManish Chopra int i; 1584cee4d264SManish Chopra 1585cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1586cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1587cee4d264SManish Chopra u16 opaque_fid; 1588cee4d264SManish Chopra 1589dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1590dacd88d6SYuval Mintz rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); 1591dacd88d6SYuval Mintz continue; 1592dacd88d6SYuval Mintz } 1593cee4d264SManish Chopra 1594cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1595cee4d264SManish Chopra 1596cee4d264SManish Chopra rc = qed_sp_eth_filter_ucast(p_hwfn, 1597cee4d264SManish Chopra opaque_fid, 1598cee4d264SManish Chopra p_filter_cmd, 15991a635e48SYuval Mintz comp_mode, p_comp_data); 16001a635e48SYuval Mintz if (rc) 1601dacd88d6SYuval Mintz break; 1602cee4d264SManish Chopra } 1603cee4d264SManish Chopra 1604cee4d264SManish Chopra return rc; 1605cee4d264SManish Chopra } 1606cee4d264SManish Chopra 160786622ee7SYuval Mintz /* Statistics related code */ 160886622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 160986622ee7SYuval Mintz u32 *p_addr, 1610dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 161186622ee7SYuval Mintz { 1612dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 161386622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_PSDM_RAM + 161486622ee7SYuval Mintz PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 161586622ee7SYuval Mintz *p_len = sizeof(struct eth_pstorm_per_queue_stat); 1616dacd88d6SYuval Mintz } else { 1617dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1618dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1619dacd88d6SYuval Mintz 1620dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.pstats.address; 1621dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.pstats.len; 1622dacd88d6SYuval Mintz } 162386622ee7SYuval Mintz } 162486622ee7SYuval Mintz 162586622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 162686622ee7SYuval Mintz struct qed_ptt *p_ptt, 162786622ee7SYuval Mintz struct qed_eth_stats *p_stats, 162886622ee7SYuval Mintz u16 statistics_bin) 162986622ee7SYuval Mintz { 163086622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 163186622ee7SYuval Mintz u32 pstats_addr = 0, pstats_len = 0; 163286622ee7SYuval Mintz 163386622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 163486622ee7SYuval Mintz statistics_bin); 163586622ee7SYuval Mintz 163686622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 1637dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); 163886622ee7SYuval Mintz 16399c79ddaaSMintz, Yuval p_stats->common.tx_ucast_bytes += 16409c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_bytes); 16419c79ddaaSMintz, Yuval p_stats->common.tx_mcast_bytes += 16429c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_bytes); 16439c79ddaaSMintz, Yuval p_stats->common.tx_bcast_bytes += 16449c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_bytes); 16459c79ddaaSMintz, Yuval p_stats->common.tx_ucast_pkts += 16469c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_pkts); 16479c79ddaaSMintz, Yuval p_stats->common.tx_mcast_pkts += 16489c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_pkts); 16499c79ddaaSMintz, Yuval p_stats->common.tx_bcast_pkts += 16509c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_pkts); 16519c79ddaaSMintz, Yuval p_stats->common.tx_err_drop_pkts += 16529c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.error_drop_pkts); 165386622ee7SYuval Mintz } 165486622ee7SYuval Mintz 165586622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 165686622ee7SYuval Mintz struct qed_ptt *p_ptt, 165786622ee7SYuval Mintz struct qed_eth_stats *p_stats, 165886622ee7SYuval Mintz u16 statistics_bin) 165986622ee7SYuval Mintz { 166086622ee7SYuval Mintz struct tstorm_per_port_stat tstats; 1661dacd88d6SYuval Mintz u32 tstats_addr, tstats_len; 166286622ee7SYuval Mintz 1663dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1664dacd88d6SYuval Mintz tstats_addr = BAR0_MAP_REG_TSDM_RAM + 1665dacd88d6SYuval Mintz TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 1666dacd88d6SYuval Mintz tstats_len = sizeof(struct tstorm_per_port_stat); 1667dacd88d6SYuval Mintz } else { 1668dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1669dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1670dacd88d6SYuval Mintz 1671dacd88d6SYuval Mintz tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; 1672dacd88d6SYuval Mintz tstats_len = p_resp->pfdev_info.stats_info.tstats.len; 1673dacd88d6SYuval Mintz } 167486622ee7SYuval Mintz 167586622ee7SYuval Mintz memset(&tstats, 0, sizeof(tstats)); 1676dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); 167786622ee7SYuval Mintz 16789c79ddaaSMintz, Yuval p_stats->common.mftag_filter_discards += 167986622ee7SYuval Mintz HILO_64_REGPAIR(tstats.mftag_filter_discard); 16809c79ddaaSMintz, Yuval p_stats->common.mac_filter_discards += 168186622ee7SYuval Mintz HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 1682608e00d0SManish Chopra p_stats->common.gft_filter_drop += 1683608e00d0SManish Chopra HILO_64_REGPAIR(tstats.eth_gft_drop_pkt); 168486622ee7SYuval Mintz } 168586622ee7SYuval Mintz 168686622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 168786622ee7SYuval Mintz u32 *p_addr, 1688dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 168986622ee7SYuval Mintz { 1690dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 169186622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_USDM_RAM + 169286622ee7SYuval Mintz USTORM_QUEUE_STAT_OFFSET(statistics_bin); 169386622ee7SYuval Mintz *p_len = sizeof(struct eth_ustorm_per_queue_stat); 1694dacd88d6SYuval Mintz } else { 1695dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1696dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1697dacd88d6SYuval Mintz 1698dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.ustats.address; 1699dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.ustats.len; 1700dacd88d6SYuval Mintz } 170186622ee7SYuval Mintz } 170286622ee7SYuval Mintz 170386622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 170486622ee7SYuval Mintz struct qed_ptt *p_ptt, 170586622ee7SYuval Mintz struct qed_eth_stats *p_stats, 170686622ee7SYuval Mintz u16 statistics_bin) 170786622ee7SYuval Mintz { 170886622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 170986622ee7SYuval Mintz u32 ustats_addr = 0, ustats_len = 0; 171086622ee7SYuval Mintz 171186622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 171286622ee7SYuval Mintz statistics_bin); 171386622ee7SYuval Mintz 171486622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 1715dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); 171686622ee7SYuval Mintz 17179c79ddaaSMintz, Yuval p_stats->common.rx_ucast_bytes += 17189c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 17199c79ddaaSMintz, Yuval p_stats->common.rx_mcast_bytes += 17209c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 17219c79ddaaSMintz, Yuval p_stats->common.rx_bcast_bytes += 17229c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 17239c79ddaaSMintz, Yuval p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 17249c79ddaaSMintz, Yuval p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 17259c79ddaaSMintz, Yuval p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 172686622ee7SYuval Mintz } 172786622ee7SYuval Mintz 172886622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 172986622ee7SYuval Mintz u32 *p_addr, 1730dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 173186622ee7SYuval Mintz { 1732dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 173386622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_MSDM_RAM + 173486622ee7SYuval Mintz MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 173586622ee7SYuval Mintz *p_len = sizeof(struct eth_mstorm_per_queue_stat); 1736dacd88d6SYuval Mintz } else { 1737dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1738dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1739dacd88d6SYuval Mintz 1740dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.mstats.address; 1741dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.mstats.len; 1742dacd88d6SYuval Mintz } 174386622ee7SYuval Mintz } 174486622ee7SYuval Mintz 174586622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 174686622ee7SYuval Mintz struct qed_ptt *p_ptt, 174786622ee7SYuval Mintz struct qed_eth_stats *p_stats, 174886622ee7SYuval Mintz u16 statistics_bin) 174986622ee7SYuval Mintz { 175086622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 175186622ee7SYuval Mintz u32 mstats_addr = 0, mstats_len = 0; 175286622ee7SYuval Mintz 175386622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 175486622ee7SYuval Mintz statistics_bin); 175586622ee7SYuval Mintz 175686622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 1757dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); 175886622ee7SYuval Mintz 17599c79ddaaSMintz, Yuval p_stats->common.no_buff_discards += 17609c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.no_buff_discard); 17619c79ddaaSMintz, Yuval p_stats->common.packet_too_big_discard += 176286622ee7SYuval Mintz HILO_64_REGPAIR(mstats.packet_too_big_discard); 17639c79ddaaSMintz, Yuval p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); 17649c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_pkts += 176586622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 17669c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_events += 176786622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_events); 17689c79ddaaSMintz, Yuval p_stats->common.tpa_aborts_num += 17699c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.tpa_aborts_num); 17709c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_bytes += 177186622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 177286622ee7SYuval Mintz } 177386622ee7SYuval Mintz 177486622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 177586622ee7SYuval Mintz struct qed_ptt *p_ptt, 177686622ee7SYuval Mintz struct qed_eth_stats *p_stats) 177786622ee7SYuval Mintz { 17789c79ddaaSMintz, Yuval struct qed_eth_stats_common *p_common = &p_stats->common; 177986622ee7SYuval Mintz struct port_stats port_stats; 178086622ee7SYuval Mintz int j; 178186622ee7SYuval Mintz 178286622ee7SYuval Mintz memset(&port_stats, 0, sizeof(port_stats)); 178386622ee7SYuval Mintz 178486622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 178586622ee7SYuval Mintz p_hwfn->mcp_info->port_addr + 178686622ee7SYuval Mintz offsetof(struct public_port, stats), 178786622ee7SYuval Mintz sizeof(port_stats)); 178886622ee7SYuval Mintz 17899c79ddaaSMintz, Yuval p_common->rx_64_byte_packets += port_stats.eth.r64; 17909c79ddaaSMintz, Yuval p_common->rx_65_to_127_byte_packets += port_stats.eth.r127; 17919c79ddaaSMintz, Yuval p_common->rx_128_to_255_byte_packets += port_stats.eth.r255; 17929c79ddaaSMintz, Yuval p_common->rx_256_to_511_byte_packets += port_stats.eth.r511; 17939c79ddaaSMintz, Yuval p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023; 17949c79ddaaSMintz, Yuval p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; 17959c79ddaaSMintz, Yuval p_common->rx_crc_errors += port_stats.eth.rfcs; 17969c79ddaaSMintz, Yuval p_common->rx_mac_crtl_frames += port_stats.eth.rxcf; 17979c79ddaaSMintz, Yuval p_common->rx_pause_frames += port_stats.eth.rxpf; 17989c79ddaaSMintz, Yuval p_common->rx_pfc_frames += port_stats.eth.rxpp; 17999c79ddaaSMintz, Yuval p_common->rx_align_errors += port_stats.eth.raln; 18009c79ddaaSMintz, Yuval p_common->rx_carrier_errors += port_stats.eth.rfcr; 18019c79ddaaSMintz, Yuval p_common->rx_oversize_packets += port_stats.eth.rovr; 18029c79ddaaSMintz, Yuval p_common->rx_jabbers += port_stats.eth.rjbr; 18039c79ddaaSMintz, Yuval p_common->rx_undersize_packets += port_stats.eth.rund; 18049c79ddaaSMintz, Yuval p_common->rx_fragments += port_stats.eth.rfrg; 18059c79ddaaSMintz, Yuval p_common->tx_64_byte_packets += port_stats.eth.t64; 18069c79ddaaSMintz, Yuval p_common->tx_65_to_127_byte_packets += port_stats.eth.t127; 18079c79ddaaSMintz, Yuval p_common->tx_128_to_255_byte_packets += port_stats.eth.t255; 18089c79ddaaSMintz, Yuval p_common->tx_256_to_511_byte_packets += port_stats.eth.t511; 18099c79ddaaSMintz, Yuval p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023; 18109c79ddaaSMintz, Yuval p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; 18119c79ddaaSMintz, Yuval p_common->tx_pause_frames += port_stats.eth.txpf; 18129c79ddaaSMintz, Yuval p_common->tx_pfc_frames += port_stats.eth.txpp; 18139c79ddaaSMintz, Yuval p_common->rx_mac_bytes += port_stats.eth.rbyte; 18149c79ddaaSMintz, Yuval p_common->rx_mac_uc_packets += port_stats.eth.rxuca; 18159c79ddaaSMintz, Yuval p_common->rx_mac_mc_packets += port_stats.eth.rxmca; 18169c79ddaaSMintz, Yuval p_common->rx_mac_bc_packets += port_stats.eth.rxbca; 18179c79ddaaSMintz, Yuval p_common->rx_mac_frames_ok += port_stats.eth.rxpok; 18189c79ddaaSMintz, Yuval p_common->tx_mac_bytes += port_stats.eth.tbyte; 18199c79ddaaSMintz, Yuval p_common->tx_mac_uc_packets += port_stats.eth.txuca; 18209c79ddaaSMintz, Yuval p_common->tx_mac_mc_packets += port_stats.eth.txmca; 18219c79ddaaSMintz, Yuval p_common->tx_mac_bc_packets += port_stats.eth.txbca; 18229c79ddaaSMintz, Yuval p_common->tx_mac_ctrl_frames += port_stats.eth.txcf; 182386622ee7SYuval Mintz for (j = 0; j < 8; j++) { 18249c79ddaaSMintz, Yuval p_common->brb_truncates += port_stats.brb.brb_truncate[j]; 18259c79ddaaSMintz, Yuval p_common->brb_discards += port_stats.brb.brb_discard[j]; 18269c79ddaaSMintz, Yuval } 18279c79ddaaSMintz, Yuval 18289c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) { 18299c79ddaaSMintz, Yuval struct qed_eth_stats_bb *p_bb = &p_stats->bb; 18309c79ddaaSMintz, Yuval 18319c79ddaaSMintz, Yuval p_bb->rx_1519_to_1522_byte_packets += 18329c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r1522; 18339c79ddaaSMintz, Yuval p_bb->rx_1519_to_2047_byte_packets += 18349c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r2047; 18359c79ddaaSMintz, Yuval p_bb->rx_2048_to_4095_byte_packets += 18369c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r4095; 18379c79ddaaSMintz, Yuval p_bb->rx_4096_to_9216_byte_packets += 18389c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r9216; 18399c79ddaaSMintz, Yuval p_bb->rx_9217_to_16383_byte_packets += 18409c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r16383; 18419c79ddaaSMintz, Yuval p_bb->tx_1519_to_2047_byte_packets += 18429c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t2047; 18439c79ddaaSMintz, Yuval p_bb->tx_2048_to_4095_byte_packets += 18449c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t4095; 18459c79ddaaSMintz, Yuval p_bb->tx_4096_to_9216_byte_packets += 18469c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t9216; 18479c79ddaaSMintz, Yuval p_bb->tx_9217_to_16383_byte_packets += 18489c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t16383; 18499c79ddaaSMintz, Yuval p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec; 18509c79ddaaSMintz, Yuval p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl; 18519c79ddaaSMintz, Yuval } else { 18529c79ddaaSMintz, Yuval struct qed_eth_stats_ah *p_ah = &p_stats->ah; 18539c79ddaaSMintz, Yuval 18549c79ddaaSMintz, Yuval p_ah->rx_1519_to_max_byte_packets += 18559c79ddaaSMintz, Yuval port_stats.eth.u0.ah0.r1519_to_max; 18569c79ddaaSMintz, Yuval p_ah->tx_1519_to_max_byte_packets = 18579c79ddaaSMintz, Yuval port_stats.eth.u1.ah1.t1519_to_max; 185886622ee7SYuval Mintz } 185932d26a68SSudarsana Reddy Kalluru 186032d26a68SSudarsana Reddy Kalluru p_common->link_change_count = qed_rd(p_hwfn, p_ptt, 186132d26a68SSudarsana Reddy Kalluru p_hwfn->mcp_info->port_addr + 186232d26a68SSudarsana Reddy Kalluru offsetof(struct public_port, 186332d26a68SSudarsana Reddy Kalluru link_change_count)); 186486622ee7SYuval Mintz } 186586622ee7SYuval Mintz 186686622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 186786622ee7SYuval Mintz struct qed_ptt *p_ptt, 186886622ee7SYuval Mintz struct qed_eth_stats *stats, 1869dacd88d6SYuval Mintz u16 statistics_bin, bool b_get_port_stats) 187086622ee7SYuval Mintz { 187186622ee7SYuval Mintz __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 187286622ee7SYuval Mintz __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 187386622ee7SYuval Mintz __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 187486622ee7SYuval Mintz __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 187586622ee7SYuval Mintz 1876dacd88d6SYuval Mintz if (b_get_port_stats && p_hwfn->mcp_info) 187786622ee7SYuval Mintz __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 187886622ee7SYuval Mintz } 187986622ee7SYuval Mintz 188086622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev, 188186622ee7SYuval Mintz struct qed_eth_stats *stats) 188286622ee7SYuval Mintz { 188386622ee7SYuval Mintz u8 fw_vport = 0; 188486622ee7SYuval Mintz int i; 188586622ee7SYuval Mintz 188686622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 188786622ee7SYuval Mintz 188886622ee7SYuval Mintz for_each_hwfn(cdev, i) { 188986622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1890dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1891dacd88d6SYuval Mintz : NULL; 189286622ee7SYuval Mintz 1893dacd88d6SYuval Mintz if (IS_PF(cdev)) { 189486622ee7SYuval Mintz /* The main vport index is relative first */ 189586622ee7SYuval Mintz if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 189686622ee7SYuval Mintz DP_ERR(p_hwfn, "No vport available!\n"); 1897dacd88d6SYuval Mintz goto out; 1898dacd88d6SYuval Mintz } 189986622ee7SYuval Mintz } 190086622ee7SYuval Mintz 1901dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 190286622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 190386622ee7SYuval Mintz continue; 190486622ee7SYuval Mintz } 190586622ee7SYuval Mintz 1906dacd88d6SYuval Mintz __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, 1907dacd88d6SYuval Mintz IS_PF(cdev) ? true : false); 190886622ee7SYuval Mintz 1909dacd88d6SYuval Mintz out: 1910dacd88d6SYuval Mintz if (IS_PF(cdev) && p_ptt) 191186622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 191286622ee7SYuval Mintz } 191386622ee7SYuval Mintz } 191486622ee7SYuval Mintz 19151a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats) 191686622ee7SYuval Mintz { 191786622ee7SYuval Mintz u32 i; 191886622ee7SYuval Mintz 191986622ee7SYuval Mintz if (!cdev) { 192086622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 192186622ee7SYuval Mintz return; 192286622ee7SYuval Mintz } 192386622ee7SYuval Mintz 192486622ee7SYuval Mintz _qed_get_vport_stats(cdev, stats); 192586622ee7SYuval Mintz 192686622ee7SYuval Mintz if (!cdev->reset_stats) 192786622ee7SYuval Mintz return; 192886622ee7SYuval Mintz 192986622ee7SYuval Mintz /* Reduce the statistics baseline */ 193086622ee7SYuval Mintz for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 193186622ee7SYuval Mintz ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 193286622ee7SYuval Mintz } 193386622ee7SYuval Mintz 193486622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 193586622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev) 193686622ee7SYuval Mintz { 193786622ee7SYuval Mintz int i; 193886622ee7SYuval Mintz 193986622ee7SYuval Mintz for_each_hwfn(cdev, i) { 194086622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 194186622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 194286622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 194386622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 1944dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1945dacd88d6SYuval Mintz : NULL; 194686622ee7SYuval Mintz u32 addr = 0, len = 0; 194786622ee7SYuval Mintz 1948dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 194986622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 195086622ee7SYuval Mintz continue; 195186622ee7SYuval Mintz } 195286622ee7SYuval Mintz 195386622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 195486622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 195586622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 195686622ee7SYuval Mintz 195786622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 195886622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 195986622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 196086622ee7SYuval Mintz 196186622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 196286622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 196386622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 196486622ee7SYuval Mintz 1965dacd88d6SYuval Mintz if (IS_PF(cdev)) 196686622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 196786622ee7SYuval Mintz } 196886622ee7SYuval Mintz 196986622ee7SYuval Mintz /* PORT statistics are not necessarily reset, so we need to 197086622ee7SYuval Mintz * read and create a baseline for future statistics. 197132d26a68SSudarsana Reddy Kalluru * Link change stat is maintained by MFW, return its value as is. 197286622ee7SYuval Mintz */ 197332d26a68SSudarsana Reddy Kalluru if (!cdev->reset_stats) { 197486622ee7SYuval Mintz DP_INFO(cdev, "Reset stats not allocated\n"); 197532d26a68SSudarsana Reddy Kalluru } else { 197686622ee7SYuval Mintz _qed_get_vport_stats(cdev, cdev->reset_stats); 197732d26a68SSudarsana Reddy Kalluru cdev->reset_stats->common.link_change_count = 0; 197832d26a68SSudarsana Reddy Kalluru } 197986622ee7SYuval Mintz } 198086622ee7SYuval Mintz 1981da090917STomer Tayar static enum gft_profile_type 1982da090917STomer Tayar qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode) 1983da090917STomer Tayar { 1984da090917STomer Tayar if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE) 1985da090917STomer Tayar return GFT_PROFILE_TYPE_4_TUPLE; 1986da090917STomer Tayar if (mode == QED_FILTER_CONFIG_MODE_IP_DEST) 198750bc60cbSMichal Kalderon return GFT_PROFILE_TYPE_IP_DST_ADDR; 19883893fc62SManish Chopra if (mode == QED_FILTER_CONFIG_MODE_IP_SRC) 19893893fc62SManish Chopra return GFT_PROFILE_TYPE_IP_SRC_ADDR; 1990da090917STomer Tayar return GFT_PROFILE_TYPE_L4_DST_PORT; 1991da090917STomer Tayar } 1992da090917STomer Tayar 1993da090917STomer Tayar void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, 1994da090917STomer Tayar struct qed_ptt *p_ptt, 1995d51e4af5SChopra, Manish struct qed_arfs_config_params *p_cfg_params) 1996d51e4af5SChopra, Manish { 1997da090917STomer Tayar if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) { 1998da090917STomer Tayar qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 1999da090917STomer Tayar p_cfg_params->tcp, 2000da090917STomer Tayar p_cfg_params->udp, 2001da090917STomer Tayar p_cfg_params->ipv4, 2002da090917STomer Tayar p_cfg_params->ipv6, 2003da090917STomer Tayar qed_arfs_mode_to_hsi(p_cfg_params->mode)); 2004da090917STomer Tayar DP_VERBOSE(p_hwfn, 2005da090917STomer Tayar QED_MSG_SP, 2006da090917STomer Tayar "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n", 2007d51e4af5SChopra, Manish p_cfg_params->tcp ? "Enable" : "Disable", 2008d51e4af5SChopra, Manish p_cfg_params->udp ? "Enable" : "Disable", 2009d51e4af5SChopra, Manish p_cfg_params->ipv4 ? "Enable" : "Disable", 2010da090917STomer Tayar p_cfg_params->ipv6 ? "Enable" : "Disable", 2011da090917STomer Tayar (u32)p_cfg_params->mode); 2012d51e4af5SChopra, Manish } else { 2013da090917STomer Tayar DP_VERBOSE(p_hwfn, QED_MSG_SP, "Disabled Filtering\n"); 2014da090917STomer Tayar qed_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2015da090917STomer Tayar } 2016d51e4af5SChopra, Manish } 2017d51e4af5SChopra, Manish 2018da090917STomer Tayar int 2019da090917STomer Tayar qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, 2020d51e4af5SChopra, Manish struct qed_spq_comp_cb *p_cb, 2021da090917STomer Tayar struct qed_ntuple_filter_params *p_params) 2022d51e4af5SChopra, Manish { 2023d51e4af5SChopra, Manish struct rx_update_gft_filter_data *p_ramrod = NULL; 2024d51e4af5SChopra, Manish struct qed_spq_entry *p_ent = NULL; 2025d51e4af5SChopra, Manish struct qed_sp_init_data init_data; 2026d51e4af5SChopra, Manish u16 abs_rx_q_id = 0; 2027d51e4af5SChopra, Manish u8 abs_vport_id = 0; 2028d51e4af5SChopra, Manish int rc = -EINVAL; 2029d51e4af5SChopra, Manish 2030d51e4af5SChopra, Manish /* Get SPQ entry */ 2031d51e4af5SChopra, Manish memset(&init_data, 0, sizeof(init_data)); 2032d51e4af5SChopra, Manish init_data.cid = qed_spq_get_cid(p_hwfn); 2033d51e4af5SChopra, Manish 2034d51e4af5SChopra, Manish init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2035d51e4af5SChopra, Manish 2036d51e4af5SChopra, Manish if (p_cb) { 2037d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_CB; 2038d51e4af5SChopra, Manish init_data.p_comp_data = p_cb; 2039d51e4af5SChopra, Manish } else { 2040d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2041d51e4af5SChopra, Manish } 2042d51e4af5SChopra, Manish 2043d51e4af5SChopra, Manish rc = qed_sp_init_request(p_hwfn, &p_ent, 2044d51e4af5SChopra, Manish ETH_RAMROD_GFT_UPDATE_FILTER, 2045d51e4af5SChopra, Manish PROTOCOLID_ETH, &init_data); 2046d51e4af5SChopra, Manish if (rc) 2047d51e4af5SChopra, Manish return rc; 2048d51e4af5SChopra, Manish 2049d51e4af5SChopra, Manish p_ramrod = &p_ent->ramrod.rx_update_gft; 2050da090917STomer Tayar 2051da090917STomer Tayar DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr); 2052da090917STomer Tayar p_ramrod->pkt_hdr_length = cpu_to_le16(p_params->length); 2053da090917STomer Tayar 2054608e00d0SManish Chopra if (p_params->b_is_drop) { 2055608e00d0SManish Chopra p_ramrod->vport_id = cpu_to_le16(ETH_GFT_TRASHCAN_VPORT); 2056608e00d0SManish Chopra } else { 2057608e00d0SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 2058608e00d0SManish Chopra if (rc) 2059608e00d0SManish Chopra return rc; 2060608e00d0SManish Chopra 2061da090917STomer Tayar if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) { 2062608e00d0SManish Chopra rc = qed_fw_l2_queue(p_hwfn, p_params->qid, 2063608e00d0SManish Chopra &abs_rx_q_id); 2064608e00d0SManish Chopra if (rc) 2065608e00d0SManish Chopra return rc; 2066608e00d0SManish Chopra 2067da090917STomer Tayar p_ramrod->rx_qid_valid = 1; 2068da090917STomer Tayar p_ramrod->rx_qid = cpu_to_le16(abs_rx_q_id); 2069da090917STomer Tayar } 2070da090917STomer Tayar 2071608e00d0SManish Chopra p_ramrod->vport_id = cpu_to_le16((u16)abs_vport_id); 2072608e00d0SManish Chopra } 2073608e00d0SManish Chopra 2074da090917STomer Tayar p_ramrod->flow_id_valid = 0; 2075da090917STomer Tayar p_ramrod->flow_id = 0; 2076da090917STomer Tayar p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER 2077da090917STomer Tayar : GFT_DELETE_FILTER; 2078d51e4af5SChopra, Manish 2079d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, 2080d51e4af5SChopra, Manish "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n", 2081d51e4af5SChopra, Manish abs_vport_id, abs_rx_q_id, 2082da090917STomer Tayar p_params->b_is_add ? "Adding" : "Removing", 2083da090917STomer Tayar (u64)p_params->addr, p_params->length); 2084d51e4af5SChopra, Manish 2085d51e4af5SChopra, Manish return qed_spq_post(p_hwfn, p_ent, NULL); 2086d51e4af5SChopra, Manish } 2087d51e4af5SChopra, Manish 2088bf5a94bfSRahul Verma int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn, 2089bf5a94bfSRahul Verma struct qed_ptt *p_ptt, 2090bf5a94bfSRahul Verma struct qed_queue_cid *p_cid, u16 *p_rx_coal) 2091bf5a94bfSRahul Verma { 2092bf5a94bfSRahul Verma u32 coalesce, address, is_valid; 2093bf5a94bfSRahul Verma struct cau_sb_entry sb_entry; 2094bf5a94bfSRahul Verma u8 timer_res; 2095bf5a94bfSRahul Verma int rc; 2096bf5a94bfSRahul Verma 2097bf5a94bfSRahul Verma rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2098bf5a94bfSRahul Verma p_cid->sb_igu_id * sizeof(u64), 2099bf5a94bfSRahul Verma (u64)(uintptr_t)&sb_entry, 2, 0); 2100bf5a94bfSRahul Verma if (rc) { 2101bf5a94bfSRahul Verma DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2102bf5a94bfSRahul Verma return rc; 2103bf5a94bfSRahul Verma } 2104bf5a94bfSRahul Verma 2105bf5a94bfSRahul Verma timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0); 2106bf5a94bfSRahul Verma 2107bf5a94bfSRahul Verma address = BAR0_MAP_REG_USDM_RAM + 2108bf5a94bfSRahul Verma USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 2109bf5a94bfSRahul Verma coalesce = qed_rd(p_hwfn, p_ptt, address); 2110bf5a94bfSRahul Verma 2111bf5a94bfSRahul Verma is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); 2112bf5a94bfSRahul Verma if (!is_valid) 2113bf5a94bfSRahul Verma return -EINVAL; 2114bf5a94bfSRahul Verma 2115bf5a94bfSRahul Verma coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); 2116bf5a94bfSRahul Verma *p_rx_coal = (u16)(coalesce << timer_res); 2117bf5a94bfSRahul Verma 2118bf5a94bfSRahul Verma return 0; 2119bf5a94bfSRahul Verma } 2120bf5a94bfSRahul Verma 2121bf5a94bfSRahul Verma int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn, 2122bf5a94bfSRahul Verma struct qed_ptt *p_ptt, 2123bf5a94bfSRahul Verma struct qed_queue_cid *p_cid, u16 *p_tx_coal) 2124bf5a94bfSRahul Verma { 2125bf5a94bfSRahul Verma u32 coalesce, address, is_valid; 2126bf5a94bfSRahul Verma struct cau_sb_entry sb_entry; 2127bf5a94bfSRahul Verma u8 timer_res; 2128bf5a94bfSRahul Verma int rc; 2129bf5a94bfSRahul Verma 2130bf5a94bfSRahul Verma rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2131bf5a94bfSRahul Verma p_cid->sb_igu_id * sizeof(u64), 2132bf5a94bfSRahul Verma (u64)(uintptr_t)&sb_entry, 2, 0); 2133bf5a94bfSRahul Verma if (rc) { 2134bf5a94bfSRahul Verma DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2135bf5a94bfSRahul Verma return rc; 2136bf5a94bfSRahul Verma } 2137bf5a94bfSRahul Verma 2138bf5a94bfSRahul Verma timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1); 2139bf5a94bfSRahul Verma 2140bf5a94bfSRahul Verma address = BAR0_MAP_REG_XSDM_RAM + 2141bf5a94bfSRahul Verma XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 2142bf5a94bfSRahul Verma coalesce = qed_rd(p_hwfn, p_ptt, address); 2143bf5a94bfSRahul Verma 2144bf5a94bfSRahul Verma is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); 2145bf5a94bfSRahul Verma if (!is_valid) 2146bf5a94bfSRahul Verma return -EINVAL; 2147bf5a94bfSRahul Verma 2148bf5a94bfSRahul Verma coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); 2149bf5a94bfSRahul Verma *p_tx_coal = (u16)(coalesce << timer_res); 2150bf5a94bfSRahul Verma 2151bf5a94bfSRahul Verma return 0; 2152bf5a94bfSRahul Verma } 2153bf5a94bfSRahul Verma 2154bf5a94bfSRahul Verma int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle) 2155bf5a94bfSRahul Verma { 2156bf5a94bfSRahul Verma struct qed_queue_cid *p_cid = handle; 2157bf5a94bfSRahul Verma struct qed_ptt *p_ptt; 2158bf5a94bfSRahul Verma int rc = 0; 2159bf5a94bfSRahul Verma 2160bf5a94bfSRahul Verma if (IS_VF(p_hwfn->cdev)) { 2161bf5a94bfSRahul Verma rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid); 2162bf5a94bfSRahul Verma if (rc) 2163bf5a94bfSRahul Verma DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n"); 2164bf5a94bfSRahul Verma 2165bf5a94bfSRahul Verma return rc; 2166bf5a94bfSRahul Verma } 2167bf5a94bfSRahul Verma 2168bf5a94bfSRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 2169bf5a94bfSRahul Verma if (!p_ptt) 2170bf5a94bfSRahul Verma return -EAGAIN; 2171bf5a94bfSRahul Verma 2172bf5a94bfSRahul Verma if (p_cid->b_is_rx) { 2173bf5a94bfSRahul Verma rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); 2174bf5a94bfSRahul Verma if (rc) 2175bf5a94bfSRahul Verma goto out; 2176bf5a94bfSRahul Verma } else { 2177bf5a94bfSRahul Verma rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); 2178bf5a94bfSRahul Verma if (rc) 2179bf5a94bfSRahul Verma goto out; 2180bf5a94bfSRahul Verma } 2181bf5a94bfSRahul Verma 2182bf5a94bfSRahul Verma out: 2183bf5a94bfSRahul Verma qed_ptt_release(p_hwfn, p_ptt); 2184bf5a94bfSRahul Verma 2185bf5a94bfSRahul Verma return rc; 2186bf5a94bfSRahul Verma } 2187bf5a94bfSRahul Verma 218825c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev, 218925c089d7SYuval Mintz struct qed_dev_eth_info *info) 219025c089d7SYuval Mintz { 219125c089d7SYuval Mintz int i; 219225c089d7SYuval Mintz 219325c089d7SYuval Mintz memset(info, 0, sizeof(*info)); 219425c089d7SYuval Mintz 219525c089d7SYuval Mintz info->num_tc = 1; 219625c089d7SYuval Mintz 21971408cc1fSYuval Mintz if (IS_PF(cdev)) { 219825eb8d46SYuval Mintz int max_vf_vlan_filters = 0; 21997b7e70f9SYuval Mintz int max_vf_mac_filters = 0; 220025eb8d46SYuval Mintz 220125c089d7SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 2202e1d32acbSMintz, Yuval u16 num_queues = 0; 2203e1d32acbSMintz, Yuval 2204e1d32acbSMintz, Yuval /* Since the feature controls only queue-zones, 2205e1d32acbSMintz, Yuval * make sure we have the contexts [rx, tx, xdp] to 2206e1d32acbSMintz, Yuval * match. 2207e1d32acbSMintz, Yuval */ 2208e1d32acbSMintz, Yuval for_each_hwfn(cdev, i) { 2209e1d32acbSMintz, Yuval struct qed_hwfn *hwfn = &cdev->hwfns[i]; 2210e1d32acbSMintz, Yuval u16 l2_queues = (u16)FEAT_NUM(hwfn, 2211e1d32acbSMintz, Yuval QED_PF_L2_QUE); 2212e1d32acbSMintz, Yuval u16 cids; 2213e1d32acbSMintz, Yuval 2214e1d32acbSMintz, Yuval cids = hwfn->pf_params.eth_pf_params.num_cons; 2215e1d32acbSMintz, Yuval num_queues += min_t(u16, l2_queues, cids / 3); 2216e1d32acbSMintz, Yuval } 2217e1d32acbSMintz, Yuval 2218e1d32acbSMintz, Yuval /* queues might theoretically be >256, but interrupts' 2219e1d32acbSMintz, Yuval * upper-limit guarantes that it would fit in a u8. 2220e1d32acbSMintz, Yuval */ 2221e1d32acbSMintz, Yuval if (cdev->int_params.fp_msix_cnt) { 2222e1d32acbSMintz, Yuval u8 irqs = cdev->int_params.fp_msix_cnt; 2223e1d32acbSMintz, Yuval 2224e1d32acbSMintz, Yuval info->num_queues = (u8)min_t(u16, 2225e1d32acbSMintz, Yuval num_queues, irqs); 2226e1d32acbSMintz, Yuval } 222725c089d7SYuval Mintz } else { 222825c089d7SYuval Mintz info->num_queues = cdev->num_hwfns; 222925c089d7SYuval Mintz } 223025c089d7SYuval Mintz 22317b7e70f9SYuval Mintz if (IS_QED_SRIOV(cdev)) { 223225eb8d46SYuval Mintz max_vf_vlan_filters = cdev->p_iov_info->total_vfs * 223325eb8d46SYuval Mintz QED_ETH_VF_NUM_VLAN_FILTERS; 22347b7e70f9SYuval Mintz max_vf_mac_filters = cdev->p_iov_info->total_vfs * 22357b7e70f9SYuval Mintz QED_ETH_VF_NUM_MAC_FILTERS; 22367b7e70f9SYuval Mintz } 22377b7e70f9SYuval Mintz info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 22387b7e70f9SYuval Mintz QED_VLAN) - 223925eb8d46SYuval Mintz max_vf_vlan_filters; 22407b7e70f9SYuval Mintz info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 22417b7e70f9SYuval Mintz QED_MAC) - 22427b7e70f9SYuval Mintz max_vf_mac_filters; 224325eb8d46SYuval Mintz 224425c089d7SYuval Mintz ether_addr_copy(info->port_mac, 224525c089d7SYuval Mintz cdev->hwfns[0].hw_info.hw_mac_addr); 22461408cc1fSYuval Mintz 2247cbb8a12cSMintz, Yuval info->xdp_supported = true; 2248cbb8a12cSMintz, Yuval } else { 2249cbb8a12cSMintz, Yuval u16 total_cids = 0; 2250cbb8a12cSMintz, Yuval 2251cbb8a12cSMintz, Yuval /* Determine queues & XDP support */ 2252cbb8a12cSMintz, Yuval for_each_hwfn(cdev, i) { 2253cbb8a12cSMintz, Yuval struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2254cbb8a12cSMintz, Yuval u8 queues, cids; 2255cbb8a12cSMintz, Yuval 2256cbb8a12cSMintz, Yuval qed_vf_get_num_cids(p_hwfn, &cids); 2257cbb8a12cSMintz, Yuval qed_vf_get_num_rxqs(p_hwfn, &queues); 22581408cc1fSYuval Mintz info->num_queues += queues; 2259cbb8a12cSMintz, Yuval total_cids += cids; 22601408cc1fSYuval Mintz } 22611408cc1fSYuval Mintz 2262cbb8a12cSMintz, Yuval /* Enable VF XDP in case PF guarntees sufficient connections */ 2263cbb8a12cSMintz, Yuval if (total_cids >= info->num_queues * 3) 2264cbb8a12cSMintz, Yuval info->xdp_supported = true; 2265cbb8a12cSMintz, Yuval 22661408cc1fSYuval Mintz qed_vf_get_num_vlan_filters(&cdev->hwfns[0], 22672edbff8dSTomer Tayar (u8 *)&info->num_vlan_filters); 2268b0fca312SMintz, Yuval qed_vf_get_num_mac_filters(&cdev->hwfns[0], 2269b0fca312SMintz, Yuval (u8 *)&info->num_mac_filters); 22701408cc1fSYuval Mintz qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); 2271d8c2c7e3SYuval Mintz 2272d8c2c7e3SYuval Mintz info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi; 22731408cc1fSYuval Mintz } 227425c089d7SYuval Mintz 227525c089d7SYuval Mintz qed_fill_dev_info(cdev, &info->common); 227625c089d7SYuval Mintz 22771408cc1fSYuval Mintz if (IS_VF(cdev)) 22780ee28e31SShyam Saini eth_zero_addr(info->common.hw_mac); 22791408cc1fSYuval Mintz 228025c089d7SYuval Mintz return 0; 228125c089d7SYuval Mintz } 228225c089d7SYuval Mintz 2283cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev, 22841408cc1fSYuval Mintz struct qed_eth_cb_ops *ops, void *cookie) 2285cc875c2eSYuval Mintz { 2286cc875c2eSYuval Mintz cdev->protocol_ops.eth = ops; 2287cc875c2eSYuval Mintz cdev->ops_cookie = cookie; 22881408cc1fSYuval Mintz 22891408cc1fSYuval Mintz /* For VF, we start bulletin reading */ 22901408cc1fSYuval Mintz if (IS_VF(cdev)) 22911408cc1fSYuval Mintz qed_vf_start_iov_wq(cdev); 2292cc875c2eSYuval Mintz } 2293cc875c2eSYuval Mintz 2294eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) 2295eff16960SYuval Mintz { 2296eff16960SYuval Mintz if (IS_PF(cdev)) 2297eff16960SYuval Mintz return true; 2298eff16960SYuval Mintz 2299eff16960SYuval Mintz return qed_vf_check_mac(&cdev->hwfns[0], mac); 2300eff16960SYuval Mintz } 2301eff16960SYuval Mintz 2302cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev, 2303088c8618SManish Chopra struct qed_start_vport_params *params) 2304cee4d264SManish Chopra { 2305cee4d264SManish Chopra int rc, i; 2306cee4d264SManish Chopra 2307cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2308088c8618SManish Chopra struct qed_sp_vport_start_params start = { 0 }; 2309cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2310cee4d264SManish Chopra 2311088c8618SManish Chopra start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : 2312088c8618SManish Chopra QED_TPA_MODE_NONE; 2313088c8618SManish Chopra start.remove_inner_vlan = params->remove_inner_vlan; 231408feecd7SYuval Mintz start.only_untagged = true; /* untagged only */ 2315088c8618SManish Chopra start.drop_ttl0 = params->drop_ttl0; 2316088c8618SManish Chopra start.opaque_fid = p_hwfn->hw_info.opaque_fid; 2317088c8618SManish Chopra start.concrete_fid = p_hwfn->hw_info.concrete_fid; 2318c78c70faSSudarsana Reddy Kalluru start.handle_ptp_pkts = params->handle_ptp_pkts; 2319088c8618SManish Chopra start.vport_id = params->vport_id; 2320088c8618SManish Chopra start.max_buffers_per_cqe = 16; 2321088c8618SManish Chopra start.mtu = params->mtu; 2322cee4d264SManish Chopra 2323088c8618SManish Chopra rc = qed_sp_vport_start(p_hwfn, &start); 2324cee4d264SManish Chopra if (rc) { 2325cee4d264SManish Chopra DP_ERR(cdev, "Failed to start VPORT\n"); 2326cee4d264SManish Chopra return rc; 2327cee4d264SManish Chopra } 2328cee4d264SManish Chopra 232915582962SRahul Verma rc = qed_hw_start_fastpath(p_hwfn); 233015582962SRahul Verma if (rc) { 233115582962SRahul Verma DP_ERR(cdev, "Failed to start VPORT fastpath\n"); 233215582962SRahul Verma return rc; 233315582962SRahul Verma } 2334cee4d264SManish Chopra 2335cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2336cee4d264SManish Chopra "Started V-PORT %d with MTU %d\n", 2337088c8618SManish Chopra start.vport_id, start.mtu); 2338cee4d264SManish Chopra } 2339cee4d264SManish Chopra 2340a0d26d5aSYuval Mintz if (params->clear_stats) 23419df2ed04SManish Chopra qed_reset_vport_stats(cdev); 23429df2ed04SManish Chopra 2343cee4d264SManish Chopra return 0; 2344cee4d264SManish Chopra } 2345cee4d264SManish Chopra 23461a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id) 2347cee4d264SManish Chopra { 2348cee4d264SManish Chopra int rc, i; 2349cee4d264SManish Chopra 2350cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2351cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2352cee4d264SManish Chopra 2353cee4d264SManish Chopra rc = qed_sp_vport_stop(p_hwfn, 23541a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid, vport_id); 2355cee4d264SManish Chopra 2356cee4d264SManish Chopra if (rc) { 2357cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop VPORT\n"); 2358cee4d264SManish Chopra return rc; 2359cee4d264SManish Chopra } 2360cee4d264SManish Chopra } 2361cee4d264SManish Chopra return 0; 2362cee4d264SManish Chopra } 2363cee4d264SManish Chopra 2364f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev, 2365f29ffdb6SMintz, Yuval struct qed_update_vport_rss_params *input, 2366f29ffdb6SMintz, Yuval struct qed_rss_params *rss) 2367f29ffdb6SMintz, Yuval { 2368f29ffdb6SMintz, Yuval int i, fn; 2369f29ffdb6SMintz, Yuval 2370f29ffdb6SMintz, Yuval /* Update configuration with what's correct regardless of CMT */ 2371f29ffdb6SMintz, Yuval rss->update_rss_config = 1; 2372f29ffdb6SMintz, Yuval rss->rss_enable = 1; 2373f29ffdb6SMintz, Yuval rss->update_rss_capabilities = 1; 2374f29ffdb6SMintz, Yuval rss->update_rss_ind_table = 1; 2375f29ffdb6SMintz, Yuval rss->update_rss_key = 1; 2376f29ffdb6SMintz, Yuval rss->rss_caps = input->rss_caps; 2377f29ffdb6SMintz, Yuval memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32)); 2378f29ffdb6SMintz, Yuval 2379f29ffdb6SMintz, Yuval /* In regular scenario, we'd simply need to take input handlers. 2380f29ffdb6SMintz, Yuval * But in CMT, we'd have to split the handlers according to the 2381f29ffdb6SMintz, Yuval * engine they were configured on. We'd then have to understand 2382f29ffdb6SMintz, Yuval * whether RSS is really required, since 2-queues on CMT doesn't 2383f29ffdb6SMintz, Yuval * require RSS. 2384f29ffdb6SMintz, Yuval */ 2385f29ffdb6SMintz, Yuval if (cdev->num_hwfns == 1) { 2386f29ffdb6SMintz, Yuval memcpy(rss->rss_ind_table, 2387f29ffdb6SMintz, Yuval input->rss_ind_table, 2388f29ffdb6SMintz, Yuval QED_RSS_IND_TABLE_SIZE * sizeof(void *)); 2389f29ffdb6SMintz, Yuval rss->rss_table_size_log = 7; 2390f29ffdb6SMintz, Yuval return 0; 2391f29ffdb6SMintz, Yuval } 2392f29ffdb6SMintz, Yuval 2393f29ffdb6SMintz, Yuval /* Start by copying the non-spcific information to the 2nd copy */ 2394f29ffdb6SMintz, Yuval memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params)); 2395f29ffdb6SMintz, Yuval 2396f29ffdb6SMintz, Yuval /* CMT should be round-robin */ 2397f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 2398f29ffdb6SMintz, Yuval struct qed_queue_cid *cid = input->rss_ind_table[i]; 2399f29ffdb6SMintz, Yuval struct qed_rss_params *t_rss; 2400f29ffdb6SMintz, Yuval 2401f29ffdb6SMintz, Yuval if (cid->p_owner == QED_LEADING_HWFN(cdev)) 2402f29ffdb6SMintz, Yuval t_rss = &rss[0]; 2403f29ffdb6SMintz, Yuval else 2404f29ffdb6SMintz, Yuval t_rss = &rss[1]; 2405f29ffdb6SMintz, Yuval 2406f29ffdb6SMintz, Yuval t_rss->rss_ind_table[i / cdev->num_hwfns] = cid; 2407f29ffdb6SMintz, Yuval } 2408f29ffdb6SMintz, Yuval 2409f29ffdb6SMintz, Yuval /* Make sure RSS is actually required */ 2410f29ffdb6SMintz, Yuval for_each_hwfn(cdev, fn) { 2411f29ffdb6SMintz, Yuval for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) { 2412f29ffdb6SMintz, Yuval if (rss[fn].rss_ind_table[i] != 2413f29ffdb6SMintz, Yuval rss[fn].rss_ind_table[0]) 2414f29ffdb6SMintz, Yuval break; 2415f29ffdb6SMintz, Yuval } 2416f29ffdb6SMintz, Yuval if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) { 2417f29ffdb6SMintz, Yuval DP_VERBOSE(cdev, NETIF_MSG_IFUP, 2418f29ffdb6SMintz, Yuval "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2419f29ffdb6SMintz, Yuval return -EINVAL; 2420f29ffdb6SMintz, Yuval } 2421f29ffdb6SMintz, Yuval rss[fn].rss_table_size_log = 6; 2422f29ffdb6SMintz, Yuval } 2423f29ffdb6SMintz, Yuval 2424f29ffdb6SMintz, Yuval return 0; 2425f29ffdb6SMintz, Yuval } 2426f29ffdb6SMintz, Yuval 2427cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev, 2428cee4d264SManish Chopra struct qed_update_vport_params *params) 2429cee4d264SManish Chopra { 2430cee4d264SManish Chopra struct qed_sp_vport_update_params sp_params; 2431f29ffdb6SMintz, Yuval struct qed_rss_params *rss; 2432f29ffdb6SMintz, Yuval int rc = 0, i; 2433cee4d264SManish Chopra 2434cee4d264SManish Chopra if (!cdev) 2435cee4d264SManish Chopra return -ENODEV; 2436cee4d264SManish Chopra 2437fad953ceSKees Cook rss = vzalloc(array_size(sizeof(*rss), cdev->num_hwfns)); 2438f29ffdb6SMintz, Yuval if (!rss) 2439f29ffdb6SMintz, Yuval return -ENOMEM; 2440f29ffdb6SMintz, Yuval 2441cee4d264SManish Chopra memset(&sp_params, 0, sizeof(sp_params)); 2442cee4d264SManish Chopra 2443cee4d264SManish Chopra /* Translate protocol params into sp params */ 2444cee4d264SManish Chopra sp_params.vport_id = params->vport_id; 24451a635e48SYuval Mintz sp_params.update_vport_active_rx_flg = params->update_vport_active_flg; 24461a635e48SYuval Mintz sp_params.update_vport_active_tx_flg = params->update_vport_active_flg; 2447cee4d264SManish Chopra sp_params.vport_active_rx_flg = params->vport_active_flg; 2448cee4d264SManish Chopra sp_params.vport_active_tx_flg = params->vport_active_flg; 2449831bfb0eSYuval Mintz sp_params.update_tx_switching_flg = params->update_tx_switching_flg; 2450831bfb0eSYuval Mintz sp_params.tx_switching_flg = params->tx_switching_flg; 24513f9b4a69SYuval Mintz sp_params.accept_any_vlan = params->accept_any_vlan; 24523f9b4a69SYuval Mintz sp_params.update_accept_any_vlan_flg = 24533f9b4a69SYuval Mintz params->update_accept_any_vlan_flg; 2454cee4d264SManish Chopra 2455f29ffdb6SMintz, Yuval /* Prepare the RSS configuration */ 2456f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2457f29ffdb6SMintz, Yuval if (qed_update_vport_rss(cdev, ¶ms->rss_params, rss)) 2458cee4d264SManish Chopra params->update_rss_flg = 0; 2459cee4d264SManish Chopra 2460cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2461cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2462cee4d264SManish Chopra 2463f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2464f29ffdb6SMintz, Yuval sp_params.rss_params = &rss[i]; 2465f29ffdb6SMintz, Yuval 2466cee4d264SManish Chopra sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2467cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &sp_params, 2468cee4d264SManish Chopra QED_SPQ_MODE_EBLOCK, 2469cee4d264SManish Chopra NULL); 2470cee4d264SManish Chopra if (rc) { 2471cee4d264SManish Chopra DP_ERR(cdev, "Failed to update VPORT\n"); 2472f29ffdb6SMintz, Yuval goto out; 2473cee4d264SManish Chopra } 2474cee4d264SManish Chopra 2475cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2476cee4d264SManish Chopra "Updated V-PORT %d: active_flag %d [update %d]\n", 2477cee4d264SManish Chopra params->vport_id, params->vport_active_flg, 2478cee4d264SManish Chopra params->update_vport_active_flg); 2479cee4d264SManish Chopra } 2480cee4d264SManish Chopra 2481f29ffdb6SMintz, Yuval out: 2482f29ffdb6SMintz, Yuval vfree(rss); 2483f29ffdb6SMintz, Yuval return rc; 2484cee4d264SManish Chopra } 2485cee4d264SManish Chopra 2486cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev, 24873da7a37aSMintz, Yuval u8 rss_num, 24883da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 2489cee4d264SManish Chopra u16 bd_max_bytes, 2490cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 2491cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 2492cee4d264SManish Chopra u16 cqe_pbl_size, 24933da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *ret_params) 2494cee4d264SManish Chopra { 2495cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 24961a635e48SYuval Mintz int rc, hwfn_index; 2497cee4d264SManish Chopra 24983da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2499cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2500cee4d264SManish Chopra 25013da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 25023da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2503cee4d264SManish Chopra 25043da7a37aSMintz, Yuval rc = qed_eth_rx_queue_start(p_hwfn, 2505cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 25063da7a37aSMintz, Yuval p_params, 2507cee4d264SManish Chopra bd_max_bytes, 2508cee4d264SManish Chopra bd_chain_phys_addr, 25093da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, ret_params); 2510cee4d264SManish Chopra if (rc) { 25113da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id); 2512cee4d264SManish Chopra return rc; 2513cee4d264SManish Chopra } 2514cee4d264SManish Chopra 2515cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2516f604b17dSMintz, Yuval "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", 25173da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 2518f604b17dSMintz, Yuval p_params->p_sb->igu_sb_id); 2519cee4d264SManish Chopra 2520cee4d264SManish Chopra return 0; 2521cee4d264SManish Chopra } 2522cee4d264SManish Chopra 25233da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle) 2524cee4d264SManish Chopra { 2525cee4d264SManish Chopra int rc, hwfn_index; 2526cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2527cee4d264SManish Chopra 25283da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2529cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2530cee4d264SManish Chopra 25313da7a37aSMintz, Yuval rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false); 2532cee4d264SManish Chopra if (rc) { 25333da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id); 2534cee4d264SManish Chopra return rc; 2535cee4d264SManish Chopra } 2536cee4d264SManish Chopra 2537cee4d264SManish Chopra return 0; 2538cee4d264SManish Chopra } 2539cee4d264SManish Chopra 2540cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev, 25413da7a37aSMintz, Yuval u8 rss_num, 2542cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 2543cee4d264SManish Chopra dma_addr_t pbl_addr, 2544cee4d264SManish Chopra u16 pbl_size, 25453da7a37aSMintz, Yuval struct qed_txq_start_ret_params *ret_params) 2546cee4d264SManish Chopra { 2547cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2548cee4d264SManish Chopra int rc, hwfn_index; 2549cee4d264SManish Chopra 25503da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2551cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 25523da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 25533da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2554cee4d264SManish Chopra 25553da7a37aSMintz, Yuval rc = qed_eth_tx_queue_start(p_hwfn, 2556cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 25573da7a37aSMintz, Yuval p_params, 0, 25583da7a37aSMintz, Yuval pbl_addr, pbl_size, ret_params); 2559cee4d264SManish Chopra 2560cee4d264SManish Chopra if (rc) { 2561cee4d264SManish Chopra DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 2562cee4d264SManish Chopra return rc; 2563cee4d264SManish Chopra } 2564cee4d264SManish Chopra 2565cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2566f604b17dSMintz, Yuval "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", 25673da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 2568f604b17dSMintz, Yuval p_params->p_sb->igu_sb_id); 2569cee4d264SManish Chopra 2570cee4d264SManish Chopra return 0; 2571cee4d264SManish Chopra } 2572cee4d264SManish Chopra 2573cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10) 2574cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev) 2575cee4d264SManish Chopra { 257615582962SRahul Verma int rc; 257715582962SRahul Verma 257815582962SRahul Verma rc = qed_hw_stop_fastpath(cdev); 257915582962SRahul Verma if (rc) { 258015582962SRahul Verma DP_ERR(cdev, "Failed to stop Fastpath\n"); 258115582962SRahul Verma return rc; 258215582962SRahul Verma } 2583cee4d264SManish Chopra 2584cee4d264SManish Chopra return 0; 2585cee4d264SManish Chopra } 2586cee4d264SManish Chopra 25873da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle) 2588cee4d264SManish Chopra { 2589cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2590cee4d264SManish Chopra int rc, hwfn_index; 2591cee4d264SManish Chopra 25923da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2593cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2594cee4d264SManish Chopra 25953da7a37aSMintz, Yuval rc = qed_eth_tx_queue_stop(p_hwfn, handle); 2596cee4d264SManish Chopra if (rc) { 25973da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id); 2598cee4d264SManish Chopra return rc; 2599cee4d264SManish Chopra } 2600cee4d264SManish Chopra 2601cee4d264SManish Chopra return 0; 2602cee4d264SManish Chopra } 2603cee4d264SManish Chopra 2604464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev, 2605464f6645SManish Chopra struct qed_tunn_params *tunn_params) 2606464f6645SManish Chopra { 260719968430SChopra, Manish struct qed_tunnel_info tunn_info; 2608464f6645SManish Chopra int i, rc; 2609464f6645SManish Chopra 2610464f6645SManish Chopra memset(&tunn_info, 0, sizeof(tunn_info)); 261119968430SChopra, Manish if (tunn_params->update_vxlan_port) { 261219968430SChopra, Manish tunn_info.vxlan_port.b_update_port = true; 261319968430SChopra, Manish tunn_info.vxlan_port.port = tunn_params->vxlan_port; 2614464f6645SManish Chopra } 2615464f6645SManish Chopra 261619968430SChopra, Manish if (tunn_params->update_geneve_port) { 261719968430SChopra, Manish tunn_info.geneve_port.b_update_port = true; 261819968430SChopra, Manish tunn_info.geneve_port.port = tunn_params->geneve_port; 2619464f6645SManish Chopra } 2620464f6645SManish Chopra 2621464f6645SManish Chopra for_each_hwfn(cdev, i) { 2622464f6645SManish Chopra struct qed_hwfn *hwfn = &cdev->hwfns[i]; 26234f64675fSManish Chopra struct qed_ptt *p_ptt; 262497379f15SChopra, Manish struct qed_tunnel_info *tun; 262597379f15SChopra, Manish 262697379f15SChopra, Manish tun = &hwfn->cdev->tunnel; 26274f64675fSManish Chopra if (IS_PF(cdev)) { 26284f64675fSManish Chopra p_ptt = qed_ptt_acquire(hwfn); 26294f64675fSManish Chopra if (!p_ptt) 26304f64675fSManish Chopra return -EAGAIN; 26314f64675fSManish Chopra } else { 26324f64675fSManish Chopra p_ptt = NULL; 26334f64675fSManish Chopra } 2634464f6645SManish Chopra 26354f64675fSManish Chopra rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info, 2636464f6645SManish Chopra QED_SPQ_MODE_EBLOCK, NULL); 26374f64675fSManish Chopra if (rc) { 26384f64675fSManish Chopra if (IS_PF(cdev)) 26394f64675fSManish Chopra qed_ptt_release(hwfn, p_ptt); 2640464f6645SManish Chopra return rc; 26414f64675fSManish Chopra } 264297379f15SChopra, Manish 264397379f15SChopra, Manish if (IS_PF_SRIOV(hwfn)) { 264497379f15SChopra, Manish u16 vxlan_port, geneve_port; 264597379f15SChopra, Manish int j; 264697379f15SChopra, Manish 264797379f15SChopra, Manish vxlan_port = tun->vxlan_port.port; 264897379f15SChopra, Manish geneve_port = tun->geneve_port.port; 264997379f15SChopra, Manish 265097379f15SChopra, Manish qed_for_each_vf(hwfn, j) { 265197379f15SChopra, Manish qed_iov_bulletin_set_udp_ports(hwfn, j, 265297379f15SChopra, Manish vxlan_port, 265397379f15SChopra, Manish geneve_port); 265497379f15SChopra, Manish } 265597379f15SChopra, Manish 265697379f15SChopra, Manish qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG); 265797379f15SChopra, Manish } 26584f64675fSManish Chopra if (IS_PF(cdev)) 26594f64675fSManish Chopra qed_ptt_release(hwfn, p_ptt); 2660464f6645SManish Chopra } 2661464f6645SManish Chopra 2662464f6645SManish Chopra return 0; 2663464f6645SManish Chopra } 2664464f6645SManish Chopra 2665cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 2666cee4d264SManish Chopra enum qed_filter_rx_mode_type type) 2667cee4d264SManish Chopra { 2668cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 2669cee4d264SManish Chopra 2670cee4d264SManish Chopra memset(&accept_flags, 0, sizeof(accept_flags)); 2671cee4d264SManish Chopra 2672cee4d264SManish Chopra accept_flags.update_rx_mode_config = 1; 2673cee4d264SManish Chopra accept_flags.update_tx_mode_config = 1; 2674cee4d264SManish Chopra accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2675cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2676cee4d264SManish Chopra QED_ACCEPT_BCAST; 2677cee4d264SManish Chopra accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2678cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2679cee4d264SManish Chopra QED_ACCEPT_BCAST; 2680cee4d264SManish Chopra 268188067876SMintz, Yuval if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 2682cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 2683cee4d264SManish Chopra QED_ACCEPT_MCAST_UNMATCHED; 268488067876SMintz, Yuval accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 268588067876SMintz, Yuval } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 2686cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 268788067876SMintz, Yuval accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 268888067876SMintz, Yuval } 2689cee4d264SManish Chopra 26903f9b4a69SYuval Mintz return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 2691cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 2692cee4d264SManish Chopra } 2693cee4d264SManish Chopra 2694cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev, 2695cee4d264SManish Chopra struct qed_filter_ucast_params *params) 2696cee4d264SManish Chopra { 2697cee4d264SManish Chopra struct qed_filter_ucast ucast; 2698cee4d264SManish Chopra 2699cee4d264SManish Chopra if (!params->vlan_valid && !params->mac_valid) { 27001a635e48SYuval Mintz DP_NOTICE(cdev, 2701cee4d264SManish Chopra "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 2702cee4d264SManish Chopra return -EINVAL; 2703cee4d264SManish Chopra } 2704cee4d264SManish Chopra 2705cee4d264SManish Chopra memset(&ucast, 0, sizeof(ucast)); 2706cee4d264SManish Chopra switch (params->type) { 2707cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2708cee4d264SManish Chopra ucast.opcode = QED_FILTER_ADD; 2709cee4d264SManish Chopra break; 2710cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2711cee4d264SManish Chopra ucast.opcode = QED_FILTER_REMOVE; 2712cee4d264SManish Chopra break; 2713cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_REPLACE: 2714cee4d264SManish Chopra ucast.opcode = QED_FILTER_REPLACE; 2715cee4d264SManish Chopra break; 2716cee4d264SManish Chopra default: 2717cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 2718cee4d264SManish Chopra params->type); 2719cee4d264SManish Chopra } 2720cee4d264SManish Chopra 2721cee4d264SManish Chopra if (params->vlan_valid && params->mac_valid) { 2722cee4d264SManish Chopra ucast.type = QED_FILTER_MAC_VLAN; 2723cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2724cee4d264SManish Chopra ucast.vlan = params->vlan; 2725cee4d264SManish Chopra } else if (params->mac_valid) { 2726cee4d264SManish Chopra ucast.type = QED_FILTER_MAC; 2727cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2728cee4d264SManish Chopra } else { 2729cee4d264SManish Chopra ucast.type = QED_FILTER_VLAN; 2730cee4d264SManish Chopra ucast.vlan = params->vlan; 2731cee4d264SManish Chopra } 2732cee4d264SManish Chopra 2733cee4d264SManish Chopra ucast.is_rx_filter = true; 2734cee4d264SManish Chopra ucast.is_tx_filter = true; 2735cee4d264SManish Chopra 2736cee4d264SManish Chopra return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 2737cee4d264SManish Chopra } 2738cee4d264SManish Chopra 2739cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev, 2740cee4d264SManish Chopra struct qed_filter_mcast_params *params) 2741cee4d264SManish Chopra { 2742cee4d264SManish Chopra struct qed_filter_mcast mcast; 2743cee4d264SManish Chopra int i; 2744cee4d264SManish Chopra 2745cee4d264SManish Chopra memset(&mcast, 0, sizeof(mcast)); 2746cee4d264SManish Chopra switch (params->type) { 2747cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2748cee4d264SManish Chopra mcast.opcode = QED_FILTER_ADD; 2749cee4d264SManish Chopra break; 2750cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2751cee4d264SManish Chopra mcast.opcode = QED_FILTER_REMOVE; 2752cee4d264SManish Chopra break; 2753cee4d264SManish Chopra default: 2754cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 2755cee4d264SManish Chopra params->type); 2756cee4d264SManish Chopra } 2757cee4d264SManish Chopra 2758cee4d264SManish Chopra mcast.num_mc_addrs = params->num; 2759cee4d264SManish Chopra for (i = 0; i < mcast.num_mc_addrs; i++) 2760cee4d264SManish Chopra ether_addr_copy(mcast.mac[i], params->mac[i]); 2761cee4d264SManish Chopra 27621a635e48SYuval Mintz return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL); 2763cee4d264SManish Chopra } 2764cee4d264SManish Chopra 2765cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev, 2766cee4d264SManish Chopra struct qed_filter_params *params) 2767cee4d264SManish Chopra { 2768cee4d264SManish Chopra enum qed_filter_rx_mode_type accept_flags; 2769cee4d264SManish Chopra 2770cee4d264SManish Chopra switch (params->type) { 2771cee4d264SManish Chopra case QED_FILTER_TYPE_UCAST: 2772cee4d264SManish Chopra return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 2773cee4d264SManish Chopra case QED_FILTER_TYPE_MCAST: 2774cee4d264SManish Chopra return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 2775cee4d264SManish Chopra case QED_FILTER_TYPE_RX_MODE: 2776cee4d264SManish Chopra accept_flags = params->filter.accept_flags; 2777cee4d264SManish Chopra return qed_configure_filter_rx_mode(cdev, accept_flags); 2778cee4d264SManish Chopra default: 27791a635e48SYuval Mintz DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type); 2780cee4d264SManish Chopra return -EINVAL; 2781cee4d264SManish Chopra } 2782cee4d264SManish Chopra } 2783cee4d264SManish Chopra 2784da090917STomer Tayar static int qed_configure_arfs_searcher(struct qed_dev *cdev, 2785da090917STomer Tayar enum qed_filter_config_mode mode) 2786d51e4af5SChopra, Manish { 2787d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2788d51e4af5SChopra, Manish struct qed_arfs_config_params arfs_config_params; 2789d51e4af5SChopra, Manish 2790d51e4af5SChopra, Manish memset(&arfs_config_params, 0, sizeof(arfs_config_params)); 2791d51e4af5SChopra, Manish arfs_config_params.tcp = true; 2792d51e4af5SChopra, Manish arfs_config_params.udp = true; 2793d51e4af5SChopra, Manish arfs_config_params.ipv4 = true; 2794d51e4af5SChopra, Manish arfs_config_params.ipv6 = true; 2795da090917STomer Tayar arfs_config_params.mode = mode; 2796d51e4af5SChopra, Manish qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt, 2797d51e4af5SChopra, Manish &arfs_config_params); 2798d51e4af5SChopra, Manish return 0; 2799d51e4af5SChopra, Manish } 2800d51e4af5SChopra, Manish 2801d51e4af5SChopra, Manish static void 2802d51e4af5SChopra, Manish qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn, 2803da090917STomer Tayar void *cookie, 2804da090917STomer Tayar union event_ring_data *data, u8 fw_return_code) 2805d51e4af5SChopra, Manish { 2806d51e4af5SChopra, Manish struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common; 2807d51e4af5SChopra, Manish void *dev = p_hwfn->cdev->ops_cookie; 2808d51e4af5SChopra, Manish 2809d51e4af5SChopra, Manish op->arfs_filter_op(dev, cookie, fw_return_code); 2810d51e4af5SChopra, Manish } 2811d51e4af5SChopra, Manish 2812da090917STomer Tayar static int 2813da090917STomer Tayar qed_ntuple_arfs_filter_config(struct qed_dev *cdev, 2814da090917STomer Tayar void *cookie, 2815da090917STomer Tayar struct qed_ntuple_filter_params *params) 2816d51e4af5SChopra, Manish { 2817d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2818d51e4af5SChopra, Manish struct qed_spq_comp_cb cb; 2819d51e4af5SChopra, Manish int rc = -EINVAL; 2820d51e4af5SChopra, Manish 2821d51e4af5SChopra, Manish cb.function = qed_arfs_sp_response_handler; 2822d51e4af5SChopra, Manish cb.cookie = cookie; 2823d51e4af5SChopra, Manish 2824da090917STomer Tayar if (params->b_is_vf) { 2825da090917STomer Tayar if (!qed_iov_is_valid_vfid(p_hwfn, params->vf_id, false, 2826da090917STomer Tayar false)) { 2827da090917STomer Tayar DP_INFO(p_hwfn, "vfid 0x%02x is out of bounds\n", 2828da090917STomer Tayar params->vf_id); 2829da090917STomer Tayar return rc; 2830da090917STomer Tayar } 2831da090917STomer Tayar 2832da090917STomer Tayar params->vport_id = params->vf_id + 1; 2833da090917STomer Tayar params->qid = QED_RFS_NTUPLE_QID_RSS; 2834da090917STomer Tayar } 2835da090917STomer Tayar 2836da090917STomer Tayar rc = qed_configure_rfs_ntuple_filter(p_hwfn, &cb, params); 2837d51e4af5SChopra, Manish if (rc) 2838d51e4af5SChopra, Manish DP_NOTICE(p_hwfn, 2839d51e4af5SChopra, Manish "Failed to issue a-RFS filter configuration\n"); 2840d51e4af5SChopra, Manish else 2841d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, 2842d51e4af5SChopra, Manish "Successfully issued a-RFS filter configuration\n"); 2843d51e4af5SChopra, Manish 2844d51e4af5SChopra, Manish return rc; 2845d51e4af5SChopra, Manish } 2846d51e4af5SChopra, Manish 2847bf5a94bfSRahul Verma static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle) 2848bf5a94bfSRahul Verma { 2849bf5a94bfSRahul Verma struct qed_queue_cid *p_cid = handle; 2850bf5a94bfSRahul Verma struct qed_hwfn *p_hwfn; 2851bf5a94bfSRahul Verma int rc; 2852bf5a94bfSRahul Verma 2853bf5a94bfSRahul Verma p_hwfn = p_cid->p_owner; 2854bf5a94bfSRahul Verma rc = qed_get_queue_coalesce(p_hwfn, coal, handle); 2855bf5a94bfSRahul Verma if (rc) 28569e4a5613SColin Ian King DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n"); 2857bf5a94bfSRahul Verma 2858bf5a94bfSRahul Verma return rc; 2859bf5a94bfSRahul Verma } 2860bf5a94bfSRahul Verma 2861cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev, 28621a635e48SYuval Mintz u8 rss_id, struct eth_slow_path_rx_cqe *cqe) 2863cee4d264SManish Chopra { 2864cee4d264SManish Chopra return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 2865cee4d264SManish Chopra cqe); 2866cee4d264SManish Chopra } 2867cee4d264SManish Chopra 2868809c45a0SShahed Shaikh static int qed_req_bulletin_update_mac(struct qed_dev *cdev, u8 *mac) 2869809c45a0SShahed Shaikh { 2870809c45a0SShahed Shaikh int i, ret; 2871809c45a0SShahed Shaikh 2872809c45a0SShahed Shaikh if (IS_PF(cdev)) 2873809c45a0SShahed Shaikh return 0; 2874809c45a0SShahed Shaikh 2875809c45a0SShahed Shaikh for_each_hwfn(cdev, i) { 2876809c45a0SShahed Shaikh struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2877809c45a0SShahed Shaikh 2878809c45a0SShahed Shaikh ret = qed_vf_pf_bulletin_update_mac(p_hwfn, mac); 2879809c45a0SShahed Shaikh if (ret) 2880809c45a0SShahed Shaikh return ret; 2881809c45a0SShahed Shaikh } 2882809c45a0SShahed Shaikh 2883809c45a0SShahed Shaikh return 0; 2884809c45a0SShahed Shaikh } 2885809c45a0SShahed Shaikh 28860b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 28870b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass; 28880b55e27dSYuval Mintz #endif 28890b55e27dSYuval Mintz 2890a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2891a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass; 2892a1d8d8a5SSudarsana Reddy Kalluru #endif 2893a1d8d8a5SSudarsana Reddy Kalluru 2894c78c70faSSudarsana Reddy Kalluru extern const struct qed_eth_ptp_ops qed_ptp_ops_pass; 2895c78c70faSSudarsana Reddy Kalluru 289625c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = { 289725c089d7SYuval Mintz .common = &qed_common_ops_pass, 28980b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 28990b55e27dSYuval Mintz .iov = &qed_iov_ops_pass, 29000b55e27dSYuval Mintz #endif 2901a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2902a1d8d8a5SSudarsana Reddy Kalluru .dcb = &qed_dcbnl_ops_pass, 2903a1d8d8a5SSudarsana Reddy Kalluru #endif 2904c78c70faSSudarsana Reddy Kalluru .ptp = &qed_ptp_ops_pass, 290525c089d7SYuval Mintz .fill_dev_info = &qed_fill_eth_dev_info, 2906cc875c2eSYuval Mintz .register_ops = &qed_register_eth_ops, 2907eff16960SYuval Mintz .check_mac = &qed_check_mac, 2908cee4d264SManish Chopra .vport_start = &qed_start_vport, 2909cee4d264SManish Chopra .vport_stop = &qed_stop_vport, 2910cee4d264SManish Chopra .vport_update = &qed_update_vport, 2911cee4d264SManish Chopra .q_rx_start = &qed_start_rxq, 2912cee4d264SManish Chopra .q_rx_stop = &qed_stop_rxq, 2913cee4d264SManish Chopra .q_tx_start = &qed_start_txq, 2914cee4d264SManish Chopra .q_tx_stop = &qed_stop_txq, 2915cee4d264SManish Chopra .filter_config = &qed_configure_filter, 2916cee4d264SManish Chopra .fastpath_stop = &qed_fastpath_stop, 2917cee4d264SManish Chopra .eth_cqe_completion = &qed_fp_cqe_completion, 29189df2ed04SManish Chopra .get_vport_stats = &qed_get_vport_stats, 2919464f6645SManish Chopra .tunn_config = &qed_tunn_configure, 2920d51e4af5SChopra, Manish .ntuple_filter_config = &qed_ntuple_arfs_filter_config, 2921d51e4af5SChopra, Manish .configure_arfs_searcher = &qed_configure_arfs_searcher, 2922bf5a94bfSRahul Verma .get_coalesce = &qed_get_coalesce, 2923809c45a0SShahed Shaikh .req_bulletin_update_mac = &qed_req_bulletin_update_mac, 292425c089d7SYuval Mintz }; 292525c089d7SYuval Mintz 292695114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void) 292725c089d7SYuval Mintz { 292825c089d7SYuval Mintz return &qed_eth_ops_pass; 292925c089d7SYuval Mintz } 293025c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops); 293125c089d7SYuval Mintz 293225c089d7SYuval Mintz void qed_put_eth_ops(void) 293325c089d7SYuval Mintz { 293425c089d7SYuval Mintz /* TODO - reference count for module? */ 293525c089d7SYuval Mintz } 293625c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops); 2937