125c089d7SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 325c089d7SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 3125c089d7SYuval Mintz */ 3225c089d7SYuval Mintz 3325c089d7SYuval Mintz #include <linux/types.h> 3425c089d7SYuval Mintz #include <asm/byteorder.h> 3525c089d7SYuval Mintz #include <asm/param.h> 3625c089d7SYuval Mintz #include <linux/delay.h> 3725c089d7SYuval Mintz #include <linux/dma-mapping.h> 3825c089d7SYuval Mintz #include <linux/etherdevice.h> 3925c089d7SYuval Mintz #include <linux/interrupt.h> 4025c089d7SYuval Mintz #include <linux/kernel.h> 4125c089d7SYuval Mintz #include <linux/module.h> 4225c089d7SYuval Mintz #include <linux/pci.h> 4325c089d7SYuval Mintz #include <linux/slab.h> 4425c089d7SYuval Mintz #include <linux/stddef.h> 4525c089d7SYuval Mintz #include <linux/string.h> 4625c089d7SYuval Mintz #include <linux/version.h> 4725c089d7SYuval Mintz #include <linux/workqueue.h> 4825c089d7SYuval Mintz #include <linux/bitops.h> 4925c089d7SYuval Mintz #include <linux/bug.h> 503da7a37aSMintz, Yuval #include <linux/vmalloc.h> 5125c089d7SYuval Mintz #include "qed.h" 5225c089d7SYuval Mintz #include <linux/qed/qed_chain.h> 5325c089d7SYuval Mintz #include "qed_cxt.h" 5425c089d7SYuval Mintz #include "qed_dev_api.h" 5525c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h> 5625c089d7SYuval Mintz #include "qed_hsi.h" 5725c089d7SYuval Mintz #include "qed_hw.h" 5825c089d7SYuval Mintz #include "qed_int.h" 59dacd88d6SYuval Mintz #include "qed_l2.h" 6086622ee7SYuval Mintz #include "qed_mcp.h" 6125c089d7SYuval Mintz #include "qed_reg_addr.h" 6225c089d7SYuval Mintz #include "qed_sp.h" 631408cc1fSYuval Mintz #include "qed_sriov.h" 6425c089d7SYuval Mintz 65088c8618SManish Chopra 66cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16 67cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41 68cee4d264SManish Chopra 693da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn, 703da7a37aSMintz, Yuval struct qed_queue_cid *p_cid) 713da7a37aSMintz, Yuval { 723da7a37aSMintz, Yuval /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */ 733da7a37aSMintz, Yuval if (!p_cid->is_vf && IS_PF(p_hwfn->cdev)) 743da7a37aSMintz, Yuval qed_cxt_release_cid(p_hwfn, p_cid->cid); 753da7a37aSMintz, Yuval vfree(p_cid); 763da7a37aSMintz, Yuval } 773da7a37aSMintz, Yuval 783da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs 793da7a37aSMintz, Yuval * for their VFs. 803da7a37aSMintz, Yuval */ 813da7a37aSMintz, Yuval struct qed_queue_cid * 823da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 833da7a37aSMintz, Yuval u16 opaque_fid, 843da7a37aSMintz, Yuval u32 cid, 853da7a37aSMintz, Yuval u8 vf_qid, 863da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params) 873da7a37aSMintz, Yuval { 883da7a37aSMintz, Yuval bool b_is_same = (p_hwfn->hw_info.opaque_fid == opaque_fid); 893da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 903da7a37aSMintz, Yuval int rc; 913da7a37aSMintz, Yuval 923da7a37aSMintz, Yuval p_cid = vmalloc(sizeof(*p_cid)); 933da7a37aSMintz, Yuval if (!p_cid) 943da7a37aSMintz, Yuval return NULL; 953da7a37aSMintz, Yuval memset(p_cid, 0, sizeof(*p_cid)); 963da7a37aSMintz, Yuval 973da7a37aSMintz, Yuval p_cid->opaque_fid = opaque_fid; 983da7a37aSMintz, Yuval p_cid->cid = cid; 993da7a37aSMintz, Yuval p_cid->vf_qid = vf_qid; 1003da7a37aSMintz, Yuval p_cid->rel = *p_params; 101f29ffdb6SMintz, Yuval p_cid->p_owner = p_hwfn; 1023da7a37aSMintz, Yuval 1033da7a37aSMintz, Yuval /* Don't try calculating the absolute indices for VFs */ 1043da7a37aSMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 1053da7a37aSMintz, Yuval p_cid->abs = p_cid->rel; 1063da7a37aSMintz, Yuval goto out; 1073da7a37aSMintz, Yuval } 1083da7a37aSMintz, Yuval 1093da7a37aSMintz, Yuval /* Calculate the engine-absolute indices of the resources. 1103da7a37aSMintz, Yuval * This would guarantee they're valid later on. 1113da7a37aSMintz, Yuval * In some cases [SBs] we already have the right values. 1123da7a37aSMintz, Yuval */ 1133da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id); 1143da7a37aSMintz, Yuval if (rc) 1153da7a37aSMintz, Yuval goto fail; 1163da7a37aSMintz, Yuval 1173da7a37aSMintz, Yuval rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id); 1183da7a37aSMintz, Yuval if (rc) 1193da7a37aSMintz, Yuval goto fail; 1203da7a37aSMintz, Yuval 1213da7a37aSMintz, Yuval /* In case of a PF configuring its VF's queues, the stats-id is already 1223da7a37aSMintz, Yuval * absolute [since there's a single index that's suitable per-VF]. 1233da7a37aSMintz, Yuval */ 1243da7a37aSMintz, Yuval if (b_is_same) { 1253da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id, 1263da7a37aSMintz, Yuval &p_cid->abs.stats_id); 1273da7a37aSMintz, Yuval if (rc) 1283da7a37aSMintz, Yuval goto fail; 1293da7a37aSMintz, Yuval } else { 1303da7a37aSMintz, Yuval p_cid->abs.stats_id = p_cid->rel.stats_id; 1313da7a37aSMintz, Yuval } 1323da7a37aSMintz, Yuval 1333da7a37aSMintz, Yuval /* SBs relevant information was already provided as absolute */ 1343da7a37aSMintz, Yuval p_cid->abs.sb = p_cid->rel.sb; 1353da7a37aSMintz, Yuval p_cid->abs.sb_idx = p_cid->rel.sb_idx; 1363da7a37aSMintz, Yuval 1373da7a37aSMintz, Yuval /* This is tricky - we're actually interested in whehter this is a PF 1383da7a37aSMintz, Yuval * entry meant for the VF. 1393da7a37aSMintz, Yuval */ 1403da7a37aSMintz, Yuval if (!b_is_same) 1413da7a37aSMintz, Yuval p_cid->is_vf = true; 1423da7a37aSMintz, Yuval out: 1433da7a37aSMintz, Yuval DP_VERBOSE(p_hwfn, 1443da7a37aSMintz, Yuval QED_MSG_SP, 1453da7a37aSMintz, Yuval "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x [%04x] stats %02x [%02x] SB %04x PI %02x\n", 1463da7a37aSMintz, Yuval p_cid->opaque_fid, 1473da7a37aSMintz, Yuval p_cid->cid, 1483da7a37aSMintz, Yuval p_cid->rel.vport_id, 1493da7a37aSMintz, Yuval p_cid->abs.vport_id, 1503da7a37aSMintz, Yuval p_cid->rel.queue_id, 1513da7a37aSMintz, Yuval p_cid->abs.queue_id, 1523da7a37aSMintz, Yuval p_cid->rel.stats_id, 1533da7a37aSMintz, Yuval p_cid->abs.stats_id, p_cid->abs.sb, p_cid->abs.sb_idx); 1543da7a37aSMintz, Yuval 1553da7a37aSMintz, Yuval return p_cid; 1563da7a37aSMintz, Yuval 1573da7a37aSMintz, Yuval fail: 1583da7a37aSMintz, Yuval vfree(p_cid); 1593da7a37aSMintz, Yuval return NULL; 1603da7a37aSMintz, Yuval } 1613da7a37aSMintz, Yuval 1623da7a37aSMintz, Yuval static struct qed_queue_cid *qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 1633da7a37aSMintz, Yuval u16 opaque_fid, struct 1643da7a37aSMintz, Yuval qed_queue_start_common_params 1653da7a37aSMintz, Yuval *p_params) 1663da7a37aSMintz, Yuval { 1673da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 1683da7a37aSMintz, Yuval u32 cid = 0; 1693da7a37aSMintz, Yuval 1703da7a37aSMintz, Yuval /* Get a unique firmware CID for this queue, in case it's a PF. 1713da7a37aSMintz, Yuval * VF's don't need a CID as the queue configuration will be done 1723da7a37aSMintz, Yuval * by PF. 1733da7a37aSMintz, Yuval */ 1743da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 1753da7a37aSMintz, Yuval if (qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &cid)) { 1763da7a37aSMintz, Yuval DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 1773da7a37aSMintz, Yuval return NULL; 1783da7a37aSMintz, Yuval } 1793da7a37aSMintz, Yuval } 1803da7a37aSMintz, Yuval 1813da7a37aSMintz, Yuval p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 0, p_params); 1823da7a37aSMintz, Yuval if (!p_cid && IS_PF(p_hwfn->cdev)) 1833da7a37aSMintz, Yuval qed_cxt_release_cid(p_hwfn, cid); 1843da7a37aSMintz, Yuval 1853da7a37aSMintz, Yuval return p_cid; 1863da7a37aSMintz, Yuval } 1873da7a37aSMintz, Yuval 188dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 189088c8618SManish Chopra struct qed_sp_vport_start_params *p_params) 190cee4d264SManish Chopra { 191cee4d264SManish Chopra struct vport_start_ramrod_data *p_ramrod = NULL; 192cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 19306f56b81SYuval Mintz struct qed_sp_init_data init_data; 194dacd88d6SYuval Mintz u8 abs_vport_id = 0; 195cee4d264SManish Chopra int rc = -EINVAL; 196cee4d264SManish Chopra u16 rx_mode = 0; 197cee4d264SManish Chopra 198088c8618SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 1991a635e48SYuval Mintz if (rc) 200cee4d264SManish Chopra return rc; 201cee4d264SManish Chopra 20206f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 20306f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 204088c8618SManish Chopra init_data.opaque_fid = p_params->opaque_fid; 20506f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 206cee4d264SManish Chopra 207cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 208cee4d264SManish Chopra ETH_RAMROD_VPORT_START, 20906f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 210cee4d264SManish Chopra if (rc) 211cee4d264SManish Chopra return rc; 212cee4d264SManish Chopra 213cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_start; 214cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 215cee4d264SManish Chopra 216088c8618SManish Chopra p_ramrod->mtu = cpu_to_le16(p_params->mtu); 217c78c70faSSudarsana Reddy Kalluru p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts; 218088c8618SManish Chopra p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 219088c8618SManish Chopra p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 220e6bd8923SYuval Mintz p_ramrod->untagged = p_params->only_untagged; 221cee4d264SManish Chopra 222cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 223cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 224cee4d264SManish Chopra 225cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 226cee4d264SManish Chopra 227cee4d264SManish Chopra /* TPA related fields */ 2281a635e48SYuval Mintz memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param)); 229cee4d264SManish Chopra 230088c8618SManish Chopra p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; 231088c8618SManish Chopra 232088c8618SManish Chopra switch (p_params->tpa_mode) { 233088c8618SManish Chopra case QED_TPA_MODE_GRO: 234088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 235088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_size = (u16)-1; 236088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; 237088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; 238088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; 239088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; 240088c8618SManish Chopra p_ramrod->tpa_param.tpa_pkt_split_flg = 1; 241088c8618SManish Chopra p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; 242088c8618SManish Chopra break; 243088c8618SManish Chopra default: 244088c8618SManish Chopra break; 245088c8618SManish Chopra } 246088c8618SManish Chopra 247831bfb0eSYuval Mintz p_ramrod->tx_switching_en = p_params->tx_switching; 248831bfb0eSYuval Mintz 24911a85d75SYuval Mintz p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac; 25011a85d75SYuval Mintz p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype; 25111a85d75SYuval Mintz 252cee4d264SManish Chopra /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 253cee4d264SManish Chopra p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 254088c8618SManish Chopra p_params->concrete_fid); 255cee4d264SManish Chopra 256cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 257cee4d264SManish Chopra } 258cee4d264SManish Chopra 259ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 260dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params) 261dacd88d6SYuval Mintz { 262dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 263dacd88d6SYuval Mintz return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, 264dacd88d6SYuval Mintz p_params->mtu, 265dacd88d6SYuval Mintz p_params->remove_inner_vlan, 266dacd88d6SYuval Mintz p_params->tpa_mode, 26708feecd7SYuval Mintz p_params->max_buffers_per_cqe, 26808feecd7SYuval Mintz p_params->only_untagged); 269dacd88d6SYuval Mintz } 270dacd88d6SYuval Mintz 271dacd88d6SYuval Mintz return qed_sp_eth_vport_start(p_hwfn, p_params); 272dacd88d6SYuval Mintz } 273dacd88d6SYuval Mintz 274cee4d264SManish Chopra static int 275cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 276cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 277f29ffdb6SMintz, Yuval struct qed_rss_params *p_rss) 278cee4d264SManish Chopra { 279f29ffdb6SMintz, Yuval struct eth_vport_rss_config *p_config; 280f29ffdb6SMintz, Yuval u16 capabilities = 0; 281f29ffdb6SMintz, Yuval int i, table_size; 282f29ffdb6SMintz, Yuval int rc = 0; 283cee4d264SManish Chopra 284f29ffdb6SMintz, Yuval if (!p_rss) { 285cee4d264SManish Chopra p_ramrod->common.update_rss_flg = 0; 286cee4d264SManish Chopra return rc; 287cee4d264SManish Chopra } 288f29ffdb6SMintz, Yuval p_config = &p_ramrod->rss_config; 289cee4d264SManish Chopra 290f29ffdb6SMintz, Yuval BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM); 291cee4d264SManish Chopra 292f29ffdb6SMintz, Yuval rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id); 293cee4d264SManish Chopra if (rc) 294cee4d264SManish Chopra return rc; 295cee4d264SManish Chopra 296f29ffdb6SMintz, Yuval p_ramrod->common.update_rss_flg = p_rss->update_rss_config; 297f29ffdb6SMintz, Yuval p_config->update_rss_capabilities = p_rss->update_rss_capabilities; 298f29ffdb6SMintz, Yuval p_config->update_rss_ind_table = p_rss->update_rss_ind_table; 299f29ffdb6SMintz, Yuval p_config->update_rss_key = p_rss->update_rss_key; 300cee4d264SManish Chopra 301f29ffdb6SMintz, Yuval p_config->rss_mode = p_rss->rss_enable ? 302cee4d264SManish Chopra ETH_VPORT_RSS_MODE_REGULAR : 303cee4d264SManish Chopra ETH_VPORT_RSS_MODE_DISABLED; 304cee4d264SManish Chopra 305cee4d264SManish Chopra SET_FIELD(capabilities, 306cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 307f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4)); 308cee4d264SManish Chopra SET_FIELD(capabilities, 309cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 310f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6)); 311cee4d264SManish Chopra SET_FIELD(capabilities, 312cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 313f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_TCP)); 314cee4d264SManish Chopra SET_FIELD(capabilities, 315cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 316f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_TCP)); 317cee4d264SManish Chopra SET_FIELD(capabilities, 318cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 319f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_UDP)); 320cee4d264SManish Chopra SET_FIELD(capabilities, 321cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 322f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_UDP)); 323f29ffdb6SMintz, Yuval p_config->tbl_size = p_rss->rss_table_size_log; 324cee4d264SManish Chopra 325f29ffdb6SMintz, Yuval p_config->capabilities = cpu_to_le16(capabilities); 326cee4d264SManish Chopra 327cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 328cee4d264SManish Chopra "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 329cee4d264SManish Chopra p_ramrod->common.update_rss_flg, 330f29ffdb6SMintz, Yuval p_config->rss_mode, 331f29ffdb6SMintz, Yuval p_config->update_rss_capabilities, 332f29ffdb6SMintz, Yuval p_config->capabilities, 333f29ffdb6SMintz, Yuval p_config->update_rss_ind_table, p_config->update_rss_key); 334cee4d264SManish Chopra 335f29ffdb6SMintz, Yuval table_size = min_t(int, QED_RSS_IND_TABLE_SIZE, 336f29ffdb6SMintz, Yuval 1 << p_config->tbl_size); 337f29ffdb6SMintz, Yuval for (i = 0; i < table_size; i++) { 338f29ffdb6SMintz, Yuval struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i]; 339cee4d264SManish Chopra 340f29ffdb6SMintz, Yuval if (!p_queue) 341f29ffdb6SMintz, Yuval return -EINVAL; 342f29ffdb6SMintz, Yuval 343f29ffdb6SMintz, Yuval p_config->indirection_table[i] = 344f29ffdb6SMintz, Yuval cpu_to_le16(p_queue->abs.queue_id); 345f29ffdb6SMintz, Yuval } 346f29ffdb6SMintz, Yuval 347f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 348f29ffdb6SMintz, Yuval "Configured RSS indirection table [%d entries]:\n", 349f29ffdb6SMintz, Yuval table_size); 350f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) { 351f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, 352f29ffdb6SMintz, Yuval NETIF_MSG_IFUP, 353f29ffdb6SMintz, Yuval "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", 354f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i]), 355f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 1]), 356f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 2]), 357f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 3]), 358f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 4]), 359f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 5]), 360f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 6]), 361f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 7]), 362f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 8]), 363f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 9]), 364f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 10]), 365f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 11]), 366f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 12]), 367f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 13]), 368f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 14]), 369f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 15])); 370cee4d264SManish Chopra } 371cee4d264SManish Chopra 372cee4d264SManish Chopra for (i = 0; i < 10; i++) 373f29ffdb6SMintz, Yuval p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]); 374cee4d264SManish Chopra 375cee4d264SManish Chopra return rc; 376cee4d264SManish Chopra } 377cee4d264SManish Chopra 378cee4d264SManish Chopra static void 379cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 380cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 381cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags) 382cee4d264SManish Chopra { 383cee4d264SManish Chopra p_ramrod->common.update_rx_mode_flg = 384cee4d264SManish Chopra accept_flags.update_rx_mode_config; 385cee4d264SManish Chopra 386cee4d264SManish Chopra p_ramrod->common.update_tx_mode_flg = 387cee4d264SManish Chopra accept_flags.update_tx_mode_config; 388cee4d264SManish Chopra 389cee4d264SManish Chopra /* Set Rx mode accept flags */ 390cee4d264SManish Chopra if (p_ramrod->common.update_rx_mode_flg) { 391cee4d264SManish Chopra u8 accept_filter = accept_flags.rx_accept_filter; 392cee4d264SManish Chopra u16 state = 0; 393cee4d264SManish Chopra 394cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 395cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 396cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 397cee4d264SManish Chopra 398cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 399cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 400cee4d264SManish Chopra 401cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 402cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 403cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 404cee4d264SManish Chopra 405cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 406cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 407cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 408cee4d264SManish Chopra 409cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 410cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 411cee4d264SManish Chopra 412cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(state); 413cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 414cee4d264SManish Chopra "p_ramrod->rx_mode.state = 0x%x\n", state); 415cee4d264SManish Chopra } 416cee4d264SManish Chopra 417cee4d264SManish Chopra /* Set Tx mode accept flags */ 418cee4d264SManish Chopra if (p_ramrod->common.update_tx_mode_flg) { 419cee4d264SManish Chopra u8 accept_filter = accept_flags.tx_accept_filter; 420cee4d264SManish Chopra u16 state = 0; 421cee4d264SManish Chopra 422cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 423cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 424cee4d264SManish Chopra 425cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 426cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 427cee4d264SManish Chopra 428cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 429cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 430cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 431cee4d264SManish Chopra 432cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 433cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 434cee4d264SManish Chopra 435cee4d264SManish Chopra p_ramrod->tx_mode.state = cpu_to_le16(state); 436cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 437cee4d264SManish Chopra "p_ramrod->tx_mode.state = 0x%x\n", state); 438cee4d264SManish Chopra } 439cee4d264SManish Chopra } 440cee4d264SManish Chopra 441cee4d264SManish Chopra static void 44217b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, 44317b235c1SYuval Mintz struct vport_update_ramrod_data *p_ramrod, 44417b235c1SYuval Mintz struct qed_sge_tpa_params *p_params) 44517b235c1SYuval Mintz { 44617b235c1SYuval Mintz struct eth_vport_tpa_param *p_tpa; 44717b235c1SYuval Mintz 44817b235c1SYuval Mintz if (!p_params) { 44917b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 45017b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = 0; 45117b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 45217b235c1SYuval Mintz return; 45317b235c1SYuval Mintz } 45417b235c1SYuval Mintz 45517b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; 45617b235c1SYuval Mintz p_tpa = &p_ramrod->tpa_param; 45717b235c1SYuval Mintz p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; 45817b235c1SYuval Mintz p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; 45917b235c1SYuval Mintz p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; 46017b235c1SYuval Mintz p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; 46117b235c1SYuval Mintz 46217b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; 46317b235c1SYuval Mintz p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 46417b235c1SYuval Mintz p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; 46517b235c1SYuval Mintz p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; 46617b235c1SYuval Mintz p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; 46717b235c1SYuval Mintz p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; 46817b235c1SYuval Mintz p_tpa->tpa_max_size = p_params->tpa_max_size; 46917b235c1SYuval Mintz p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; 47017b235c1SYuval Mintz p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; 47117b235c1SYuval Mintz } 47217b235c1SYuval Mintz 47317b235c1SYuval Mintz static void 474cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 475cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 476cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params) 477cee4d264SManish Chopra { 478cee4d264SManish Chopra int i; 479cee4d264SManish Chopra 480cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 481cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 482cee4d264SManish Chopra 48383aeb933SYuval Mintz if (!p_params->update_approx_mcast_flg) 48483aeb933SYuval Mintz return; 48583aeb933SYuval Mintz 486cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 487cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 488cee4d264SManish Chopra u32 *p_bins = (u32 *)p_params->bins; 489cee4d264SManish Chopra 49083aeb933SYuval Mintz p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]); 491cee4d264SManish Chopra } 492cee4d264SManish Chopra } 493cee4d264SManish Chopra 494dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 495cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params, 496cee4d264SManish Chopra enum spq_mode comp_mode, 497cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 498cee4d264SManish Chopra { 499cee4d264SManish Chopra struct qed_rss_params *p_rss_params = p_params->rss_params; 500cee4d264SManish Chopra struct vport_update_ramrod_data_cmn *p_cmn; 50106f56b81SYuval Mintz struct qed_sp_init_data init_data; 502cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 503cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 50417b235c1SYuval Mintz u8 abs_vport_id = 0, val; 505cee4d264SManish Chopra int rc = -EINVAL; 506cee4d264SManish Chopra 507dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 508dacd88d6SYuval Mintz rc = qed_vf_pf_vport_update(p_hwfn, p_params); 509dacd88d6SYuval Mintz return rc; 510dacd88d6SYuval Mintz } 511dacd88d6SYuval Mintz 512cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 5131a635e48SYuval Mintz if (rc) 514cee4d264SManish Chopra return rc; 515cee4d264SManish Chopra 51606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 51706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 51806f56b81SYuval Mintz init_data.opaque_fid = p_params->opaque_fid; 51906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 52006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 521cee4d264SManish Chopra 522cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 523cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 52406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 525cee4d264SManish Chopra if (rc) 526cee4d264SManish Chopra return rc; 527cee4d264SManish Chopra 528cee4d264SManish Chopra /* Copy input params to ramrod according to FW struct */ 529cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 530cee4d264SManish Chopra p_cmn = &p_ramrod->common; 531cee4d264SManish Chopra 532cee4d264SManish Chopra p_cmn->vport_id = abs_vport_id; 533cee4d264SManish Chopra p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 534cee4d264SManish Chopra p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 535cee4d264SManish Chopra p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 536cee4d264SManish Chopra p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 5373f9b4a69SYuval Mintz p_cmn->accept_any_vlan = p_params->accept_any_vlan; 53883aeb933SYuval Mintz val = p_params->update_accept_any_vlan_flg; 53983aeb933SYuval Mintz p_cmn->update_accept_any_vlan_flg = val; 54017b235c1SYuval Mintz 54117b235c1SYuval Mintz p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; 54217b235c1SYuval Mintz val = p_params->update_inner_vlan_removal_flg; 54317b235c1SYuval Mintz p_cmn->update_inner_vlan_removal_en_flg = val; 54408feecd7SYuval Mintz 54508feecd7SYuval Mintz p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; 54608feecd7SYuval Mintz val = p_params->update_default_vlan_enable_flg; 54708feecd7SYuval Mintz p_cmn->update_default_vlan_en_flg = val; 54808feecd7SYuval Mintz 54908feecd7SYuval Mintz p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); 55008feecd7SYuval Mintz p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; 55108feecd7SYuval Mintz 55208feecd7SYuval Mintz p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; 55308feecd7SYuval Mintz 55417b235c1SYuval Mintz p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; 55517b235c1SYuval Mintz p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; 55617b235c1SYuval Mintz 5576ddc7608SYuval Mintz p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; 5586ddc7608SYuval Mintz val = p_params->update_anti_spoofing_en_flg; 5596ddc7608SYuval Mintz p_ramrod->common.update_anti_spoofing_en_flg = val; 5606ddc7608SYuval Mintz 561cee4d264SManish Chopra rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 562cee4d264SManish Chopra if (rc) { 563cee4d264SManish Chopra /* Return spq entry which is taken in qed_sp_init_request()*/ 564cee4d264SManish Chopra qed_spq_return_entry(p_hwfn, p_ent); 565cee4d264SManish Chopra return rc; 566cee4d264SManish Chopra } 567cee4d264SManish Chopra 568cee4d264SManish Chopra /* Update mcast bins for VFs, PF doesn't use this functionality */ 569cee4d264SManish Chopra qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 570cee4d264SManish Chopra 571cee4d264SManish Chopra qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 57217b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); 573cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 574cee4d264SManish Chopra } 575cee4d264SManish Chopra 576dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) 577cee4d264SManish Chopra { 578cee4d264SManish Chopra struct vport_stop_ramrod_data *p_ramrod; 57906f56b81SYuval Mintz struct qed_sp_init_data init_data; 580cee4d264SManish Chopra struct qed_spq_entry *p_ent; 581cee4d264SManish Chopra u8 abs_vport_id = 0; 582cee4d264SManish Chopra int rc; 583cee4d264SManish Chopra 584dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 585dacd88d6SYuval Mintz return qed_vf_pf_vport_stop(p_hwfn); 586dacd88d6SYuval Mintz 587cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 5881a635e48SYuval Mintz if (rc) 589cee4d264SManish Chopra return rc; 590cee4d264SManish Chopra 59106f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 59206f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 59306f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 59406f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 595cee4d264SManish Chopra 596cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 597cee4d264SManish Chopra ETH_RAMROD_VPORT_STOP, 59806f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 599cee4d264SManish Chopra if (rc) 600cee4d264SManish Chopra return rc; 601cee4d264SManish Chopra 602cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_stop; 603cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 604cee4d264SManish Chopra 605cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 606cee4d264SManish Chopra } 607cee4d264SManish Chopra 608dacd88d6SYuval Mintz static int 609dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, 610dacd88d6SYuval Mintz struct qed_filter_accept_flags *p_accept_flags) 611dacd88d6SYuval Mintz { 612dacd88d6SYuval Mintz struct qed_sp_vport_update_params s_params; 613dacd88d6SYuval Mintz 614dacd88d6SYuval Mintz memset(&s_params, 0, sizeof(s_params)); 615dacd88d6SYuval Mintz memcpy(&s_params.accept_flags, p_accept_flags, 616dacd88d6SYuval Mintz sizeof(struct qed_filter_accept_flags)); 617dacd88d6SYuval Mintz 618dacd88d6SYuval Mintz return qed_vf_pf_vport_update(p_hwfn, &s_params); 619dacd88d6SYuval Mintz } 620dacd88d6SYuval Mintz 621cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev, 622cee4d264SManish Chopra u8 vport, 623cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags, 6243f9b4a69SYuval Mintz u8 update_accept_any_vlan, 6253f9b4a69SYuval Mintz u8 accept_any_vlan, 626cee4d264SManish Chopra enum spq_mode comp_mode, 627cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 628cee4d264SManish Chopra { 629cee4d264SManish Chopra struct qed_sp_vport_update_params vport_update_params; 630cee4d264SManish Chopra int i, rc; 631cee4d264SManish Chopra 632cee4d264SManish Chopra /* Prepare and send the vport rx_mode change */ 633cee4d264SManish Chopra memset(&vport_update_params, 0, sizeof(vport_update_params)); 634cee4d264SManish Chopra vport_update_params.vport_id = vport; 635cee4d264SManish Chopra vport_update_params.accept_flags = accept_flags; 6363f9b4a69SYuval Mintz vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 6373f9b4a69SYuval Mintz vport_update_params.accept_any_vlan = accept_any_vlan; 638cee4d264SManish Chopra 639cee4d264SManish Chopra for_each_hwfn(cdev, i) { 640cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 641cee4d264SManish Chopra 642cee4d264SManish Chopra vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 643cee4d264SManish Chopra 644dacd88d6SYuval Mintz if (IS_VF(cdev)) { 645dacd88d6SYuval Mintz rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); 646dacd88d6SYuval Mintz if (rc) 647dacd88d6SYuval Mintz return rc; 648dacd88d6SYuval Mintz continue; 649dacd88d6SYuval Mintz } 650dacd88d6SYuval Mintz 651cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 652cee4d264SManish Chopra comp_mode, p_comp_data); 6531a635e48SYuval Mintz if (rc) { 654cee4d264SManish Chopra DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 655cee4d264SManish Chopra return rc; 656cee4d264SManish Chopra } 657cee4d264SManish Chopra 658cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 659cee4d264SManish Chopra "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 660cee4d264SManish Chopra accept_flags.rx_accept_filter, 661cee4d264SManish Chopra accept_flags.tx_accept_filter); 6623f9b4a69SYuval Mintz if (update_accept_any_vlan) 6633f9b4a69SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 6643f9b4a69SYuval Mintz "accept_any_vlan=%d configured\n", 6653f9b4a69SYuval Mintz accept_any_vlan); 666cee4d264SManish Chopra } 667cee4d264SManish Chopra 668cee4d264SManish Chopra return 0; 669cee4d264SManish Chopra } 670cee4d264SManish Chopra 6713da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 6723da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 673cee4d264SManish Chopra u16 bd_max_bytes, 674cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 6753da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size) 676cee4d264SManish Chopra { 677cee4d264SManish Chopra struct rx_queue_start_ramrod_data *p_ramrod = NULL; 678cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 67906f56b81SYuval Mintz struct qed_sp_init_data init_data; 680cee4d264SManish Chopra int rc = -EINVAL; 681cee4d264SManish Chopra 682cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 6833da7a37aSMintz, Yuval "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n", 6843da7a37aSMintz, Yuval p_cid->opaque_fid, p_cid->cid, 6853da7a37aSMintz, Yuval p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->abs.sb); 686cee4d264SManish Chopra 68706f56b81SYuval Mintz /* Get SPQ entry */ 68806f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 6893da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 6903da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 69106f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 692cee4d264SManish Chopra 693cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 694cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_START, 69506f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 696cee4d264SManish Chopra if (rc) 697cee4d264SManish Chopra return rc; 698cee4d264SManish Chopra 699cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_start; 700cee4d264SManish Chopra 7013da7a37aSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb); 7023da7a37aSMintz, Yuval p_ramrod->sb_index = p_cid->abs.sb_idx; 7033da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 7043da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 7053da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 706cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 0; 707cee4d264SManish Chopra p_ramrod->complete_event_flg = 1; 708cee4d264SManish Chopra 709cee4d264SManish Chopra p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 71094494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 711cee4d264SManish Chopra 712cee4d264SManish Chopra p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 71394494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 714cee4d264SManish Chopra 7153da7a37aSMintz, Yuval if (p_cid->is_vf) { 7163da7a37aSMintz, Yuval p_ramrod->vf_rx_prod_index = p_cid->vf_qid; 717351a4dedSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 718a044df83SYuval Mintz "Queue%s is meant for VF rxq[%02x]\n", 7193da7a37aSMintz, Yuval !!p_cid->b_legacy_vf ? " [legacy]" : "", 7203da7a37aSMintz, Yuval p_cid->vf_qid); 7213da7a37aSMintz, Yuval p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf; 722a044df83SYuval Mintz } 723cee4d264SManish Chopra 724351a4dedSYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 725cee4d264SManish Chopra } 726cee4d264SManish Chopra 727cee4d264SManish Chopra static int 7283da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn, 7293da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 730cee4d264SManish Chopra u16 bd_max_bytes, 731cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 732cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 733dacd88d6SYuval Mintz u16 cqe_pbl_size, void __iomem **pp_prod) 734cee4d264SManish Chopra { 735b21290b7SYuval Mintz u32 init_prod_val = 0; 736cee4d264SManish Chopra 7373da7a37aSMintz, Yuval *pp_prod = p_hwfn->regview + 738cee4d264SManish Chopra GTT_BAR0_MAP_REG_MSDM_RAM + 7393da7a37aSMintz, Yuval MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); 740cee4d264SManish Chopra 741cee4d264SManish Chopra /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 742b21290b7SYuval Mintz __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), 743cee4d264SManish Chopra (u32 *)(&init_prod_val)); 744cee4d264SManish Chopra 7453da7a37aSMintz, Yuval return qed_eth_rxq_start_ramrod(p_hwfn, p_cid, 746cee4d264SManish Chopra bd_max_bytes, 747cee4d264SManish Chopra bd_chain_phys_addr, 7483da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size); 7493da7a37aSMintz, Yuval } 750cee4d264SManish Chopra 7513da7a37aSMintz, Yuval static int 7523da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 7533da7a37aSMintz, Yuval u16 opaque_fid, 7543da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 7553da7a37aSMintz, Yuval u16 bd_max_bytes, 7563da7a37aSMintz, Yuval dma_addr_t bd_chain_phys_addr, 7573da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, 7583da7a37aSMintz, Yuval u16 cqe_pbl_size, 7593da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *p_ret_params) 7603da7a37aSMintz, Yuval { 7613da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 7623da7a37aSMintz, Yuval int rc; 7633da7a37aSMintz, Yuval 7643da7a37aSMintz, Yuval /* Allocate a CID for the queue */ 7653da7a37aSMintz, Yuval p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params); 7663da7a37aSMintz, Yuval if (!p_cid) 7673da7a37aSMintz, Yuval return -ENOMEM; 7683da7a37aSMintz, Yuval 7693da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 7703da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid, 7713da7a37aSMintz, Yuval bd_max_bytes, 7723da7a37aSMintz, Yuval bd_chain_phys_addr, 7733da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, 7743da7a37aSMintz, Yuval &p_ret_params->p_prod); 7753da7a37aSMintz, Yuval } else { 7763da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_start(p_hwfn, p_cid, 7773da7a37aSMintz, Yuval bd_max_bytes, 7783da7a37aSMintz, Yuval bd_chain_phys_addr, 7793da7a37aSMintz, Yuval cqe_pbl_addr, 7803da7a37aSMintz, Yuval cqe_pbl_size, &p_ret_params->p_prod); 7813da7a37aSMintz, Yuval } 7823da7a37aSMintz, Yuval 7833da7a37aSMintz, Yuval /* Provide the caller with a reference to as handler */ 7841a635e48SYuval Mintz if (rc) 7853da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 7863da7a37aSMintz, Yuval else 7873da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 788cee4d264SManish Chopra 789cee4d264SManish Chopra return rc; 790cee4d264SManish Chopra } 791cee4d264SManish Chopra 79217b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 7933da7a37aSMintz, Yuval void **pp_rxq_handles, 79417b235c1SYuval Mintz u8 num_rxqs, 79517b235c1SYuval Mintz u8 complete_cqe_flg, 79617b235c1SYuval Mintz u8 complete_event_flg, 79717b235c1SYuval Mintz enum spq_mode comp_mode, 79817b235c1SYuval Mintz struct qed_spq_comp_cb *p_comp_data) 79917b235c1SYuval Mintz { 80017b235c1SYuval Mintz struct rx_queue_update_ramrod_data *p_ramrod = NULL; 80117b235c1SYuval Mintz struct qed_spq_entry *p_ent = NULL; 80217b235c1SYuval Mintz struct qed_sp_init_data init_data; 8033da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 80417b235c1SYuval Mintz int rc = -EINVAL; 80517b235c1SYuval Mintz u8 i; 80617b235c1SYuval Mintz 80717b235c1SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 80817b235c1SYuval Mintz init_data.comp_mode = comp_mode; 80917b235c1SYuval Mintz init_data.p_comp_data = p_comp_data; 81017b235c1SYuval Mintz 81117b235c1SYuval Mintz for (i = 0; i < num_rxqs; i++) { 8123da7a37aSMintz, Yuval p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i]; 81317b235c1SYuval Mintz 81417b235c1SYuval Mintz /* Get SPQ entry */ 8153da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 8163da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 81717b235c1SYuval Mintz 81817b235c1SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 81917b235c1SYuval Mintz ETH_RAMROD_RX_QUEUE_UPDATE, 82017b235c1SYuval Mintz PROTOCOLID_ETH, &init_data); 82117b235c1SYuval Mintz if (rc) 82217b235c1SYuval Mintz return rc; 82317b235c1SYuval Mintz 82417b235c1SYuval Mintz p_ramrod = &p_ent->ramrod.rx_queue_update; 8253da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 82617b235c1SYuval Mintz 8273da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 82817b235c1SYuval Mintz p_ramrod->complete_cqe_flg = complete_cqe_flg; 82917b235c1SYuval Mintz p_ramrod->complete_event_flg = complete_event_flg; 83017b235c1SYuval Mintz 83117b235c1SYuval Mintz rc = qed_spq_post(p_hwfn, p_ent, NULL); 83217b235c1SYuval Mintz if (rc) 83317b235c1SYuval Mintz return rc; 83417b235c1SYuval Mintz } 83517b235c1SYuval Mintz 83617b235c1SYuval Mintz return rc; 83717b235c1SYuval Mintz } 83817b235c1SYuval Mintz 8393da7a37aSMintz, Yuval static int 8403da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn, 8413da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 8423da7a37aSMintz, Yuval bool b_eq_completion_only, bool b_cqe_completion) 843cee4d264SManish Chopra { 844cee4d264SManish Chopra struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 845cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 84606f56b81SYuval Mintz struct qed_sp_init_data init_data; 8473da7a37aSMintz, Yuval int rc; 848cee4d264SManish Chopra 84906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 8503da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 8513da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 85206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 853cee4d264SManish Chopra 854cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 855cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_STOP, 85606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 857cee4d264SManish Chopra if (rc) 858cee4d264SManish Chopra return rc; 859cee4d264SManish Chopra 860cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_stop; 8613da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 8623da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 863cee4d264SManish Chopra 864cee4d264SManish Chopra /* Cleaning the queue requires the completion to arrive there. 865cee4d264SManish Chopra * In addition, VFs require the answer to come as eqe to PF. 866cee4d264SManish Chopra */ 8673da7a37aSMintz, Yuval p_ramrod->complete_cqe_flg = (!p_cid->is_vf && 8683da7a37aSMintz, Yuval !b_eq_completion_only) || 8693da7a37aSMintz, Yuval b_cqe_completion; 8703da7a37aSMintz, Yuval p_ramrod->complete_event_flg = p_cid->is_vf || b_eq_completion_only; 871cee4d264SManish Chopra 8723da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 873cee4d264SManish Chopra } 874cee4d264SManish Chopra 8753da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 8763da7a37aSMintz, Yuval void *p_rxq, 8773da7a37aSMintz, Yuval bool eq_completion_only, bool cqe_completion) 8783da7a37aSMintz, Yuval { 8793da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq; 8803da7a37aSMintz, Yuval int rc = -EINVAL; 8813da7a37aSMintz, Yuval 8823da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 8833da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid, 8843da7a37aSMintz, Yuval eq_completion_only, 8853da7a37aSMintz, Yuval cqe_completion); 8863da7a37aSMintz, Yuval else 8873da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion); 8883da7a37aSMintz, Yuval 8893da7a37aSMintz, Yuval if (!rc) 8903da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 8913da7a37aSMintz, Yuval return rc; 8923da7a37aSMintz, Yuval } 8933da7a37aSMintz, Yuval 8943da7a37aSMintz, Yuval int 8953da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 8963da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 8973da7a37aSMintz, Yuval dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id) 898cee4d264SManish Chopra { 899cee4d264SManish Chopra struct tx_queue_start_ramrod_data *p_ramrod = NULL; 900cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 90106f56b81SYuval Mintz struct qed_sp_init_data init_data; 902cee4d264SManish Chopra int rc = -EINVAL; 903351a4dedSYuval Mintz 90406f56b81SYuval Mintz /* Get SPQ entry */ 90506f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 9063da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 9073da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 90806f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 909cee4d264SManish Chopra 91006f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 911cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_START, 91206f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 913cee4d264SManish Chopra if (rc) 914cee4d264SManish Chopra return rc; 915cee4d264SManish Chopra 916cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.tx_queue_start; 9173da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 918cee4d264SManish Chopra 9193da7a37aSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb); 9203da7a37aSMintz, Yuval p_ramrod->sb_index = p_cid->abs.sb_idx; 9213da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 922cee4d264SManish Chopra 9233da7a37aSMintz, Yuval p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id); 9243da7a37aSMintz, Yuval p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id); 9251a635e48SYuval Mintz 926cee4d264SManish Chopra p_ramrod->pbl_size = cpu_to_le16(pbl_size); 92794494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 928cee4d264SManish Chopra 929cee4d264SManish Chopra p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 930cee4d264SManish Chopra 931cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 932cee4d264SManish Chopra } 933cee4d264SManish Chopra 934cee4d264SManish Chopra static int 9353da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn, 9363da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 9373da7a37aSMintz, Yuval u8 tc, 938cee4d264SManish Chopra dma_addr_t pbl_addr, 939dacd88d6SYuval Mintz u16 pbl_size, void __iomem **pp_doorbell) 940cee4d264SManish Chopra { 941cee4d264SManish Chopra int rc; 942cee4d264SManish Chopra 943cee4d264SManish Chopra 9443da7a37aSMintz, Yuval rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid, 9453da7a37aSMintz, Yuval pbl_addr, pbl_size, 946b5a9ee7cSAriel Elior qed_get_cm_pq_idx_mcos(p_hwfn, tc)); 9473da7a37aSMintz, Yuval if (rc) 948cee4d264SManish Chopra return rc; 9493da7a37aSMintz, Yuval 9503da7a37aSMintz, Yuval /* Provide the caller with the necessary return values */ 9513da7a37aSMintz, Yuval *pp_doorbell = p_hwfn->doorbells + 9523da7a37aSMintz, Yuval qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY); 9533da7a37aSMintz, Yuval 9543da7a37aSMintz, Yuval return 0; 955cee4d264SManish Chopra } 956cee4d264SManish Chopra 9573da7a37aSMintz, Yuval static int 9583da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 9593da7a37aSMintz, Yuval u16 opaque_fid, 9603da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 9613da7a37aSMintz, Yuval u8 tc, 9623da7a37aSMintz, Yuval dma_addr_t pbl_addr, 9633da7a37aSMintz, Yuval u16 pbl_size, 9643da7a37aSMintz, Yuval struct qed_txq_start_ret_params *p_ret_params) 9653da7a37aSMintz, Yuval { 9663da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 9673da7a37aSMintz, Yuval int rc; 968cee4d264SManish Chopra 9693da7a37aSMintz, Yuval p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params); 9703da7a37aSMintz, Yuval if (!p_cid) 9713da7a37aSMintz, Yuval return -EINVAL; 972cee4d264SManish Chopra 9733da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 9743da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc, 9753da7a37aSMintz, Yuval pbl_addr, pbl_size, 9763da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 9773da7a37aSMintz, Yuval else 9783da7a37aSMintz, Yuval rc = qed_vf_pf_txq_start(p_hwfn, p_cid, 9793da7a37aSMintz, Yuval pbl_addr, pbl_size, 9803da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 981cee4d264SManish Chopra 982cee4d264SManish Chopra if (rc) 9833da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 9843da7a37aSMintz, Yuval else 9853da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 986cee4d264SManish Chopra 987cee4d264SManish Chopra return rc; 988cee4d264SManish Chopra } 989cee4d264SManish Chopra 9903da7a37aSMintz, Yuval static int 9913da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid) 992cee4d264SManish Chopra { 993cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 99406f56b81SYuval Mintz struct qed_sp_init_data init_data; 9953da7a37aSMintz, Yuval int rc; 996cee4d264SManish Chopra 99706f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 9983da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 9993da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 100006f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1001cee4d264SManish Chopra 1002cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1003cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_STOP, 100406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1005cee4d264SManish Chopra if (rc) 1006cee4d264SManish Chopra return rc; 1007cee4d264SManish Chopra 10083da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 10093da7a37aSMintz, Yuval } 1010cee4d264SManish Chopra 10113da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle) 10123da7a37aSMintz, Yuval { 10133da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle; 10143da7a37aSMintz, Yuval int rc; 10153da7a37aSMintz, Yuval 10163da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 10173da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid); 10183da7a37aSMintz, Yuval else 10193da7a37aSMintz, Yuval rc = qed_vf_pf_txq_stop(p_hwfn, p_cid); 10203da7a37aSMintz, Yuval 10213da7a37aSMintz, Yuval if (!rc) 10223da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 10233da7a37aSMintz, Yuval return rc; 1024cee4d264SManish Chopra } 1025cee4d264SManish Chopra 10261a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode) 1027cee4d264SManish Chopra { 1028cee4d264SManish Chopra enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 1029cee4d264SManish Chopra 1030cee4d264SManish Chopra switch (opcode) { 1031cee4d264SManish Chopra case QED_FILTER_ADD: 1032cee4d264SManish Chopra action = ETH_FILTER_ACTION_ADD; 1033cee4d264SManish Chopra break; 1034cee4d264SManish Chopra case QED_FILTER_REMOVE: 1035cee4d264SManish Chopra action = ETH_FILTER_ACTION_REMOVE; 1036cee4d264SManish Chopra break; 1037cee4d264SManish Chopra case QED_FILTER_FLUSH: 1038fc48b7a6SYuval Mintz action = ETH_FILTER_ACTION_REMOVE_ALL; 1039cee4d264SManish Chopra break; 1040cee4d264SManish Chopra default: 1041cee4d264SManish Chopra action = MAX_ETH_FILTER_ACTION; 1042cee4d264SManish Chopra } 1043cee4d264SManish Chopra 1044cee4d264SManish Chopra return action; 1045cee4d264SManish Chopra } 1046cee4d264SManish Chopra 1047cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb, 1048cee4d264SManish Chopra __le16 *fw_mid, 1049cee4d264SManish Chopra __le16 *fw_lsb, 1050cee4d264SManish Chopra u8 *mac) 1051cee4d264SManish Chopra { 1052cee4d264SManish Chopra ((u8 *)fw_msb)[0] = mac[1]; 1053cee4d264SManish Chopra ((u8 *)fw_msb)[1] = mac[0]; 1054cee4d264SManish Chopra ((u8 *)fw_mid)[0] = mac[3]; 1055cee4d264SManish Chopra ((u8 *)fw_mid)[1] = mac[2]; 1056cee4d264SManish Chopra ((u8 *)fw_lsb)[0] = mac[5]; 1057cee4d264SManish Chopra ((u8 *)fw_lsb)[1] = mac[4]; 1058cee4d264SManish Chopra } 1059cee4d264SManish Chopra 1060cee4d264SManish Chopra static int 1061cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 1062cee4d264SManish Chopra u16 opaque_fid, 1063cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1064cee4d264SManish Chopra struct vport_filter_update_ramrod_data **pp_ramrod, 1065cee4d264SManish Chopra struct qed_spq_entry **pp_ent, 1066cee4d264SManish Chopra enum spq_mode comp_mode, 1067cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1068cee4d264SManish Chopra { 1069cee4d264SManish Chopra u8 vport_to_add_to = 0, vport_to_remove_from = 0; 1070cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod; 1071cee4d264SManish Chopra struct eth_filter_cmd *p_first_filter; 1072cee4d264SManish Chopra struct eth_filter_cmd *p_second_filter; 107306f56b81SYuval Mintz struct qed_sp_init_data init_data; 1074cee4d264SManish Chopra enum eth_filter_action action; 1075cee4d264SManish Chopra int rc; 1076cee4d264SManish Chopra 1077cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1078cee4d264SManish Chopra &vport_to_remove_from); 1079cee4d264SManish Chopra if (rc) 1080cee4d264SManish Chopra return rc; 1081cee4d264SManish Chopra 1082cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1083cee4d264SManish Chopra &vport_to_add_to); 1084cee4d264SManish Chopra if (rc) 1085cee4d264SManish Chopra return rc; 1086cee4d264SManish Chopra 108706f56b81SYuval Mintz /* Get SPQ entry */ 108806f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 108906f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 109006f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 109106f56b81SYuval Mintz init_data.comp_mode = comp_mode; 109206f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1093cee4d264SManish Chopra 1094cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, pp_ent, 1095cee4d264SManish Chopra ETH_RAMROD_FILTERS_UPDATE, 109606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1097cee4d264SManish Chopra if (rc) 1098cee4d264SManish Chopra return rc; 1099cee4d264SManish Chopra 1100cee4d264SManish Chopra *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 1101cee4d264SManish Chopra p_ramrod = *pp_ramrod; 1102cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 1103cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 1104cee4d264SManish Chopra 1105cee4d264SManish Chopra switch (p_filter_cmd->opcode) { 1106fc48b7a6SYuval Mintz case QED_FILTER_REPLACE: 1107cee4d264SManish Chopra case QED_FILTER_MOVE: 1108cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 1109cee4d264SManish Chopra default: 1110cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 1111cee4d264SManish Chopra } 1112cee4d264SManish Chopra 1113cee4d264SManish Chopra p_first_filter = &p_ramrod->filter_cmds[0]; 1114cee4d264SManish Chopra p_second_filter = &p_ramrod->filter_cmds[1]; 1115cee4d264SManish Chopra 1116cee4d264SManish Chopra switch (p_filter_cmd->type) { 1117cee4d264SManish Chopra case QED_FILTER_MAC: 1118cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 1119cee4d264SManish Chopra case QED_FILTER_VLAN: 1120cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 1121cee4d264SManish Chopra case QED_FILTER_MAC_VLAN: 1122cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 1123cee4d264SManish Chopra case QED_FILTER_INNER_MAC: 1124cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 1125cee4d264SManish Chopra case QED_FILTER_INNER_VLAN: 1126cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 1127cee4d264SManish Chopra case QED_FILTER_INNER_PAIR: 1128cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 1129cee4d264SManish Chopra case QED_FILTER_INNER_MAC_VNI_PAIR: 1130cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 1131cee4d264SManish Chopra break; 1132cee4d264SManish Chopra case QED_FILTER_MAC_VNI_PAIR: 1133cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 1134cee4d264SManish Chopra case QED_FILTER_VNI: 1135cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 1136cee4d264SManish Chopra } 1137cee4d264SManish Chopra 1138cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 1139cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1140cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 1141cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 1142cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1143cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 1144cee4d264SManish Chopra qed_set_fw_mac_addr(&p_first_filter->mac_msb, 1145cee4d264SManish Chopra &p_first_filter->mac_mid, 1146cee4d264SManish Chopra &p_first_filter->mac_lsb, 1147cee4d264SManish Chopra (u8 *)p_filter_cmd->mac); 1148cee4d264SManish Chopra } 1149cee4d264SManish Chopra 1150cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 1151cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1152cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 1153cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 1154cee4d264SManish Chopra p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 1155cee4d264SManish Chopra 1156cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1157cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 1158cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 1159cee4d264SManish Chopra p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 1160cee4d264SManish Chopra 1161cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 1162cee4d264SManish Chopra p_second_filter->type = p_first_filter->type; 1163cee4d264SManish Chopra p_second_filter->mac_msb = p_first_filter->mac_msb; 1164cee4d264SManish Chopra p_second_filter->mac_mid = p_first_filter->mac_mid; 1165cee4d264SManish Chopra p_second_filter->mac_lsb = p_first_filter->mac_lsb; 1166cee4d264SManish Chopra p_second_filter->vlan_id = p_first_filter->vlan_id; 1167cee4d264SManish Chopra p_second_filter->vni = p_first_filter->vni; 1168cee4d264SManish Chopra 1169cee4d264SManish Chopra p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 1170cee4d264SManish Chopra 1171cee4d264SManish Chopra p_first_filter->vport_id = vport_to_remove_from; 1172cee4d264SManish Chopra 1173cee4d264SManish Chopra p_second_filter->action = ETH_FILTER_ACTION_ADD; 1174cee4d264SManish Chopra p_second_filter->vport_id = vport_to_add_to; 1175fc48b7a6SYuval Mintz } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 1176fc48b7a6SYuval Mintz p_first_filter->vport_id = vport_to_add_to; 1177fc48b7a6SYuval Mintz memcpy(p_second_filter, p_first_filter, 1178fc48b7a6SYuval Mintz sizeof(*p_second_filter)); 1179fc48b7a6SYuval Mintz p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 1180fc48b7a6SYuval Mintz p_second_filter->action = ETH_FILTER_ACTION_ADD; 1181cee4d264SManish Chopra } else { 1182cee4d264SManish Chopra action = qed_filter_action(p_filter_cmd->opcode); 1183cee4d264SManish Chopra 1184cee4d264SManish Chopra if (action == MAX_ETH_FILTER_ACTION) { 1185cee4d264SManish Chopra DP_NOTICE(p_hwfn, 1186cee4d264SManish Chopra "%d is not supported yet\n", 1187cee4d264SManish Chopra p_filter_cmd->opcode); 1188cee4d264SManish Chopra return -EINVAL; 1189cee4d264SManish Chopra } 1190cee4d264SManish Chopra 1191cee4d264SManish Chopra p_first_filter->action = action; 1192cee4d264SManish Chopra p_first_filter->vport_id = (p_filter_cmd->opcode == 1193cee4d264SManish Chopra QED_FILTER_REMOVE) ? 1194cee4d264SManish Chopra vport_to_remove_from : 1195cee4d264SManish Chopra vport_to_add_to; 1196cee4d264SManish Chopra } 1197cee4d264SManish Chopra 1198cee4d264SManish Chopra return 0; 1199cee4d264SManish Chopra } 1200cee4d264SManish Chopra 1201dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 1202cee4d264SManish Chopra u16 opaque_fid, 1203cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1204cee4d264SManish Chopra enum spq_mode comp_mode, 1205cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1206cee4d264SManish Chopra { 1207cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod = NULL; 1208cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 1209cee4d264SManish Chopra struct eth_filter_cmd_header *p_header; 1210cee4d264SManish Chopra int rc; 1211cee4d264SManish Chopra 1212cee4d264SManish Chopra rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1213cee4d264SManish Chopra &p_ramrod, &p_ent, 1214cee4d264SManish Chopra comp_mode, p_comp_data); 12151a635e48SYuval Mintz if (rc) { 1216cee4d264SManish Chopra DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1217cee4d264SManish Chopra return rc; 1218cee4d264SManish Chopra } 1219cee4d264SManish Chopra p_header = &p_ramrod->filter_cmd_hdr; 1220cee4d264SManish Chopra p_header->assert_on_error = p_filter_cmd->assert_on_error; 1221cee4d264SManish Chopra 1222cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 12231a635e48SYuval Mintz if (rc) { 12241a635e48SYuval Mintz DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc); 1225cee4d264SManish Chopra return rc; 1226cee4d264SManish Chopra } 1227cee4d264SManish Chopra 1228cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1229cee4d264SManish Chopra "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1230cee4d264SManish Chopra (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1231cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1232cee4d264SManish Chopra "REMOVE" : 1233cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1234cee4d264SManish Chopra "MOVE" : "REPLACE")), 1235cee4d264SManish Chopra (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1236cee4d264SManish Chopra ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1237cee4d264SManish Chopra "VLAN" : "MAC & VLAN"), 1238cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt, 1239cee4d264SManish Chopra p_filter_cmd->is_rx_filter, 1240cee4d264SManish Chopra p_filter_cmd->is_tx_filter); 1241cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1242cee4d264SManish Chopra "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1243cee4d264SManish Chopra p_filter_cmd->vport_to_add_to, 1244cee4d264SManish Chopra p_filter_cmd->vport_to_remove_from, 1245cee4d264SManish Chopra p_filter_cmd->mac[0], 1246cee4d264SManish Chopra p_filter_cmd->mac[1], 1247cee4d264SManish Chopra p_filter_cmd->mac[2], 1248cee4d264SManish Chopra p_filter_cmd->mac[3], 1249cee4d264SManish Chopra p_filter_cmd->mac[4], 1250cee4d264SManish Chopra p_filter_cmd->mac[5], 1251cee4d264SManish Chopra p_filter_cmd->vlan); 1252cee4d264SManish Chopra 1253cee4d264SManish Chopra return 0; 1254cee4d264SManish Chopra } 1255cee4d264SManish Chopra 1256cee4d264SManish Chopra /******************************************************************************* 1257cee4d264SManish Chopra * Description: 1258cee4d264SManish Chopra * Calculates crc 32 on a buffer 1259cee4d264SManish Chopra * Note: crc32_length MUST be aligned to 8 1260cee4d264SManish Chopra * Return: 1261cee4d264SManish Chopra ******************************************************************************/ 1262cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet, 12631a635e48SYuval Mintz u32 crc32_length, u32 crc32_seed, u8 complement) 1264cee4d264SManish Chopra { 12651a635e48SYuval Mintz u32 byte = 0, bit = 0, crc32_result = crc32_seed; 12661a635e48SYuval Mintz u8 msb = 0, current_byte = 0; 1267cee4d264SManish Chopra 1268cee4d264SManish Chopra if ((!crc32_packet) || 1269cee4d264SManish Chopra (crc32_length == 0) || 1270cee4d264SManish Chopra ((crc32_length % 8) != 0)) 1271cee4d264SManish Chopra return crc32_result; 1272cee4d264SManish Chopra for (byte = 0; byte < crc32_length; byte++) { 1273cee4d264SManish Chopra current_byte = crc32_packet[byte]; 1274cee4d264SManish Chopra for (bit = 0; bit < 8; bit++) { 1275cee4d264SManish Chopra msb = (u8)(crc32_result >> 31); 1276cee4d264SManish Chopra crc32_result = crc32_result << 1; 1277cee4d264SManish Chopra if (msb != (0x1 & (current_byte >> bit))) { 1278cee4d264SManish Chopra crc32_result = crc32_result ^ CRC32_POLY; 1279cee4d264SManish Chopra crc32_result |= 1; /*crc32_result[0] = 1;*/ 1280cee4d264SManish Chopra } 1281cee4d264SManish Chopra } 1282cee4d264SManish Chopra } 1283cee4d264SManish Chopra return crc32_result; 1284cee4d264SManish Chopra } 1285cee4d264SManish Chopra 12861a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len) 1287cee4d264SManish Chopra { 1288cee4d264SManish Chopra u32 packet_buf[2] = { 0 }; 1289cee4d264SManish Chopra 1290cee4d264SManish Chopra memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1291cee4d264SManish Chopra return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1292cee4d264SManish Chopra } 1293cee4d264SManish Chopra 1294dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac) 1295cee4d264SManish Chopra { 1296cee4d264SManish Chopra u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1297cee4d264SManish Chopra mac, ETH_ALEN); 1298cee4d264SManish Chopra 1299cee4d264SManish Chopra return crc & 0xff; 1300cee4d264SManish Chopra } 1301cee4d264SManish Chopra 1302cee4d264SManish Chopra static int 1303cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1304cee4d264SManish Chopra u16 opaque_fid, 1305cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1306cee4d264SManish Chopra enum spq_mode comp_mode, 1307cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1308cee4d264SManish Chopra { 1309cee4d264SManish Chopra unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1310cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 1311cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 131206f56b81SYuval Mintz struct qed_sp_init_data init_data; 1313cee4d264SManish Chopra u8 abs_vport_id = 0; 1314cee4d264SManish Chopra int rc, i; 1315cee4d264SManish Chopra 131683aeb933SYuval Mintz if (p_filter_cmd->opcode == QED_FILTER_ADD) 1317cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1318cee4d264SManish Chopra &abs_vport_id); 131983aeb933SYuval Mintz else 1320cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1321cee4d264SManish Chopra &abs_vport_id); 1322cee4d264SManish Chopra if (rc) 1323cee4d264SManish Chopra return rc; 1324cee4d264SManish Chopra 132506f56b81SYuval Mintz /* Get SPQ entry */ 132606f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 132706f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 132806f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 132906f56b81SYuval Mintz init_data.comp_mode = comp_mode; 133006f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1331cee4d264SManish Chopra 1332cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1333cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 133406f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1335cee4d264SManish Chopra if (rc) { 1336cee4d264SManish Chopra DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1337cee4d264SManish Chopra return rc; 1338cee4d264SManish Chopra } 1339cee4d264SManish Chopra 1340cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 1341cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 1342cee4d264SManish Chopra 1343cee4d264SManish Chopra /* explicitly clear out the entire vector */ 1344cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 1345cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 1346cee4d264SManish Chopra memset(bins, 0, sizeof(unsigned long) * 1347cee4d264SManish Chopra ETH_MULTICAST_MAC_BINS_IN_REGS); 1348cee4d264SManish Chopra /* filter ADD op is explicit set op and it removes 1349cee4d264SManish Chopra * any existing filters for the vport 1350cee4d264SManish Chopra */ 1351cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1352cee4d264SManish Chopra for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 1353cee4d264SManish Chopra u32 bit; 1354cee4d264SManish Chopra 1355cee4d264SManish Chopra bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 1356cee4d264SManish Chopra __set_bit(bit, bins); 1357cee4d264SManish Chopra } 1358cee4d264SManish Chopra 1359cee4d264SManish Chopra /* Convert to correct endianity */ 1360cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 13611a635e48SYuval Mintz struct vport_update_ramrod_mcast *p_ramrod_bins; 1362cee4d264SManish Chopra u32 *p_bins = (u32 *)bins; 1363cee4d264SManish Chopra 13641a635e48SYuval Mintz p_ramrod_bins = &p_ramrod->approx_mcast; 13651a635e48SYuval Mintz p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]); 1366cee4d264SManish Chopra } 1367cee4d264SManish Chopra } 1368cee4d264SManish Chopra 1369cee4d264SManish Chopra p_ramrod->common.vport_id = abs_vport_id; 1370cee4d264SManish Chopra 1371cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1372cee4d264SManish Chopra } 1373cee4d264SManish Chopra 1374dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev, 1375cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1376cee4d264SManish Chopra enum spq_mode comp_mode, 1377cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1378cee4d264SManish Chopra { 1379cee4d264SManish Chopra int rc = 0; 1380cee4d264SManish Chopra int i; 1381cee4d264SManish Chopra 1382cee4d264SManish Chopra /* only ADD and REMOVE operations are supported for multi-cast */ 1383cee4d264SManish Chopra if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1384cee4d264SManish Chopra (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1385cee4d264SManish Chopra (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1386cee4d264SManish Chopra return -EINVAL; 1387cee4d264SManish Chopra 1388cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1389cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1390cee4d264SManish Chopra 1391cee4d264SManish Chopra u16 opaque_fid; 1392cee4d264SManish Chopra 1393dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1394dacd88d6SYuval Mintz qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); 1395dacd88d6SYuval Mintz continue; 1396dacd88d6SYuval Mintz } 1397cee4d264SManish Chopra 1398cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1399cee4d264SManish Chopra 1400cee4d264SManish Chopra rc = qed_sp_eth_filter_mcast(p_hwfn, 1401cee4d264SManish Chopra opaque_fid, 1402cee4d264SManish Chopra p_filter_cmd, 14031a635e48SYuval Mintz comp_mode, p_comp_data); 1404cee4d264SManish Chopra } 1405cee4d264SManish Chopra return rc; 1406cee4d264SManish Chopra } 1407cee4d264SManish Chopra 1408cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1409cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1410cee4d264SManish Chopra enum spq_mode comp_mode, 1411cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1412cee4d264SManish Chopra { 1413cee4d264SManish Chopra int rc = 0; 1414cee4d264SManish Chopra int i; 1415cee4d264SManish Chopra 1416cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1417cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1418cee4d264SManish Chopra u16 opaque_fid; 1419cee4d264SManish Chopra 1420dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1421dacd88d6SYuval Mintz rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); 1422dacd88d6SYuval Mintz continue; 1423dacd88d6SYuval Mintz } 1424cee4d264SManish Chopra 1425cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1426cee4d264SManish Chopra 1427cee4d264SManish Chopra rc = qed_sp_eth_filter_ucast(p_hwfn, 1428cee4d264SManish Chopra opaque_fid, 1429cee4d264SManish Chopra p_filter_cmd, 14301a635e48SYuval Mintz comp_mode, p_comp_data); 14311a635e48SYuval Mintz if (rc) 1432dacd88d6SYuval Mintz break; 1433cee4d264SManish Chopra } 1434cee4d264SManish Chopra 1435cee4d264SManish Chopra return rc; 1436cee4d264SManish Chopra } 1437cee4d264SManish Chopra 143886622ee7SYuval Mintz /* Statistics related code */ 143986622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 144086622ee7SYuval Mintz u32 *p_addr, 1441dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 144286622ee7SYuval Mintz { 1443dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 144486622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_PSDM_RAM + 144586622ee7SYuval Mintz PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 144686622ee7SYuval Mintz *p_len = sizeof(struct eth_pstorm_per_queue_stat); 1447dacd88d6SYuval Mintz } else { 1448dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1449dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1450dacd88d6SYuval Mintz 1451dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.pstats.address; 1452dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.pstats.len; 1453dacd88d6SYuval Mintz } 145486622ee7SYuval Mintz } 145586622ee7SYuval Mintz 145686622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 145786622ee7SYuval Mintz struct qed_ptt *p_ptt, 145886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 145986622ee7SYuval Mintz u16 statistics_bin) 146086622ee7SYuval Mintz { 146186622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 146286622ee7SYuval Mintz u32 pstats_addr = 0, pstats_len = 0; 146386622ee7SYuval Mintz 146486622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 146586622ee7SYuval Mintz statistics_bin); 146686622ee7SYuval Mintz 146786622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 1468dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); 146986622ee7SYuval Mintz 14709c79ddaaSMintz, Yuval p_stats->common.tx_ucast_bytes += 14719c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_bytes); 14729c79ddaaSMintz, Yuval p_stats->common.tx_mcast_bytes += 14739c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_bytes); 14749c79ddaaSMintz, Yuval p_stats->common.tx_bcast_bytes += 14759c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_bytes); 14769c79ddaaSMintz, Yuval p_stats->common.tx_ucast_pkts += 14779c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_pkts); 14789c79ddaaSMintz, Yuval p_stats->common.tx_mcast_pkts += 14799c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_pkts); 14809c79ddaaSMintz, Yuval p_stats->common.tx_bcast_pkts += 14819c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_pkts); 14829c79ddaaSMintz, Yuval p_stats->common.tx_err_drop_pkts += 14839c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.error_drop_pkts); 148486622ee7SYuval Mintz } 148586622ee7SYuval Mintz 148686622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 148786622ee7SYuval Mintz struct qed_ptt *p_ptt, 148886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 148986622ee7SYuval Mintz u16 statistics_bin) 149086622ee7SYuval Mintz { 149186622ee7SYuval Mintz struct tstorm_per_port_stat tstats; 1492dacd88d6SYuval Mintz u32 tstats_addr, tstats_len; 149386622ee7SYuval Mintz 1494dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1495dacd88d6SYuval Mintz tstats_addr = BAR0_MAP_REG_TSDM_RAM + 1496dacd88d6SYuval Mintz TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 1497dacd88d6SYuval Mintz tstats_len = sizeof(struct tstorm_per_port_stat); 1498dacd88d6SYuval Mintz } else { 1499dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1500dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1501dacd88d6SYuval Mintz 1502dacd88d6SYuval Mintz tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; 1503dacd88d6SYuval Mintz tstats_len = p_resp->pfdev_info.stats_info.tstats.len; 1504dacd88d6SYuval Mintz } 150586622ee7SYuval Mintz 150686622ee7SYuval Mintz memset(&tstats, 0, sizeof(tstats)); 1507dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); 150886622ee7SYuval Mintz 15099c79ddaaSMintz, Yuval p_stats->common.mftag_filter_discards += 151086622ee7SYuval Mintz HILO_64_REGPAIR(tstats.mftag_filter_discard); 15119c79ddaaSMintz, Yuval p_stats->common.mac_filter_discards += 151286622ee7SYuval Mintz HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 151386622ee7SYuval Mintz } 151486622ee7SYuval Mintz 151586622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 151686622ee7SYuval Mintz u32 *p_addr, 1517dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 151886622ee7SYuval Mintz { 1519dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 152086622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_USDM_RAM + 152186622ee7SYuval Mintz USTORM_QUEUE_STAT_OFFSET(statistics_bin); 152286622ee7SYuval Mintz *p_len = sizeof(struct eth_ustorm_per_queue_stat); 1523dacd88d6SYuval Mintz } else { 1524dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1525dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1526dacd88d6SYuval Mintz 1527dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.ustats.address; 1528dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.ustats.len; 1529dacd88d6SYuval Mintz } 153086622ee7SYuval Mintz } 153186622ee7SYuval Mintz 153286622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 153386622ee7SYuval Mintz struct qed_ptt *p_ptt, 153486622ee7SYuval Mintz struct qed_eth_stats *p_stats, 153586622ee7SYuval Mintz u16 statistics_bin) 153686622ee7SYuval Mintz { 153786622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 153886622ee7SYuval Mintz u32 ustats_addr = 0, ustats_len = 0; 153986622ee7SYuval Mintz 154086622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 154186622ee7SYuval Mintz statistics_bin); 154286622ee7SYuval Mintz 154386622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 1544dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); 154586622ee7SYuval Mintz 15469c79ddaaSMintz, Yuval p_stats->common.rx_ucast_bytes += 15479c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 15489c79ddaaSMintz, Yuval p_stats->common.rx_mcast_bytes += 15499c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 15509c79ddaaSMintz, Yuval p_stats->common.rx_bcast_bytes += 15519c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 15529c79ddaaSMintz, Yuval p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 15539c79ddaaSMintz, Yuval p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 15549c79ddaaSMintz, Yuval p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 155586622ee7SYuval Mintz } 155686622ee7SYuval Mintz 155786622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 155886622ee7SYuval Mintz u32 *p_addr, 1559dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 156086622ee7SYuval Mintz { 1561dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 156286622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_MSDM_RAM + 156386622ee7SYuval Mintz MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 156486622ee7SYuval Mintz *p_len = sizeof(struct eth_mstorm_per_queue_stat); 1565dacd88d6SYuval Mintz } else { 1566dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1567dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1568dacd88d6SYuval Mintz 1569dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.mstats.address; 1570dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.mstats.len; 1571dacd88d6SYuval Mintz } 157286622ee7SYuval Mintz } 157386622ee7SYuval Mintz 157486622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 157586622ee7SYuval Mintz struct qed_ptt *p_ptt, 157686622ee7SYuval Mintz struct qed_eth_stats *p_stats, 157786622ee7SYuval Mintz u16 statistics_bin) 157886622ee7SYuval Mintz { 157986622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 158086622ee7SYuval Mintz u32 mstats_addr = 0, mstats_len = 0; 158186622ee7SYuval Mintz 158286622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 158386622ee7SYuval Mintz statistics_bin); 158486622ee7SYuval Mintz 158586622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 1586dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); 158786622ee7SYuval Mintz 15889c79ddaaSMintz, Yuval p_stats->common.no_buff_discards += 15899c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.no_buff_discard); 15909c79ddaaSMintz, Yuval p_stats->common.packet_too_big_discard += 159186622ee7SYuval Mintz HILO_64_REGPAIR(mstats.packet_too_big_discard); 15929c79ddaaSMintz, Yuval p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); 15939c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_pkts += 159486622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 15959c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_events += 159686622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_events); 15979c79ddaaSMintz, Yuval p_stats->common.tpa_aborts_num += 15989c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.tpa_aborts_num); 15999c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_bytes += 160086622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 160186622ee7SYuval Mintz } 160286622ee7SYuval Mintz 160386622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 160486622ee7SYuval Mintz struct qed_ptt *p_ptt, 160586622ee7SYuval Mintz struct qed_eth_stats *p_stats) 160686622ee7SYuval Mintz { 16079c79ddaaSMintz, Yuval struct qed_eth_stats_common *p_common = &p_stats->common; 160886622ee7SYuval Mintz struct port_stats port_stats; 160986622ee7SYuval Mintz int j; 161086622ee7SYuval Mintz 161186622ee7SYuval Mintz memset(&port_stats, 0, sizeof(port_stats)); 161286622ee7SYuval Mintz 161386622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 161486622ee7SYuval Mintz p_hwfn->mcp_info->port_addr + 161586622ee7SYuval Mintz offsetof(struct public_port, stats), 161686622ee7SYuval Mintz sizeof(port_stats)); 161786622ee7SYuval Mintz 16189c79ddaaSMintz, Yuval p_common->rx_64_byte_packets += port_stats.eth.r64; 16199c79ddaaSMintz, Yuval p_common->rx_65_to_127_byte_packets += port_stats.eth.r127; 16209c79ddaaSMintz, Yuval p_common->rx_128_to_255_byte_packets += port_stats.eth.r255; 16219c79ddaaSMintz, Yuval p_common->rx_256_to_511_byte_packets += port_stats.eth.r511; 16229c79ddaaSMintz, Yuval p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023; 16239c79ddaaSMintz, Yuval p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; 16249c79ddaaSMintz, Yuval p_common->rx_crc_errors += port_stats.eth.rfcs; 16259c79ddaaSMintz, Yuval p_common->rx_mac_crtl_frames += port_stats.eth.rxcf; 16269c79ddaaSMintz, Yuval p_common->rx_pause_frames += port_stats.eth.rxpf; 16279c79ddaaSMintz, Yuval p_common->rx_pfc_frames += port_stats.eth.rxpp; 16289c79ddaaSMintz, Yuval p_common->rx_align_errors += port_stats.eth.raln; 16299c79ddaaSMintz, Yuval p_common->rx_carrier_errors += port_stats.eth.rfcr; 16309c79ddaaSMintz, Yuval p_common->rx_oversize_packets += port_stats.eth.rovr; 16319c79ddaaSMintz, Yuval p_common->rx_jabbers += port_stats.eth.rjbr; 16329c79ddaaSMintz, Yuval p_common->rx_undersize_packets += port_stats.eth.rund; 16339c79ddaaSMintz, Yuval p_common->rx_fragments += port_stats.eth.rfrg; 16349c79ddaaSMintz, Yuval p_common->tx_64_byte_packets += port_stats.eth.t64; 16359c79ddaaSMintz, Yuval p_common->tx_65_to_127_byte_packets += port_stats.eth.t127; 16369c79ddaaSMintz, Yuval p_common->tx_128_to_255_byte_packets += port_stats.eth.t255; 16379c79ddaaSMintz, Yuval p_common->tx_256_to_511_byte_packets += port_stats.eth.t511; 16389c79ddaaSMintz, Yuval p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023; 16399c79ddaaSMintz, Yuval p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; 16409c79ddaaSMintz, Yuval p_common->tx_pause_frames += port_stats.eth.txpf; 16419c79ddaaSMintz, Yuval p_common->tx_pfc_frames += port_stats.eth.txpp; 16429c79ddaaSMintz, Yuval p_common->rx_mac_bytes += port_stats.eth.rbyte; 16439c79ddaaSMintz, Yuval p_common->rx_mac_uc_packets += port_stats.eth.rxuca; 16449c79ddaaSMintz, Yuval p_common->rx_mac_mc_packets += port_stats.eth.rxmca; 16459c79ddaaSMintz, Yuval p_common->rx_mac_bc_packets += port_stats.eth.rxbca; 16469c79ddaaSMintz, Yuval p_common->rx_mac_frames_ok += port_stats.eth.rxpok; 16479c79ddaaSMintz, Yuval p_common->tx_mac_bytes += port_stats.eth.tbyte; 16489c79ddaaSMintz, Yuval p_common->tx_mac_uc_packets += port_stats.eth.txuca; 16499c79ddaaSMintz, Yuval p_common->tx_mac_mc_packets += port_stats.eth.txmca; 16509c79ddaaSMintz, Yuval p_common->tx_mac_bc_packets += port_stats.eth.txbca; 16519c79ddaaSMintz, Yuval p_common->tx_mac_ctrl_frames += port_stats.eth.txcf; 165286622ee7SYuval Mintz for (j = 0; j < 8; j++) { 16539c79ddaaSMintz, Yuval p_common->brb_truncates += port_stats.brb.brb_truncate[j]; 16549c79ddaaSMintz, Yuval p_common->brb_discards += port_stats.brb.brb_discard[j]; 16559c79ddaaSMintz, Yuval } 16569c79ddaaSMintz, Yuval 16579c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) { 16589c79ddaaSMintz, Yuval struct qed_eth_stats_bb *p_bb = &p_stats->bb; 16599c79ddaaSMintz, Yuval 16609c79ddaaSMintz, Yuval p_bb->rx_1519_to_1522_byte_packets += 16619c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r1522; 16629c79ddaaSMintz, Yuval p_bb->rx_1519_to_2047_byte_packets += 16639c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r2047; 16649c79ddaaSMintz, Yuval p_bb->rx_2048_to_4095_byte_packets += 16659c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r4095; 16669c79ddaaSMintz, Yuval p_bb->rx_4096_to_9216_byte_packets += 16679c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r9216; 16689c79ddaaSMintz, Yuval p_bb->rx_9217_to_16383_byte_packets += 16699c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r16383; 16709c79ddaaSMintz, Yuval p_bb->tx_1519_to_2047_byte_packets += 16719c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t2047; 16729c79ddaaSMintz, Yuval p_bb->tx_2048_to_4095_byte_packets += 16739c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t4095; 16749c79ddaaSMintz, Yuval p_bb->tx_4096_to_9216_byte_packets += 16759c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t9216; 16769c79ddaaSMintz, Yuval p_bb->tx_9217_to_16383_byte_packets += 16779c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t16383; 16789c79ddaaSMintz, Yuval p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec; 16799c79ddaaSMintz, Yuval p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl; 16809c79ddaaSMintz, Yuval } else { 16819c79ddaaSMintz, Yuval struct qed_eth_stats_ah *p_ah = &p_stats->ah; 16829c79ddaaSMintz, Yuval 16839c79ddaaSMintz, Yuval p_ah->rx_1519_to_max_byte_packets += 16849c79ddaaSMintz, Yuval port_stats.eth.u0.ah0.r1519_to_max; 16859c79ddaaSMintz, Yuval p_ah->tx_1519_to_max_byte_packets = 16869c79ddaaSMintz, Yuval port_stats.eth.u1.ah1.t1519_to_max; 168786622ee7SYuval Mintz } 168886622ee7SYuval Mintz } 168986622ee7SYuval Mintz 169086622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 169186622ee7SYuval Mintz struct qed_ptt *p_ptt, 169286622ee7SYuval Mintz struct qed_eth_stats *stats, 1693dacd88d6SYuval Mintz u16 statistics_bin, bool b_get_port_stats) 169486622ee7SYuval Mintz { 169586622ee7SYuval Mintz __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 169686622ee7SYuval Mintz __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 169786622ee7SYuval Mintz __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 169886622ee7SYuval Mintz __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 169986622ee7SYuval Mintz 1700dacd88d6SYuval Mintz if (b_get_port_stats && p_hwfn->mcp_info) 170186622ee7SYuval Mintz __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 170286622ee7SYuval Mintz } 170386622ee7SYuval Mintz 170486622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev, 170586622ee7SYuval Mintz struct qed_eth_stats *stats) 170686622ee7SYuval Mintz { 170786622ee7SYuval Mintz u8 fw_vport = 0; 170886622ee7SYuval Mintz int i; 170986622ee7SYuval Mintz 171086622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 171186622ee7SYuval Mintz 171286622ee7SYuval Mintz for_each_hwfn(cdev, i) { 171386622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1714dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1715dacd88d6SYuval Mintz : NULL; 171686622ee7SYuval Mintz 1717dacd88d6SYuval Mintz if (IS_PF(cdev)) { 171886622ee7SYuval Mintz /* The main vport index is relative first */ 171986622ee7SYuval Mintz if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 172086622ee7SYuval Mintz DP_ERR(p_hwfn, "No vport available!\n"); 1721dacd88d6SYuval Mintz goto out; 1722dacd88d6SYuval Mintz } 172386622ee7SYuval Mintz } 172486622ee7SYuval Mintz 1725dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 172686622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 172786622ee7SYuval Mintz continue; 172886622ee7SYuval Mintz } 172986622ee7SYuval Mintz 1730dacd88d6SYuval Mintz __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, 1731dacd88d6SYuval Mintz IS_PF(cdev) ? true : false); 173286622ee7SYuval Mintz 1733dacd88d6SYuval Mintz out: 1734dacd88d6SYuval Mintz if (IS_PF(cdev) && p_ptt) 173586622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 173686622ee7SYuval Mintz } 173786622ee7SYuval Mintz } 173886622ee7SYuval Mintz 17391a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats) 174086622ee7SYuval Mintz { 174186622ee7SYuval Mintz u32 i; 174286622ee7SYuval Mintz 174386622ee7SYuval Mintz if (!cdev) { 174486622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 174586622ee7SYuval Mintz return; 174686622ee7SYuval Mintz } 174786622ee7SYuval Mintz 174886622ee7SYuval Mintz _qed_get_vport_stats(cdev, stats); 174986622ee7SYuval Mintz 175086622ee7SYuval Mintz if (!cdev->reset_stats) 175186622ee7SYuval Mintz return; 175286622ee7SYuval Mintz 175386622ee7SYuval Mintz /* Reduce the statistics baseline */ 175486622ee7SYuval Mintz for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 175586622ee7SYuval Mintz ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 175686622ee7SYuval Mintz } 175786622ee7SYuval Mintz 175886622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 175986622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev) 176086622ee7SYuval Mintz { 176186622ee7SYuval Mintz int i; 176286622ee7SYuval Mintz 176386622ee7SYuval Mintz for_each_hwfn(cdev, i) { 176486622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 176586622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 176686622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 176786622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 1768dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1769dacd88d6SYuval Mintz : NULL; 177086622ee7SYuval Mintz u32 addr = 0, len = 0; 177186622ee7SYuval Mintz 1772dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 177386622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 177486622ee7SYuval Mintz continue; 177586622ee7SYuval Mintz } 177686622ee7SYuval Mintz 177786622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 177886622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 177986622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 178086622ee7SYuval Mintz 178186622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 178286622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 178386622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 178486622ee7SYuval Mintz 178586622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 178686622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 178786622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 178886622ee7SYuval Mintz 1789dacd88d6SYuval Mintz if (IS_PF(cdev)) 179086622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 179186622ee7SYuval Mintz } 179286622ee7SYuval Mintz 179386622ee7SYuval Mintz /* PORT statistics are not necessarily reset, so we need to 179486622ee7SYuval Mintz * read and create a baseline for future statistics. 179586622ee7SYuval Mintz */ 179686622ee7SYuval Mintz if (!cdev->reset_stats) 179786622ee7SYuval Mintz DP_INFO(cdev, "Reset stats not allocated\n"); 179886622ee7SYuval Mintz else 179986622ee7SYuval Mintz _qed_get_vport_stats(cdev, cdev->reset_stats); 180086622ee7SYuval Mintz } 180186622ee7SYuval Mintz 1802d51e4af5SChopra, Manish static void 1803d51e4af5SChopra, Manish qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1804d51e4af5SChopra, Manish struct qed_arfs_config_params *p_cfg_params) 1805d51e4af5SChopra, Manish { 1806d51e4af5SChopra, Manish if (p_cfg_params->arfs_enable) { 1807d51e4af5SChopra, Manish qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 1808d51e4af5SChopra, Manish p_cfg_params->tcp, p_cfg_params->udp, 1809d51e4af5SChopra, Manish p_cfg_params->ipv4, p_cfg_params->ipv6); 1810d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, 1811d51e4af5SChopra, Manish "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n", 1812d51e4af5SChopra, Manish p_cfg_params->tcp ? "Enable" : "Disable", 1813d51e4af5SChopra, Manish p_cfg_params->udp ? "Enable" : "Disable", 1814d51e4af5SChopra, Manish p_cfg_params->ipv4 ? "Enable" : "Disable", 1815d51e4af5SChopra, Manish p_cfg_params->ipv6 ? "Enable" : "Disable"); 1816d51e4af5SChopra, Manish } else { 1817d51e4af5SChopra, Manish qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1818d51e4af5SChopra, Manish } 1819d51e4af5SChopra, Manish 1820d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n", 1821d51e4af5SChopra, Manish p_cfg_params->arfs_enable ? "Enable" : "Disable"); 1822d51e4af5SChopra, Manish } 1823d51e4af5SChopra, Manish 1824d51e4af5SChopra, Manish static int 1825d51e4af5SChopra, Manish qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1826d51e4af5SChopra, Manish struct qed_spq_comp_cb *p_cb, 1827d51e4af5SChopra, Manish dma_addr_t p_addr, u16 length, u16 qid, 1828d51e4af5SChopra, Manish u8 vport_id, bool b_is_add) 1829d51e4af5SChopra, Manish { 1830d51e4af5SChopra, Manish struct rx_update_gft_filter_data *p_ramrod = NULL; 1831d51e4af5SChopra, Manish struct qed_spq_entry *p_ent = NULL; 1832d51e4af5SChopra, Manish struct qed_sp_init_data init_data; 1833d51e4af5SChopra, Manish u16 abs_rx_q_id = 0; 1834d51e4af5SChopra, Manish u8 abs_vport_id = 0; 1835d51e4af5SChopra, Manish int rc = -EINVAL; 1836d51e4af5SChopra, Manish 1837d51e4af5SChopra, Manish rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 1838d51e4af5SChopra, Manish if (rc) 1839d51e4af5SChopra, Manish return rc; 1840d51e4af5SChopra, Manish 1841d51e4af5SChopra, Manish rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id); 1842d51e4af5SChopra, Manish if (rc) 1843d51e4af5SChopra, Manish return rc; 1844d51e4af5SChopra, Manish 1845d51e4af5SChopra, Manish /* Get SPQ entry */ 1846d51e4af5SChopra, Manish memset(&init_data, 0, sizeof(init_data)); 1847d51e4af5SChopra, Manish init_data.cid = qed_spq_get_cid(p_hwfn); 1848d51e4af5SChopra, Manish 1849d51e4af5SChopra, Manish init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1850d51e4af5SChopra, Manish 1851d51e4af5SChopra, Manish if (p_cb) { 1852d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_CB; 1853d51e4af5SChopra, Manish init_data.p_comp_data = p_cb; 1854d51e4af5SChopra, Manish } else { 1855d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1856d51e4af5SChopra, Manish } 1857d51e4af5SChopra, Manish 1858d51e4af5SChopra, Manish rc = qed_sp_init_request(p_hwfn, &p_ent, 1859d51e4af5SChopra, Manish ETH_RAMROD_GFT_UPDATE_FILTER, 1860d51e4af5SChopra, Manish PROTOCOLID_ETH, &init_data); 1861d51e4af5SChopra, Manish if (rc) 1862d51e4af5SChopra, Manish return rc; 1863d51e4af5SChopra, Manish 1864d51e4af5SChopra, Manish p_ramrod = &p_ent->ramrod.rx_update_gft; 1865d51e4af5SChopra, Manish DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr); 1866d51e4af5SChopra, Manish p_ramrod->pkt_hdr_length = cpu_to_le16(length); 1867d51e4af5SChopra, Manish p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id); 1868d51e4af5SChopra, Manish p_ramrod->vport_id = abs_vport_id; 1869d51e4af5SChopra, Manish p_ramrod->filter_type = RFS_FILTER_TYPE; 1870d51e4af5SChopra, Manish p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER; 1871d51e4af5SChopra, Manish 1872d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, 1873d51e4af5SChopra, Manish "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n", 1874d51e4af5SChopra, Manish abs_vport_id, abs_rx_q_id, 1875d51e4af5SChopra, Manish b_is_add ? "Adding" : "Removing", (u64)p_addr, length); 1876d51e4af5SChopra, Manish 1877d51e4af5SChopra, Manish return qed_spq_post(p_hwfn, p_ent, NULL); 1878d51e4af5SChopra, Manish } 1879d51e4af5SChopra, Manish 188025c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev, 188125c089d7SYuval Mintz struct qed_dev_eth_info *info) 188225c089d7SYuval Mintz { 188325c089d7SYuval Mintz int i; 188425c089d7SYuval Mintz 188525c089d7SYuval Mintz memset(info, 0, sizeof(*info)); 188625c089d7SYuval Mintz 188725c089d7SYuval Mintz info->num_tc = 1; 188825c089d7SYuval Mintz 18891408cc1fSYuval Mintz if (IS_PF(cdev)) { 189025eb8d46SYuval Mintz int max_vf_vlan_filters = 0; 18917b7e70f9SYuval Mintz int max_vf_mac_filters = 0; 189225eb8d46SYuval Mintz 189325c089d7SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 1894e1d32acbSMintz, Yuval u16 num_queues = 0; 1895e1d32acbSMintz, Yuval 1896e1d32acbSMintz, Yuval /* Since the feature controls only queue-zones, 1897e1d32acbSMintz, Yuval * make sure we have the contexts [rx, tx, xdp] to 1898e1d32acbSMintz, Yuval * match. 1899e1d32acbSMintz, Yuval */ 1900e1d32acbSMintz, Yuval for_each_hwfn(cdev, i) { 1901e1d32acbSMintz, Yuval struct qed_hwfn *hwfn = &cdev->hwfns[i]; 1902e1d32acbSMintz, Yuval u16 l2_queues = (u16)FEAT_NUM(hwfn, 1903e1d32acbSMintz, Yuval QED_PF_L2_QUE); 1904e1d32acbSMintz, Yuval u16 cids; 1905e1d32acbSMintz, Yuval 1906e1d32acbSMintz, Yuval cids = hwfn->pf_params.eth_pf_params.num_cons; 1907e1d32acbSMintz, Yuval num_queues += min_t(u16, l2_queues, cids / 3); 1908e1d32acbSMintz, Yuval } 1909e1d32acbSMintz, Yuval 1910e1d32acbSMintz, Yuval /* queues might theoretically be >256, but interrupts' 1911e1d32acbSMintz, Yuval * upper-limit guarantes that it would fit in a u8. 1912e1d32acbSMintz, Yuval */ 1913e1d32acbSMintz, Yuval if (cdev->int_params.fp_msix_cnt) { 1914e1d32acbSMintz, Yuval u8 irqs = cdev->int_params.fp_msix_cnt; 1915e1d32acbSMintz, Yuval 1916e1d32acbSMintz, Yuval info->num_queues = (u8)min_t(u16, 1917e1d32acbSMintz, Yuval num_queues, irqs); 1918e1d32acbSMintz, Yuval } 191925c089d7SYuval Mintz } else { 192025c089d7SYuval Mintz info->num_queues = cdev->num_hwfns; 192125c089d7SYuval Mintz } 192225c089d7SYuval Mintz 19237b7e70f9SYuval Mintz if (IS_QED_SRIOV(cdev)) { 192425eb8d46SYuval Mintz max_vf_vlan_filters = cdev->p_iov_info->total_vfs * 192525eb8d46SYuval Mintz QED_ETH_VF_NUM_VLAN_FILTERS; 19267b7e70f9SYuval Mintz max_vf_mac_filters = cdev->p_iov_info->total_vfs * 19277b7e70f9SYuval Mintz QED_ETH_VF_NUM_MAC_FILTERS; 19287b7e70f9SYuval Mintz } 19297b7e70f9SYuval Mintz info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 19307b7e70f9SYuval Mintz QED_VLAN) - 193125eb8d46SYuval Mintz max_vf_vlan_filters; 19327b7e70f9SYuval Mintz info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 19337b7e70f9SYuval Mintz QED_MAC) - 19347b7e70f9SYuval Mintz max_vf_mac_filters; 193525eb8d46SYuval Mintz 193625c089d7SYuval Mintz ether_addr_copy(info->port_mac, 193725c089d7SYuval Mintz cdev->hwfns[0].hw_info.hw_mac_addr); 19381408cc1fSYuval Mintz } else { 19391408cc1fSYuval Mintz qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues); 19401408cc1fSYuval Mintz if (cdev->num_hwfns > 1) { 19411408cc1fSYuval Mintz u8 queues = 0; 19421408cc1fSYuval Mintz 19431408cc1fSYuval Mintz qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues); 19441408cc1fSYuval Mintz info->num_queues += queues; 19451408cc1fSYuval Mintz } 19461408cc1fSYuval Mintz 19471408cc1fSYuval Mintz qed_vf_get_num_vlan_filters(&cdev->hwfns[0], 19482edbff8dSTomer Tayar (u8 *)&info->num_vlan_filters); 1949b0fca312SMintz, Yuval qed_vf_get_num_mac_filters(&cdev->hwfns[0], 1950b0fca312SMintz, Yuval (u8 *)&info->num_mac_filters); 19511408cc1fSYuval Mintz qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); 1952d8c2c7e3SYuval Mintz 1953d8c2c7e3SYuval Mintz info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi; 19541408cc1fSYuval Mintz } 195525c089d7SYuval Mintz 195625c089d7SYuval Mintz qed_fill_dev_info(cdev, &info->common); 195725c089d7SYuval Mintz 19581408cc1fSYuval Mintz if (IS_VF(cdev)) 19590ee28e31SShyam Saini eth_zero_addr(info->common.hw_mac); 19601408cc1fSYuval Mintz 196125c089d7SYuval Mintz return 0; 196225c089d7SYuval Mintz } 196325c089d7SYuval Mintz 1964cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev, 19651408cc1fSYuval Mintz struct qed_eth_cb_ops *ops, void *cookie) 1966cc875c2eSYuval Mintz { 1967cc875c2eSYuval Mintz cdev->protocol_ops.eth = ops; 1968cc875c2eSYuval Mintz cdev->ops_cookie = cookie; 19691408cc1fSYuval Mintz 19701408cc1fSYuval Mintz /* For VF, we start bulletin reading */ 19711408cc1fSYuval Mintz if (IS_VF(cdev)) 19721408cc1fSYuval Mintz qed_vf_start_iov_wq(cdev); 1973cc875c2eSYuval Mintz } 1974cc875c2eSYuval Mintz 1975eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) 1976eff16960SYuval Mintz { 1977eff16960SYuval Mintz if (IS_PF(cdev)) 1978eff16960SYuval Mintz return true; 1979eff16960SYuval Mintz 1980eff16960SYuval Mintz return qed_vf_check_mac(&cdev->hwfns[0], mac); 1981eff16960SYuval Mintz } 1982eff16960SYuval Mintz 1983cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev, 1984088c8618SManish Chopra struct qed_start_vport_params *params) 1985cee4d264SManish Chopra { 1986cee4d264SManish Chopra int rc, i; 1987cee4d264SManish Chopra 1988cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1989088c8618SManish Chopra struct qed_sp_vport_start_params start = { 0 }; 1990cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1991cee4d264SManish Chopra 1992088c8618SManish Chopra start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : 1993088c8618SManish Chopra QED_TPA_MODE_NONE; 1994088c8618SManish Chopra start.remove_inner_vlan = params->remove_inner_vlan; 199508feecd7SYuval Mintz start.only_untagged = true; /* untagged only */ 1996088c8618SManish Chopra start.drop_ttl0 = params->drop_ttl0; 1997088c8618SManish Chopra start.opaque_fid = p_hwfn->hw_info.opaque_fid; 1998088c8618SManish Chopra start.concrete_fid = p_hwfn->hw_info.concrete_fid; 1999c78c70faSSudarsana Reddy Kalluru start.handle_ptp_pkts = params->handle_ptp_pkts; 2000088c8618SManish Chopra start.vport_id = params->vport_id; 2001088c8618SManish Chopra start.max_buffers_per_cqe = 16; 2002088c8618SManish Chopra start.mtu = params->mtu; 2003cee4d264SManish Chopra 2004088c8618SManish Chopra rc = qed_sp_vport_start(p_hwfn, &start); 2005cee4d264SManish Chopra if (rc) { 2006cee4d264SManish Chopra DP_ERR(cdev, "Failed to start VPORT\n"); 2007cee4d264SManish Chopra return rc; 2008cee4d264SManish Chopra } 2009cee4d264SManish Chopra 201015582962SRahul Verma rc = qed_hw_start_fastpath(p_hwfn); 201115582962SRahul Verma if (rc) { 201215582962SRahul Verma DP_ERR(cdev, "Failed to start VPORT fastpath\n"); 201315582962SRahul Verma return rc; 201415582962SRahul Verma } 2015cee4d264SManish Chopra 2016cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2017cee4d264SManish Chopra "Started V-PORT %d with MTU %d\n", 2018088c8618SManish Chopra start.vport_id, start.mtu); 2019cee4d264SManish Chopra } 2020cee4d264SManish Chopra 2021a0d26d5aSYuval Mintz if (params->clear_stats) 20229df2ed04SManish Chopra qed_reset_vport_stats(cdev); 20239df2ed04SManish Chopra 2024cee4d264SManish Chopra return 0; 2025cee4d264SManish Chopra } 2026cee4d264SManish Chopra 20271a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id) 2028cee4d264SManish Chopra { 2029cee4d264SManish Chopra int rc, i; 2030cee4d264SManish Chopra 2031cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2032cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2033cee4d264SManish Chopra 2034cee4d264SManish Chopra rc = qed_sp_vport_stop(p_hwfn, 20351a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid, vport_id); 2036cee4d264SManish Chopra 2037cee4d264SManish Chopra if (rc) { 2038cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop VPORT\n"); 2039cee4d264SManish Chopra return rc; 2040cee4d264SManish Chopra } 2041cee4d264SManish Chopra } 2042cee4d264SManish Chopra return 0; 2043cee4d264SManish Chopra } 2044cee4d264SManish Chopra 2045f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev, 2046f29ffdb6SMintz, Yuval struct qed_update_vport_rss_params *input, 2047f29ffdb6SMintz, Yuval struct qed_rss_params *rss) 2048f29ffdb6SMintz, Yuval { 2049f29ffdb6SMintz, Yuval int i, fn; 2050f29ffdb6SMintz, Yuval 2051f29ffdb6SMintz, Yuval /* Update configuration with what's correct regardless of CMT */ 2052f29ffdb6SMintz, Yuval rss->update_rss_config = 1; 2053f29ffdb6SMintz, Yuval rss->rss_enable = 1; 2054f29ffdb6SMintz, Yuval rss->update_rss_capabilities = 1; 2055f29ffdb6SMintz, Yuval rss->update_rss_ind_table = 1; 2056f29ffdb6SMintz, Yuval rss->update_rss_key = 1; 2057f29ffdb6SMintz, Yuval rss->rss_caps = input->rss_caps; 2058f29ffdb6SMintz, Yuval memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32)); 2059f29ffdb6SMintz, Yuval 2060f29ffdb6SMintz, Yuval /* In regular scenario, we'd simply need to take input handlers. 2061f29ffdb6SMintz, Yuval * But in CMT, we'd have to split the handlers according to the 2062f29ffdb6SMintz, Yuval * engine they were configured on. We'd then have to understand 2063f29ffdb6SMintz, Yuval * whether RSS is really required, since 2-queues on CMT doesn't 2064f29ffdb6SMintz, Yuval * require RSS. 2065f29ffdb6SMintz, Yuval */ 2066f29ffdb6SMintz, Yuval if (cdev->num_hwfns == 1) { 2067f29ffdb6SMintz, Yuval memcpy(rss->rss_ind_table, 2068f29ffdb6SMintz, Yuval input->rss_ind_table, 2069f29ffdb6SMintz, Yuval QED_RSS_IND_TABLE_SIZE * sizeof(void *)); 2070f29ffdb6SMintz, Yuval rss->rss_table_size_log = 7; 2071f29ffdb6SMintz, Yuval return 0; 2072f29ffdb6SMintz, Yuval } 2073f29ffdb6SMintz, Yuval 2074f29ffdb6SMintz, Yuval /* Start by copying the non-spcific information to the 2nd copy */ 2075f29ffdb6SMintz, Yuval memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params)); 2076f29ffdb6SMintz, Yuval 2077f29ffdb6SMintz, Yuval /* CMT should be round-robin */ 2078f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 2079f29ffdb6SMintz, Yuval struct qed_queue_cid *cid = input->rss_ind_table[i]; 2080f29ffdb6SMintz, Yuval struct qed_rss_params *t_rss; 2081f29ffdb6SMintz, Yuval 2082f29ffdb6SMintz, Yuval if (cid->p_owner == QED_LEADING_HWFN(cdev)) 2083f29ffdb6SMintz, Yuval t_rss = &rss[0]; 2084f29ffdb6SMintz, Yuval else 2085f29ffdb6SMintz, Yuval t_rss = &rss[1]; 2086f29ffdb6SMintz, Yuval 2087f29ffdb6SMintz, Yuval t_rss->rss_ind_table[i / cdev->num_hwfns] = cid; 2088f29ffdb6SMintz, Yuval } 2089f29ffdb6SMintz, Yuval 2090f29ffdb6SMintz, Yuval /* Make sure RSS is actually required */ 2091f29ffdb6SMintz, Yuval for_each_hwfn(cdev, fn) { 2092f29ffdb6SMintz, Yuval for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) { 2093f29ffdb6SMintz, Yuval if (rss[fn].rss_ind_table[i] != 2094f29ffdb6SMintz, Yuval rss[fn].rss_ind_table[0]) 2095f29ffdb6SMintz, Yuval break; 2096f29ffdb6SMintz, Yuval } 2097f29ffdb6SMintz, Yuval if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) { 2098f29ffdb6SMintz, Yuval DP_VERBOSE(cdev, NETIF_MSG_IFUP, 2099f29ffdb6SMintz, Yuval "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2100f29ffdb6SMintz, Yuval return -EINVAL; 2101f29ffdb6SMintz, Yuval } 2102f29ffdb6SMintz, Yuval rss[fn].rss_table_size_log = 6; 2103f29ffdb6SMintz, Yuval } 2104f29ffdb6SMintz, Yuval 2105f29ffdb6SMintz, Yuval return 0; 2106f29ffdb6SMintz, Yuval } 2107f29ffdb6SMintz, Yuval 2108cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev, 2109cee4d264SManish Chopra struct qed_update_vport_params *params) 2110cee4d264SManish Chopra { 2111cee4d264SManish Chopra struct qed_sp_vport_update_params sp_params; 2112f29ffdb6SMintz, Yuval struct qed_rss_params *rss; 2113f29ffdb6SMintz, Yuval int rc = 0, i; 2114cee4d264SManish Chopra 2115cee4d264SManish Chopra if (!cdev) 2116cee4d264SManish Chopra return -ENODEV; 2117cee4d264SManish Chopra 2118f29ffdb6SMintz, Yuval rss = vzalloc(sizeof(*rss) * cdev->num_hwfns); 2119f29ffdb6SMintz, Yuval if (!rss) 2120f29ffdb6SMintz, Yuval return -ENOMEM; 2121f29ffdb6SMintz, Yuval 2122cee4d264SManish Chopra memset(&sp_params, 0, sizeof(sp_params)); 2123cee4d264SManish Chopra 2124cee4d264SManish Chopra /* Translate protocol params into sp params */ 2125cee4d264SManish Chopra sp_params.vport_id = params->vport_id; 21261a635e48SYuval Mintz sp_params.update_vport_active_rx_flg = params->update_vport_active_flg; 21271a635e48SYuval Mintz sp_params.update_vport_active_tx_flg = params->update_vport_active_flg; 2128cee4d264SManish Chopra sp_params.vport_active_rx_flg = params->vport_active_flg; 2129cee4d264SManish Chopra sp_params.vport_active_tx_flg = params->vport_active_flg; 2130831bfb0eSYuval Mintz sp_params.update_tx_switching_flg = params->update_tx_switching_flg; 2131831bfb0eSYuval Mintz sp_params.tx_switching_flg = params->tx_switching_flg; 21323f9b4a69SYuval Mintz sp_params.accept_any_vlan = params->accept_any_vlan; 21333f9b4a69SYuval Mintz sp_params.update_accept_any_vlan_flg = 21343f9b4a69SYuval Mintz params->update_accept_any_vlan_flg; 2135cee4d264SManish Chopra 2136f29ffdb6SMintz, Yuval /* Prepare the RSS configuration */ 2137f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2138f29ffdb6SMintz, Yuval if (qed_update_vport_rss(cdev, ¶ms->rss_params, rss)) 2139cee4d264SManish Chopra params->update_rss_flg = 0; 2140cee4d264SManish Chopra 2141cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2142cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2143cee4d264SManish Chopra 2144f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2145f29ffdb6SMintz, Yuval sp_params.rss_params = &rss[i]; 2146f29ffdb6SMintz, Yuval 2147cee4d264SManish Chopra sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2148cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &sp_params, 2149cee4d264SManish Chopra QED_SPQ_MODE_EBLOCK, 2150cee4d264SManish Chopra NULL); 2151cee4d264SManish Chopra if (rc) { 2152cee4d264SManish Chopra DP_ERR(cdev, "Failed to update VPORT\n"); 2153f29ffdb6SMintz, Yuval goto out; 2154cee4d264SManish Chopra } 2155cee4d264SManish Chopra 2156cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2157cee4d264SManish Chopra "Updated V-PORT %d: active_flag %d [update %d]\n", 2158cee4d264SManish Chopra params->vport_id, params->vport_active_flg, 2159cee4d264SManish Chopra params->update_vport_active_flg); 2160cee4d264SManish Chopra } 2161cee4d264SManish Chopra 2162f29ffdb6SMintz, Yuval out: 2163f29ffdb6SMintz, Yuval vfree(rss); 2164f29ffdb6SMintz, Yuval return rc; 2165cee4d264SManish Chopra } 2166cee4d264SManish Chopra 2167cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev, 21683da7a37aSMintz, Yuval u8 rss_num, 21693da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 2170cee4d264SManish Chopra u16 bd_max_bytes, 2171cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 2172cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 2173cee4d264SManish Chopra u16 cqe_pbl_size, 21743da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *ret_params) 2175cee4d264SManish Chopra { 2176cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 21771a635e48SYuval Mintz int rc, hwfn_index; 2178cee4d264SManish Chopra 21793da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2180cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2181cee4d264SManish Chopra 21823da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 21833da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2184cee4d264SManish Chopra 21853da7a37aSMintz, Yuval rc = qed_eth_rx_queue_start(p_hwfn, 2186cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 21873da7a37aSMintz, Yuval p_params, 2188cee4d264SManish Chopra bd_max_bytes, 2189cee4d264SManish Chopra bd_chain_phys_addr, 21903da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, ret_params); 2191cee4d264SManish Chopra if (rc) { 21923da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id); 2193cee4d264SManish Chopra return rc; 2194cee4d264SManish Chopra } 2195cee4d264SManish Chopra 2196cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 21973da7a37aSMintz, Yuval "Started RX-Q %d [rss_num %d] on V-PORT %d and SB %d\n", 21983da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 21993da7a37aSMintz, Yuval p_params->sb); 2200cee4d264SManish Chopra 2201cee4d264SManish Chopra return 0; 2202cee4d264SManish Chopra } 2203cee4d264SManish Chopra 22043da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle) 2205cee4d264SManish Chopra { 2206cee4d264SManish Chopra int rc, hwfn_index; 2207cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2208cee4d264SManish Chopra 22093da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2210cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2211cee4d264SManish Chopra 22123da7a37aSMintz, Yuval rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false); 2213cee4d264SManish Chopra if (rc) { 22143da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id); 2215cee4d264SManish Chopra return rc; 2216cee4d264SManish Chopra } 2217cee4d264SManish Chopra 2218cee4d264SManish Chopra return 0; 2219cee4d264SManish Chopra } 2220cee4d264SManish Chopra 2221cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev, 22223da7a37aSMintz, Yuval u8 rss_num, 2223cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 2224cee4d264SManish Chopra dma_addr_t pbl_addr, 2225cee4d264SManish Chopra u16 pbl_size, 22263da7a37aSMintz, Yuval struct qed_txq_start_ret_params *ret_params) 2227cee4d264SManish Chopra { 2228cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2229cee4d264SManish Chopra int rc, hwfn_index; 2230cee4d264SManish Chopra 22313da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2232cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 22333da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 22343da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2235cee4d264SManish Chopra 22363da7a37aSMintz, Yuval rc = qed_eth_tx_queue_start(p_hwfn, 2237cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 22383da7a37aSMintz, Yuval p_params, 0, 22393da7a37aSMintz, Yuval pbl_addr, pbl_size, ret_params); 2240cee4d264SManish Chopra 2241cee4d264SManish Chopra if (rc) { 2242cee4d264SManish Chopra DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 2243cee4d264SManish Chopra return rc; 2244cee4d264SManish Chopra } 2245cee4d264SManish Chopra 2246cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 22473da7a37aSMintz, Yuval "Started TX-Q %d [rss_num %d] on V-PORT %d and SB %d\n", 22483da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 2249cee4d264SManish Chopra p_params->sb); 2250cee4d264SManish Chopra 2251cee4d264SManish Chopra return 0; 2252cee4d264SManish Chopra } 2253cee4d264SManish Chopra 2254cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10) 2255cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev) 2256cee4d264SManish Chopra { 225715582962SRahul Verma int rc; 225815582962SRahul Verma 225915582962SRahul Verma rc = qed_hw_stop_fastpath(cdev); 226015582962SRahul Verma if (rc) { 226115582962SRahul Verma DP_ERR(cdev, "Failed to stop Fastpath\n"); 226215582962SRahul Verma return rc; 226315582962SRahul Verma } 2264cee4d264SManish Chopra 2265cee4d264SManish Chopra return 0; 2266cee4d264SManish Chopra } 2267cee4d264SManish Chopra 22683da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle) 2269cee4d264SManish Chopra { 2270cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2271cee4d264SManish Chopra int rc, hwfn_index; 2272cee4d264SManish Chopra 22733da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2274cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2275cee4d264SManish Chopra 22763da7a37aSMintz, Yuval rc = qed_eth_tx_queue_stop(p_hwfn, handle); 2277cee4d264SManish Chopra if (rc) { 22783da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id); 2279cee4d264SManish Chopra return rc; 2280cee4d264SManish Chopra } 2281cee4d264SManish Chopra 2282cee4d264SManish Chopra return 0; 2283cee4d264SManish Chopra } 2284cee4d264SManish Chopra 2285464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev, 2286464f6645SManish Chopra struct qed_tunn_params *tunn_params) 2287464f6645SManish Chopra { 228819968430SChopra, Manish struct qed_tunnel_info tunn_info; 2289464f6645SManish Chopra int i, rc; 2290464f6645SManish Chopra 22911408cc1fSYuval Mintz if (IS_VF(cdev)) 22921408cc1fSYuval Mintz return 0; 22931408cc1fSYuval Mintz 2294464f6645SManish Chopra memset(&tunn_info, 0, sizeof(tunn_info)); 229519968430SChopra, Manish if (tunn_params->update_vxlan_port) { 229619968430SChopra, Manish tunn_info.vxlan_port.b_update_port = true; 229719968430SChopra, Manish tunn_info.vxlan_port.port = tunn_params->vxlan_port; 2298464f6645SManish Chopra } 2299464f6645SManish Chopra 230019968430SChopra, Manish if (tunn_params->update_geneve_port) { 230119968430SChopra, Manish tunn_info.geneve_port.b_update_port = true; 230219968430SChopra, Manish tunn_info.geneve_port.port = tunn_params->geneve_port; 2303464f6645SManish Chopra } 2304464f6645SManish Chopra 2305464f6645SManish Chopra for_each_hwfn(cdev, i) { 2306464f6645SManish Chopra struct qed_hwfn *hwfn = &cdev->hwfns[i]; 2307464f6645SManish Chopra 2308464f6645SManish Chopra rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info, 2309464f6645SManish Chopra QED_SPQ_MODE_EBLOCK, NULL); 2310464f6645SManish Chopra if (rc) 2311464f6645SManish Chopra return rc; 2312464f6645SManish Chopra } 2313464f6645SManish Chopra 2314464f6645SManish Chopra return 0; 2315464f6645SManish Chopra } 2316464f6645SManish Chopra 2317cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 2318cee4d264SManish Chopra enum qed_filter_rx_mode_type type) 2319cee4d264SManish Chopra { 2320cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 2321cee4d264SManish Chopra 2322cee4d264SManish Chopra memset(&accept_flags, 0, sizeof(accept_flags)); 2323cee4d264SManish Chopra 2324cee4d264SManish Chopra accept_flags.update_rx_mode_config = 1; 2325cee4d264SManish Chopra accept_flags.update_tx_mode_config = 1; 2326cee4d264SManish Chopra accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2327cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2328cee4d264SManish Chopra QED_ACCEPT_BCAST; 2329cee4d264SManish Chopra accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2330cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2331cee4d264SManish Chopra QED_ACCEPT_BCAST; 2332cee4d264SManish Chopra 233388067876SMintz, Yuval if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 2334cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 2335cee4d264SManish Chopra QED_ACCEPT_MCAST_UNMATCHED; 233688067876SMintz, Yuval accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 233788067876SMintz, Yuval } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 2338cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 233988067876SMintz, Yuval accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 234088067876SMintz, Yuval } 2341cee4d264SManish Chopra 23423f9b4a69SYuval Mintz return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 2343cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 2344cee4d264SManish Chopra } 2345cee4d264SManish Chopra 2346cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev, 2347cee4d264SManish Chopra struct qed_filter_ucast_params *params) 2348cee4d264SManish Chopra { 2349cee4d264SManish Chopra struct qed_filter_ucast ucast; 2350cee4d264SManish Chopra 2351cee4d264SManish Chopra if (!params->vlan_valid && !params->mac_valid) { 23521a635e48SYuval Mintz DP_NOTICE(cdev, 2353cee4d264SManish Chopra "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 2354cee4d264SManish Chopra return -EINVAL; 2355cee4d264SManish Chopra } 2356cee4d264SManish Chopra 2357cee4d264SManish Chopra memset(&ucast, 0, sizeof(ucast)); 2358cee4d264SManish Chopra switch (params->type) { 2359cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2360cee4d264SManish Chopra ucast.opcode = QED_FILTER_ADD; 2361cee4d264SManish Chopra break; 2362cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2363cee4d264SManish Chopra ucast.opcode = QED_FILTER_REMOVE; 2364cee4d264SManish Chopra break; 2365cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_REPLACE: 2366cee4d264SManish Chopra ucast.opcode = QED_FILTER_REPLACE; 2367cee4d264SManish Chopra break; 2368cee4d264SManish Chopra default: 2369cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 2370cee4d264SManish Chopra params->type); 2371cee4d264SManish Chopra } 2372cee4d264SManish Chopra 2373cee4d264SManish Chopra if (params->vlan_valid && params->mac_valid) { 2374cee4d264SManish Chopra ucast.type = QED_FILTER_MAC_VLAN; 2375cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2376cee4d264SManish Chopra ucast.vlan = params->vlan; 2377cee4d264SManish Chopra } else if (params->mac_valid) { 2378cee4d264SManish Chopra ucast.type = QED_FILTER_MAC; 2379cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2380cee4d264SManish Chopra } else { 2381cee4d264SManish Chopra ucast.type = QED_FILTER_VLAN; 2382cee4d264SManish Chopra ucast.vlan = params->vlan; 2383cee4d264SManish Chopra } 2384cee4d264SManish Chopra 2385cee4d264SManish Chopra ucast.is_rx_filter = true; 2386cee4d264SManish Chopra ucast.is_tx_filter = true; 2387cee4d264SManish Chopra 2388cee4d264SManish Chopra return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 2389cee4d264SManish Chopra } 2390cee4d264SManish Chopra 2391cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev, 2392cee4d264SManish Chopra struct qed_filter_mcast_params *params) 2393cee4d264SManish Chopra { 2394cee4d264SManish Chopra struct qed_filter_mcast mcast; 2395cee4d264SManish Chopra int i; 2396cee4d264SManish Chopra 2397cee4d264SManish Chopra memset(&mcast, 0, sizeof(mcast)); 2398cee4d264SManish Chopra switch (params->type) { 2399cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2400cee4d264SManish Chopra mcast.opcode = QED_FILTER_ADD; 2401cee4d264SManish Chopra break; 2402cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2403cee4d264SManish Chopra mcast.opcode = QED_FILTER_REMOVE; 2404cee4d264SManish Chopra break; 2405cee4d264SManish Chopra default: 2406cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 2407cee4d264SManish Chopra params->type); 2408cee4d264SManish Chopra } 2409cee4d264SManish Chopra 2410cee4d264SManish Chopra mcast.num_mc_addrs = params->num; 2411cee4d264SManish Chopra for (i = 0; i < mcast.num_mc_addrs; i++) 2412cee4d264SManish Chopra ether_addr_copy(mcast.mac[i], params->mac[i]); 2413cee4d264SManish Chopra 24141a635e48SYuval Mintz return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL); 2415cee4d264SManish Chopra } 2416cee4d264SManish Chopra 2417cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev, 2418cee4d264SManish Chopra struct qed_filter_params *params) 2419cee4d264SManish Chopra { 2420cee4d264SManish Chopra enum qed_filter_rx_mode_type accept_flags; 2421cee4d264SManish Chopra 2422cee4d264SManish Chopra switch (params->type) { 2423cee4d264SManish Chopra case QED_FILTER_TYPE_UCAST: 2424cee4d264SManish Chopra return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 2425cee4d264SManish Chopra case QED_FILTER_TYPE_MCAST: 2426cee4d264SManish Chopra return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 2427cee4d264SManish Chopra case QED_FILTER_TYPE_RX_MODE: 2428cee4d264SManish Chopra accept_flags = params->filter.accept_flags; 2429cee4d264SManish Chopra return qed_configure_filter_rx_mode(cdev, accept_flags); 2430cee4d264SManish Chopra default: 24311a635e48SYuval Mintz DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type); 2432cee4d264SManish Chopra return -EINVAL; 2433cee4d264SManish Chopra } 2434cee4d264SManish Chopra } 2435cee4d264SManish Chopra 2436d51e4af5SChopra, Manish static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher) 2437d51e4af5SChopra, Manish { 2438d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2439d51e4af5SChopra, Manish struct qed_arfs_config_params arfs_config_params; 2440d51e4af5SChopra, Manish 2441d51e4af5SChopra, Manish memset(&arfs_config_params, 0, sizeof(arfs_config_params)); 2442d51e4af5SChopra, Manish arfs_config_params.tcp = true; 2443d51e4af5SChopra, Manish arfs_config_params.udp = true; 2444d51e4af5SChopra, Manish arfs_config_params.ipv4 = true; 2445d51e4af5SChopra, Manish arfs_config_params.ipv6 = true; 2446d51e4af5SChopra, Manish arfs_config_params.arfs_enable = en_searcher; 2447d51e4af5SChopra, Manish 2448d51e4af5SChopra, Manish qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt, 2449d51e4af5SChopra, Manish &arfs_config_params); 2450d51e4af5SChopra, Manish return 0; 2451d51e4af5SChopra, Manish } 2452d51e4af5SChopra, Manish 2453d51e4af5SChopra, Manish static void 2454d51e4af5SChopra, Manish qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn, 2455d51e4af5SChopra, Manish void *cookie, union event_ring_data *data, 2456d51e4af5SChopra, Manish u8 fw_return_code) 2457d51e4af5SChopra, Manish { 2458d51e4af5SChopra, Manish struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common; 2459d51e4af5SChopra, Manish void *dev = p_hwfn->cdev->ops_cookie; 2460d51e4af5SChopra, Manish 2461d51e4af5SChopra, Manish op->arfs_filter_op(dev, cookie, fw_return_code); 2462d51e4af5SChopra, Manish } 2463d51e4af5SChopra, Manish 2464d51e4af5SChopra, Manish static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie, 2465d51e4af5SChopra, Manish dma_addr_t mapping, u16 length, 2466d51e4af5SChopra, Manish u16 vport_id, u16 rx_queue_id, 2467d51e4af5SChopra, Manish bool add_filter) 2468d51e4af5SChopra, Manish { 2469d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2470d51e4af5SChopra, Manish struct qed_spq_comp_cb cb; 2471d51e4af5SChopra, Manish int rc = -EINVAL; 2472d51e4af5SChopra, Manish 2473d51e4af5SChopra, Manish cb.function = qed_arfs_sp_response_handler; 2474d51e4af5SChopra, Manish cb.cookie = cookie; 2475d51e4af5SChopra, Manish 2476d51e4af5SChopra, Manish rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt, 2477d51e4af5SChopra, Manish &cb, mapping, length, rx_queue_id, 2478d51e4af5SChopra, Manish vport_id, add_filter); 2479d51e4af5SChopra, Manish if (rc) 2480d51e4af5SChopra, Manish DP_NOTICE(p_hwfn, 2481d51e4af5SChopra, Manish "Failed to issue a-RFS filter configuration\n"); 2482d51e4af5SChopra, Manish else 2483d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, 2484d51e4af5SChopra, Manish "Successfully issued a-RFS filter configuration\n"); 2485d51e4af5SChopra, Manish 2486d51e4af5SChopra, Manish return rc; 2487d51e4af5SChopra, Manish } 2488d51e4af5SChopra, Manish 2489cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev, 24901a635e48SYuval Mintz u8 rss_id, struct eth_slow_path_rx_cqe *cqe) 2491cee4d264SManish Chopra { 2492cee4d264SManish Chopra return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 2493cee4d264SManish Chopra cqe); 2494cee4d264SManish Chopra } 2495cee4d264SManish Chopra 24960b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 24970b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass; 24980b55e27dSYuval Mintz #endif 24990b55e27dSYuval Mintz 2500a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2501a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass; 2502a1d8d8a5SSudarsana Reddy Kalluru #endif 2503a1d8d8a5SSudarsana Reddy Kalluru 2504c78c70faSSudarsana Reddy Kalluru extern const struct qed_eth_ptp_ops qed_ptp_ops_pass; 2505c78c70faSSudarsana Reddy Kalluru 250625c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = { 250725c089d7SYuval Mintz .common = &qed_common_ops_pass, 25080b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 25090b55e27dSYuval Mintz .iov = &qed_iov_ops_pass, 25100b55e27dSYuval Mintz #endif 2511a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2512a1d8d8a5SSudarsana Reddy Kalluru .dcb = &qed_dcbnl_ops_pass, 2513a1d8d8a5SSudarsana Reddy Kalluru #endif 2514c78c70faSSudarsana Reddy Kalluru .ptp = &qed_ptp_ops_pass, 251525c089d7SYuval Mintz .fill_dev_info = &qed_fill_eth_dev_info, 2516cc875c2eSYuval Mintz .register_ops = &qed_register_eth_ops, 2517eff16960SYuval Mintz .check_mac = &qed_check_mac, 2518cee4d264SManish Chopra .vport_start = &qed_start_vport, 2519cee4d264SManish Chopra .vport_stop = &qed_stop_vport, 2520cee4d264SManish Chopra .vport_update = &qed_update_vport, 2521cee4d264SManish Chopra .q_rx_start = &qed_start_rxq, 2522cee4d264SManish Chopra .q_rx_stop = &qed_stop_rxq, 2523cee4d264SManish Chopra .q_tx_start = &qed_start_txq, 2524cee4d264SManish Chopra .q_tx_stop = &qed_stop_txq, 2525cee4d264SManish Chopra .filter_config = &qed_configure_filter, 2526cee4d264SManish Chopra .fastpath_stop = &qed_fastpath_stop, 2527cee4d264SManish Chopra .eth_cqe_completion = &qed_fp_cqe_completion, 25289df2ed04SManish Chopra .get_vport_stats = &qed_get_vport_stats, 2529464f6645SManish Chopra .tunn_config = &qed_tunn_configure, 2530d51e4af5SChopra, Manish .ntuple_filter_config = &qed_ntuple_arfs_filter_config, 2531d51e4af5SChopra, Manish .configure_arfs_searcher = &qed_configure_arfs_searcher, 253225c089d7SYuval Mintz }; 253325c089d7SYuval Mintz 253495114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void) 253525c089d7SYuval Mintz { 253625c089d7SYuval Mintz return &qed_eth_ops_pass; 253725c089d7SYuval Mintz } 253825c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops); 253925c089d7SYuval Mintz 254025c089d7SYuval Mintz void qed_put_eth_ops(void) 254125c089d7SYuval Mintz { 254225c089d7SYuval Mintz /* TODO - reference count for module? */ 254325c089d7SYuval Mintz } 254425c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops); 2545