125c089d7SYuval Mintz /* QLogic qed NIC Driver
225c089d7SYuval Mintz  * Copyright (c) 2015 QLogic Corporation
325c089d7SYuval Mintz  *
425c089d7SYuval Mintz  * This software is available under the terms of the GNU General Public License
525c089d7SYuval Mintz  * (GPL) Version 2, available from the file COPYING in the main directory of
625c089d7SYuval Mintz  * this source tree.
725c089d7SYuval Mintz  */
825c089d7SYuval Mintz 
925c089d7SYuval Mintz #include <linux/types.h>
1025c089d7SYuval Mintz #include <asm/byteorder.h>
1125c089d7SYuval Mintz #include <asm/param.h>
1225c089d7SYuval Mintz #include <linux/delay.h>
1325c089d7SYuval Mintz #include <linux/dma-mapping.h>
1425c089d7SYuval Mintz #include <linux/etherdevice.h>
1525c089d7SYuval Mintz #include <linux/interrupt.h>
1625c089d7SYuval Mintz #include <linux/kernel.h>
1725c089d7SYuval Mintz #include <linux/module.h>
1825c089d7SYuval Mintz #include <linux/pci.h>
1925c089d7SYuval Mintz #include <linux/slab.h>
2025c089d7SYuval Mintz #include <linux/stddef.h>
2125c089d7SYuval Mintz #include <linux/string.h>
2225c089d7SYuval Mintz #include <linux/version.h>
2325c089d7SYuval Mintz #include <linux/workqueue.h>
2425c089d7SYuval Mintz #include <linux/bitops.h>
2525c089d7SYuval Mintz #include <linux/bug.h>
2625c089d7SYuval Mintz #include "qed.h"
2725c089d7SYuval Mintz #include <linux/qed/qed_chain.h>
2825c089d7SYuval Mintz #include "qed_cxt.h"
2925c089d7SYuval Mintz #include "qed_dev_api.h"
3025c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h>
3125c089d7SYuval Mintz #include "qed_hsi.h"
3225c089d7SYuval Mintz #include "qed_hw.h"
3325c089d7SYuval Mintz #include "qed_int.h"
34dacd88d6SYuval Mintz #include "qed_l2.h"
3586622ee7SYuval Mintz #include "qed_mcp.h"
3625c089d7SYuval Mintz #include "qed_reg_addr.h"
3725c089d7SYuval Mintz #include "qed_sp.h"
381408cc1fSYuval Mintz #include "qed_sriov.h"
3925c089d7SYuval Mintz 
40088c8618SManish Chopra 
41cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16
42cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41
43cee4d264SManish Chopra 
44dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
45088c8618SManish Chopra 			   struct qed_sp_vport_start_params *p_params)
46cee4d264SManish Chopra {
47cee4d264SManish Chopra 	struct vport_start_ramrod_data *p_ramrod = NULL;
48cee4d264SManish Chopra 	struct qed_spq_entry *p_ent =  NULL;
4906f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
50dacd88d6SYuval Mintz 	u8 abs_vport_id = 0;
51cee4d264SManish Chopra 	int rc = -EINVAL;
52cee4d264SManish Chopra 	u16 rx_mode = 0;
53cee4d264SManish Chopra 
54088c8618SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
55cee4d264SManish Chopra 	if (rc != 0)
56cee4d264SManish Chopra 		return rc;
57cee4d264SManish Chopra 
5806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
5906f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
60088c8618SManish Chopra 	init_data.opaque_fid = p_params->opaque_fid;
6106f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
62cee4d264SManish Chopra 
63cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
64cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_START,
6506f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
66cee4d264SManish Chopra 	if (rc)
67cee4d264SManish Chopra 		return rc;
68cee4d264SManish Chopra 
69cee4d264SManish Chopra 	p_ramrod		= &p_ent->ramrod.vport_start;
70cee4d264SManish Chopra 	p_ramrod->vport_id	= abs_vport_id;
71cee4d264SManish Chopra 
72088c8618SManish Chopra 	p_ramrod->mtu			= cpu_to_le16(p_params->mtu);
73088c8618SManish Chopra 	p_ramrod->inner_vlan_removal_en	= p_params->remove_inner_vlan;
74088c8618SManish Chopra 	p_ramrod->drop_ttl0_en		= p_params->drop_ttl0;
75cee4d264SManish Chopra 
76cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
77cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
78cee4d264SManish Chopra 
79cee4d264SManish Chopra 	p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
80cee4d264SManish Chopra 
81cee4d264SManish Chopra 	/* TPA related fields */
82cee4d264SManish Chopra 	memset(&p_ramrod->tpa_param, 0,
83cee4d264SManish Chopra 	       sizeof(struct eth_vport_tpa_param));
84cee4d264SManish Chopra 
85088c8618SManish Chopra 	p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
86088c8618SManish Chopra 
87088c8618SManish Chopra 	switch (p_params->tpa_mode) {
88088c8618SManish Chopra 	case QED_TPA_MODE_GRO:
89088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
90088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_max_size = (u16)-1;
91088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
92088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
93088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
94088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
95088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
96088c8618SManish Chopra 		p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
97088c8618SManish Chopra 		break;
98088c8618SManish Chopra 	default:
99088c8618SManish Chopra 		break;
100088c8618SManish Chopra 	}
101088c8618SManish Chopra 
102cee4d264SManish Chopra 	/* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
103cee4d264SManish Chopra 	p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
104088c8618SManish Chopra 						  p_params->concrete_fid);
105cee4d264SManish Chopra 
106cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
107cee4d264SManish Chopra }
108cee4d264SManish Chopra 
109dacd88d6SYuval Mintz int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
110dacd88d6SYuval Mintz 		       struct qed_sp_vport_start_params *p_params)
111dacd88d6SYuval Mintz {
112dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
113dacd88d6SYuval Mintz 		return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
114dacd88d6SYuval Mintz 					     p_params->mtu,
115dacd88d6SYuval Mintz 					     p_params->remove_inner_vlan,
116dacd88d6SYuval Mintz 					     p_params->tpa_mode,
11708feecd7SYuval Mintz 					     p_params->max_buffers_per_cqe,
11808feecd7SYuval Mintz 					     p_params->only_untagged);
119dacd88d6SYuval Mintz 	}
120dacd88d6SYuval Mintz 
121dacd88d6SYuval Mintz 	return qed_sp_eth_vport_start(p_hwfn, p_params);
122dacd88d6SYuval Mintz }
123dacd88d6SYuval Mintz 
124cee4d264SManish Chopra static int
125cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
126cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
127cee4d264SManish Chopra 			struct qed_rss_params *p_params)
128cee4d264SManish Chopra {
129cee4d264SManish Chopra 	struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
130cee4d264SManish Chopra 	u16 abs_l2_queue = 0, capabilities = 0;
131cee4d264SManish Chopra 	int rc = 0, i;
132cee4d264SManish Chopra 
133cee4d264SManish Chopra 	if (!p_params) {
134cee4d264SManish Chopra 		p_ramrod->common.update_rss_flg = 0;
135cee4d264SManish Chopra 		return rc;
136cee4d264SManish Chopra 	}
137cee4d264SManish Chopra 
138cee4d264SManish Chopra 	BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
139cee4d264SManish Chopra 		     ETH_RSS_IND_TABLE_ENTRIES_NUM);
140cee4d264SManish Chopra 
141cee4d264SManish Chopra 	rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
142cee4d264SManish Chopra 	if (rc)
143cee4d264SManish Chopra 		return rc;
144cee4d264SManish Chopra 
145cee4d264SManish Chopra 	p_ramrod->common.update_rss_flg = p_params->update_rss_config;
146cee4d264SManish Chopra 	rss->update_rss_capabilities = p_params->update_rss_capabilities;
147cee4d264SManish Chopra 	rss->update_rss_ind_table = p_params->update_rss_ind_table;
148cee4d264SManish Chopra 	rss->update_rss_key = p_params->update_rss_key;
149cee4d264SManish Chopra 
150cee4d264SManish Chopra 	rss->rss_mode = p_params->rss_enable ?
151cee4d264SManish Chopra 			ETH_VPORT_RSS_MODE_REGULAR :
152cee4d264SManish Chopra 			ETH_VPORT_RSS_MODE_DISABLED;
153cee4d264SManish Chopra 
154cee4d264SManish Chopra 	SET_FIELD(capabilities,
155cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
156cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV4));
157cee4d264SManish Chopra 	SET_FIELD(capabilities,
158cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
159cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV6));
160cee4d264SManish Chopra 	SET_FIELD(capabilities,
161cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
162cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
163cee4d264SManish Chopra 	SET_FIELD(capabilities,
164cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
165cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
166cee4d264SManish Chopra 	SET_FIELD(capabilities,
167cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
168cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
169cee4d264SManish Chopra 	SET_FIELD(capabilities,
170cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
171cee4d264SManish Chopra 		  !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
172cee4d264SManish Chopra 	rss->tbl_size = p_params->rss_table_size_log;
173cee4d264SManish Chopra 
174cee4d264SManish Chopra 	rss->capabilities = cpu_to_le16(capabilities);
175cee4d264SManish Chopra 
176cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
177cee4d264SManish Chopra 		   "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
178cee4d264SManish Chopra 		   p_ramrod->common.update_rss_flg,
179cee4d264SManish Chopra 		   rss->rss_mode, rss->update_rss_capabilities,
180cee4d264SManish Chopra 		   capabilities, rss->update_rss_ind_table,
181cee4d264SManish Chopra 		   rss->update_rss_key);
182cee4d264SManish Chopra 
183cee4d264SManish Chopra 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
184cee4d264SManish Chopra 		rc = qed_fw_l2_queue(p_hwfn,
185cee4d264SManish Chopra 				     (u8)p_params->rss_ind_table[i],
186cee4d264SManish Chopra 				     &abs_l2_queue);
187cee4d264SManish Chopra 		if (rc)
188cee4d264SManish Chopra 			return rc;
189cee4d264SManish Chopra 
190cee4d264SManish Chopra 		rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
191cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
192cee4d264SManish Chopra 			   i, rss->indirection_table[i]);
193cee4d264SManish Chopra 	}
194cee4d264SManish Chopra 
195cee4d264SManish Chopra 	for (i = 0; i < 10; i++)
196cee4d264SManish Chopra 		rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
197cee4d264SManish Chopra 
198cee4d264SManish Chopra 	return rc;
199cee4d264SManish Chopra }
200cee4d264SManish Chopra 
201cee4d264SManish Chopra static void
202cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
203cee4d264SManish Chopra 			  struct vport_update_ramrod_data *p_ramrod,
204cee4d264SManish Chopra 			  struct qed_filter_accept_flags accept_flags)
205cee4d264SManish Chopra {
206cee4d264SManish Chopra 	p_ramrod->common.update_rx_mode_flg =
207cee4d264SManish Chopra 		accept_flags.update_rx_mode_config;
208cee4d264SManish Chopra 
209cee4d264SManish Chopra 	p_ramrod->common.update_tx_mode_flg =
210cee4d264SManish Chopra 		accept_flags.update_tx_mode_config;
211cee4d264SManish Chopra 
212cee4d264SManish Chopra 	/* Set Rx mode accept flags */
213cee4d264SManish Chopra 	if (p_ramrod->common.update_rx_mode_flg) {
214cee4d264SManish Chopra 		u8 accept_filter = accept_flags.rx_accept_filter;
215cee4d264SManish Chopra 		u16 state = 0;
216cee4d264SManish Chopra 
217cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
218cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
219cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
220cee4d264SManish Chopra 
221cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
222cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
223cee4d264SManish Chopra 
224cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
225cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
226cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
227cee4d264SManish Chopra 
228cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
229cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
230cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
231cee4d264SManish Chopra 
232cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
233cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
234cee4d264SManish Chopra 
235cee4d264SManish Chopra 		p_ramrod->rx_mode.state = cpu_to_le16(state);
236cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
237cee4d264SManish Chopra 			   "p_ramrod->rx_mode.state = 0x%x\n", state);
238cee4d264SManish Chopra 	}
239cee4d264SManish Chopra 
240cee4d264SManish Chopra 	/* Set Tx mode accept flags */
241cee4d264SManish Chopra 	if (p_ramrod->common.update_tx_mode_flg) {
242cee4d264SManish Chopra 		u8 accept_filter = accept_flags.tx_accept_filter;
243cee4d264SManish Chopra 		u16 state = 0;
244cee4d264SManish Chopra 
245cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
246cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
247cee4d264SManish Chopra 
248cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
249cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
250cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
251cee4d264SManish Chopra 
252cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
253cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
254cee4d264SManish Chopra 
255cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
256cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
257cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
258cee4d264SManish Chopra 
259cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
260cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
261cee4d264SManish Chopra 
262cee4d264SManish Chopra 		p_ramrod->tx_mode.state = cpu_to_le16(state);
263cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
264cee4d264SManish Chopra 			   "p_ramrod->tx_mode.state = 0x%x\n", state);
265cee4d264SManish Chopra 	}
266cee4d264SManish Chopra }
267cee4d264SManish Chopra 
268cee4d264SManish Chopra static void
26917b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
27017b235c1SYuval Mintz 			    struct vport_update_ramrod_data *p_ramrod,
27117b235c1SYuval Mintz 			    struct qed_sge_tpa_params *p_params)
27217b235c1SYuval Mintz {
27317b235c1SYuval Mintz 	struct eth_vport_tpa_param *p_tpa;
27417b235c1SYuval Mintz 
27517b235c1SYuval Mintz 	if (!p_params) {
27617b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
27717b235c1SYuval Mintz 		p_ramrod->common.update_tpa_en_flg = 0;
27817b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
27917b235c1SYuval Mintz 		return;
28017b235c1SYuval Mintz 	}
28117b235c1SYuval Mintz 
28217b235c1SYuval Mintz 	p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
28317b235c1SYuval Mintz 	p_tpa = &p_ramrod->tpa_param;
28417b235c1SYuval Mintz 	p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
28517b235c1SYuval Mintz 	p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
28617b235c1SYuval Mintz 	p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
28717b235c1SYuval Mintz 	p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
28817b235c1SYuval Mintz 
28917b235c1SYuval Mintz 	p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
29017b235c1SYuval Mintz 	p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
29117b235c1SYuval Mintz 	p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
29217b235c1SYuval Mintz 	p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
29317b235c1SYuval Mintz 	p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
29417b235c1SYuval Mintz 	p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
29517b235c1SYuval Mintz 	p_tpa->tpa_max_size = p_params->tpa_max_size;
29617b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
29717b235c1SYuval Mintz 	p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
29817b235c1SYuval Mintz }
29917b235c1SYuval Mintz 
30017b235c1SYuval Mintz static void
301cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
302cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
303cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params)
304cee4d264SManish Chopra {
305cee4d264SManish Chopra 	int i;
306cee4d264SManish Chopra 
307cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
308cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
309cee4d264SManish Chopra 
310cee4d264SManish Chopra 	if (p_params->update_approx_mcast_flg) {
311cee4d264SManish Chopra 		p_ramrod->common.update_approx_mcast_flg = 1;
312cee4d264SManish Chopra 		for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
313cee4d264SManish Chopra 			u32 *p_bins = (u32 *)p_params->bins;
314cee4d264SManish Chopra 			__le32 val = cpu_to_le32(p_bins[i]);
315cee4d264SManish Chopra 
316cee4d264SManish Chopra 			p_ramrod->approx_mcast.bins[i] = val;
317cee4d264SManish Chopra 		}
318cee4d264SManish Chopra 	}
319cee4d264SManish Chopra }
320cee4d264SManish Chopra 
321dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
322cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params,
323cee4d264SManish Chopra 			enum spq_mode comp_mode,
324cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
325cee4d264SManish Chopra {
326cee4d264SManish Chopra 	struct qed_rss_params *p_rss_params = p_params->rss_params;
327cee4d264SManish Chopra 	struct vport_update_ramrod_data_cmn *p_cmn;
32806f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
329cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
330cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
33117b235c1SYuval Mintz 	u8 abs_vport_id = 0, val;
332cee4d264SManish Chopra 	int rc = -EINVAL;
333cee4d264SManish Chopra 
334dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
335dacd88d6SYuval Mintz 		rc = qed_vf_pf_vport_update(p_hwfn, p_params);
336dacd88d6SYuval Mintz 		return rc;
337dacd88d6SYuval Mintz 	}
338dacd88d6SYuval Mintz 
339cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
340cee4d264SManish Chopra 	if (rc != 0)
341cee4d264SManish Chopra 		return rc;
342cee4d264SManish Chopra 
34306f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
34406f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
34506f56b81SYuval Mintz 	init_data.opaque_fid = p_params->opaque_fid;
34606f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
34706f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
348cee4d264SManish Chopra 
349cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
350cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
35106f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
352cee4d264SManish Chopra 	if (rc)
353cee4d264SManish Chopra 		return rc;
354cee4d264SManish Chopra 
355cee4d264SManish Chopra 	/* Copy input params to ramrod according to FW struct */
356cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
357cee4d264SManish Chopra 	p_cmn = &p_ramrod->common;
358cee4d264SManish Chopra 
359cee4d264SManish Chopra 	p_cmn->vport_id = abs_vport_id;
360cee4d264SManish Chopra 	p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
361cee4d264SManish Chopra 	p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
362cee4d264SManish Chopra 	p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
363cee4d264SManish Chopra 	p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3643f9b4a69SYuval Mintz 	p_cmn->accept_any_vlan = p_params->accept_any_vlan;
3653f9b4a69SYuval Mintz 	p_cmn->update_accept_any_vlan_flg =
3663f9b4a69SYuval Mintz 			p_params->update_accept_any_vlan_flg;
36717b235c1SYuval Mintz 
36817b235c1SYuval Mintz 	p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
36917b235c1SYuval Mintz 	val = p_params->update_inner_vlan_removal_flg;
37017b235c1SYuval Mintz 	p_cmn->update_inner_vlan_removal_en_flg = val;
37108feecd7SYuval Mintz 
37208feecd7SYuval Mintz 	p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
37308feecd7SYuval Mintz 	val = p_params->update_default_vlan_enable_flg;
37408feecd7SYuval Mintz 	p_cmn->update_default_vlan_en_flg = val;
37508feecd7SYuval Mintz 
37608feecd7SYuval Mintz 	p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
37708feecd7SYuval Mintz 	p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
37808feecd7SYuval Mintz 
37908feecd7SYuval Mintz 	p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
38008feecd7SYuval Mintz 
38117b235c1SYuval Mintz 	p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
38217b235c1SYuval Mintz 	p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
38317b235c1SYuval Mintz 
384cee4d264SManish Chopra 	rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
385cee4d264SManish Chopra 	if (rc) {
386cee4d264SManish Chopra 		/* Return spq entry which is taken in qed_sp_init_request()*/
387cee4d264SManish Chopra 		qed_spq_return_entry(p_hwfn, p_ent);
388cee4d264SManish Chopra 		return rc;
389cee4d264SManish Chopra 	}
390cee4d264SManish Chopra 
391cee4d264SManish Chopra 	/* Update mcast bins for VFs, PF doesn't use this functionality */
392cee4d264SManish Chopra 	qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
393cee4d264SManish Chopra 
394cee4d264SManish Chopra 	qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
39517b235c1SYuval Mintz 	qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
396cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
397cee4d264SManish Chopra }
398cee4d264SManish Chopra 
399dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
400cee4d264SManish Chopra {
401cee4d264SManish Chopra 	struct vport_stop_ramrod_data *p_ramrod;
40206f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
403cee4d264SManish Chopra 	struct qed_spq_entry *p_ent;
404cee4d264SManish Chopra 	u8 abs_vport_id = 0;
405cee4d264SManish Chopra 	int rc;
406cee4d264SManish Chopra 
407dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
408dacd88d6SYuval Mintz 		return qed_vf_pf_vport_stop(p_hwfn);
409dacd88d6SYuval Mintz 
410cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
411cee4d264SManish Chopra 	if (rc != 0)
412cee4d264SManish Chopra 		return rc;
413cee4d264SManish Chopra 
41406f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
41506f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
41606f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
41706f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
418cee4d264SManish Chopra 
419cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
420cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_STOP,
42106f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
422cee4d264SManish Chopra 	if (rc)
423cee4d264SManish Chopra 		return rc;
424cee4d264SManish Chopra 
425cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_stop;
426cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
427cee4d264SManish Chopra 
428cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
429cee4d264SManish Chopra }
430cee4d264SManish Chopra 
431dacd88d6SYuval Mintz static int
432dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
433dacd88d6SYuval Mintz 		       struct qed_filter_accept_flags *p_accept_flags)
434dacd88d6SYuval Mintz {
435dacd88d6SYuval Mintz 	struct qed_sp_vport_update_params s_params;
436dacd88d6SYuval Mintz 
437dacd88d6SYuval Mintz 	memset(&s_params, 0, sizeof(s_params));
438dacd88d6SYuval Mintz 	memcpy(&s_params.accept_flags, p_accept_flags,
439dacd88d6SYuval Mintz 	       sizeof(struct qed_filter_accept_flags));
440dacd88d6SYuval Mintz 
441dacd88d6SYuval Mintz 	return qed_vf_pf_vport_update(p_hwfn, &s_params);
442dacd88d6SYuval Mintz }
443dacd88d6SYuval Mintz 
444cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev,
445cee4d264SManish Chopra 				 u8 vport,
446cee4d264SManish Chopra 				 struct qed_filter_accept_flags accept_flags,
4473f9b4a69SYuval Mintz 				 u8 update_accept_any_vlan,
4483f9b4a69SYuval Mintz 				 u8 accept_any_vlan,
449cee4d264SManish Chopra 				 enum spq_mode comp_mode,
450cee4d264SManish Chopra 				 struct qed_spq_comp_cb *p_comp_data)
451cee4d264SManish Chopra {
452cee4d264SManish Chopra 	struct qed_sp_vport_update_params vport_update_params;
453cee4d264SManish Chopra 	int i, rc;
454cee4d264SManish Chopra 
455cee4d264SManish Chopra 	/* Prepare and send the vport rx_mode change */
456cee4d264SManish Chopra 	memset(&vport_update_params, 0, sizeof(vport_update_params));
457cee4d264SManish Chopra 	vport_update_params.vport_id = vport;
458cee4d264SManish Chopra 	vport_update_params.accept_flags = accept_flags;
4593f9b4a69SYuval Mintz 	vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
4603f9b4a69SYuval Mintz 	vport_update_params.accept_any_vlan = accept_any_vlan;
461cee4d264SManish Chopra 
462cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
463cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
464cee4d264SManish Chopra 
465cee4d264SManish Chopra 		vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
466cee4d264SManish Chopra 
467dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
468dacd88d6SYuval Mintz 			rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
469dacd88d6SYuval Mintz 			if (rc)
470dacd88d6SYuval Mintz 				return rc;
471dacd88d6SYuval Mintz 			continue;
472dacd88d6SYuval Mintz 		}
473dacd88d6SYuval Mintz 
474cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
475cee4d264SManish Chopra 					 comp_mode, p_comp_data);
476cee4d264SManish Chopra 		if (rc != 0) {
477cee4d264SManish Chopra 			DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
478cee4d264SManish Chopra 			return rc;
479cee4d264SManish Chopra 		}
480cee4d264SManish Chopra 
481cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
482cee4d264SManish Chopra 			   "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
483cee4d264SManish Chopra 			   accept_flags.rx_accept_filter,
484cee4d264SManish Chopra 			   accept_flags.tx_accept_filter);
4853f9b4a69SYuval Mintz 		if (update_accept_any_vlan)
4863f9b4a69SYuval Mintz 			DP_VERBOSE(p_hwfn, QED_MSG_SP,
4873f9b4a69SYuval Mintz 				   "accept_any_vlan=%d configured\n",
4883f9b4a69SYuval Mintz 				   accept_any_vlan);
489cee4d264SManish Chopra 	}
490cee4d264SManish Chopra 
491cee4d264SManish Chopra 	return 0;
492cee4d264SManish Chopra }
493cee4d264SManish Chopra 
494cee4d264SManish Chopra static int qed_sp_release_queue_cid(
495cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn,
496cee4d264SManish Chopra 	struct qed_hw_cid_data *p_cid_data)
497cee4d264SManish Chopra {
498cee4d264SManish Chopra 	if (!p_cid_data->b_cid_allocated)
499cee4d264SManish Chopra 		return 0;
500cee4d264SManish Chopra 
501cee4d264SManish Chopra 	qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
502cee4d264SManish Chopra 
503cee4d264SManish Chopra 	p_cid_data->b_cid_allocated = false;
504cee4d264SManish Chopra 
505cee4d264SManish Chopra 	return 0;
506cee4d264SManish Chopra }
507cee4d264SManish Chopra 
508dacd88d6SYuval Mintz int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
509cee4d264SManish Chopra 				u16 opaque_fid,
510cee4d264SManish Chopra 				u32 cid,
511cee4d264SManish Chopra 				struct qed_queue_start_common_params *params,
512cee4d264SManish Chopra 				u8 stats_id,
513cee4d264SManish Chopra 				u16 bd_max_bytes,
514cee4d264SManish Chopra 				dma_addr_t bd_chain_phys_addr,
515dacd88d6SYuval Mintz 				dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
516cee4d264SManish Chopra {
517cee4d264SManish Chopra 	struct rx_queue_start_ramrod_data *p_ramrod = NULL;
518cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
51906f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
520cee4d264SManish Chopra 	struct qed_hw_cid_data *p_rx_cid;
521cee4d264SManish Chopra 	u16 abs_rx_q_id = 0;
522cee4d264SManish Chopra 	u8 abs_vport_id = 0;
523cee4d264SManish Chopra 	int rc = -EINVAL;
524cee4d264SManish Chopra 
525cee4d264SManish Chopra 	/* Store information for the stop */
526cee4d264SManish Chopra 	p_rx_cid		= &p_hwfn->p_rx_cids[params->queue_id];
527cee4d264SManish Chopra 	p_rx_cid->cid		= cid;
528cee4d264SManish Chopra 	p_rx_cid->opaque_fid	= opaque_fid;
529cee4d264SManish Chopra 	p_rx_cid->vport_id	= params->vport_id;
530cee4d264SManish Chopra 
531cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id);
532cee4d264SManish Chopra 	if (rc != 0)
533cee4d264SManish Chopra 		return rc;
534cee4d264SManish Chopra 
535cee4d264SManish Chopra 	rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id);
536cee4d264SManish Chopra 	if (rc != 0)
537cee4d264SManish Chopra 		return rc;
538cee4d264SManish Chopra 
539cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
540cee4d264SManish Chopra 		   "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
541cee4d264SManish Chopra 		   opaque_fid, cid, params->queue_id, params->vport_id,
542cee4d264SManish Chopra 		   params->sb);
543cee4d264SManish Chopra 
54406f56b81SYuval Mintz 	/* Get SPQ entry */
54506f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
54606f56b81SYuval Mintz 	init_data.cid = cid;
54706f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
54806f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
549cee4d264SManish Chopra 
550cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
551cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_START,
55206f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
553cee4d264SManish Chopra 	if (rc)
554cee4d264SManish Chopra 		return rc;
555cee4d264SManish Chopra 
556cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_start;
557cee4d264SManish Chopra 
558cee4d264SManish Chopra 	p_ramrod->sb_id			= cpu_to_le16(params->sb);
559cee4d264SManish Chopra 	p_ramrod->sb_index		= params->sb_idx;
560cee4d264SManish Chopra 	p_ramrod->vport_id		= abs_vport_id;
561cee4d264SManish Chopra 	p_ramrod->stats_counter_id	= stats_id;
562cee4d264SManish Chopra 	p_ramrod->rx_queue_id		= cpu_to_le16(abs_rx_q_id);
563cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg	= 0;
564cee4d264SManish Chopra 	p_ramrod->complete_event_flg	= 1;
565cee4d264SManish Chopra 
566cee4d264SManish Chopra 	p_ramrod->bd_max_bytes	= cpu_to_le16(bd_max_bytes);
56794494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
568cee4d264SManish Chopra 
569cee4d264SManish Chopra 	p_ramrod->num_of_pbl_pages	= cpu_to_le16(cqe_pbl_size);
57094494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
571cee4d264SManish Chopra 
572cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
573cee4d264SManish Chopra 
574cee4d264SManish Chopra 	return rc;
575cee4d264SManish Chopra }
576cee4d264SManish Chopra 
577cee4d264SManish Chopra static int
578cee4d264SManish Chopra qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
579cee4d264SManish Chopra 			  u16 opaque_fid,
580cee4d264SManish Chopra 			  struct qed_queue_start_common_params *params,
581cee4d264SManish Chopra 			  u16 bd_max_bytes,
582cee4d264SManish Chopra 			  dma_addr_t bd_chain_phys_addr,
583cee4d264SManish Chopra 			  dma_addr_t cqe_pbl_addr,
584dacd88d6SYuval Mintz 			  u16 cqe_pbl_size, void __iomem **pp_prod)
585cee4d264SManish Chopra {
586cee4d264SManish Chopra 	struct qed_hw_cid_data *p_rx_cid;
587cee4d264SManish Chopra 	u64 init_prod_val = 0;
588cee4d264SManish Chopra 	u16 abs_l2_queue = 0;
589cee4d264SManish Chopra 	u8 abs_stats_id = 0;
590cee4d264SManish Chopra 	int rc;
591cee4d264SManish Chopra 
592dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
593dacd88d6SYuval Mintz 		return qed_vf_pf_rxq_start(p_hwfn,
594dacd88d6SYuval Mintz 					   params->queue_id,
595dacd88d6SYuval Mintz 					   params->sb,
596dacd88d6SYuval Mintz 					   params->sb_idx,
597dacd88d6SYuval Mintz 					   bd_max_bytes,
598dacd88d6SYuval Mintz 					   bd_chain_phys_addr,
599dacd88d6SYuval Mintz 					   cqe_pbl_addr, cqe_pbl_size, pp_prod);
600dacd88d6SYuval Mintz 	}
601dacd88d6SYuval Mintz 
602cee4d264SManish Chopra 	rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue);
603cee4d264SManish Chopra 	if (rc != 0)
604cee4d264SManish Chopra 		return rc;
605cee4d264SManish Chopra 
606cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id);
607cee4d264SManish Chopra 	if (rc != 0)
608cee4d264SManish Chopra 		return rc;
609cee4d264SManish Chopra 
610cee4d264SManish Chopra 	*pp_prod = (u8 __iomem *)p_hwfn->regview +
611cee4d264SManish Chopra 				 GTT_BAR0_MAP_REG_MSDM_RAM +
612cee4d264SManish Chopra 				 MSTORM_PRODS_OFFSET(abs_l2_queue);
613cee4d264SManish Chopra 
614cee4d264SManish Chopra 	/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
615cee4d264SManish Chopra 	__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
616cee4d264SManish Chopra 			  (u32 *)(&init_prod_val));
617cee4d264SManish Chopra 
618cee4d264SManish Chopra 	/* Allocate a CID for the queue */
619cee4d264SManish Chopra 	p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
620cee4d264SManish Chopra 	rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
621cee4d264SManish Chopra 				 &p_rx_cid->cid);
622cee4d264SManish Chopra 	if (rc) {
623cee4d264SManish Chopra 		DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
624cee4d264SManish Chopra 		return rc;
625cee4d264SManish Chopra 	}
626cee4d264SManish Chopra 	p_rx_cid->b_cid_allocated = true;
627cee4d264SManish Chopra 
628cee4d264SManish Chopra 	rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
629cee4d264SManish Chopra 					 opaque_fid,
630cee4d264SManish Chopra 					 p_rx_cid->cid,
631cee4d264SManish Chopra 					 params,
632cee4d264SManish Chopra 					 abs_stats_id,
633cee4d264SManish Chopra 					 bd_max_bytes,
634cee4d264SManish Chopra 					 bd_chain_phys_addr,
635cee4d264SManish Chopra 					 cqe_pbl_addr,
636cee4d264SManish Chopra 					 cqe_pbl_size);
637cee4d264SManish Chopra 
638cee4d264SManish Chopra 	if (rc != 0)
639cee4d264SManish Chopra 		qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
640cee4d264SManish Chopra 
641cee4d264SManish Chopra 	return rc;
642cee4d264SManish Chopra }
643cee4d264SManish Chopra 
64417b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
64517b235c1SYuval Mintz 				u16 rx_queue_id,
64617b235c1SYuval Mintz 				u8 num_rxqs,
64717b235c1SYuval Mintz 				u8 complete_cqe_flg,
64817b235c1SYuval Mintz 				u8 complete_event_flg,
64917b235c1SYuval Mintz 				enum spq_mode comp_mode,
65017b235c1SYuval Mintz 				struct qed_spq_comp_cb *p_comp_data)
65117b235c1SYuval Mintz {
65217b235c1SYuval Mintz 	struct rx_queue_update_ramrod_data *p_ramrod = NULL;
65317b235c1SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
65417b235c1SYuval Mintz 	struct qed_sp_init_data init_data;
65517b235c1SYuval Mintz 	struct qed_hw_cid_data *p_rx_cid;
65617b235c1SYuval Mintz 	u16 qid, abs_rx_q_id = 0;
65717b235c1SYuval Mintz 	int rc = -EINVAL;
65817b235c1SYuval Mintz 	u8 i;
65917b235c1SYuval Mintz 
66017b235c1SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
66117b235c1SYuval Mintz 	init_data.comp_mode = comp_mode;
66217b235c1SYuval Mintz 	init_data.p_comp_data = p_comp_data;
66317b235c1SYuval Mintz 
66417b235c1SYuval Mintz 	for (i = 0; i < num_rxqs; i++) {
66517b235c1SYuval Mintz 		qid = rx_queue_id + i;
66617b235c1SYuval Mintz 		p_rx_cid = &p_hwfn->p_rx_cids[qid];
66717b235c1SYuval Mintz 
66817b235c1SYuval Mintz 		/* Get SPQ entry */
66917b235c1SYuval Mintz 		init_data.cid = p_rx_cid->cid;
67017b235c1SYuval Mintz 		init_data.opaque_fid = p_rx_cid->opaque_fid;
67117b235c1SYuval Mintz 
67217b235c1SYuval Mintz 		rc = qed_sp_init_request(p_hwfn, &p_ent,
67317b235c1SYuval Mintz 					 ETH_RAMROD_RX_QUEUE_UPDATE,
67417b235c1SYuval Mintz 					 PROTOCOLID_ETH, &init_data);
67517b235c1SYuval Mintz 		if (rc)
67617b235c1SYuval Mintz 			return rc;
67717b235c1SYuval Mintz 
67817b235c1SYuval Mintz 		p_ramrod = &p_ent->ramrod.rx_queue_update;
67917b235c1SYuval Mintz 
68017b235c1SYuval Mintz 		qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
68117b235c1SYuval Mintz 		qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
68217b235c1SYuval Mintz 		p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
68317b235c1SYuval Mintz 		p_ramrod->complete_cqe_flg = complete_cqe_flg;
68417b235c1SYuval Mintz 		p_ramrod->complete_event_flg = complete_event_flg;
68517b235c1SYuval Mintz 
68617b235c1SYuval Mintz 		rc = qed_spq_post(p_hwfn, p_ent, NULL);
68717b235c1SYuval Mintz 		if (rc)
68817b235c1SYuval Mintz 			return rc;
68917b235c1SYuval Mintz 	}
69017b235c1SYuval Mintz 
69117b235c1SYuval Mintz 	return rc;
69217b235c1SYuval Mintz }
69317b235c1SYuval Mintz 
694dacd88d6SYuval Mintz int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
695cee4d264SManish Chopra 			     u16 rx_queue_id,
696dacd88d6SYuval Mintz 			     bool eq_completion_only, bool cqe_completion)
697cee4d264SManish Chopra {
698cee4d264SManish Chopra 	struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
699cee4d264SManish Chopra 	struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
700cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
70106f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
702cee4d264SManish Chopra 	u16 abs_rx_q_id = 0;
703cee4d264SManish Chopra 	int rc = -EINVAL;
704cee4d264SManish Chopra 
705dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
706dacd88d6SYuval Mintz 		return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion);
707dacd88d6SYuval Mintz 
70806f56b81SYuval Mintz 	/* Get SPQ entry */
70906f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
71006f56b81SYuval Mintz 	init_data.cid = p_rx_cid->cid;
71106f56b81SYuval Mintz 	init_data.opaque_fid = p_rx_cid->opaque_fid;
71206f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
713cee4d264SManish Chopra 
714cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
715cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_STOP,
71606f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
717cee4d264SManish Chopra 	if (rc)
718cee4d264SManish Chopra 		return rc;
719cee4d264SManish Chopra 
720cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_stop;
721cee4d264SManish Chopra 
722cee4d264SManish Chopra 	qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
723cee4d264SManish Chopra 	qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
724cee4d264SManish Chopra 	p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
725cee4d264SManish Chopra 
726cee4d264SManish Chopra 	/* Cleaning the queue requires the completion to arrive there.
727cee4d264SManish Chopra 	 * In addition, VFs require the answer to come as eqe to PF.
728cee4d264SManish Chopra 	 */
729cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg =
730cee4d264SManish Chopra 		(!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
731cee4d264SManish Chopra 		 !eq_completion_only) || cqe_completion;
732cee4d264SManish Chopra 	p_ramrod->complete_event_flg =
733cee4d264SManish Chopra 		!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
734cee4d264SManish Chopra 		eq_completion_only;
735cee4d264SManish Chopra 
736cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
737cee4d264SManish Chopra 	if (rc)
738cee4d264SManish Chopra 		return rc;
739cee4d264SManish Chopra 
740cee4d264SManish Chopra 	return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
741cee4d264SManish Chopra }
742cee4d264SManish Chopra 
743dacd88d6SYuval Mintz int qed_sp_eth_txq_start_ramrod(struct qed_hwfn  *p_hwfn,
744cee4d264SManish Chopra 				u16  opaque_fid,
745cee4d264SManish Chopra 				u32  cid,
746cee4d264SManish Chopra 				struct qed_queue_start_common_params *p_params,
747cee4d264SManish Chopra 				u8  stats_id,
748cee4d264SManish Chopra 				dma_addr_t pbl_addr,
749cee4d264SManish Chopra 				u16 pbl_size,
750cee4d264SManish Chopra 				union qed_qm_pq_params *p_pq_params)
751cee4d264SManish Chopra {
752cee4d264SManish Chopra 	struct tx_queue_start_ramrod_data *p_ramrod = NULL;
753cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
75406f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
755cee4d264SManish Chopra 	struct qed_hw_cid_data *p_tx_cid;
756cee4d264SManish Chopra 	u8 abs_vport_id;
757cee4d264SManish Chopra 	int rc = -EINVAL;
758cee4d264SManish Chopra 	u16 pq_id;
759cee4d264SManish Chopra 
760cee4d264SManish Chopra 	/* Store information for the stop */
761cee4d264SManish Chopra 	p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
762cee4d264SManish Chopra 	p_tx_cid->cid		= cid;
763cee4d264SManish Chopra 	p_tx_cid->opaque_fid	= opaque_fid;
764cee4d264SManish Chopra 
765cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
766cee4d264SManish Chopra 	if (rc)
767cee4d264SManish Chopra 		return rc;
768cee4d264SManish Chopra 
76906f56b81SYuval Mintz 	/* Get SPQ entry */
77006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
77106f56b81SYuval Mintz 	init_data.cid = cid;
77206f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
77306f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
774cee4d264SManish Chopra 
77506f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
776cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_START,
77706f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
778cee4d264SManish Chopra 	if (rc)
779cee4d264SManish Chopra 		return rc;
780cee4d264SManish Chopra 
781cee4d264SManish Chopra 	p_ramrod		= &p_ent->ramrod.tx_queue_start;
782cee4d264SManish Chopra 	p_ramrod->vport_id	= abs_vport_id;
783cee4d264SManish Chopra 
784cee4d264SManish Chopra 	p_ramrod->sb_id			= cpu_to_le16(p_params->sb);
785cee4d264SManish Chopra 	p_ramrod->sb_index		= p_params->sb_idx;
786cee4d264SManish Chopra 	p_ramrod->stats_counter_id	= stats_id;
787cee4d264SManish Chopra 
788cee4d264SManish Chopra 	p_ramrod->pbl_size		= cpu_to_le16(pbl_size);
78994494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
790cee4d264SManish Chopra 
791cee4d264SManish Chopra 	pq_id			= qed_get_qm_pq(p_hwfn,
792cee4d264SManish Chopra 						PROTOCOLID_ETH,
793cee4d264SManish Chopra 						p_pq_params);
794cee4d264SManish Chopra 	p_ramrod->qm_pq_id	= cpu_to_le16(pq_id);
795cee4d264SManish Chopra 
796cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
797cee4d264SManish Chopra }
798cee4d264SManish Chopra 
799cee4d264SManish Chopra static int
800cee4d264SManish Chopra qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
801cee4d264SManish Chopra 			  u16 opaque_fid,
802cee4d264SManish Chopra 			  struct qed_queue_start_common_params *p_params,
803cee4d264SManish Chopra 			  dma_addr_t pbl_addr,
804dacd88d6SYuval Mintz 			  u16 pbl_size, void __iomem **pp_doorbell)
805cee4d264SManish Chopra {
806cee4d264SManish Chopra 	struct qed_hw_cid_data *p_tx_cid;
807cee4d264SManish Chopra 	union qed_qm_pq_params pq_params;
808cee4d264SManish Chopra 	u8 abs_stats_id = 0;
809cee4d264SManish Chopra 	int rc;
810cee4d264SManish Chopra 
811dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
812dacd88d6SYuval Mintz 		return qed_vf_pf_txq_start(p_hwfn,
813dacd88d6SYuval Mintz 					   p_params->queue_id,
814dacd88d6SYuval Mintz 					   p_params->sb,
815dacd88d6SYuval Mintz 					   p_params->sb_idx,
816dacd88d6SYuval Mintz 					   pbl_addr, pbl_size, pp_doorbell);
817dacd88d6SYuval Mintz 	}
818dacd88d6SYuval Mintz 
819cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
820cee4d264SManish Chopra 	if (rc)
821cee4d264SManish Chopra 		return rc;
822cee4d264SManish Chopra 
823cee4d264SManish Chopra 	p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
824cee4d264SManish Chopra 	memset(p_tx_cid, 0, sizeof(*p_tx_cid));
825cee4d264SManish Chopra 	memset(&pq_params, 0, sizeof(pq_params));
826cee4d264SManish Chopra 
827cee4d264SManish Chopra 	/* Allocate a CID for the queue */
828cee4d264SManish Chopra 	rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
829cee4d264SManish Chopra 				 &p_tx_cid->cid);
830cee4d264SManish Chopra 	if (rc) {
831cee4d264SManish Chopra 		DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
832cee4d264SManish Chopra 		return rc;
833cee4d264SManish Chopra 	}
834cee4d264SManish Chopra 	p_tx_cid->b_cid_allocated = true;
835cee4d264SManish Chopra 
836cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
837cee4d264SManish Chopra 		   "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
838cee4d264SManish Chopra 		   opaque_fid, p_tx_cid->cid,
839cee4d264SManish Chopra 		   p_params->queue_id, p_params->vport_id, p_params->sb);
840cee4d264SManish Chopra 
841cee4d264SManish Chopra 	rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
842cee4d264SManish Chopra 					 opaque_fid,
843cee4d264SManish Chopra 					 p_tx_cid->cid,
844cee4d264SManish Chopra 					 p_params,
845cee4d264SManish Chopra 					 abs_stats_id,
846cee4d264SManish Chopra 					 pbl_addr,
847cee4d264SManish Chopra 					 pbl_size,
848cee4d264SManish Chopra 					 &pq_params);
849cee4d264SManish Chopra 
850cee4d264SManish Chopra 	*pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
851cee4d264SManish Chopra 				     qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
852cee4d264SManish Chopra 
853cee4d264SManish Chopra 	if (rc)
854cee4d264SManish Chopra 		qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
855cee4d264SManish Chopra 
856cee4d264SManish Chopra 	return rc;
857cee4d264SManish Chopra }
858cee4d264SManish Chopra 
859dacd88d6SYuval Mintz int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id)
860cee4d264SManish Chopra {
861cee4d264SManish Chopra 	struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
862cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
86306f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
864cee4d264SManish Chopra 	int rc = -EINVAL;
865cee4d264SManish Chopra 
866dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
867dacd88d6SYuval Mintz 		return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id);
868dacd88d6SYuval Mintz 
86906f56b81SYuval Mintz 	/* Get SPQ entry */
87006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
87106f56b81SYuval Mintz 	init_data.cid = p_tx_cid->cid;
87206f56b81SYuval Mintz 	init_data.opaque_fid = p_tx_cid->opaque_fid;
87306f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
874cee4d264SManish Chopra 
875cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
876cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_STOP,
87706f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
878cee4d264SManish Chopra 	if (rc)
879cee4d264SManish Chopra 		return rc;
880cee4d264SManish Chopra 
881cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
882cee4d264SManish Chopra 	if (rc)
883cee4d264SManish Chopra 		return rc;
884cee4d264SManish Chopra 
885cee4d264SManish Chopra 	return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
886cee4d264SManish Chopra }
887cee4d264SManish Chopra 
888cee4d264SManish Chopra static enum eth_filter_action
889cee4d264SManish Chopra qed_filter_action(enum qed_filter_opcode opcode)
890cee4d264SManish Chopra {
891cee4d264SManish Chopra 	enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
892cee4d264SManish Chopra 
893cee4d264SManish Chopra 	switch (opcode) {
894cee4d264SManish Chopra 	case QED_FILTER_ADD:
895cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_ADD;
896cee4d264SManish Chopra 		break;
897cee4d264SManish Chopra 	case QED_FILTER_REMOVE:
898cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_REMOVE;
899cee4d264SManish Chopra 		break;
900cee4d264SManish Chopra 	case QED_FILTER_FLUSH:
901fc48b7a6SYuval Mintz 		action = ETH_FILTER_ACTION_REMOVE_ALL;
902cee4d264SManish Chopra 		break;
903cee4d264SManish Chopra 	default:
904cee4d264SManish Chopra 		action = MAX_ETH_FILTER_ACTION;
905cee4d264SManish Chopra 	}
906cee4d264SManish Chopra 
907cee4d264SManish Chopra 	return action;
908cee4d264SManish Chopra }
909cee4d264SManish Chopra 
910cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb,
911cee4d264SManish Chopra 				__le16 *fw_mid,
912cee4d264SManish Chopra 				__le16 *fw_lsb,
913cee4d264SManish Chopra 				u8 *mac)
914cee4d264SManish Chopra {
915cee4d264SManish Chopra 	((u8 *)fw_msb)[0] = mac[1];
916cee4d264SManish Chopra 	((u8 *)fw_msb)[1] = mac[0];
917cee4d264SManish Chopra 	((u8 *)fw_mid)[0] = mac[3];
918cee4d264SManish Chopra 	((u8 *)fw_mid)[1] = mac[2];
919cee4d264SManish Chopra 	((u8 *)fw_lsb)[0] = mac[5];
920cee4d264SManish Chopra 	((u8 *)fw_lsb)[1] = mac[4];
921cee4d264SManish Chopra }
922cee4d264SManish Chopra 
923cee4d264SManish Chopra static int
924cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
925cee4d264SManish Chopra 			u16 opaque_fid,
926cee4d264SManish Chopra 			struct qed_filter_ucast *p_filter_cmd,
927cee4d264SManish Chopra 			struct vport_filter_update_ramrod_data **pp_ramrod,
928cee4d264SManish Chopra 			struct qed_spq_entry **pp_ent,
929cee4d264SManish Chopra 			enum spq_mode comp_mode,
930cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
931cee4d264SManish Chopra {
932cee4d264SManish Chopra 	u8 vport_to_add_to = 0, vport_to_remove_from = 0;
933cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data *p_ramrod;
934cee4d264SManish Chopra 	struct eth_filter_cmd *p_first_filter;
935cee4d264SManish Chopra 	struct eth_filter_cmd *p_second_filter;
93606f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
937cee4d264SManish Chopra 	enum eth_filter_action action;
938cee4d264SManish Chopra 	int rc;
939cee4d264SManish Chopra 
940cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
941cee4d264SManish Chopra 			  &vport_to_remove_from);
942cee4d264SManish Chopra 	if (rc)
943cee4d264SManish Chopra 		return rc;
944cee4d264SManish Chopra 
945cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
946cee4d264SManish Chopra 			  &vport_to_add_to);
947cee4d264SManish Chopra 	if (rc)
948cee4d264SManish Chopra 		return rc;
949cee4d264SManish Chopra 
95006f56b81SYuval Mintz 	/* Get SPQ entry */
95106f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
95206f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
95306f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
95406f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
95506f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
956cee4d264SManish Chopra 
957cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, pp_ent,
958cee4d264SManish Chopra 				 ETH_RAMROD_FILTERS_UPDATE,
95906f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
960cee4d264SManish Chopra 	if (rc)
961cee4d264SManish Chopra 		return rc;
962cee4d264SManish Chopra 
963cee4d264SManish Chopra 	*pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
964cee4d264SManish Chopra 	p_ramrod = *pp_ramrod;
965cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
966cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
967cee4d264SManish Chopra 
968cee4d264SManish Chopra 	switch (p_filter_cmd->opcode) {
969fc48b7a6SYuval Mintz 	case QED_FILTER_REPLACE:
970cee4d264SManish Chopra 	case QED_FILTER_MOVE:
971cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
972cee4d264SManish Chopra 	default:
973cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
974cee4d264SManish Chopra 	}
975cee4d264SManish Chopra 
976cee4d264SManish Chopra 	p_first_filter	= &p_ramrod->filter_cmds[0];
977cee4d264SManish Chopra 	p_second_filter = &p_ramrod->filter_cmds[1];
978cee4d264SManish Chopra 
979cee4d264SManish Chopra 	switch (p_filter_cmd->type) {
980cee4d264SManish Chopra 	case QED_FILTER_MAC:
981cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
982cee4d264SManish Chopra 	case QED_FILTER_VLAN:
983cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
984cee4d264SManish Chopra 	case QED_FILTER_MAC_VLAN:
985cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
986cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC:
987cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
988cee4d264SManish Chopra 	case QED_FILTER_INNER_VLAN:
989cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
990cee4d264SManish Chopra 	case QED_FILTER_INNER_PAIR:
991cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
992cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC_VNI_PAIR:
993cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
994cee4d264SManish Chopra 		break;
995cee4d264SManish Chopra 	case QED_FILTER_MAC_VNI_PAIR:
996cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
997cee4d264SManish Chopra 	case QED_FILTER_VNI:
998cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
999cee4d264SManish Chopra 	}
1000cee4d264SManish Chopra 
1001cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1002cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1003cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1004cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1005cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1006cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1007cee4d264SManish Chopra 		qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1008cee4d264SManish Chopra 				    &p_first_filter->mac_mid,
1009cee4d264SManish Chopra 				    &p_first_filter->mac_lsb,
1010cee4d264SManish Chopra 				    (u8 *)p_filter_cmd->mac);
1011cee4d264SManish Chopra 	}
1012cee4d264SManish Chopra 
1013cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1014cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1015cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1016cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1017cee4d264SManish Chopra 		p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1018cee4d264SManish Chopra 
1019cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1020cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1021cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1022cee4d264SManish Chopra 		p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1023cee4d264SManish Chopra 
1024cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1025cee4d264SManish Chopra 		p_second_filter->type		= p_first_filter->type;
1026cee4d264SManish Chopra 		p_second_filter->mac_msb	= p_first_filter->mac_msb;
1027cee4d264SManish Chopra 		p_second_filter->mac_mid	= p_first_filter->mac_mid;
1028cee4d264SManish Chopra 		p_second_filter->mac_lsb	= p_first_filter->mac_lsb;
1029cee4d264SManish Chopra 		p_second_filter->vlan_id	= p_first_filter->vlan_id;
1030cee4d264SManish Chopra 		p_second_filter->vni		= p_first_filter->vni;
1031cee4d264SManish Chopra 
1032cee4d264SManish Chopra 		p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1033cee4d264SManish Chopra 
1034cee4d264SManish Chopra 		p_first_filter->vport_id = vport_to_remove_from;
1035cee4d264SManish Chopra 
1036cee4d264SManish Chopra 		p_second_filter->action		= ETH_FILTER_ACTION_ADD;
1037cee4d264SManish Chopra 		p_second_filter->vport_id	= vport_to_add_to;
1038fc48b7a6SYuval Mintz 	} else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1039fc48b7a6SYuval Mintz 		p_first_filter->vport_id = vport_to_add_to;
1040fc48b7a6SYuval Mintz 		memcpy(p_second_filter, p_first_filter,
1041fc48b7a6SYuval Mintz 		       sizeof(*p_second_filter));
1042fc48b7a6SYuval Mintz 		p_first_filter->action	= ETH_FILTER_ACTION_REMOVE_ALL;
1043fc48b7a6SYuval Mintz 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1044cee4d264SManish Chopra 	} else {
1045cee4d264SManish Chopra 		action = qed_filter_action(p_filter_cmd->opcode);
1046cee4d264SManish Chopra 
1047cee4d264SManish Chopra 		if (action == MAX_ETH_FILTER_ACTION) {
1048cee4d264SManish Chopra 			DP_NOTICE(p_hwfn,
1049cee4d264SManish Chopra 				  "%d is not supported yet\n",
1050cee4d264SManish Chopra 				  p_filter_cmd->opcode);
1051cee4d264SManish Chopra 			return -EINVAL;
1052cee4d264SManish Chopra 		}
1053cee4d264SManish Chopra 
1054cee4d264SManish Chopra 		p_first_filter->action = action;
1055cee4d264SManish Chopra 		p_first_filter->vport_id = (p_filter_cmd->opcode ==
1056cee4d264SManish Chopra 					    QED_FILTER_REMOVE) ?
1057cee4d264SManish Chopra 					   vport_to_remove_from :
1058cee4d264SManish Chopra 					   vport_to_add_to;
1059cee4d264SManish Chopra 	}
1060cee4d264SManish Chopra 
1061cee4d264SManish Chopra 	return 0;
1062cee4d264SManish Chopra }
1063cee4d264SManish Chopra 
1064dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1065cee4d264SManish Chopra 			    u16 opaque_fid,
1066cee4d264SManish Chopra 			    struct qed_filter_ucast *p_filter_cmd,
1067cee4d264SManish Chopra 			    enum spq_mode comp_mode,
1068cee4d264SManish Chopra 			    struct qed_spq_comp_cb *p_comp_data)
1069cee4d264SManish Chopra {
1070cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data	*p_ramrod	= NULL;
1071cee4d264SManish Chopra 	struct qed_spq_entry			*p_ent		= NULL;
1072cee4d264SManish Chopra 	struct eth_filter_cmd_header		*p_header;
1073cee4d264SManish Chopra 	int					rc;
1074cee4d264SManish Chopra 
1075cee4d264SManish Chopra 	rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1076cee4d264SManish Chopra 				     &p_ramrod, &p_ent,
1077cee4d264SManish Chopra 				     comp_mode, p_comp_data);
1078cee4d264SManish Chopra 	if (rc != 0) {
1079cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1080cee4d264SManish Chopra 		return rc;
1081cee4d264SManish Chopra 	}
1082cee4d264SManish Chopra 	p_header = &p_ramrod->filter_cmd_hdr;
1083cee4d264SManish Chopra 	p_header->assert_on_error = p_filter_cmd->assert_on_error;
1084cee4d264SManish Chopra 
1085cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
1086cee4d264SManish Chopra 	if (rc != 0) {
1087cee4d264SManish Chopra 		DP_ERR(p_hwfn,
1088cee4d264SManish Chopra 		       "Unicast filter ADD command failed %d\n",
1089cee4d264SManish Chopra 		       rc);
1090cee4d264SManish Chopra 		return rc;
1091cee4d264SManish Chopra 	}
1092cee4d264SManish Chopra 
1093cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1094cee4d264SManish Chopra 		   "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1095cee4d264SManish Chopra 		   (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1096cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1097cee4d264SManish Chopra 		   "REMOVE" :
1098cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1099cee4d264SManish Chopra 		    "MOVE" : "REPLACE")),
1100cee4d264SManish Chopra 		   (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1101cee4d264SManish Chopra 		   ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1102cee4d264SManish Chopra 		    "VLAN" : "MAC & VLAN"),
1103cee4d264SManish Chopra 		   p_ramrod->filter_cmd_hdr.cmd_cnt,
1104cee4d264SManish Chopra 		   p_filter_cmd->is_rx_filter,
1105cee4d264SManish Chopra 		   p_filter_cmd->is_tx_filter);
1106cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1107cee4d264SManish Chopra 		   "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1108cee4d264SManish Chopra 		   p_filter_cmd->vport_to_add_to,
1109cee4d264SManish Chopra 		   p_filter_cmd->vport_to_remove_from,
1110cee4d264SManish Chopra 		   p_filter_cmd->mac[0],
1111cee4d264SManish Chopra 		   p_filter_cmd->mac[1],
1112cee4d264SManish Chopra 		   p_filter_cmd->mac[2],
1113cee4d264SManish Chopra 		   p_filter_cmd->mac[3],
1114cee4d264SManish Chopra 		   p_filter_cmd->mac[4],
1115cee4d264SManish Chopra 		   p_filter_cmd->mac[5],
1116cee4d264SManish Chopra 		   p_filter_cmd->vlan);
1117cee4d264SManish Chopra 
1118cee4d264SManish Chopra 	return 0;
1119cee4d264SManish Chopra }
1120cee4d264SManish Chopra 
1121cee4d264SManish Chopra /*******************************************************************************
1122cee4d264SManish Chopra  * Description:
1123cee4d264SManish Chopra  *         Calculates crc 32 on a buffer
1124cee4d264SManish Chopra  *         Note: crc32_length MUST be aligned to 8
1125cee4d264SManish Chopra  * Return:
1126cee4d264SManish Chopra  ******************************************************************************/
1127cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet,
1128cee4d264SManish Chopra 			   u32 crc32_length,
1129cee4d264SManish Chopra 			   u32 crc32_seed,
1130cee4d264SManish Chopra 			   u8 complement)
1131cee4d264SManish Chopra {
1132cee4d264SManish Chopra 	u32 byte = 0;
1133cee4d264SManish Chopra 	u32 bit = 0;
1134cee4d264SManish Chopra 	u8 msb = 0;
1135cee4d264SManish Chopra 	u8 current_byte = 0;
1136cee4d264SManish Chopra 	u32 crc32_result = crc32_seed;
1137cee4d264SManish Chopra 
1138cee4d264SManish Chopra 	if ((!crc32_packet) ||
1139cee4d264SManish Chopra 	    (crc32_length == 0) ||
1140cee4d264SManish Chopra 	    ((crc32_length % 8) != 0))
1141cee4d264SManish Chopra 		return crc32_result;
1142cee4d264SManish Chopra 	for (byte = 0; byte < crc32_length; byte++) {
1143cee4d264SManish Chopra 		current_byte = crc32_packet[byte];
1144cee4d264SManish Chopra 		for (bit = 0; bit < 8; bit++) {
1145cee4d264SManish Chopra 			msb = (u8)(crc32_result >> 31);
1146cee4d264SManish Chopra 			crc32_result = crc32_result << 1;
1147cee4d264SManish Chopra 			if (msb != (0x1 & (current_byte >> bit))) {
1148cee4d264SManish Chopra 				crc32_result = crc32_result ^ CRC32_POLY;
1149cee4d264SManish Chopra 				crc32_result |= 1; /*crc32_result[0] = 1;*/
1150cee4d264SManish Chopra 			}
1151cee4d264SManish Chopra 		}
1152cee4d264SManish Chopra 	}
1153cee4d264SManish Chopra 	return crc32_result;
1154cee4d264SManish Chopra }
1155cee4d264SManish Chopra 
1156cee4d264SManish Chopra static inline u32 qed_crc32c_le(u32 seed,
1157cee4d264SManish Chopra 				u8 *mac,
1158cee4d264SManish Chopra 				u32 len)
1159cee4d264SManish Chopra {
1160cee4d264SManish Chopra 	u32 packet_buf[2] = { 0 };
1161cee4d264SManish Chopra 
1162cee4d264SManish Chopra 	memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1163cee4d264SManish Chopra 	return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1164cee4d264SManish Chopra }
1165cee4d264SManish Chopra 
1166dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac)
1167cee4d264SManish Chopra {
1168cee4d264SManish Chopra 	u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1169cee4d264SManish Chopra 				mac, ETH_ALEN);
1170cee4d264SManish Chopra 
1171cee4d264SManish Chopra 	return crc & 0xff;
1172cee4d264SManish Chopra }
1173cee4d264SManish Chopra 
1174cee4d264SManish Chopra static int
1175cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1176cee4d264SManish Chopra 			u16 opaque_fid,
1177cee4d264SManish Chopra 			struct qed_filter_mcast *p_filter_cmd,
1178cee4d264SManish Chopra 			enum spq_mode comp_mode,
1179cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1180cee4d264SManish Chopra {
1181cee4d264SManish Chopra 	unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1182cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
1183cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
118406f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1185cee4d264SManish Chopra 	u8 abs_vport_id = 0;
1186cee4d264SManish Chopra 	int rc, i;
1187cee4d264SManish Chopra 
1188cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1189cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1190cee4d264SManish Chopra 				  &abs_vport_id);
1191cee4d264SManish Chopra 		if (rc)
1192cee4d264SManish Chopra 			return rc;
1193cee4d264SManish Chopra 	} else {
1194cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1195cee4d264SManish Chopra 				  &abs_vport_id);
1196cee4d264SManish Chopra 		if (rc)
1197cee4d264SManish Chopra 			return rc;
1198cee4d264SManish Chopra 	}
1199cee4d264SManish Chopra 
120006f56b81SYuval Mintz 	/* Get SPQ entry */
120106f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
120206f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
120306f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
120406f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
120506f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1206cee4d264SManish Chopra 
1207cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1208cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
120906f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1210cee4d264SManish Chopra 	if (rc) {
1211cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1212cee4d264SManish Chopra 		return rc;
1213cee4d264SManish Chopra 	}
1214cee4d264SManish Chopra 
1215cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
1216cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
1217cee4d264SManish Chopra 
1218cee4d264SManish Chopra 	/* explicitly clear out the entire vector */
1219cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
1220cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
1221cee4d264SManish Chopra 	memset(bins, 0, sizeof(unsigned long) *
1222cee4d264SManish Chopra 	       ETH_MULTICAST_MAC_BINS_IN_REGS);
1223cee4d264SManish Chopra 	/* filter ADD op is explicit set op and it removes
1224cee4d264SManish Chopra 	 *  any existing filters for the vport
1225cee4d264SManish Chopra 	 */
1226cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1227cee4d264SManish Chopra 		for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1228cee4d264SManish Chopra 			u32 bit;
1229cee4d264SManish Chopra 
1230cee4d264SManish Chopra 			bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1231cee4d264SManish Chopra 			__set_bit(bit, bins);
1232cee4d264SManish Chopra 		}
1233cee4d264SManish Chopra 
1234cee4d264SManish Chopra 		/* Convert to correct endianity */
1235cee4d264SManish Chopra 		for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1236cee4d264SManish Chopra 			u32 *p_bins = (u32 *)bins;
1237cee4d264SManish Chopra 			struct vport_update_ramrod_mcast *approx_mcast;
1238cee4d264SManish Chopra 
1239cee4d264SManish Chopra 			approx_mcast = &p_ramrod->approx_mcast;
1240cee4d264SManish Chopra 			approx_mcast->bins[i] = cpu_to_le32(p_bins[i]);
1241cee4d264SManish Chopra 		}
1242cee4d264SManish Chopra 	}
1243cee4d264SManish Chopra 
1244cee4d264SManish Chopra 	p_ramrod->common.vport_id = abs_vport_id;
1245cee4d264SManish Chopra 
1246cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1247cee4d264SManish Chopra }
1248cee4d264SManish Chopra 
1249dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1250cee4d264SManish Chopra 				struct qed_filter_mcast *p_filter_cmd,
1251cee4d264SManish Chopra 				enum spq_mode comp_mode,
1252cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1253cee4d264SManish Chopra {
1254cee4d264SManish Chopra 	int rc = 0;
1255cee4d264SManish Chopra 	int i;
1256cee4d264SManish Chopra 
1257cee4d264SManish Chopra 	/* only ADD and REMOVE operations are supported for multi-cast */
1258cee4d264SManish Chopra 	if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1259cee4d264SManish Chopra 	     (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1260cee4d264SManish Chopra 	    (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1261cee4d264SManish Chopra 		return -EINVAL;
1262cee4d264SManish Chopra 
1263cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1264cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1265cee4d264SManish Chopra 
1266cee4d264SManish Chopra 		u16 opaque_fid;
1267cee4d264SManish Chopra 
1268dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1269dacd88d6SYuval Mintz 			qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1270dacd88d6SYuval Mintz 			continue;
1271dacd88d6SYuval Mintz 		}
1272cee4d264SManish Chopra 
1273cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1274cee4d264SManish Chopra 
1275cee4d264SManish Chopra 		rc = qed_sp_eth_filter_mcast(p_hwfn,
1276cee4d264SManish Chopra 					     opaque_fid,
1277cee4d264SManish Chopra 					     p_filter_cmd,
1278cee4d264SManish Chopra 					     comp_mode,
1279cee4d264SManish Chopra 					     p_comp_data);
1280cee4d264SManish Chopra 	}
1281cee4d264SManish Chopra 	return rc;
1282cee4d264SManish Chopra }
1283cee4d264SManish Chopra 
1284cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1285cee4d264SManish Chopra 				struct qed_filter_ucast *p_filter_cmd,
1286cee4d264SManish Chopra 				enum spq_mode comp_mode,
1287cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1288cee4d264SManish Chopra {
1289cee4d264SManish Chopra 	int rc = 0;
1290cee4d264SManish Chopra 	int i;
1291cee4d264SManish Chopra 
1292cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1293cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1294cee4d264SManish Chopra 		u16 opaque_fid;
1295cee4d264SManish Chopra 
1296dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1297dacd88d6SYuval Mintz 			rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1298dacd88d6SYuval Mintz 			continue;
1299dacd88d6SYuval Mintz 		}
1300cee4d264SManish Chopra 
1301cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1302cee4d264SManish Chopra 
1303cee4d264SManish Chopra 		rc = qed_sp_eth_filter_ucast(p_hwfn,
1304cee4d264SManish Chopra 					     opaque_fid,
1305cee4d264SManish Chopra 					     p_filter_cmd,
1306cee4d264SManish Chopra 					     comp_mode,
1307cee4d264SManish Chopra 					     p_comp_data);
1308dacd88d6SYuval Mintz 		if (rc != 0)
1309dacd88d6SYuval Mintz 			break;
1310cee4d264SManish Chopra 	}
1311cee4d264SManish Chopra 
1312cee4d264SManish Chopra 	return rc;
1313cee4d264SManish Chopra }
1314cee4d264SManish Chopra 
131586622ee7SYuval Mintz /* Statistics related code */
131686622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
131786622ee7SYuval Mintz 					   u32 *p_addr,
1318dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
131986622ee7SYuval Mintz {
1320dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
132186622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_PSDM_RAM +
132286622ee7SYuval Mintz 		    PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
132386622ee7SYuval Mintz 		*p_len = sizeof(struct eth_pstorm_per_queue_stat);
1324dacd88d6SYuval Mintz 	} else {
1325dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1326dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1327dacd88d6SYuval Mintz 
1328dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1329dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.pstats.len;
1330dacd88d6SYuval Mintz 	}
133186622ee7SYuval Mintz }
133286622ee7SYuval Mintz 
133386622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
133486622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
133586622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
133686622ee7SYuval Mintz 				   u16 statistics_bin)
133786622ee7SYuval Mintz {
133886622ee7SYuval Mintz 	struct eth_pstorm_per_queue_stat pstats;
133986622ee7SYuval Mintz 	u32 pstats_addr = 0, pstats_len = 0;
134086622ee7SYuval Mintz 
134186622ee7SYuval Mintz 	__qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
134286622ee7SYuval Mintz 				       statistics_bin);
134386622ee7SYuval Mintz 
134486622ee7SYuval Mintz 	memset(&pstats, 0, sizeof(pstats));
1345dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
134686622ee7SYuval Mintz 
1347dacd88d6SYuval Mintz 	p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1348dacd88d6SYuval Mintz 	p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1349dacd88d6SYuval Mintz 	p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1350dacd88d6SYuval Mintz 	p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1351dacd88d6SYuval Mintz 	p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1352dacd88d6SYuval Mintz 	p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1353dacd88d6SYuval Mintz 	p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
135486622ee7SYuval Mintz }
135586622ee7SYuval Mintz 
135686622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
135786622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
135886622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
135986622ee7SYuval Mintz 				   u16 statistics_bin)
136086622ee7SYuval Mintz {
136186622ee7SYuval Mintz 	struct tstorm_per_port_stat tstats;
1362dacd88d6SYuval Mintz 	u32 tstats_addr, tstats_len;
136386622ee7SYuval Mintz 
1364dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
1365dacd88d6SYuval Mintz 		tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1366dacd88d6SYuval Mintz 		    TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1367dacd88d6SYuval Mintz 		tstats_len = sizeof(struct tstorm_per_port_stat);
1368dacd88d6SYuval Mintz 	} else {
1369dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1370dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1371dacd88d6SYuval Mintz 
1372dacd88d6SYuval Mintz 		tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1373dacd88d6SYuval Mintz 		tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1374dacd88d6SYuval Mintz 	}
137586622ee7SYuval Mintz 
137686622ee7SYuval Mintz 	memset(&tstats, 0, sizeof(tstats));
1377dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
137886622ee7SYuval Mintz 
137986622ee7SYuval Mintz 	p_stats->mftag_filter_discards +=
138086622ee7SYuval Mintz 		HILO_64_REGPAIR(tstats.mftag_filter_discard);
138186622ee7SYuval Mintz 	p_stats->mac_filter_discards +=
138286622ee7SYuval Mintz 		HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
138386622ee7SYuval Mintz }
138486622ee7SYuval Mintz 
138586622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
138686622ee7SYuval Mintz 					   u32 *p_addr,
1387dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
138886622ee7SYuval Mintz {
1389dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
139086622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_USDM_RAM +
139186622ee7SYuval Mintz 		    USTORM_QUEUE_STAT_OFFSET(statistics_bin);
139286622ee7SYuval Mintz 		*p_len = sizeof(struct eth_ustorm_per_queue_stat);
1393dacd88d6SYuval Mintz 	} else {
1394dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1395dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1396dacd88d6SYuval Mintz 
1397dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1398dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.ustats.len;
1399dacd88d6SYuval Mintz 	}
140086622ee7SYuval Mintz }
140186622ee7SYuval Mintz 
140286622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
140386622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
140486622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
140586622ee7SYuval Mintz 				   u16 statistics_bin)
140686622ee7SYuval Mintz {
140786622ee7SYuval Mintz 	struct eth_ustorm_per_queue_stat ustats;
140886622ee7SYuval Mintz 	u32 ustats_addr = 0, ustats_len = 0;
140986622ee7SYuval Mintz 
141086622ee7SYuval Mintz 	__qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
141186622ee7SYuval Mintz 				       statistics_bin);
141286622ee7SYuval Mintz 
141386622ee7SYuval Mintz 	memset(&ustats, 0, sizeof(ustats));
1414dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
141586622ee7SYuval Mintz 
1416dacd88d6SYuval Mintz 	p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1417dacd88d6SYuval Mintz 	p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1418dacd88d6SYuval Mintz 	p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1419dacd88d6SYuval Mintz 	p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1420dacd88d6SYuval Mintz 	p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1421dacd88d6SYuval Mintz 	p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
142286622ee7SYuval Mintz }
142386622ee7SYuval Mintz 
142486622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
142586622ee7SYuval Mintz 					   u32 *p_addr,
1426dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
142786622ee7SYuval Mintz {
1428dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
142986622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_MSDM_RAM +
143086622ee7SYuval Mintz 		    MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
143186622ee7SYuval Mintz 		*p_len = sizeof(struct eth_mstorm_per_queue_stat);
1432dacd88d6SYuval Mintz 	} else {
1433dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1434dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1435dacd88d6SYuval Mintz 
1436dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1437dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.mstats.len;
1438dacd88d6SYuval Mintz 	}
143986622ee7SYuval Mintz }
144086622ee7SYuval Mintz 
144186622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
144286622ee7SYuval Mintz 				   struct qed_ptt *p_ptt,
144386622ee7SYuval Mintz 				   struct qed_eth_stats *p_stats,
144486622ee7SYuval Mintz 				   u16 statistics_bin)
144586622ee7SYuval Mintz {
144686622ee7SYuval Mintz 	struct eth_mstorm_per_queue_stat mstats;
144786622ee7SYuval Mintz 	u32 mstats_addr = 0, mstats_len = 0;
144886622ee7SYuval Mintz 
144986622ee7SYuval Mintz 	__qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
145086622ee7SYuval Mintz 				       statistics_bin);
145186622ee7SYuval Mintz 
145286622ee7SYuval Mintz 	memset(&mstats, 0, sizeof(mstats));
1453dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
145486622ee7SYuval Mintz 
1455dacd88d6SYuval Mintz 	p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
145686622ee7SYuval Mintz 	p_stats->packet_too_big_discard +=
145786622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.packet_too_big_discard);
1458dacd88d6SYuval Mintz 	p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
145986622ee7SYuval Mintz 	p_stats->tpa_coalesced_pkts +=
146086622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
146186622ee7SYuval Mintz 	p_stats->tpa_coalesced_events +=
146286622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1463dacd88d6SYuval Mintz 	p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
146486622ee7SYuval Mintz 	p_stats->tpa_coalesced_bytes +=
146586622ee7SYuval Mintz 		HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
146686622ee7SYuval Mintz }
146786622ee7SYuval Mintz 
146886622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
146986622ee7SYuval Mintz 				       struct qed_ptt *p_ptt,
147086622ee7SYuval Mintz 				       struct qed_eth_stats *p_stats)
147186622ee7SYuval Mintz {
147286622ee7SYuval Mintz 	struct port_stats port_stats;
147386622ee7SYuval Mintz 	int j;
147486622ee7SYuval Mintz 
147586622ee7SYuval Mintz 	memset(&port_stats, 0, sizeof(port_stats));
147686622ee7SYuval Mintz 
147786622ee7SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
147886622ee7SYuval Mintz 			p_hwfn->mcp_info->port_addr +
147986622ee7SYuval Mintz 			offsetof(struct public_port, stats),
148086622ee7SYuval Mintz 			sizeof(port_stats));
148186622ee7SYuval Mintz 
148286622ee7SYuval Mintz 	p_stats->rx_64_byte_packets		+= port_stats.pmm.r64;
1483d4967cf3SYuval Mintz 	p_stats->rx_65_to_127_byte_packets	+= port_stats.pmm.r127;
1484d4967cf3SYuval Mintz 	p_stats->rx_128_to_255_byte_packets	+= port_stats.pmm.r255;
1485d4967cf3SYuval Mintz 	p_stats->rx_256_to_511_byte_packets	+= port_stats.pmm.r511;
1486d4967cf3SYuval Mintz 	p_stats->rx_512_to_1023_byte_packets	+= port_stats.pmm.r1023;
1487d4967cf3SYuval Mintz 	p_stats->rx_1024_to_1518_byte_packets	+= port_stats.pmm.r1518;
1488d4967cf3SYuval Mintz 	p_stats->rx_1519_to_1522_byte_packets	+= port_stats.pmm.r1522;
1489d4967cf3SYuval Mintz 	p_stats->rx_1519_to_2047_byte_packets	+= port_stats.pmm.r2047;
1490d4967cf3SYuval Mintz 	p_stats->rx_2048_to_4095_byte_packets	+= port_stats.pmm.r4095;
1491d4967cf3SYuval Mintz 	p_stats->rx_4096_to_9216_byte_packets	+= port_stats.pmm.r9216;
1492d4967cf3SYuval Mintz 	p_stats->rx_9217_to_16383_byte_packets	+= port_stats.pmm.r16383;
149386622ee7SYuval Mintz 	p_stats->rx_crc_errors			+= port_stats.pmm.rfcs;
149486622ee7SYuval Mintz 	p_stats->rx_mac_crtl_frames		+= port_stats.pmm.rxcf;
149586622ee7SYuval Mintz 	p_stats->rx_pause_frames		+= port_stats.pmm.rxpf;
149686622ee7SYuval Mintz 	p_stats->rx_pfc_frames			+= port_stats.pmm.rxpp;
149786622ee7SYuval Mintz 	p_stats->rx_align_errors		+= port_stats.pmm.raln;
149886622ee7SYuval Mintz 	p_stats->rx_carrier_errors		+= port_stats.pmm.rfcr;
149986622ee7SYuval Mintz 	p_stats->rx_oversize_packets		+= port_stats.pmm.rovr;
150086622ee7SYuval Mintz 	p_stats->rx_jabbers			+= port_stats.pmm.rjbr;
150186622ee7SYuval Mintz 	p_stats->rx_undersize_packets		+= port_stats.pmm.rund;
150286622ee7SYuval Mintz 	p_stats->rx_fragments			+= port_stats.pmm.rfrg;
150386622ee7SYuval Mintz 	p_stats->tx_64_byte_packets		+= port_stats.pmm.t64;
150486622ee7SYuval Mintz 	p_stats->tx_65_to_127_byte_packets	+= port_stats.pmm.t127;
150586622ee7SYuval Mintz 	p_stats->tx_128_to_255_byte_packets	+= port_stats.pmm.t255;
150686622ee7SYuval Mintz 	p_stats->tx_256_to_511_byte_packets	+= port_stats.pmm.t511;
150786622ee7SYuval Mintz 	p_stats->tx_512_to_1023_byte_packets	+= port_stats.pmm.t1023;
150886622ee7SYuval Mintz 	p_stats->tx_1024_to_1518_byte_packets	+= port_stats.pmm.t1518;
150986622ee7SYuval Mintz 	p_stats->tx_1519_to_2047_byte_packets	+= port_stats.pmm.t2047;
151086622ee7SYuval Mintz 	p_stats->tx_2048_to_4095_byte_packets	+= port_stats.pmm.t4095;
151186622ee7SYuval Mintz 	p_stats->tx_4096_to_9216_byte_packets	+= port_stats.pmm.t9216;
151286622ee7SYuval Mintz 	p_stats->tx_9217_to_16383_byte_packets	+= port_stats.pmm.t16383;
151386622ee7SYuval Mintz 	p_stats->tx_pause_frames		+= port_stats.pmm.txpf;
151486622ee7SYuval Mintz 	p_stats->tx_pfc_frames			+= port_stats.pmm.txpp;
151586622ee7SYuval Mintz 	p_stats->tx_lpi_entry_count		+= port_stats.pmm.tlpiec;
151686622ee7SYuval Mintz 	p_stats->tx_total_collisions		+= port_stats.pmm.tncl;
151786622ee7SYuval Mintz 	p_stats->rx_mac_bytes			+= port_stats.pmm.rbyte;
151886622ee7SYuval Mintz 	p_stats->rx_mac_uc_packets		+= port_stats.pmm.rxuca;
151986622ee7SYuval Mintz 	p_stats->rx_mac_mc_packets		+= port_stats.pmm.rxmca;
152086622ee7SYuval Mintz 	p_stats->rx_mac_bc_packets		+= port_stats.pmm.rxbca;
152186622ee7SYuval Mintz 	p_stats->rx_mac_frames_ok		+= port_stats.pmm.rxpok;
152286622ee7SYuval Mintz 	p_stats->tx_mac_bytes			+= port_stats.pmm.tbyte;
152386622ee7SYuval Mintz 	p_stats->tx_mac_uc_packets		+= port_stats.pmm.txuca;
152486622ee7SYuval Mintz 	p_stats->tx_mac_mc_packets		+= port_stats.pmm.txmca;
152586622ee7SYuval Mintz 	p_stats->tx_mac_bc_packets		+= port_stats.pmm.txbca;
152686622ee7SYuval Mintz 	p_stats->tx_mac_ctrl_frames		+= port_stats.pmm.txcf;
152786622ee7SYuval Mintz 	for (j = 0; j < 8; j++) {
152886622ee7SYuval Mintz 		p_stats->brb_truncates	+= port_stats.brb.brb_truncate[j];
152986622ee7SYuval Mintz 		p_stats->brb_discards	+= port_stats.brb.brb_discard[j];
153086622ee7SYuval Mintz 	}
153186622ee7SYuval Mintz }
153286622ee7SYuval Mintz 
153386622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
153486622ee7SYuval Mintz 				  struct qed_ptt *p_ptt,
153586622ee7SYuval Mintz 				  struct qed_eth_stats *stats,
1536dacd88d6SYuval Mintz 				  u16 statistics_bin, bool b_get_port_stats)
153786622ee7SYuval Mintz {
153886622ee7SYuval Mintz 	__qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
153986622ee7SYuval Mintz 	__qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
154086622ee7SYuval Mintz 	__qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
154186622ee7SYuval Mintz 	__qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
154286622ee7SYuval Mintz 
1543dacd88d6SYuval Mintz 	if (b_get_port_stats && p_hwfn->mcp_info)
154486622ee7SYuval Mintz 		__qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
154586622ee7SYuval Mintz }
154686622ee7SYuval Mintz 
154786622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev,
154886622ee7SYuval Mintz 				 struct qed_eth_stats *stats)
154986622ee7SYuval Mintz {
155086622ee7SYuval Mintz 	u8 fw_vport = 0;
155186622ee7SYuval Mintz 	int i;
155286622ee7SYuval Mintz 
155386622ee7SYuval Mintz 	memset(stats, 0, sizeof(*stats));
155486622ee7SYuval Mintz 
155586622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
155686622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1557dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1558dacd88d6SYuval Mintz 						    :  NULL;
155986622ee7SYuval Mintz 
1560dacd88d6SYuval Mintz 		if (IS_PF(cdev)) {
156186622ee7SYuval Mintz 			/* The main vport index is relative first */
156286622ee7SYuval Mintz 			if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
156386622ee7SYuval Mintz 				DP_ERR(p_hwfn, "No vport available!\n");
1564dacd88d6SYuval Mintz 				goto out;
1565dacd88d6SYuval Mintz 			}
156686622ee7SYuval Mintz 		}
156786622ee7SYuval Mintz 
1568dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
156986622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
157086622ee7SYuval Mintz 			continue;
157186622ee7SYuval Mintz 		}
157286622ee7SYuval Mintz 
1573dacd88d6SYuval Mintz 		__qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1574dacd88d6SYuval Mintz 				      IS_PF(cdev) ? true : false);
157586622ee7SYuval Mintz 
1576dacd88d6SYuval Mintz out:
1577dacd88d6SYuval Mintz 		if (IS_PF(cdev) && p_ptt)
157886622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
157986622ee7SYuval Mintz 	}
158086622ee7SYuval Mintz }
158186622ee7SYuval Mintz 
158286622ee7SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev,
158386622ee7SYuval Mintz 			 struct qed_eth_stats *stats)
158486622ee7SYuval Mintz {
158586622ee7SYuval Mintz 	u32 i;
158686622ee7SYuval Mintz 
158786622ee7SYuval Mintz 	if (!cdev) {
158886622ee7SYuval Mintz 		memset(stats, 0, sizeof(*stats));
158986622ee7SYuval Mintz 		return;
159086622ee7SYuval Mintz 	}
159186622ee7SYuval Mintz 
159286622ee7SYuval Mintz 	_qed_get_vport_stats(cdev, stats);
159386622ee7SYuval Mintz 
159486622ee7SYuval Mintz 	if (!cdev->reset_stats)
159586622ee7SYuval Mintz 		return;
159686622ee7SYuval Mintz 
159786622ee7SYuval Mintz 	/* Reduce the statistics baseline */
159886622ee7SYuval Mintz 	for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
159986622ee7SYuval Mintz 		((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
160086622ee7SYuval Mintz }
160186622ee7SYuval Mintz 
160286622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
160386622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev)
160486622ee7SYuval Mintz {
160586622ee7SYuval Mintz 	int i;
160686622ee7SYuval Mintz 
160786622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
160886622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
160986622ee7SYuval Mintz 		struct eth_mstorm_per_queue_stat mstats;
161086622ee7SYuval Mintz 		struct eth_ustorm_per_queue_stat ustats;
161186622ee7SYuval Mintz 		struct eth_pstorm_per_queue_stat pstats;
1612dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1613dacd88d6SYuval Mintz 						    : NULL;
161486622ee7SYuval Mintz 		u32 addr = 0, len = 0;
161586622ee7SYuval Mintz 
1616dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
161786622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
161886622ee7SYuval Mintz 			continue;
161986622ee7SYuval Mintz 		}
162086622ee7SYuval Mintz 
162186622ee7SYuval Mintz 		memset(&mstats, 0, sizeof(mstats));
162286622ee7SYuval Mintz 		__qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
162386622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
162486622ee7SYuval Mintz 
162586622ee7SYuval Mintz 		memset(&ustats, 0, sizeof(ustats));
162686622ee7SYuval Mintz 		__qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
162786622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
162886622ee7SYuval Mintz 
162986622ee7SYuval Mintz 		memset(&pstats, 0, sizeof(pstats));
163086622ee7SYuval Mintz 		__qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
163186622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
163286622ee7SYuval Mintz 
1633dacd88d6SYuval Mintz 		if (IS_PF(cdev))
163486622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
163586622ee7SYuval Mintz 	}
163686622ee7SYuval Mintz 
163786622ee7SYuval Mintz 	/* PORT statistics are not necessarily reset, so we need to
163886622ee7SYuval Mintz 	 * read and create a baseline for future statistics.
163986622ee7SYuval Mintz 	 */
164086622ee7SYuval Mintz 	if (!cdev->reset_stats)
164186622ee7SYuval Mintz 		DP_INFO(cdev, "Reset stats not allocated\n");
164286622ee7SYuval Mintz 	else
164386622ee7SYuval Mintz 		_qed_get_vport_stats(cdev, cdev->reset_stats);
164486622ee7SYuval Mintz }
164586622ee7SYuval Mintz 
164625c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev,
164725c089d7SYuval Mintz 				 struct qed_dev_eth_info *info)
164825c089d7SYuval Mintz {
164925c089d7SYuval Mintz 	int i;
165025c089d7SYuval Mintz 
165125c089d7SYuval Mintz 	memset(info, 0, sizeof(*info));
165225c089d7SYuval Mintz 
165325c089d7SYuval Mintz 	info->num_tc = 1;
165425c089d7SYuval Mintz 
16551408cc1fSYuval Mintz 	if (IS_PF(cdev)) {
165625c089d7SYuval Mintz 		if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
165725c089d7SYuval Mintz 			for_each_hwfn(cdev, i)
16581408cc1fSYuval Mintz 			    info->num_queues +=
16591408cc1fSYuval Mintz 			    FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
166025c089d7SYuval Mintz 			if (cdev->int_params.fp_msix_cnt)
16611408cc1fSYuval Mintz 				info->num_queues =
16621408cc1fSYuval Mintz 				    min_t(u8, info->num_queues,
166325c089d7SYuval Mintz 					  cdev->int_params.fp_msix_cnt);
166425c089d7SYuval Mintz 		} else {
166525c089d7SYuval Mintz 			info->num_queues = cdev->num_hwfns;
166625c089d7SYuval Mintz 		}
166725c089d7SYuval Mintz 
166825c089d7SYuval Mintz 		info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN);
166925c089d7SYuval Mintz 		ether_addr_copy(info->port_mac,
167025c089d7SYuval Mintz 				cdev->hwfns[0].hw_info.hw_mac_addr);
16711408cc1fSYuval Mintz 	} else {
16721408cc1fSYuval Mintz 		qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
16731408cc1fSYuval Mintz 		if (cdev->num_hwfns > 1) {
16741408cc1fSYuval Mintz 			u8 queues = 0;
16751408cc1fSYuval Mintz 
16761408cc1fSYuval Mintz 			qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
16771408cc1fSYuval Mintz 			info->num_queues += queues;
16781408cc1fSYuval Mintz 		}
16791408cc1fSYuval Mintz 
16801408cc1fSYuval Mintz 		qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
16811408cc1fSYuval Mintz 					    &info->num_vlan_filters);
16821408cc1fSYuval Mintz 		qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
16831408cc1fSYuval Mintz 	}
168425c089d7SYuval Mintz 
168525c089d7SYuval Mintz 	qed_fill_dev_info(cdev, &info->common);
168625c089d7SYuval Mintz 
16871408cc1fSYuval Mintz 	if (IS_VF(cdev))
16881408cc1fSYuval Mintz 		memset(info->common.hw_mac, 0, ETH_ALEN);
16891408cc1fSYuval Mintz 
169025c089d7SYuval Mintz 	return 0;
169125c089d7SYuval Mintz }
169225c089d7SYuval Mintz 
1693cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev,
16941408cc1fSYuval Mintz 				 struct qed_eth_cb_ops *ops, void *cookie)
1695cc875c2eSYuval Mintz {
1696cc875c2eSYuval Mintz 	cdev->protocol_ops.eth = ops;
1697cc875c2eSYuval Mintz 	cdev->ops_cookie = cookie;
16981408cc1fSYuval Mintz 
16991408cc1fSYuval Mintz 	/* For VF, we start bulletin reading */
17001408cc1fSYuval Mintz 	if (IS_VF(cdev))
17011408cc1fSYuval Mintz 		qed_vf_start_iov_wq(cdev);
1702cc875c2eSYuval Mintz }
1703cc875c2eSYuval Mintz 
1704cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev,
1705088c8618SManish Chopra 			   struct qed_start_vport_params *params)
1706cee4d264SManish Chopra {
1707cee4d264SManish Chopra 	int rc, i;
1708cee4d264SManish Chopra 
1709cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1710088c8618SManish Chopra 		struct qed_sp_vport_start_params start = { 0 };
1711cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1712cee4d264SManish Chopra 
1713088c8618SManish Chopra 		start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1714088c8618SManish Chopra 							QED_TPA_MODE_NONE;
1715088c8618SManish Chopra 		start.remove_inner_vlan = params->remove_inner_vlan;
171608feecd7SYuval Mintz 		start.only_untagged = true;	/* untagged only */
1717088c8618SManish Chopra 		start.drop_ttl0 = params->drop_ttl0;
1718088c8618SManish Chopra 		start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1719088c8618SManish Chopra 		start.concrete_fid = p_hwfn->hw_info.concrete_fid;
1720088c8618SManish Chopra 		start.vport_id = params->vport_id;
1721088c8618SManish Chopra 		start.max_buffers_per_cqe = 16;
1722088c8618SManish Chopra 		start.mtu = params->mtu;
1723cee4d264SManish Chopra 
1724088c8618SManish Chopra 		rc = qed_sp_vport_start(p_hwfn, &start);
1725cee4d264SManish Chopra 		if (rc) {
1726cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to start VPORT\n");
1727cee4d264SManish Chopra 			return rc;
1728cee4d264SManish Chopra 		}
1729cee4d264SManish Chopra 
1730cee4d264SManish Chopra 		qed_hw_start_fastpath(p_hwfn);
1731cee4d264SManish Chopra 
1732cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1733cee4d264SManish Chopra 			   "Started V-PORT %d with MTU %d\n",
1734088c8618SManish Chopra 			   start.vport_id, start.mtu);
1735cee4d264SManish Chopra 	}
1736cee4d264SManish Chopra 
17379df2ed04SManish Chopra 	qed_reset_vport_stats(cdev);
17389df2ed04SManish Chopra 
1739cee4d264SManish Chopra 	return 0;
1740cee4d264SManish Chopra }
1741cee4d264SManish Chopra 
1742cee4d264SManish Chopra static int qed_stop_vport(struct qed_dev *cdev,
1743cee4d264SManish Chopra 			  u8 vport_id)
1744cee4d264SManish Chopra {
1745cee4d264SManish Chopra 	int rc, i;
1746cee4d264SManish Chopra 
1747cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1748cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1749cee4d264SManish Chopra 
1750cee4d264SManish Chopra 		rc = qed_sp_vport_stop(p_hwfn,
1751cee4d264SManish Chopra 				       p_hwfn->hw_info.opaque_fid,
1752cee4d264SManish Chopra 				       vport_id);
1753cee4d264SManish Chopra 
1754cee4d264SManish Chopra 		if (rc) {
1755cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to stop VPORT\n");
1756cee4d264SManish Chopra 			return rc;
1757cee4d264SManish Chopra 		}
1758cee4d264SManish Chopra 	}
1759cee4d264SManish Chopra 	return 0;
1760cee4d264SManish Chopra }
1761cee4d264SManish Chopra 
1762cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev,
1763cee4d264SManish Chopra 			    struct qed_update_vport_params *params)
1764cee4d264SManish Chopra {
1765cee4d264SManish Chopra 	struct qed_sp_vport_update_params sp_params;
1766cee4d264SManish Chopra 	struct qed_rss_params sp_rss_params;
1767cee4d264SManish Chopra 	int rc, i;
1768cee4d264SManish Chopra 
1769cee4d264SManish Chopra 	if (!cdev)
1770cee4d264SManish Chopra 		return -ENODEV;
1771cee4d264SManish Chopra 
1772cee4d264SManish Chopra 	memset(&sp_params, 0, sizeof(sp_params));
1773cee4d264SManish Chopra 	memset(&sp_rss_params, 0, sizeof(sp_rss_params));
1774cee4d264SManish Chopra 
1775cee4d264SManish Chopra 	/* Translate protocol params into sp params */
1776cee4d264SManish Chopra 	sp_params.vport_id = params->vport_id;
1777cee4d264SManish Chopra 	sp_params.update_vport_active_rx_flg =
1778cee4d264SManish Chopra 		params->update_vport_active_flg;
1779cee4d264SManish Chopra 	sp_params.update_vport_active_tx_flg =
1780cee4d264SManish Chopra 		params->update_vport_active_flg;
1781cee4d264SManish Chopra 	sp_params.vport_active_rx_flg = params->vport_active_flg;
1782cee4d264SManish Chopra 	sp_params.vport_active_tx_flg = params->vport_active_flg;
17833f9b4a69SYuval Mintz 	sp_params.accept_any_vlan = params->accept_any_vlan;
17843f9b4a69SYuval Mintz 	sp_params.update_accept_any_vlan_flg =
17853f9b4a69SYuval Mintz 		params->update_accept_any_vlan_flg;
1786cee4d264SManish Chopra 
1787cee4d264SManish Chopra 	/* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
1788cee4d264SManish Chopra 	 * We need to re-fix the rss values per engine for CMT.
1789cee4d264SManish Chopra 	 */
1790cee4d264SManish Chopra 	if (cdev->num_hwfns > 1 && params->update_rss_flg) {
1791cee4d264SManish Chopra 		struct qed_update_vport_rss_params *rss =
1792cee4d264SManish Chopra 			&params->rss_params;
1793cee4d264SManish Chopra 		int k, max = 0;
1794cee4d264SManish Chopra 
1795cee4d264SManish Chopra 		/* Find largest entry, since it's possible RSS needs to
1796cee4d264SManish Chopra 		 * be disabled [in case only 1 queue per-hwfn]
1797cee4d264SManish Chopra 		 */
1798cee4d264SManish Chopra 		for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1799cee4d264SManish Chopra 			max = (max > rss->rss_ind_table[k]) ?
1800cee4d264SManish Chopra 				max : rss->rss_ind_table[k];
1801cee4d264SManish Chopra 
1802cee4d264SManish Chopra 		/* Either fix RSS values or disable RSS */
1803cee4d264SManish Chopra 		if (cdev->num_hwfns < max + 1) {
1804cee4d264SManish Chopra 			int divisor = (max + cdev->num_hwfns - 1) /
1805cee4d264SManish Chopra 				cdev->num_hwfns;
1806cee4d264SManish Chopra 
1807cee4d264SManish Chopra 			DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1808cee4d264SManish Chopra 				   "CMT - fixing RSS values (modulo %02x)\n",
1809cee4d264SManish Chopra 				   divisor);
1810cee4d264SManish Chopra 
1811cee4d264SManish Chopra 			for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1812cee4d264SManish Chopra 				rss->rss_ind_table[k] =
1813cee4d264SManish Chopra 					rss->rss_ind_table[k] % divisor;
1814cee4d264SManish Chopra 		} else {
1815cee4d264SManish Chopra 			DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1816cee4d264SManish Chopra 				   "CMT - 1 queue per-hwfn; Disabling RSS\n");
1817cee4d264SManish Chopra 			params->update_rss_flg = 0;
1818cee4d264SManish Chopra 		}
1819cee4d264SManish Chopra 	}
1820cee4d264SManish Chopra 
1821cee4d264SManish Chopra 	/* Now, update the RSS configuration for actual configuration */
1822cee4d264SManish Chopra 	if (params->update_rss_flg) {
1823cee4d264SManish Chopra 		sp_rss_params.update_rss_config = 1;
1824cee4d264SManish Chopra 		sp_rss_params.rss_enable = 1;
1825cee4d264SManish Chopra 		sp_rss_params.update_rss_capabilities = 1;
1826cee4d264SManish Chopra 		sp_rss_params.update_rss_ind_table = 1;
1827cee4d264SManish Chopra 		sp_rss_params.update_rss_key = 1;
18288c5ebd0cSSudarsana Reddy Kalluru 		sp_rss_params.rss_caps = params->rss_params.rss_caps;
1829cee4d264SManish Chopra 		sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
1830cee4d264SManish Chopra 		memcpy(sp_rss_params.rss_ind_table,
1831cee4d264SManish Chopra 		       params->rss_params.rss_ind_table,
1832cee4d264SManish Chopra 		       QED_RSS_IND_TABLE_SIZE * sizeof(u16));
1833cee4d264SManish Chopra 		memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
1834cee4d264SManish Chopra 		       QED_RSS_KEY_SIZE * sizeof(u32));
1835cee4d264SManish Chopra 	}
1836cee4d264SManish Chopra 	sp_params.rss_params = &sp_rss_params;
1837cee4d264SManish Chopra 
1838cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1839cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1840cee4d264SManish Chopra 
1841cee4d264SManish Chopra 		sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1842cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &sp_params,
1843cee4d264SManish Chopra 					 QED_SPQ_MODE_EBLOCK,
1844cee4d264SManish Chopra 					 NULL);
1845cee4d264SManish Chopra 		if (rc) {
1846cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to update VPORT\n");
1847cee4d264SManish Chopra 			return rc;
1848cee4d264SManish Chopra 		}
1849cee4d264SManish Chopra 
1850cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1851cee4d264SManish Chopra 			   "Updated V-PORT %d: active_flag %d [update %d]\n",
1852cee4d264SManish Chopra 			   params->vport_id, params->vport_active_flg,
1853cee4d264SManish Chopra 			   params->update_vport_active_flg);
1854cee4d264SManish Chopra 	}
1855cee4d264SManish Chopra 
1856cee4d264SManish Chopra 	return 0;
1857cee4d264SManish Chopra }
1858cee4d264SManish Chopra 
1859cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev,
1860cee4d264SManish Chopra 			 struct qed_queue_start_common_params *params,
1861cee4d264SManish Chopra 			 u16 bd_max_bytes,
1862cee4d264SManish Chopra 			 dma_addr_t bd_chain_phys_addr,
1863cee4d264SManish Chopra 			 dma_addr_t cqe_pbl_addr,
1864cee4d264SManish Chopra 			 u16 cqe_pbl_size,
1865cee4d264SManish Chopra 			 void __iomem **pp_prod)
1866cee4d264SManish Chopra {
1867cee4d264SManish Chopra 	int rc, hwfn_index;
1868cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
1869cee4d264SManish Chopra 
1870cee4d264SManish Chopra 	hwfn_index = params->rss_id % cdev->num_hwfns;
1871cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
1872cee4d264SManish Chopra 
1873cee4d264SManish Chopra 	/* Fix queue ID in 100g mode */
1874cee4d264SManish Chopra 	params->queue_id /= cdev->num_hwfns;
1875cee4d264SManish Chopra 
1876cee4d264SManish Chopra 	rc = qed_sp_eth_rx_queue_start(p_hwfn,
1877cee4d264SManish Chopra 				       p_hwfn->hw_info.opaque_fid,
1878cee4d264SManish Chopra 				       params,
1879cee4d264SManish Chopra 				       bd_max_bytes,
1880cee4d264SManish Chopra 				       bd_chain_phys_addr,
1881cee4d264SManish Chopra 				       cqe_pbl_addr,
1882cee4d264SManish Chopra 				       cqe_pbl_size,
1883cee4d264SManish Chopra 				       pp_prod);
1884cee4d264SManish Chopra 
1885cee4d264SManish Chopra 	if (rc) {
1886cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
1887cee4d264SManish Chopra 		return rc;
1888cee4d264SManish Chopra 	}
1889cee4d264SManish Chopra 
1890cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1891cee4d264SManish Chopra 		   "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1892cee4d264SManish Chopra 		   params->queue_id, params->rss_id, params->vport_id,
1893cee4d264SManish Chopra 		   params->sb);
1894cee4d264SManish Chopra 
1895cee4d264SManish Chopra 	return 0;
1896cee4d264SManish Chopra }
1897cee4d264SManish Chopra 
1898cee4d264SManish Chopra static int qed_stop_rxq(struct qed_dev *cdev,
1899cee4d264SManish Chopra 			struct qed_stop_rxq_params *params)
1900cee4d264SManish Chopra {
1901cee4d264SManish Chopra 	int rc, hwfn_index;
1902cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
1903cee4d264SManish Chopra 
1904cee4d264SManish Chopra 	hwfn_index	= params->rss_id % cdev->num_hwfns;
1905cee4d264SManish Chopra 	p_hwfn		= &cdev->hwfns[hwfn_index];
1906cee4d264SManish Chopra 
1907cee4d264SManish Chopra 	rc = qed_sp_eth_rx_queue_stop(p_hwfn,
1908cee4d264SManish Chopra 				      params->rx_queue_id / cdev->num_hwfns,
1909cee4d264SManish Chopra 				      params->eq_completion_only,
1910cee4d264SManish Chopra 				      false);
1911cee4d264SManish Chopra 	if (rc) {
1912cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
1913cee4d264SManish Chopra 		return rc;
1914cee4d264SManish Chopra 	}
1915cee4d264SManish Chopra 
1916cee4d264SManish Chopra 	return 0;
1917cee4d264SManish Chopra }
1918cee4d264SManish Chopra 
1919cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev,
1920cee4d264SManish Chopra 			 struct qed_queue_start_common_params *p_params,
1921cee4d264SManish Chopra 			 dma_addr_t pbl_addr,
1922cee4d264SManish Chopra 			 u16 pbl_size,
1923cee4d264SManish Chopra 			 void __iomem **pp_doorbell)
1924cee4d264SManish Chopra {
1925cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
1926cee4d264SManish Chopra 	int rc, hwfn_index;
1927cee4d264SManish Chopra 
1928cee4d264SManish Chopra 	hwfn_index	= p_params->rss_id % cdev->num_hwfns;
1929cee4d264SManish Chopra 	p_hwfn		= &cdev->hwfns[hwfn_index];
1930cee4d264SManish Chopra 
1931cee4d264SManish Chopra 	/* Fix queue ID in 100g mode */
1932cee4d264SManish Chopra 	p_params->queue_id /= cdev->num_hwfns;
1933cee4d264SManish Chopra 
1934cee4d264SManish Chopra 	rc = qed_sp_eth_tx_queue_start(p_hwfn,
1935cee4d264SManish Chopra 				       p_hwfn->hw_info.opaque_fid,
1936cee4d264SManish Chopra 				       p_params,
1937cee4d264SManish Chopra 				       pbl_addr,
1938cee4d264SManish Chopra 				       pbl_size,
1939cee4d264SManish Chopra 				       pp_doorbell);
1940cee4d264SManish Chopra 
1941cee4d264SManish Chopra 	if (rc) {
1942cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
1943cee4d264SManish Chopra 		return rc;
1944cee4d264SManish Chopra 	}
1945cee4d264SManish Chopra 
1946cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1947cee4d264SManish Chopra 		   "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1948cee4d264SManish Chopra 		   p_params->queue_id, p_params->rss_id, p_params->vport_id,
1949cee4d264SManish Chopra 		   p_params->sb);
1950cee4d264SManish Chopra 
1951cee4d264SManish Chopra 	return 0;
1952cee4d264SManish Chopra }
1953cee4d264SManish Chopra 
1954cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10)
1955cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev)
1956cee4d264SManish Chopra {
1957cee4d264SManish Chopra 	qed_hw_stop_fastpath(cdev);
1958cee4d264SManish Chopra 
1959cee4d264SManish Chopra 	return 0;
1960cee4d264SManish Chopra }
1961cee4d264SManish Chopra 
1962cee4d264SManish Chopra static int qed_stop_txq(struct qed_dev *cdev,
1963cee4d264SManish Chopra 			struct qed_stop_txq_params *params)
1964cee4d264SManish Chopra {
1965cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
1966cee4d264SManish Chopra 	int rc, hwfn_index;
1967cee4d264SManish Chopra 
1968cee4d264SManish Chopra 	hwfn_index	= params->rss_id % cdev->num_hwfns;
1969cee4d264SManish Chopra 	p_hwfn		= &cdev->hwfns[hwfn_index];
1970cee4d264SManish Chopra 
1971cee4d264SManish Chopra 	rc = qed_sp_eth_tx_queue_stop(p_hwfn,
1972cee4d264SManish Chopra 				      params->tx_queue_id / cdev->num_hwfns);
1973cee4d264SManish Chopra 	if (rc) {
1974cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
1975cee4d264SManish Chopra 		return rc;
1976cee4d264SManish Chopra 	}
1977cee4d264SManish Chopra 
1978cee4d264SManish Chopra 	return 0;
1979cee4d264SManish Chopra }
1980cee4d264SManish Chopra 
1981464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev,
1982464f6645SManish Chopra 			      struct qed_tunn_params *tunn_params)
1983464f6645SManish Chopra {
1984464f6645SManish Chopra 	struct qed_tunn_update_params tunn_info;
1985464f6645SManish Chopra 	int i, rc;
1986464f6645SManish Chopra 
19871408cc1fSYuval Mintz 	if (IS_VF(cdev))
19881408cc1fSYuval Mintz 		return 0;
19891408cc1fSYuval Mintz 
1990464f6645SManish Chopra 	memset(&tunn_info, 0, sizeof(tunn_info));
1991464f6645SManish Chopra 	if (tunn_params->update_vxlan_port == 1) {
1992464f6645SManish Chopra 		tunn_info.update_vxlan_udp_port = 1;
1993464f6645SManish Chopra 		tunn_info.vxlan_udp_port = tunn_params->vxlan_port;
1994464f6645SManish Chopra 	}
1995464f6645SManish Chopra 
1996464f6645SManish Chopra 	if (tunn_params->update_geneve_port == 1) {
1997464f6645SManish Chopra 		tunn_info.update_geneve_udp_port = 1;
1998464f6645SManish Chopra 		tunn_info.geneve_udp_port = tunn_params->geneve_port;
1999464f6645SManish Chopra 	}
2000464f6645SManish Chopra 
2001464f6645SManish Chopra 	for_each_hwfn(cdev, i) {
2002464f6645SManish Chopra 		struct qed_hwfn *hwfn = &cdev->hwfns[i];
2003464f6645SManish Chopra 
2004464f6645SManish Chopra 		rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
2005464f6645SManish Chopra 					       QED_SPQ_MODE_EBLOCK, NULL);
2006464f6645SManish Chopra 
2007464f6645SManish Chopra 		if (rc)
2008464f6645SManish Chopra 			return rc;
2009464f6645SManish Chopra 	}
2010464f6645SManish Chopra 
2011464f6645SManish Chopra 	return 0;
2012464f6645SManish Chopra }
2013464f6645SManish Chopra 
2014cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2015cee4d264SManish Chopra 					enum qed_filter_rx_mode_type type)
2016cee4d264SManish Chopra {
2017cee4d264SManish Chopra 	struct qed_filter_accept_flags accept_flags;
2018cee4d264SManish Chopra 
2019cee4d264SManish Chopra 	memset(&accept_flags, 0, sizeof(accept_flags));
2020cee4d264SManish Chopra 
2021cee4d264SManish Chopra 	accept_flags.update_rx_mode_config	= 1;
2022cee4d264SManish Chopra 	accept_flags.update_tx_mode_config	= 1;
2023cee4d264SManish Chopra 	accept_flags.rx_accept_filter		= QED_ACCEPT_UCAST_MATCHED |
2024cee4d264SManish Chopra 						  QED_ACCEPT_MCAST_MATCHED |
2025cee4d264SManish Chopra 						  QED_ACCEPT_BCAST;
2026cee4d264SManish Chopra 	accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2027cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2028cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2029cee4d264SManish Chopra 
2030cee4d264SManish Chopra 	if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
2031cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2032cee4d264SManish Chopra 						 QED_ACCEPT_MCAST_UNMATCHED;
2033cee4d264SManish Chopra 	else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
2034cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2035cee4d264SManish Chopra 
20363f9b4a69SYuval Mintz 	return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
2037cee4d264SManish Chopra 				     QED_SPQ_MODE_CB, NULL);
2038cee4d264SManish Chopra }
2039cee4d264SManish Chopra 
2040cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev,
2041cee4d264SManish Chopra 				      struct qed_filter_ucast_params *params)
2042cee4d264SManish Chopra {
2043cee4d264SManish Chopra 	struct qed_filter_ucast ucast;
2044cee4d264SManish Chopra 
2045cee4d264SManish Chopra 	if (!params->vlan_valid && !params->mac_valid) {
2046cee4d264SManish Chopra 		DP_NOTICE(
2047cee4d264SManish Chopra 			cdev,
2048cee4d264SManish Chopra 			"Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
2049cee4d264SManish Chopra 		return -EINVAL;
2050cee4d264SManish Chopra 	}
2051cee4d264SManish Chopra 
2052cee4d264SManish Chopra 	memset(&ucast, 0, sizeof(ucast));
2053cee4d264SManish Chopra 	switch (params->type) {
2054cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2055cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_ADD;
2056cee4d264SManish Chopra 		break;
2057cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2058cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REMOVE;
2059cee4d264SManish Chopra 		break;
2060cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_REPLACE:
2061cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REPLACE;
2062cee4d264SManish Chopra 		break;
2063cee4d264SManish Chopra 	default:
2064cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2065cee4d264SManish Chopra 			  params->type);
2066cee4d264SManish Chopra 	}
2067cee4d264SManish Chopra 
2068cee4d264SManish Chopra 	if (params->vlan_valid && params->mac_valid) {
2069cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC_VLAN;
2070cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2071cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2072cee4d264SManish Chopra 	} else if (params->mac_valid) {
2073cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC;
2074cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2075cee4d264SManish Chopra 	} else {
2076cee4d264SManish Chopra 		ucast.type = QED_FILTER_VLAN;
2077cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2078cee4d264SManish Chopra 	}
2079cee4d264SManish Chopra 
2080cee4d264SManish Chopra 	ucast.is_rx_filter = true;
2081cee4d264SManish Chopra 	ucast.is_tx_filter = true;
2082cee4d264SManish Chopra 
2083cee4d264SManish Chopra 	return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2084cee4d264SManish Chopra }
2085cee4d264SManish Chopra 
2086cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev,
2087cee4d264SManish Chopra 				      struct qed_filter_mcast_params *params)
2088cee4d264SManish Chopra {
2089cee4d264SManish Chopra 	struct qed_filter_mcast mcast;
2090cee4d264SManish Chopra 	int i;
2091cee4d264SManish Chopra 
2092cee4d264SManish Chopra 	memset(&mcast, 0, sizeof(mcast));
2093cee4d264SManish Chopra 	switch (params->type) {
2094cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2095cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_ADD;
2096cee4d264SManish Chopra 		break;
2097cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2098cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_REMOVE;
2099cee4d264SManish Chopra 		break;
2100cee4d264SManish Chopra 	default:
2101cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2102cee4d264SManish Chopra 			  params->type);
2103cee4d264SManish Chopra 	}
2104cee4d264SManish Chopra 
2105cee4d264SManish Chopra 	mcast.num_mc_addrs = params->num;
2106cee4d264SManish Chopra 	for (i = 0; i < mcast.num_mc_addrs; i++)
2107cee4d264SManish Chopra 		ether_addr_copy(mcast.mac[i], params->mac[i]);
2108cee4d264SManish Chopra 
2109cee4d264SManish Chopra 	return qed_filter_mcast_cmd(cdev, &mcast,
2110cee4d264SManish Chopra 				    QED_SPQ_MODE_CB, NULL);
2111cee4d264SManish Chopra }
2112cee4d264SManish Chopra 
2113cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev,
2114cee4d264SManish Chopra 				struct qed_filter_params *params)
2115cee4d264SManish Chopra {
2116cee4d264SManish Chopra 	enum qed_filter_rx_mode_type accept_flags;
2117cee4d264SManish Chopra 
2118cee4d264SManish Chopra 	switch (params->type) {
2119cee4d264SManish Chopra 	case QED_FILTER_TYPE_UCAST:
2120cee4d264SManish Chopra 		return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2121cee4d264SManish Chopra 	case QED_FILTER_TYPE_MCAST:
2122cee4d264SManish Chopra 		return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2123cee4d264SManish Chopra 	case QED_FILTER_TYPE_RX_MODE:
2124cee4d264SManish Chopra 		accept_flags = params->filter.accept_flags;
2125cee4d264SManish Chopra 		return qed_configure_filter_rx_mode(cdev, accept_flags);
2126cee4d264SManish Chopra 	default:
2127cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown filter type %d\n",
2128cee4d264SManish Chopra 			  (int)params->type);
2129cee4d264SManish Chopra 		return -EINVAL;
2130cee4d264SManish Chopra 	}
2131cee4d264SManish Chopra }
2132cee4d264SManish Chopra 
2133cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev,
2134cee4d264SManish Chopra 				 u8 rss_id,
2135cee4d264SManish Chopra 				 struct eth_slow_path_rx_cqe *cqe)
2136cee4d264SManish Chopra {
2137cee4d264SManish Chopra 	return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2138cee4d264SManish Chopra 				      cqe);
2139cee4d264SManish Chopra }
2140cee4d264SManish Chopra 
21410b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
21420b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass;
21430b55e27dSYuval Mintz #endif
21440b55e27dSYuval Mintz 
214525c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = {
214625c089d7SYuval Mintz 	.common = &qed_common_ops_pass,
21470b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
21480b55e27dSYuval Mintz 	.iov = &qed_iov_ops_pass,
21490b55e27dSYuval Mintz #endif
215025c089d7SYuval Mintz 	.fill_dev_info = &qed_fill_eth_dev_info,
2151cc875c2eSYuval Mintz 	.register_ops = &qed_register_eth_ops,
2152cee4d264SManish Chopra 	.vport_start = &qed_start_vport,
2153cee4d264SManish Chopra 	.vport_stop = &qed_stop_vport,
2154cee4d264SManish Chopra 	.vport_update = &qed_update_vport,
2155cee4d264SManish Chopra 	.q_rx_start = &qed_start_rxq,
2156cee4d264SManish Chopra 	.q_rx_stop = &qed_stop_rxq,
2157cee4d264SManish Chopra 	.q_tx_start = &qed_start_txq,
2158cee4d264SManish Chopra 	.q_tx_stop = &qed_stop_txq,
2159cee4d264SManish Chopra 	.filter_config = &qed_configure_filter,
2160cee4d264SManish Chopra 	.fastpath_stop = &qed_fastpath_stop,
2161cee4d264SManish Chopra 	.eth_cqe_completion = &qed_fp_cqe_completion,
21629df2ed04SManish Chopra 	.get_vport_stats = &qed_get_vport_stats,
2163464f6645SManish Chopra 	.tunn_config = &qed_tunn_configure,
216425c089d7SYuval Mintz };
216525c089d7SYuval Mintz 
216695114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void)
216725c089d7SYuval Mintz {
216825c089d7SYuval Mintz 	return &qed_eth_ops_pass;
216925c089d7SYuval Mintz }
217025c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops);
217125c089d7SYuval Mintz 
217225c089d7SYuval Mintz void qed_put_eth_ops(void)
217325c089d7SYuval Mintz {
217425c089d7SYuval Mintz 	/* TODO - reference count for module? */
217525c089d7SYuval Mintz }
217625c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops);
2177