125c089d7SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 325c089d7SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 3125c089d7SYuval Mintz */ 3225c089d7SYuval Mintz 3325c089d7SYuval Mintz #include <linux/types.h> 3425c089d7SYuval Mintz #include <asm/byteorder.h> 3525c089d7SYuval Mintz #include <asm/param.h> 3625c089d7SYuval Mintz #include <linux/delay.h> 3725c089d7SYuval Mintz #include <linux/dma-mapping.h> 3825c089d7SYuval Mintz #include <linux/etherdevice.h> 3925c089d7SYuval Mintz #include <linux/interrupt.h> 4025c089d7SYuval Mintz #include <linux/kernel.h> 4125c089d7SYuval Mintz #include <linux/module.h> 4225c089d7SYuval Mintz #include <linux/pci.h> 4325c089d7SYuval Mintz #include <linux/slab.h> 4425c089d7SYuval Mintz #include <linux/stddef.h> 4525c089d7SYuval Mintz #include <linux/string.h> 4625c089d7SYuval Mintz #include <linux/workqueue.h> 4725c089d7SYuval Mintz #include <linux/bitops.h> 4825c089d7SYuval Mintz #include <linux/bug.h> 493da7a37aSMintz, Yuval #include <linux/vmalloc.h> 5025c089d7SYuval Mintz #include "qed.h" 5125c089d7SYuval Mintz #include <linux/qed/qed_chain.h> 5225c089d7SYuval Mintz #include "qed_cxt.h" 5325c089d7SYuval Mintz #include "qed_dev_api.h" 5425c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h> 5525c089d7SYuval Mintz #include "qed_hsi.h" 5625c089d7SYuval Mintz #include "qed_hw.h" 5725c089d7SYuval Mintz #include "qed_int.h" 58dacd88d6SYuval Mintz #include "qed_l2.h" 5986622ee7SYuval Mintz #include "qed_mcp.h" 6025c089d7SYuval Mintz #include "qed_reg_addr.h" 6125c089d7SYuval Mintz #include "qed_sp.h" 621408cc1fSYuval Mintz #include "qed_sriov.h" 6325c089d7SYuval Mintz 64088c8618SManish Chopra 65cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16 66cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41 67cee4d264SManish Chopra 680db711bbSMintz, Yuval struct qed_l2_info { 690db711bbSMintz, Yuval u32 queues; 700db711bbSMintz, Yuval unsigned long **pp_qid_usage; 710db711bbSMintz, Yuval 720db711bbSMintz, Yuval /* The lock is meant to synchronize access to the qid usage */ 730db711bbSMintz, Yuval struct mutex lock; 740db711bbSMintz, Yuval }; 750db711bbSMintz, Yuval 760db711bbSMintz, Yuval int qed_l2_alloc(struct qed_hwfn *p_hwfn) 770db711bbSMintz, Yuval { 780db711bbSMintz, Yuval struct qed_l2_info *p_l2_info; 790db711bbSMintz, Yuval unsigned long **pp_qids; 800db711bbSMintz, Yuval u32 i; 810db711bbSMintz, Yuval 820db711bbSMintz, Yuval if (p_hwfn->hw_info.personality != QED_PCI_ETH && 830db711bbSMintz, Yuval p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE) 840db711bbSMintz, Yuval return 0; 850db711bbSMintz, Yuval 860db711bbSMintz, Yuval p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL); 870db711bbSMintz, Yuval if (!p_l2_info) 880db711bbSMintz, Yuval return -ENOMEM; 890db711bbSMintz, Yuval p_hwfn->p_l2_info = p_l2_info; 900db711bbSMintz, Yuval 910db711bbSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 920db711bbSMintz, Yuval p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE); 930db711bbSMintz, Yuval } else { 940db711bbSMintz, Yuval u8 rx = 0, tx = 0; 950db711bbSMintz, Yuval 960db711bbSMintz, Yuval qed_vf_get_num_rxqs(p_hwfn, &rx); 970db711bbSMintz, Yuval qed_vf_get_num_txqs(p_hwfn, &tx); 980db711bbSMintz, Yuval 990db711bbSMintz, Yuval p_l2_info->queues = max_t(u8, rx, tx); 1000db711bbSMintz, Yuval } 1010db711bbSMintz, Yuval 1020db711bbSMintz, Yuval pp_qids = kzalloc(sizeof(unsigned long *) * p_l2_info->queues, 1030db711bbSMintz, Yuval GFP_KERNEL); 1040db711bbSMintz, Yuval if (!pp_qids) 1050db711bbSMintz, Yuval return -ENOMEM; 1060db711bbSMintz, Yuval p_l2_info->pp_qid_usage = pp_qids; 1070db711bbSMintz, Yuval 1080db711bbSMintz, Yuval for (i = 0; i < p_l2_info->queues; i++) { 1090db711bbSMintz, Yuval pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL); 1100db711bbSMintz, Yuval if (!pp_qids[i]) 1110db711bbSMintz, Yuval return -ENOMEM; 1120db711bbSMintz, Yuval } 1130db711bbSMintz, Yuval 1140db711bbSMintz, Yuval return 0; 1150db711bbSMintz, Yuval } 1160db711bbSMintz, Yuval 1170db711bbSMintz, Yuval void qed_l2_setup(struct qed_hwfn *p_hwfn) 1180db711bbSMintz, Yuval { 1190db711bbSMintz, Yuval if (p_hwfn->hw_info.personality != QED_PCI_ETH && 1200db711bbSMintz, Yuval p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE) 1210db711bbSMintz, Yuval return; 1220db711bbSMintz, Yuval 1230db711bbSMintz, Yuval mutex_init(&p_hwfn->p_l2_info->lock); 1240db711bbSMintz, Yuval } 1250db711bbSMintz, Yuval 1260db711bbSMintz, Yuval void qed_l2_free(struct qed_hwfn *p_hwfn) 1270db711bbSMintz, Yuval { 1280db711bbSMintz, Yuval u32 i; 1290db711bbSMintz, Yuval 1300db711bbSMintz, Yuval if (p_hwfn->hw_info.personality != QED_PCI_ETH && 1310db711bbSMintz, Yuval p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE) 1320db711bbSMintz, Yuval return; 1330db711bbSMintz, Yuval 1340db711bbSMintz, Yuval if (!p_hwfn->p_l2_info) 1350db711bbSMintz, Yuval return; 1360db711bbSMintz, Yuval 1370db711bbSMintz, Yuval if (!p_hwfn->p_l2_info->pp_qid_usage) 1380db711bbSMintz, Yuval goto out_l2_info; 1390db711bbSMintz, Yuval 1400db711bbSMintz, Yuval /* Free until hit first uninitialized entry */ 1410db711bbSMintz, Yuval for (i = 0; i < p_hwfn->p_l2_info->queues; i++) { 1420db711bbSMintz, Yuval if (!p_hwfn->p_l2_info->pp_qid_usage[i]) 1430db711bbSMintz, Yuval break; 1440db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info->pp_qid_usage[i]); 1450db711bbSMintz, Yuval } 1460db711bbSMintz, Yuval 1470db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info->pp_qid_usage); 1480db711bbSMintz, Yuval 1490db711bbSMintz, Yuval out_l2_info: 1500db711bbSMintz, Yuval kfree(p_hwfn->p_l2_info); 1510db711bbSMintz, Yuval p_hwfn->p_l2_info = NULL; 1520db711bbSMintz, Yuval } 1530db711bbSMintz, Yuval 154bbe3f233SMintz, Yuval static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn, 155bbe3f233SMintz, Yuval struct qed_queue_cid *p_cid) 156bbe3f233SMintz, Yuval { 157bbe3f233SMintz, Yuval struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info; 158bbe3f233SMintz, Yuval u16 queue_id = p_cid->rel.queue_id; 159bbe3f233SMintz, Yuval bool b_rc = true; 160bbe3f233SMintz, Yuval u8 first; 161bbe3f233SMintz, Yuval 162bbe3f233SMintz, Yuval mutex_lock(&p_l2_info->lock); 163bbe3f233SMintz, Yuval 1640331402aSDan Carpenter if (queue_id >= p_l2_info->queues) { 165bbe3f233SMintz, Yuval DP_NOTICE(p_hwfn, 166bbe3f233SMintz, Yuval "Requested to increase usage for qzone %04x out of %08x\n", 167bbe3f233SMintz, Yuval queue_id, p_l2_info->queues); 168bbe3f233SMintz, Yuval b_rc = false; 169bbe3f233SMintz, Yuval goto out; 170bbe3f233SMintz, Yuval } 171bbe3f233SMintz, Yuval 172bbe3f233SMintz, Yuval first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id], 173bbe3f233SMintz, Yuval MAX_QUEUES_PER_QZONE); 174bbe3f233SMintz, Yuval if (first >= MAX_QUEUES_PER_QZONE) { 175bbe3f233SMintz, Yuval b_rc = false; 176bbe3f233SMintz, Yuval goto out; 177bbe3f233SMintz, Yuval } 178bbe3f233SMintz, Yuval 179bbe3f233SMintz, Yuval __set_bit(first, p_l2_info->pp_qid_usage[queue_id]); 180bbe3f233SMintz, Yuval p_cid->qid_usage_idx = first; 181bbe3f233SMintz, Yuval 182bbe3f233SMintz, Yuval out: 183bbe3f233SMintz, Yuval mutex_unlock(&p_l2_info->lock); 184bbe3f233SMintz, Yuval return b_rc; 185bbe3f233SMintz, Yuval } 186bbe3f233SMintz, Yuval 187bbe3f233SMintz, Yuval static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn, 188bbe3f233SMintz, Yuval struct qed_queue_cid *p_cid) 189bbe3f233SMintz, Yuval { 190bbe3f233SMintz, Yuval mutex_lock(&p_hwfn->p_l2_info->lock); 191bbe3f233SMintz, Yuval 192bbe3f233SMintz, Yuval clear_bit(p_cid->qid_usage_idx, 193bbe3f233SMintz, Yuval p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]); 194bbe3f233SMintz, Yuval 195bbe3f233SMintz, Yuval mutex_unlock(&p_hwfn->p_l2_info->lock); 196bbe3f233SMintz, Yuval } 197bbe3f233SMintz, Yuval 1983da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn, 1993da7a37aSMintz, Yuval struct qed_queue_cid *p_cid) 2003da7a37aSMintz, Yuval { 20108bc8f15SMintz, Yuval bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID); 20208bc8f15SMintz, Yuval 20308bc8f15SMintz, Yuval if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) 20408bc8f15SMintz, Yuval _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid); 205bbe3f233SMintz, Yuval 206bbe3f233SMintz, Yuval /* For PF's VFs we maintain the index inside queue-zone in IOV */ 207bbe3f233SMintz, Yuval if (p_cid->vfid == QED_QUEUE_CID_SELF) 208bbe3f233SMintz, Yuval qed_eth_queue_qid_usage_del(p_hwfn, p_cid); 209bbe3f233SMintz, Yuval 2103da7a37aSMintz, Yuval vfree(p_cid); 2113da7a37aSMintz, Yuval } 2123da7a37aSMintz, Yuval 2133da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs 2143da7a37aSMintz, Yuval * for their VFs. 2153da7a37aSMintz, Yuval */ 2163946497aSMintz, Yuval static struct qed_queue_cid * 2173da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 2183da7a37aSMintz, Yuval u16 opaque_fid, 2193da7a37aSMintz, Yuval u32 cid, 2203946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 221007bc371SMintz, Yuval bool b_is_rx, 2223946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params) 2233da7a37aSMintz, Yuval { 2243da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 2253da7a37aSMintz, Yuval int rc; 2263da7a37aSMintz, Yuval 2273da7a37aSMintz, Yuval p_cid = vmalloc(sizeof(*p_cid)); 2283da7a37aSMintz, Yuval if (!p_cid) 2293da7a37aSMintz, Yuval return NULL; 2303da7a37aSMintz, Yuval memset(p_cid, 0, sizeof(*p_cid)); 2313da7a37aSMintz, Yuval 2323da7a37aSMintz, Yuval p_cid->opaque_fid = opaque_fid; 2333da7a37aSMintz, Yuval p_cid->cid = cid; 234f29ffdb6SMintz, Yuval p_cid->p_owner = p_hwfn; 2353da7a37aSMintz, Yuval 236f604b17dSMintz, Yuval /* Fill in parameters */ 237f604b17dSMintz, Yuval p_cid->rel.vport_id = p_params->vport_id; 238f604b17dSMintz, Yuval p_cid->rel.queue_id = p_params->queue_id; 239f604b17dSMintz, Yuval p_cid->rel.stats_id = p_params->stats_id; 240f604b17dSMintz, Yuval p_cid->sb_igu_id = p_params->p_sb->igu_sb_id; 241007bc371SMintz, Yuval p_cid->b_is_rx = b_is_rx; 242f604b17dSMintz, Yuval p_cid->sb_idx = p_params->sb_idx; 243f604b17dSMintz, Yuval 2443946497aSMintz, Yuval /* Fill-in bits related to VFs' queues if information was provided */ 2453946497aSMintz, Yuval if (p_vf_params) { 2463946497aSMintz, Yuval p_cid->vfid = p_vf_params->vfid; 2473946497aSMintz, Yuval p_cid->vf_qid = p_vf_params->vf_qid; 2483b19f478SMintz, Yuval p_cid->vf_legacy = p_vf_params->vf_legacy; 2493946497aSMintz, Yuval } else { 2503946497aSMintz, Yuval p_cid->vfid = QED_QUEUE_CID_SELF; 2513946497aSMintz, Yuval } 2523946497aSMintz, Yuval 2533da7a37aSMintz, Yuval /* Don't try calculating the absolute indices for VFs */ 2543da7a37aSMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 2553da7a37aSMintz, Yuval p_cid->abs = p_cid->rel; 2563da7a37aSMintz, Yuval goto out; 2573da7a37aSMintz, Yuval } 2583da7a37aSMintz, Yuval 2593da7a37aSMintz, Yuval /* Calculate the engine-absolute indices of the resources. 2603da7a37aSMintz, Yuval * This would guarantee they're valid later on. 2613da7a37aSMintz, Yuval * In some cases [SBs] we already have the right values. 2623da7a37aSMintz, Yuval */ 2633da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id); 2643da7a37aSMintz, Yuval if (rc) 2653da7a37aSMintz, Yuval goto fail; 2663da7a37aSMintz, Yuval 2673da7a37aSMintz, Yuval rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id); 2683da7a37aSMintz, Yuval if (rc) 2693da7a37aSMintz, Yuval goto fail; 2703da7a37aSMintz, Yuval 2713da7a37aSMintz, Yuval /* In case of a PF configuring its VF's queues, the stats-id is already 2723da7a37aSMintz, Yuval * absolute [since there's a single index that's suitable per-VF]. 2733da7a37aSMintz, Yuval */ 2743946497aSMintz, Yuval if (p_cid->vfid == QED_QUEUE_CID_SELF) { 2753da7a37aSMintz, Yuval rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id, 2763da7a37aSMintz, Yuval &p_cid->abs.stats_id); 2773da7a37aSMintz, Yuval if (rc) 2783da7a37aSMintz, Yuval goto fail; 2793da7a37aSMintz, Yuval } else { 2803da7a37aSMintz, Yuval p_cid->abs.stats_id = p_cid->rel.stats_id; 2813da7a37aSMintz, Yuval } 2823da7a37aSMintz, Yuval 2833da7a37aSMintz, Yuval out: 284bbe3f233SMintz, Yuval /* VF-images have provided the qid_usage_idx on their own. 285bbe3f233SMintz, Yuval * Otherwise, we need to allocate a unique one. 286bbe3f233SMintz, Yuval */ 287bbe3f233SMintz, Yuval if (!p_vf_params) { 288bbe3f233SMintz, Yuval if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid)) 289bbe3f233SMintz, Yuval goto fail; 290bbe3f233SMintz, Yuval } else { 291bbe3f233SMintz, Yuval p_cid->qid_usage_idx = p_vf_params->qid_usage_idx; 292bbe3f233SMintz, Yuval } 293bbe3f233SMintz, Yuval 2943da7a37aSMintz, Yuval DP_VERBOSE(p_hwfn, 2953da7a37aSMintz, Yuval QED_MSG_SP, 296bbe3f233SMintz, Yuval "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n", 2973da7a37aSMintz, Yuval p_cid->opaque_fid, 2983da7a37aSMintz, Yuval p_cid->cid, 2993da7a37aSMintz, Yuval p_cid->rel.vport_id, 3003da7a37aSMintz, Yuval p_cid->abs.vport_id, 3013da7a37aSMintz, Yuval p_cid->rel.queue_id, 302bbe3f233SMintz, Yuval p_cid->qid_usage_idx, 3033da7a37aSMintz, Yuval p_cid->abs.queue_id, 3043da7a37aSMintz, Yuval p_cid->rel.stats_id, 305f604b17dSMintz, Yuval p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx); 3063da7a37aSMintz, Yuval 3073da7a37aSMintz, Yuval return p_cid; 3083da7a37aSMintz, Yuval 3093da7a37aSMintz, Yuval fail: 3103da7a37aSMintz, Yuval vfree(p_cid); 3113da7a37aSMintz, Yuval return NULL; 3123da7a37aSMintz, Yuval } 3133da7a37aSMintz, Yuval 3143946497aSMintz, Yuval struct qed_queue_cid * 3153946497aSMintz, Yuval qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, 3163946497aSMintz, Yuval u16 opaque_fid, 3173946497aSMintz, Yuval struct qed_queue_start_common_params *p_params, 318007bc371SMintz, Yuval bool b_is_rx, 3193946497aSMintz, Yuval struct qed_queue_cid_vf_params *p_vf_params) 3203da7a37aSMintz, Yuval { 3213da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 32208bc8f15SMintz, Yuval u8 vfid = QED_CXT_PF_CID; 3233946497aSMintz, Yuval bool b_legacy_vf = false; 3243da7a37aSMintz, Yuval u32 cid = 0; 3253da7a37aSMintz, Yuval 32608bc8f15SMintz, Yuval /* In case of legacy VFs, The CID can be derived from the additional 32708bc8f15SMintz, Yuval * VF parameters - the VF assumes queue X uses CID X, so we can simply 32808bc8f15SMintz, Yuval * use the vf_qid for this purpose as well. 32908bc8f15SMintz, Yuval */ 33008bc8f15SMintz, Yuval if (p_vf_params) { 33108bc8f15SMintz, Yuval vfid = p_vf_params->vfid; 33208bc8f15SMintz, Yuval 33308bc8f15SMintz, Yuval if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) { 3343946497aSMintz, Yuval b_legacy_vf = true; 33508bc8f15SMintz, Yuval cid = p_vf_params->vf_qid; 33608bc8f15SMintz, Yuval } 33708bc8f15SMintz, Yuval } 33808bc8f15SMintz, Yuval 3393da7a37aSMintz, Yuval /* Get a unique firmware CID for this queue, in case it's a PF. 3403da7a37aSMintz, Yuval * VF's don't need a CID as the queue configuration will be done 3413da7a37aSMintz, Yuval * by PF. 3423da7a37aSMintz, Yuval */ 3433946497aSMintz, Yuval if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) { 34408bc8f15SMintz, Yuval if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 34508bc8f15SMintz, Yuval &cid, vfid)) { 3463da7a37aSMintz, Yuval DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); 3473da7a37aSMintz, Yuval return NULL; 3483da7a37aSMintz, Yuval } 3493da7a37aSMintz, Yuval } 3503da7a37aSMintz, Yuval 3513946497aSMintz, Yuval p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 352007bc371SMintz, Yuval p_params, b_is_rx, p_vf_params); 3533946497aSMintz, Yuval if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf) 35408bc8f15SMintz, Yuval _qed_cxt_release_cid(p_hwfn, cid, vfid); 3553da7a37aSMintz, Yuval 3563da7a37aSMintz, Yuval return p_cid; 3573da7a37aSMintz, Yuval } 3583da7a37aSMintz, Yuval 3593946497aSMintz, Yuval static struct qed_queue_cid * 3603946497aSMintz, Yuval qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn, 3613946497aSMintz, Yuval u16 opaque_fid, 362007bc371SMintz, Yuval bool b_is_rx, 3633946497aSMintz, Yuval struct qed_queue_start_common_params *p_params) 3643946497aSMintz, Yuval { 365007bc371SMintz, Yuval return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx, 3663946497aSMintz, Yuval NULL); 3673946497aSMintz, Yuval } 3683946497aSMintz, Yuval 369dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, 370088c8618SManish Chopra struct qed_sp_vport_start_params *p_params) 371cee4d264SManish Chopra { 372cee4d264SManish Chopra struct vport_start_ramrod_data *p_ramrod = NULL; 373cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 37406f56b81SYuval Mintz struct qed_sp_init_data init_data; 375dacd88d6SYuval Mintz u8 abs_vport_id = 0; 376cee4d264SManish Chopra int rc = -EINVAL; 377cee4d264SManish Chopra u16 rx_mode = 0; 378cee4d264SManish Chopra 379088c8618SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 3801a635e48SYuval Mintz if (rc) 381cee4d264SManish Chopra return rc; 382cee4d264SManish Chopra 38306f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 38406f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 385088c8618SManish Chopra init_data.opaque_fid = p_params->opaque_fid; 38606f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 387cee4d264SManish Chopra 388cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 389cee4d264SManish Chopra ETH_RAMROD_VPORT_START, 39006f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 391cee4d264SManish Chopra if (rc) 392cee4d264SManish Chopra return rc; 393cee4d264SManish Chopra 394cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_start; 395cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 396cee4d264SManish Chopra 397088c8618SManish Chopra p_ramrod->mtu = cpu_to_le16(p_params->mtu); 398c78c70faSSudarsana Reddy Kalluru p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts; 399088c8618SManish Chopra p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 400088c8618SManish Chopra p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 401e6bd8923SYuval Mintz p_ramrod->untagged = p_params->only_untagged; 402cee4d264SManish Chopra 403cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 404cee4d264SManish Chopra SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 405cee4d264SManish Chopra 406cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); 407cee4d264SManish Chopra 408cee4d264SManish Chopra /* TPA related fields */ 4091a635e48SYuval Mintz memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param)); 410cee4d264SManish Chopra 411088c8618SManish Chopra p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; 412088c8618SManish Chopra 413088c8618SManish Chopra switch (p_params->tpa_mode) { 414088c8618SManish Chopra case QED_TPA_MODE_GRO: 415088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 416088c8618SManish Chopra p_ramrod->tpa_param.tpa_max_size = (u16)-1; 417088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; 418088c8618SManish Chopra p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; 419088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; 420088c8618SManish Chopra p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; 421088c8618SManish Chopra p_ramrod->tpa_param.tpa_pkt_split_flg = 1; 422088c8618SManish Chopra p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; 423088c8618SManish Chopra break; 424088c8618SManish Chopra default: 425088c8618SManish Chopra break; 426088c8618SManish Chopra } 427088c8618SManish Chopra 428831bfb0eSYuval Mintz p_ramrod->tx_switching_en = p_params->tx_switching; 429831bfb0eSYuval Mintz 43011a85d75SYuval Mintz p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac; 43111a85d75SYuval Mintz p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype; 43211a85d75SYuval Mintz 433cee4d264SManish Chopra /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 434cee4d264SManish Chopra p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, 435088c8618SManish Chopra p_params->concrete_fid); 436cee4d264SManish Chopra 437cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 438cee4d264SManish Chopra } 439cee4d264SManish Chopra 440ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, 441dacd88d6SYuval Mintz struct qed_sp_vport_start_params *p_params) 442dacd88d6SYuval Mintz { 443dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 444dacd88d6SYuval Mintz return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, 445dacd88d6SYuval Mintz p_params->mtu, 446dacd88d6SYuval Mintz p_params->remove_inner_vlan, 447dacd88d6SYuval Mintz p_params->tpa_mode, 44808feecd7SYuval Mintz p_params->max_buffers_per_cqe, 44908feecd7SYuval Mintz p_params->only_untagged); 450dacd88d6SYuval Mintz } 451dacd88d6SYuval Mintz 452dacd88d6SYuval Mintz return qed_sp_eth_vport_start(p_hwfn, p_params); 453dacd88d6SYuval Mintz } 454dacd88d6SYuval Mintz 455cee4d264SManish Chopra static int 456cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, 457cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 458f29ffdb6SMintz, Yuval struct qed_rss_params *p_rss) 459cee4d264SManish Chopra { 460f29ffdb6SMintz, Yuval struct eth_vport_rss_config *p_config; 461f29ffdb6SMintz, Yuval u16 capabilities = 0; 462f29ffdb6SMintz, Yuval int i, table_size; 463f29ffdb6SMintz, Yuval int rc = 0; 464cee4d264SManish Chopra 465f29ffdb6SMintz, Yuval if (!p_rss) { 466cee4d264SManish Chopra p_ramrod->common.update_rss_flg = 0; 467cee4d264SManish Chopra return rc; 468cee4d264SManish Chopra } 469f29ffdb6SMintz, Yuval p_config = &p_ramrod->rss_config; 470cee4d264SManish Chopra 471f29ffdb6SMintz, Yuval BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM); 472cee4d264SManish Chopra 473f29ffdb6SMintz, Yuval rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id); 474cee4d264SManish Chopra if (rc) 475cee4d264SManish Chopra return rc; 476cee4d264SManish Chopra 477f29ffdb6SMintz, Yuval p_ramrod->common.update_rss_flg = p_rss->update_rss_config; 478f29ffdb6SMintz, Yuval p_config->update_rss_capabilities = p_rss->update_rss_capabilities; 479f29ffdb6SMintz, Yuval p_config->update_rss_ind_table = p_rss->update_rss_ind_table; 480f29ffdb6SMintz, Yuval p_config->update_rss_key = p_rss->update_rss_key; 481cee4d264SManish Chopra 482f29ffdb6SMintz, Yuval p_config->rss_mode = p_rss->rss_enable ? 483cee4d264SManish Chopra ETH_VPORT_RSS_MODE_REGULAR : 484cee4d264SManish Chopra ETH_VPORT_RSS_MODE_DISABLED; 485cee4d264SManish Chopra 486cee4d264SManish Chopra SET_FIELD(capabilities, 487cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 488f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4)); 489cee4d264SManish Chopra SET_FIELD(capabilities, 490cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 491f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6)); 492cee4d264SManish Chopra SET_FIELD(capabilities, 493cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 494f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_TCP)); 495cee4d264SManish Chopra SET_FIELD(capabilities, 496cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 497f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_TCP)); 498cee4d264SManish Chopra SET_FIELD(capabilities, 499cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 500f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV4_UDP)); 501cee4d264SManish Chopra SET_FIELD(capabilities, 502cee4d264SManish Chopra ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 503f29ffdb6SMintz, Yuval !!(p_rss->rss_caps & QED_RSS_IPV6_UDP)); 504f29ffdb6SMintz, Yuval p_config->tbl_size = p_rss->rss_table_size_log; 505cee4d264SManish Chopra 506f29ffdb6SMintz, Yuval p_config->capabilities = cpu_to_le16(capabilities); 507cee4d264SManish Chopra 508cee4d264SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 509cee4d264SManish Chopra "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 510cee4d264SManish Chopra p_ramrod->common.update_rss_flg, 511f29ffdb6SMintz, Yuval p_config->rss_mode, 512f29ffdb6SMintz, Yuval p_config->update_rss_capabilities, 513f29ffdb6SMintz, Yuval p_config->capabilities, 514f29ffdb6SMintz, Yuval p_config->update_rss_ind_table, p_config->update_rss_key); 515cee4d264SManish Chopra 516f29ffdb6SMintz, Yuval table_size = min_t(int, QED_RSS_IND_TABLE_SIZE, 517f29ffdb6SMintz, Yuval 1 << p_config->tbl_size); 518f29ffdb6SMintz, Yuval for (i = 0; i < table_size; i++) { 519f29ffdb6SMintz, Yuval struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i]; 520cee4d264SManish Chopra 521f29ffdb6SMintz, Yuval if (!p_queue) 522f29ffdb6SMintz, Yuval return -EINVAL; 523f29ffdb6SMintz, Yuval 524f29ffdb6SMintz, Yuval p_config->indirection_table[i] = 525f29ffdb6SMintz, Yuval cpu_to_le16(p_queue->abs.queue_id); 526f29ffdb6SMintz, Yuval } 527f29ffdb6SMintz, Yuval 528f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 529f29ffdb6SMintz, Yuval "Configured RSS indirection table [%d entries]:\n", 530f29ffdb6SMintz, Yuval table_size); 531f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) { 532f29ffdb6SMintz, Yuval DP_VERBOSE(p_hwfn, 533f29ffdb6SMintz, Yuval NETIF_MSG_IFUP, 534f29ffdb6SMintz, Yuval "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", 535f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i]), 536f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 1]), 537f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 2]), 538f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 3]), 539f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 4]), 540f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 5]), 541f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 6]), 542f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 7]), 543f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 8]), 544f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 9]), 545f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 10]), 546f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 11]), 547f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 12]), 548f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 13]), 549f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 14]), 550f29ffdb6SMintz, Yuval le16_to_cpu(p_config->indirection_table[i + 15])); 551cee4d264SManish Chopra } 552cee4d264SManish Chopra 553cee4d264SManish Chopra for (i = 0; i < 10; i++) 554f29ffdb6SMintz, Yuval p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]); 555cee4d264SManish Chopra 556cee4d264SManish Chopra return rc; 557cee4d264SManish Chopra } 558cee4d264SManish Chopra 559cee4d264SManish Chopra static void 560cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, 561cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 562cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags) 563cee4d264SManish Chopra { 564cee4d264SManish Chopra p_ramrod->common.update_rx_mode_flg = 565cee4d264SManish Chopra accept_flags.update_rx_mode_config; 566cee4d264SManish Chopra 567cee4d264SManish Chopra p_ramrod->common.update_tx_mode_flg = 568cee4d264SManish Chopra accept_flags.update_tx_mode_config; 569cee4d264SManish Chopra 570cee4d264SManish Chopra /* Set Rx mode accept flags */ 571cee4d264SManish Chopra if (p_ramrod->common.update_rx_mode_flg) { 572cee4d264SManish Chopra u8 accept_filter = accept_flags.rx_accept_filter; 573cee4d264SManish Chopra u16 state = 0; 574cee4d264SManish Chopra 575cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 576cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || 577cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); 578cee4d264SManish Chopra 579cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 580cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); 581cee4d264SManish Chopra 582cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 583cee4d264SManish Chopra !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || 584cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 585cee4d264SManish Chopra 586cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 587cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 588cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 589cee4d264SManish Chopra 590cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 591cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 592cee4d264SManish Chopra 593cee4d264SManish Chopra p_ramrod->rx_mode.state = cpu_to_le16(state); 594cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 595cee4d264SManish Chopra "p_ramrod->rx_mode.state = 0x%x\n", state); 596cee4d264SManish Chopra } 597cee4d264SManish Chopra 598cee4d264SManish Chopra /* Set Tx mode accept flags */ 599cee4d264SManish Chopra if (p_ramrod->common.update_tx_mode_flg) { 600cee4d264SManish Chopra u8 accept_filter = accept_flags.tx_accept_filter; 601cee4d264SManish Chopra u16 state = 0; 602cee4d264SManish Chopra 603cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 604cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 605cee4d264SManish Chopra 606cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 607cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_NONE)); 608cee4d264SManish Chopra 609cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 610cee4d264SManish Chopra (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && 611cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); 612cee4d264SManish Chopra 613cee4d264SManish Chopra SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 614cee4d264SManish Chopra !!(accept_filter & QED_ACCEPT_BCAST)); 615cee4d264SManish Chopra 616cee4d264SManish Chopra p_ramrod->tx_mode.state = cpu_to_le16(state); 617cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 618cee4d264SManish Chopra "p_ramrod->tx_mode.state = 0x%x\n", state); 619cee4d264SManish Chopra } 620cee4d264SManish Chopra } 621cee4d264SManish Chopra 622cee4d264SManish Chopra static void 62317b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, 62417b235c1SYuval Mintz struct vport_update_ramrod_data *p_ramrod, 62517b235c1SYuval Mintz struct qed_sge_tpa_params *p_params) 62617b235c1SYuval Mintz { 62717b235c1SYuval Mintz struct eth_vport_tpa_param *p_tpa; 62817b235c1SYuval Mintz 62917b235c1SYuval Mintz if (!p_params) { 63017b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 63117b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = 0; 63217b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = 0; 63317b235c1SYuval Mintz return; 63417b235c1SYuval Mintz } 63517b235c1SYuval Mintz 63617b235c1SYuval Mintz p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; 63717b235c1SYuval Mintz p_tpa = &p_ramrod->tpa_param; 63817b235c1SYuval Mintz p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; 63917b235c1SYuval Mintz p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; 64017b235c1SYuval Mintz p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; 64117b235c1SYuval Mintz p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; 64217b235c1SYuval Mintz 64317b235c1SYuval Mintz p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; 64417b235c1SYuval Mintz p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 64517b235c1SYuval Mintz p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; 64617b235c1SYuval Mintz p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; 64717b235c1SYuval Mintz p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; 64817b235c1SYuval Mintz p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; 64917b235c1SYuval Mintz p_tpa->tpa_max_size = p_params->tpa_max_size; 65017b235c1SYuval Mintz p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; 65117b235c1SYuval Mintz p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; 65217b235c1SYuval Mintz } 65317b235c1SYuval Mintz 65417b235c1SYuval Mintz static void 655cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, 656cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod, 657cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params) 658cee4d264SManish Chopra { 659cee4d264SManish Chopra int i; 660cee4d264SManish Chopra 661cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 662cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 663cee4d264SManish Chopra 66483aeb933SYuval Mintz if (!p_params->update_approx_mcast_flg) 66583aeb933SYuval Mintz return; 66683aeb933SYuval Mintz 667cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 668cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 669cee4d264SManish Chopra u32 *p_bins = (u32 *)p_params->bins; 670cee4d264SManish Chopra 67183aeb933SYuval Mintz p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]); 672cee4d264SManish Chopra } 673cee4d264SManish Chopra } 674cee4d264SManish Chopra 675dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn, 676cee4d264SManish Chopra struct qed_sp_vport_update_params *p_params, 677cee4d264SManish Chopra enum spq_mode comp_mode, 678cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 679cee4d264SManish Chopra { 680cee4d264SManish Chopra struct qed_rss_params *p_rss_params = p_params->rss_params; 681cee4d264SManish Chopra struct vport_update_ramrod_data_cmn *p_cmn; 68206f56b81SYuval Mintz struct qed_sp_init_data init_data; 683cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 684cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 68517b235c1SYuval Mintz u8 abs_vport_id = 0, val; 686cee4d264SManish Chopra int rc = -EINVAL; 687cee4d264SManish Chopra 688dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) { 689dacd88d6SYuval Mintz rc = qed_vf_pf_vport_update(p_hwfn, p_params); 690dacd88d6SYuval Mintz return rc; 691dacd88d6SYuval Mintz } 692dacd88d6SYuval Mintz 693cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 6941a635e48SYuval Mintz if (rc) 695cee4d264SManish Chopra return rc; 696cee4d264SManish Chopra 69706f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 69806f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 69906f56b81SYuval Mintz init_data.opaque_fid = p_params->opaque_fid; 70006f56b81SYuval Mintz init_data.comp_mode = comp_mode; 70106f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 702cee4d264SManish Chopra 703cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 704cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 70506f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 706cee4d264SManish Chopra if (rc) 707cee4d264SManish Chopra return rc; 708cee4d264SManish Chopra 709cee4d264SManish Chopra /* Copy input params to ramrod according to FW struct */ 710cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 711cee4d264SManish Chopra p_cmn = &p_ramrod->common; 712cee4d264SManish Chopra 713cee4d264SManish Chopra p_cmn->vport_id = abs_vport_id; 714cee4d264SManish Chopra p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 715cee4d264SManish Chopra p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 716cee4d264SManish Chopra p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 717cee4d264SManish Chopra p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 7183f9b4a69SYuval Mintz p_cmn->accept_any_vlan = p_params->accept_any_vlan; 71983aeb933SYuval Mintz val = p_params->update_accept_any_vlan_flg; 72083aeb933SYuval Mintz p_cmn->update_accept_any_vlan_flg = val; 72117b235c1SYuval Mintz 72217b235c1SYuval Mintz p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; 72317b235c1SYuval Mintz val = p_params->update_inner_vlan_removal_flg; 72417b235c1SYuval Mintz p_cmn->update_inner_vlan_removal_en_flg = val; 72508feecd7SYuval Mintz 72608feecd7SYuval Mintz p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; 72708feecd7SYuval Mintz val = p_params->update_default_vlan_enable_flg; 72808feecd7SYuval Mintz p_cmn->update_default_vlan_en_flg = val; 72908feecd7SYuval Mintz 73008feecd7SYuval Mintz p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); 73108feecd7SYuval Mintz p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; 73208feecd7SYuval Mintz 73308feecd7SYuval Mintz p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; 73408feecd7SYuval Mintz 73517b235c1SYuval Mintz p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; 73617b235c1SYuval Mintz p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; 73717b235c1SYuval Mintz 7386ddc7608SYuval Mintz p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; 7396ddc7608SYuval Mintz val = p_params->update_anti_spoofing_en_flg; 7406ddc7608SYuval Mintz p_ramrod->common.update_anti_spoofing_en_flg = val; 7416ddc7608SYuval Mintz 742cee4d264SManish Chopra rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 743cee4d264SManish Chopra if (rc) { 744cee4d264SManish Chopra /* Return spq entry which is taken in qed_sp_init_request()*/ 745cee4d264SManish Chopra qed_spq_return_entry(p_hwfn, p_ent); 746cee4d264SManish Chopra return rc; 747cee4d264SManish Chopra } 748cee4d264SManish Chopra 749cee4d264SManish Chopra /* Update mcast bins for VFs, PF doesn't use this functionality */ 750cee4d264SManish Chopra qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); 751cee4d264SManish Chopra 752cee4d264SManish Chopra qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 75317b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); 754cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 755cee4d264SManish Chopra } 756cee4d264SManish Chopra 757dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) 758cee4d264SManish Chopra { 759cee4d264SManish Chopra struct vport_stop_ramrod_data *p_ramrod; 76006f56b81SYuval Mintz struct qed_sp_init_data init_data; 761cee4d264SManish Chopra struct qed_spq_entry *p_ent; 762cee4d264SManish Chopra u8 abs_vport_id = 0; 763cee4d264SManish Chopra int rc; 764cee4d264SManish Chopra 765dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 766dacd88d6SYuval Mintz return qed_vf_pf_vport_stop(p_hwfn); 767dacd88d6SYuval Mintz 768cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 7691a635e48SYuval Mintz if (rc) 770cee4d264SManish Chopra return rc; 771cee4d264SManish Chopra 77206f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 77306f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 77406f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 77506f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 776cee4d264SManish Chopra 777cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 778cee4d264SManish Chopra ETH_RAMROD_VPORT_STOP, 77906f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 780cee4d264SManish Chopra if (rc) 781cee4d264SManish Chopra return rc; 782cee4d264SManish Chopra 783cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_stop; 784cee4d264SManish Chopra p_ramrod->vport_id = abs_vport_id; 785cee4d264SManish Chopra 786cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 787cee4d264SManish Chopra } 788cee4d264SManish Chopra 789dacd88d6SYuval Mintz static int 790dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, 791dacd88d6SYuval Mintz struct qed_filter_accept_flags *p_accept_flags) 792dacd88d6SYuval Mintz { 793dacd88d6SYuval Mintz struct qed_sp_vport_update_params s_params; 794dacd88d6SYuval Mintz 795dacd88d6SYuval Mintz memset(&s_params, 0, sizeof(s_params)); 796dacd88d6SYuval Mintz memcpy(&s_params.accept_flags, p_accept_flags, 797dacd88d6SYuval Mintz sizeof(struct qed_filter_accept_flags)); 798dacd88d6SYuval Mintz 799dacd88d6SYuval Mintz return qed_vf_pf_vport_update(p_hwfn, &s_params); 800dacd88d6SYuval Mintz } 801dacd88d6SYuval Mintz 802cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev, 803cee4d264SManish Chopra u8 vport, 804cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags, 8053f9b4a69SYuval Mintz u8 update_accept_any_vlan, 8063f9b4a69SYuval Mintz u8 accept_any_vlan, 807cee4d264SManish Chopra enum spq_mode comp_mode, 808cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 809cee4d264SManish Chopra { 810cee4d264SManish Chopra struct qed_sp_vport_update_params vport_update_params; 811cee4d264SManish Chopra int i, rc; 812cee4d264SManish Chopra 813cee4d264SManish Chopra /* Prepare and send the vport rx_mode change */ 814cee4d264SManish Chopra memset(&vport_update_params, 0, sizeof(vport_update_params)); 815cee4d264SManish Chopra vport_update_params.vport_id = vport; 816cee4d264SManish Chopra vport_update_params.accept_flags = accept_flags; 8173f9b4a69SYuval Mintz vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 8183f9b4a69SYuval Mintz vport_update_params.accept_any_vlan = accept_any_vlan; 819cee4d264SManish Chopra 820cee4d264SManish Chopra for_each_hwfn(cdev, i) { 821cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 822cee4d264SManish Chopra 823cee4d264SManish Chopra vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 824cee4d264SManish Chopra 825dacd88d6SYuval Mintz if (IS_VF(cdev)) { 826dacd88d6SYuval Mintz rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); 827dacd88d6SYuval Mintz if (rc) 828dacd88d6SYuval Mintz return rc; 829dacd88d6SYuval Mintz continue; 830dacd88d6SYuval Mintz } 831dacd88d6SYuval Mintz 832cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &vport_update_params, 833cee4d264SManish Chopra comp_mode, p_comp_data); 8341a635e48SYuval Mintz if (rc) { 835cee4d264SManish Chopra DP_ERR(cdev, "Update rx_mode failed %d\n", rc); 836cee4d264SManish Chopra return rc; 837cee4d264SManish Chopra } 838cee4d264SManish Chopra 839cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 840cee4d264SManish Chopra "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 841cee4d264SManish Chopra accept_flags.rx_accept_filter, 842cee4d264SManish Chopra accept_flags.tx_accept_filter); 8433f9b4a69SYuval Mintz if (update_accept_any_vlan) 8443f9b4a69SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 8453f9b4a69SYuval Mintz "accept_any_vlan=%d configured\n", 8463f9b4a69SYuval Mintz accept_any_vlan); 847cee4d264SManish Chopra } 848cee4d264SManish Chopra 849cee4d264SManish Chopra return 0; 850cee4d264SManish Chopra } 851cee4d264SManish Chopra 8523da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, 8533da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 854cee4d264SManish Chopra u16 bd_max_bytes, 855cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 8563da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size) 857cee4d264SManish Chopra { 858cee4d264SManish Chopra struct rx_queue_start_ramrod_data *p_ramrod = NULL; 859cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 86006f56b81SYuval Mintz struct qed_sp_init_data init_data; 861cee4d264SManish Chopra int rc = -EINVAL; 862cee4d264SManish Chopra 863cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 8643da7a37aSMintz, Yuval "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n", 8653da7a37aSMintz, Yuval p_cid->opaque_fid, p_cid->cid, 866f604b17dSMintz, Yuval p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id); 867cee4d264SManish Chopra 86806f56b81SYuval Mintz /* Get SPQ entry */ 86906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 8703da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 8713da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 87206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 873cee4d264SManish Chopra 874cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 875cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_START, 87606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 877cee4d264SManish Chopra if (rc) 878cee4d264SManish Chopra return rc; 879cee4d264SManish Chopra 880cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_start; 881cee4d264SManish Chopra 882f604b17dSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); 883f604b17dSMintz, Yuval p_ramrod->sb_index = p_cid->sb_idx; 8843da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 8853da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 8863da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 887cee4d264SManish Chopra p_ramrod->complete_cqe_flg = 0; 888cee4d264SManish Chopra p_ramrod->complete_event_flg = 1; 889cee4d264SManish Chopra 890cee4d264SManish Chopra p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); 89194494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 892cee4d264SManish Chopra 893cee4d264SManish Chopra p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); 89494494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 895cee4d264SManish Chopra 8963946497aSMintz, Yuval if (p_cid->vfid != QED_QUEUE_CID_SELF) { 8973b19f478SMintz, Yuval bool b_legacy_vf = !!(p_cid->vf_legacy & 8983b19f478SMintz, Yuval QED_QCID_LEGACY_VF_RX_PROD); 8993b19f478SMintz, Yuval 9003da7a37aSMintz, Yuval p_ramrod->vf_rx_prod_index = p_cid->vf_qid; 901351a4dedSYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 902a044df83SYuval Mintz "Queue%s is meant for VF rxq[%02x]\n", 9033b19f478SMintz, Yuval b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid); 9043b19f478SMintz, Yuval p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf; 905a044df83SYuval Mintz } 906cee4d264SManish Chopra 907351a4dedSYuval Mintz return qed_spq_post(p_hwfn, p_ent, NULL); 908cee4d264SManish Chopra } 909cee4d264SManish Chopra 910cee4d264SManish Chopra static int 9113da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn, 9123da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 913cee4d264SManish Chopra u16 bd_max_bytes, 914cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 915cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 916dacd88d6SYuval Mintz u16 cqe_pbl_size, void __iomem **pp_prod) 917cee4d264SManish Chopra { 918b21290b7SYuval Mintz u32 init_prod_val = 0; 919cee4d264SManish Chopra 9203da7a37aSMintz, Yuval *pp_prod = p_hwfn->regview + 921cee4d264SManish Chopra GTT_BAR0_MAP_REG_MSDM_RAM + 9223da7a37aSMintz, Yuval MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); 923cee4d264SManish Chopra 924cee4d264SManish Chopra /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 925b21290b7SYuval Mintz __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), 926cee4d264SManish Chopra (u32 *)(&init_prod_val)); 927cee4d264SManish Chopra 9283da7a37aSMintz, Yuval return qed_eth_rxq_start_ramrod(p_hwfn, p_cid, 929cee4d264SManish Chopra bd_max_bytes, 930cee4d264SManish Chopra bd_chain_phys_addr, 9313da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size); 9323da7a37aSMintz, Yuval } 933cee4d264SManish Chopra 9343da7a37aSMintz, Yuval static int 9353da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn, 9363da7a37aSMintz, Yuval u16 opaque_fid, 9373da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 9383da7a37aSMintz, Yuval u16 bd_max_bytes, 9393da7a37aSMintz, Yuval dma_addr_t bd_chain_phys_addr, 9403da7a37aSMintz, Yuval dma_addr_t cqe_pbl_addr, 9413da7a37aSMintz, Yuval u16 cqe_pbl_size, 9423da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *p_ret_params) 9433da7a37aSMintz, Yuval { 9443da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 9453da7a37aSMintz, Yuval int rc; 9463da7a37aSMintz, Yuval 9473da7a37aSMintz, Yuval /* Allocate a CID for the queue */ 948007bc371SMintz, Yuval p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params); 9493da7a37aSMintz, Yuval if (!p_cid) 9503da7a37aSMintz, Yuval return -ENOMEM; 9513da7a37aSMintz, Yuval 9523da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 9533da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid, 9543da7a37aSMintz, Yuval bd_max_bytes, 9553da7a37aSMintz, Yuval bd_chain_phys_addr, 9563da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, 9573da7a37aSMintz, Yuval &p_ret_params->p_prod); 9583da7a37aSMintz, Yuval } else { 9593da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_start(p_hwfn, p_cid, 9603da7a37aSMintz, Yuval bd_max_bytes, 9613da7a37aSMintz, Yuval bd_chain_phys_addr, 9623da7a37aSMintz, Yuval cqe_pbl_addr, 9633da7a37aSMintz, Yuval cqe_pbl_size, &p_ret_params->p_prod); 9643da7a37aSMintz, Yuval } 9653da7a37aSMintz, Yuval 9663da7a37aSMintz, Yuval /* Provide the caller with a reference to as handler */ 9671a635e48SYuval Mintz if (rc) 9683da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 9693da7a37aSMintz, Yuval else 9703da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 971cee4d264SManish Chopra 972cee4d264SManish Chopra return rc; 973cee4d264SManish Chopra } 974cee4d264SManish Chopra 97517b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, 9763da7a37aSMintz, Yuval void **pp_rxq_handles, 97717b235c1SYuval Mintz u8 num_rxqs, 97817b235c1SYuval Mintz u8 complete_cqe_flg, 97917b235c1SYuval Mintz u8 complete_event_flg, 98017b235c1SYuval Mintz enum spq_mode comp_mode, 98117b235c1SYuval Mintz struct qed_spq_comp_cb *p_comp_data) 98217b235c1SYuval Mintz { 98317b235c1SYuval Mintz struct rx_queue_update_ramrod_data *p_ramrod = NULL; 98417b235c1SYuval Mintz struct qed_spq_entry *p_ent = NULL; 98517b235c1SYuval Mintz struct qed_sp_init_data init_data; 9863da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 98717b235c1SYuval Mintz int rc = -EINVAL; 98817b235c1SYuval Mintz u8 i; 98917b235c1SYuval Mintz 99017b235c1SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 99117b235c1SYuval Mintz init_data.comp_mode = comp_mode; 99217b235c1SYuval Mintz init_data.p_comp_data = p_comp_data; 99317b235c1SYuval Mintz 99417b235c1SYuval Mintz for (i = 0; i < num_rxqs; i++) { 9953da7a37aSMintz, Yuval p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i]; 99617b235c1SYuval Mintz 99717b235c1SYuval Mintz /* Get SPQ entry */ 9983da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 9993da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 100017b235c1SYuval Mintz 100117b235c1SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 100217b235c1SYuval Mintz ETH_RAMROD_RX_QUEUE_UPDATE, 100317b235c1SYuval Mintz PROTOCOLID_ETH, &init_data); 100417b235c1SYuval Mintz if (rc) 100517b235c1SYuval Mintz return rc; 100617b235c1SYuval Mintz 100717b235c1SYuval Mintz p_ramrod = &p_ent->ramrod.rx_queue_update; 10083da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 100917b235c1SYuval Mintz 10103da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 101117b235c1SYuval Mintz p_ramrod->complete_cqe_flg = complete_cqe_flg; 101217b235c1SYuval Mintz p_ramrod->complete_event_flg = complete_event_flg; 101317b235c1SYuval Mintz 101417b235c1SYuval Mintz rc = qed_spq_post(p_hwfn, p_ent, NULL); 101517b235c1SYuval Mintz if (rc) 101617b235c1SYuval Mintz return rc; 101717b235c1SYuval Mintz } 101817b235c1SYuval Mintz 101917b235c1SYuval Mintz return rc; 102017b235c1SYuval Mintz } 102117b235c1SYuval Mintz 10223da7a37aSMintz, Yuval static int 10233da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn, 10243da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 10253da7a37aSMintz, Yuval bool b_eq_completion_only, bool b_cqe_completion) 1026cee4d264SManish Chopra { 1027cee4d264SManish Chopra struct rx_queue_stop_ramrod_data *p_ramrod = NULL; 1028cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 102906f56b81SYuval Mintz struct qed_sp_init_data init_data; 10303da7a37aSMintz, Yuval int rc; 1031cee4d264SManish Chopra 103206f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 10333da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 10343da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 103506f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1036cee4d264SManish Chopra 1037cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1038cee4d264SManish Chopra ETH_RAMROD_RX_QUEUE_STOP, 103906f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1040cee4d264SManish Chopra if (rc) 1041cee4d264SManish Chopra return rc; 1042cee4d264SManish Chopra 1043cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.rx_queue_stop; 10443da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 10453da7a37aSMintz, Yuval p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); 1046cee4d264SManish Chopra 1047cee4d264SManish Chopra /* Cleaning the queue requires the completion to arrive there. 1048cee4d264SManish Chopra * In addition, VFs require the answer to come as eqe to PF. 1049cee4d264SManish Chopra */ 10503946497aSMintz, Yuval p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) && 10513da7a37aSMintz, Yuval !b_eq_completion_only) || 10523da7a37aSMintz, Yuval b_cqe_completion; 10533946497aSMintz, Yuval p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) || 10543946497aSMintz, Yuval b_eq_completion_only; 1055cee4d264SManish Chopra 10563da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 1057cee4d264SManish Chopra } 1058cee4d264SManish Chopra 10593da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, 10603da7a37aSMintz, Yuval void *p_rxq, 10613da7a37aSMintz, Yuval bool eq_completion_only, bool cqe_completion) 10623da7a37aSMintz, Yuval { 10633da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq; 10643da7a37aSMintz, Yuval int rc = -EINVAL; 10653da7a37aSMintz, Yuval 10663da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 10673da7a37aSMintz, Yuval rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid, 10683da7a37aSMintz, Yuval eq_completion_only, 10693da7a37aSMintz, Yuval cqe_completion); 10703da7a37aSMintz, Yuval else 10713da7a37aSMintz, Yuval rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion); 10723da7a37aSMintz, Yuval 10733da7a37aSMintz, Yuval if (!rc) 10743da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 10753da7a37aSMintz, Yuval return rc; 10763da7a37aSMintz, Yuval } 10773da7a37aSMintz, Yuval 10783da7a37aSMintz, Yuval int 10793da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 10803da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 10813da7a37aSMintz, Yuval dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id) 1082cee4d264SManish Chopra { 1083cee4d264SManish Chopra struct tx_queue_start_ramrod_data *p_ramrod = NULL; 1084cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 108506f56b81SYuval Mintz struct qed_sp_init_data init_data; 1086cee4d264SManish Chopra int rc = -EINVAL; 1087351a4dedSYuval Mintz 108806f56b81SYuval Mintz /* Get SPQ entry */ 108906f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 10903da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 10913da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 109206f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1093cee4d264SManish Chopra 109406f56b81SYuval Mintz rc = qed_sp_init_request(p_hwfn, &p_ent, 1095cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_START, 109606f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1097cee4d264SManish Chopra if (rc) 1098cee4d264SManish Chopra return rc; 1099cee4d264SManish Chopra 1100cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.tx_queue_start; 11013da7a37aSMintz, Yuval p_ramrod->vport_id = p_cid->abs.vport_id; 1102cee4d264SManish Chopra 1103f604b17dSMintz, Yuval p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); 1104f604b17dSMintz, Yuval p_ramrod->sb_index = p_cid->sb_idx; 11053da7a37aSMintz, Yuval p_ramrod->stats_counter_id = p_cid->abs.stats_id; 1106cee4d264SManish Chopra 11073da7a37aSMintz, Yuval p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id); 11083da7a37aSMintz, Yuval p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id); 11091a635e48SYuval Mintz 1110cee4d264SManish Chopra p_ramrod->pbl_size = cpu_to_le16(pbl_size); 111194494598SYuval Mintz DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 1112cee4d264SManish Chopra 1113cee4d264SManish Chopra p_ramrod->qm_pq_id = cpu_to_le16(pq_id); 1114cee4d264SManish Chopra 1115cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1116cee4d264SManish Chopra } 1117cee4d264SManish Chopra 1118cee4d264SManish Chopra static int 11193da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn, 11203da7a37aSMintz, Yuval struct qed_queue_cid *p_cid, 11213da7a37aSMintz, Yuval u8 tc, 1122cee4d264SManish Chopra dma_addr_t pbl_addr, 1123dacd88d6SYuval Mintz u16 pbl_size, void __iomem **pp_doorbell) 1124cee4d264SManish Chopra { 1125cee4d264SManish Chopra int rc; 1126cee4d264SManish Chopra 1127cee4d264SManish Chopra 11283da7a37aSMintz, Yuval rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid, 11293da7a37aSMintz, Yuval pbl_addr, pbl_size, 1130b5a9ee7cSAriel Elior qed_get_cm_pq_idx_mcos(p_hwfn, tc)); 11313da7a37aSMintz, Yuval if (rc) 1132cee4d264SManish Chopra return rc; 11333da7a37aSMintz, Yuval 11343da7a37aSMintz, Yuval /* Provide the caller with the necessary return values */ 11353da7a37aSMintz, Yuval *pp_doorbell = p_hwfn->doorbells + 11363da7a37aSMintz, Yuval qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY); 11373da7a37aSMintz, Yuval 11383da7a37aSMintz, Yuval return 0; 1139cee4d264SManish Chopra } 1140cee4d264SManish Chopra 11413da7a37aSMintz, Yuval static int 11423da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn, 11433da7a37aSMintz, Yuval u16 opaque_fid, 11443da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 11453da7a37aSMintz, Yuval u8 tc, 11463da7a37aSMintz, Yuval dma_addr_t pbl_addr, 11473da7a37aSMintz, Yuval u16 pbl_size, 11483da7a37aSMintz, Yuval struct qed_txq_start_ret_params *p_ret_params) 11493da7a37aSMintz, Yuval { 11503da7a37aSMintz, Yuval struct qed_queue_cid *p_cid; 11513da7a37aSMintz, Yuval int rc; 1152cee4d264SManish Chopra 1153007bc371SMintz, Yuval p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params); 11543da7a37aSMintz, Yuval if (!p_cid) 11553da7a37aSMintz, Yuval return -EINVAL; 1156cee4d264SManish Chopra 11573da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 11583da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc, 11593da7a37aSMintz, Yuval pbl_addr, pbl_size, 11603da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 11613da7a37aSMintz, Yuval else 11623da7a37aSMintz, Yuval rc = qed_vf_pf_txq_start(p_hwfn, p_cid, 11633da7a37aSMintz, Yuval pbl_addr, pbl_size, 11643da7a37aSMintz, Yuval &p_ret_params->p_doorbell); 1165cee4d264SManish Chopra 1166cee4d264SManish Chopra if (rc) 11673da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 11683da7a37aSMintz, Yuval else 11693da7a37aSMintz, Yuval p_ret_params->p_handle = (void *)p_cid; 1170cee4d264SManish Chopra 1171cee4d264SManish Chopra return rc; 1172cee4d264SManish Chopra } 1173cee4d264SManish Chopra 11743da7a37aSMintz, Yuval static int 11753da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid) 1176cee4d264SManish Chopra { 1177cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 117806f56b81SYuval Mintz struct qed_sp_init_data init_data; 11793da7a37aSMintz, Yuval int rc; 1180cee4d264SManish Chopra 118106f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 11823da7a37aSMintz, Yuval init_data.cid = p_cid->cid; 11833da7a37aSMintz, Yuval init_data.opaque_fid = p_cid->opaque_fid; 118406f56b81SYuval Mintz init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1185cee4d264SManish Chopra 1186cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1187cee4d264SManish Chopra ETH_RAMROD_TX_QUEUE_STOP, 118806f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1189cee4d264SManish Chopra if (rc) 1190cee4d264SManish Chopra return rc; 1191cee4d264SManish Chopra 11923da7a37aSMintz, Yuval return qed_spq_post(p_hwfn, p_ent, NULL); 11933da7a37aSMintz, Yuval } 1194cee4d264SManish Chopra 11953da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle) 11963da7a37aSMintz, Yuval { 11973da7a37aSMintz, Yuval struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle; 11983da7a37aSMintz, Yuval int rc; 11993da7a37aSMintz, Yuval 12003da7a37aSMintz, Yuval if (IS_PF(p_hwfn->cdev)) 12013da7a37aSMintz, Yuval rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid); 12023da7a37aSMintz, Yuval else 12033da7a37aSMintz, Yuval rc = qed_vf_pf_txq_stop(p_hwfn, p_cid); 12043da7a37aSMintz, Yuval 12053da7a37aSMintz, Yuval if (!rc) 12063da7a37aSMintz, Yuval qed_eth_queue_cid_release(p_hwfn, p_cid); 12073da7a37aSMintz, Yuval return rc; 1208cee4d264SManish Chopra } 1209cee4d264SManish Chopra 12101a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode) 1211cee4d264SManish Chopra { 1212cee4d264SManish Chopra enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 1213cee4d264SManish Chopra 1214cee4d264SManish Chopra switch (opcode) { 1215cee4d264SManish Chopra case QED_FILTER_ADD: 1216cee4d264SManish Chopra action = ETH_FILTER_ACTION_ADD; 1217cee4d264SManish Chopra break; 1218cee4d264SManish Chopra case QED_FILTER_REMOVE: 1219cee4d264SManish Chopra action = ETH_FILTER_ACTION_REMOVE; 1220cee4d264SManish Chopra break; 1221cee4d264SManish Chopra case QED_FILTER_FLUSH: 1222fc48b7a6SYuval Mintz action = ETH_FILTER_ACTION_REMOVE_ALL; 1223cee4d264SManish Chopra break; 1224cee4d264SManish Chopra default: 1225cee4d264SManish Chopra action = MAX_ETH_FILTER_ACTION; 1226cee4d264SManish Chopra } 1227cee4d264SManish Chopra 1228cee4d264SManish Chopra return action; 1229cee4d264SManish Chopra } 1230cee4d264SManish Chopra 1231cee4d264SManish Chopra static void qed_set_fw_mac_addr(__le16 *fw_msb, 1232cee4d264SManish Chopra __le16 *fw_mid, 1233cee4d264SManish Chopra __le16 *fw_lsb, 1234cee4d264SManish Chopra u8 *mac) 1235cee4d264SManish Chopra { 1236cee4d264SManish Chopra ((u8 *)fw_msb)[0] = mac[1]; 1237cee4d264SManish Chopra ((u8 *)fw_msb)[1] = mac[0]; 1238cee4d264SManish Chopra ((u8 *)fw_mid)[0] = mac[3]; 1239cee4d264SManish Chopra ((u8 *)fw_mid)[1] = mac[2]; 1240cee4d264SManish Chopra ((u8 *)fw_lsb)[0] = mac[5]; 1241cee4d264SManish Chopra ((u8 *)fw_lsb)[1] = mac[4]; 1242cee4d264SManish Chopra } 1243cee4d264SManish Chopra 1244cee4d264SManish Chopra static int 1245cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn, 1246cee4d264SManish Chopra u16 opaque_fid, 1247cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1248cee4d264SManish Chopra struct vport_filter_update_ramrod_data **pp_ramrod, 1249cee4d264SManish Chopra struct qed_spq_entry **pp_ent, 1250cee4d264SManish Chopra enum spq_mode comp_mode, 1251cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1252cee4d264SManish Chopra { 1253cee4d264SManish Chopra u8 vport_to_add_to = 0, vport_to_remove_from = 0; 1254cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod; 1255cee4d264SManish Chopra struct eth_filter_cmd *p_first_filter; 1256cee4d264SManish Chopra struct eth_filter_cmd *p_second_filter; 125706f56b81SYuval Mintz struct qed_sp_init_data init_data; 1258cee4d264SManish Chopra enum eth_filter_action action; 1259cee4d264SManish Chopra int rc; 1260cee4d264SManish Chopra 1261cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1262cee4d264SManish Chopra &vport_to_remove_from); 1263cee4d264SManish Chopra if (rc) 1264cee4d264SManish Chopra return rc; 1265cee4d264SManish Chopra 1266cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1267cee4d264SManish Chopra &vport_to_add_to); 1268cee4d264SManish Chopra if (rc) 1269cee4d264SManish Chopra return rc; 1270cee4d264SManish Chopra 127106f56b81SYuval Mintz /* Get SPQ entry */ 127206f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 127306f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 127406f56b81SYuval Mintz init_data.opaque_fid = opaque_fid; 127506f56b81SYuval Mintz init_data.comp_mode = comp_mode; 127606f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1277cee4d264SManish Chopra 1278cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, pp_ent, 1279cee4d264SManish Chopra ETH_RAMROD_FILTERS_UPDATE, 128006f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1281cee4d264SManish Chopra if (rc) 1282cee4d264SManish Chopra return rc; 1283cee4d264SManish Chopra 1284cee4d264SManish Chopra *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 1285cee4d264SManish Chopra p_ramrod = *pp_ramrod; 1286cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 1287cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 1288cee4d264SManish Chopra 1289cee4d264SManish Chopra switch (p_filter_cmd->opcode) { 1290fc48b7a6SYuval Mintz case QED_FILTER_REPLACE: 1291cee4d264SManish Chopra case QED_FILTER_MOVE: 1292cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 1293cee4d264SManish Chopra default: 1294cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 1295cee4d264SManish Chopra } 1296cee4d264SManish Chopra 1297cee4d264SManish Chopra p_first_filter = &p_ramrod->filter_cmds[0]; 1298cee4d264SManish Chopra p_second_filter = &p_ramrod->filter_cmds[1]; 1299cee4d264SManish Chopra 1300cee4d264SManish Chopra switch (p_filter_cmd->type) { 1301cee4d264SManish Chopra case QED_FILTER_MAC: 1302cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 1303cee4d264SManish Chopra case QED_FILTER_VLAN: 1304cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 1305cee4d264SManish Chopra case QED_FILTER_MAC_VLAN: 1306cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 1307cee4d264SManish Chopra case QED_FILTER_INNER_MAC: 1308cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 1309cee4d264SManish Chopra case QED_FILTER_INNER_VLAN: 1310cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 1311cee4d264SManish Chopra case QED_FILTER_INNER_PAIR: 1312cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 1313cee4d264SManish Chopra case QED_FILTER_INNER_MAC_VNI_PAIR: 1314cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 1315cee4d264SManish Chopra break; 1316cee4d264SManish Chopra case QED_FILTER_MAC_VNI_PAIR: 1317cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 1318cee4d264SManish Chopra case QED_FILTER_VNI: 1319cee4d264SManish Chopra p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 1320cee4d264SManish Chopra } 1321cee4d264SManish Chopra 1322cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 1323cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1324cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 1325cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 1326cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1327cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { 1328cee4d264SManish Chopra qed_set_fw_mac_addr(&p_first_filter->mac_msb, 1329cee4d264SManish Chopra &p_first_filter->mac_mid, 1330cee4d264SManish Chopra &p_first_filter->mac_lsb, 1331cee4d264SManish Chopra (u8 *)p_filter_cmd->mac); 1332cee4d264SManish Chopra } 1333cee4d264SManish Chopra 1334cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 1335cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1336cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 1337cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 1338cee4d264SManish Chopra p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); 1339cee4d264SManish Chopra 1340cee4d264SManish Chopra if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1341cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 1342cee4d264SManish Chopra (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 1343cee4d264SManish Chopra p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); 1344cee4d264SManish Chopra 1345cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_MOVE) { 1346cee4d264SManish Chopra p_second_filter->type = p_first_filter->type; 1347cee4d264SManish Chopra p_second_filter->mac_msb = p_first_filter->mac_msb; 1348cee4d264SManish Chopra p_second_filter->mac_mid = p_first_filter->mac_mid; 1349cee4d264SManish Chopra p_second_filter->mac_lsb = p_first_filter->mac_lsb; 1350cee4d264SManish Chopra p_second_filter->vlan_id = p_first_filter->vlan_id; 1351cee4d264SManish Chopra p_second_filter->vni = p_first_filter->vni; 1352cee4d264SManish Chopra 1353cee4d264SManish Chopra p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 1354cee4d264SManish Chopra 1355cee4d264SManish Chopra p_first_filter->vport_id = vport_to_remove_from; 1356cee4d264SManish Chopra 1357cee4d264SManish Chopra p_second_filter->action = ETH_FILTER_ACTION_ADD; 1358cee4d264SManish Chopra p_second_filter->vport_id = vport_to_add_to; 1359fc48b7a6SYuval Mintz } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { 1360fc48b7a6SYuval Mintz p_first_filter->vport_id = vport_to_add_to; 1361fc48b7a6SYuval Mintz memcpy(p_second_filter, p_first_filter, 1362fc48b7a6SYuval Mintz sizeof(*p_second_filter)); 1363fc48b7a6SYuval Mintz p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 1364fc48b7a6SYuval Mintz p_second_filter->action = ETH_FILTER_ACTION_ADD; 1365cee4d264SManish Chopra } else { 1366cee4d264SManish Chopra action = qed_filter_action(p_filter_cmd->opcode); 1367cee4d264SManish Chopra 1368cee4d264SManish Chopra if (action == MAX_ETH_FILTER_ACTION) { 1369cee4d264SManish Chopra DP_NOTICE(p_hwfn, 1370cee4d264SManish Chopra "%d is not supported yet\n", 1371cee4d264SManish Chopra p_filter_cmd->opcode); 1372cee4d264SManish Chopra return -EINVAL; 1373cee4d264SManish Chopra } 1374cee4d264SManish Chopra 1375cee4d264SManish Chopra p_first_filter->action = action; 1376cee4d264SManish Chopra p_first_filter->vport_id = (p_filter_cmd->opcode == 1377cee4d264SManish Chopra QED_FILTER_REMOVE) ? 1378cee4d264SManish Chopra vport_to_remove_from : 1379cee4d264SManish Chopra vport_to_add_to; 1380cee4d264SManish Chopra } 1381cee4d264SManish Chopra 1382cee4d264SManish Chopra return 0; 1383cee4d264SManish Chopra } 1384cee4d264SManish Chopra 1385dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, 1386cee4d264SManish Chopra u16 opaque_fid, 1387cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1388cee4d264SManish Chopra enum spq_mode comp_mode, 1389cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1390cee4d264SManish Chopra { 1391cee4d264SManish Chopra struct vport_filter_update_ramrod_data *p_ramrod = NULL; 1392cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 1393cee4d264SManish Chopra struct eth_filter_cmd_header *p_header; 1394cee4d264SManish Chopra int rc; 1395cee4d264SManish Chopra 1396cee4d264SManish Chopra rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1397cee4d264SManish Chopra &p_ramrod, &p_ent, 1398cee4d264SManish Chopra comp_mode, p_comp_data); 13991a635e48SYuval Mintz if (rc) { 1400cee4d264SManish Chopra DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1401cee4d264SManish Chopra return rc; 1402cee4d264SManish Chopra } 1403cee4d264SManish Chopra p_header = &p_ramrod->filter_cmd_hdr; 1404cee4d264SManish Chopra p_header->assert_on_error = p_filter_cmd->assert_on_error; 1405cee4d264SManish Chopra 1406cee4d264SManish Chopra rc = qed_spq_post(p_hwfn, p_ent, NULL); 14071a635e48SYuval Mintz if (rc) { 14081a635e48SYuval Mintz DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc); 1409cee4d264SManish Chopra return rc; 1410cee4d264SManish Chopra } 1411cee4d264SManish Chopra 1412cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1413cee4d264SManish Chopra "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1414cee4d264SManish Chopra (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : 1415cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? 1416cee4d264SManish Chopra "REMOVE" : 1417cee4d264SManish Chopra ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? 1418cee4d264SManish Chopra "MOVE" : "REPLACE")), 1419cee4d264SManish Chopra (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : 1420cee4d264SManish Chopra ((p_filter_cmd->type == QED_FILTER_VLAN) ? 1421cee4d264SManish Chopra "VLAN" : "MAC & VLAN"), 1422cee4d264SManish Chopra p_ramrod->filter_cmd_hdr.cmd_cnt, 1423cee4d264SManish Chopra p_filter_cmd->is_rx_filter, 1424cee4d264SManish Chopra p_filter_cmd->is_tx_filter); 1425cee4d264SManish Chopra DP_VERBOSE(p_hwfn, QED_MSG_SP, 1426cee4d264SManish Chopra "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1427cee4d264SManish Chopra p_filter_cmd->vport_to_add_to, 1428cee4d264SManish Chopra p_filter_cmd->vport_to_remove_from, 1429cee4d264SManish Chopra p_filter_cmd->mac[0], 1430cee4d264SManish Chopra p_filter_cmd->mac[1], 1431cee4d264SManish Chopra p_filter_cmd->mac[2], 1432cee4d264SManish Chopra p_filter_cmd->mac[3], 1433cee4d264SManish Chopra p_filter_cmd->mac[4], 1434cee4d264SManish Chopra p_filter_cmd->mac[5], 1435cee4d264SManish Chopra p_filter_cmd->vlan); 1436cee4d264SManish Chopra 1437cee4d264SManish Chopra return 0; 1438cee4d264SManish Chopra } 1439cee4d264SManish Chopra 1440cee4d264SManish Chopra /******************************************************************************* 1441cee4d264SManish Chopra * Description: 1442cee4d264SManish Chopra * Calculates crc 32 on a buffer 1443cee4d264SManish Chopra * Note: crc32_length MUST be aligned to 8 1444cee4d264SManish Chopra * Return: 1445cee4d264SManish Chopra ******************************************************************************/ 1446cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet, 14471a635e48SYuval Mintz u32 crc32_length, u32 crc32_seed, u8 complement) 1448cee4d264SManish Chopra { 14491a635e48SYuval Mintz u32 byte = 0, bit = 0, crc32_result = crc32_seed; 14501a635e48SYuval Mintz u8 msb = 0, current_byte = 0; 1451cee4d264SManish Chopra 1452cee4d264SManish Chopra if ((!crc32_packet) || 1453cee4d264SManish Chopra (crc32_length == 0) || 1454cee4d264SManish Chopra ((crc32_length % 8) != 0)) 1455cee4d264SManish Chopra return crc32_result; 1456cee4d264SManish Chopra for (byte = 0; byte < crc32_length; byte++) { 1457cee4d264SManish Chopra current_byte = crc32_packet[byte]; 1458cee4d264SManish Chopra for (bit = 0; bit < 8; bit++) { 1459cee4d264SManish Chopra msb = (u8)(crc32_result >> 31); 1460cee4d264SManish Chopra crc32_result = crc32_result << 1; 1461cee4d264SManish Chopra if (msb != (0x1 & (current_byte >> bit))) { 1462cee4d264SManish Chopra crc32_result = crc32_result ^ CRC32_POLY; 1463cee4d264SManish Chopra crc32_result |= 1; /*crc32_result[0] = 1;*/ 1464cee4d264SManish Chopra } 1465cee4d264SManish Chopra } 1466cee4d264SManish Chopra } 1467cee4d264SManish Chopra return crc32_result; 1468cee4d264SManish Chopra } 1469cee4d264SManish Chopra 14701a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len) 1471cee4d264SManish Chopra { 1472cee4d264SManish Chopra u32 packet_buf[2] = { 0 }; 1473cee4d264SManish Chopra 1474cee4d264SManish Chopra memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); 1475cee4d264SManish Chopra return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); 1476cee4d264SManish Chopra } 1477cee4d264SManish Chopra 1478dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac) 1479cee4d264SManish Chopra { 1480cee4d264SManish Chopra u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, 1481cee4d264SManish Chopra mac, ETH_ALEN); 1482cee4d264SManish Chopra 1483cee4d264SManish Chopra return crc & 0xff; 1484cee4d264SManish Chopra } 1485cee4d264SManish Chopra 1486cee4d264SManish Chopra static int 1487cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, 1488cee4d264SManish Chopra u16 opaque_fid, 1489cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1490cee4d264SManish Chopra enum spq_mode comp_mode, 1491cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1492cee4d264SManish Chopra { 1493cee4d264SManish Chopra unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1494cee4d264SManish Chopra struct vport_update_ramrod_data *p_ramrod = NULL; 1495cee4d264SManish Chopra struct qed_spq_entry *p_ent = NULL; 149606f56b81SYuval Mintz struct qed_sp_init_data init_data; 1497cee4d264SManish Chopra u8 abs_vport_id = 0; 1498cee4d264SManish Chopra int rc, i; 1499cee4d264SManish Chopra 150083aeb933SYuval Mintz if (p_filter_cmd->opcode == QED_FILTER_ADD) 1501cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1502cee4d264SManish Chopra &abs_vport_id); 150383aeb933SYuval Mintz else 1504cee4d264SManish Chopra rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1505cee4d264SManish Chopra &abs_vport_id); 1506cee4d264SManish Chopra if (rc) 1507cee4d264SManish Chopra return rc; 1508cee4d264SManish Chopra 150906f56b81SYuval Mintz /* Get SPQ entry */ 151006f56b81SYuval Mintz memset(&init_data, 0, sizeof(init_data)); 151106f56b81SYuval Mintz init_data.cid = qed_spq_get_cid(p_hwfn); 151206f56b81SYuval Mintz init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 151306f56b81SYuval Mintz init_data.comp_mode = comp_mode; 151406f56b81SYuval Mintz init_data.p_comp_data = p_comp_data; 1515cee4d264SManish Chopra 1516cee4d264SManish Chopra rc = qed_sp_init_request(p_hwfn, &p_ent, 1517cee4d264SManish Chopra ETH_RAMROD_VPORT_UPDATE, 151806f56b81SYuval Mintz PROTOCOLID_ETH, &init_data); 1519cee4d264SManish Chopra if (rc) { 1520cee4d264SManish Chopra DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1521cee4d264SManish Chopra return rc; 1522cee4d264SManish Chopra } 1523cee4d264SManish Chopra 1524cee4d264SManish Chopra p_ramrod = &p_ent->ramrod.vport_update; 1525cee4d264SManish Chopra p_ramrod->common.update_approx_mcast_flg = 1; 1526cee4d264SManish Chopra 1527cee4d264SManish Chopra /* explicitly clear out the entire vector */ 1528cee4d264SManish Chopra memset(&p_ramrod->approx_mcast.bins, 0, 1529cee4d264SManish Chopra sizeof(p_ramrod->approx_mcast.bins)); 1530cee4d264SManish Chopra memset(bins, 0, sizeof(unsigned long) * 1531cee4d264SManish Chopra ETH_MULTICAST_MAC_BINS_IN_REGS); 1532cee4d264SManish Chopra /* filter ADD op is explicit set op and it removes 1533cee4d264SManish Chopra * any existing filters for the vport 1534cee4d264SManish Chopra */ 1535cee4d264SManish Chopra if (p_filter_cmd->opcode == QED_FILTER_ADD) { 1536cee4d264SManish Chopra for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 1537cee4d264SManish Chopra u32 bit; 1538cee4d264SManish Chopra 1539cee4d264SManish Chopra bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); 1540cee4d264SManish Chopra __set_bit(bit, bins); 1541cee4d264SManish Chopra } 1542cee4d264SManish Chopra 1543cee4d264SManish Chopra /* Convert to correct endianity */ 1544cee4d264SManish Chopra for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 15451a635e48SYuval Mintz struct vport_update_ramrod_mcast *p_ramrod_bins; 1546cee4d264SManish Chopra u32 *p_bins = (u32 *)bins; 1547cee4d264SManish Chopra 15481a635e48SYuval Mintz p_ramrod_bins = &p_ramrod->approx_mcast; 15491a635e48SYuval Mintz p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]); 1550cee4d264SManish Chopra } 1551cee4d264SManish Chopra } 1552cee4d264SManish Chopra 1553cee4d264SManish Chopra p_ramrod->common.vport_id = abs_vport_id; 1554cee4d264SManish Chopra 1555cee4d264SManish Chopra return qed_spq_post(p_hwfn, p_ent, NULL); 1556cee4d264SManish Chopra } 1557cee4d264SManish Chopra 1558dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev, 1559cee4d264SManish Chopra struct qed_filter_mcast *p_filter_cmd, 1560cee4d264SManish Chopra enum spq_mode comp_mode, 1561cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1562cee4d264SManish Chopra { 1563cee4d264SManish Chopra int rc = 0; 1564cee4d264SManish Chopra int i; 1565cee4d264SManish Chopra 1566cee4d264SManish Chopra /* only ADD and REMOVE operations are supported for multi-cast */ 1567cee4d264SManish Chopra if ((p_filter_cmd->opcode != QED_FILTER_ADD && 1568cee4d264SManish Chopra (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || 1569cee4d264SManish Chopra (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) 1570cee4d264SManish Chopra return -EINVAL; 1571cee4d264SManish Chopra 1572cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1573cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1574cee4d264SManish Chopra 1575cee4d264SManish Chopra u16 opaque_fid; 1576cee4d264SManish Chopra 1577dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1578dacd88d6SYuval Mintz qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); 1579dacd88d6SYuval Mintz continue; 1580dacd88d6SYuval Mintz } 1581cee4d264SManish Chopra 1582cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1583cee4d264SManish Chopra 1584cee4d264SManish Chopra rc = qed_sp_eth_filter_mcast(p_hwfn, 1585cee4d264SManish Chopra opaque_fid, 1586cee4d264SManish Chopra p_filter_cmd, 15871a635e48SYuval Mintz comp_mode, p_comp_data); 1588cee4d264SManish Chopra } 1589cee4d264SManish Chopra return rc; 1590cee4d264SManish Chopra } 1591cee4d264SManish Chopra 1592cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev, 1593cee4d264SManish Chopra struct qed_filter_ucast *p_filter_cmd, 1594cee4d264SManish Chopra enum spq_mode comp_mode, 1595cee4d264SManish Chopra struct qed_spq_comp_cb *p_comp_data) 1596cee4d264SManish Chopra { 1597cee4d264SManish Chopra int rc = 0; 1598cee4d264SManish Chopra int i; 1599cee4d264SManish Chopra 1600cee4d264SManish Chopra for_each_hwfn(cdev, i) { 1601cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1602cee4d264SManish Chopra u16 opaque_fid; 1603cee4d264SManish Chopra 1604dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1605dacd88d6SYuval Mintz rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); 1606dacd88d6SYuval Mintz continue; 1607dacd88d6SYuval Mintz } 1608cee4d264SManish Chopra 1609cee4d264SManish Chopra opaque_fid = p_hwfn->hw_info.opaque_fid; 1610cee4d264SManish Chopra 1611cee4d264SManish Chopra rc = qed_sp_eth_filter_ucast(p_hwfn, 1612cee4d264SManish Chopra opaque_fid, 1613cee4d264SManish Chopra p_filter_cmd, 16141a635e48SYuval Mintz comp_mode, p_comp_data); 16151a635e48SYuval Mintz if (rc) 1616dacd88d6SYuval Mintz break; 1617cee4d264SManish Chopra } 1618cee4d264SManish Chopra 1619cee4d264SManish Chopra return rc; 1620cee4d264SManish Chopra } 1621cee4d264SManish Chopra 162286622ee7SYuval Mintz /* Statistics related code */ 162386622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, 162486622ee7SYuval Mintz u32 *p_addr, 1625dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 162686622ee7SYuval Mintz { 1627dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 162886622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_PSDM_RAM + 162986622ee7SYuval Mintz PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 163086622ee7SYuval Mintz *p_len = sizeof(struct eth_pstorm_per_queue_stat); 1631dacd88d6SYuval Mintz } else { 1632dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1633dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1634dacd88d6SYuval Mintz 1635dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.pstats.address; 1636dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.pstats.len; 1637dacd88d6SYuval Mintz } 163886622ee7SYuval Mintz } 163986622ee7SYuval Mintz 164086622ee7SYuval Mintz static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, 164186622ee7SYuval Mintz struct qed_ptt *p_ptt, 164286622ee7SYuval Mintz struct qed_eth_stats *p_stats, 164386622ee7SYuval Mintz u16 statistics_bin) 164486622ee7SYuval Mintz { 164586622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 164686622ee7SYuval Mintz u32 pstats_addr = 0, pstats_len = 0; 164786622ee7SYuval Mintz 164886622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 164986622ee7SYuval Mintz statistics_bin); 165086622ee7SYuval Mintz 165186622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 1652dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); 165386622ee7SYuval Mintz 16549c79ddaaSMintz, Yuval p_stats->common.tx_ucast_bytes += 16559c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_bytes); 16569c79ddaaSMintz, Yuval p_stats->common.tx_mcast_bytes += 16579c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_bytes); 16589c79ddaaSMintz, Yuval p_stats->common.tx_bcast_bytes += 16599c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_bytes); 16609c79ddaaSMintz, Yuval p_stats->common.tx_ucast_pkts += 16619c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_ucast_pkts); 16629c79ddaaSMintz, Yuval p_stats->common.tx_mcast_pkts += 16639c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_mcast_pkts); 16649c79ddaaSMintz, Yuval p_stats->common.tx_bcast_pkts += 16659c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.sent_bcast_pkts); 16669c79ddaaSMintz, Yuval p_stats->common.tx_err_drop_pkts += 16679c79ddaaSMintz, Yuval HILO_64_REGPAIR(pstats.error_drop_pkts); 166886622ee7SYuval Mintz } 166986622ee7SYuval Mintz 167086622ee7SYuval Mintz static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, 167186622ee7SYuval Mintz struct qed_ptt *p_ptt, 167286622ee7SYuval Mintz struct qed_eth_stats *p_stats, 167386622ee7SYuval Mintz u16 statistics_bin) 167486622ee7SYuval Mintz { 167586622ee7SYuval Mintz struct tstorm_per_port_stat tstats; 1676dacd88d6SYuval Mintz u32 tstats_addr, tstats_len; 167786622ee7SYuval Mintz 1678dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1679dacd88d6SYuval Mintz tstats_addr = BAR0_MAP_REG_TSDM_RAM + 1680dacd88d6SYuval Mintz TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 1681dacd88d6SYuval Mintz tstats_len = sizeof(struct tstorm_per_port_stat); 1682dacd88d6SYuval Mintz } else { 1683dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1684dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1685dacd88d6SYuval Mintz 1686dacd88d6SYuval Mintz tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; 1687dacd88d6SYuval Mintz tstats_len = p_resp->pfdev_info.stats_info.tstats.len; 1688dacd88d6SYuval Mintz } 168986622ee7SYuval Mintz 169086622ee7SYuval Mintz memset(&tstats, 0, sizeof(tstats)); 1691dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); 169286622ee7SYuval Mintz 16939c79ddaaSMintz, Yuval p_stats->common.mftag_filter_discards += 169486622ee7SYuval Mintz HILO_64_REGPAIR(tstats.mftag_filter_discard); 16959c79ddaaSMintz, Yuval p_stats->common.mac_filter_discards += 169686622ee7SYuval Mintz HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 169786622ee7SYuval Mintz } 169886622ee7SYuval Mintz 169986622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, 170086622ee7SYuval Mintz u32 *p_addr, 1701dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 170286622ee7SYuval Mintz { 1703dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 170486622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_USDM_RAM + 170586622ee7SYuval Mintz USTORM_QUEUE_STAT_OFFSET(statistics_bin); 170686622ee7SYuval Mintz *p_len = sizeof(struct eth_ustorm_per_queue_stat); 1707dacd88d6SYuval Mintz } else { 1708dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1709dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1710dacd88d6SYuval Mintz 1711dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.ustats.address; 1712dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.ustats.len; 1713dacd88d6SYuval Mintz } 171486622ee7SYuval Mintz } 171586622ee7SYuval Mintz 171686622ee7SYuval Mintz static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, 171786622ee7SYuval Mintz struct qed_ptt *p_ptt, 171886622ee7SYuval Mintz struct qed_eth_stats *p_stats, 171986622ee7SYuval Mintz u16 statistics_bin) 172086622ee7SYuval Mintz { 172186622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 172286622ee7SYuval Mintz u32 ustats_addr = 0, ustats_len = 0; 172386622ee7SYuval Mintz 172486622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 172586622ee7SYuval Mintz statistics_bin); 172686622ee7SYuval Mintz 172786622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 1728dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); 172986622ee7SYuval Mintz 17309c79ddaaSMintz, Yuval p_stats->common.rx_ucast_bytes += 17319c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 17329c79ddaaSMintz, Yuval p_stats->common.rx_mcast_bytes += 17339c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 17349c79ddaaSMintz, Yuval p_stats->common.rx_bcast_bytes += 17359c79ddaaSMintz, Yuval HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 17369c79ddaaSMintz, Yuval p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 17379c79ddaaSMintz, Yuval p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 17389c79ddaaSMintz, Yuval p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 173986622ee7SYuval Mintz } 174086622ee7SYuval Mintz 174186622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, 174286622ee7SYuval Mintz u32 *p_addr, 1743dacd88d6SYuval Mintz u32 *p_len, u16 statistics_bin) 174486622ee7SYuval Mintz { 1745dacd88d6SYuval Mintz if (IS_PF(p_hwfn->cdev)) { 174686622ee7SYuval Mintz *p_addr = BAR0_MAP_REG_MSDM_RAM + 174786622ee7SYuval Mintz MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 174886622ee7SYuval Mintz *p_len = sizeof(struct eth_mstorm_per_queue_stat); 1749dacd88d6SYuval Mintz } else { 1750dacd88d6SYuval Mintz struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; 1751dacd88d6SYuval Mintz struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1752dacd88d6SYuval Mintz 1753dacd88d6SYuval Mintz *p_addr = p_resp->pfdev_info.stats_info.mstats.address; 1754dacd88d6SYuval Mintz *p_len = p_resp->pfdev_info.stats_info.mstats.len; 1755dacd88d6SYuval Mintz } 175686622ee7SYuval Mintz } 175786622ee7SYuval Mintz 175886622ee7SYuval Mintz static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, 175986622ee7SYuval Mintz struct qed_ptt *p_ptt, 176086622ee7SYuval Mintz struct qed_eth_stats *p_stats, 176186622ee7SYuval Mintz u16 statistics_bin) 176286622ee7SYuval Mintz { 176386622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 176486622ee7SYuval Mintz u32 mstats_addr = 0, mstats_len = 0; 176586622ee7SYuval Mintz 176686622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 176786622ee7SYuval Mintz statistics_bin); 176886622ee7SYuval Mintz 176986622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 1770dacd88d6SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); 177186622ee7SYuval Mintz 17729c79ddaaSMintz, Yuval p_stats->common.no_buff_discards += 17739c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.no_buff_discard); 17749c79ddaaSMintz, Yuval p_stats->common.packet_too_big_discard += 177586622ee7SYuval Mintz HILO_64_REGPAIR(mstats.packet_too_big_discard); 17769c79ddaaSMintz, Yuval p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); 17779c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_pkts += 177886622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 17799c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_events += 178086622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_events); 17819c79ddaaSMintz, Yuval p_stats->common.tpa_aborts_num += 17829c79ddaaSMintz, Yuval HILO_64_REGPAIR(mstats.tpa_aborts_num); 17839c79ddaaSMintz, Yuval p_stats->common.tpa_coalesced_bytes += 178486622ee7SYuval Mintz HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 178586622ee7SYuval Mintz } 178686622ee7SYuval Mintz 178786622ee7SYuval Mintz static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, 178886622ee7SYuval Mintz struct qed_ptt *p_ptt, 178986622ee7SYuval Mintz struct qed_eth_stats *p_stats) 179086622ee7SYuval Mintz { 17919c79ddaaSMintz, Yuval struct qed_eth_stats_common *p_common = &p_stats->common; 179286622ee7SYuval Mintz struct port_stats port_stats; 179386622ee7SYuval Mintz int j; 179486622ee7SYuval Mintz 179586622ee7SYuval Mintz memset(&port_stats, 0, sizeof(port_stats)); 179686622ee7SYuval Mintz 179786622ee7SYuval Mintz qed_memcpy_from(p_hwfn, p_ptt, &port_stats, 179886622ee7SYuval Mintz p_hwfn->mcp_info->port_addr + 179986622ee7SYuval Mintz offsetof(struct public_port, stats), 180086622ee7SYuval Mintz sizeof(port_stats)); 180186622ee7SYuval Mintz 18029c79ddaaSMintz, Yuval p_common->rx_64_byte_packets += port_stats.eth.r64; 18039c79ddaaSMintz, Yuval p_common->rx_65_to_127_byte_packets += port_stats.eth.r127; 18049c79ddaaSMintz, Yuval p_common->rx_128_to_255_byte_packets += port_stats.eth.r255; 18059c79ddaaSMintz, Yuval p_common->rx_256_to_511_byte_packets += port_stats.eth.r511; 18069c79ddaaSMintz, Yuval p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023; 18079c79ddaaSMintz, Yuval p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; 18089c79ddaaSMintz, Yuval p_common->rx_crc_errors += port_stats.eth.rfcs; 18099c79ddaaSMintz, Yuval p_common->rx_mac_crtl_frames += port_stats.eth.rxcf; 18109c79ddaaSMintz, Yuval p_common->rx_pause_frames += port_stats.eth.rxpf; 18119c79ddaaSMintz, Yuval p_common->rx_pfc_frames += port_stats.eth.rxpp; 18129c79ddaaSMintz, Yuval p_common->rx_align_errors += port_stats.eth.raln; 18139c79ddaaSMintz, Yuval p_common->rx_carrier_errors += port_stats.eth.rfcr; 18149c79ddaaSMintz, Yuval p_common->rx_oversize_packets += port_stats.eth.rovr; 18159c79ddaaSMintz, Yuval p_common->rx_jabbers += port_stats.eth.rjbr; 18169c79ddaaSMintz, Yuval p_common->rx_undersize_packets += port_stats.eth.rund; 18179c79ddaaSMintz, Yuval p_common->rx_fragments += port_stats.eth.rfrg; 18189c79ddaaSMintz, Yuval p_common->tx_64_byte_packets += port_stats.eth.t64; 18199c79ddaaSMintz, Yuval p_common->tx_65_to_127_byte_packets += port_stats.eth.t127; 18209c79ddaaSMintz, Yuval p_common->tx_128_to_255_byte_packets += port_stats.eth.t255; 18219c79ddaaSMintz, Yuval p_common->tx_256_to_511_byte_packets += port_stats.eth.t511; 18229c79ddaaSMintz, Yuval p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023; 18239c79ddaaSMintz, Yuval p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; 18249c79ddaaSMintz, Yuval p_common->tx_pause_frames += port_stats.eth.txpf; 18259c79ddaaSMintz, Yuval p_common->tx_pfc_frames += port_stats.eth.txpp; 18269c79ddaaSMintz, Yuval p_common->rx_mac_bytes += port_stats.eth.rbyte; 18279c79ddaaSMintz, Yuval p_common->rx_mac_uc_packets += port_stats.eth.rxuca; 18289c79ddaaSMintz, Yuval p_common->rx_mac_mc_packets += port_stats.eth.rxmca; 18299c79ddaaSMintz, Yuval p_common->rx_mac_bc_packets += port_stats.eth.rxbca; 18309c79ddaaSMintz, Yuval p_common->rx_mac_frames_ok += port_stats.eth.rxpok; 18319c79ddaaSMintz, Yuval p_common->tx_mac_bytes += port_stats.eth.tbyte; 18329c79ddaaSMintz, Yuval p_common->tx_mac_uc_packets += port_stats.eth.txuca; 18339c79ddaaSMintz, Yuval p_common->tx_mac_mc_packets += port_stats.eth.txmca; 18349c79ddaaSMintz, Yuval p_common->tx_mac_bc_packets += port_stats.eth.txbca; 18359c79ddaaSMintz, Yuval p_common->tx_mac_ctrl_frames += port_stats.eth.txcf; 183686622ee7SYuval Mintz for (j = 0; j < 8; j++) { 18379c79ddaaSMintz, Yuval p_common->brb_truncates += port_stats.brb.brb_truncate[j]; 18389c79ddaaSMintz, Yuval p_common->brb_discards += port_stats.brb.brb_discard[j]; 18399c79ddaaSMintz, Yuval } 18409c79ddaaSMintz, Yuval 18419c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) { 18429c79ddaaSMintz, Yuval struct qed_eth_stats_bb *p_bb = &p_stats->bb; 18439c79ddaaSMintz, Yuval 18449c79ddaaSMintz, Yuval p_bb->rx_1519_to_1522_byte_packets += 18459c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r1522; 18469c79ddaaSMintz, Yuval p_bb->rx_1519_to_2047_byte_packets += 18479c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r2047; 18489c79ddaaSMintz, Yuval p_bb->rx_2048_to_4095_byte_packets += 18499c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r4095; 18509c79ddaaSMintz, Yuval p_bb->rx_4096_to_9216_byte_packets += 18519c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r9216; 18529c79ddaaSMintz, Yuval p_bb->rx_9217_to_16383_byte_packets += 18539c79ddaaSMintz, Yuval port_stats.eth.u0.bb0.r16383; 18549c79ddaaSMintz, Yuval p_bb->tx_1519_to_2047_byte_packets += 18559c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t2047; 18569c79ddaaSMintz, Yuval p_bb->tx_2048_to_4095_byte_packets += 18579c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t4095; 18589c79ddaaSMintz, Yuval p_bb->tx_4096_to_9216_byte_packets += 18599c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t9216; 18609c79ddaaSMintz, Yuval p_bb->tx_9217_to_16383_byte_packets += 18619c79ddaaSMintz, Yuval port_stats.eth.u1.bb1.t16383; 18629c79ddaaSMintz, Yuval p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec; 18639c79ddaaSMintz, Yuval p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl; 18649c79ddaaSMintz, Yuval } else { 18659c79ddaaSMintz, Yuval struct qed_eth_stats_ah *p_ah = &p_stats->ah; 18669c79ddaaSMintz, Yuval 18679c79ddaaSMintz, Yuval p_ah->rx_1519_to_max_byte_packets += 18689c79ddaaSMintz, Yuval port_stats.eth.u0.ah0.r1519_to_max; 18699c79ddaaSMintz, Yuval p_ah->tx_1519_to_max_byte_packets = 18709c79ddaaSMintz, Yuval port_stats.eth.u1.ah1.t1519_to_max; 187186622ee7SYuval Mintz } 187286622ee7SYuval Mintz } 187386622ee7SYuval Mintz 187486622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, 187586622ee7SYuval Mintz struct qed_ptt *p_ptt, 187686622ee7SYuval Mintz struct qed_eth_stats *stats, 1877dacd88d6SYuval Mintz u16 statistics_bin, bool b_get_port_stats) 187886622ee7SYuval Mintz { 187986622ee7SYuval Mintz __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 188086622ee7SYuval Mintz __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 188186622ee7SYuval Mintz __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); 188286622ee7SYuval Mintz __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 188386622ee7SYuval Mintz 1884dacd88d6SYuval Mintz if (b_get_port_stats && p_hwfn->mcp_info) 188586622ee7SYuval Mintz __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); 188686622ee7SYuval Mintz } 188786622ee7SYuval Mintz 188886622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev, 188986622ee7SYuval Mintz struct qed_eth_stats *stats) 189086622ee7SYuval Mintz { 189186622ee7SYuval Mintz u8 fw_vport = 0; 189286622ee7SYuval Mintz int i; 189386622ee7SYuval Mintz 189486622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 189586622ee7SYuval Mintz 189686622ee7SYuval Mintz for_each_hwfn(cdev, i) { 189786622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1898dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1899dacd88d6SYuval Mintz : NULL; 190086622ee7SYuval Mintz 1901dacd88d6SYuval Mintz if (IS_PF(cdev)) { 190286622ee7SYuval Mintz /* The main vport index is relative first */ 190386622ee7SYuval Mintz if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { 190486622ee7SYuval Mintz DP_ERR(p_hwfn, "No vport available!\n"); 1905dacd88d6SYuval Mintz goto out; 1906dacd88d6SYuval Mintz } 190786622ee7SYuval Mintz } 190886622ee7SYuval Mintz 1909dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 191086622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 191186622ee7SYuval Mintz continue; 191286622ee7SYuval Mintz } 191386622ee7SYuval Mintz 1914dacd88d6SYuval Mintz __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, 1915dacd88d6SYuval Mintz IS_PF(cdev) ? true : false); 191686622ee7SYuval Mintz 1917dacd88d6SYuval Mintz out: 1918dacd88d6SYuval Mintz if (IS_PF(cdev) && p_ptt) 191986622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 192086622ee7SYuval Mintz } 192186622ee7SYuval Mintz } 192286622ee7SYuval Mintz 19231a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats) 192486622ee7SYuval Mintz { 192586622ee7SYuval Mintz u32 i; 192686622ee7SYuval Mintz 192786622ee7SYuval Mintz if (!cdev) { 192886622ee7SYuval Mintz memset(stats, 0, sizeof(*stats)); 192986622ee7SYuval Mintz return; 193086622ee7SYuval Mintz } 193186622ee7SYuval Mintz 193286622ee7SYuval Mintz _qed_get_vport_stats(cdev, stats); 193386622ee7SYuval Mintz 193486622ee7SYuval Mintz if (!cdev->reset_stats) 193586622ee7SYuval Mintz return; 193686622ee7SYuval Mintz 193786622ee7SYuval Mintz /* Reduce the statistics baseline */ 193886622ee7SYuval Mintz for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) 193986622ee7SYuval Mintz ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; 194086622ee7SYuval Mintz } 194186622ee7SYuval Mintz 194286622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 194386622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev) 194486622ee7SYuval Mintz { 194586622ee7SYuval Mintz int i; 194686622ee7SYuval Mintz 194786622ee7SYuval Mintz for_each_hwfn(cdev, i) { 194886622ee7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 194986622ee7SYuval Mintz struct eth_mstorm_per_queue_stat mstats; 195086622ee7SYuval Mintz struct eth_ustorm_per_queue_stat ustats; 195186622ee7SYuval Mintz struct eth_pstorm_per_queue_stat pstats; 1952dacd88d6SYuval Mintz struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) 1953dacd88d6SYuval Mintz : NULL; 195486622ee7SYuval Mintz u32 addr = 0, len = 0; 195586622ee7SYuval Mintz 1956dacd88d6SYuval Mintz if (IS_PF(cdev) && !p_ptt) { 195786622ee7SYuval Mintz DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 195886622ee7SYuval Mintz continue; 195986622ee7SYuval Mintz } 196086622ee7SYuval Mintz 196186622ee7SYuval Mintz memset(&mstats, 0, sizeof(mstats)); 196286622ee7SYuval Mintz __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 196386622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 196486622ee7SYuval Mintz 196586622ee7SYuval Mintz memset(&ustats, 0, sizeof(ustats)); 196686622ee7SYuval Mintz __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 196786622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 196886622ee7SYuval Mintz 196986622ee7SYuval Mintz memset(&pstats, 0, sizeof(pstats)); 197086622ee7SYuval Mintz __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 197186622ee7SYuval Mintz qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 197286622ee7SYuval Mintz 1973dacd88d6SYuval Mintz if (IS_PF(cdev)) 197486622ee7SYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 197586622ee7SYuval Mintz } 197686622ee7SYuval Mintz 197786622ee7SYuval Mintz /* PORT statistics are not necessarily reset, so we need to 197886622ee7SYuval Mintz * read and create a baseline for future statistics. 197986622ee7SYuval Mintz */ 198086622ee7SYuval Mintz if (!cdev->reset_stats) 198186622ee7SYuval Mintz DP_INFO(cdev, "Reset stats not allocated\n"); 198286622ee7SYuval Mintz else 198386622ee7SYuval Mintz _qed_get_vport_stats(cdev, cdev->reset_stats); 198486622ee7SYuval Mintz } 198586622ee7SYuval Mintz 1986d51e4af5SChopra, Manish static void 1987d51e4af5SChopra, Manish qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1988d51e4af5SChopra, Manish struct qed_arfs_config_params *p_cfg_params) 1989d51e4af5SChopra, Manish { 1990d51e4af5SChopra, Manish if (p_cfg_params->arfs_enable) { 1991d51e4af5SChopra, Manish qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 1992d51e4af5SChopra, Manish p_cfg_params->tcp, p_cfg_params->udp, 1993d51e4af5SChopra, Manish p_cfg_params->ipv4, p_cfg_params->ipv6); 1994d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, 1995d51e4af5SChopra, Manish "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n", 1996d51e4af5SChopra, Manish p_cfg_params->tcp ? "Enable" : "Disable", 1997d51e4af5SChopra, Manish p_cfg_params->udp ? "Enable" : "Disable", 1998d51e4af5SChopra, Manish p_cfg_params->ipv4 ? "Enable" : "Disable", 1999d51e4af5SChopra, Manish p_cfg_params->ipv6 ? "Enable" : "Disable"); 2000d51e4af5SChopra, Manish } else { 2001d51e4af5SChopra, Manish qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2002d51e4af5SChopra, Manish } 2003d51e4af5SChopra, Manish 2004d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n", 2005d51e4af5SChopra, Manish p_cfg_params->arfs_enable ? "Enable" : "Disable"); 2006d51e4af5SChopra, Manish } 2007d51e4af5SChopra, Manish 2008d51e4af5SChopra, Manish static int 2009d51e4af5SChopra, Manish qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2010d51e4af5SChopra, Manish struct qed_spq_comp_cb *p_cb, 2011d51e4af5SChopra, Manish dma_addr_t p_addr, u16 length, u16 qid, 2012d51e4af5SChopra, Manish u8 vport_id, bool b_is_add) 2013d51e4af5SChopra, Manish { 2014d51e4af5SChopra, Manish struct rx_update_gft_filter_data *p_ramrod = NULL; 2015d51e4af5SChopra, Manish struct qed_spq_entry *p_ent = NULL; 2016d51e4af5SChopra, Manish struct qed_sp_init_data init_data; 2017d51e4af5SChopra, Manish u16 abs_rx_q_id = 0; 2018d51e4af5SChopra, Manish u8 abs_vport_id = 0; 2019d51e4af5SChopra, Manish int rc = -EINVAL; 2020d51e4af5SChopra, Manish 2021d51e4af5SChopra, Manish rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); 2022d51e4af5SChopra, Manish if (rc) 2023d51e4af5SChopra, Manish return rc; 2024d51e4af5SChopra, Manish 2025d51e4af5SChopra, Manish rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id); 2026d51e4af5SChopra, Manish if (rc) 2027d51e4af5SChopra, Manish return rc; 2028d51e4af5SChopra, Manish 2029d51e4af5SChopra, Manish /* Get SPQ entry */ 2030d51e4af5SChopra, Manish memset(&init_data, 0, sizeof(init_data)); 2031d51e4af5SChopra, Manish init_data.cid = qed_spq_get_cid(p_hwfn); 2032d51e4af5SChopra, Manish 2033d51e4af5SChopra, Manish init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2034d51e4af5SChopra, Manish 2035d51e4af5SChopra, Manish if (p_cb) { 2036d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_CB; 2037d51e4af5SChopra, Manish init_data.p_comp_data = p_cb; 2038d51e4af5SChopra, Manish } else { 2039d51e4af5SChopra, Manish init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 2040d51e4af5SChopra, Manish } 2041d51e4af5SChopra, Manish 2042d51e4af5SChopra, Manish rc = qed_sp_init_request(p_hwfn, &p_ent, 2043d51e4af5SChopra, Manish ETH_RAMROD_GFT_UPDATE_FILTER, 2044d51e4af5SChopra, Manish PROTOCOLID_ETH, &init_data); 2045d51e4af5SChopra, Manish if (rc) 2046d51e4af5SChopra, Manish return rc; 2047d51e4af5SChopra, Manish 2048d51e4af5SChopra, Manish p_ramrod = &p_ent->ramrod.rx_update_gft; 2049d51e4af5SChopra, Manish DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr); 2050d51e4af5SChopra, Manish p_ramrod->pkt_hdr_length = cpu_to_le16(length); 2051d51e4af5SChopra, Manish p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id); 2052d51e4af5SChopra, Manish p_ramrod->vport_id = abs_vport_id; 2053d51e4af5SChopra, Manish p_ramrod->filter_type = RFS_FILTER_TYPE; 2054d51e4af5SChopra, Manish p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER; 2055d51e4af5SChopra, Manish 2056d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, QED_MSG_SP, 2057d51e4af5SChopra, Manish "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n", 2058d51e4af5SChopra, Manish abs_vport_id, abs_rx_q_id, 2059d51e4af5SChopra, Manish b_is_add ? "Adding" : "Removing", (u64)p_addr, length); 2060d51e4af5SChopra, Manish 2061d51e4af5SChopra, Manish return qed_spq_post(p_hwfn, p_ent, NULL); 2062d51e4af5SChopra, Manish } 2063d51e4af5SChopra, Manish 206425c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev, 206525c089d7SYuval Mintz struct qed_dev_eth_info *info) 206625c089d7SYuval Mintz { 206725c089d7SYuval Mintz int i; 206825c089d7SYuval Mintz 206925c089d7SYuval Mintz memset(info, 0, sizeof(*info)); 207025c089d7SYuval Mintz 207125c089d7SYuval Mintz info->num_tc = 1; 207225c089d7SYuval Mintz 20731408cc1fSYuval Mintz if (IS_PF(cdev)) { 207425eb8d46SYuval Mintz int max_vf_vlan_filters = 0; 20757b7e70f9SYuval Mintz int max_vf_mac_filters = 0; 207625eb8d46SYuval Mintz 207725c089d7SYuval Mintz if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 2078e1d32acbSMintz, Yuval u16 num_queues = 0; 2079e1d32acbSMintz, Yuval 2080e1d32acbSMintz, Yuval /* Since the feature controls only queue-zones, 2081e1d32acbSMintz, Yuval * make sure we have the contexts [rx, tx, xdp] to 2082e1d32acbSMintz, Yuval * match. 2083e1d32acbSMintz, Yuval */ 2084e1d32acbSMintz, Yuval for_each_hwfn(cdev, i) { 2085e1d32acbSMintz, Yuval struct qed_hwfn *hwfn = &cdev->hwfns[i]; 2086e1d32acbSMintz, Yuval u16 l2_queues = (u16)FEAT_NUM(hwfn, 2087e1d32acbSMintz, Yuval QED_PF_L2_QUE); 2088e1d32acbSMintz, Yuval u16 cids; 2089e1d32acbSMintz, Yuval 2090e1d32acbSMintz, Yuval cids = hwfn->pf_params.eth_pf_params.num_cons; 2091e1d32acbSMintz, Yuval num_queues += min_t(u16, l2_queues, cids / 3); 2092e1d32acbSMintz, Yuval } 2093e1d32acbSMintz, Yuval 2094e1d32acbSMintz, Yuval /* queues might theoretically be >256, but interrupts' 2095e1d32acbSMintz, Yuval * upper-limit guarantes that it would fit in a u8. 2096e1d32acbSMintz, Yuval */ 2097e1d32acbSMintz, Yuval if (cdev->int_params.fp_msix_cnt) { 2098e1d32acbSMintz, Yuval u8 irqs = cdev->int_params.fp_msix_cnt; 2099e1d32acbSMintz, Yuval 2100e1d32acbSMintz, Yuval info->num_queues = (u8)min_t(u16, 2101e1d32acbSMintz, Yuval num_queues, irqs); 2102e1d32acbSMintz, Yuval } 210325c089d7SYuval Mintz } else { 210425c089d7SYuval Mintz info->num_queues = cdev->num_hwfns; 210525c089d7SYuval Mintz } 210625c089d7SYuval Mintz 21077b7e70f9SYuval Mintz if (IS_QED_SRIOV(cdev)) { 210825eb8d46SYuval Mintz max_vf_vlan_filters = cdev->p_iov_info->total_vfs * 210925eb8d46SYuval Mintz QED_ETH_VF_NUM_VLAN_FILTERS; 21107b7e70f9SYuval Mintz max_vf_mac_filters = cdev->p_iov_info->total_vfs * 21117b7e70f9SYuval Mintz QED_ETH_VF_NUM_MAC_FILTERS; 21127b7e70f9SYuval Mintz } 21137b7e70f9SYuval Mintz info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 21147b7e70f9SYuval Mintz QED_VLAN) - 211525eb8d46SYuval Mintz max_vf_vlan_filters; 21167b7e70f9SYuval Mintz info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev), 21177b7e70f9SYuval Mintz QED_MAC) - 21187b7e70f9SYuval Mintz max_vf_mac_filters; 211925eb8d46SYuval Mintz 212025c089d7SYuval Mintz ether_addr_copy(info->port_mac, 212125c089d7SYuval Mintz cdev->hwfns[0].hw_info.hw_mac_addr); 21221408cc1fSYuval Mintz 2123cbb8a12cSMintz, Yuval info->xdp_supported = true; 2124cbb8a12cSMintz, Yuval } else { 2125cbb8a12cSMintz, Yuval u16 total_cids = 0; 2126cbb8a12cSMintz, Yuval 2127cbb8a12cSMintz, Yuval /* Determine queues & XDP support */ 2128cbb8a12cSMintz, Yuval for_each_hwfn(cdev, i) { 2129cbb8a12cSMintz, Yuval struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2130cbb8a12cSMintz, Yuval u8 queues, cids; 2131cbb8a12cSMintz, Yuval 2132cbb8a12cSMintz, Yuval qed_vf_get_num_cids(p_hwfn, &cids); 2133cbb8a12cSMintz, Yuval qed_vf_get_num_rxqs(p_hwfn, &queues); 21341408cc1fSYuval Mintz info->num_queues += queues; 2135cbb8a12cSMintz, Yuval total_cids += cids; 21361408cc1fSYuval Mintz } 21371408cc1fSYuval Mintz 2138cbb8a12cSMintz, Yuval /* Enable VF XDP in case PF guarntees sufficient connections */ 2139cbb8a12cSMintz, Yuval if (total_cids >= info->num_queues * 3) 2140cbb8a12cSMintz, Yuval info->xdp_supported = true; 2141cbb8a12cSMintz, Yuval 21421408cc1fSYuval Mintz qed_vf_get_num_vlan_filters(&cdev->hwfns[0], 21432edbff8dSTomer Tayar (u8 *)&info->num_vlan_filters); 2144b0fca312SMintz, Yuval qed_vf_get_num_mac_filters(&cdev->hwfns[0], 2145b0fca312SMintz, Yuval (u8 *)&info->num_mac_filters); 21461408cc1fSYuval Mintz qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); 2147d8c2c7e3SYuval Mintz 2148d8c2c7e3SYuval Mintz info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi; 21491408cc1fSYuval Mintz } 215025c089d7SYuval Mintz 215125c089d7SYuval Mintz qed_fill_dev_info(cdev, &info->common); 215225c089d7SYuval Mintz 21531408cc1fSYuval Mintz if (IS_VF(cdev)) 21540ee28e31SShyam Saini eth_zero_addr(info->common.hw_mac); 21551408cc1fSYuval Mintz 215625c089d7SYuval Mintz return 0; 215725c089d7SYuval Mintz } 215825c089d7SYuval Mintz 2159cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev, 21601408cc1fSYuval Mintz struct qed_eth_cb_ops *ops, void *cookie) 2161cc875c2eSYuval Mintz { 2162cc875c2eSYuval Mintz cdev->protocol_ops.eth = ops; 2163cc875c2eSYuval Mintz cdev->ops_cookie = cookie; 21641408cc1fSYuval Mintz 21651408cc1fSYuval Mintz /* For VF, we start bulletin reading */ 21661408cc1fSYuval Mintz if (IS_VF(cdev)) 21671408cc1fSYuval Mintz qed_vf_start_iov_wq(cdev); 2168cc875c2eSYuval Mintz } 2169cc875c2eSYuval Mintz 2170eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) 2171eff16960SYuval Mintz { 2172eff16960SYuval Mintz if (IS_PF(cdev)) 2173eff16960SYuval Mintz return true; 2174eff16960SYuval Mintz 2175eff16960SYuval Mintz return qed_vf_check_mac(&cdev->hwfns[0], mac); 2176eff16960SYuval Mintz } 2177eff16960SYuval Mintz 2178cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev, 2179088c8618SManish Chopra struct qed_start_vport_params *params) 2180cee4d264SManish Chopra { 2181cee4d264SManish Chopra int rc, i; 2182cee4d264SManish Chopra 2183cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2184088c8618SManish Chopra struct qed_sp_vport_start_params start = { 0 }; 2185cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2186cee4d264SManish Chopra 2187088c8618SManish Chopra start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : 2188088c8618SManish Chopra QED_TPA_MODE_NONE; 2189088c8618SManish Chopra start.remove_inner_vlan = params->remove_inner_vlan; 219008feecd7SYuval Mintz start.only_untagged = true; /* untagged only */ 2191088c8618SManish Chopra start.drop_ttl0 = params->drop_ttl0; 2192088c8618SManish Chopra start.opaque_fid = p_hwfn->hw_info.opaque_fid; 2193088c8618SManish Chopra start.concrete_fid = p_hwfn->hw_info.concrete_fid; 2194c78c70faSSudarsana Reddy Kalluru start.handle_ptp_pkts = params->handle_ptp_pkts; 2195088c8618SManish Chopra start.vport_id = params->vport_id; 2196088c8618SManish Chopra start.max_buffers_per_cqe = 16; 2197088c8618SManish Chopra start.mtu = params->mtu; 2198cee4d264SManish Chopra 2199088c8618SManish Chopra rc = qed_sp_vport_start(p_hwfn, &start); 2200cee4d264SManish Chopra if (rc) { 2201cee4d264SManish Chopra DP_ERR(cdev, "Failed to start VPORT\n"); 2202cee4d264SManish Chopra return rc; 2203cee4d264SManish Chopra } 2204cee4d264SManish Chopra 220515582962SRahul Verma rc = qed_hw_start_fastpath(p_hwfn); 220615582962SRahul Verma if (rc) { 220715582962SRahul Verma DP_ERR(cdev, "Failed to start VPORT fastpath\n"); 220815582962SRahul Verma return rc; 220915582962SRahul Verma } 2210cee4d264SManish Chopra 2211cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2212cee4d264SManish Chopra "Started V-PORT %d with MTU %d\n", 2213088c8618SManish Chopra start.vport_id, start.mtu); 2214cee4d264SManish Chopra } 2215cee4d264SManish Chopra 2216a0d26d5aSYuval Mintz if (params->clear_stats) 22179df2ed04SManish Chopra qed_reset_vport_stats(cdev); 22189df2ed04SManish Chopra 2219cee4d264SManish Chopra return 0; 2220cee4d264SManish Chopra } 2221cee4d264SManish Chopra 22221a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id) 2223cee4d264SManish Chopra { 2224cee4d264SManish Chopra int rc, i; 2225cee4d264SManish Chopra 2226cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2227cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2228cee4d264SManish Chopra 2229cee4d264SManish Chopra rc = qed_sp_vport_stop(p_hwfn, 22301a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid, vport_id); 2231cee4d264SManish Chopra 2232cee4d264SManish Chopra if (rc) { 2233cee4d264SManish Chopra DP_ERR(cdev, "Failed to stop VPORT\n"); 2234cee4d264SManish Chopra return rc; 2235cee4d264SManish Chopra } 2236cee4d264SManish Chopra } 2237cee4d264SManish Chopra return 0; 2238cee4d264SManish Chopra } 2239cee4d264SManish Chopra 2240f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev, 2241f29ffdb6SMintz, Yuval struct qed_update_vport_rss_params *input, 2242f29ffdb6SMintz, Yuval struct qed_rss_params *rss) 2243f29ffdb6SMintz, Yuval { 2244f29ffdb6SMintz, Yuval int i, fn; 2245f29ffdb6SMintz, Yuval 2246f29ffdb6SMintz, Yuval /* Update configuration with what's correct regardless of CMT */ 2247f29ffdb6SMintz, Yuval rss->update_rss_config = 1; 2248f29ffdb6SMintz, Yuval rss->rss_enable = 1; 2249f29ffdb6SMintz, Yuval rss->update_rss_capabilities = 1; 2250f29ffdb6SMintz, Yuval rss->update_rss_ind_table = 1; 2251f29ffdb6SMintz, Yuval rss->update_rss_key = 1; 2252f29ffdb6SMintz, Yuval rss->rss_caps = input->rss_caps; 2253f29ffdb6SMintz, Yuval memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32)); 2254f29ffdb6SMintz, Yuval 2255f29ffdb6SMintz, Yuval /* In regular scenario, we'd simply need to take input handlers. 2256f29ffdb6SMintz, Yuval * But in CMT, we'd have to split the handlers according to the 2257f29ffdb6SMintz, Yuval * engine they were configured on. We'd then have to understand 2258f29ffdb6SMintz, Yuval * whether RSS is really required, since 2-queues on CMT doesn't 2259f29ffdb6SMintz, Yuval * require RSS. 2260f29ffdb6SMintz, Yuval */ 2261f29ffdb6SMintz, Yuval if (cdev->num_hwfns == 1) { 2262f29ffdb6SMintz, Yuval memcpy(rss->rss_ind_table, 2263f29ffdb6SMintz, Yuval input->rss_ind_table, 2264f29ffdb6SMintz, Yuval QED_RSS_IND_TABLE_SIZE * sizeof(void *)); 2265f29ffdb6SMintz, Yuval rss->rss_table_size_log = 7; 2266f29ffdb6SMintz, Yuval return 0; 2267f29ffdb6SMintz, Yuval } 2268f29ffdb6SMintz, Yuval 2269f29ffdb6SMintz, Yuval /* Start by copying the non-spcific information to the 2nd copy */ 2270f29ffdb6SMintz, Yuval memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params)); 2271f29ffdb6SMintz, Yuval 2272f29ffdb6SMintz, Yuval /* CMT should be round-robin */ 2273f29ffdb6SMintz, Yuval for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { 2274f29ffdb6SMintz, Yuval struct qed_queue_cid *cid = input->rss_ind_table[i]; 2275f29ffdb6SMintz, Yuval struct qed_rss_params *t_rss; 2276f29ffdb6SMintz, Yuval 2277f29ffdb6SMintz, Yuval if (cid->p_owner == QED_LEADING_HWFN(cdev)) 2278f29ffdb6SMintz, Yuval t_rss = &rss[0]; 2279f29ffdb6SMintz, Yuval else 2280f29ffdb6SMintz, Yuval t_rss = &rss[1]; 2281f29ffdb6SMintz, Yuval 2282f29ffdb6SMintz, Yuval t_rss->rss_ind_table[i / cdev->num_hwfns] = cid; 2283f29ffdb6SMintz, Yuval } 2284f29ffdb6SMintz, Yuval 2285f29ffdb6SMintz, Yuval /* Make sure RSS is actually required */ 2286f29ffdb6SMintz, Yuval for_each_hwfn(cdev, fn) { 2287f29ffdb6SMintz, Yuval for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) { 2288f29ffdb6SMintz, Yuval if (rss[fn].rss_ind_table[i] != 2289f29ffdb6SMintz, Yuval rss[fn].rss_ind_table[0]) 2290f29ffdb6SMintz, Yuval break; 2291f29ffdb6SMintz, Yuval } 2292f29ffdb6SMintz, Yuval if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) { 2293f29ffdb6SMintz, Yuval DP_VERBOSE(cdev, NETIF_MSG_IFUP, 2294f29ffdb6SMintz, Yuval "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2295f29ffdb6SMintz, Yuval return -EINVAL; 2296f29ffdb6SMintz, Yuval } 2297f29ffdb6SMintz, Yuval rss[fn].rss_table_size_log = 6; 2298f29ffdb6SMintz, Yuval } 2299f29ffdb6SMintz, Yuval 2300f29ffdb6SMintz, Yuval return 0; 2301f29ffdb6SMintz, Yuval } 2302f29ffdb6SMintz, Yuval 2303cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev, 2304cee4d264SManish Chopra struct qed_update_vport_params *params) 2305cee4d264SManish Chopra { 2306cee4d264SManish Chopra struct qed_sp_vport_update_params sp_params; 2307f29ffdb6SMintz, Yuval struct qed_rss_params *rss; 2308f29ffdb6SMintz, Yuval int rc = 0, i; 2309cee4d264SManish Chopra 2310cee4d264SManish Chopra if (!cdev) 2311cee4d264SManish Chopra return -ENODEV; 2312cee4d264SManish Chopra 2313f29ffdb6SMintz, Yuval rss = vzalloc(sizeof(*rss) * cdev->num_hwfns); 2314f29ffdb6SMintz, Yuval if (!rss) 2315f29ffdb6SMintz, Yuval return -ENOMEM; 2316f29ffdb6SMintz, Yuval 2317cee4d264SManish Chopra memset(&sp_params, 0, sizeof(sp_params)); 2318cee4d264SManish Chopra 2319cee4d264SManish Chopra /* Translate protocol params into sp params */ 2320cee4d264SManish Chopra sp_params.vport_id = params->vport_id; 23211a635e48SYuval Mintz sp_params.update_vport_active_rx_flg = params->update_vport_active_flg; 23221a635e48SYuval Mintz sp_params.update_vport_active_tx_flg = params->update_vport_active_flg; 2323cee4d264SManish Chopra sp_params.vport_active_rx_flg = params->vport_active_flg; 2324cee4d264SManish Chopra sp_params.vport_active_tx_flg = params->vport_active_flg; 2325831bfb0eSYuval Mintz sp_params.update_tx_switching_flg = params->update_tx_switching_flg; 2326831bfb0eSYuval Mintz sp_params.tx_switching_flg = params->tx_switching_flg; 23273f9b4a69SYuval Mintz sp_params.accept_any_vlan = params->accept_any_vlan; 23283f9b4a69SYuval Mintz sp_params.update_accept_any_vlan_flg = 23293f9b4a69SYuval Mintz params->update_accept_any_vlan_flg; 2330cee4d264SManish Chopra 2331f29ffdb6SMintz, Yuval /* Prepare the RSS configuration */ 2332f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2333f29ffdb6SMintz, Yuval if (qed_update_vport_rss(cdev, ¶ms->rss_params, rss)) 2334cee4d264SManish Chopra params->update_rss_flg = 0; 2335cee4d264SManish Chopra 2336cee4d264SManish Chopra for_each_hwfn(cdev, i) { 2337cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2338cee4d264SManish Chopra 2339f29ffdb6SMintz, Yuval if (params->update_rss_flg) 2340f29ffdb6SMintz, Yuval sp_params.rss_params = &rss[i]; 2341f29ffdb6SMintz, Yuval 2342cee4d264SManish Chopra sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2343cee4d264SManish Chopra rc = qed_sp_vport_update(p_hwfn, &sp_params, 2344cee4d264SManish Chopra QED_SPQ_MODE_EBLOCK, 2345cee4d264SManish Chopra NULL); 2346cee4d264SManish Chopra if (rc) { 2347cee4d264SManish Chopra DP_ERR(cdev, "Failed to update VPORT\n"); 2348f29ffdb6SMintz, Yuval goto out; 2349cee4d264SManish Chopra } 2350cee4d264SManish Chopra 2351cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2352cee4d264SManish Chopra "Updated V-PORT %d: active_flag %d [update %d]\n", 2353cee4d264SManish Chopra params->vport_id, params->vport_active_flg, 2354cee4d264SManish Chopra params->update_vport_active_flg); 2355cee4d264SManish Chopra } 2356cee4d264SManish Chopra 2357f29ffdb6SMintz, Yuval out: 2358f29ffdb6SMintz, Yuval vfree(rss); 2359f29ffdb6SMintz, Yuval return rc; 2360cee4d264SManish Chopra } 2361cee4d264SManish Chopra 2362cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev, 23633da7a37aSMintz, Yuval u8 rss_num, 23643da7a37aSMintz, Yuval struct qed_queue_start_common_params *p_params, 2365cee4d264SManish Chopra u16 bd_max_bytes, 2366cee4d264SManish Chopra dma_addr_t bd_chain_phys_addr, 2367cee4d264SManish Chopra dma_addr_t cqe_pbl_addr, 2368cee4d264SManish Chopra u16 cqe_pbl_size, 23693da7a37aSMintz, Yuval struct qed_rxq_start_ret_params *ret_params) 2370cee4d264SManish Chopra { 2371cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 23721a635e48SYuval Mintz int rc, hwfn_index; 2373cee4d264SManish Chopra 23743da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2375cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2376cee4d264SManish Chopra 23773da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 23783da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2379cee4d264SManish Chopra 23803da7a37aSMintz, Yuval rc = qed_eth_rx_queue_start(p_hwfn, 2381cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 23823da7a37aSMintz, Yuval p_params, 2383cee4d264SManish Chopra bd_max_bytes, 2384cee4d264SManish Chopra bd_chain_phys_addr, 23853da7a37aSMintz, Yuval cqe_pbl_addr, cqe_pbl_size, ret_params); 2386cee4d264SManish Chopra if (rc) { 23873da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id); 2388cee4d264SManish Chopra return rc; 2389cee4d264SManish Chopra } 2390cee4d264SManish Chopra 2391cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2392f604b17dSMintz, Yuval "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", 23933da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 2394f604b17dSMintz, Yuval p_params->p_sb->igu_sb_id); 2395cee4d264SManish Chopra 2396cee4d264SManish Chopra return 0; 2397cee4d264SManish Chopra } 2398cee4d264SManish Chopra 23993da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle) 2400cee4d264SManish Chopra { 2401cee4d264SManish Chopra int rc, hwfn_index; 2402cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2403cee4d264SManish Chopra 24043da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2405cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2406cee4d264SManish Chopra 24073da7a37aSMintz, Yuval rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false); 2408cee4d264SManish Chopra if (rc) { 24093da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id); 2410cee4d264SManish Chopra return rc; 2411cee4d264SManish Chopra } 2412cee4d264SManish Chopra 2413cee4d264SManish Chopra return 0; 2414cee4d264SManish Chopra } 2415cee4d264SManish Chopra 2416cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev, 24173da7a37aSMintz, Yuval u8 rss_num, 2418cee4d264SManish Chopra struct qed_queue_start_common_params *p_params, 2419cee4d264SManish Chopra dma_addr_t pbl_addr, 2420cee4d264SManish Chopra u16 pbl_size, 24213da7a37aSMintz, Yuval struct qed_txq_start_ret_params *ret_params) 2422cee4d264SManish Chopra { 2423cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2424cee4d264SManish Chopra int rc, hwfn_index; 2425cee4d264SManish Chopra 24263da7a37aSMintz, Yuval hwfn_index = rss_num % cdev->num_hwfns; 2427cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 24283da7a37aSMintz, Yuval p_params->queue_id = p_params->queue_id / cdev->num_hwfns; 24293da7a37aSMintz, Yuval p_params->stats_id = p_params->vport_id; 2430cee4d264SManish Chopra 24313da7a37aSMintz, Yuval rc = qed_eth_tx_queue_start(p_hwfn, 2432cee4d264SManish Chopra p_hwfn->hw_info.opaque_fid, 24333da7a37aSMintz, Yuval p_params, 0, 24343da7a37aSMintz, Yuval pbl_addr, pbl_size, ret_params); 2435cee4d264SManish Chopra 2436cee4d264SManish Chopra if (rc) { 2437cee4d264SManish Chopra DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); 2438cee4d264SManish Chopra return rc; 2439cee4d264SManish Chopra } 2440cee4d264SManish Chopra 2441cee4d264SManish Chopra DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), 2442f604b17dSMintz, Yuval "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", 24433da7a37aSMintz, Yuval p_params->queue_id, rss_num, p_params->vport_id, 2444f604b17dSMintz, Yuval p_params->p_sb->igu_sb_id); 2445cee4d264SManish Chopra 2446cee4d264SManish Chopra return 0; 2447cee4d264SManish Chopra } 2448cee4d264SManish Chopra 2449cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10) 2450cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev) 2451cee4d264SManish Chopra { 245215582962SRahul Verma int rc; 245315582962SRahul Verma 245415582962SRahul Verma rc = qed_hw_stop_fastpath(cdev); 245515582962SRahul Verma if (rc) { 245615582962SRahul Verma DP_ERR(cdev, "Failed to stop Fastpath\n"); 245715582962SRahul Verma return rc; 245815582962SRahul Verma } 2459cee4d264SManish Chopra 2460cee4d264SManish Chopra return 0; 2461cee4d264SManish Chopra } 2462cee4d264SManish Chopra 24633da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle) 2464cee4d264SManish Chopra { 2465cee4d264SManish Chopra struct qed_hwfn *p_hwfn; 2466cee4d264SManish Chopra int rc, hwfn_index; 2467cee4d264SManish Chopra 24683da7a37aSMintz, Yuval hwfn_index = rss_id % cdev->num_hwfns; 2469cee4d264SManish Chopra p_hwfn = &cdev->hwfns[hwfn_index]; 2470cee4d264SManish Chopra 24713da7a37aSMintz, Yuval rc = qed_eth_tx_queue_stop(p_hwfn, handle); 2472cee4d264SManish Chopra if (rc) { 24733da7a37aSMintz, Yuval DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id); 2474cee4d264SManish Chopra return rc; 2475cee4d264SManish Chopra } 2476cee4d264SManish Chopra 2477cee4d264SManish Chopra return 0; 2478cee4d264SManish Chopra } 2479cee4d264SManish Chopra 2480464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev, 2481464f6645SManish Chopra struct qed_tunn_params *tunn_params) 2482464f6645SManish Chopra { 248319968430SChopra, Manish struct qed_tunnel_info tunn_info; 2484464f6645SManish Chopra int i, rc; 2485464f6645SManish Chopra 2486464f6645SManish Chopra memset(&tunn_info, 0, sizeof(tunn_info)); 248719968430SChopra, Manish if (tunn_params->update_vxlan_port) { 248819968430SChopra, Manish tunn_info.vxlan_port.b_update_port = true; 248919968430SChopra, Manish tunn_info.vxlan_port.port = tunn_params->vxlan_port; 2490464f6645SManish Chopra } 2491464f6645SManish Chopra 249219968430SChopra, Manish if (tunn_params->update_geneve_port) { 249319968430SChopra, Manish tunn_info.geneve_port.b_update_port = true; 249419968430SChopra, Manish tunn_info.geneve_port.port = tunn_params->geneve_port; 2495464f6645SManish Chopra } 2496464f6645SManish Chopra 2497464f6645SManish Chopra for_each_hwfn(cdev, i) { 2498464f6645SManish Chopra struct qed_hwfn *hwfn = &cdev->hwfns[i]; 24994f64675fSManish Chopra struct qed_ptt *p_ptt; 250097379f15SChopra, Manish struct qed_tunnel_info *tun; 250197379f15SChopra, Manish 250297379f15SChopra, Manish tun = &hwfn->cdev->tunnel; 25034f64675fSManish Chopra if (IS_PF(cdev)) { 25044f64675fSManish Chopra p_ptt = qed_ptt_acquire(hwfn); 25054f64675fSManish Chopra if (!p_ptt) 25064f64675fSManish Chopra return -EAGAIN; 25074f64675fSManish Chopra } else { 25084f64675fSManish Chopra p_ptt = NULL; 25094f64675fSManish Chopra } 2510464f6645SManish Chopra 25114f64675fSManish Chopra rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info, 2512464f6645SManish Chopra QED_SPQ_MODE_EBLOCK, NULL); 25134f64675fSManish Chopra if (rc) { 25144f64675fSManish Chopra if (IS_PF(cdev)) 25154f64675fSManish Chopra qed_ptt_release(hwfn, p_ptt); 2516464f6645SManish Chopra return rc; 25174f64675fSManish Chopra } 251897379f15SChopra, Manish 251997379f15SChopra, Manish if (IS_PF_SRIOV(hwfn)) { 252097379f15SChopra, Manish u16 vxlan_port, geneve_port; 252197379f15SChopra, Manish int j; 252297379f15SChopra, Manish 252397379f15SChopra, Manish vxlan_port = tun->vxlan_port.port; 252497379f15SChopra, Manish geneve_port = tun->geneve_port.port; 252597379f15SChopra, Manish 252697379f15SChopra, Manish qed_for_each_vf(hwfn, j) { 252797379f15SChopra, Manish qed_iov_bulletin_set_udp_ports(hwfn, j, 252897379f15SChopra, Manish vxlan_port, 252997379f15SChopra, Manish geneve_port); 253097379f15SChopra, Manish } 253197379f15SChopra, Manish 253297379f15SChopra, Manish qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG); 253397379f15SChopra, Manish } 25344f64675fSManish Chopra if (IS_PF(cdev)) 25354f64675fSManish Chopra qed_ptt_release(hwfn, p_ptt); 2536464f6645SManish Chopra } 2537464f6645SManish Chopra 2538464f6645SManish Chopra return 0; 2539464f6645SManish Chopra } 2540464f6645SManish Chopra 2541cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev, 2542cee4d264SManish Chopra enum qed_filter_rx_mode_type type) 2543cee4d264SManish Chopra { 2544cee4d264SManish Chopra struct qed_filter_accept_flags accept_flags; 2545cee4d264SManish Chopra 2546cee4d264SManish Chopra memset(&accept_flags, 0, sizeof(accept_flags)); 2547cee4d264SManish Chopra 2548cee4d264SManish Chopra accept_flags.update_rx_mode_config = 1; 2549cee4d264SManish Chopra accept_flags.update_tx_mode_config = 1; 2550cee4d264SManish Chopra accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2551cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2552cee4d264SManish Chopra QED_ACCEPT_BCAST; 2553cee4d264SManish Chopra accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | 2554cee4d264SManish Chopra QED_ACCEPT_MCAST_MATCHED | 2555cee4d264SManish Chopra QED_ACCEPT_BCAST; 2556cee4d264SManish Chopra 255788067876SMintz, Yuval if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 2558cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | 2559cee4d264SManish Chopra QED_ACCEPT_MCAST_UNMATCHED; 256088067876SMintz, Yuval accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 256188067876SMintz, Yuval } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 2562cee4d264SManish Chopra accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 256388067876SMintz, Yuval accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; 256488067876SMintz, Yuval } 2565cee4d264SManish Chopra 25663f9b4a69SYuval Mintz return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, 2567cee4d264SManish Chopra QED_SPQ_MODE_CB, NULL); 2568cee4d264SManish Chopra } 2569cee4d264SManish Chopra 2570cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev, 2571cee4d264SManish Chopra struct qed_filter_ucast_params *params) 2572cee4d264SManish Chopra { 2573cee4d264SManish Chopra struct qed_filter_ucast ucast; 2574cee4d264SManish Chopra 2575cee4d264SManish Chopra if (!params->vlan_valid && !params->mac_valid) { 25761a635e48SYuval Mintz DP_NOTICE(cdev, 2577cee4d264SManish Chopra "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); 2578cee4d264SManish Chopra return -EINVAL; 2579cee4d264SManish Chopra } 2580cee4d264SManish Chopra 2581cee4d264SManish Chopra memset(&ucast, 0, sizeof(ucast)); 2582cee4d264SManish Chopra switch (params->type) { 2583cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2584cee4d264SManish Chopra ucast.opcode = QED_FILTER_ADD; 2585cee4d264SManish Chopra break; 2586cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2587cee4d264SManish Chopra ucast.opcode = QED_FILTER_REMOVE; 2588cee4d264SManish Chopra break; 2589cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_REPLACE: 2590cee4d264SManish Chopra ucast.opcode = QED_FILTER_REPLACE; 2591cee4d264SManish Chopra break; 2592cee4d264SManish Chopra default: 2593cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown unicast filter type %d\n", 2594cee4d264SManish Chopra params->type); 2595cee4d264SManish Chopra } 2596cee4d264SManish Chopra 2597cee4d264SManish Chopra if (params->vlan_valid && params->mac_valid) { 2598cee4d264SManish Chopra ucast.type = QED_FILTER_MAC_VLAN; 2599cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2600cee4d264SManish Chopra ucast.vlan = params->vlan; 2601cee4d264SManish Chopra } else if (params->mac_valid) { 2602cee4d264SManish Chopra ucast.type = QED_FILTER_MAC; 2603cee4d264SManish Chopra ether_addr_copy(ucast.mac, params->mac); 2604cee4d264SManish Chopra } else { 2605cee4d264SManish Chopra ucast.type = QED_FILTER_VLAN; 2606cee4d264SManish Chopra ucast.vlan = params->vlan; 2607cee4d264SManish Chopra } 2608cee4d264SManish Chopra 2609cee4d264SManish Chopra ucast.is_rx_filter = true; 2610cee4d264SManish Chopra ucast.is_tx_filter = true; 2611cee4d264SManish Chopra 2612cee4d264SManish Chopra return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); 2613cee4d264SManish Chopra } 2614cee4d264SManish Chopra 2615cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev, 2616cee4d264SManish Chopra struct qed_filter_mcast_params *params) 2617cee4d264SManish Chopra { 2618cee4d264SManish Chopra struct qed_filter_mcast mcast; 2619cee4d264SManish Chopra int i; 2620cee4d264SManish Chopra 2621cee4d264SManish Chopra memset(&mcast, 0, sizeof(mcast)); 2622cee4d264SManish Chopra switch (params->type) { 2623cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_ADD: 2624cee4d264SManish Chopra mcast.opcode = QED_FILTER_ADD; 2625cee4d264SManish Chopra break; 2626cee4d264SManish Chopra case QED_FILTER_XCAST_TYPE_DEL: 2627cee4d264SManish Chopra mcast.opcode = QED_FILTER_REMOVE; 2628cee4d264SManish Chopra break; 2629cee4d264SManish Chopra default: 2630cee4d264SManish Chopra DP_NOTICE(cdev, "Unknown multicast filter type %d\n", 2631cee4d264SManish Chopra params->type); 2632cee4d264SManish Chopra } 2633cee4d264SManish Chopra 2634cee4d264SManish Chopra mcast.num_mc_addrs = params->num; 2635cee4d264SManish Chopra for (i = 0; i < mcast.num_mc_addrs; i++) 2636cee4d264SManish Chopra ether_addr_copy(mcast.mac[i], params->mac[i]); 2637cee4d264SManish Chopra 26381a635e48SYuval Mintz return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL); 2639cee4d264SManish Chopra } 2640cee4d264SManish Chopra 2641cee4d264SManish Chopra static int qed_configure_filter(struct qed_dev *cdev, 2642cee4d264SManish Chopra struct qed_filter_params *params) 2643cee4d264SManish Chopra { 2644cee4d264SManish Chopra enum qed_filter_rx_mode_type accept_flags; 2645cee4d264SManish Chopra 2646cee4d264SManish Chopra switch (params->type) { 2647cee4d264SManish Chopra case QED_FILTER_TYPE_UCAST: 2648cee4d264SManish Chopra return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); 2649cee4d264SManish Chopra case QED_FILTER_TYPE_MCAST: 2650cee4d264SManish Chopra return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); 2651cee4d264SManish Chopra case QED_FILTER_TYPE_RX_MODE: 2652cee4d264SManish Chopra accept_flags = params->filter.accept_flags; 2653cee4d264SManish Chopra return qed_configure_filter_rx_mode(cdev, accept_flags); 2654cee4d264SManish Chopra default: 26551a635e48SYuval Mintz DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type); 2656cee4d264SManish Chopra return -EINVAL; 2657cee4d264SManish Chopra } 2658cee4d264SManish Chopra } 2659cee4d264SManish Chopra 2660d51e4af5SChopra, Manish static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher) 2661d51e4af5SChopra, Manish { 2662d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2663d51e4af5SChopra, Manish struct qed_arfs_config_params arfs_config_params; 2664d51e4af5SChopra, Manish 2665d51e4af5SChopra, Manish memset(&arfs_config_params, 0, sizeof(arfs_config_params)); 2666d51e4af5SChopra, Manish arfs_config_params.tcp = true; 2667d51e4af5SChopra, Manish arfs_config_params.udp = true; 2668d51e4af5SChopra, Manish arfs_config_params.ipv4 = true; 2669d51e4af5SChopra, Manish arfs_config_params.ipv6 = true; 2670d51e4af5SChopra, Manish arfs_config_params.arfs_enable = en_searcher; 2671d51e4af5SChopra, Manish 2672d51e4af5SChopra, Manish qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt, 2673d51e4af5SChopra, Manish &arfs_config_params); 2674d51e4af5SChopra, Manish return 0; 2675d51e4af5SChopra, Manish } 2676d51e4af5SChopra, Manish 2677d51e4af5SChopra, Manish static void 2678d51e4af5SChopra, Manish qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn, 2679d51e4af5SChopra, Manish void *cookie, union event_ring_data *data, 2680d51e4af5SChopra, Manish u8 fw_return_code) 2681d51e4af5SChopra, Manish { 2682d51e4af5SChopra, Manish struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common; 2683d51e4af5SChopra, Manish void *dev = p_hwfn->cdev->ops_cookie; 2684d51e4af5SChopra, Manish 2685d51e4af5SChopra, Manish op->arfs_filter_op(dev, cookie, fw_return_code); 2686d51e4af5SChopra, Manish } 2687d51e4af5SChopra, Manish 2688d51e4af5SChopra, Manish static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie, 2689d51e4af5SChopra, Manish dma_addr_t mapping, u16 length, 2690d51e4af5SChopra, Manish u16 vport_id, u16 rx_queue_id, 2691d51e4af5SChopra, Manish bool add_filter) 2692d51e4af5SChopra, Manish { 2693d51e4af5SChopra, Manish struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2694d51e4af5SChopra, Manish struct qed_spq_comp_cb cb; 2695d51e4af5SChopra, Manish int rc = -EINVAL; 2696d51e4af5SChopra, Manish 2697d51e4af5SChopra, Manish cb.function = qed_arfs_sp_response_handler; 2698d51e4af5SChopra, Manish cb.cookie = cookie; 2699d51e4af5SChopra, Manish 2700d51e4af5SChopra, Manish rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt, 2701d51e4af5SChopra, Manish &cb, mapping, length, rx_queue_id, 2702d51e4af5SChopra, Manish vport_id, add_filter); 2703d51e4af5SChopra, Manish if (rc) 2704d51e4af5SChopra, Manish DP_NOTICE(p_hwfn, 2705d51e4af5SChopra, Manish "Failed to issue a-RFS filter configuration\n"); 2706d51e4af5SChopra, Manish else 2707d51e4af5SChopra, Manish DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, 2708d51e4af5SChopra, Manish "Successfully issued a-RFS filter configuration\n"); 2709d51e4af5SChopra, Manish 2710d51e4af5SChopra, Manish return rc; 2711d51e4af5SChopra, Manish } 2712d51e4af5SChopra, Manish 2713cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev, 27141a635e48SYuval Mintz u8 rss_id, struct eth_slow_path_rx_cqe *cqe) 2715cee4d264SManish Chopra { 2716cee4d264SManish Chopra return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], 2717cee4d264SManish Chopra cqe); 2718cee4d264SManish Chopra } 2719cee4d264SManish Chopra 27200b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 27210b55e27dSYuval Mintz extern const struct qed_iov_hv_ops qed_iov_ops_pass; 27220b55e27dSYuval Mintz #endif 27230b55e27dSYuval Mintz 2724a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2725a1d8d8a5SSudarsana Reddy Kalluru extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass; 2726a1d8d8a5SSudarsana Reddy Kalluru #endif 2727a1d8d8a5SSudarsana Reddy Kalluru 2728c78c70faSSudarsana Reddy Kalluru extern const struct qed_eth_ptp_ops qed_ptp_ops_pass; 2729c78c70faSSudarsana Reddy Kalluru 273025c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = { 273125c089d7SYuval Mintz .common = &qed_common_ops_pass, 27320b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV 27330b55e27dSYuval Mintz .iov = &qed_iov_ops_pass, 27340b55e27dSYuval Mintz #endif 2735a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB 2736a1d8d8a5SSudarsana Reddy Kalluru .dcb = &qed_dcbnl_ops_pass, 2737a1d8d8a5SSudarsana Reddy Kalluru #endif 2738c78c70faSSudarsana Reddy Kalluru .ptp = &qed_ptp_ops_pass, 273925c089d7SYuval Mintz .fill_dev_info = &qed_fill_eth_dev_info, 2740cc875c2eSYuval Mintz .register_ops = &qed_register_eth_ops, 2741eff16960SYuval Mintz .check_mac = &qed_check_mac, 2742cee4d264SManish Chopra .vport_start = &qed_start_vport, 2743cee4d264SManish Chopra .vport_stop = &qed_stop_vport, 2744cee4d264SManish Chopra .vport_update = &qed_update_vport, 2745cee4d264SManish Chopra .q_rx_start = &qed_start_rxq, 2746cee4d264SManish Chopra .q_rx_stop = &qed_stop_rxq, 2747cee4d264SManish Chopra .q_tx_start = &qed_start_txq, 2748cee4d264SManish Chopra .q_tx_stop = &qed_stop_txq, 2749cee4d264SManish Chopra .filter_config = &qed_configure_filter, 2750cee4d264SManish Chopra .fastpath_stop = &qed_fastpath_stop, 2751cee4d264SManish Chopra .eth_cqe_completion = &qed_fp_cqe_completion, 27529df2ed04SManish Chopra .get_vport_stats = &qed_get_vport_stats, 2753464f6645SManish Chopra .tunn_config = &qed_tunn_configure, 2754d51e4af5SChopra, Manish .ntuple_filter_config = &qed_ntuple_arfs_filter_config, 2755d51e4af5SChopra, Manish .configure_arfs_searcher = &qed_configure_arfs_searcher, 275625c089d7SYuval Mintz }; 275725c089d7SYuval Mintz 275895114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void) 275925c089d7SYuval Mintz { 276025c089d7SYuval Mintz return &qed_eth_ops_pass; 276125c089d7SYuval Mintz } 276225c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops); 276325c089d7SYuval Mintz 276425c089d7SYuval Mintz void qed_put_eth_ops(void) 276525c089d7SYuval Mintz { 276625c089d7SYuval Mintz /* TODO - reference count for module? */ 276725c089d7SYuval Mintz } 276825c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops); 2769