11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
225c089d7SYuval Mintz /* QLogic qed NIC Driver
3e8f1cb50SMintz, Yuval  * Copyright (c) 2015-2017  QLogic Corporation
4663eacd8SAlexander Lobakin  * Copyright (c) 2019-2020 Marvell International Ltd.
525c089d7SYuval Mintz  */
625c089d7SYuval Mintz 
725c089d7SYuval Mintz #include <linux/types.h>
825c089d7SYuval Mintz #include <asm/byteorder.h>
925c089d7SYuval Mintz #include <asm/param.h>
1025c089d7SYuval Mintz #include <linux/delay.h>
1125c089d7SYuval Mintz #include <linux/dma-mapping.h>
1225c089d7SYuval Mintz #include <linux/etherdevice.h>
1325c089d7SYuval Mintz #include <linux/interrupt.h>
1425c089d7SYuval Mintz #include <linux/kernel.h>
1525c089d7SYuval Mintz #include <linux/module.h>
1625c089d7SYuval Mintz #include <linux/pci.h>
1725c089d7SYuval Mintz #include <linux/slab.h>
1825c089d7SYuval Mintz #include <linux/stddef.h>
1925c089d7SYuval Mintz #include <linux/string.h>
2025c089d7SYuval Mintz #include <linux/workqueue.h>
2125c089d7SYuval Mintz #include <linux/bitops.h>
2225c089d7SYuval Mintz #include <linux/bug.h>
233da7a37aSMintz, Yuval #include <linux/vmalloc.h>
2425c089d7SYuval Mintz #include "qed.h"
2525c089d7SYuval Mintz #include <linux/qed/qed_chain.h>
2625c089d7SYuval Mintz #include "qed_cxt.h"
27c6b7314dSAlexander Lobakin #include "qed_dcbx.h"
2825c089d7SYuval Mintz #include "qed_dev_api.h"
2925c089d7SYuval Mintz #include <linux/qed/qed_eth_if.h>
3025c089d7SYuval Mintz #include "qed_hsi.h"
31ee824f4bSOmkar Kulkarni #include "qed_iro_hsi.h"
3225c089d7SYuval Mintz #include "qed_hw.h"
3325c089d7SYuval Mintz #include "qed_int.h"
34dacd88d6SYuval Mintz #include "qed_l2.h"
3586622ee7SYuval Mintz #include "qed_mcp.h"
36c6b7314dSAlexander Lobakin #include "qed_ptp.h"
3725c089d7SYuval Mintz #include "qed_reg_addr.h"
3825c089d7SYuval Mintz #include "qed_sp.h"
391408cc1fSYuval Mintz #include "qed_sriov.h"
4025c089d7SYuval Mintz 
41cee4d264SManish Chopra #define QED_MAX_SGES_NUM 16
42cee4d264SManish Chopra #define CRC32_POLY 0x1edc6f41
43cee4d264SManish Chopra 
440db711bbSMintz, Yuval struct qed_l2_info {
450db711bbSMintz, Yuval 	u32 queues;
460db711bbSMintz, Yuval 	unsigned long **pp_qid_usage;
470db711bbSMintz, Yuval 
480db711bbSMintz, Yuval 	/* The lock is meant to synchronize access to the qid usage */
490db711bbSMintz, Yuval 	struct mutex lock;
500db711bbSMintz, Yuval };
510db711bbSMintz, Yuval 
qed_l2_alloc(struct qed_hwfn * p_hwfn)520db711bbSMintz, Yuval int qed_l2_alloc(struct qed_hwfn *p_hwfn)
530db711bbSMintz, Yuval {
540db711bbSMintz, Yuval 	struct qed_l2_info *p_l2_info;
550db711bbSMintz, Yuval 	unsigned long **pp_qids;
560db711bbSMintz, Yuval 	u32 i;
570db711bbSMintz, Yuval 
58c851a9dcSKalderon, Michal 	if (!QED_IS_L2_PERSONALITY(p_hwfn))
590db711bbSMintz, Yuval 		return 0;
600db711bbSMintz, Yuval 
610db711bbSMintz, Yuval 	p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL);
620db711bbSMintz, Yuval 	if (!p_l2_info)
630db711bbSMintz, Yuval 		return -ENOMEM;
640db711bbSMintz, Yuval 	p_hwfn->p_l2_info = p_l2_info;
650db711bbSMintz, Yuval 
660db711bbSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
670db711bbSMintz, Yuval 		p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE);
680db711bbSMintz, Yuval 	} else {
690db711bbSMintz, Yuval 		u8 rx = 0, tx = 0;
700db711bbSMintz, Yuval 
710db711bbSMintz, Yuval 		qed_vf_get_num_rxqs(p_hwfn, &rx);
720db711bbSMintz, Yuval 		qed_vf_get_num_txqs(p_hwfn, &tx);
730db711bbSMintz, Yuval 
740db711bbSMintz, Yuval 		p_l2_info->queues = max_t(u8, rx, tx);
750db711bbSMintz, Yuval 	}
760db711bbSMintz, Yuval 
776396bb22SKees Cook 	pp_qids = kcalloc(p_l2_info->queues, sizeof(unsigned long *),
780db711bbSMintz, Yuval 			  GFP_KERNEL);
790db711bbSMintz, Yuval 	if (!pp_qids)
800db711bbSMintz, Yuval 		return -ENOMEM;
810db711bbSMintz, Yuval 	p_l2_info->pp_qid_usage = pp_qids;
820db711bbSMintz, Yuval 
830db711bbSMintz, Yuval 	for (i = 0; i < p_l2_info->queues; i++) {
840db711bbSMintz, Yuval 		pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL);
850db711bbSMintz, Yuval 		if (!pp_qids[i])
860db711bbSMintz, Yuval 			return -ENOMEM;
870db711bbSMintz, Yuval 	}
880db711bbSMintz, Yuval 
890db711bbSMintz, Yuval 	return 0;
900db711bbSMintz, Yuval }
910db711bbSMintz, Yuval 
qed_l2_setup(struct qed_hwfn * p_hwfn)920db711bbSMintz, Yuval void qed_l2_setup(struct qed_hwfn *p_hwfn)
930db711bbSMintz, Yuval {
94af6858eeSMichal Kalderon 	if (!QED_IS_L2_PERSONALITY(p_hwfn))
950db711bbSMintz, Yuval 		return;
960db711bbSMintz, Yuval 
970db711bbSMintz, Yuval 	mutex_init(&p_hwfn->p_l2_info->lock);
980db711bbSMintz, Yuval }
990db711bbSMintz, Yuval 
qed_l2_free(struct qed_hwfn * p_hwfn)1000db711bbSMintz, Yuval void qed_l2_free(struct qed_hwfn *p_hwfn)
1010db711bbSMintz, Yuval {
1020db711bbSMintz, Yuval 	u32 i;
1030db711bbSMintz, Yuval 
104af6858eeSMichal Kalderon 	if (!QED_IS_L2_PERSONALITY(p_hwfn))
1050db711bbSMintz, Yuval 		return;
1060db711bbSMintz, Yuval 
1070db711bbSMintz, Yuval 	if (!p_hwfn->p_l2_info)
1080db711bbSMintz, Yuval 		return;
1090db711bbSMintz, Yuval 
1100db711bbSMintz, Yuval 	if (!p_hwfn->p_l2_info->pp_qid_usage)
1110db711bbSMintz, Yuval 		goto out_l2_info;
1120db711bbSMintz, Yuval 
1130db711bbSMintz, Yuval 	/* Free until hit first uninitialized entry */
1140db711bbSMintz, Yuval 	for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
1150db711bbSMintz, Yuval 		if (!p_hwfn->p_l2_info->pp_qid_usage[i])
1160db711bbSMintz, Yuval 			break;
1170db711bbSMintz, Yuval 		kfree(p_hwfn->p_l2_info->pp_qid_usage[i]);
1180db711bbSMintz, Yuval 	}
1190db711bbSMintz, Yuval 
1200db711bbSMintz, Yuval 	kfree(p_hwfn->p_l2_info->pp_qid_usage);
1210db711bbSMintz, Yuval 
1220db711bbSMintz, Yuval out_l2_info:
1230db711bbSMintz, Yuval 	kfree(p_hwfn->p_l2_info);
1240db711bbSMintz, Yuval 	p_hwfn->p_l2_info = NULL;
1250db711bbSMintz, Yuval }
1260db711bbSMintz, Yuval 
qed_eth_queue_qid_usage_add(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid)127bbe3f233SMintz, Yuval static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn,
128bbe3f233SMintz, Yuval 					struct qed_queue_cid *p_cid)
129bbe3f233SMintz, Yuval {
130bbe3f233SMintz, Yuval 	struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info;
131bbe3f233SMintz, Yuval 	u16 queue_id = p_cid->rel.queue_id;
132bbe3f233SMintz, Yuval 	bool b_rc = true;
133bbe3f233SMintz, Yuval 	u8 first;
134bbe3f233SMintz, Yuval 
135bbe3f233SMintz, Yuval 	mutex_lock(&p_l2_info->lock);
136bbe3f233SMintz, Yuval 
1370331402aSDan Carpenter 	if (queue_id >= p_l2_info->queues) {
138bbe3f233SMintz, Yuval 		DP_NOTICE(p_hwfn,
139bbe3f233SMintz, Yuval 			  "Requested to increase usage for qzone %04x out of %08x\n",
140bbe3f233SMintz, Yuval 			  queue_id, p_l2_info->queues);
141bbe3f233SMintz, Yuval 		b_rc = false;
142bbe3f233SMintz, Yuval 		goto out;
143bbe3f233SMintz, Yuval 	}
144bbe3f233SMintz, Yuval 
145bbe3f233SMintz, Yuval 	first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id],
146bbe3f233SMintz, Yuval 					MAX_QUEUES_PER_QZONE);
147bbe3f233SMintz, Yuval 	if (first >= MAX_QUEUES_PER_QZONE) {
148bbe3f233SMintz, Yuval 		b_rc = false;
149bbe3f233SMintz, Yuval 		goto out;
150bbe3f233SMintz, Yuval 	}
151bbe3f233SMintz, Yuval 
152bbe3f233SMintz, Yuval 	__set_bit(first, p_l2_info->pp_qid_usage[queue_id]);
153bbe3f233SMintz, Yuval 	p_cid->qid_usage_idx = first;
154bbe3f233SMintz, Yuval 
155bbe3f233SMintz, Yuval out:
156bbe3f233SMintz, Yuval 	mutex_unlock(&p_l2_info->lock);
157bbe3f233SMintz, Yuval 	return b_rc;
158bbe3f233SMintz, Yuval }
159bbe3f233SMintz, Yuval 
qed_eth_queue_qid_usage_del(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid)160bbe3f233SMintz, Yuval static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn,
161bbe3f233SMintz, Yuval 					struct qed_queue_cid *p_cid)
162bbe3f233SMintz, Yuval {
163bbe3f233SMintz, Yuval 	mutex_lock(&p_hwfn->p_l2_info->lock);
164bbe3f233SMintz, Yuval 
165bbe3f233SMintz, Yuval 	clear_bit(p_cid->qid_usage_idx,
166bbe3f233SMintz, Yuval 		  p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
167bbe3f233SMintz, Yuval 
168bbe3f233SMintz, Yuval 	mutex_unlock(&p_hwfn->p_l2_info->lock);
169bbe3f233SMintz, Yuval }
170bbe3f233SMintz, Yuval 
qed_eth_queue_cid_release(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid)1713da7a37aSMintz, Yuval void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
1723da7a37aSMintz, Yuval 			       struct qed_queue_cid *p_cid)
1733da7a37aSMintz, Yuval {
17408bc8f15SMintz, Yuval 	bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID);
17508bc8f15SMintz, Yuval 
17608bc8f15SMintz, Yuval 	if (IS_PF(p_hwfn->cdev) && !b_legacy_vf)
17708bc8f15SMintz, Yuval 		_qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
178bbe3f233SMintz, Yuval 
179bbe3f233SMintz, Yuval 	/* For PF's VFs we maintain the index inside queue-zone in IOV */
180bbe3f233SMintz, Yuval 	if (p_cid->vfid == QED_QUEUE_CID_SELF)
181bbe3f233SMintz, Yuval 		qed_eth_queue_qid_usage_del(p_hwfn, p_cid);
182bbe3f233SMintz, Yuval 
1833da7a37aSMintz, Yuval 	vfree(p_cid);
1843da7a37aSMintz, Yuval }
1853da7a37aSMintz, Yuval 
1863da7a37aSMintz, Yuval /* The internal is only meant to be directly called by PFs initializeing CIDs
1873da7a37aSMintz, Yuval  * for their VFs.
1883da7a37aSMintz, Yuval  */
1893946497aSMintz, Yuval static struct qed_queue_cid *
_qed_eth_queue_to_cid(struct qed_hwfn * p_hwfn,u16 opaque_fid,u32 cid,struct qed_queue_start_common_params * p_params,bool b_is_rx,struct qed_queue_cid_vf_params * p_vf_params)1903da7a37aSMintz, Yuval _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
1913da7a37aSMintz, Yuval 		      u16 opaque_fid,
1923da7a37aSMintz, Yuval 		      u32 cid,
1933946497aSMintz, Yuval 		      struct qed_queue_start_common_params *p_params,
194007bc371SMintz, Yuval 		      bool b_is_rx,
1953946497aSMintz, Yuval 		      struct qed_queue_cid_vf_params *p_vf_params)
1963da7a37aSMintz, Yuval {
1973da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
1983da7a37aSMintz, Yuval 	int rc;
1993da7a37aSMintz, Yuval 
2005f58dff9SHimanshu Jha 	p_cid = vzalloc(sizeof(*p_cid));
2013da7a37aSMintz, Yuval 	if (!p_cid)
2023da7a37aSMintz, Yuval 		return NULL;
2033da7a37aSMintz, Yuval 
2043da7a37aSMintz, Yuval 	p_cid->opaque_fid = opaque_fid;
2053da7a37aSMintz, Yuval 	p_cid->cid = cid;
206f29ffdb6SMintz, Yuval 	p_cid->p_owner = p_hwfn;
2073da7a37aSMintz, Yuval 
208f604b17dSMintz, Yuval 	/* Fill in parameters */
209f604b17dSMintz, Yuval 	p_cid->rel.vport_id = p_params->vport_id;
210f604b17dSMintz, Yuval 	p_cid->rel.queue_id = p_params->queue_id;
211f604b17dSMintz, Yuval 	p_cid->rel.stats_id = p_params->stats_id;
212f604b17dSMintz, Yuval 	p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
213007bc371SMintz, Yuval 	p_cid->b_is_rx = b_is_rx;
214f604b17dSMintz, Yuval 	p_cid->sb_idx = p_params->sb_idx;
215f604b17dSMintz, Yuval 
2163946497aSMintz, Yuval 	/* Fill-in bits related to VFs' queues if information was provided */
2173946497aSMintz, Yuval 	if (p_vf_params) {
2183946497aSMintz, Yuval 		p_cid->vfid = p_vf_params->vfid;
2193946497aSMintz, Yuval 		p_cid->vf_qid = p_vf_params->vf_qid;
2203b19f478SMintz, Yuval 		p_cid->vf_legacy = p_vf_params->vf_legacy;
2213946497aSMintz, Yuval 	} else {
2223946497aSMintz, Yuval 		p_cid->vfid = QED_QUEUE_CID_SELF;
2233946497aSMintz, Yuval 	}
2243946497aSMintz, Yuval 
2253da7a37aSMintz, Yuval 	/* Don't try calculating the absolute indices for VFs */
2263da7a37aSMintz, Yuval 	if (IS_VF(p_hwfn->cdev)) {
2273da7a37aSMintz, Yuval 		p_cid->abs = p_cid->rel;
2283da7a37aSMintz, Yuval 		goto out;
2293da7a37aSMintz, Yuval 	}
2303da7a37aSMintz, Yuval 
2313da7a37aSMintz, Yuval 	/* Calculate the engine-absolute indices of the resources.
2323da7a37aSMintz, Yuval 	 * This would guarantee they're valid later on.
2333da7a37aSMintz, Yuval 	 * In some cases [SBs] we already have the right values.
2343da7a37aSMintz, Yuval 	 */
2353da7a37aSMintz, Yuval 	rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
2363da7a37aSMintz, Yuval 	if (rc)
2373da7a37aSMintz, Yuval 		goto fail;
2383da7a37aSMintz, Yuval 
2393da7a37aSMintz, Yuval 	rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
2403da7a37aSMintz, Yuval 	if (rc)
2413da7a37aSMintz, Yuval 		goto fail;
2423da7a37aSMintz, Yuval 
2433da7a37aSMintz, Yuval 	/* In case of a PF configuring its VF's queues, the stats-id is already
2443da7a37aSMintz, Yuval 	 * absolute [since there's a single index that's suitable per-VF].
2453da7a37aSMintz, Yuval 	 */
2463946497aSMintz, Yuval 	if (p_cid->vfid == QED_QUEUE_CID_SELF) {
2473da7a37aSMintz, Yuval 		rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
2483da7a37aSMintz, Yuval 				  &p_cid->abs.stats_id);
2493da7a37aSMintz, Yuval 		if (rc)
2503da7a37aSMintz, Yuval 			goto fail;
2513da7a37aSMintz, Yuval 	} else {
2523da7a37aSMintz, Yuval 		p_cid->abs.stats_id = p_cid->rel.stats_id;
2533da7a37aSMintz, Yuval 	}
2543da7a37aSMintz, Yuval 
2553da7a37aSMintz, Yuval out:
256bbe3f233SMintz, Yuval 	/* VF-images have provided the qid_usage_idx on their own.
257bbe3f233SMintz, Yuval 	 * Otherwise, we need to allocate a unique one.
258bbe3f233SMintz, Yuval 	 */
259bbe3f233SMintz, Yuval 	if (!p_vf_params) {
260bbe3f233SMintz, Yuval 		if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid))
261bbe3f233SMintz, Yuval 			goto fail;
262bbe3f233SMintz, Yuval 	} else {
263bbe3f233SMintz, Yuval 		p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
264bbe3f233SMintz, Yuval 	}
265bbe3f233SMintz, Yuval 
2663da7a37aSMintz, Yuval 	DP_VERBOSE(p_hwfn,
2673da7a37aSMintz, Yuval 		   QED_MSG_SP,
268bbe3f233SMintz, Yuval 		   "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
2693da7a37aSMintz, Yuval 		   p_cid->opaque_fid,
2703da7a37aSMintz, Yuval 		   p_cid->cid,
2713da7a37aSMintz, Yuval 		   p_cid->rel.vport_id,
2723da7a37aSMintz, Yuval 		   p_cid->abs.vport_id,
2733da7a37aSMintz, Yuval 		   p_cid->rel.queue_id,
274bbe3f233SMintz, Yuval 		   p_cid->qid_usage_idx,
2753da7a37aSMintz, Yuval 		   p_cid->abs.queue_id,
2763da7a37aSMintz, Yuval 		   p_cid->rel.stats_id,
277f604b17dSMintz, Yuval 		   p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx);
2783da7a37aSMintz, Yuval 
2793da7a37aSMintz, Yuval 	return p_cid;
2803da7a37aSMintz, Yuval 
2813da7a37aSMintz, Yuval fail:
2823da7a37aSMintz, Yuval 	vfree(p_cid);
2833da7a37aSMintz, Yuval 	return NULL;
2843da7a37aSMintz, Yuval }
2853da7a37aSMintz, Yuval 
2863946497aSMintz, Yuval struct qed_queue_cid *
qed_eth_queue_to_cid(struct qed_hwfn * p_hwfn,u16 opaque_fid,struct qed_queue_start_common_params * p_params,bool b_is_rx,struct qed_queue_cid_vf_params * p_vf_params)2873946497aSMintz, Yuval qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
2883946497aSMintz, Yuval 		     u16 opaque_fid,
2893946497aSMintz, Yuval 		     struct qed_queue_start_common_params *p_params,
290007bc371SMintz, Yuval 		     bool b_is_rx,
2913946497aSMintz, Yuval 		     struct qed_queue_cid_vf_params *p_vf_params)
2923da7a37aSMintz, Yuval {
2933da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
29408bc8f15SMintz, Yuval 	u8 vfid = QED_CXT_PF_CID;
2953946497aSMintz, Yuval 	bool b_legacy_vf = false;
2963da7a37aSMintz, Yuval 	u32 cid = 0;
2973da7a37aSMintz, Yuval 
29808bc8f15SMintz, Yuval 	/* In case of legacy VFs, The CID can be derived from the additional
29908bc8f15SMintz, Yuval 	 * VF parameters - the VF assumes queue X uses CID X, so we can simply
30008bc8f15SMintz, Yuval 	 * use the vf_qid for this purpose as well.
30108bc8f15SMintz, Yuval 	 */
30208bc8f15SMintz, Yuval 	if (p_vf_params) {
30308bc8f15SMintz, Yuval 		vfid = p_vf_params->vfid;
30408bc8f15SMintz, Yuval 
30508bc8f15SMintz, Yuval 		if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) {
3063946497aSMintz, Yuval 			b_legacy_vf = true;
30708bc8f15SMintz, Yuval 			cid = p_vf_params->vf_qid;
30808bc8f15SMintz, Yuval 		}
30908bc8f15SMintz, Yuval 	}
31008bc8f15SMintz, Yuval 
3113da7a37aSMintz, Yuval 	/* Get a unique firmware CID for this queue, in case it's a PF.
3123da7a37aSMintz, Yuval 	 * VF's don't need a CID as the queue configuration will be done
3133da7a37aSMintz, Yuval 	 * by PF.
3143da7a37aSMintz, Yuval 	 */
3153946497aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) {
31608bc8f15SMintz, Yuval 		if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
31708bc8f15SMintz, Yuval 					 &cid, vfid)) {
3183da7a37aSMintz, Yuval 			DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
3193da7a37aSMintz, Yuval 			return NULL;
3203da7a37aSMintz, Yuval 		}
3213da7a37aSMintz, Yuval 	}
3223da7a37aSMintz, Yuval 
3233946497aSMintz, Yuval 	p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
324007bc371SMintz, Yuval 				      p_params, b_is_rx, p_vf_params);
3253946497aSMintz, Yuval 	if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf)
32608bc8f15SMintz, Yuval 		_qed_cxt_release_cid(p_hwfn, cid, vfid);
3273da7a37aSMintz, Yuval 
3283da7a37aSMintz, Yuval 	return p_cid;
3293da7a37aSMintz, Yuval }
3303da7a37aSMintz, Yuval 
3313946497aSMintz, Yuval static struct qed_queue_cid *
qed_eth_queue_to_cid_pf(struct qed_hwfn * p_hwfn,u16 opaque_fid,bool b_is_rx,struct qed_queue_start_common_params * p_params)3323946497aSMintz, Yuval qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn,
3333946497aSMintz, Yuval 			u16 opaque_fid,
334007bc371SMintz, Yuval 			bool b_is_rx,
3353946497aSMintz, Yuval 			struct qed_queue_start_common_params *p_params)
3363946497aSMintz, Yuval {
337007bc371SMintz, Yuval 	return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx,
3383946497aSMintz, Yuval 				    NULL);
3393946497aSMintz, Yuval }
3403946497aSMintz, Yuval 
qed_sp_eth_vport_start(struct qed_hwfn * p_hwfn,struct qed_sp_vport_start_params * p_params)341dacd88d6SYuval Mintz int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
342088c8618SManish Chopra 			   struct qed_sp_vport_start_params *p_params)
343cee4d264SManish Chopra {
344cee4d264SManish Chopra 	struct vport_start_ramrod_data *p_ramrod = NULL;
345a0f3266fSAlexander Lobakin 	struct eth_vport_tpa_param *tpa_param;
346cee4d264SManish Chopra 	struct qed_spq_entry *p_ent =  NULL;
34706f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
3485ab90341SAlexander Lobakin 	u16 min_size, rx_mode = 0;
349dacd88d6SYuval Mintz 	u8 abs_vport_id = 0;
3507df0a6a3SColin Ian King 	int rc;
351cee4d264SManish Chopra 
352088c8618SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
3531a635e48SYuval Mintz 	if (rc)
354cee4d264SManish Chopra 		return rc;
355cee4d264SManish Chopra 
35606f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
35706f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
358088c8618SManish Chopra 	init_data.opaque_fid = p_params->opaque_fid;
35906f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
360cee4d264SManish Chopra 
361cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
362cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_START,
36306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
364cee4d264SManish Chopra 	if (rc)
365cee4d264SManish Chopra 		return rc;
366cee4d264SManish Chopra 
367cee4d264SManish Chopra 	p_ramrod		= &p_ent->ramrod.vport_start;
368cee4d264SManish Chopra 	p_ramrod->vport_id	= abs_vport_id;
369cee4d264SManish Chopra 
370088c8618SManish Chopra 	p_ramrod->mtu			= cpu_to_le16(p_params->mtu);
371c78c70faSSudarsana Reddy Kalluru 	p_ramrod->handle_ptp_pkts	= p_params->handle_ptp_pkts;
372088c8618SManish Chopra 	p_ramrod->inner_vlan_removal_en	= p_params->remove_inner_vlan;
373088c8618SManish Chopra 	p_ramrod->drop_ttl0_en		= p_params->drop_ttl0;
374e6bd8923SYuval Mintz 	p_ramrod->untagged		= p_params->only_untagged;
375cee4d264SManish Chopra 
376cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
377cee4d264SManish Chopra 	SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
378cee4d264SManish Chopra 
379cee4d264SManish Chopra 	p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
380cee4d264SManish Chopra 
381cee4d264SManish Chopra 	/* TPA related fields */
382a0f3266fSAlexander Lobakin 	tpa_param = &p_ramrod->tpa_param;
383a0f3266fSAlexander Lobakin 	memset(tpa_param, 0, sizeof(*tpa_param));
384cee4d264SManish Chopra 
385a0f3266fSAlexander Lobakin 	tpa_param->max_buff_num = p_params->max_buffers_per_cqe;
386088c8618SManish Chopra 
387088c8618SManish Chopra 	switch (p_params->tpa_mode) {
388088c8618SManish Chopra 	case QED_TPA_MODE_GRO:
3895ab90341SAlexander Lobakin 		min_size = p_params->mtu / 2;
3905ab90341SAlexander Lobakin 
391a0f3266fSAlexander Lobakin 		tpa_param->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
3925ab90341SAlexander Lobakin 		tpa_param->tpa_max_size = cpu_to_le16(U16_MAX);
3935ab90341SAlexander Lobakin 		tpa_param->tpa_min_size_to_cont = cpu_to_le16(min_size);
3945ab90341SAlexander Lobakin 		tpa_param->tpa_min_size_to_start = cpu_to_le16(min_size);
395a0f3266fSAlexander Lobakin 		tpa_param->tpa_ipv4_en_flg = 1;
396a0f3266fSAlexander Lobakin 		tpa_param->tpa_ipv6_en_flg = 1;
397a0f3266fSAlexander Lobakin 		tpa_param->tpa_pkt_split_flg = 1;
398a0f3266fSAlexander Lobakin 		tpa_param->tpa_gro_consistent_flg = 1;
399134639e9SGustavo A. R. Silva 		break;
400088c8618SManish Chopra 	default:
401088c8618SManish Chopra 		break;
402088c8618SManish Chopra 	}
403088c8618SManish Chopra 
404831bfb0eSYuval Mintz 	p_ramrod->tx_switching_en = p_params->tx_switching;
405831bfb0eSYuval Mintz 
40611a85d75SYuval Mintz 	p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
40711a85d75SYuval Mintz 	p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
40811a85d75SYuval Mintz 
409cee4d264SManish Chopra 	/* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
410cee4d264SManish Chopra 	p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
411088c8618SManish Chopra 						  p_params->concrete_fid);
412cee4d264SManish Chopra 
413cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
414cee4d264SManish Chopra }
415cee4d264SManish Chopra 
qed_sp_vport_start(struct qed_hwfn * p_hwfn,struct qed_sp_vport_start_params * p_params)416ba56947aSBaoyou Xie static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
417dacd88d6SYuval Mintz 			      struct qed_sp_vport_start_params *p_params)
418dacd88d6SYuval Mintz {
419dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
420dacd88d6SYuval Mintz 		return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
421dacd88d6SYuval Mintz 					     p_params->mtu,
422dacd88d6SYuval Mintz 					     p_params->remove_inner_vlan,
423dacd88d6SYuval Mintz 					     p_params->tpa_mode,
42408feecd7SYuval Mintz 					     p_params->max_buffers_per_cqe,
42508feecd7SYuval Mintz 					     p_params->only_untagged);
426dacd88d6SYuval Mintz 	}
427dacd88d6SYuval Mintz 
428dacd88d6SYuval Mintz 	return qed_sp_eth_vport_start(p_hwfn, p_params);
429dacd88d6SYuval Mintz }
430dacd88d6SYuval Mintz 
431cee4d264SManish Chopra static int
qed_sp_vport_update_rss(struct qed_hwfn * p_hwfn,struct vport_update_ramrod_data * p_ramrod,struct qed_rss_params * p_rss)432cee4d264SManish Chopra qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
433cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
434f29ffdb6SMintz, Yuval 			struct qed_rss_params *p_rss)
435cee4d264SManish Chopra {
436f29ffdb6SMintz, Yuval 	struct eth_vport_rss_config *p_config;
437f29ffdb6SMintz, Yuval 	u16 capabilities = 0;
438f29ffdb6SMintz, Yuval 	int i, table_size;
439f29ffdb6SMintz, Yuval 	int rc = 0;
440cee4d264SManish Chopra 
441f29ffdb6SMintz, Yuval 	if (!p_rss) {
442cee4d264SManish Chopra 		p_ramrod->common.update_rss_flg = 0;
443cee4d264SManish Chopra 		return rc;
444cee4d264SManish Chopra 	}
445f29ffdb6SMintz, Yuval 	p_config = &p_ramrod->rss_config;
446cee4d264SManish Chopra 
447f29ffdb6SMintz, Yuval 	BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
448cee4d264SManish Chopra 
449f29ffdb6SMintz, Yuval 	rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
450cee4d264SManish Chopra 	if (rc)
451cee4d264SManish Chopra 		return rc;
452cee4d264SManish Chopra 
453f29ffdb6SMintz, Yuval 	p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
454f29ffdb6SMintz, Yuval 	p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
455f29ffdb6SMintz, Yuval 	p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
456f29ffdb6SMintz, Yuval 	p_config->update_rss_key = p_rss->update_rss_key;
457cee4d264SManish Chopra 
458f29ffdb6SMintz, Yuval 	p_config->rss_mode = p_rss->rss_enable ?
459cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_REGULAR :
460cee4d264SManish Chopra 			     ETH_VPORT_RSS_MODE_DISABLED;
461cee4d264SManish Chopra 
462cee4d264SManish Chopra 	SET_FIELD(capabilities,
463cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
464f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4));
465cee4d264SManish Chopra 	SET_FIELD(capabilities,
466cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
467f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6));
468cee4d264SManish Chopra 	SET_FIELD(capabilities,
469cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
470f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
471cee4d264SManish Chopra 	SET_FIELD(capabilities,
472cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
473f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
474cee4d264SManish Chopra 	SET_FIELD(capabilities,
475cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
476f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
477cee4d264SManish Chopra 	SET_FIELD(capabilities,
478cee4d264SManish Chopra 		  ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
479f29ffdb6SMintz, Yuval 		  !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
480f29ffdb6SMintz, Yuval 	p_config->tbl_size = p_rss->rss_table_size_log;
481cee4d264SManish Chopra 
482f29ffdb6SMintz, Yuval 	p_config->capabilities = cpu_to_le16(capabilities);
483cee4d264SManish Chopra 
484cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
485cee4d264SManish Chopra 		   "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
486cee4d264SManish Chopra 		   p_ramrod->common.update_rss_flg,
487f29ffdb6SMintz, Yuval 		   p_config->rss_mode,
488f29ffdb6SMintz, Yuval 		   p_config->update_rss_capabilities,
489f29ffdb6SMintz, Yuval 		   p_config->capabilities,
490f29ffdb6SMintz, Yuval 		   p_config->update_rss_ind_table, p_config->update_rss_key);
491cee4d264SManish Chopra 
492f29ffdb6SMintz, Yuval 	table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
493f29ffdb6SMintz, Yuval 			   1 << p_config->tbl_size);
494f29ffdb6SMintz, Yuval 	for (i = 0; i < table_size; i++) {
495f29ffdb6SMintz, Yuval 		struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
496cee4d264SManish Chopra 
497f29ffdb6SMintz, Yuval 		if (!p_queue)
498f29ffdb6SMintz, Yuval 			return -EINVAL;
499f29ffdb6SMintz, Yuval 
500f29ffdb6SMintz, Yuval 		p_config->indirection_table[i] =
501f29ffdb6SMintz, Yuval 		    cpu_to_le16(p_queue->abs.queue_id);
502f29ffdb6SMintz, Yuval 	}
503f29ffdb6SMintz, Yuval 
504f29ffdb6SMintz, Yuval 	DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
505f29ffdb6SMintz, Yuval 		   "Configured RSS indirection table [%d entries]:\n",
506f29ffdb6SMintz, Yuval 		   table_size);
507f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
508f29ffdb6SMintz, Yuval 		DP_VERBOSE(p_hwfn,
509f29ffdb6SMintz, Yuval 			   NETIF_MSG_IFUP,
510f29ffdb6SMintz, Yuval 			   "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
511f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i]),
512f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 1]),
513f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 2]),
514f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 3]),
515f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 4]),
516f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 5]),
517f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 6]),
518f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 7]),
519f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 8]),
520f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 9]),
521f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 10]),
522f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 11]),
523f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 12]),
524f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 13]),
525f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 14]),
526f29ffdb6SMintz, Yuval 			   le16_to_cpu(p_config->indirection_table[i + 15]));
527cee4d264SManish Chopra 	}
528cee4d264SManish Chopra 
529cee4d264SManish Chopra 	for (i = 0; i < 10; i++)
530f29ffdb6SMintz, Yuval 		p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
531cee4d264SManish Chopra 
532cee4d264SManish Chopra 	return rc;
533cee4d264SManish Chopra }
534cee4d264SManish Chopra 
535cee4d264SManish Chopra static void
qed_sp_update_accept_mode(struct qed_hwfn * p_hwfn,struct vport_update_ramrod_data * p_ramrod,struct qed_filter_accept_flags accept_flags)536cee4d264SManish Chopra qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
537cee4d264SManish Chopra 			  struct vport_update_ramrod_data *p_ramrod,
538cee4d264SManish Chopra 			  struct qed_filter_accept_flags accept_flags)
539cee4d264SManish Chopra {
540cee4d264SManish Chopra 	p_ramrod->common.update_rx_mode_flg =
541cee4d264SManish Chopra 		accept_flags.update_rx_mode_config;
542cee4d264SManish Chopra 
543cee4d264SManish Chopra 	p_ramrod->common.update_tx_mode_flg =
544cee4d264SManish Chopra 		accept_flags.update_tx_mode_config;
545cee4d264SManish Chopra 
546cee4d264SManish Chopra 	/* Set Rx mode accept flags */
547cee4d264SManish Chopra 	if (p_ramrod->common.update_rx_mode_flg) {
548cee4d264SManish Chopra 		u8 accept_filter = accept_flags.rx_accept_filter;
549cee4d264SManish Chopra 		u16 state = 0;
550cee4d264SManish Chopra 
551cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
552cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
553cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
554cee4d264SManish Chopra 
555cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
556cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
557cee4d264SManish Chopra 
558cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
559cee4d264SManish Chopra 			  !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
560cee4d264SManish Chopra 			    !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
561cee4d264SManish Chopra 
562cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
563cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
564cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
565cee4d264SManish Chopra 
566cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
567cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
568cee4d264SManish Chopra 
569d52c89f1SMichal Kalderon 		SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI,
570d52c89f1SMichal Kalderon 			  !!(accept_filter & QED_ACCEPT_ANY_VNI));
571d52c89f1SMichal Kalderon 
572cee4d264SManish Chopra 		p_ramrod->rx_mode.state = cpu_to_le16(state);
573cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
574cee4d264SManish Chopra 			   "p_ramrod->rx_mode.state = 0x%x\n", state);
575cee4d264SManish Chopra 	}
576cee4d264SManish Chopra 
577cee4d264SManish Chopra 	/* Set Tx mode accept flags */
578cee4d264SManish Chopra 	if (p_ramrod->common.update_tx_mode_flg) {
579cee4d264SManish Chopra 		u8 accept_filter = accept_flags.tx_accept_filter;
580cee4d264SManish Chopra 		u16 state = 0;
581cee4d264SManish Chopra 
582cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
583cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
584cee4d264SManish Chopra 
585cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
586cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_NONE));
587cee4d264SManish Chopra 
588cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
589cee4d264SManish Chopra 			  (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
590cee4d264SManish Chopra 			   !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
591cee4d264SManish Chopra 
5929e71a15dSManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
5939e71a15dSManish Chopra 			  (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
5949e71a15dSManish Chopra 			   !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
5959e71a15dSManish Chopra 
596cee4d264SManish Chopra 		SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
597cee4d264SManish Chopra 			  !!(accept_filter & QED_ACCEPT_BCAST));
598cee4d264SManish Chopra 
599cee4d264SManish Chopra 		p_ramrod->tx_mode.state = cpu_to_le16(state);
600cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
601cee4d264SManish Chopra 			   "p_ramrod->tx_mode.state = 0x%x\n", state);
602cee4d264SManish Chopra 	}
603cee4d264SManish Chopra }
604cee4d264SManish Chopra 
605cee4d264SManish Chopra static void
qed_sp_vport_update_sge_tpa(struct qed_hwfn * p_hwfn,struct vport_update_ramrod_data * p_ramrod,const struct qed_sge_tpa_params * param)60617b235c1SYuval Mintz qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
60717b235c1SYuval Mintz 			    struct vport_update_ramrod_data *p_ramrod,
608a0f3266fSAlexander Lobakin 			    const struct qed_sge_tpa_params *param)
60917b235c1SYuval Mintz {
610a0f3266fSAlexander Lobakin 	struct eth_vport_tpa_param *tpa;
61117b235c1SYuval Mintz 
612a0f3266fSAlexander Lobakin 	if (!param) {
61317b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
61417b235c1SYuval Mintz 		p_ramrod->common.update_tpa_en_flg = 0;
61517b235c1SYuval Mintz 		p_ramrod->common.update_tpa_param_flg = 0;
61617b235c1SYuval Mintz 		return;
61717b235c1SYuval Mintz 	}
61817b235c1SYuval Mintz 
619a0f3266fSAlexander Lobakin 	p_ramrod->common.update_tpa_en_flg = param->update_tpa_en_flg;
620a0f3266fSAlexander Lobakin 	tpa = &p_ramrod->tpa_param;
621a0f3266fSAlexander Lobakin 	tpa->tpa_ipv4_en_flg = param->tpa_ipv4_en_flg;
622a0f3266fSAlexander Lobakin 	tpa->tpa_ipv6_en_flg = param->tpa_ipv6_en_flg;
623a0f3266fSAlexander Lobakin 	tpa->tpa_ipv4_tunn_en_flg = param->tpa_ipv4_tunn_en_flg;
624a0f3266fSAlexander Lobakin 	tpa->tpa_ipv6_tunn_en_flg = param->tpa_ipv6_tunn_en_flg;
62517b235c1SYuval Mintz 
626a0f3266fSAlexander Lobakin 	p_ramrod->common.update_tpa_param_flg = param->update_tpa_param_flg;
627a0f3266fSAlexander Lobakin 	tpa->max_buff_num = param->max_buffers_per_cqe;
628a0f3266fSAlexander Lobakin 	tpa->tpa_pkt_split_flg = param->tpa_pkt_split_flg;
629a0f3266fSAlexander Lobakin 	tpa->tpa_hdr_data_split_flg = param->tpa_hdr_data_split_flg;
630a0f3266fSAlexander Lobakin 	tpa->tpa_gro_consistent_flg = param->tpa_gro_consistent_flg;
631a0f3266fSAlexander Lobakin 	tpa->tpa_max_aggs_num = param->tpa_max_aggs_num;
6325ab90341SAlexander Lobakin 	tpa->tpa_max_size = cpu_to_le16(param->tpa_max_size);
6335ab90341SAlexander Lobakin 	tpa->tpa_min_size_to_start = cpu_to_le16(param->tpa_min_size_to_start);
6345ab90341SAlexander Lobakin 	tpa->tpa_min_size_to_cont = cpu_to_le16(param->tpa_min_size_to_cont);
63517b235c1SYuval Mintz }
63617b235c1SYuval Mintz 
63717b235c1SYuval Mintz static void
qed_sp_update_mcast_bin(struct qed_hwfn * p_hwfn,struct vport_update_ramrod_data * p_ramrod,struct qed_sp_vport_update_params * p_params)638cee4d264SManish Chopra qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
639cee4d264SManish Chopra 			struct vport_update_ramrod_data *p_ramrod,
640cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params)
641cee4d264SManish Chopra {
642cee4d264SManish Chopra 	int i;
643cee4d264SManish Chopra 
644cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
645cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
646cee4d264SManish Chopra 
64783aeb933SYuval Mintz 	if (!p_params->update_approx_mcast_flg)
64883aeb933SYuval Mintz 		return;
64983aeb933SYuval Mintz 
650cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
651cee4d264SManish Chopra 	for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
65225c020a9SSudarsana Reddy Kalluru 		u32 *p_bins = p_params->bins;
653cee4d264SManish Chopra 
65483aeb933SYuval Mintz 		p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
655cee4d264SManish Chopra 	}
656cee4d264SManish Chopra }
657cee4d264SManish Chopra 
qed_sp_vport_update(struct qed_hwfn * p_hwfn,struct qed_sp_vport_update_params * p_params,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)658dacd88d6SYuval Mintz int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
659cee4d264SManish Chopra 			struct qed_sp_vport_update_params *p_params,
660cee4d264SManish Chopra 			enum spq_mode comp_mode,
661cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
662cee4d264SManish Chopra {
663cee4d264SManish Chopra 	struct qed_rss_params *p_rss_params = p_params->rss_params;
664cee4d264SManish Chopra 	struct vport_update_ramrod_data_cmn *p_cmn;
66506f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
666cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
667cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
66817b235c1SYuval Mintz 	u8 abs_vport_id = 0, val;
669cee4d264SManish Chopra 	int rc = -EINVAL;
670cee4d264SManish Chopra 
671dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev)) {
672dacd88d6SYuval Mintz 		rc = qed_vf_pf_vport_update(p_hwfn, p_params);
673dacd88d6SYuval Mintz 		return rc;
674dacd88d6SYuval Mintz 	}
675dacd88d6SYuval Mintz 
676cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
6771a635e48SYuval Mintz 	if (rc)
678cee4d264SManish Chopra 		return rc;
679cee4d264SManish Chopra 
68006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
68106f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
68206f56b81SYuval Mintz 	init_data.opaque_fid = p_params->opaque_fid;
68306f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
68406f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
685cee4d264SManish Chopra 
686cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
687cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
68806f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
689cee4d264SManish Chopra 	if (rc)
690cee4d264SManish Chopra 		return rc;
691cee4d264SManish Chopra 
692cee4d264SManish Chopra 	/* Copy input params to ramrod according to FW struct */
693cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
694cee4d264SManish Chopra 	p_cmn = &p_ramrod->common;
695cee4d264SManish Chopra 
696cee4d264SManish Chopra 	p_cmn->vport_id = abs_vport_id;
697cee4d264SManish Chopra 	p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
698cee4d264SManish Chopra 	p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
699cee4d264SManish Chopra 	p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
700cee4d264SManish Chopra 	p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
7013f9b4a69SYuval Mintz 	p_cmn->accept_any_vlan = p_params->accept_any_vlan;
70283aeb933SYuval Mintz 	val = p_params->update_accept_any_vlan_flg;
70383aeb933SYuval Mintz 	p_cmn->update_accept_any_vlan_flg = val;
70417b235c1SYuval Mintz 
70517b235c1SYuval Mintz 	p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
70617b235c1SYuval Mintz 	val = p_params->update_inner_vlan_removal_flg;
70717b235c1SYuval Mintz 	p_cmn->update_inner_vlan_removal_en_flg = val;
70808feecd7SYuval Mintz 
70908feecd7SYuval Mintz 	p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
71008feecd7SYuval Mintz 	val = p_params->update_default_vlan_enable_flg;
71108feecd7SYuval Mintz 	p_cmn->update_default_vlan_en_flg = val;
71208feecd7SYuval Mintz 
71308feecd7SYuval Mintz 	p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
71408feecd7SYuval Mintz 	p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
71508feecd7SYuval Mintz 
71608feecd7SYuval Mintz 	p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
71708feecd7SYuval Mintz 
71817b235c1SYuval Mintz 	p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
71917b235c1SYuval Mintz 	p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
72017b235c1SYuval Mintz 
7216ddc7608SYuval Mintz 	p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
7226ddc7608SYuval Mintz 	val = p_params->update_anti_spoofing_en_flg;
7236ddc7608SYuval Mintz 	p_ramrod->common.update_anti_spoofing_en_flg = val;
7246ddc7608SYuval Mintz 
725cee4d264SManish Chopra 	rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
726cee4d264SManish Chopra 	if (rc) {
727fb5e7438SDenis Bolotin 		qed_sp_destroy_request(p_hwfn, p_ent);
728cee4d264SManish Chopra 		return rc;
729cee4d264SManish Chopra 	}
730cee4d264SManish Chopra 
731ff929696SManish Chopra 	if (p_params->update_ctl_frame_check) {
732ff929696SManish Chopra 		p_cmn->ctl_frame_mac_check_en = p_params->mac_chk_en;
733ff929696SManish Chopra 		p_cmn->ctl_frame_ethtype_check_en = p_params->ethtype_chk_en;
734ff929696SManish Chopra 	}
735ff929696SManish Chopra 
736cee4d264SManish Chopra 	/* Update mcast bins for VFs, PF doesn't use this functionality */
737cee4d264SManish Chopra 	qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
738cee4d264SManish Chopra 
739cee4d264SManish Chopra 	qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
74017b235c1SYuval Mintz 	qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
741cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
742cee4d264SManish Chopra }
743cee4d264SManish Chopra 
qed_sp_vport_stop(struct qed_hwfn * p_hwfn,u16 opaque_fid,u8 vport_id)744dacd88d6SYuval Mintz int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
745cee4d264SManish Chopra {
746cee4d264SManish Chopra 	struct vport_stop_ramrod_data *p_ramrod;
74706f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
748cee4d264SManish Chopra 	struct qed_spq_entry *p_ent;
749cee4d264SManish Chopra 	u8 abs_vport_id = 0;
750cee4d264SManish Chopra 	int rc;
751cee4d264SManish Chopra 
752dacd88d6SYuval Mintz 	if (IS_VF(p_hwfn->cdev))
753dacd88d6SYuval Mintz 		return qed_vf_pf_vport_stop(p_hwfn);
754dacd88d6SYuval Mintz 
755cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
7561a635e48SYuval Mintz 	if (rc)
757cee4d264SManish Chopra 		return rc;
758cee4d264SManish Chopra 
75906f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
76006f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
76106f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
76206f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
763cee4d264SManish Chopra 
764cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
765cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_STOP,
76606f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
767cee4d264SManish Chopra 	if (rc)
768cee4d264SManish Chopra 		return rc;
769cee4d264SManish Chopra 
770cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_stop;
771cee4d264SManish Chopra 	p_ramrod->vport_id = abs_vport_id;
772cee4d264SManish Chopra 
773cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
774cee4d264SManish Chopra }
775cee4d264SManish Chopra 
776dacd88d6SYuval Mintz static int
qed_vf_pf_accept_flags(struct qed_hwfn * p_hwfn,struct qed_filter_accept_flags * p_accept_flags)777dacd88d6SYuval Mintz qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
778dacd88d6SYuval Mintz 		       struct qed_filter_accept_flags *p_accept_flags)
779dacd88d6SYuval Mintz {
780dacd88d6SYuval Mintz 	struct qed_sp_vport_update_params s_params;
781dacd88d6SYuval Mintz 
782dacd88d6SYuval Mintz 	memset(&s_params, 0, sizeof(s_params));
783dacd88d6SYuval Mintz 	memcpy(&s_params.accept_flags, p_accept_flags,
784dacd88d6SYuval Mintz 	       sizeof(struct qed_filter_accept_flags));
785dacd88d6SYuval Mintz 
786dacd88d6SYuval Mintz 	return qed_vf_pf_vport_update(p_hwfn, &s_params);
787dacd88d6SYuval Mintz }
788dacd88d6SYuval Mintz 
qed_filter_accept_cmd(struct qed_dev * cdev,u8 vport,struct qed_filter_accept_flags accept_flags,u8 update_accept_any_vlan,u8 accept_any_vlan,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)789cee4d264SManish Chopra static int qed_filter_accept_cmd(struct qed_dev *cdev,
790cee4d264SManish Chopra 				 u8 vport,
791cee4d264SManish Chopra 				 struct qed_filter_accept_flags accept_flags,
7923f9b4a69SYuval Mintz 				 u8 update_accept_any_vlan,
7933f9b4a69SYuval Mintz 				 u8 accept_any_vlan,
794cee4d264SManish Chopra 				 enum spq_mode comp_mode,
795cee4d264SManish Chopra 				 struct qed_spq_comp_cb *p_comp_data)
796cee4d264SManish Chopra {
797cee4d264SManish Chopra 	struct qed_sp_vport_update_params vport_update_params;
798cee4d264SManish Chopra 	int i, rc;
799cee4d264SManish Chopra 
800cee4d264SManish Chopra 	/* Prepare and send the vport rx_mode change */
801cee4d264SManish Chopra 	memset(&vport_update_params, 0, sizeof(vport_update_params));
802cee4d264SManish Chopra 	vport_update_params.vport_id = vport;
803cee4d264SManish Chopra 	vport_update_params.accept_flags = accept_flags;
8043f9b4a69SYuval Mintz 	vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
8053f9b4a69SYuval Mintz 	vport_update_params.accept_any_vlan = accept_any_vlan;
806cee4d264SManish Chopra 
807cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
808cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
809cee4d264SManish Chopra 
810cee4d264SManish Chopra 		vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
811cee4d264SManish Chopra 
812dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
813dacd88d6SYuval Mintz 			rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
814dacd88d6SYuval Mintz 			if (rc)
815dacd88d6SYuval Mintz 				return rc;
816dacd88d6SYuval Mintz 			continue;
817dacd88d6SYuval Mintz 		}
818dacd88d6SYuval Mintz 
819cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
820cee4d264SManish Chopra 					 comp_mode, p_comp_data);
8211a635e48SYuval Mintz 		if (rc) {
822cee4d264SManish Chopra 			DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
823cee4d264SManish Chopra 			return rc;
824cee4d264SManish Chopra 		}
825cee4d264SManish Chopra 
826cee4d264SManish Chopra 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
827cee4d264SManish Chopra 			   "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
828cee4d264SManish Chopra 			   accept_flags.rx_accept_filter,
829cee4d264SManish Chopra 			   accept_flags.tx_accept_filter);
8303f9b4a69SYuval Mintz 		if (update_accept_any_vlan)
8313f9b4a69SYuval Mintz 			DP_VERBOSE(p_hwfn, QED_MSG_SP,
8323f9b4a69SYuval Mintz 				   "accept_any_vlan=%d configured\n",
8333f9b4a69SYuval Mintz 				   accept_any_vlan);
834cee4d264SManish Chopra 	}
835cee4d264SManish Chopra 
836cee4d264SManish Chopra 	return 0;
837cee4d264SManish Chopra }
838cee4d264SManish Chopra 
qed_eth_rxq_start_ramrod(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid,u16 bd_max_bytes,dma_addr_t bd_chain_phys_addr,dma_addr_t cqe_pbl_addr,u16 cqe_pbl_size)8393da7a37aSMintz, Yuval int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
8403da7a37aSMintz, Yuval 			     struct qed_queue_cid *p_cid,
841cee4d264SManish Chopra 			     u16 bd_max_bytes,
842cee4d264SManish Chopra 			     dma_addr_t bd_chain_phys_addr,
8433da7a37aSMintz, Yuval 			     dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
844cee4d264SManish Chopra {
845cee4d264SManish Chopra 	struct rx_queue_start_ramrod_data *p_ramrod = NULL;
846cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
84706f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
848cee4d264SManish Chopra 	int rc = -EINVAL;
849cee4d264SManish Chopra 
850cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
8513da7a37aSMintz, Yuval 		   "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
8523da7a37aSMintz, Yuval 		   p_cid->opaque_fid, p_cid->cid,
853f604b17dSMintz, Yuval 		   p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id);
854cee4d264SManish Chopra 
85506f56b81SYuval Mintz 	/* Get SPQ entry */
85606f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
8573da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
8583da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
85906f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
860cee4d264SManish Chopra 
861cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
862cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_START,
86306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
864cee4d264SManish Chopra 	if (rc)
865cee4d264SManish Chopra 		return rc;
866cee4d264SManish Chopra 
867cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_start;
868cee4d264SManish Chopra 
869f604b17dSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
870f604b17dSMintz, Yuval 	p_ramrod->sb_index = p_cid->sb_idx;
8713da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
8723da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
8733da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
874cee4d264SManish Chopra 	p_ramrod->complete_cqe_flg = 0;
875cee4d264SManish Chopra 	p_ramrod->complete_event_flg = 1;
876cee4d264SManish Chopra 
877cee4d264SManish Chopra 	p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
87894494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
879cee4d264SManish Chopra 
880cee4d264SManish Chopra 	p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
88194494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
882cee4d264SManish Chopra 
8833946497aSMintz, Yuval 	if (p_cid->vfid != QED_QUEUE_CID_SELF) {
8843b19f478SMintz, Yuval 		bool b_legacy_vf = !!(p_cid->vf_legacy &
8853b19f478SMintz, Yuval 				      QED_QCID_LEGACY_VF_RX_PROD);
8863b19f478SMintz, Yuval 
8873da7a37aSMintz, Yuval 		p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
888351a4dedSYuval Mintz 		DP_VERBOSE(p_hwfn, QED_MSG_SP,
889a044df83SYuval Mintz 			   "Queue%s is meant for VF rxq[%02x]\n",
8903b19f478SMintz, Yuval 			   b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid);
8913b19f478SMintz, Yuval 		p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
892a044df83SYuval Mintz 	}
893cee4d264SManish Chopra 
894351a4dedSYuval Mintz 	return qed_spq_post(p_hwfn, p_ent, NULL);
895cee4d264SManish Chopra }
896cee4d264SManish Chopra 
897cee4d264SManish Chopra static int
qed_eth_pf_rx_queue_start(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid,u16 bd_max_bytes,dma_addr_t bd_chain_phys_addr,dma_addr_t cqe_pbl_addr,u16 cqe_pbl_size,void __iomem ** pp_prod)8983da7a37aSMintz, Yuval qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
8993da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
900cee4d264SManish Chopra 			  u16 bd_max_bytes,
901cee4d264SManish Chopra 			  dma_addr_t bd_chain_phys_addr,
902cee4d264SManish Chopra 			  dma_addr_t cqe_pbl_addr,
903dacd88d6SYuval Mintz 			  u16 cqe_pbl_size, void __iomem **pp_prod)
904cee4d264SManish Chopra {
905b21290b7SYuval Mintz 	u32 init_prod_val = 0;
906cee4d264SManish Chopra 
907e2dbc223SPrabhakar Kushwaha 	*pp_prod = (u8 __iomem *)
908e2dbc223SPrabhakar Kushwaha 	    p_hwfn->regview +
909e2dbc223SPrabhakar Kushwaha 	    GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_MSDM_RAM,
910e2dbc223SPrabhakar Kushwaha 			     MSTORM_ETH_PF_PRODS, p_cid->abs.queue_id);
911cee4d264SManish Chopra 
912cee4d264SManish Chopra 	/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
913b21290b7SYuval Mintz 	__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
914cee4d264SManish Chopra 			  (u32 *)(&init_prod_val));
915cee4d264SManish Chopra 
9163da7a37aSMintz, Yuval 	return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
917cee4d264SManish Chopra 					bd_max_bytes,
918cee4d264SManish Chopra 					bd_chain_phys_addr,
9193da7a37aSMintz, Yuval 					cqe_pbl_addr, cqe_pbl_size);
9203da7a37aSMintz, Yuval }
921cee4d264SManish Chopra 
9223da7a37aSMintz, Yuval static int
qed_eth_rx_queue_start(struct qed_hwfn * p_hwfn,u16 opaque_fid,struct qed_queue_start_common_params * p_params,u16 bd_max_bytes,dma_addr_t bd_chain_phys_addr,dma_addr_t cqe_pbl_addr,u16 cqe_pbl_size,struct qed_rxq_start_ret_params * p_ret_params)9233da7a37aSMintz, Yuval qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
9243da7a37aSMintz, Yuval 		       u16 opaque_fid,
9253da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
9263da7a37aSMintz, Yuval 		       u16 bd_max_bytes,
9273da7a37aSMintz, Yuval 		       dma_addr_t bd_chain_phys_addr,
9283da7a37aSMintz, Yuval 		       dma_addr_t cqe_pbl_addr,
9293da7a37aSMintz, Yuval 		       u16 cqe_pbl_size,
9303da7a37aSMintz, Yuval 		       struct qed_rxq_start_ret_params *p_ret_params)
9313da7a37aSMintz, Yuval {
9323da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
9333da7a37aSMintz, Yuval 	int rc;
9343da7a37aSMintz, Yuval 
9353da7a37aSMintz, Yuval 	/* Allocate a CID for the queue */
936007bc371SMintz, Yuval 	p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params);
9373da7a37aSMintz, Yuval 	if (!p_cid)
9383da7a37aSMintz, Yuval 		return -ENOMEM;
9393da7a37aSMintz, Yuval 
9403da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev)) {
9413da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
9423da7a37aSMintz, Yuval 					       bd_max_bytes,
9433da7a37aSMintz, Yuval 					       bd_chain_phys_addr,
9443da7a37aSMintz, Yuval 					       cqe_pbl_addr, cqe_pbl_size,
9453da7a37aSMintz, Yuval 					       &p_ret_params->p_prod);
9463da7a37aSMintz, Yuval 	} else {
9473da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
9483da7a37aSMintz, Yuval 					 bd_max_bytes,
9493da7a37aSMintz, Yuval 					 bd_chain_phys_addr,
9503da7a37aSMintz, Yuval 					 cqe_pbl_addr,
9513da7a37aSMintz, Yuval 					 cqe_pbl_size, &p_ret_params->p_prod);
9523da7a37aSMintz, Yuval 	}
9533da7a37aSMintz, Yuval 
9543da7a37aSMintz, Yuval 	/* Provide the caller with a reference to as handler */
9551a635e48SYuval Mintz 	if (rc)
9563da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
9573da7a37aSMintz, Yuval 	else
9583da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
959cee4d264SManish Chopra 
960cee4d264SManish Chopra 	return rc;
961cee4d264SManish Chopra }
962cee4d264SManish Chopra 
qed_sp_eth_rx_queues_update(struct qed_hwfn * p_hwfn,void ** pp_rxq_handles,u8 num_rxqs,u8 complete_cqe_flg,u8 complete_event_flg,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)96317b235c1SYuval Mintz int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
9643da7a37aSMintz, Yuval 				void **pp_rxq_handles,
96517b235c1SYuval Mintz 				u8 num_rxqs,
96617b235c1SYuval Mintz 				u8 complete_cqe_flg,
96717b235c1SYuval Mintz 				u8 complete_event_flg,
96817b235c1SYuval Mintz 				enum spq_mode comp_mode,
96917b235c1SYuval Mintz 				struct qed_spq_comp_cb *p_comp_data)
97017b235c1SYuval Mintz {
97117b235c1SYuval Mintz 	struct rx_queue_update_ramrod_data *p_ramrod = NULL;
97217b235c1SYuval Mintz 	struct qed_spq_entry *p_ent = NULL;
97317b235c1SYuval Mintz 	struct qed_sp_init_data init_data;
9743da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
97517b235c1SYuval Mintz 	int rc = -EINVAL;
97617b235c1SYuval Mintz 	u8 i;
97717b235c1SYuval Mintz 
97817b235c1SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
97917b235c1SYuval Mintz 	init_data.comp_mode = comp_mode;
98017b235c1SYuval Mintz 	init_data.p_comp_data = p_comp_data;
98117b235c1SYuval Mintz 
98217b235c1SYuval Mintz 	for (i = 0; i < num_rxqs; i++) {
9833da7a37aSMintz, Yuval 		p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
98417b235c1SYuval Mintz 
98517b235c1SYuval Mintz 		/* Get SPQ entry */
9863da7a37aSMintz, Yuval 		init_data.cid = p_cid->cid;
9873da7a37aSMintz, Yuval 		init_data.opaque_fid = p_cid->opaque_fid;
98817b235c1SYuval Mintz 
98917b235c1SYuval Mintz 		rc = qed_sp_init_request(p_hwfn, &p_ent,
99017b235c1SYuval Mintz 					 ETH_RAMROD_RX_QUEUE_UPDATE,
99117b235c1SYuval Mintz 					 PROTOCOLID_ETH, &init_data);
99217b235c1SYuval Mintz 		if (rc)
99317b235c1SYuval Mintz 			return rc;
99417b235c1SYuval Mintz 
99517b235c1SYuval Mintz 		p_ramrod = &p_ent->ramrod.rx_queue_update;
9963da7a37aSMintz, Yuval 		p_ramrod->vport_id = p_cid->abs.vport_id;
99717b235c1SYuval Mintz 
9983da7a37aSMintz, Yuval 		p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
99917b235c1SYuval Mintz 		p_ramrod->complete_cqe_flg = complete_cqe_flg;
100017b235c1SYuval Mintz 		p_ramrod->complete_event_flg = complete_event_flg;
100117b235c1SYuval Mintz 
100217b235c1SYuval Mintz 		rc = qed_spq_post(p_hwfn, p_ent, NULL);
100317b235c1SYuval Mintz 		if (rc)
100417b235c1SYuval Mintz 			return rc;
100517b235c1SYuval Mintz 	}
100617b235c1SYuval Mintz 
100717b235c1SYuval Mintz 	return rc;
100817b235c1SYuval Mintz }
100917b235c1SYuval Mintz 
10103da7a37aSMintz, Yuval static int
qed_eth_pf_rx_queue_stop(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid,bool b_eq_completion_only,bool b_cqe_completion)10113da7a37aSMintz, Yuval qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
10123da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
10133da7a37aSMintz, Yuval 			 bool b_eq_completion_only, bool b_cqe_completion)
1014cee4d264SManish Chopra {
1015cee4d264SManish Chopra 	struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
1016cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
101706f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
10183da7a37aSMintz, Yuval 	int rc;
1019cee4d264SManish Chopra 
102006f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
10213da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
10223da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
102306f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1024cee4d264SManish Chopra 
1025cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1026cee4d264SManish Chopra 				 ETH_RAMROD_RX_QUEUE_STOP,
102706f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1028cee4d264SManish Chopra 	if (rc)
1029cee4d264SManish Chopra 		return rc;
1030cee4d264SManish Chopra 
1031cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.rx_queue_stop;
10323da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
10333da7a37aSMintz, Yuval 	p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
1034cee4d264SManish Chopra 
1035cee4d264SManish Chopra 	/* Cleaning the queue requires the completion to arrive there.
1036cee4d264SManish Chopra 	 * In addition, VFs require the answer to come as eqe to PF.
1037cee4d264SManish Chopra 	 */
10383946497aSMintz, Yuval 	p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
10393da7a37aSMintz, Yuval 				      !b_eq_completion_only) ||
10403da7a37aSMintz, Yuval 				     b_cqe_completion;
10413946497aSMintz, Yuval 	p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) ||
10423946497aSMintz, Yuval 				       b_eq_completion_only;
1043cee4d264SManish Chopra 
10443da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
1045cee4d264SManish Chopra }
1046cee4d264SManish Chopra 
qed_eth_rx_queue_stop(struct qed_hwfn * p_hwfn,void * p_rxq,bool eq_completion_only,bool cqe_completion)10473da7a37aSMintz, Yuval int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
10483da7a37aSMintz, Yuval 			  void *p_rxq,
10493da7a37aSMintz, Yuval 			  bool eq_completion_only, bool cqe_completion)
10503da7a37aSMintz, Yuval {
10513da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
10523da7a37aSMintz, Yuval 	int rc = -EINVAL;
10533da7a37aSMintz, Yuval 
10543da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
10553da7a37aSMintz, Yuval 		rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
10563da7a37aSMintz, Yuval 					      eq_completion_only,
10573da7a37aSMintz, Yuval 					      cqe_completion);
10583da7a37aSMintz, Yuval 	else
10593da7a37aSMintz, Yuval 		rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
10603da7a37aSMintz, Yuval 
10613da7a37aSMintz, Yuval 	if (!rc)
10623da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
10633da7a37aSMintz, Yuval 	return rc;
10643da7a37aSMintz, Yuval }
10653da7a37aSMintz, Yuval 
10663da7a37aSMintz, Yuval int
qed_eth_txq_start_ramrod(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid,dma_addr_t pbl_addr,u16 pbl_size,u16 pq_id)10673da7a37aSMintz, Yuval qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
10683da7a37aSMintz, Yuval 			 struct qed_queue_cid *p_cid,
10693da7a37aSMintz, Yuval 			 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
1070cee4d264SManish Chopra {
1071cee4d264SManish Chopra 	struct tx_queue_start_ramrod_data *p_ramrod = NULL;
1072cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
107306f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1074cee4d264SManish Chopra 	int rc = -EINVAL;
1075351a4dedSYuval Mintz 
107606f56b81SYuval Mintz 	/* Get SPQ entry */
107706f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
10783da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
10793da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
108006f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1081cee4d264SManish Chopra 
108206f56b81SYuval Mintz 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1083cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_START,
108406f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1085cee4d264SManish Chopra 	if (rc)
1086cee4d264SManish Chopra 		return rc;
1087cee4d264SManish Chopra 
1088cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.tx_queue_start;
10893da7a37aSMintz, Yuval 	p_ramrod->vport_id = p_cid->abs.vport_id;
1090cee4d264SManish Chopra 
1091f604b17dSMintz, Yuval 	p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
1092f604b17dSMintz, Yuval 	p_ramrod->sb_index = p_cid->sb_idx;
10933da7a37aSMintz, Yuval 	p_ramrod->stats_counter_id = p_cid->abs.stats_id;
1094cee4d264SManish Chopra 
10953da7a37aSMintz, Yuval 	p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
10963da7a37aSMintz, Yuval 	p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
10971a635e48SYuval Mintz 
1098cee4d264SManish Chopra 	p_ramrod->pbl_size = cpu_to_le16(pbl_size);
109994494598SYuval Mintz 	DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
1100cee4d264SManish Chopra 
1101cee4d264SManish Chopra 	p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
1102cee4d264SManish Chopra 
1103cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1104cee4d264SManish Chopra }
1105cee4d264SManish Chopra 
1106cee4d264SManish Chopra static int
qed_eth_pf_tx_queue_start(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid,u8 tc,dma_addr_t pbl_addr,u16 pbl_size,void __iomem ** pp_doorbell)11073da7a37aSMintz, Yuval qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
11083da7a37aSMintz, Yuval 			  struct qed_queue_cid *p_cid,
11093da7a37aSMintz, Yuval 			  u8 tc,
1110cee4d264SManish Chopra 			  dma_addr_t pbl_addr,
1111dacd88d6SYuval Mintz 			  u16 pbl_size, void __iomem **pp_doorbell)
1112cee4d264SManish Chopra {
1113cee4d264SManish Chopra 	int rc;
1114cee4d264SManish Chopra 
11153da7a37aSMintz, Yuval 	rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
11163da7a37aSMintz, Yuval 				      pbl_addr, pbl_size,
1117b5a9ee7cSAriel Elior 				      qed_get_cm_pq_idx_mcos(p_hwfn, tc));
11183da7a37aSMintz, Yuval 	if (rc)
1119cee4d264SManish Chopra 		return rc;
11203da7a37aSMintz, Yuval 
11213da7a37aSMintz, Yuval 	/* Provide the caller with the necessary return values */
11223da7a37aSMintz, Yuval 	*pp_doorbell = p_hwfn->doorbells +
11233da7a37aSMintz, Yuval 		       qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
11243da7a37aSMintz, Yuval 
11253da7a37aSMintz, Yuval 	return 0;
1126cee4d264SManish Chopra }
1127cee4d264SManish Chopra 
11283da7a37aSMintz, Yuval static int
qed_eth_tx_queue_start(struct qed_hwfn * p_hwfn,u16 opaque_fid,struct qed_queue_start_common_params * p_params,u8 tc,dma_addr_t pbl_addr,u16 pbl_size,struct qed_txq_start_ret_params * p_ret_params)11293da7a37aSMintz, Yuval qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
11303da7a37aSMintz, Yuval 		       u16 opaque_fid,
11313da7a37aSMintz, Yuval 		       struct qed_queue_start_common_params *p_params,
11323da7a37aSMintz, Yuval 		       u8 tc,
11333da7a37aSMintz, Yuval 		       dma_addr_t pbl_addr,
11343da7a37aSMintz, Yuval 		       u16 pbl_size,
11353da7a37aSMintz, Yuval 		       struct qed_txq_start_ret_params *p_ret_params)
11363da7a37aSMintz, Yuval {
11373da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid;
11383da7a37aSMintz, Yuval 	int rc;
1139cee4d264SManish Chopra 
1140007bc371SMintz, Yuval 	p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params);
11413da7a37aSMintz, Yuval 	if (!p_cid)
11423da7a37aSMintz, Yuval 		return -EINVAL;
1143cee4d264SManish Chopra 
11443da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
11453da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
11463da7a37aSMintz, Yuval 					       pbl_addr, pbl_size,
11473da7a37aSMintz, Yuval 					       &p_ret_params->p_doorbell);
11483da7a37aSMintz, Yuval 	else
11493da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
11503da7a37aSMintz, Yuval 					 pbl_addr, pbl_size,
11513da7a37aSMintz, Yuval 					 &p_ret_params->p_doorbell);
1152cee4d264SManish Chopra 
1153cee4d264SManish Chopra 	if (rc)
11543da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
11553da7a37aSMintz, Yuval 	else
11563da7a37aSMintz, Yuval 		p_ret_params->p_handle = (void *)p_cid;
1157cee4d264SManish Chopra 
1158cee4d264SManish Chopra 	return rc;
1159cee4d264SManish Chopra }
1160cee4d264SManish Chopra 
11613da7a37aSMintz, Yuval static int
qed_eth_pf_tx_queue_stop(struct qed_hwfn * p_hwfn,struct qed_queue_cid * p_cid)11623da7a37aSMintz, Yuval qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
1163cee4d264SManish Chopra {
1164cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
116506f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
11663da7a37aSMintz, Yuval 	int rc;
1167cee4d264SManish Chopra 
116806f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
11693da7a37aSMintz, Yuval 	init_data.cid = p_cid->cid;
11703da7a37aSMintz, Yuval 	init_data.opaque_fid = p_cid->opaque_fid;
117106f56b81SYuval Mintz 	init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1172cee4d264SManish Chopra 
1173cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1174cee4d264SManish Chopra 				 ETH_RAMROD_TX_QUEUE_STOP,
117506f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1176cee4d264SManish Chopra 	if (rc)
1177cee4d264SManish Chopra 		return rc;
1178cee4d264SManish Chopra 
11793da7a37aSMintz, Yuval 	return qed_spq_post(p_hwfn, p_ent, NULL);
11803da7a37aSMintz, Yuval }
1181cee4d264SManish Chopra 
qed_eth_tx_queue_stop(struct qed_hwfn * p_hwfn,void * p_handle)11823da7a37aSMintz, Yuval int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
11833da7a37aSMintz, Yuval {
11843da7a37aSMintz, Yuval 	struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
11853da7a37aSMintz, Yuval 	int rc;
11863da7a37aSMintz, Yuval 
11873da7a37aSMintz, Yuval 	if (IS_PF(p_hwfn->cdev))
11883da7a37aSMintz, Yuval 		rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
11893da7a37aSMintz, Yuval 	else
11903da7a37aSMintz, Yuval 		rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
11913da7a37aSMintz, Yuval 
11923da7a37aSMintz, Yuval 	if (!rc)
11933da7a37aSMintz, Yuval 		qed_eth_queue_cid_release(p_hwfn, p_cid);
11943da7a37aSMintz, Yuval 	return rc;
1195cee4d264SManish Chopra }
1196cee4d264SManish Chopra 
qed_filter_action(enum qed_filter_opcode opcode)11971a635e48SYuval Mintz static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
1198cee4d264SManish Chopra {
1199cee4d264SManish Chopra 	enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1200cee4d264SManish Chopra 
1201cee4d264SManish Chopra 	switch (opcode) {
1202cee4d264SManish Chopra 	case QED_FILTER_ADD:
1203cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_ADD;
1204cee4d264SManish Chopra 		break;
1205cee4d264SManish Chopra 	case QED_FILTER_REMOVE:
1206cee4d264SManish Chopra 		action = ETH_FILTER_ACTION_REMOVE;
1207cee4d264SManish Chopra 		break;
1208cee4d264SManish Chopra 	case QED_FILTER_FLUSH:
1209fc48b7a6SYuval Mintz 		action = ETH_FILTER_ACTION_REMOVE_ALL;
1210cee4d264SManish Chopra 		break;
1211cee4d264SManish Chopra 	default:
1212cee4d264SManish Chopra 		action = MAX_ETH_FILTER_ACTION;
1213cee4d264SManish Chopra 	}
1214cee4d264SManish Chopra 
1215cee4d264SManish Chopra 	return action;
1216cee4d264SManish Chopra }
1217cee4d264SManish Chopra 
1218cee4d264SManish Chopra static int
qed_filter_ucast_common(struct qed_hwfn * p_hwfn,u16 opaque_fid,struct qed_filter_ucast * p_filter_cmd,struct vport_filter_update_ramrod_data ** pp_ramrod,struct qed_spq_entry ** pp_ent,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)1219cee4d264SManish Chopra qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1220cee4d264SManish Chopra 			u16 opaque_fid,
1221cee4d264SManish Chopra 			struct qed_filter_ucast *p_filter_cmd,
1222cee4d264SManish Chopra 			struct vport_filter_update_ramrod_data **pp_ramrod,
1223cee4d264SManish Chopra 			struct qed_spq_entry **pp_ent,
1224cee4d264SManish Chopra 			enum spq_mode comp_mode,
1225cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1226cee4d264SManish Chopra {
1227cee4d264SManish Chopra 	u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1228cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data *p_ramrod;
1229cee4d264SManish Chopra 	struct eth_filter_cmd *p_first_filter;
1230cee4d264SManish Chopra 	struct eth_filter_cmd *p_second_filter;
123106f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1232cee4d264SManish Chopra 	enum eth_filter_action action;
1233cee4d264SManish Chopra 	int rc;
1234cee4d264SManish Chopra 
1235cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1236cee4d264SManish Chopra 			  &vport_to_remove_from);
1237cee4d264SManish Chopra 	if (rc)
1238cee4d264SManish Chopra 		return rc;
1239cee4d264SManish Chopra 
1240cee4d264SManish Chopra 	rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1241cee4d264SManish Chopra 			  &vport_to_add_to);
1242cee4d264SManish Chopra 	if (rc)
1243cee4d264SManish Chopra 		return rc;
1244cee4d264SManish Chopra 
124506f56b81SYuval Mintz 	/* Get SPQ entry */
124606f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
124706f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
124806f56b81SYuval Mintz 	init_data.opaque_fid = opaque_fid;
124906f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
125006f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1251cee4d264SManish Chopra 
1252cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, pp_ent,
1253cee4d264SManish Chopra 				 ETH_RAMROD_FILTERS_UPDATE,
125406f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1255cee4d264SManish Chopra 	if (rc)
1256cee4d264SManish Chopra 		return rc;
1257cee4d264SManish Chopra 
1258cee4d264SManish Chopra 	*pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1259cee4d264SManish Chopra 	p_ramrod = *pp_ramrod;
1260cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1261cee4d264SManish Chopra 	p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1262cee4d264SManish Chopra 
1263cee4d264SManish Chopra 	switch (p_filter_cmd->opcode) {
1264fc48b7a6SYuval Mintz 	case QED_FILTER_REPLACE:
1265cee4d264SManish Chopra 	case QED_FILTER_MOVE:
1266cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1267cee4d264SManish Chopra 	default:
1268cee4d264SManish Chopra 		p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1269cee4d264SManish Chopra 	}
1270cee4d264SManish Chopra 
1271cee4d264SManish Chopra 	p_first_filter	= &p_ramrod->filter_cmds[0];
1272cee4d264SManish Chopra 	p_second_filter = &p_ramrod->filter_cmds[1];
1273cee4d264SManish Chopra 
1274cee4d264SManish Chopra 	switch (p_filter_cmd->type) {
1275cee4d264SManish Chopra 	case QED_FILTER_MAC:
1276cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1277cee4d264SManish Chopra 	case QED_FILTER_VLAN:
1278cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1279cee4d264SManish Chopra 	case QED_FILTER_MAC_VLAN:
1280cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1281cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC:
1282cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1283cee4d264SManish Chopra 	case QED_FILTER_INNER_VLAN:
1284cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1285cee4d264SManish Chopra 	case QED_FILTER_INNER_PAIR:
1286cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1287cee4d264SManish Chopra 	case QED_FILTER_INNER_MAC_VNI_PAIR:
1288cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1289cee4d264SManish Chopra 		break;
1290cee4d264SManish Chopra 	case QED_FILTER_MAC_VNI_PAIR:
1291cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1292cee4d264SManish Chopra 	case QED_FILTER_VNI:
1293cee4d264SManish Chopra 		p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1294cee4d264SManish Chopra 	}
1295cee4d264SManish Chopra 
1296cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1297cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1298cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1299cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1300cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1301cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1302cee4d264SManish Chopra 		qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1303cee4d264SManish Chopra 				    &p_first_filter->mac_mid,
1304cee4d264SManish Chopra 				    &p_first_filter->mac_lsb,
1305cee4d264SManish Chopra 				    (u8 *)p_filter_cmd->mac);
1306cee4d264SManish Chopra 	}
1307cee4d264SManish Chopra 
1308cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1309cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1310cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1311cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1312cee4d264SManish Chopra 		p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1313cee4d264SManish Chopra 
1314cee4d264SManish Chopra 	if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1315cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1316cee4d264SManish Chopra 	    (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1317cee4d264SManish Chopra 		p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1318cee4d264SManish Chopra 
1319cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1320cee4d264SManish Chopra 		p_second_filter->type = p_first_filter->type;
1321cee4d264SManish Chopra 		p_second_filter->mac_msb = p_first_filter->mac_msb;
1322cee4d264SManish Chopra 		p_second_filter->mac_mid = p_first_filter->mac_mid;
1323cee4d264SManish Chopra 		p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1324cee4d264SManish Chopra 		p_second_filter->vlan_id = p_first_filter->vlan_id;
1325cee4d264SManish Chopra 		p_second_filter->vni = p_first_filter->vni;
1326cee4d264SManish Chopra 
1327cee4d264SManish Chopra 		p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1328cee4d264SManish Chopra 
1329cee4d264SManish Chopra 		p_first_filter->vport_id = vport_to_remove_from;
1330cee4d264SManish Chopra 
1331cee4d264SManish Chopra 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1332cee4d264SManish Chopra 		p_second_filter->vport_id = vport_to_add_to;
1333fc48b7a6SYuval Mintz 	} else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1334fc48b7a6SYuval Mintz 		p_first_filter->vport_id = vport_to_add_to;
1335fc48b7a6SYuval Mintz 		memcpy(p_second_filter, p_first_filter,
1336fc48b7a6SYuval Mintz 		       sizeof(*p_second_filter));
1337fc48b7a6SYuval Mintz 		p_first_filter->action	= ETH_FILTER_ACTION_REMOVE_ALL;
1338fc48b7a6SYuval Mintz 		p_second_filter->action = ETH_FILTER_ACTION_ADD;
1339cee4d264SManish Chopra 	} else {
1340cee4d264SManish Chopra 		action = qed_filter_action(p_filter_cmd->opcode);
1341cee4d264SManish Chopra 
1342cee4d264SManish Chopra 		if (action == MAX_ETH_FILTER_ACTION) {
1343cee4d264SManish Chopra 			DP_NOTICE(p_hwfn,
1344cee4d264SManish Chopra 				  "%d is not supported yet\n",
1345cee4d264SManish Chopra 				  p_filter_cmd->opcode);
1346fb5e7438SDenis Bolotin 			qed_sp_destroy_request(p_hwfn, *pp_ent);
1347cee4d264SManish Chopra 			return -EINVAL;
1348cee4d264SManish Chopra 		}
1349cee4d264SManish Chopra 
1350cee4d264SManish Chopra 		p_first_filter->action = action;
1351cee4d264SManish Chopra 		p_first_filter->vport_id = (p_filter_cmd->opcode ==
1352cee4d264SManish Chopra 					    QED_FILTER_REMOVE) ?
1353cee4d264SManish Chopra 					   vport_to_remove_from :
1354cee4d264SManish Chopra 					   vport_to_add_to;
1355cee4d264SManish Chopra 	}
1356cee4d264SManish Chopra 
1357cee4d264SManish Chopra 	return 0;
1358cee4d264SManish Chopra }
1359cee4d264SManish Chopra 
qed_sp_eth_filter_ucast(struct qed_hwfn * p_hwfn,u16 opaque_fid,struct qed_filter_ucast * p_filter_cmd,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)1360dacd88d6SYuval Mintz int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1361cee4d264SManish Chopra 			    u16 opaque_fid,
1362cee4d264SManish Chopra 			    struct qed_filter_ucast *p_filter_cmd,
1363cee4d264SManish Chopra 			    enum spq_mode comp_mode,
1364cee4d264SManish Chopra 			    struct qed_spq_comp_cb *p_comp_data)
1365cee4d264SManish Chopra {
1366cee4d264SManish Chopra 	struct vport_filter_update_ramrod_data	*p_ramrod	= NULL;
1367cee4d264SManish Chopra 	struct qed_spq_entry			*p_ent		= NULL;
1368cee4d264SManish Chopra 	struct eth_filter_cmd_header		*p_header;
1369cee4d264SManish Chopra 	int					rc;
1370cee4d264SManish Chopra 
1371cee4d264SManish Chopra 	rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1372cee4d264SManish Chopra 				     &p_ramrod, &p_ent,
1373cee4d264SManish Chopra 				     comp_mode, p_comp_data);
13741a635e48SYuval Mintz 	if (rc) {
1375cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1376cee4d264SManish Chopra 		return rc;
1377cee4d264SManish Chopra 	}
1378cee4d264SManish Chopra 	p_header = &p_ramrod->filter_cmd_hdr;
1379cee4d264SManish Chopra 	p_header->assert_on_error = p_filter_cmd->assert_on_error;
1380cee4d264SManish Chopra 
1381cee4d264SManish Chopra 	rc = qed_spq_post(p_hwfn, p_ent, NULL);
13821a635e48SYuval Mintz 	if (rc) {
13831a635e48SYuval Mintz 		DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1384cee4d264SManish Chopra 		return rc;
1385cee4d264SManish Chopra 	}
1386cee4d264SManish Chopra 
1387cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1388cee4d264SManish Chopra 		   "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1389cee4d264SManish Chopra 		   (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1390cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1391cee4d264SManish Chopra 		   "REMOVE" :
1392cee4d264SManish Chopra 		   ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1393cee4d264SManish Chopra 		    "MOVE" : "REPLACE")),
1394cee4d264SManish Chopra 		   (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1395cee4d264SManish Chopra 		   ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1396cee4d264SManish Chopra 		    "VLAN" : "MAC & VLAN"),
1397cee4d264SManish Chopra 		   p_ramrod->filter_cmd_hdr.cmd_cnt,
1398cee4d264SManish Chopra 		   p_filter_cmd->is_rx_filter,
1399cee4d264SManish Chopra 		   p_filter_cmd->is_tx_filter);
1400cee4d264SManish Chopra 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
1401cee4d264SManish Chopra 		   "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1402cee4d264SManish Chopra 		   p_filter_cmd->vport_to_add_to,
1403cee4d264SManish Chopra 		   p_filter_cmd->vport_to_remove_from,
1404cee4d264SManish Chopra 		   p_filter_cmd->mac[0],
1405cee4d264SManish Chopra 		   p_filter_cmd->mac[1],
1406cee4d264SManish Chopra 		   p_filter_cmd->mac[2],
1407cee4d264SManish Chopra 		   p_filter_cmd->mac[3],
1408cee4d264SManish Chopra 		   p_filter_cmd->mac[4],
1409cee4d264SManish Chopra 		   p_filter_cmd->mac[5],
1410cee4d264SManish Chopra 		   p_filter_cmd->vlan);
1411cee4d264SManish Chopra 
1412cee4d264SManish Chopra 	return 0;
1413cee4d264SManish Chopra }
1414cee4d264SManish Chopra 
1415cee4d264SManish Chopra /*******************************************************************************
1416cee4d264SManish Chopra  * Description:
1417cee4d264SManish Chopra  *         Calculates crc 32 on a buffer
1418cee4d264SManish Chopra  *         Note: crc32_length MUST be aligned to 8
1419cee4d264SManish Chopra  * Return:
1420cee4d264SManish Chopra  ******************************************************************************/
qed_calc_crc32c(u8 * crc32_packet,u32 crc32_length,u32 crc32_seed,u8 complement)1421cee4d264SManish Chopra static u32 qed_calc_crc32c(u8 *crc32_packet,
14221a635e48SYuval Mintz 			   u32 crc32_length, u32 crc32_seed, u8 complement)
1423cee4d264SManish Chopra {
14241a635e48SYuval Mintz 	u32 byte = 0, bit = 0, crc32_result = crc32_seed;
14251a635e48SYuval Mintz 	u8 msb = 0, current_byte = 0;
1426cee4d264SManish Chopra 
1427cee4d264SManish Chopra 	if ((!crc32_packet) ||
1428cee4d264SManish Chopra 	    (crc32_length == 0) ||
1429cee4d264SManish Chopra 	    ((crc32_length % 8) != 0))
1430cee4d264SManish Chopra 		return crc32_result;
1431cee4d264SManish Chopra 	for (byte = 0; byte < crc32_length; byte++) {
1432cee4d264SManish Chopra 		current_byte = crc32_packet[byte];
1433cee4d264SManish Chopra 		for (bit = 0; bit < 8; bit++) {
1434cee4d264SManish Chopra 			msb = (u8)(crc32_result >> 31);
1435cee4d264SManish Chopra 			crc32_result = crc32_result << 1;
1436cee4d264SManish Chopra 			if (msb != (0x1 & (current_byte >> bit))) {
1437cee4d264SManish Chopra 				crc32_result = crc32_result ^ CRC32_POLY;
1438cee4d264SManish Chopra 				crc32_result |= 1; /*crc32_result[0] = 1;*/
1439cee4d264SManish Chopra 			}
1440cee4d264SManish Chopra 		}
1441cee4d264SManish Chopra 	}
1442cee4d264SManish Chopra 	return crc32_result;
1443cee4d264SManish Chopra }
1444cee4d264SManish Chopra 
qed_crc32c_le(u32 seed,u8 * mac,u32 len)14451a635e48SYuval Mintz static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
1446cee4d264SManish Chopra {
1447cee4d264SManish Chopra 	u32 packet_buf[2] = { 0 };
1448cee4d264SManish Chopra 
1449cee4d264SManish Chopra 	memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1450cee4d264SManish Chopra 	return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1451cee4d264SManish Chopra }
1452cee4d264SManish Chopra 
qed_mcast_bin_from_mac(u8 * mac)1453dacd88d6SYuval Mintz u8 qed_mcast_bin_from_mac(u8 *mac)
1454cee4d264SManish Chopra {
1455cee4d264SManish Chopra 	u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1456cee4d264SManish Chopra 				mac, ETH_ALEN);
1457cee4d264SManish Chopra 
1458cee4d264SManish Chopra 	return crc & 0xff;
1459cee4d264SManish Chopra }
1460cee4d264SManish Chopra 
1461cee4d264SManish Chopra static int
qed_sp_eth_filter_mcast(struct qed_hwfn * p_hwfn,u16 opaque_fid,struct qed_filter_mcast * p_filter_cmd,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)1462cee4d264SManish Chopra qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1463cee4d264SManish Chopra 			u16 opaque_fid,
1464cee4d264SManish Chopra 			struct qed_filter_mcast *p_filter_cmd,
1465cee4d264SManish Chopra 			enum spq_mode comp_mode,
1466cee4d264SManish Chopra 			struct qed_spq_comp_cb *p_comp_data)
1467cee4d264SManish Chopra {
1468cee4d264SManish Chopra 	struct vport_update_ramrod_data *p_ramrod = NULL;
146925c020a9SSudarsana Reddy Kalluru 	u32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1470cee4d264SManish Chopra 	struct qed_spq_entry *p_ent = NULL;
147106f56b81SYuval Mintz 	struct qed_sp_init_data init_data;
1472cee4d264SManish Chopra 	u8 abs_vport_id = 0;
1473cee4d264SManish Chopra 	int rc, i;
1474cee4d264SManish Chopra 
147583aeb933SYuval Mintz 	if (p_filter_cmd->opcode == QED_FILTER_ADD)
1476cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1477cee4d264SManish Chopra 				  &abs_vport_id);
147883aeb933SYuval Mintz 	else
1479cee4d264SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1480cee4d264SManish Chopra 				  &abs_vport_id);
1481cee4d264SManish Chopra 	if (rc)
1482cee4d264SManish Chopra 		return rc;
1483cee4d264SManish Chopra 
148406f56b81SYuval Mintz 	/* Get SPQ entry */
148506f56b81SYuval Mintz 	memset(&init_data, 0, sizeof(init_data));
148606f56b81SYuval Mintz 	init_data.cid = qed_spq_get_cid(p_hwfn);
148706f56b81SYuval Mintz 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
148806f56b81SYuval Mintz 	init_data.comp_mode = comp_mode;
148906f56b81SYuval Mintz 	init_data.p_comp_data = p_comp_data;
1490cee4d264SManish Chopra 
1491cee4d264SManish Chopra 	rc = qed_sp_init_request(p_hwfn, &p_ent,
1492cee4d264SManish Chopra 				 ETH_RAMROD_VPORT_UPDATE,
149306f56b81SYuval Mintz 				 PROTOCOLID_ETH, &init_data);
1494cee4d264SManish Chopra 	if (rc) {
1495cee4d264SManish Chopra 		DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1496cee4d264SManish Chopra 		return rc;
1497cee4d264SManish Chopra 	}
1498cee4d264SManish Chopra 
1499cee4d264SManish Chopra 	p_ramrod = &p_ent->ramrod.vport_update;
1500cee4d264SManish Chopra 	p_ramrod->common.update_approx_mcast_flg = 1;
1501cee4d264SManish Chopra 
1502cee4d264SManish Chopra 	/* explicitly clear out the entire vector */
1503cee4d264SManish Chopra 	memset(&p_ramrod->approx_mcast.bins, 0,
1504cee4d264SManish Chopra 	       sizeof(p_ramrod->approx_mcast.bins));
150525c020a9SSudarsana Reddy Kalluru 	memset(bins, 0, sizeof(bins));
1506cee4d264SManish Chopra 	/* filter ADD op is explicit set op and it removes
1507cee4d264SManish Chopra 	 *  any existing filters for the vport
1508cee4d264SManish Chopra 	 */
1509cee4d264SManish Chopra 	if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1510cee4d264SManish Chopra 		for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
151125c020a9SSudarsana Reddy Kalluru 			u32 bit, nbits;
1512cee4d264SManish Chopra 
1513cee4d264SManish Chopra 			bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
151425c020a9SSudarsana Reddy Kalluru 			nbits = sizeof(u32) * BITS_PER_BYTE;
151525c020a9SSudarsana Reddy Kalluru 			bins[bit / nbits] |= 1 << (bit % nbits);
1516cee4d264SManish Chopra 		}
1517cee4d264SManish Chopra 
1518cee4d264SManish Chopra 		/* Convert to correct endianity */
1519cee4d264SManish Chopra 		for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
15201a635e48SYuval Mintz 			struct vport_update_ramrod_mcast *p_ramrod_bins;
1521cee4d264SManish Chopra 
15221a635e48SYuval Mintz 			p_ramrod_bins = &p_ramrod->approx_mcast;
152325c020a9SSudarsana Reddy Kalluru 			p_ramrod_bins->bins[i] = cpu_to_le32(bins[i]);
1524cee4d264SManish Chopra 		}
1525cee4d264SManish Chopra 	}
1526cee4d264SManish Chopra 
1527cee4d264SManish Chopra 	p_ramrod->common.vport_id = abs_vport_id;
1528cee4d264SManish Chopra 
1529cee4d264SManish Chopra 	return qed_spq_post(p_hwfn, p_ent, NULL);
1530cee4d264SManish Chopra }
1531cee4d264SManish Chopra 
qed_filter_mcast_cmd(struct qed_dev * cdev,struct qed_filter_mcast * p_filter_cmd,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)1532dacd88d6SYuval Mintz static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1533cee4d264SManish Chopra 				struct qed_filter_mcast *p_filter_cmd,
1534cee4d264SManish Chopra 				enum spq_mode comp_mode,
1535cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1536cee4d264SManish Chopra {
1537cee4d264SManish Chopra 	int rc = 0;
1538cee4d264SManish Chopra 	int i;
1539cee4d264SManish Chopra 
1540cee4d264SManish Chopra 	/* only ADD and REMOVE operations are supported for multi-cast */
1541cee4d264SManish Chopra 	if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1542cee4d264SManish Chopra 	     (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1543cee4d264SManish Chopra 	    (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1544cee4d264SManish Chopra 		return -EINVAL;
1545cee4d264SManish Chopra 
1546cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1547cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1548cee4d264SManish Chopra 
1549cee4d264SManish Chopra 		u16 opaque_fid;
1550cee4d264SManish Chopra 
1551dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1552dacd88d6SYuval Mintz 			qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1553dacd88d6SYuval Mintz 			continue;
1554dacd88d6SYuval Mintz 		}
1555cee4d264SManish Chopra 
1556cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1557cee4d264SManish Chopra 
1558cee4d264SManish Chopra 		rc = qed_sp_eth_filter_mcast(p_hwfn,
1559cee4d264SManish Chopra 					     opaque_fid,
1560cee4d264SManish Chopra 					     p_filter_cmd,
15611a635e48SYuval Mintz 					     comp_mode, p_comp_data);
1562cee4d264SManish Chopra 	}
1563cee4d264SManish Chopra 	return rc;
1564cee4d264SManish Chopra }
1565cee4d264SManish Chopra 
qed_filter_ucast_cmd(struct qed_dev * cdev,struct qed_filter_ucast * p_filter_cmd,enum spq_mode comp_mode,struct qed_spq_comp_cb * p_comp_data)1566cee4d264SManish Chopra static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1567cee4d264SManish Chopra 				struct qed_filter_ucast *p_filter_cmd,
1568cee4d264SManish Chopra 				enum spq_mode comp_mode,
1569cee4d264SManish Chopra 				struct qed_spq_comp_cb *p_comp_data)
1570cee4d264SManish Chopra {
1571cee4d264SManish Chopra 	int rc = 0;
1572cee4d264SManish Chopra 	int i;
1573cee4d264SManish Chopra 
1574cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
1575cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1576cee4d264SManish Chopra 		u16 opaque_fid;
1577cee4d264SManish Chopra 
1578dacd88d6SYuval Mintz 		if (IS_VF(cdev)) {
1579dacd88d6SYuval Mintz 			rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1580dacd88d6SYuval Mintz 			continue;
1581dacd88d6SYuval Mintz 		}
1582cee4d264SManish Chopra 
1583cee4d264SManish Chopra 		opaque_fid = p_hwfn->hw_info.opaque_fid;
1584cee4d264SManish Chopra 
1585cee4d264SManish Chopra 		rc = qed_sp_eth_filter_ucast(p_hwfn,
1586cee4d264SManish Chopra 					     opaque_fid,
1587cee4d264SManish Chopra 					     p_filter_cmd,
15881a635e48SYuval Mintz 					     comp_mode, p_comp_data);
15891a635e48SYuval Mintz 		if (rc)
1590dacd88d6SYuval Mintz 			break;
1591cee4d264SManish Chopra 	}
1592cee4d264SManish Chopra 
1593cee4d264SManish Chopra 	return rc;
1594cee4d264SManish Chopra }
1595cee4d264SManish Chopra 
159686622ee7SYuval Mintz /* Statistics related code */
__qed_get_vport_pstats_addrlen(struct qed_hwfn * p_hwfn,u32 * p_addr,u32 * p_len,u16 statistics_bin)159786622ee7SYuval Mintz static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
159886622ee7SYuval Mintz 					   u32 *p_addr,
1599dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
160086622ee7SYuval Mintz {
1601dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
160286622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_PSDM_RAM +
160386622ee7SYuval Mintz 		    PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
160486622ee7SYuval Mintz 		*p_len = sizeof(struct eth_pstorm_per_queue_stat);
1605dacd88d6SYuval Mintz 	} else {
1606dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1607dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1608dacd88d6SYuval Mintz 
1609dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1610dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.pstats.len;
1611dacd88d6SYuval Mintz 	}
161286622ee7SYuval Mintz }
161386622ee7SYuval Mintz 
16147c116e02SArnd Bergmann static noinline_for_stack void
__qed_get_vport_pstats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_eth_stats * p_stats,u16 statistics_bin)16157c116e02SArnd Bergmann __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
16167c116e02SArnd Bergmann 		       struct qed_eth_stats *p_stats, u16 statistics_bin)
161786622ee7SYuval Mintz {
161886622ee7SYuval Mintz 	struct eth_pstorm_per_queue_stat pstats;
161986622ee7SYuval Mintz 	u32 pstats_addr = 0, pstats_len = 0;
162086622ee7SYuval Mintz 
162186622ee7SYuval Mintz 	__qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
162286622ee7SYuval Mintz 				       statistics_bin);
162386622ee7SYuval Mintz 
162486622ee7SYuval Mintz 	memset(&pstats, 0, sizeof(pstats));
1625dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
162686622ee7SYuval Mintz 
16279c79ddaaSMintz, Yuval 	p_stats->common.tx_ucast_bytes +=
16289c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_ucast_bytes);
16299c79ddaaSMintz, Yuval 	p_stats->common.tx_mcast_bytes +=
16309c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_mcast_bytes);
16319c79ddaaSMintz, Yuval 	p_stats->common.tx_bcast_bytes +=
16329c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_bcast_bytes);
16339c79ddaaSMintz, Yuval 	p_stats->common.tx_ucast_pkts +=
16349c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_ucast_pkts);
16359c79ddaaSMintz, Yuval 	p_stats->common.tx_mcast_pkts +=
16369c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_mcast_pkts);
16379c79ddaaSMintz, Yuval 	p_stats->common.tx_bcast_pkts +=
16389c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.sent_bcast_pkts);
16399c79ddaaSMintz, Yuval 	p_stats->common.tx_err_drop_pkts +=
16409c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(pstats.error_drop_pkts);
164186622ee7SYuval Mintz }
164286622ee7SYuval Mintz 
16437c116e02SArnd Bergmann static noinline_for_stack void
__qed_get_vport_tstats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_eth_stats * p_stats,u16 statistics_bin)16447c116e02SArnd Bergmann __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
16457c116e02SArnd Bergmann 		       struct qed_eth_stats *p_stats, u16 statistics_bin)
164686622ee7SYuval Mintz {
164786622ee7SYuval Mintz 	struct tstorm_per_port_stat tstats;
1648dacd88d6SYuval Mintz 	u32 tstats_addr, tstats_len;
164986622ee7SYuval Mintz 
1650dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
1651dacd88d6SYuval Mintz 		tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1652dacd88d6SYuval Mintz 		    TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1653dacd88d6SYuval Mintz 		tstats_len = sizeof(struct tstorm_per_port_stat);
1654dacd88d6SYuval Mintz 	} else {
1655dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1656dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1657dacd88d6SYuval Mintz 
1658dacd88d6SYuval Mintz 		tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1659dacd88d6SYuval Mintz 		tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1660dacd88d6SYuval Mintz 	}
166186622ee7SYuval Mintz 
166286622ee7SYuval Mintz 	memset(&tstats, 0, sizeof(tstats));
1663dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
166486622ee7SYuval Mintz 
16659c79ddaaSMintz, Yuval 	p_stats->common.mftag_filter_discards +=
166686622ee7SYuval Mintz 	    HILO_64_REGPAIR(tstats.mftag_filter_discard);
16679c79ddaaSMintz, Yuval 	p_stats->common.mac_filter_discards +=
166886622ee7SYuval Mintz 	    HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1669608e00d0SManish Chopra 	p_stats->common.gft_filter_drop +=
1670608e00d0SManish Chopra 		HILO_64_REGPAIR(tstats.eth_gft_drop_pkt);
167186622ee7SYuval Mintz }
167286622ee7SYuval Mintz 
__qed_get_vport_ustats_addrlen(struct qed_hwfn * p_hwfn,u32 * p_addr,u32 * p_len,u16 statistics_bin)167386622ee7SYuval Mintz static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
167486622ee7SYuval Mintz 					   u32 *p_addr,
1675dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
167686622ee7SYuval Mintz {
1677dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
167886622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_USDM_RAM +
167986622ee7SYuval Mintz 		    USTORM_QUEUE_STAT_OFFSET(statistics_bin);
168086622ee7SYuval Mintz 		*p_len = sizeof(struct eth_ustorm_per_queue_stat);
1681dacd88d6SYuval Mintz 	} else {
1682dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1683dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1684dacd88d6SYuval Mintz 
1685dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1686dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.ustats.len;
1687dacd88d6SYuval Mintz 	}
168886622ee7SYuval Mintz }
168986622ee7SYuval Mintz 
16907c116e02SArnd Bergmann static noinline_for_stack
__qed_get_vport_ustats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_eth_stats * p_stats,u16 statistics_bin)16917c116e02SArnd Bergmann void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
16927c116e02SArnd Bergmann 			    struct qed_eth_stats *p_stats, u16 statistics_bin)
169386622ee7SYuval Mintz {
169486622ee7SYuval Mintz 	struct eth_ustorm_per_queue_stat ustats;
169586622ee7SYuval Mintz 	u32 ustats_addr = 0, ustats_len = 0;
169686622ee7SYuval Mintz 
169786622ee7SYuval Mintz 	__qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
169886622ee7SYuval Mintz 				       statistics_bin);
169986622ee7SYuval Mintz 
170086622ee7SYuval Mintz 	memset(&ustats, 0, sizeof(ustats));
1701dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
170286622ee7SYuval Mintz 
17039c79ddaaSMintz, Yuval 	p_stats->common.rx_ucast_bytes +=
17049c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
17059c79ddaaSMintz, Yuval 	p_stats->common.rx_mcast_bytes +=
17069c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
17079c79ddaaSMintz, Yuval 	p_stats->common.rx_bcast_bytes +=
17089c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
17099c79ddaaSMintz, Yuval 	p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
17109c79ddaaSMintz, Yuval 	p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
17119c79ddaaSMintz, Yuval 	p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
171286622ee7SYuval Mintz }
171386622ee7SYuval Mintz 
__qed_get_vport_mstats_addrlen(struct qed_hwfn * p_hwfn,u32 * p_addr,u32 * p_len,u16 statistics_bin)171486622ee7SYuval Mintz static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
171586622ee7SYuval Mintz 					   u32 *p_addr,
1716dacd88d6SYuval Mintz 					   u32 *p_len, u16 statistics_bin)
171786622ee7SYuval Mintz {
1718dacd88d6SYuval Mintz 	if (IS_PF(p_hwfn->cdev)) {
171986622ee7SYuval Mintz 		*p_addr = BAR0_MAP_REG_MSDM_RAM +
172086622ee7SYuval Mintz 		    MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
172186622ee7SYuval Mintz 		*p_len = sizeof(struct eth_mstorm_per_queue_stat);
1722dacd88d6SYuval Mintz 	} else {
1723dacd88d6SYuval Mintz 		struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1724dacd88d6SYuval Mintz 		struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1725dacd88d6SYuval Mintz 
1726dacd88d6SYuval Mintz 		*p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1727dacd88d6SYuval Mintz 		*p_len = p_resp->pfdev_info.stats_info.mstats.len;
1728dacd88d6SYuval Mintz 	}
172986622ee7SYuval Mintz }
173086622ee7SYuval Mintz 
17317c116e02SArnd Bergmann static noinline_for_stack void
__qed_get_vport_mstats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_eth_stats * p_stats,u16 statistics_bin)17327c116e02SArnd Bergmann __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
17337c116e02SArnd Bergmann 		       struct qed_eth_stats *p_stats, u16 statistics_bin)
173486622ee7SYuval Mintz {
173586622ee7SYuval Mintz 	struct eth_mstorm_per_queue_stat mstats;
173686622ee7SYuval Mintz 	u32 mstats_addr = 0, mstats_len = 0;
173786622ee7SYuval Mintz 
173886622ee7SYuval Mintz 	__qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
173986622ee7SYuval Mintz 				       statistics_bin);
174086622ee7SYuval Mintz 
174186622ee7SYuval Mintz 	memset(&mstats, 0, sizeof(mstats));
1742dacd88d6SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
174386622ee7SYuval Mintz 
17449c79ddaaSMintz, Yuval 	p_stats->common.no_buff_discards +=
17459c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(mstats.no_buff_discard);
17469c79ddaaSMintz, Yuval 	p_stats->common.packet_too_big_discard +=
174786622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.packet_too_big_discard);
17489c79ddaaSMintz, Yuval 	p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
17499c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_pkts +=
175086622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
17519c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_events +=
175286622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_events);
17539c79ddaaSMintz, Yuval 	p_stats->common.tpa_aborts_num +=
17549c79ddaaSMintz, Yuval 	    HILO_64_REGPAIR(mstats.tpa_aborts_num);
17559c79ddaaSMintz, Yuval 	p_stats->common.tpa_coalesced_bytes +=
175686622ee7SYuval Mintz 	    HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
175786622ee7SYuval Mintz }
175886622ee7SYuval Mintz 
17597c116e02SArnd Bergmann static noinline_for_stack void
__qed_get_vport_port_stats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_eth_stats * p_stats)17607c116e02SArnd Bergmann __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
176186622ee7SYuval Mintz 			   struct qed_eth_stats *p_stats)
176286622ee7SYuval Mintz {
17639c79ddaaSMintz, Yuval 	struct qed_eth_stats_common *p_common = &p_stats->common;
176486622ee7SYuval Mintz 	struct port_stats port_stats;
176586622ee7SYuval Mintz 	int j;
176686622ee7SYuval Mintz 
176786622ee7SYuval Mintz 	memset(&port_stats, 0, sizeof(port_stats));
176886622ee7SYuval Mintz 
176986622ee7SYuval Mintz 	qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
177086622ee7SYuval Mintz 			p_hwfn->mcp_info->port_addr +
177186622ee7SYuval Mintz 			offsetof(struct public_port, stats),
177286622ee7SYuval Mintz 			sizeof(port_stats));
177386622ee7SYuval Mintz 
17749c79ddaaSMintz, Yuval 	p_common->rx_64_byte_packets += port_stats.eth.r64;
17759c79ddaaSMintz, Yuval 	p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
17769c79ddaaSMintz, Yuval 	p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
17779c79ddaaSMintz, Yuval 	p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
17789c79ddaaSMintz, Yuval 	p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
17799c79ddaaSMintz, Yuval 	p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
17809c79ddaaSMintz, Yuval 	p_common->rx_crc_errors += port_stats.eth.rfcs;
17819c79ddaaSMintz, Yuval 	p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
17829c79ddaaSMintz, Yuval 	p_common->rx_pause_frames += port_stats.eth.rxpf;
17839c79ddaaSMintz, Yuval 	p_common->rx_pfc_frames += port_stats.eth.rxpp;
17849c79ddaaSMintz, Yuval 	p_common->rx_align_errors += port_stats.eth.raln;
17859c79ddaaSMintz, Yuval 	p_common->rx_carrier_errors += port_stats.eth.rfcr;
17869c79ddaaSMintz, Yuval 	p_common->rx_oversize_packets += port_stats.eth.rovr;
17879c79ddaaSMintz, Yuval 	p_common->rx_jabbers += port_stats.eth.rjbr;
17889c79ddaaSMintz, Yuval 	p_common->rx_undersize_packets += port_stats.eth.rund;
17899c79ddaaSMintz, Yuval 	p_common->rx_fragments += port_stats.eth.rfrg;
17909c79ddaaSMintz, Yuval 	p_common->tx_64_byte_packets += port_stats.eth.t64;
17919c79ddaaSMintz, Yuval 	p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
17929c79ddaaSMintz, Yuval 	p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
17939c79ddaaSMintz, Yuval 	p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
17949c79ddaaSMintz, Yuval 	p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
17959c79ddaaSMintz, Yuval 	p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
17969c79ddaaSMintz, Yuval 	p_common->tx_pause_frames += port_stats.eth.txpf;
17979c79ddaaSMintz, Yuval 	p_common->tx_pfc_frames += port_stats.eth.txpp;
17989c79ddaaSMintz, Yuval 	p_common->rx_mac_bytes += port_stats.eth.rbyte;
17999c79ddaaSMintz, Yuval 	p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
18009c79ddaaSMintz, Yuval 	p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
18019c79ddaaSMintz, Yuval 	p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
18029c79ddaaSMintz, Yuval 	p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
18039c79ddaaSMintz, Yuval 	p_common->tx_mac_bytes += port_stats.eth.tbyte;
18049c79ddaaSMintz, Yuval 	p_common->tx_mac_uc_packets += port_stats.eth.txuca;
18059c79ddaaSMintz, Yuval 	p_common->tx_mac_mc_packets += port_stats.eth.txmca;
18069c79ddaaSMintz, Yuval 	p_common->tx_mac_bc_packets += port_stats.eth.txbca;
18079c79ddaaSMintz, Yuval 	p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
180886622ee7SYuval Mintz 	for (j = 0; j < 8; j++) {
18099c79ddaaSMintz, Yuval 		p_common->brb_truncates += port_stats.brb.brb_truncate[j];
18109c79ddaaSMintz, Yuval 		p_common->brb_discards += port_stats.brb.brb_discard[j];
18119c79ddaaSMintz, Yuval 	}
18129c79ddaaSMintz, Yuval 
18139c79ddaaSMintz, Yuval 	if (QED_IS_BB(p_hwfn->cdev)) {
18149c79ddaaSMintz, Yuval 		struct qed_eth_stats_bb *p_bb = &p_stats->bb;
18159c79ddaaSMintz, Yuval 
18169c79ddaaSMintz, Yuval 		p_bb->rx_1519_to_1522_byte_packets +=
18179c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r1522;
18189c79ddaaSMintz, Yuval 		p_bb->rx_1519_to_2047_byte_packets +=
18199c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r2047;
18209c79ddaaSMintz, Yuval 		p_bb->rx_2048_to_4095_byte_packets +=
18219c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r4095;
18229c79ddaaSMintz, Yuval 		p_bb->rx_4096_to_9216_byte_packets +=
18239c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r9216;
18249c79ddaaSMintz, Yuval 		p_bb->rx_9217_to_16383_byte_packets +=
18259c79ddaaSMintz, Yuval 		    port_stats.eth.u0.bb0.r16383;
18269c79ddaaSMintz, Yuval 		p_bb->tx_1519_to_2047_byte_packets +=
18279c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t2047;
18289c79ddaaSMintz, Yuval 		p_bb->tx_2048_to_4095_byte_packets +=
18299c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t4095;
18309c79ddaaSMintz, Yuval 		p_bb->tx_4096_to_9216_byte_packets +=
18319c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t9216;
18329c79ddaaSMintz, Yuval 		p_bb->tx_9217_to_16383_byte_packets +=
18339c79ddaaSMintz, Yuval 		    port_stats.eth.u1.bb1.t16383;
18349c79ddaaSMintz, Yuval 		p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
18359c79ddaaSMintz, Yuval 		p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
18369c79ddaaSMintz, Yuval 	} else {
18379c79ddaaSMintz, Yuval 		struct qed_eth_stats_ah *p_ah = &p_stats->ah;
18389c79ddaaSMintz, Yuval 
18399c79ddaaSMintz, Yuval 		p_ah->rx_1519_to_max_byte_packets +=
18409c79ddaaSMintz, Yuval 		    port_stats.eth.u0.ah0.r1519_to_max;
18419c79ddaaSMintz, Yuval 		p_ah->tx_1519_to_max_byte_packets =
18429c79ddaaSMintz, Yuval 		    port_stats.eth.u1.ah1.t1519_to_max;
184386622ee7SYuval Mintz 	}
184432d26a68SSudarsana Reddy Kalluru 
184532d26a68SSudarsana Reddy Kalluru 	p_common->link_change_count = qed_rd(p_hwfn, p_ptt,
184632d26a68SSudarsana Reddy Kalluru 					     p_hwfn->mcp_info->port_addr +
184732d26a68SSudarsana Reddy Kalluru 					     offsetof(struct public_port,
184832d26a68SSudarsana Reddy Kalluru 						      link_change_count));
184986622ee7SYuval Mintz }
185086622ee7SYuval Mintz 
__qed_get_vport_stats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_eth_stats * stats,u16 statistics_bin,bool b_get_port_stats)185186622ee7SYuval Mintz static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
185286622ee7SYuval Mintz 				  struct qed_ptt *p_ptt,
185386622ee7SYuval Mintz 				  struct qed_eth_stats *stats,
1854dacd88d6SYuval Mintz 				  u16 statistics_bin, bool b_get_port_stats)
185586622ee7SYuval Mintz {
185686622ee7SYuval Mintz 	__qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
185786622ee7SYuval Mintz 	__qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
185886622ee7SYuval Mintz 	__qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
185986622ee7SYuval Mintz 	__qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
186086622ee7SYuval Mintz 
1861dacd88d6SYuval Mintz 	if (b_get_port_stats && p_hwfn->mcp_info)
186286622ee7SYuval Mintz 		__qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
186386622ee7SYuval Mintz }
186486622ee7SYuval Mintz 
_qed_get_vport_stats(struct qed_dev * cdev,struct qed_eth_stats * stats,bool is_atomic)186586622ee7SYuval Mintz static void _qed_get_vport_stats(struct qed_dev *cdev,
1866*e346e231SKonstantin Khorenko 				 struct qed_eth_stats *stats,
1867*e346e231SKonstantin Khorenko 				 bool is_atomic)
186886622ee7SYuval Mintz {
186986622ee7SYuval Mintz 	u8 fw_vport = 0;
187086622ee7SYuval Mintz 	int i;
187186622ee7SYuval Mintz 
187286622ee7SYuval Mintz 	memset(stats, 0, sizeof(*stats));
187386622ee7SYuval Mintz 
187486622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
187586622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1876*e346e231SKonstantin Khorenko 		struct qed_ptt *p_ptt;
18770ebcebbeSSudarsana Reddy Kalluru 		bool b_get_port_stats;
187886622ee7SYuval Mintz 
1879*e346e231SKonstantin Khorenko 		p_ptt = IS_PF(cdev) ? qed_ptt_acquire_context(p_hwfn, is_atomic)
1880*e346e231SKonstantin Khorenko 				    : NULL;
1881dacd88d6SYuval Mintz 		if (IS_PF(cdev)) {
188286622ee7SYuval Mintz 			/* The main vport index is relative first */
188386622ee7SYuval Mintz 			if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
188486622ee7SYuval Mintz 				DP_ERR(p_hwfn, "No vport available!\n");
1885dacd88d6SYuval Mintz 				goto out;
1886dacd88d6SYuval Mintz 			}
188786622ee7SYuval Mintz 		}
188886622ee7SYuval Mintz 
1889dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
189086622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
189186622ee7SYuval Mintz 			continue;
189286622ee7SYuval Mintz 		}
189386622ee7SYuval Mintz 
18940ebcebbeSSudarsana Reddy Kalluru 		b_get_port_stats = IS_PF(cdev) && IS_LEAD_HWFN(p_hwfn);
1895dacd88d6SYuval Mintz 		__qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
18960ebcebbeSSudarsana Reddy Kalluru 				      b_get_port_stats);
189786622ee7SYuval Mintz 
1898dacd88d6SYuval Mintz out:
1899dacd88d6SYuval Mintz 		if (IS_PF(cdev) && p_ptt)
190086622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
190186622ee7SYuval Mintz 	}
190286622ee7SYuval Mintz }
190386622ee7SYuval Mintz 
qed_get_vport_stats(struct qed_dev * cdev,struct qed_eth_stats * stats)19041a635e48SYuval Mintz void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
190586622ee7SYuval Mintz {
1906*e346e231SKonstantin Khorenko 	qed_get_vport_stats_context(cdev, stats, false);
1907*e346e231SKonstantin Khorenko }
1908*e346e231SKonstantin Khorenko 
qed_get_vport_stats_context(struct qed_dev * cdev,struct qed_eth_stats * stats,bool is_atomic)1909*e346e231SKonstantin Khorenko void qed_get_vport_stats_context(struct qed_dev *cdev,
1910*e346e231SKonstantin Khorenko 				 struct qed_eth_stats *stats,
1911*e346e231SKonstantin Khorenko 				 bool is_atomic)
1912*e346e231SKonstantin Khorenko {
191386622ee7SYuval Mintz 	u32 i;
191486622ee7SYuval Mintz 
191542510dffSManish Chopra 	if (!cdev || cdev->recov_in_prog) {
191686622ee7SYuval Mintz 		memset(stats, 0, sizeof(*stats));
191786622ee7SYuval Mintz 		return;
191886622ee7SYuval Mintz 	}
191986622ee7SYuval Mintz 
1920*e346e231SKonstantin Khorenko 	_qed_get_vport_stats(cdev, stats, is_atomic);
192186622ee7SYuval Mintz 
192286622ee7SYuval Mintz 	if (!cdev->reset_stats)
192386622ee7SYuval Mintz 		return;
192486622ee7SYuval Mintz 
192586622ee7SYuval Mintz 	/* Reduce the statistics baseline */
192686622ee7SYuval Mintz 	for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
192786622ee7SYuval Mintz 		((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
192886622ee7SYuval Mintz }
192986622ee7SYuval Mintz 
193086622ee7SYuval Mintz /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
qed_reset_vport_stats(struct qed_dev * cdev)193186622ee7SYuval Mintz void qed_reset_vport_stats(struct qed_dev *cdev)
193286622ee7SYuval Mintz {
193386622ee7SYuval Mintz 	int i;
193486622ee7SYuval Mintz 
193586622ee7SYuval Mintz 	for_each_hwfn(cdev, i) {
193686622ee7SYuval Mintz 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
193786622ee7SYuval Mintz 		struct eth_mstorm_per_queue_stat mstats;
193886622ee7SYuval Mintz 		struct eth_ustorm_per_queue_stat ustats;
193986622ee7SYuval Mintz 		struct eth_pstorm_per_queue_stat pstats;
1940dacd88d6SYuval Mintz 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1941dacd88d6SYuval Mintz 						    : NULL;
194286622ee7SYuval Mintz 		u32 addr = 0, len = 0;
194386622ee7SYuval Mintz 
1944dacd88d6SYuval Mintz 		if (IS_PF(cdev) && !p_ptt) {
194586622ee7SYuval Mintz 			DP_ERR(p_hwfn, "Failed to acquire ptt\n");
194686622ee7SYuval Mintz 			continue;
194786622ee7SYuval Mintz 		}
194886622ee7SYuval Mintz 
194986622ee7SYuval Mintz 		memset(&mstats, 0, sizeof(mstats));
195086622ee7SYuval Mintz 		__qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
195186622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
195286622ee7SYuval Mintz 
195386622ee7SYuval Mintz 		memset(&ustats, 0, sizeof(ustats));
195486622ee7SYuval Mintz 		__qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
195586622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
195686622ee7SYuval Mintz 
195786622ee7SYuval Mintz 		memset(&pstats, 0, sizeof(pstats));
195886622ee7SYuval Mintz 		__qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
195986622ee7SYuval Mintz 		qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
196086622ee7SYuval Mintz 
1961dacd88d6SYuval Mintz 		if (IS_PF(cdev))
196286622ee7SYuval Mintz 			qed_ptt_release(p_hwfn, p_ptt);
196386622ee7SYuval Mintz 	}
196486622ee7SYuval Mintz 
196586622ee7SYuval Mintz 	/* PORT statistics are not necessarily reset, so we need to
196686622ee7SYuval Mintz 	 * read and create a baseline for future statistics.
196732d26a68SSudarsana Reddy Kalluru 	 * Link change stat is maintained by MFW, return its value as is.
196886622ee7SYuval Mintz 	 */
196932d26a68SSudarsana Reddy Kalluru 	if (!cdev->reset_stats) {
197086622ee7SYuval Mintz 		DP_INFO(cdev, "Reset stats not allocated\n");
197132d26a68SSudarsana Reddy Kalluru 	} else {
1972*e346e231SKonstantin Khorenko 		_qed_get_vport_stats(cdev, cdev->reset_stats, false);
197332d26a68SSudarsana Reddy Kalluru 		cdev->reset_stats->common.link_change_count = 0;
197432d26a68SSudarsana Reddy Kalluru 	}
197586622ee7SYuval Mintz }
197686622ee7SYuval Mintz 
1977da090917STomer Tayar static enum gft_profile_type
qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode)1978da090917STomer Tayar qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode)
1979da090917STomer Tayar {
1980da090917STomer Tayar 	if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE)
1981da090917STomer Tayar 		return GFT_PROFILE_TYPE_4_TUPLE;
1982da090917STomer Tayar 	if (mode == QED_FILTER_CONFIG_MODE_IP_DEST)
198350bc60cbSMichal Kalderon 		return GFT_PROFILE_TYPE_IP_DST_ADDR;
19843893fc62SManish Chopra 	if (mode == QED_FILTER_CONFIG_MODE_IP_SRC)
19853893fc62SManish Chopra 		return GFT_PROFILE_TYPE_IP_SRC_ADDR;
1986da090917STomer Tayar 	return GFT_PROFILE_TYPE_L4_DST_PORT;
1987da090917STomer Tayar }
1988da090917STomer Tayar 
qed_arfs_mode_configure(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_arfs_config_params * p_cfg_params)1989da090917STomer Tayar void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn,
1990da090917STomer Tayar 			     struct qed_ptt *p_ptt,
1991d51e4af5SChopra, Manish 			     struct qed_arfs_config_params *p_cfg_params)
1992d51e4af5SChopra, Manish {
19932d2fe843SDmitry Bogdanov 	if (test_bit(QED_MF_DISABLE_ARFS, &p_hwfn->cdev->mf_bits))
19942d2fe843SDmitry Bogdanov 		return;
19952d2fe843SDmitry Bogdanov 
1996da090917STomer Tayar 	if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) {
1997da090917STomer Tayar 		qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1998da090917STomer Tayar 			       p_cfg_params->tcp,
1999da090917STomer Tayar 			       p_cfg_params->udp,
2000da090917STomer Tayar 			       p_cfg_params->ipv4,
2001da090917STomer Tayar 			       p_cfg_params->ipv6,
2002da090917STomer Tayar 			       qed_arfs_mode_to_hsi(p_cfg_params->mode));
2003da090917STomer Tayar 		DP_VERBOSE(p_hwfn,
2004da090917STomer Tayar 			   QED_MSG_SP,
2005da090917STomer Tayar 			   "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n",
2006d51e4af5SChopra, Manish 			   p_cfg_params->tcp ? "Enable" : "Disable",
2007d51e4af5SChopra, Manish 			   p_cfg_params->udp ? "Enable" : "Disable",
2008d51e4af5SChopra, Manish 			   p_cfg_params->ipv4 ? "Enable" : "Disable",
2009da090917STomer Tayar 			   p_cfg_params->ipv6 ? "Enable" : "Disable",
2010da090917STomer Tayar 			   (u32)p_cfg_params->mode);
2011d51e4af5SChopra, Manish 	} else {
2012da090917STomer Tayar 		DP_VERBOSE(p_hwfn, QED_MSG_SP, "Disabled Filtering\n");
2013da090917STomer Tayar 		qed_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2014da090917STomer Tayar 	}
2015d51e4af5SChopra, Manish }
2016d51e4af5SChopra, Manish 
2017da090917STomer Tayar int
qed_configure_rfs_ntuple_filter(struct qed_hwfn * p_hwfn,struct qed_spq_comp_cb * p_cb,struct qed_ntuple_filter_params * p_params)2018da090917STomer Tayar qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
2019d51e4af5SChopra, Manish 				struct qed_spq_comp_cb *p_cb,
2020da090917STomer Tayar 				struct qed_ntuple_filter_params *p_params)
2021d51e4af5SChopra, Manish {
2022fe40a830SPrabhakar Kushwaha 	struct rx_update_gft_filter_ramrod_data *p_ramrod = NULL;
2023d51e4af5SChopra, Manish 	struct qed_spq_entry *p_ent = NULL;
2024d51e4af5SChopra, Manish 	struct qed_sp_init_data init_data;
2025d51e4af5SChopra, Manish 	u16 abs_rx_q_id = 0;
2026d51e4af5SChopra, Manish 	u8 abs_vport_id = 0;
2027d51e4af5SChopra, Manish 	int rc = -EINVAL;
2028d51e4af5SChopra, Manish 
2029d51e4af5SChopra, Manish 	/* Get SPQ entry */
2030d51e4af5SChopra, Manish 	memset(&init_data, 0, sizeof(init_data));
2031d51e4af5SChopra, Manish 	init_data.cid = qed_spq_get_cid(p_hwfn);
2032d51e4af5SChopra, Manish 
2033d51e4af5SChopra, Manish 	init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2034d51e4af5SChopra, Manish 
2035d51e4af5SChopra, Manish 	if (p_cb) {
2036d51e4af5SChopra, Manish 		init_data.comp_mode = QED_SPQ_MODE_CB;
2037d51e4af5SChopra, Manish 		init_data.p_comp_data = p_cb;
2038d51e4af5SChopra, Manish 	} else {
2039d51e4af5SChopra, Manish 		init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2040d51e4af5SChopra, Manish 	}
2041d51e4af5SChopra, Manish 
2042d51e4af5SChopra, Manish 	rc = qed_sp_init_request(p_hwfn, &p_ent,
2043fe40a830SPrabhakar Kushwaha 				 ETH_RAMROD_RX_UPDATE_GFT_FILTER,
2044d51e4af5SChopra, Manish 				 PROTOCOLID_ETH, &init_data);
2045d51e4af5SChopra, Manish 	if (rc)
2046d51e4af5SChopra, Manish 		return rc;
2047d51e4af5SChopra, Manish 
2048d51e4af5SChopra, Manish 	p_ramrod = &p_ent->ramrod.rx_update_gft;
2049da090917STomer Tayar 
2050da090917STomer Tayar 	DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr);
2051da090917STomer Tayar 	p_ramrod->pkt_hdr_length = cpu_to_le16(p_params->length);
2052da090917STomer Tayar 
2053608e00d0SManish Chopra 	if (p_params->b_is_drop) {
2054608e00d0SManish Chopra 		p_ramrod->vport_id = cpu_to_le16(ETH_GFT_TRASHCAN_VPORT);
2055608e00d0SManish Chopra 	} else {
2056608e00d0SManish Chopra 		rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
2057608e00d0SManish Chopra 		if (rc)
2058fb5e7438SDenis Bolotin 			goto err;
2059608e00d0SManish Chopra 
2060da090917STomer Tayar 		if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) {
2061608e00d0SManish Chopra 			rc = qed_fw_l2_queue(p_hwfn, p_params->qid,
2062608e00d0SManish Chopra 					     &abs_rx_q_id);
2063608e00d0SManish Chopra 			if (rc)
2064fb5e7438SDenis Bolotin 				goto err;
2065608e00d0SManish Chopra 
2066da090917STomer Tayar 			p_ramrod->rx_qid_valid = 1;
2067da090917STomer Tayar 			p_ramrod->rx_qid = cpu_to_le16(abs_rx_q_id);
2068da090917STomer Tayar 		}
2069da090917STomer Tayar 
2070608e00d0SManish Chopra 		p_ramrod->vport_id = cpu_to_le16((u16)abs_vport_id);
2071608e00d0SManish Chopra 	}
2072608e00d0SManish Chopra 
2073da090917STomer Tayar 	p_ramrod->flow_id_valid = 0;
2074da090917STomer Tayar 	p_ramrod->flow_id = 0;
2075da090917STomer Tayar 	p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER
2076da090917STomer Tayar 	    : GFT_DELETE_FILTER;
2077d51e4af5SChopra, Manish 
2078d51e4af5SChopra, Manish 	DP_VERBOSE(p_hwfn, QED_MSG_SP,
2079d51e4af5SChopra, Manish 		   "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
2080d51e4af5SChopra, Manish 		   abs_vport_id, abs_rx_q_id,
2081da090917STomer Tayar 		   p_params->b_is_add ? "Adding" : "Removing",
2082da090917STomer Tayar 		   (u64)p_params->addr, p_params->length);
2083d51e4af5SChopra, Manish 
2084d51e4af5SChopra, Manish 	return qed_spq_post(p_hwfn, p_ent, NULL);
2085fb5e7438SDenis Bolotin 
2086fb5e7438SDenis Bolotin err:
2087fb5e7438SDenis Bolotin 	qed_sp_destroy_request(p_hwfn, p_ent);
2088fb5e7438SDenis Bolotin 	return rc;
2089d51e4af5SChopra, Manish }
2090d51e4af5SChopra, Manish 
qed_get_rxq_coalesce(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_queue_cid * p_cid,u16 * p_rx_coal)2091bf5a94bfSRahul Verma int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,
2092bf5a94bfSRahul Verma 			 struct qed_ptt *p_ptt,
2093bf5a94bfSRahul Verma 			 struct qed_queue_cid *p_cid, u16 *p_rx_coal)
2094bf5a94bfSRahul Verma {
2095bf5a94bfSRahul Verma 	u32 coalesce, address, is_valid;
2096bf5a94bfSRahul Verma 	struct cau_sb_entry sb_entry;
2097bf5a94bfSRahul Verma 	u8 timer_res;
2098bf5a94bfSRahul Verma 	int rc;
2099bf5a94bfSRahul Verma 
2100bf5a94bfSRahul Verma 	rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2101bf5a94bfSRahul Verma 			       p_cid->sb_igu_id * sizeof(u64),
210283bf76e3SMichal Kalderon 			       (u64)(uintptr_t)&sb_entry, 2, NULL);
2103bf5a94bfSRahul Verma 	if (rc) {
2104bf5a94bfSRahul Verma 		DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2105bf5a94bfSRahul Verma 		return rc;
2106bf5a94bfSRahul Verma 	}
2107bf5a94bfSRahul Verma 
21085ab90341SAlexander Lobakin 	timer_res = GET_FIELD(le32_to_cpu(sb_entry.params),
21095ab90341SAlexander Lobakin 			      CAU_SB_ENTRY_TIMER_RES0);
2110bf5a94bfSRahul Verma 
2111bf5a94bfSRahul Verma 	address = BAR0_MAP_REG_USDM_RAM +
2112e2dbc223SPrabhakar Kushwaha 		  USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id);
2113bf5a94bfSRahul Verma 	coalesce = qed_rd(p_hwfn, p_ptt, address);
2114bf5a94bfSRahul Verma 
2115bf5a94bfSRahul Verma 	is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2116bf5a94bfSRahul Verma 	if (!is_valid)
2117bf5a94bfSRahul Verma 		return -EINVAL;
2118bf5a94bfSRahul Verma 
2119bf5a94bfSRahul Verma 	coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2120bf5a94bfSRahul Verma 	*p_rx_coal = (u16)(coalesce << timer_res);
2121bf5a94bfSRahul Verma 
2122bf5a94bfSRahul Verma 	return 0;
2123bf5a94bfSRahul Verma }
2124bf5a94bfSRahul Verma 
qed_get_txq_coalesce(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_queue_cid * p_cid,u16 * p_tx_coal)2125bf5a94bfSRahul Verma int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,
2126bf5a94bfSRahul Verma 			 struct qed_ptt *p_ptt,
2127bf5a94bfSRahul Verma 			 struct qed_queue_cid *p_cid, u16 *p_tx_coal)
2128bf5a94bfSRahul Verma {
2129bf5a94bfSRahul Verma 	u32 coalesce, address, is_valid;
2130bf5a94bfSRahul Verma 	struct cau_sb_entry sb_entry;
2131bf5a94bfSRahul Verma 	u8 timer_res;
2132bf5a94bfSRahul Verma 	int rc;
2133bf5a94bfSRahul Verma 
2134bf5a94bfSRahul Verma 	rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2135bf5a94bfSRahul Verma 			       p_cid->sb_igu_id * sizeof(u64),
213683bf76e3SMichal Kalderon 			       (u64)(uintptr_t)&sb_entry, 2, NULL);
2137bf5a94bfSRahul Verma 	if (rc) {
2138bf5a94bfSRahul Verma 		DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2139bf5a94bfSRahul Verma 		return rc;
2140bf5a94bfSRahul Verma 	}
2141bf5a94bfSRahul Verma 
21425ab90341SAlexander Lobakin 	timer_res = GET_FIELD(le32_to_cpu(sb_entry.params),
21435ab90341SAlexander Lobakin 			      CAU_SB_ENTRY_TIMER_RES1);
2144bf5a94bfSRahul Verma 
2145bf5a94bfSRahul Verma 	address = BAR0_MAP_REG_XSDM_RAM +
2146e2dbc223SPrabhakar Kushwaha 		  XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id);
2147bf5a94bfSRahul Verma 	coalesce = qed_rd(p_hwfn, p_ptt, address);
2148bf5a94bfSRahul Verma 
2149bf5a94bfSRahul Verma 	is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2150bf5a94bfSRahul Verma 	if (!is_valid)
2151bf5a94bfSRahul Verma 		return -EINVAL;
2152bf5a94bfSRahul Verma 
2153bf5a94bfSRahul Verma 	coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2154bf5a94bfSRahul Verma 	*p_tx_coal = (u16)(coalesce << timer_res);
2155bf5a94bfSRahul Verma 
2156bf5a94bfSRahul Verma 	return 0;
2157bf5a94bfSRahul Verma }
2158bf5a94bfSRahul Verma 
qed_get_queue_coalesce(struct qed_hwfn * p_hwfn,u16 * p_coal,void * handle)2159bf5a94bfSRahul Verma int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle)
2160bf5a94bfSRahul Verma {
2161bf5a94bfSRahul Verma 	struct qed_queue_cid *p_cid = handle;
2162bf5a94bfSRahul Verma 	struct qed_ptt *p_ptt;
2163bf5a94bfSRahul Verma 	int rc = 0;
2164bf5a94bfSRahul Verma 
2165bf5a94bfSRahul Verma 	if (IS_VF(p_hwfn->cdev)) {
2166bf5a94bfSRahul Verma 		rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);
2167bf5a94bfSRahul Verma 		if (rc)
2168bf5a94bfSRahul Verma 			DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
2169bf5a94bfSRahul Verma 
2170bf5a94bfSRahul Verma 		return rc;
2171bf5a94bfSRahul Verma 	}
2172bf5a94bfSRahul Verma 
2173bf5a94bfSRahul Verma 	p_ptt = qed_ptt_acquire(p_hwfn);
2174bf5a94bfSRahul Verma 	if (!p_ptt)
2175bf5a94bfSRahul Verma 		return -EAGAIN;
2176bf5a94bfSRahul Verma 
2177bf5a94bfSRahul Verma 	if (p_cid->b_is_rx) {
2178bf5a94bfSRahul Verma 		rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2179bf5a94bfSRahul Verma 		if (rc)
2180bf5a94bfSRahul Verma 			goto out;
2181bf5a94bfSRahul Verma 	} else {
2182bf5a94bfSRahul Verma 		rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2183bf5a94bfSRahul Verma 		if (rc)
2184bf5a94bfSRahul Verma 			goto out;
2185bf5a94bfSRahul Verma 	}
2186bf5a94bfSRahul Verma 
2187bf5a94bfSRahul Verma out:
2188bf5a94bfSRahul Verma 	qed_ptt_release(p_hwfn, p_ptt);
2189bf5a94bfSRahul Verma 
2190bf5a94bfSRahul Verma 	return rc;
2191bf5a94bfSRahul Verma }
2192bf5a94bfSRahul Verma 
qed_fill_eth_dev_info(struct qed_dev * cdev,struct qed_dev_eth_info * info)219325c089d7SYuval Mintz static int qed_fill_eth_dev_info(struct qed_dev *cdev,
219425c089d7SYuval Mintz 				 struct qed_dev_eth_info *info)
219525c089d7SYuval Mintz {
21965e7baf0fSManish Chopra 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
219725c089d7SYuval Mintz 	int i;
219825c089d7SYuval Mintz 
219925c089d7SYuval Mintz 	memset(info, 0, sizeof(*info));
220025c089d7SYuval Mintz 
22011408cc1fSYuval Mintz 	if (IS_PF(cdev)) {
220225eb8d46SYuval Mintz 		int max_vf_vlan_filters = 0;
22037b7e70f9SYuval Mintz 		int max_vf_mac_filters = 0;
220425eb8d46SYuval Mintz 
22055e7baf0fSManish Chopra 		info->num_tc = p_hwfn->hw_info.num_hw_tc;
22065e7baf0fSManish Chopra 
220725c089d7SYuval Mintz 		if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
2208e1d32acbSMintz, Yuval 			u16 num_queues = 0;
2209e1d32acbSMintz, Yuval 
2210e1d32acbSMintz, Yuval 			/* Since the feature controls only queue-zones,
2211fb1faab7SSudarsana Reddy Kalluru 			 * make sure we have the contexts [rx, xdp, tcs] to
2212e1d32acbSMintz, Yuval 			 * match.
2213e1d32acbSMintz, Yuval 			 */
2214e1d32acbSMintz, Yuval 			for_each_hwfn(cdev, i) {
2215e1d32acbSMintz, Yuval 				struct qed_hwfn *hwfn = &cdev->hwfns[i];
2216e1d32acbSMintz, Yuval 				u16 l2_queues = (u16)FEAT_NUM(hwfn,
2217e1d32acbSMintz, Yuval 							      QED_PF_L2_QUE);
2218e1d32acbSMintz, Yuval 				u16 cids;
2219e1d32acbSMintz, Yuval 
2220e1d32acbSMintz, Yuval 				cids = hwfn->pf_params.eth_pf_params.num_cons;
2221fb1faab7SSudarsana Reddy Kalluru 				cids /= (2 + info->num_tc);
2222fb1faab7SSudarsana Reddy Kalluru 				num_queues += min_t(u16, l2_queues, cids);
2223e1d32acbSMintz, Yuval 			}
2224e1d32acbSMintz, Yuval 
2225e1d32acbSMintz, Yuval 			/* queues might theoretically be >256, but interrupts'
2226e1d32acbSMintz, Yuval 			 * upper-limit guarantes that it would fit in a u8.
2227e1d32acbSMintz, Yuval 			 */
2228e1d32acbSMintz, Yuval 			if (cdev->int_params.fp_msix_cnt) {
2229e1d32acbSMintz, Yuval 				u8 irqs = cdev->int_params.fp_msix_cnt;
2230e1d32acbSMintz, Yuval 
2231e1d32acbSMintz, Yuval 				info->num_queues = (u8)min_t(u16,
2232e1d32acbSMintz, Yuval 							     num_queues, irqs);
2233e1d32acbSMintz, Yuval 			}
223425c089d7SYuval Mintz 		} else {
223525c089d7SYuval Mintz 			info->num_queues = cdev->num_hwfns;
223625c089d7SYuval Mintz 		}
223725c089d7SYuval Mintz 
22387b7e70f9SYuval Mintz 		if (IS_QED_SRIOV(cdev)) {
223925eb8d46SYuval Mintz 			max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
224025eb8d46SYuval Mintz 					      QED_ETH_VF_NUM_VLAN_FILTERS;
22417b7e70f9SYuval Mintz 			max_vf_mac_filters = cdev->p_iov_info->total_vfs *
22427b7e70f9SYuval Mintz 					     QED_ETH_VF_NUM_MAC_FILTERS;
22437b7e70f9SYuval Mintz 		}
22447b7e70f9SYuval Mintz 		info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
22457b7e70f9SYuval Mintz 						  QED_VLAN) -
224625eb8d46SYuval Mintz 					 max_vf_vlan_filters;
22477b7e70f9SYuval Mintz 		info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
22487b7e70f9SYuval Mintz 						 QED_MAC) -
22497b7e70f9SYuval Mintz 					max_vf_mac_filters;
225025eb8d46SYuval Mintz 
225125c089d7SYuval Mintz 		ether_addr_copy(info->port_mac,
225225c089d7SYuval Mintz 				cdev->hwfns[0].hw_info.hw_mac_addr);
22531408cc1fSYuval Mintz 
2254cbb8a12cSMintz, Yuval 		info->xdp_supported = true;
2255cbb8a12cSMintz, Yuval 	} else {
2256cbb8a12cSMintz, Yuval 		u16 total_cids = 0;
2257cbb8a12cSMintz, Yuval 
22585e7baf0fSManish Chopra 		info->num_tc = 1;
22595e7baf0fSManish Chopra 
2260cbb8a12cSMintz, Yuval 		/* Determine queues &  XDP support */
2261cbb8a12cSMintz, Yuval 		for_each_hwfn(cdev, i) {
2262cbb8a12cSMintz, Yuval 			struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2263cbb8a12cSMintz, Yuval 			u8 queues, cids;
2264cbb8a12cSMintz, Yuval 
2265cbb8a12cSMintz, Yuval 			qed_vf_get_num_cids(p_hwfn, &cids);
2266cbb8a12cSMintz, Yuval 			qed_vf_get_num_rxqs(p_hwfn, &queues);
22671408cc1fSYuval Mintz 			info->num_queues += queues;
2268cbb8a12cSMintz, Yuval 			total_cids += cids;
22691408cc1fSYuval Mintz 		}
22701408cc1fSYuval Mintz 
2271cbb8a12cSMintz, Yuval 		/* Enable VF XDP in case PF guarntees sufficient connections */
2272cbb8a12cSMintz, Yuval 		if (total_cids >= info->num_queues * 3)
2273cbb8a12cSMintz, Yuval 			info->xdp_supported = true;
2274cbb8a12cSMintz, Yuval 
22751408cc1fSYuval Mintz 		qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
22762edbff8dSTomer Tayar 					    (u8 *)&info->num_vlan_filters);
2277b0fca312SMintz, Yuval 		qed_vf_get_num_mac_filters(&cdev->hwfns[0],
2278b0fca312SMintz, Yuval 					   (u8 *)&info->num_mac_filters);
22791408cc1fSYuval Mintz 		qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
2280d8c2c7e3SYuval Mintz 
2281d8c2c7e3SYuval Mintz 		info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
22821408cc1fSYuval Mintz 	}
228325c089d7SYuval Mintz 
228425c089d7SYuval Mintz 	qed_fill_dev_info(cdev, &info->common);
228525c089d7SYuval Mintz 
22861408cc1fSYuval Mintz 	if (IS_VF(cdev))
22870ee28e31SShyam Saini 		eth_zero_addr(info->common.hw_mac);
22881408cc1fSYuval Mintz 
228925c089d7SYuval Mintz 	return 0;
229025c089d7SYuval Mintz }
229125c089d7SYuval Mintz 
qed_register_eth_ops(struct qed_dev * cdev,struct qed_eth_cb_ops * ops,void * cookie)2292cc875c2eSYuval Mintz static void qed_register_eth_ops(struct qed_dev *cdev,
22931408cc1fSYuval Mintz 				 struct qed_eth_cb_ops *ops, void *cookie)
2294cc875c2eSYuval Mintz {
2295cc875c2eSYuval Mintz 	cdev->protocol_ops.eth = ops;
2296cc875c2eSYuval Mintz 	cdev->ops_cookie = cookie;
22971408cc1fSYuval Mintz 
22981408cc1fSYuval Mintz 	/* For VF, we start bulletin reading */
22991408cc1fSYuval Mintz 	if (IS_VF(cdev))
23001408cc1fSYuval Mintz 		qed_vf_start_iov_wq(cdev);
2301cc875c2eSYuval Mintz }
2302cc875c2eSYuval Mintz 
qed_check_mac(struct qed_dev * cdev,u8 * mac)2303eff16960SYuval Mintz static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
2304eff16960SYuval Mintz {
2305eff16960SYuval Mintz 	if (IS_PF(cdev))
2306eff16960SYuval Mintz 		return true;
2307eff16960SYuval Mintz 
2308eff16960SYuval Mintz 	return qed_vf_check_mac(&cdev->hwfns[0], mac);
2309eff16960SYuval Mintz }
2310eff16960SYuval Mintz 
qed_start_vport(struct qed_dev * cdev,struct qed_start_vport_params * params)2311cee4d264SManish Chopra static int qed_start_vport(struct qed_dev *cdev,
2312088c8618SManish Chopra 			   struct qed_start_vport_params *params)
2313cee4d264SManish Chopra {
2314cee4d264SManish Chopra 	int rc, i;
2315cee4d264SManish Chopra 
2316cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2317088c8618SManish Chopra 		struct qed_sp_vport_start_params start = { 0 };
2318cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2319cee4d264SManish Chopra 
2320088c8618SManish Chopra 		start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
2321088c8618SManish Chopra 							QED_TPA_MODE_NONE;
2322088c8618SManish Chopra 		start.remove_inner_vlan = params->remove_inner_vlan;
232308feecd7SYuval Mintz 		start.only_untagged = true;	/* untagged only */
2324088c8618SManish Chopra 		start.drop_ttl0 = params->drop_ttl0;
2325088c8618SManish Chopra 		start.opaque_fid = p_hwfn->hw_info.opaque_fid;
2326088c8618SManish Chopra 		start.concrete_fid = p_hwfn->hw_info.concrete_fid;
2327c78c70faSSudarsana Reddy Kalluru 		start.handle_ptp_pkts = params->handle_ptp_pkts;
2328088c8618SManish Chopra 		start.vport_id = params->vport_id;
2329088c8618SManish Chopra 		start.max_buffers_per_cqe = 16;
2330088c8618SManish Chopra 		start.mtu = params->mtu;
2331cee4d264SManish Chopra 
2332088c8618SManish Chopra 		rc = qed_sp_vport_start(p_hwfn, &start);
2333cee4d264SManish Chopra 		if (rc) {
2334cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to start VPORT\n");
2335cee4d264SManish Chopra 			return rc;
2336cee4d264SManish Chopra 		}
2337cee4d264SManish Chopra 
233815582962SRahul Verma 		rc = qed_hw_start_fastpath(p_hwfn);
233915582962SRahul Verma 		if (rc) {
234015582962SRahul Verma 			DP_ERR(cdev, "Failed to start VPORT fastpath\n");
234115582962SRahul Verma 			return rc;
234215582962SRahul Verma 		}
2343cee4d264SManish Chopra 
2344cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2345cee4d264SManish Chopra 			   "Started V-PORT %d with MTU %d\n",
2346088c8618SManish Chopra 			   start.vport_id, start.mtu);
2347cee4d264SManish Chopra 	}
2348cee4d264SManish Chopra 
2349a0d26d5aSYuval Mintz 	if (params->clear_stats)
23509df2ed04SManish Chopra 		qed_reset_vport_stats(cdev);
23519df2ed04SManish Chopra 
2352cee4d264SManish Chopra 	return 0;
2353cee4d264SManish Chopra }
2354cee4d264SManish Chopra 
qed_stop_vport(struct qed_dev * cdev,u8 vport_id)23551a635e48SYuval Mintz static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
2356cee4d264SManish Chopra {
2357cee4d264SManish Chopra 	int rc, i;
2358cee4d264SManish Chopra 
2359cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2360cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2361cee4d264SManish Chopra 
2362cee4d264SManish Chopra 		rc = qed_sp_vport_stop(p_hwfn,
23631a635e48SYuval Mintz 				       p_hwfn->hw_info.opaque_fid, vport_id);
2364cee4d264SManish Chopra 
2365cee4d264SManish Chopra 		if (rc) {
2366cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to stop VPORT\n");
2367cee4d264SManish Chopra 			return rc;
2368cee4d264SManish Chopra 		}
2369cee4d264SManish Chopra 	}
2370cee4d264SManish Chopra 	return 0;
2371cee4d264SManish Chopra }
2372cee4d264SManish Chopra 
qed_update_vport_rss(struct qed_dev * cdev,struct qed_update_vport_rss_params * input,struct qed_rss_params * rss)2373f29ffdb6SMintz, Yuval static int qed_update_vport_rss(struct qed_dev *cdev,
2374f29ffdb6SMintz, Yuval 				struct qed_update_vport_rss_params *input,
2375f29ffdb6SMintz, Yuval 				struct qed_rss_params *rss)
2376f29ffdb6SMintz, Yuval {
2377f29ffdb6SMintz, Yuval 	int i, fn;
2378f29ffdb6SMintz, Yuval 
2379f29ffdb6SMintz, Yuval 	/* Update configuration with what's correct regardless of CMT */
2380f29ffdb6SMintz, Yuval 	rss->update_rss_config = 1;
2381f29ffdb6SMintz, Yuval 	rss->rss_enable = 1;
2382f29ffdb6SMintz, Yuval 	rss->update_rss_capabilities = 1;
2383f29ffdb6SMintz, Yuval 	rss->update_rss_ind_table = 1;
2384f29ffdb6SMintz, Yuval 	rss->update_rss_key = 1;
2385f29ffdb6SMintz, Yuval 	rss->rss_caps = input->rss_caps;
2386f29ffdb6SMintz, Yuval 	memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
2387f29ffdb6SMintz, Yuval 
2388f29ffdb6SMintz, Yuval 	/* In regular scenario, we'd simply need to take input handlers.
2389f29ffdb6SMintz, Yuval 	 * But in CMT, we'd have to split the handlers according to the
2390f29ffdb6SMintz, Yuval 	 * engine they were configured on. We'd then have to understand
2391f29ffdb6SMintz, Yuval 	 * whether RSS is really required, since 2-queues on CMT doesn't
2392f29ffdb6SMintz, Yuval 	 * require RSS.
2393f29ffdb6SMintz, Yuval 	 */
2394f29ffdb6SMintz, Yuval 	if (cdev->num_hwfns == 1) {
2395f29ffdb6SMintz, Yuval 		memcpy(rss->rss_ind_table,
2396f29ffdb6SMintz, Yuval 		       input->rss_ind_table,
2397f29ffdb6SMintz, Yuval 		       QED_RSS_IND_TABLE_SIZE * sizeof(void *));
2398f29ffdb6SMintz, Yuval 		rss->rss_table_size_log = 7;
2399f29ffdb6SMintz, Yuval 		return 0;
2400f29ffdb6SMintz, Yuval 	}
2401f29ffdb6SMintz, Yuval 
2402f29ffdb6SMintz, Yuval 	/* Start by copying the non-spcific information to the 2nd copy */
2403f29ffdb6SMintz, Yuval 	memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
2404f29ffdb6SMintz, Yuval 
2405f29ffdb6SMintz, Yuval 	/* CMT should be round-robin */
2406f29ffdb6SMintz, Yuval 	for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
2407f29ffdb6SMintz, Yuval 		struct qed_queue_cid *cid = input->rss_ind_table[i];
2408f29ffdb6SMintz, Yuval 		struct qed_rss_params *t_rss;
2409f29ffdb6SMintz, Yuval 
2410f29ffdb6SMintz, Yuval 		if (cid->p_owner == QED_LEADING_HWFN(cdev))
2411f29ffdb6SMintz, Yuval 			t_rss = &rss[0];
2412f29ffdb6SMintz, Yuval 		else
2413f29ffdb6SMintz, Yuval 			t_rss = &rss[1];
2414f29ffdb6SMintz, Yuval 
2415f29ffdb6SMintz, Yuval 		t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
2416f29ffdb6SMintz, Yuval 	}
2417f29ffdb6SMintz, Yuval 
2418f29ffdb6SMintz, Yuval 	/* Make sure RSS is actually required */
2419f29ffdb6SMintz, Yuval 	for_each_hwfn(cdev, fn) {
2420f29ffdb6SMintz, Yuval 		for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
2421f29ffdb6SMintz, Yuval 			if (rss[fn].rss_ind_table[i] !=
2422f29ffdb6SMintz, Yuval 			    rss[fn].rss_ind_table[0])
2423f29ffdb6SMintz, Yuval 				break;
2424f29ffdb6SMintz, Yuval 		}
2425f29ffdb6SMintz, Yuval 		if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
2426f29ffdb6SMintz, Yuval 			DP_VERBOSE(cdev, NETIF_MSG_IFUP,
2427f29ffdb6SMintz, Yuval 				   "CMT - 1 queue per-hwfn; Disabling RSS\n");
2428f29ffdb6SMintz, Yuval 			return -EINVAL;
2429f29ffdb6SMintz, Yuval 		}
2430f29ffdb6SMintz, Yuval 		rss[fn].rss_table_size_log = 6;
2431f29ffdb6SMintz, Yuval 	}
2432f29ffdb6SMintz, Yuval 
2433f29ffdb6SMintz, Yuval 	return 0;
2434f29ffdb6SMintz, Yuval }
2435f29ffdb6SMintz, Yuval 
qed_update_vport(struct qed_dev * cdev,struct qed_update_vport_params * params)2436cee4d264SManish Chopra static int qed_update_vport(struct qed_dev *cdev,
2437cee4d264SManish Chopra 			    struct qed_update_vport_params *params)
2438cee4d264SManish Chopra {
2439cee4d264SManish Chopra 	struct qed_sp_vport_update_params sp_params;
2440f29ffdb6SMintz, Yuval 	struct qed_rss_params *rss;
2441f29ffdb6SMintz, Yuval 	int rc = 0, i;
2442cee4d264SManish Chopra 
2443cee4d264SManish Chopra 	if (!cdev)
2444cee4d264SManish Chopra 		return -ENODEV;
2445cee4d264SManish Chopra 
2446fad953ceSKees Cook 	rss = vzalloc(array_size(sizeof(*rss), cdev->num_hwfns));
2447f29ffdb6SMintz, Yuval 	if (!rss)
2448f29ffdb6SMintz, Yuval 		return -ENOMEM;
2449f29ffdb6SMintz, Yuval 
2450cee4d264SManish Chopra 	memset(&sp_params, 0, sizeof(sp_params));
2451cee4d264SManish Chopra 
2452cee4d264SManish Chopra 	/* Translate protocol params into sp params */
2453cee4d264SManish Chopra 	sp_params.vport_id = params->vport_id;
24541a635e48SYuval Mintz 	sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
24551a635e48SYuval Mintz 	sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
2456cee4d264SManish Chopra 	sp_params.vport_active_rx_flg = params->vport_active_flg;
2457cee4d264SManish Chopra 	sp_params.vport_active_tx_flg = params->vport_active_flg;
2458831bfb0eSYuval Mintz 	sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2459831bfb0eSYuval Mintz 	sp_params.tx_switching_flg = params->tx_switching_flg;
24603f9b4a69SYuval Mintz 	sp_params.accept_any_vlan = params->accept_any_vlan;
24613f9b4a69SYuval Mintz 	sp_params.update_accept_any_vlan_flg =
24623f9b4a69SYuval Mintz 		params->update_accept_any_vlan_flg;
2463cee4d264SManish Chopra 
2464f29ffdb6SMintz, Yuval 	/* Prepare the RSS configuration */
2465f29ffdb6SMintz, Yuval 	if (params->update_rss_flg)
2466f29ffdb6SMintz, Yuval 		if (qed_update_vport_rss(cdev, &params->rss_params, rss))
2467cee4d264SManish Chopra 			params->update_rss_flg = 0;
2468cee4d264SManish Chopra 
2469cee4d264SManish Chopra 	for_each_hwfn(cdev, i) {
2470cee4d264SManish Chopra 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2471cee4d264SManish Chopra 
2472f29ffdb6SMintz, Yuval 		if (params->update_rss_flg)
2473f29ffdb6SMintz, Yuval 			sp_params.rss_params = &rss[i];
2474f29ffdb6SMintz, Yuval 
2475cee4d264SManish Chopra 		sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2476cee4d264SManish Chopra 		rc = qed_sp_vport_update(p_hwfn, &sp_params,
2477cee4d264SManish Chopra 					 QED_SPQ_MODE_EBLOCK,
2478cee4d264SManish Chopra 					 NULL);
2479cee4d264SManish Chopra 		if (rc) {
2480cee4d264SManish Chopra 			DP_ERR(cdev, "Failed to update VPORT\n");
2481f29ffdb6SMintz, Yuval 			goto out;
2482cee4d264SManish Chopra 		}
2483cee4d264SManish Chopra 
2484cee4d264SManish Chopra 		DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2485cee4d264SManish Chopra 			   "Updated V-PORT %d: active_flag %d [update %d]\n",
2486cee4d264SManish Chopra 			   params->vport_id, params->vport_active_flg,
2487cee4d264SManish Chopra 			   params->update_vport_active_flg);
2488cee4d264SManish Chopra 	}
2489cee4d264SManish Chopra 
2490f29ffdb6SMintz, Yuval out:
2491f29ffdb6SMintz, Yuval 	vfree(rss);
2492f29ffdb6SMintz, Yuval 	return rc;
2493cee4d264SManish Chopra }
2494cee4d264SManish Chopra 
qed_start_rxq(struct qed_dev * cdev,u8 rss_num,struct qed_queue_start_common_params * p_params,u16 bd_max_bytes,dma_addr_t bd_chain_phys_addr,dma_addr_t cqe_pbl_addr,u16 cqe_pbl_size,struct qed_rxq_start_ret_params * ret_params)2495cee4d264SManish Chopra static int qed_start_rxq(struct qed_dev *cdev,
24963da7a37aSMintz, Yuval 			 u8 rss_num,
24973da7a37aSMintz, Yuval 			 struct qed_queue_start_common_params *p_params,
2498cee4d264SManish Chopra 			 u16 bd_max_bytes,
2499cee4d264SManish Chopra 			 dma_addr_t bd_chain_phys_addr,
2500cee4d264SManish Chopra 			 dma_addr_t cqe_pbl_addr,
2501cee4d264SManish Chopra 			 u16 cqe_pbl_size,
25023da7a37aSMintz, Yuval 			 struct qed_rxq_start_ret_params *ret_params)
2503cee4d264SManish Chopra {
2504cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
25051a635e48SYuval Mintz 	int rc, hwfn_index;
2506cee4d264SManish Chopra 
25073da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2508cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2509cee4d264SManish Chopra 
25103da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
25113da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2512cee4d264SManish Chopra 
25133da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_start(p_hwfn,
2514cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
25153da7a37aSMintz, Yuval 				    p_params,
2516cee4d264SManish Chopra 				    bd_max_bytes,
2517cee4d264SManish Chopra 				    bd_chain_phys_addr,
25183da7a37aSMintz, Yuval 				    cqe_pbl_addr, cqe_pbl_size, ret_params);
2519cee4d264SManish Chopra 	if (rc) {
25203da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
2521cee4d264SManish Chopra 		return rc;
2522cee4d264SManish Chopra 	}
2523cee4d264SManish Chopra 
2524cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2525f604b17dSMintz, Yuval 		   "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
25263da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
2527f604b17dSMintz, Yuval 		   p_params->p_sb->igu_sb_id);
2528cee4d264SManish Chopra 
2529cee4d264SManish Chopra 	return 0;
2530cee4d264SManish Chopra }
2531cee4d264SManish Chopra 
qed_stop_rxq(struct qed_dev * cdev,u8 rss_id,void * handle)25323da7a37aSMintz, Yuval static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
2533cee4d264SManish Chopra {
2534cee4d264SManish Chopra 	int rc, hwfn_index;
2535cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2536cee4d264SManish Chopra 
25373da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2538cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2539cee4d264SManish Chopra 
25403da7a37aSMintz, Yuval 	rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
2541cee4d264SManish Chopra 	if (rc) {
25423da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
2543cee4d264SManish Chopra 		return rc;
2544cee4d264SManish Chopra 	}
2545cee4d264SManish Chopra 
2546cee4d264SManish Chopra 	return 0;
2547cee4d264SManish Chopra }
2548cee4d264SManish Chopra 
qed_start_txq(struct qed_dev * cdev,u8 rss_num,struct qed_queue_start_common_params * p_params,dma_addr_t pbl_addr,u16 pbl_size,struct qed_txq_start_ret_params * ret_params)2549cee4d264SManish Chopra static int qed_start_txq(struct qed_dev *cdev,
25503da7a37aSMintz, Yuval 			 u8 rss_num,
2551cee4d264SManish Chopra 			 struct qed_queue_start_common_params *p_params,
2552cee4d264SManish Chopra 			 dma_addr_t pbl_addr,
2553cee4d264SManish Chopra 			 u16 pbl_size,
25543da7a37aSMintz, Yuval 			 struct qed_txq_start_ret_params *ret_params)
2555cee4d264SManish Chopra {
2556cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2557cee4d264SManish Chopra 	int rc, hwfn_index;
2558cee4d264SManish Chopra 
25593da7a37aSMintz, Yuval 	hwfn_index = rss_num % cdev->num_hwfns;
2560cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
25613da7a37aSMintz, Yuval 	p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
25623da7a37aSMintz, Yuval 	p_params->stats_id = p_params->vport_id;
2563cee4d264SManish Chopra 
25643da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_start(p_hwfn,
2565cee4d264SManish Chopra 				    p_hwfn->hw_info.opaque_fid,
25665e7baf0fSManish Chopra 				    p_params, p_params->tc,
25673da7a37aSMintz, Yuval 				    pbl_addr, pbl_size, ret_params);
2568cee4d264SManish Chopra 
2569cee4d264SManish Chopra 	if (rc) {
2570cee4d264SManish Chopra 		DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2571cee4d264SManish Chopra 		return rc;
2572cee4d264SManish Chopra 	}
2573cee4d264SManish Chopra 
2574cee4d264SManish Chopra 	DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2575f604b17dSMintz, Yuval 		   "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
25763da7a37aSMintz, Yuval 		   p_params->queue_id, rss_num, p_params->vport_id,
2577f604b17dSMintz, Yuval 		   p_params->p_sb->igu_sb_id);
2578cee4d264SManish Chopra 
2579cee4d264SManish Chopra 	return 0;
2580cee4d264SManish Chopra }
2581cee4d264SManish Chopra 
2582cee4d264SManish Chopra #define QED_HW_STOP_RETRY_LIMIT (10)
qed_fastpath_stop(struct qed_dev * cdev)2583cee4d264SManish Chopra static int qed_fastpath_stop(struct qed_dev *cdev)
2584cee4d264SManish Chopra {
258515582962SRahul Verma 	int rc;
258615582962SRahul Verma 
258715582962SRahul Verma 	rc = qed_hw_stop_fastpath(cdev);
258815582962SRahul Verma 	if (rc) {
258915582962SRahul Verma 		DP_ERR(cdev, "Failed to stop Fastpath\n");
259015582962SRahul Verma 		return rc;
259115582962SRahul Verma 	}
2592cee4d264SManish Chopra 
2593cee4d264SManish Chopra 	return 0;
2594cee4d264SManish Chopra }
2595cee4d264SManish Chopra 
qed_stop_txq(struct qed_dev * cdev,u8 rss_id,void * handle)25963da7a37aSMintz, Yuval static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
2597cee4d264SManish Chopra {
2598cee4d264SManish Chopra 	struct qed_hwfn *p_hwfn;
2599cee4d264SManish Chopra 	int rc, hwfn_index;
2600cee4d264SManish Chopra 
26013da7a37aSMintz, Yuval 	hwfn_index = rss_id % cdev->num_hwfns;
2602cee4d264SManish Chopra 	p_hwfn = &cdev->hwfns[hwfn_index];
2603cee4d264SManish Chopra 
26043da7a37aSMintz, Yuval 	rc = qed_eth_tx_queue_stop(p_hwfn, handle);
2605cee4d264SManish Chopra 	if (rc) {
26063da7a37aSMintz, Yuval 		DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
2607cee4d264SManish Chopra 		return rc;
2608cee4d264SManish Chopra 	}
2609cee4d264SManish Chopra 
2610cee4d264SManish Chopra 	return 0;
2611cee4d264SManish Chopra }
2612cee4d264SManish Chopra 
qed_tunn_configure(struct qed_dev * cdev,struct qed_tunn_params * tunn_params)2613464f6645SManish Chopra static int qed_tunn_configure(struct qed_dev *cdev,
2614464f6645SManish Chopra 			      struct qed_tunn_params *tunn_params)
2615464f6645SManish Chopra {
261619968430SChopra, Manish 	struct qed_tunnel_info tunn_info;
2617464f6645SManish Chopra 	int i, rc;
2618464f6645SManish Chopra 
2619464f6645SManish Chopra 	memset(&tunn_info, 0, sizeof(tunn_info));
262019968430SChopra, Manish 	if (tunn_params->update_vxlan_port) {
262119968430SChopra, Manish 		tunn_info.vxlan_port.b_update_port = true;
262219968430SChopra, Manish 		tunn_info.vxlan_port.port = tunn_params->vxlan_port;
2623464f6645SManish Chopra 	}
2624464f6645SManish Chopra 
262519968430SChopra, Manish 	if (tunn_params->update_geneve_port) {
262619968430SChopra, Manish 		tunn_info.geneve_port.b_update_port = true;
262719968430SChopra, Manish 		tunn_info.geneve_port.port = tunn_params->geneve_port;
2628464f6645SManish Chopra 	}
2629464f6645SManish Chopra 
2630464f6645SManish Chopra 	for_each_hwfn(cdev, i) {
2631464f6645SManish Chopra 		struct qed_hwfn *hwfn = &cdev->hwfns[i];
26324f64675fSManish Chopra 		struct qed_ptt *p_ptt;
263397379f15SChopra, Manish 		struct qed_tunnel_info *tun;
263497379f15SChopra, Manish 
263597379f15SChopra, Manish 		tun = &hwfn->cdev->tunnel;
26364f64675fSManish Chopra 		if (IS_PF(cdev)) {
26374f64675fSManish Chopra 			p_ptt = qed_ptt_acquire(hwfn);
26384f64675fSManish Chopra 			if (!p_ptt)
26394f64675fSManish Chopra 				return -EAGAIN;
26404f64675fSManish Chopra 		} else {
26414f64675fSManish Chopra 			p_ptt = NULL;
26424f64675fSManish Chopra 		}
2643464f6645SManish Chopra 
26444f64675fSManish Chopra 		rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
2645464f6645SManish Chopra 					       QED_SPQ_MODE_EBLOCK, NULL);
26464f64675fSManish Chopra 		if (rc) {
26474f64675fSManish Chopra 			if (IS_PF(cdev))
26484f64675fSManish Chopra 				qed_ptt_release(hwfn, p_ptt);
2649464f6645SManish Chopra 			return rc;
26504f64675fSManish Chopra 		}
265197379f15SChopra, Manish 
265297379f15SChopra, Manish 		if (IS_PF_SRIOV(hwfn)) {
265397379f15SChopra, Manish 			u16 vxlan_port, geneve_port;
265497379f15SChopra, Manish 			int j;
265597379f15SChopra, Manish 
265697379f15SChopra, Manish 			vxlan_port = tun->vxlan_port.port;
265797379f15SChopra, Manish 			geneve_port = tun->geneve_port.port;
265897379f15SChopra, Manish 
265997379f15SChopra, Manish 			qed_for_each_vf(hwfn, j) {
266097379f15SChopra, Manish 				qed_iov_bulletin_set_udp_ports(hwfn, j,
266197379f15SChopra, Manish 							       vxlan_port,
266297379f15SChopra, Manish 							       geneve_port);
266397379f15SChopra, Manish 			}
266497379f15SChopra, Manish 
266597379f15SChopra, Manish 			qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
266697379f15SChopra, Manish 		}
26674f64675fSManish Chopra 		if (IS_PF(cdev))
26684f64675fSManish Chopra 			qed_ptt_release(hwfn, p_ptt);
2669464f6645SManish Chopra 	}
2670464f6645SManish Chopra 
2671464f6645SManish Chopra 	return 0;
2672464f6645SManish Chopra }
2673464f6645SManish Chopra 
qed_configure_filter_rx_mode(struct qed_dev * cdev,enum qed_filter_rx_mode_type type)2674cee4d264SManish Chopra static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2675cee4d264SManish Chopra 					enum qed_filter_rx_mode_type type)
2676cee4d264SManish Chopra {
2677cee4d264SManish Chopra 	struct qed_filter_accept_flags accept_flags;
2678cee4d264SManish Chopra 
2679cee4d264SManish Chopra 	memset(&accept_flags, 0, sizeof(accept_flags));
2680cee4d264SManish Chopra 
2681cee4d264SManish Chopra 	accept_flags.update_rx_mode_config = 1;
2682cee4d264SManish Chopra 	accept_flags.update_tx_mode_config = 1;
2683cee4d264SManish Chopra 	accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2684cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2685cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2686cee4d264SManish Chopra 	accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2687cee4d264SManish Chopra 					QED_ACCEPT_MCAST_MATCHED |
2688cee4d264SManish Chopra 					QED_ACCEPT_BCAST;
2689cee4d264SManish Chopra 
269088067876SMintz, Yuval 	if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
2691cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2692cee4d264SManish Chopra 						 QED_ACCEPT_MCAST_UNMATCHED;
26939e71a15dSManish Chopra 		accept_flags.tx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
26949e71a15dSManish Chopra 						 QED_ACCEPT_MCAST_UNMATCHED;
269588067876SMintz, Yuval 	} else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
2696cee4d264SManish Chopra 		accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
269788067876SMintz, Yuval 		accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
269888067876SMintz, Yuval 	}
2699cee4d264SManish Chopra 
27003f9b4a69SYuval Mintz 	return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
2701cee4d264SManish Chopra 				     QED_SPQ_MODE_CB, NULL);
2702cee4d264SManish Chopra }
2703cee4d264SManish Chopra 
qed_configure_filter_ucast(struct qed_dev * cdev,struct qed_filter_ucast_params * params)2704cee4d264SManish Chopra static int qed_configure_filter_ucast(struct qed_dev *cdev,
2705cee4d264SManish Chopra 				      struct qed_filter_ucast_params *params)
2706cee4d264SManish Chopra {
2707cee4d264SManish Chopra 	struct qed_filter_ucast ucast;
2708cee4d264SManish Chopra 
2709cee4d264SManish Chopra 	if (!params->vlan_valid && !params->mac_valid) {
27101a635e48SYuval Mintz 		DP_NOTICE(cdev,
2711cee4d264SManish Chopra 			  "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
2712cee4d264SManish Chopra 		return -EINVAL;
2713cee4d264SManish Chopra 	}
2714cee4d264SManish Chopra 
2715cee4d264SManish Chopra 	memset(&ucast, 0, sizeof(ucast));
2716cee4d264SManish Chopra 	switch (params->type) {
2717cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2718cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_ADD;
2719cee4d264SManish Chopra 		break;
2720cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2721cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REMOVE;
2722cee4d264SManish Chopra 		break;
2723cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_REPLACE:
2724cee4d264SManish Chopra 		ucast.opcode = QED_FILTER_REPLACE;
2725cee4d264SManish Chopra 		break;
2726cee4d264SManish Chopra 	default:
2727cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2728cee4d264SManish Chopra 			  params->type);
2729cee4d264SManish Chopra 	}
2730cee4d264SManish Chopra 
2731cee4d264SManish Chopra 	if (params->vlan_valid && params->mac_valid) {
2732cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC_VLAN;
2733cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2734cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2735cee4d264SManish Chopra 	} else if (params->mac_valid) {
2736cee4d264SManish Chopra 		ucast.type = QED_FILTER_MAC;
2737cee4d264SManish Chopra 		ether_addr_copy(ucast.mac, params->mac);
2738cee4d264SManish Chopra 	} else {
2739cee4d264SManish Chopra 		ucast.type = QED_FILTER_VLAN;
2740cee4d264SManish Chopra 		ucast.vlan = params->vlan;
2741cee4d264SManish Chopra 	}
2742cee4d264SManish Chopra 
2743cee4d264SManish Chopra 	ucast.is_rx_filter = true;
2744cee4d264SManish Chopra 	ucast.is_tx_filter = true;
2745cee4d264SManish Chopra 
2746cee4d264SManish Chopra 	return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2747cee4d264SManish Chopra }
2748cee4d264SManish Chopra 
qed_configure_filter_mcast(struct qed_dev * cdev,struct qed_filter_mcast_params * params)2749cee4d264SManish Chopra static int qed_configure_filter_mcast(struct qed_dev *cdev,
2750cee4d264SManish Chopra 				      struct qed_filter_mcast_params *params)
2751cee4d264SManish Chopra {
2752cee4d264SManish Chopra 	struct qed_filter_mcast mcast;
2753cee4d264SManish Chopra 	int i;
2754cee4d264SManish Chopra 
2755cee4d264SManish Chopra 	memset(&mcast, 0, sizeof(mcast));
2756cee4d264SManish Chopra 	switch (params->type) {
2757cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_ADD:
2758cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_ADD;
2759cee4d264SManish Chopra 		break;
2760cee4d264SManish Chopra 	case QED_FILTER_XCAST_TYPE_DEL:
2761cee4d264SManish Chopra 		mcast.opcode = QED_FILTER_REMOVE;
2762cee4d264SManish Chopra 		break;
2763cee4d264SManish Chopra 	default:
2764cee4d264SManish Chopra 		DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2765cee4d264SManish Chopra 			  params->type);
2766cee4d264SManish Chopra 	}
2767cee4d264SManish Chopra 
2768cee4d264SManish Chopra 	mcast.num_mc_addrs = params->num;
2769cee4d264SManish Chopra 	for (i = 0; i < mcast.num_mc_addrs; i++)
2770cee4d264SManish Chopra 		ether_addr_copy(mcast.mac[i], params->mac[i]);
2771cee4d264SManish Chopra 
27721a635e48SYuval Mintz 	return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
2773cee4d264SManish Chopra }
2774cee4d264SManish Chopra 
qed_configure_arfs_searcher(struct qed_dev * cdev,enum qed_filter_config_mode mode)2775da090917STomer Tayar static int qed_configure_arfs_searcher(struct qed_dev *cdev,
2776da090917STomer Tayar 				       enum qed_filter_config_mode mode)
2777d51e4af5SChopra, Manish {
2778d51e4af5SChopra, Manish 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2779d51e4af5SChopra, Manish 	struct qed_arfs_config_params arfs_config_params;
2780d51e4af5SChopra, Manish 
2781d51e4af5SChopra, Manish 	memset(&arfs_config_params, 0, sizeof(arfs_config_params));
2782d51e4af5SChopra, Manish 	arfs_config_params.tcp = true;
2783d51e4af5SChopra, Manish 	arfs_config_params.udp = true;
2784d51e4af5SChopra, Manish 	arfs_config_params.ipv4 = true;
2785d51e4af5SChopra, Manish 	arfs_config_params.ipv6 = true;
2786da090917STomer Tayar 	arfs_config_params.mode = mode;
2787d51e4af5SChopra, Manish 	qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
2788d51e4af5SChopra, Manish 				&arfs_config_params);
2789d51e4af5SChopra, Manish 	return 0;
2790d51e4af5SChopra, Manish }
2791d51e4af5SChopra, Manish 
2792d51e4af5SChopra, Manish static void
qed_arfs_sp_response_handler(struct qed_hwfn * p_hwfn,void * cookie,union event_ring_data * data,u8 fw_return_code)2793d51e4af5SChopra, Manish qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
2794da090917STomer Tayar 			     void *cookie,
2795da090917STomer Tayar 			     union event_ring_data *data, u8 fw_return_code)
2796d51e4af5SChopra, Manish {
2797d51e4af5SChopra, Manish 	struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
2798d51e4af5SChopra, Manish 	void *dev = p_hwfn->cdev->ops_cookie;
2799d51e4af5SChopra, Manish 
2800d51e4af5SChopra, Manish 	op->arfs_filter_op(dev, cookie, fw_return_code);
2801d51e4af5SChopra, Manish }
2802d51e4af5SChopra, Manish 
2803da090917STomer Tayar static int
qed_ntuple_arfs_filter_config(struct qed_dev * cdev,void * cookie,struct qed_ntuple_filter_params * params)2804da090917STomer Tayar qed_ntuple_arfs_filter_config(struct qed_dev *cdev,
2805da090917STomer Tayar 			      void *cookie,
2806da090917STomer Tayar 			      struct qed_ntuple_filter_params *params)
2807d51e4af5SChopra, Manish {
2808d51e4af5SChopra, Manish 	struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2809d51e4af5SChopra, Manish 	struct qed_spq_comp_cb cb;
2810d51e4af5SChopra, Manish 	int rc = -EINVAL;
2811d51e4af5SChopra, Manish 
2812d51e4af5SChopra, Manish 	cb.function = qed_arfs_sp_response_handler;
2813d51e4af5SChopra, Manish 	cb.cookie = cookie;
2814d51e4af5SChopra, Manish 
2815da090917STomer Tayar 	if (params->b_is_vf) {
2816da090917STomer Tayar 		if (!qed_iov_is_valid_vfid(p_hwfn, params->vf_id, false,
2817da090917STomer Tayar 					   false)) {
2818da090917STomer Tayar 			DP_INFO(p_hwfn, "vfid 0x%02x is out of bounds\n",
2819da090917STomer Tayar 				params->vf_id);
2820da090917STomer Tayar 			return rc;
2821da090917STomer Tayar 		}
2822da090917STomer Tayar 
2823da090917STomer Tayar 		params->vport_id = params->vf_id + 1;
2824da090917STomer Tayar 		params->qid = QED_RFS_NTUPLE_QID_RSS;
2825da090917STomer Tayar 	}
2826da090917STomer Tayar 
2827da090917STomer Tayar 	rc = qed_configure_rfs_ntuple_filter(p_hwfn, &cb, params);
2828d51e4af5SChopra, Manish 	if (rc)
2829d51e4af5SChopra, Manish 		DP_NOTICE(p_hwfn,
2830d51e4af5SChopra, Manish 			  "Failed to issue a-RFS filter configuration\n");
2831d51e4af5SChopra, Manish 	else
2832d51e4af5SChopra, Manish 		DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
2833d51e4af5SChopra, Manish 			   "Successfully issued a-RFS filter configuration\n");
2834d51e4af5SChopra, Manish 
2835d51e4af5SChopra, Manish 	return rc;
2836d51e4af5SChopra, Manish }
2837d51e4af5SChopra, Manish 
qed_get_coalesce(struct qed_dev * cdev,u16 * coal,void * handle)2838bf5a94bfSRahul Verma static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle)
2839bf5a94bfSRahul Verma {
2840bf5a94bfSRahul Verma 	struct qed_queue_cid *p_cid = handle;
2841bf5a94bfSRahul Verma 	struct qed_hwfn *p_hwfn;
2842bf5a94bfSRahul Verma 	int rc;
2843bf5a94bfSRahul Verma 
2844bf5a94bfSRahul Verma 	p_hwfn = p_cid->p_owner;
2845bf5a94bfSRahul Verma 	rc = qed_get_queue_coalesce(p_hwfn, coal, handle);
2846bf5a94bfSRahul Verma 	if (rc)
28478c850253SRahul Verma 		DP_VERBOSE(cdev, QED_MSG_DEBUG,
28488c850253SRahul Verma 			   "Unable to read queue coalescing\n");
2849bf5a94bfSRahul Verma 
2850bf5a94bfSRahul Verma 	return rc;
2851bf5a94bfSRahul Verma }
2852bf5a94bfSRahul Verma 
qed_fp_cqe_completion(struct qed_dev * dev,u8 rss_id,struct eth_slow_path_rx_cqe * cqe)2853cee4d264SManish Chopra static int qed_fp_cqe_completion(struct qed_dev *dev,
28541a635e48SYuval Mintz 				 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
2855cee4d264SManish Chopra {
2856cee4d264SManish Chopra 	return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2857cee4d264SManish Chopra 				      cqe);
2858cee4d264SManish Chopra }
2859cee4d264SManish Chopra 
qed_req_bulletin_update_mac(struct qed_dev * cdev,const u8 * mac)286076660757SJakub Kicinski static int qed_req_bulletin_update_mac(struct qed_dev *cdev, const u8 *mac)
2861809c45a0SShahed Shaikh {
2862809c45a0SShahed Shaikh 	int i, ret;
2863809c45a0SShahed Shaikh 
2864809c45a0SShahed Shaikh 	if (IS_PF(cdev))
2865809c45a0SShahed Shaikh 		return 0;
2866809c45a0SShahed Shaikh 
2867809c45a0SShahed Shaikh 	for_each_hwfn(cdev, i) {
2868809c45a0SShahed Shaikh 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2869809c45a0SShahed Shaikh 
2870809c45a0SShahed Shaikh 		ret = qed_vf_pf_bulletin_update_mac(p_hwfn, mac);
2871809c45a0SShahed Shaikh 		if (ret)
2872809c45a0SShahed Shaikh 			return ret;
2873809c45a0SShahed Shaikh 	}
2874809c45a0SShahed Shaikh 
2875809c45a0SShahed Shaikh 	return 0;
2876809c45a0SShahed Shaikh }
2877809c45a0SShahed Shaikh 
287825c089d7SYuval Mintz static const struct qed_eth_ops qed_eth_ops_pass = {
287925c089d7SYuval Mintz 	.common = &qed_common_ops_pass,
28800b55e27dSYuval Mintz #ifdef CONFIG_QED_SRIOV
28810b55e27dSYuval Mintz 	.iov = &qed_iov_ops_pass,
28820b55e27dSYuval Mintz #endif
2883a1d8d8a5SSudarsana Reddy Kalluru #ifdef CONFIG_DCB
2884a1d8d8a5SSudarsana Reddy Kalluru 	.dcb = &qed_dcbnl_ops_pass,
2885a1d8d8a5SSudarsana Reddy Kalluru #endif
2886c78c70faSSudarsana Reddy Kalluru 	.ptp = &qed_ptp_ops_pass,
288725c089d7SYuval Mintz 	.fill_dev_info = &qed_fill_eth_dev_info,
2888cc875c2eSYuval Mintz 	.register_ops = &qed_register_eth_ops,
2889eff16960SYuval Mintz 	.check_mac = &qed_check_mac,
2890cee4d264SManish Chopra 	.vport_start = &qed_start_vport,
2891cee4d264SManish Chopra 	.vport_stop = &qed_stop_vport,
2892cee4d264SManish Chopra 	.vport_update = &qed_update_vport,
2893cee4d264SManish Chopra 	.q_rx_start = &qed_start_rxq,
2894cee4d264SManish Chopra 	.q_rx_stop = &qed_stop_rxq,
2895cee4d264SManish Chopra 	.q_tx_start = &qed_start_txq,
2896cee4d264SManish Chopra 	.q_tx_stop = &qed_stop_txq,
2897f55e36d5SShai Malin 	.filter_config_rx_mode = &qed_configure_filter_rx_mode,
2898f55e36d5SShai Malin 	.filter_config_ucast = &qed_configure_filter_ucast,
2899f55e36d5SShai Malin 	.filter_config_mcast = &qed_configure_filter_mcast,
2900cee4d264SManish Chopra 	.fastpath_stop = &qed_fastpath_stop,
2901cee4d264SManish Chopra 	.eth_cqe_completion = &qed_fp_cqe_completion,
29029df2ed04SManish Chopra 	.get_vport_stats = &qed_get_vport_stats,
2903464f6645SManish Chopra 	.tunn_config = &qed_tunn_configure,
2904d51e4af5SChopra, Manish 	.ntuple_filter_config = &qed_ntuple_arfs_filter_config,
2905d51e4af5SChopra, Manish 	.configure_arfs_searcher = &qed_configure_arfs_searcher,
2906bf5a94bfSRahul Verma 	.get_coalesce = &qed_get_coalesce,
2907809c45a0SShahed Shaikh 	.req_bulletin_update_mac = &qed_req_bulletin_update_mac,
290825c089d7SYuval Mintz };
290925c089d7SYuval Mintz 
qed_get_eth_ops(void)291095114344SRahul Verma const struct qed_eth_ops *qed_get_eth_ops(void)
291125c089d7SYuval Mintz {
291225c089d7SYuval Mintz 	return &qed_eth_ops_pass;
291325c089d7SYuval Mintz }
291425c089d7SYuval Mintz EXPORT_SYMBOL(qed_get_eth_ops);
291525c089d7SYuval Mintz 
qed_put_eth_ops(void)291625c089d7SYuval Mintz void qed_put_eth_ops(void)
291725c089d7SYuval Mintz {
291825c089d7SYuval Mintz 	/* TODO - reference count for module? */
291925c089d7SYuval Mintz }
292025c089d7SYuval Mintz EXPORT_SYMBOL(qed_put_eth_ops);
2921