1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef _QED_INT_H 10 #define _QED_INT_H 11 12 #include <linux/types.h> 13 #include <linux/slab.h> 14 #include "qed.h" 15 16 /* Fields of IGU PF CONFIGRATION REGISTER */ 17 #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 18 #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 19 #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 20 #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 21 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 22 #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 23 24 /* Igu control commands 25 */ 26 enum igu_ctrl_cmd { 27 IGU_CTRL_CMD_TYPE_RD, 28 IGU_CTRL_CMD_TYPE_WR, 29 MAX_IGU_CTRL_CMD 30 }; 31 32 /* Control register for the IGU command register 33 */ 34 struct igu_ctrl_reg { 35 u32 ctrl_data; 36 #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 37 #define IGU_CTRL_REG_FID_SHIFT 0 38 #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 39 #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 40 #define IGU_CTRL_REG_RESERVED_MASK 0x1 41 #define IGU_CTRL_REG_RESERVED_SHIFT 28 42 #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 43 #define IGU_CTRL_REG_TYPE_SHIFT 31 44 }; 45 46 enum qed_coalescing_fsm { 47 QED_COAL_RX_STATE_MACHINE, 48 QED_COAL_TX_STATE_MACHINE 49 }; 50 51 /** 52 * @brief qed_int_cau_conf_pi - configure cau for a given 53 * status block 54 * 55 * @param p_hwfn 56 * @param p_ptt 57 * @param igu_sb_id 58 * @param pi_index 59 * @param state 60 * @param timeset 61 */ 62 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 63 struct qed_ptt *p_ptt, 64 u16 igu_sb_id, 65 u32 pi_index, 66 enum qed_coalescing_fsm coalescing_fsm, 67 u8 timeset); 68 69 /** 70 * @brief qed_int_igu_enable_int - enable device interrupts 71 * 72 * @param p_hwfn 73 * @param p_ptt 74 * @param int_mode - interrupt mode to use 75 */ 76 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 77 struct qed_ptt *p_ptt, 78 enum qed_int_mode int_mode); 79 80 /** 81 * @brief qed_int_igu_disable_int - disable device interrupts 82 * 83 * @param p_hwfn 84 * @param p_ptt 85 */ 86 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 87 struct qed_ptt *p_ptt); 88 89 /** 90 * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 91 * register from igu. 92 * 93 * @param p_hwfn 94 * 95 * @return u64 96 */ 97 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 98 99 #define QED_SP_SB_ID 0xffff 100 /** 101 * @brief qed_int_sb_init - Initializes the sb_info structure. 102 * 103 * once the structure is initialized it can be passed to sb related functions. 104 * 105 * @param p_hwfn 106 * @param p_ptt 107 * @param sb_info points to an uninitialized (but 108 * allocated) sb_info structure 109 * @param sb_virt_addr 110 * @param sb_phy_addr 111 * @param sb_id the sb_id to be used (zero based in driver) 112 * should use QED_SP_SB_ID for SP Status block 113 * 114 * @return int 115 */ 116 int qed_int_sb_init(struct qed_hwfn *p_hwfn, 117 struct qed_ptt *p_ptt, 118 struct qed_sb_info *sb_info, 119 void *sb_virt_addr, 120 dma_addr_t sb_phy_addr, 121 u16 sb_id); 122 /** 123 * @brief qed_int_sb_setup - Setup the sb. 124 * 125 * @param p_hwfn 126 * @param p_ptt 127 * @param sb_info initialized sb_info structure 128 */ 129 void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 130 struct qed_ptt *p_ptt, 131 struct qed_sb_info *sb_info); 132 133 /** 134 * @brief qed_int_sb_release - releases the sb_info structure. 135 * 136 * once the structure is released, it's memory can be freed 137 * 138 * @param p_hwfn 139 * @param sb_info points to an allocated sb_info structure 140 * @param sb_id the sb_id to be used (zero based in driver) 141 * should never be equal to QED_SP_SB_ID 142 * (SP Status block) 143 * 144 * @return int 145 */ 146 int qed_int_sb_release(struct qed_hwfn *p_hwfn, 147 struct qed_sb_info *sb_info, 148 u16 sb_id); 149 150 /** 151 * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 152 * default status block. 153 * 154 * @param p_hwfn - pointer to hwfn 155 * 156 */ 157 void qed_int_sp_dpc(unsigned long hwfn_cookie); 158 159 /** 160 * @brief qed_int_get_num_sbs - get the number of status 161 * blocks configured for this funciton in the igu. 162 * 163 * @param p_hwfn 164 * @param p_iov_blks - configured free blks for vfs 165 * 166 * @return int - number of status blocks configured 167 */ 168 int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 169 int *p_iov_blks); 170 171 /** 172 * @file 173 * 174 * @brief Interrupt handler 175 */ 176 177 #define QED_CAU_DEF_RX_TIMER_RES 0 178 #define QED_CAU_DEF_TX_TIMER_RES 0 179 180 #define QED_SB_ATT_IDX 0x0001 181 #define QED_SB_EVENT_MASK 0x0003 182 183 #define SB_ALIGNED_SIZE(p_hwfn) \ 184 ALIGNED_TYPE_SIZE(struct status_block, p_hwfn) 185 186 struct qed_igu_block { 187 u8 status; 188 #define QED_IGU_STATUS_FREE 0x01 189 #define QED_IGU_STATUS_VALID 0x02 190 #define QED_IGU_STATUS_PF 0x04 191 192 u8 vector_number; 193 u8 function_id; 194 u8 is_pf; 195 }; 196 197 struct qed_igu_map { 198 struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH]; 199 }; 200 201 struct qed_igu_info { 202 struct qed_igu_map igu_map; 203 u16 igu_dsb_id; 204 u16 igu_base_sb; 205 u16 igu_base_sb_iov; 206 u16 igu_sb_cnt; 207 u16 igu_sb_cnt_iov; 208 u16 free_blks; 209 }; 210 211 /* TODO Names of function may change... */ 212 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 213 struct qed_ptt *p_ptt, 214 bool b_set, 215 bool b_slowpath); 216 217 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 218 219 /** 220 * @brief qed_int_igu_read_cam - Reads the IGU CAM. 221 * This function needs to be called during hardware 222 * prepare. It reads the info from igu cam to know which 223 * status block is the default / base status block etc. 224 * 225 * @param p_hwfn 226 * @param p_ptt 227 * 228 * @return int 229 */ 230 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 231 struct qed_ptt *p_ptt); 232 233 typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 234 void *cookie); 235 /** 236 * @brief qed_int_register_cb - Register callback func for 237 * slowhwfn statusblock. 238 * 239 * Every protocol that uses the slowhwfn status block 240 * should register a callback function that will be called 241 * once there is an update of the sp status block. 242 * 243 * @param p_hwfn 244 * @param comp_cb - function to be called when there is an 245 * interrupt on the sp sb 246 * 247 * @param cookie - passed to the callback function 248 * @param sb_idx - OUT parameter which gives the chosen index 249 * for this protocol. 250 * @param p_fw_cons - pointer to the actual address of the 251 * consumer for this protocol. 252 * 253 * @return int 254 */ 255 int qed_int_register_cb(struct qed_hwfn *p_hwfn, 256 qed_int_comp_cb_t comp_cb, 257 void *cookie, 258 u8 *sb_idx, 259 __le16 **p_fw_cons); 260 261 /** 262 * @brief qed_int_unregister_cb - Unregisters callback 263 * function from sp sb. 264 * Partner of qed_int_register_cb -> should be called 265 * when no longer required. 266 * 267 * @param p_hwfn 268 * @param pi 269 * 270 * @return int 271 */ 272 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 273 u8 pi); 274 275 /** 276 * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 277 * 278 * @param p_hwfn 279 * 280 * @return u16 281 */ 282 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 283 284 /** 285 * @brief Status block cleanup. Should be called for each status 286 * block that will be used -> both PF / VF 287 * 288 * @param p_hwfn 289 * @param p_ptt 290 * @param sb_id - igu status block id 291 * @param cleanup_set - set(1) / clear(0) 292 * @param opaque_fid - the function for which to perform 293 * cleanup, for example a PF on behalf of 294 * its VFs. 295 */ 296 void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 297 struct qed_ptt *p_ptt, 298 u32 sb_id, 299 bool cleanup_set, 300 u16 opaque_fid); 301 302 /** 303 * @brief Status block cleanup. Should be called for each status 304 * block that will be used -> both PF / VF 305 * 306 * @param p_hwfn 307 * @param p_ptt 308 * @param sb_id - igu status block id 309 * @param opaque - opaque fid of the sb owner. 310 * @param cleanup_set - set(1) / clear(0) 311 */ 312 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 313 struct qed_ptt *p_ptt, 314 u32 sb_id, 315 u16 opaque, 316 bool b_set); 317 318 /** 319 * @brief qed_int_cau_conf - configure cau for a given status 320 * block 321 * 322 * @param p_hwfn 323 * @param ptt 324 * @param sb_phys 325 * @param igu_sb_id 326 * @param vf_number 327 * @param vf_valid 328 */ 329 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 330 struct qed_ptt *p_ptt, 331 dma_addr_t sb_phys, 332 u16 igu_sb_id, 333 u16 vf_number, 334 u8 vf_valid); 335 336 /** 337 * @brief qed_int_alloc 338 * 339 * @param p_hwfn 340 * @param p_ptt 341 * 342 * @return int 343 */ 344 int qed_int_alloc(struct qed_hwfn *p_hwfn, 345 struct qed_ptt *p_ptt); 346 347 /** 348 * @brief qed_int_free 349 * 350 * @param p_hwfn 351 */ 352 void qed_int_free(struct qed_hwfn *p_hwfn); 353 354 /** 355 * @brief qed_int_setup 356 * 357 * @param p_hwfn 358 * @param p_ptt 359 */ 360 void qed_int_setup(struct qed_hwfn *p_hwfn, 361 struct qed_ptt *p_ptt); 362 363 /** 364 * @brief - Enable Interrupt & Attention for hw function 365 * 366 * @param p_hwfn 367 * @param p_ptt 368 * @param int_mode 369 */ 370 void qed_int_igu_enable(struct qed_hwfn *p_hwfn, 371 struct qed_ptt *p_ptt, 372 enum qed_int_mode int_mode); 373 374 /** 375 * @brief - Initialize CAU status block entry 376 * 377 * @param p_hwfn 378 * @param p_sb_entry 379 * @param pf_id 380 * @param vf_number 381 * @param vf_valid 382 */ 383 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 384 struct cau_sb_entry *p_sb_entry, 385 u8 pf_id, 386 u16 vf_number, 387 u8 vf_valid); 388 389 #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 390 391 #endif 392