1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3  * Copyright (c) 2015-2017  QLogic Corporation
4  * Copyright (c) 2019-2020 Marvell International Ltd.
5  */
6 
7 #ifndef _QED_INT_H
8 #define _QED_INT_H
9 
10 #include <linux/types.h>
11 #include <linux/slab.h>
12 #include "qed.h"
13 
14 /* Fields of IGU PF CONFIGURATION REGISTER */
15 #define IGU_PF_CONF_FUNC_EN       (0x1 << 0)    /* function enable        */
16 #define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)    /* MSI/MSIX enable        */
17 #define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)    /* INT enable             */
18 #define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)    /* attention enable       */
19 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)    /* single ISR mode enable */
20 #define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)    /* simd all ones mode     */
21 /* Fields of IGU VF CONFIGURATION REGISTER */
22 #define IGU_VF_CONF_FUNC_EN        (0x1 << 0)	/* function enable        */
23 #define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)	/* MSI/MSIX enable        */
24 #define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)	/* single ISR mode enable */
25 #define IGU_VF_CONF_PARENT_MASK    (0xF)	/* Parent PF              */
26 #define IGU_VF_CONF_PARENT_SHIFT   5		/* Parent PF              */
27 
28 /* Igu control commands
29  */
30 enum igu_ctrl_cmd {
31 	IGU_CTRL_CMD_TYPE_RD,
32 	IGU_CTRL_CMD_TYPE_WR,
33 	MAX_IGU_CTRL_CMD
34 };
35 
36 /* Control register for the IGU command register
37  */
38 struct igu_ctrl_reg {
39 	u32 ctrl_data;
40 #define IGU_CTRL_REG_FID_MASK           0xFFFF  /* Opaque_FID	 */
41 #define IGU_CTRL_REG_FID_SHIFT          0
42 #define IGU_CTRL_REG_PXP_ADDR_MASK      0xFFF   /* Command address */
43 #define IGU_CTRL_REG_PXP_ADDR_SHIFT     16
44 #define IGU_CTRL_REG_RESERVED_MASK      0x1
45 #define IGU_CTRL_REG_RESERVED_SHIFT     28
46 #define IGU_CTRL_REG_TYPE_MASK          0x1 /* use enum igu_ctrl_cmd */
47 #define IGU_CTRL_REG_TYPE_SHIFT         31
48 };
49 
50 enum qed_coalescing_fsm {
51 	QED_COAL_RX_STATE_MACHINE,
52 	QED_COAL_TX_STATE_MACHINE
53 };
54 
55 /**
56  * qed_int_igu_enable_int(): Enable device interrupts.
57  *
58  * @p_hwfn: HW device data.
59  * @p_ptt: P_ptt.
60  * @int_mode: Interrupt mode to use.
61  *
62  * Return: Void.
63  */
64 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
65 			    struct qed_ptt *p_ptt,
66 			    enum qed_int_mode int_mode);
67 
68 /**
69  * qed_int_igu_disable_int():  Disable device interrupts.
70  *
71  * @p_hwfn: HW device data.
72  * @p_ptt: P_ptt.
73  *
74  * Return: Void.
75  */
76 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
77 			     struct qed_ptt *p_ptt);
78 
79 /**
80  * qed_int_igu_read_sisr_reg(): Reads the single isr multiple dpc
81  *                             register from igu.
82  *
83  * @p_hwfn: HW device data.
84  *
85  * Return: u64.
86  */
87 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
88 
89 #define QED_SP_SB_ID 0xffff
90 /**
91  * qed_int_sb_init(): Initializes the sb_info structure.
92  *
93  * @p_hwfn: HW device data.
94  * @p_ptt: P_ptt.
95  * @sb_info: points to an uninitialized (but allocated) sb_info structure
96  * @sb_virt_addr: SB Virtual address.
97  * @sb_phy_addr: SB Physial address.
98  * @sb_id: the sb_id to be used (zero based in driver)
99  *           should use QED_SP_SB_ID for SP Status block
100  *
101  * Return: int.
102  *
103  * Once the structure is initialized it can be passed to sb related functions.
104  */
105 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
106 		    struct qed_ptt *p_ptt,
107 		    struct qed_sb_info *sb_info,
108 		    void *sb_virt_addr,
109 		    dma_addr_t sb_phy_addr,
110 		    u16 sb_id);
111 /**
112  * qed_int_sb_setup(): Setup the sb.
113  *
114  * @p_hwfn: HW device data.
115  * @p_ptt: P_ptt.
116  * @sb_info: Initialized sb_info structure.
117  *
118  * Return: Void.
119  */
120 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
121 		      struct qed_ptt *p_ptt,
122 		      struct qed_sb_info *sb_info);
123 
124 /**
125  * qed_int_sb_release(): Releases the sb_info structure.
126  *
127  * @p_hwfn: HW device data.
128  * @sb_info: Points to an allocated sb_info structure.
129  * @sb_id: The sb_id to be used (zero based in driver)
130  *         should never be equal to QED_SP_SB_ID
131  *         (SP Status block).
132  *
133  * Return: int.
134  *
135  * Once the structure is released, it's memory can be freed.
136  */
137 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
138 		       struct qed_sb_info *sb_info,
139 		       u16 sb_id);
140 
141 /**
142  * qed_int_sp_dpc(): To be called when an interrupt is received on the
143  *                   default status block.
144  *
145  * @t: Tasklet.
146  *
147  * Return: Void.
148  *
149  */
150 void qed_int_sp_dpc(struct tasklet_struct *t);
151 
152 /**
153  * qed_int_get_num_sbs(): Get the number of status blocks configured
154  *                        for this funciton in the igu.
155  *
156  * @p_hwfn: HW device data.
157  * @p_sb_cnt_info: Pointer to SB count info.
158  *
159  * Return: Void.
160  */
161 void qed_int_get_num_sbs(struct qed_hwfn	*p_hwfn,
162 			 struct qed_sb_cnt_info *p_sb_cnt_info);
163 
164 /**
165  * qed_int_disable_post_isr_release(): Performs the cleanup post ISR
166  *        release. The API need to be called after releasing all slowpath IRQs
167  *        of the device.
168  *
169  * @cdev: Qed dev pointer.
170  *
171  * Return: Void.
172  */
173 void qed_int_disable_post_isr_release(struct qed_dev *cdev);
174 
175 /**
176  * qed_int_attn_clr_enable: Sets whether the general behavior is
177  *        preventing attentions from being reasserted, or following the
178  *        attributes of the specific attention.
179  *
180  * @cdev: Qed dev pointer.
181  * @clr_enable: Clear enable
182  *
183  * Return: Void.
184  *
185  */
186 void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable);
187 
188 /**
189  * qed_db_rec_handler(): Doorbell Recovery handler.
190  *          Run doorbell recovery in case of PF overflow (and flush DORQ if
191  *          needed).
192  *
193  * @p_hwfn: HW device data.
194  * @p_ptt: P_ptt.
195  *
196  * Return: Int.
197  */
198 int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
199 
200 #define QED_CAU_DEF_RX_TIMER_RES 0
201 #define QED_CAU_DEF_TX_TIMER_RES 0
202 
203 #define QED_SB_ATT_IDX  0x0001
204 #define QED_SB_EVENT_MASK       0x0003
205 
206 #define SB_ALIGNED_SIZE(p_hwfn)	\
207 	ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
208 
209 #define QED_SB_INVALID_IDX      0xffff
210 
211 struct qed_igu_block {
212 	u8 status;
213 #define QED_IGU_STATUS_FREE     0x01
214 #define QED_IGU_STATUS_VALID    0x02
215 #define QED_IGU_STATUS_PF       0x04
216 #define QED_IGU_STATUS_DSB      0x08
217 
218 	u8 vector_number;
219 	u8 function_id;
220 	u8 is_pf;
221 
222 	/* Index inside IGU [meant for back reference] */
223 	u16 igu_sb_id;
224 
225 	struct qed_sb_info *sb_info;
226 };
227 
228 struct qed_igu_info {
229 	struct qed_igu_block entry[MAX_TOT_SB_PER_PATH];
230 	u16 igu_dsb_id;
231 
232 	struct qed_sb_cnt_info usage;
233 
234 	bool b_allow_pf_vf_change;
235 };
236 
237 /**
238  * qed_int_igu_reset_cam(): Make sure the IGU CAM reflects the resources
239  *                          provided by MFW.
240  *
241  * @p_hwfn: HW device data.
242  * @p_ptt: P_ptt.
243  *
244  * Return: Void.
245  */
246 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
247 
248 /**
249  * qed_get_igu_sb_id(): Translate the weakly-defined client sb-id into
250  *                      an IGU sb-id
251  *
252  * @p_hwfn: HW device data.
253  * @sb_id: user provided sb_id.
254  *
255  * Return: An index inside IGU CAM where the SB resides.
256  */
257 u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
258 
259 /**
260  * qed_get_igu_free_sb(): Return a pointer to an unused valid SB
261  *
262  * @p_hwfn: HW device data.
263  * @b_is_pf: True iff we want a SB belonging to a PF.
264  *
265  * Return: Point to an igu_block, NULL if none is available.
266  */
267 struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn,
268 					  bool b_is_pf);
269 
270 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
271 			      struct qed_ptt *p_ptt,
272 			      bool b_set,
273 			      bool b_slowpath);
274 
275 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
276 
277 /**
278  * qed_int_igu_read_cam():  Reads the IGU CAM.
279  *	This function needs to be called during hardware
280  *	prepare. It reads the info from igu cam to know which
281  *	status block is the default / base status block etc.
282  *
283  * @p_hwfn: HW device data.
284  * @p_ptt: P_ptt.
285  *
286  * Return: Int.
287  */
288 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
289 			 struct qed_ptt *p_ptt);
290 
291 typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
292 				 void *cookie);
293 /**
294  * qed_int_register_cb(): Register callback func for slowhwfn statusblock.
295  *
296  * @p_hwfn: HW device data.
297  * @comp_cb: Function to be called when there is an
298  *           interrupt on the sp sb
299  * @cookie: Passed to the callback function
300  * @sb_idx: (OUT) parameter which gives the chosen index
301  *           for this protocol.
302  * @p_fw_cons: Pointer to the actual address of the
303  *             consumer for this protocol.
304  *
305  * Return: Int.
306  *
307  * Every protocol that uses the slowhwfn status block
308  * should register a callback function that will be called
309  * once there is an update of the sp status block.
310  */
311 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
312 			qed_int_comp_cb_t comp_cb,
313 			void *cookie,
314 			u8 *sb_idx,
315 			__le16 **p_fw_cons);
316 
317 /**
318  * qed_int_unregister_cb(): Unregisters callback function from sp sb.
319  *
320  * @p_hwfn: HW device data.
321  * @pi: Producer Index.
322  *
323  * Return: Int.
324  *
325  * Partner of qed_int_register_cb -> should be called
326  * when no longer required.
327  */
328 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
329 			  u8 pi);
330 
331 /**
332  * qed_int_get_sp_sb_id(): Get the slowhwfn sb id.
333  *
334  * @p_hwfn: HW device data.
335  *
336  * Return: u16.
337  */
338 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
339 
340 /**
341  * qed_int_igu_init_pure_rt_single(): Status block cleanup.
342  *                                    Should be called for each status
343  *                                    block that will be used -> both PF / VF.
344  *
345  * @p_hwfn: HW device data.
346  * @p_ptt: P_ptt.
347  * @igu_sb_id: IGU status block id.
348  * @opaque: Opaque fid of the sb owner.
349  * @b_set: Set(1) / Clear(0).
350  *
351  * Return: Void.
352  */
353 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
354 				     struct qed_ptt *p_ptt,
355 				     u16 igu_sb_id,
356 				     u16 opaque,
357 				     bool b_set);
358 
359 /**
360  * qed_int_cau_conf_sb(): Configure cau for a given status block.
361  *
362  * @p_hwfn: HW device data.
363  * @p_ptt: P_ptt.
364  * @sb_phys: SB Physical.
365  * @igu_sb_id: IGU status block id.
366  * @vf_number: VF number
367  * @vf_valid: VF valid or not.
368  *
369  * Return: Void.
370  */
371 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
372 			 struct qed_ptt *p_ptt,
373 			 dma_addr_t sb_phys,
374 			 u16 igu_sb_id,
375 			 u16 vf_number,
376 			 u8 vf_valid);
377 
378 /**
379  * qed_int_alloc(): QED interrupt alloc.
380  *
381  * @p_hwfn: HW device data.
382  * @p_ptt: P_ptt.
383  *
384  * Return: Int.
385  */
386 int qed_int_alloc(struct qed_hwfn *p_hwfn,
387 		  struct qed_ptt *p_ptt);
388 
389 /**
390  * qed_int_free(): QED interrupt free.
391  *
392  * @p_hwfn: HW device data.
393  *
394  * Return: Void.
395  */
396 void qed_int_free(struct qed_hwfn *p_hwfn);
397 
398 /**
399  * qed_int_setup(): QED interrupt setup.
400  *
401  * @p_hwfn: HW device data.
402  * @p_ptt: P_ptt.
403  *
404  * Return: Void.
405  */
406 void qed_int_setup(struct qed_hwfn *p_hwfn,
407 		   struct qed_ptt *p_ptt);
408 
409 /**
410  * qed_int_igu_enable(): Enable Interrupt & Attention for hw function.
411  *
412  * @p_hwfn: HW device data.
413  * @p_ptt: P_ptt.
414  * @int_mode: Interrut mode
415  *
416  * Return: Int.
417  */
418 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
419 		       enum qed_int_mode int_mode);
420 
421 /**
422  * qed_init_cau_sb_entry(): Initialize CAU status block entry.
423  *
424  * @p_hwfn: HW device data.
425  * @p_sb_entry: Pointer SB entry.
426  * @pf_id: PF number
427  * @vf_number: VF number
428  * @vf_valid: VF valid or not.
429  *
430  * Return: Void.
431  */
432 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
433 			   struct cau_sb_entry *p_sb_entry,
434 			   u8 pf_id,
435 			   u16 vf_number,
436 			   u8 vf_valid);
437 
438 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
439 			  u8 timer_res, u16 sb_id, bool tx);
440 
441 #define QED_MAPPING_MEMORY_SIZE(dev)	(NUM_OF_SBS(dev))
442 
443 int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
444 				bool hw_init);
445 
446 #endif
447