1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_INT_H 34 #define _QED_INT_H 35 36 #include <linux/types.h> 37 #include <linux/slab.h> 38 #include "qed.h" 39 40 /* Fields of IGU PF CONFIGRATION REGISTER */ 41 #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 42 #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 43 #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 44 #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 45 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 46 #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 47 /* Fields of IGU VF CONFIGRATION REGISTER */ 48 #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 49 #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 50 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 51 #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 52 #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 53 54 /* Igu control commands 55 */ 56 enum igu_ctrl_cmd { 57 IGU_CTRL_CMD_TYPE_RD, 58 IGU_CTRL_CMD_TYPE_WR, 59 MAX_IGU_CTRL_CMD 60 }; 61 62 /* Control register for the IGU command register 63 */ 64 struct igu_ctrl_reg { 65 u32 ctrl_data; 66 #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 67 #define IGU_CTRL_REG_FID_SHIFT 0 68 #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 69 #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 70 #define IGU_CTRL_REG_RESERVED_MASK 0x1 71 #define IGU_CTRL_REG_RESERVED_SHIFT 28 72 #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 73 #define IGU_CTRL_REG_TYPE_SHIFT 31 74 }; 75 76 enum qed_coalescing_fsm { 77 QED_COAL_RX_STATE_MACHINE, 78 QED_COAL_TX_STATE_MACHINE 79 }; 80 81 /** 82 * @brief qed_int_cau_conf_pi - configure cau for a given 83 * status block 84 * 85 * @param p_hwfn 86 * @param p_ptt 87 * @param igu_sb_id 88 * @param pi_index 89 * @param state 90 * @param timeset 91 */ 92 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 93 struct qed_ptt *p_ptt, 94 u16 igu_sb_id, 95 u32 pi_index, 96 enum qed_coalescing_fsm coalescing_fsm, 97 u8 timeset); 98 99 /** 100 * @brief qed_int_igu_enable_int - enable device interrupts 101 * 102 * @param p_hwfn 103 * @param p_ptt 104 * @param int_mode - interrupt mode to use 105 */ 106 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 107 struct qed_ptt *p_ptt, 108 enum qed_int_mode int_mode); 109 110 /** 111 * @brief qed_int_igu_disable_int - disable device interrupts 112 * 113 * @param p_hwfn 114 * @param p_ptt 115 */ 116 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 117 struct qed_ptt *p_ptt); 118 119 /** 120 * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 121 * register from igu. 122 * 123 * @param p_hwfn 124 * 125 * @return u64 126 */ 127 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 128 129 #define QED_SP_SB_ID 0xffff 130 /** 131 * @brief qed_int_sb_init - Initializes the sb_info structure. 132 * 133 * once the structure is initialized it can be passed to sb related functions. 134 * 135 * @param p_hwfn 136 * @param p_ptt 137 * @param sb_info points to an uninitialized (but 138 * allocated) sb_info structure 139 * @param sb_virt_addr 140 * @param sb_phy_addr 141 * @param sb_id the sb_id to be used (zero based in driver) 142 * should use QED_SP_SB_ID for SP Status block 143 * 144 * @return int 145 */ 146 int qed_int_sb_init(struct qed_hwfn *p_hwfn, 147 struct qed_ptt *p_ptt, 148 struct qed_sb_info *sb_info, 149 void *sb_virt_addr, 150 dma_addr_t sb_phy_addr, 151 u16 sb_id); 152 /** 153 * @brief qed_int_sb_setup - Setup the sb. 154 * 155 * @param p_hwfn 156 * @param p_ptt 157 * @param sb_info initialized sb_info structure 158 */ 159 void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 160 struct qed_ptt *p_ptt, 161 struct qed_sb_info *sb_info); 162 163 /** 164 * @brief qed_int_sb_release - releases the sb_info structure. 165 * 166 * once the structure is released, it's memory can be freed 167 * 168 * @param p_hwfn 169 * @param sb_info points to an allocated sb_info structure 170 * @param sb_id the sb_id to be used (zero based in driver) 171 * should never be equal to QED_SP_SB_ID 172 * (SP Status block) 173 * 174 * @return int 175 */ 176 int qed_int_sb_release(struct qed_hwfn *p_hwfn, 177 struct qed_sb_info *sb_info, 178 u16 sb_id); 179 180 /** 181 * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 182 * default status block. 183 * 184 * @param p_hwfn - pointer to hwfn 185 * 186 */ 187 void qed_int_sp_dpc(unsigned long hwfn_cookie); 188 189 /** 190 * @brief qed_int_get_num_sbs - get the number of status 191 * blocks configured for this funciton in the igu. 192 * 193 * @param p_hwfn 194 * @param p_sb_cnt_info 195 * 196 * @return int - number of status blocks configured 197 */ 198 void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 199 struct qed_sb_cnt_info *p_sb_cnt_info); 200 201 /** 202 * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR 203 * release. The API need to be called after releasing all slowpath IRQs 204 * of the device. 205 * 206 * @param cdev 207 * 208 */ 209 void qed_int_disable_post_isr_release(struct qed_dev *cdev); 210 211 #define QED_CAU_DEF_RX_TIMER_RES 0 212 #define QED_CAU_DEF_TX_TIMER_RES 0 213 214 #define QED_SB_ATT_IDX 0x0001 215 #define QED_SB_EVENT_MASK 0x0003 216 217 #define SB_ALIGNED_SIZE(p_hwfn) \ 218 ALIGNED_TYPE_SIZE(struct status_block, p_hwfn) 219 220 struct qed_igu_block { 221 u8 status; 222 #define QED_IGU_STATUS_FREE 0x01 223 #define QED_IGU_STATUS_VALID 0x02 224 #define QED_IGU_STATUS_PF 0x04 225 226 u8 vector_number; 227 u8 function_id; 228 u8 is_pf; 229 }; 230 231 struct qed_igu_map { 232 struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH]; 233 }; 234 235 struct qed_igu_info { 236 struct qed_igu_map igu_map; 237 u16 igu_dsb_id; 238 u16 igu_base_sb; 239 u16 igu_base_sb_iov; 240 u16 igu_sb_cnt; 241 u16 igu_sb_cnt_iov; 242 u16 free_blks; 243 }; 244 245 /* TODO Names of function may change... */ 246 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 247 struct qed_ptt *p_ptt, 248 bool b_set, 249 bool b_slowpath); 250 251 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 252 253 /** 254 * @brief qed_int_igu_read_cam - Reads the IGU CAM. 255 * This function needs to be called during hardware 256 * prepare. It reads the info from igu cam to know which 257 * status block is the default / base status block etc. 258 * 259 * @param p_hwfn 260 * @param p_ptt 261 * 262 * @return int 263 */ 264 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 265 struct qed_ptt *p_ptt); 266 267 typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 268 void *cookie); 269 /** 270 * @brief qed_int_register_cb - Register callback func for 271 * slowhwfn statusblock. 272 * 273 * Every protocol that uses the slowhwfn status block 274 * should register a callback function that will be called 275 * once there is an update of the sp status block. 276 * 277 * @param p_hwfn 278 * @param comp_cb - function to be called when there is an 279 * interrupt on the sp sb 280 * 281 * @param cookie - passed to the callback function 282 * @param sb_idx - OUT parameter which gives the chosen index 283 * for this protocol. 284 * @param p_fw_cons - pointer to the actual address of the 285 * consumer for this protocol. 286 * 287 * @return int 288 */ 289 int qed_int_register_cb(struct qed_hwfn *p_hwfn, 290 qed_int_comp_cb_t comp_cb, 291 void *cookie, 292 u8 *sb_idx, 293 __le16 **p_fw_cons); 294 295 /** 296 * @brief qed_int_unregister_cb - Unregisters callback 297 * function from sp sb. 298 * Partner of qed_int_register_cb -> should be called 299 * when no longer required. 300 * 301 * @param p_hwfn 302 * @param pi 303 * 304 * @return int 305 */ 306 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 307 u8 pi); 308 309 /** 310 * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 311 * 312 * @param p_hwfn 313 * 314 * @return u16 315 */ 316 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 317 318 /** 319 * @brief Status block cleanup. Should be called for each status 320 * block that will be used -> both PF / VF 321 * 322 * @param p_hwfn 323 * @param p_ptt 324 * @param sb_id - igu status block id 325 * @param opaque - opaque fid of the sb owner. 326 * @param b_set - set(1) / clear(0) 327 */ 328 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 329 struct qed_ptt *p_ptt, 330 u32 sb_id, 331 u16 opaque, 332 bool b_set); 333 334 /** 335 * @brief qed_int_cau_conf - configure cau for a given status 336 * block 337 * 338 * @param p_hwfn 339 * @param ptt 340 * @param sb_phys 341 * @param igu_sb_id 342 * @param vf_number 343 * @param vf_valid 344 */ 345 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 346 struct qed_ptt *p_ptt, 347 dma_addr_t sb_phys, 348 u16 igu_sb_id, 349 u16 vf_number, 350 u8 vf_valid); 351 352 /** 353 * @brief qed_int_alloc 354 * 355 * @param p_hwfn 356 * @param p_ptt 357 * 358 * @return int 359 */ 360 int qed_int_alloc(struct qed_hwfn *p_hwfn, 361 struct qed_ptt *p_ptt); 362 363 /** 364 * @brief qed_int_free 365 * 366 * @param p_hwfn 367 */ 368 void qed_int_free(struct qed_hwfn *p_hwfn); 369 370 /** 371 * @brief qed_int_setup 372 * 373 * @param p_hwfn 374 * @param p_ptt 375 */ 376 void qed_int_setup(struct qed_hwfn *p_hwfn, 377 struct qed_ptt *p_ptt); 378 379 /** 380 * @brief - Returns an Rx queue index appropriate for usage with given SB. 381 * 382 * @param p_hwfn 383 * @param sb_id - absolute index of SB 384 * 385 * @return index of Rx queue 386 */ 387 u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id); 388 389 /** 390 * @brief - Enable Interrupt & Attention for hw function 391 * 392 * @param p_hwfn 393 * @param p_ptt 394 * @param int_mode 395 * 396 * @return int 397 */ 398 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 399 enum qed_int_mode int_mode); 400 401 /** 402 * @brief - Initialize CAU status block entry 403 * 404 * @param p_hwfn 405 * @param p_sb_entry 406 * @param pf_id 407 * @param vf_number 408 * @param vf_valid 409 */ 410 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 411 struct cau_sb_entry *p_sb_entry, 412 u8 pf_id, 413 u16 vf_number, 414 u8 vf_valid); 415 416 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 417 u8 timer_res, u16 sb_id, bool tx); 418 419 #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 420 421 #endif 422