1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #ifndef _QED_INT_H 10fe56b9e6SYuval Mintz #define _QED_INT_H 11fe56b9e6SYuval Mintz 12fe56b9e6SYuval Mintz #include <linux/types.h> 13fe56b9e6SYuval Mintz #include <linux/slab.h> 14fe56b9e6SYuval Mintz #include "qed.h" 15fe56b9e6SYuval Mintz 16fe56b9e6SYuval Mintz /* Fields of IGU PF CONFIGRATION REGISTER */ 17fe56b9e6SYuval Mintz #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 18fe56b9e6SYuval Mintz #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 19fe56b9e6SYuval Mintz #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 20fe56b9e6SYuval Mintz #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 21fe56b9e6SYuval Mintz #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 22fe56b9e6SYuval Mintz #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 23fe56b9e6SYuval Mintz 24fe56b9e6SYuval Mintz /* Igu control commands 25fe56b9e6SYuval Mintz */ 26fe56b9e6SYuval Mintz enum igu_ctrl_cmd { 27fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_RD, 28fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_WR, 29fe56b9e6SYuval Mintz MAX_IGU_CTRL_CMD 30fe56b9e6SYuval Mintz }; 31fe56b9e6SYuval Mintz 32fe56b9e6SYuval Mintz /* Control register for the IGU command register 33fe56b9e6SYuval Mintz */ 34fe56b9e6SYuval Mintz struct igu_ctrl_reg { 35fe56b9e6SYuval Mintz u32 ctrl_data; 36fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 37fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_SHIFT 0 38fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 39fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 40fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_MASK 0x1 41fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_SHIFT 28 42fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 43fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_SHIFT 31 44fe56b9e6SYuval Mintz }; 45fe56b9e6SYuval Mintz 46fe56b9e6SYuval Mintz enum qed_coalescing_fsm { 47fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 48fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE 49fe56b9e6SYuval Mintz }; 50fe56b9e6SYuval Mintz 51fe56b9e6SYuval Mintz /** 52fe56b9e6SYuval Mintz * @brief qed_int_cau_conf_pi - configure cau for a given 53fe56b9e6SYuval Mintz * status block 54fe56b9e6SYuval Mintz * 55fe56b9e6SYuval Mintz * @param p_hwfn 56fe56b9e6SYuval Mintz * @param p_ptt 57fe56b9e6SYuval Mintz * @param igu_sb_id 58fe56b9e6SYuval Mintz * @param pi_index 59fe56b9e6SYuval Mintz * @param state 60fe56b9e6SYuval Mintz * @param timeset 61fe56b9e6SYuval Mintz */ 62fe56b9e6SYuval Mintz void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 63fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 64fe56b9e6SYuval Mintz u16 igu_sb_id, 65fe56b9e6SYuval Mintz u32 pi_index, 66fe56b9e6SYuval Mintz enum qed_coalescing_fsm coalescing_fsm, 67fe56b9e6SYuval Mintz u8 timeset); 68fe56b9e6SYuval Mintz 69fe56b9e6SYuval Mintz /** 70fe56b9e6SYuval Mintz * @brief qed_int_igu_enable_int - enable device interrupts 71fe56b9e6SYuval Mintz * 72fe56b9e6SYuval Mintz * @param p_hwfn 73fe56b9e6SYuval Mintz * @param p_ptt 74fe56b9e6SYuval Mintz * @param int_mode - interrupt mode to use 75fe56b9e6SYuval Mintz */ 76fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 77fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 78fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 79fe56b9e6SYuval Mintz 80fe56b9e6SYuval Mintz /** 81fe56b9e6SYuval Mintz * @brief qed_int_igu_disable_int - disable device interrupts 82fe56b9e6SYuval Mintz * 83fe56b9e6SYuval Mintz * @param p_hwfn 84fe56b9e6SYuval Mintz * @param p_ptt 85fe56b9e6SYuval Mintz */ 86fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 87fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz /** 90fe56b9e6SYuval Mintz * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 91fe56b9e6SYuval Mintz * register from igu. 92fe56b9e6SYuval Mintz * 93fe56b9e6SYuval Mintz * @param p_hwfn 94fe56b9e6SYuval Mintz * 95fe56b9e6SYuval Mintz * @return u64 96fe56b9e6SYuval Mintz */ 97fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 98fe56b9e6SYuval Mintz 99fe56b9e6SYuval Mintz #define QED_SP_SB_ID 0xffff 100fe56b9e6SYuval Mintz /** 101fe56b9e6SYuval Mintz * @brief qed_int_sb_init - Initializes the sb_info structure. 102fe56b9e6SYuval Mintz * 103fe56b9e6SYuval Mintz * once the structure is initialized it can be passed to sb related functions. 104fe56b9e6SYuval Mintz * 105fe56b9e6SYuval Mintz * @param p_hwfn 106fe56b9e6SYuval Mintz * @param p_ptt 107fe56b9e6SYuval Mintz * @param sb_info points to an uninitialized (but 108fe56b9e6SYuval Mintz * allocated) sb_info structure 109fe56b9e6SYuval Mintz * @param sb_virt_addr 110fe56b9e6SYuval Mintz * @param sb_phy_addr 111fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 112fe56b9e6SYuval Mintz * should use QED_SP_SB_ID for SP Status block 113fe56b9e6SYuval Mintz * 114fe56b9e6SYuval Mintz * @return int 115fe56b9e6SYuval Mintz */ 116fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 117fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 118fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 119fe56b9e6SYuval Mintz void *sb_virt_addr, 120fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 121fe56b9e6SYuval Mintz u16 sb_id); 122fe56b9e6SYuval Mintz /** 123fe56b9e6SYuval Mintz * @brief qed_int_sb_setup - Setup the sb. 124fe56b9e6SYuval Mintz * 125fe56b9e6SYuval Mintz * @param p_hwfn 126fe56b9e6SYuval Mintz * @param p_ptt 127fe56b9e6SYuval Mintz * @param sb_info initialized sb_info structure 128fe56b9e6SYuval Mintz */ 129fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 130fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 131fe56b9e6SYuval Mintz struct qed_sb_info *sb_info); 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz /** 134fe56b9e6SYuval Mintz * @brief qed_int_sb_release - releases the sb_info structure. 135fe56b9e6SYuval Mintz * 136fe56b9e6SYuval Mintz * once the structure is released, it's memory can be freed 137fe56b9e6SYuval Mintz * 138fe56b9e6SYuval Mintz * @param p_hwfn 139fe56b9e6SYuval Mintz * @param sb_info points to an allocated sb_info structure 140fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 141fe56b9e6SYuval Mintz * should never be equal to QED_SP_SB_ID 142fe56b9e6SYuval Mintz * (SP Status block) 143fe56b9e6SYuval Mintz * 144fe56b9e6SYuval Mintz * @return int 145fe56b9e6SYuval Mintz */ 146fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 147fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 148fe56b9e6SYuval Mintz u16 sb_id); 149fe56b9e6SYuval Mintz 150fe56b9e6SYuval Mintz /** 151fe56b9e6SYuval Mintz * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 152fe56b9e6SYuval Mintz * default status block. 153fe56b9e6SYuval Mintz * 154fe56b9e6SYuval Mintz * @param p_hwfn - pointer to hwfn 155fe56b9e6SYuval Mintz * 156fe56b9e6SYuval Mintz */ 157fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie); 158fe56b9e6SYuval Mintz 159fe56b9e6SYuval Mintz /** 160fe56b9e6SYuval Mintz * @brief qed_int_get_num_sbs - get the number of status 161fe56b9e6SYuval Mintz * blocks configured for this funciton in the igu. 162fe56b9e6SYuval Mintz * 163fe56b9e6SYuval Mintz * @param p_hwfn 164fe56b9e6SYuval Mintz * @param p_iov_blks - configured free blks for vfs 165fe56b9e6SYuval Mintz * 166fe56b9e6SYuval Mintz * @return int - number of status blocks configured 167fe56b9e6SYuval Mintz */ 168fe56b9e6SYuval Mintz int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 169fe56b9e6SYuval Mintz int *p_iov_blks); 170fe56b9e6SYuval Mintz 171fe56b9e6SYuval Mintz /** 172fe56b9e6SYuval Mintz * @file 173fe56b9e6SYuval Mintz * 174fe56b9e6SYuval Mintz * @brief Interrupt handler 175fe56b9e6SYuval Mintz */ 176fe56b9e6SYuval Mintz 177fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_TIMER_RES 0 178fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_TIMER_RES 0 179fe56b9e6SYuval Mintz 180fe56b9e6SYuval Mintz #define QED_SB_ATT_IDX 0x0001 181fe56b9e6SYuval Mintz #define QED_SB_EVENT_MASK 0x0003 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz #define SB_ALIGNED_SIZE(p_hwfn) \ 184fe56b9e6SYuval Mintz ALIGNED_TYPE_SIZE(struct status_block, p_hwfn) 185fe56b9e6SYuval Mintz 186fe56b9e6SYuval Mintz struct qed_igu_block { 187fe56b9e6SYuval Mintz u8 status; 188fe56b9e6SYuval Mintz #define QED_IGU_STATUS_FREE 0x01 189fe56b9e6SYuval Mintz #define QED_IGU_STATUS_VALID 0x02 190fe56b9e6SYuval Mintz #define QED_IGU_STATUS_PF 0x04 191fe56b9e6SYuval Mintz 192fe56b9e6SYuval Mintz u8 vector_number; 193fe56b9e6SYuval Mintz u8 function_id; 194fe56b9e6SYuval Mintz u8 is_pf; 195fe56b9e6SYuval Mintz }; 196fe56b9e6SYuval Mintz 197fe56b9e6SYuval Mintz struct qed_igu_map { 198fe56b9e6SYuval Mintz struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH]; 199fe56b9e6SYuval Mintz }; 200fe56b9e6SYuval Mintz 201fe56b9e6SYuval Mintz struct qed_igu_info { 202fe56b9e6SYuval Mintz struct qed_igu_map igu_map; 203fe56b9e6SYuval Mintz u16 igu_dsb_id; 204fe56b9e6SYuval Mintz u16 igu_base_sb; 205fe56b9e6SYuval Mintz u16 igu_base_sb_iov; 206fe56b9e6SYuval Mintz u16 igu_sb_cnt; 207fe56b9e6SYuval Mintz u16 igu_sb_cnt_iov; 208fe56b9e6SYuval Mintz u16 free_blks; 209fe56b9e6SYuval Mintz }; 210fe56b9e6SYuval Mintz 211fe56b9e6SYuval Mintz /* TODO Names of function may change... */ 212fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 213fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 214fe56b9e6SYuval Mintz bool b_set, 215fe56b9e6SYuval Mintz bool b_slowpath); 216fe56b9e6SYuval Mintz 217fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 218fe56b9e6SYuval Mintz 219fe56b9e6SYuval Mintz /** 220fe56b9e6SYuval Mintz * @brief qed_int_igu_read_cam - Reads the IGU CAM. 221fe56b9e6SYuval Mintz * This function needs to be called during hardware 222fe56b9e6SYuval Mintz * prepare. It reads the info from igu cam to know which 223fe56b9e6SYuval Mintz * status block is the default / base status block etc. 224fe56b9e6SYuval Mintz * 225fe56b9e6SYuval Mintz * @param p_hwfn 226fe56b9e6SYuval Mintz * @param p_ptt 227fe56b9e6SYuval Mintz * 228fe56b9e6SYuval Mintz * @return int 229fe56b9e6SYuval Mintz */ 230fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 231fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 232fe56b9e6SYuval Mintz 233fe56b9e6SYuval Mintz typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 234fe56b9e6SYuval Mintz void *cookie); 235fe56b9e6SYuval Mintz /** 236fe56b9e6SYuval Mintz * @brief qed_int_register_cb - Register callback func for 237fe56b9e6SYuval Mintz * slowhwfn statusblock. 238fe56b9e6SYuval Mintz * 239fe56b9e6SYuval Mintz * Every protocol that uses the slowhwfn status block 240fe56b9e6SYuval Mintz * should register a callback function that will be called 241fe56b9e6SYuval Mintz * once there is an update of the sp status block. 242fe56b9e6SYuval Mintz * 243fe56b9e6SYuval Mintz * @param p_hwfn 244fe56b9e6SYuval Mintz * @param comp_cb - function to be called when there is an 245fe56b9e6SYuval Mintz * interrupt on the sp sb 246fe56b9e6SYuval Mintz * 247fe56b9e6SYuval Mintz * @param cookie - passed to the callback function 248fe56b9e6SYuval Mintz * @param sb_idx - OUT parameter which gives the chosen index 249fe56b9e6SYuval Mintz * for this protocol. 250fe56b9e6SYuval Mintz * @param p_fw_cons - pointer to the actual address of the 251fe56b9e6SYuval Mintz * consumer for this protocol. 252fe56b9e6SYuval Mintz * 253fe56b9e6SYuval Mintz * @return int 254fe56b9e6SYuval Mintz */ 255fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 256fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 257fe56b9e6SYuval Mintz void *cookie, 258fe56b9e6SYuval Mintz u8 *sb_idx, 259fe56b9e6SYuval Mintz __le16 **p_fw_cons); 260fe56b9e6SYuval Mintz 261fe56b9e6SYuval Mintz /** 262fe56b9e6SYuval Mintz * @brief qed_int_unregister_cb - Unregisters callback 263fe56b9e6SYuval Mintz * function from sp sb. 264fe56b9e6SYuval Mintz * Partner of qed_int_register_cb -> should be called 265fe56b9e6SYuval Mintz * when no longer required. 266fe56b9e6SYuval Mintz * 267fe56b9e6SYuval Mintz * @param p_hwfn 268fe56b9e6SYuval Mintz * @param pi 269fe56b9e6SYuval Mintz * 270fe56b9e6SYuval Mintz * @return int 271fe56b9e6SYuval Mintz */ 272fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 273fe56b9e6SYuval Mintz u8 pi); 274fe56b9e6SYuval Mintz 275fe56b9e6SYuval Mintz /** 276fe56b9e6SYuval Mintz * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 277fe56b9e6SYuval Mintz * 278fe56b9e6SYuval Mintz * @param p_hwfn 279fe56b9e6SYuval Mintz * 280fe56b9e6SYuval Mintz * @return u16 281fe56b9e6SYuval Mintz */ 282fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 283fe56b9e6SYuval Mintz 284fe56b9e6SYuval Mintz /** 285fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 286fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 287fe56b9e6SYuval Mintz * 288fe56b9e6SYuval Mintz * @param p_hwfn 289fe56b9e6SYuval Mintz * @param p_ptt 290fe56b9e6SYuval Mintz * @param sb_id - igu status block id 291fe56b9e6SYuval Mintz * @param cleanup_set - set(1) / clear(0) 292fe56b9e6SYuval Mintz * @param opaque_fid - the function for which to perform 293fe56b9e6SYuval Mintz * cleanup, for example a PF on behalf of 294fe56b9e6SYuval Mintz * its VFs. 295fe56b9e6SYuval Mintz */ 296fe56b9e6SYuval Mintz void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 297fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 298fe56b9e6SYuval Mintz u32 sb_id, 299fe56b9e6SYuval Mintz bool cleanup_set, 300fe56b9e6SYuval Mintz u16 opaque_fid); 301fe56b9e6SYuval Mintz 302fe56b9e6SYuval Mintz /** 303fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 304fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 305fe56b9e6SYuval Mintz * 306fe56b9e6SYuval Mintz * @param p_hwfn 307fe56b9e6SYuval Mintz * @param p_ptt 308fe56b9e6SYuval Mintz * @param sb_id - igu status block id 309fe56b9e6SYuval Mintz * @param opaque - opaque fid of the sb owner. 310fe56b9e6SYuval Mintz * @param cleanup_set - set(1) / clear(0) 311fe56b9e6SYuval Mintz */ 312fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 313fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 314fe56b9e6SYuval Mintz u32 sb_id, 315fe56b9e6SYuval Mintz u16 opaque, 316fe56b9e6SYuval Mintz bool b_set); 317fe56b9e6SYuval Mintz 318fe56b9e6SYuval Mintz /** 319fe56b9e6SYuval Mintz * @brief qed_int_cau_conf - configure cau for a given status 320fe56b9e6SYuval Mintz * block 321fe56b9e6SYuval Mintz * 322fe56b9e6SYuval Mintz * @param p_hwfn 323fe56b9e6SYuval Mintz * @param ptt 324fe56b9e6SYuval Mintz * @param sb_phys 325fe56b9e6SYuval Mintz * @param igu_sb_id 326fe56b9e6SYuval Mintz * @param vf_number 327fe56b9e6SYuval Mintz * @param vf_valid 328fe56b9e6SYuval Mintz */ 329fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 330fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 331fe56b9e6SYuval Mintz dma_addr_t sb_phys, 332fe56b9e6SYuval Mintz u16 igu_sb_id, 333fe56b9e6SYuval Mintz u16 vf_number, 334fe56b9e6SYuval Mintz u8 vf_valid); 335fe56b9e6SYuval Mintz 336fe56b9e6SYuval Mintz /** 337fe56b9e6SYuval Mintz * @brief qed_int_alloc 338fe56b9e6SYuval Mintz * 339fe56b9e6SYuval Mintz * @param p_hwfn 340fe56b9e6SYuval Mintz * @param p_ptt 341fe56b9e6SYuval Mintz * 342fe56b9e6SYuval Mintz * @return int 343fe56b9e6SYuval Mintz */ 344fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 345fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 346fe56b9e6SYuval Mintz 347fe56b9e6SYuval Mintz /** 348fe56b9e6SYuval Mintz * @brief qed_int_free 349fe56b9e6SYuval Mintz * 350fe56b9e6SYuval Mintz * @param p_hwfn 351fe56b9e6SYuval Mintz */ 352fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn); 353fe56b9e6SYuval Mintz 354fe56b9e6SYuval Mintz /** 355fe56b9e6SYuval Mintz * @brief qed_int_setup 356fe56b9e6SYuval Mintz * 357fe56b9e6SYuval Mintz * @param p_hwfn 358fe56b9e6SYuval Mintz * @param p_ptt 359fe56b9e6SYuval Mintz */ 360fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 361fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 362fe56b9e6SYuval Mintz 363fe56b9e6SYuval Mintz /** 364fe56b9e6SYuval Mintz * @brief - Enable Interrupt & Attention for hw function 365fe56b9e6SYuval Mintz * 366fe56b9e6SYuval Mintz * @param p_hwfn 367fe56b9e6SYuval Mintz * @param p_ptt 368fe56b9e6SYuval Mintz * @param int_mode 369fe56b9e6SYuval Mintz */ 370fe56b9e6SYuval Mintz void qed_int_igu_enable(struct qed_hwfn *p_hwfn, 371fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 372fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 373fe56b9e6SYuval Mintz 374fe56b9e6SYuval Mintz /** 375fe56b9e6SYuval Mintz * @brief - Initialize CAU status block entry 376fe56b9e6SYuval Mintz * 377fe56b9e6SYuval Mintz * @param p_hwfn 378fe56b9e6SYuval Mintz * @param p_sb_entry 379fe56b9e6SYuval Mintz * @param pf_id 380fe56b9e6SYuval Mintz * @param vf_number 381fe56b9e6SYuval Mintz * @param vf_valid 382fe56b9e6SYuval Mintz */ 383fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 384fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 385fe56b9e6SYuval Mintz u8 pf_id, 386fe56b9e6SYuval Mintz u16 vf_number, 387fe56b9e6SYuval Mintz u8 vf_valid); 388fe56b9e6SYuval Mintz 389fe56b9e6SYuval Mintz #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 390fe56b9e6SYuval Mintz 391fe56b9e6SYuval Mintz #endif 392