11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #ifndef _QED_INT_H 8fe56b9e6SYuval Mintz #define _QED_INT_H 9fe56b9e6SYuval Mintz 10fe56b9e6SYuval Mintz #include <linux/types.h> 11fe56b9e6SYuval Mintz #include <linux/slab.h> 12fe56b9e6SYuval Mintz #include "qed.h" 13fe56b9e6SYuval Mintz 14c199ce4fSGeert Uytterhoeven /* Fields of IGU PF CONFIGURATION REGISTER */ 15fe56b9e6SYuval Mintz #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 16fe56b9e6SYuval Mintz #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 17fe56b9e6SYuval Mintz #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 18fe56b9e6SYuval Mintz #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 19fe56b9e6SYuval Mintz #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 20fe56b9e6SYuval Mintz #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 21c199ce4fSGeert Uytterhoeven /* Fields of IGU VF CONFIGURATION REGISTER */ 221408cc1fSYuval Mintz #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 231408cc1fSYuval Mintz #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 241408cc1fSYuval Mintz #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 251408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 261408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 27fe56b9e6SYuval Mintz 28fe56b9e6SYuval Mintz /* Igu control commands 29fe56b9e6SYuval Mintz */ 30fe56b9e6SYuval Mintz enum igu_ctrl_cmd { 31fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_RD, 32fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_WR, 33fe56b9e6SYuval Mintz MAX_IGU_CTRL_CMD 34fe56b9e6SYuval Mintz }; 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz /* Control register for the IGU command register 37fe56b9e6SYuval Mintz */ 38fe56b9e6SYuval Mintz struct igu_ctrl_reg { 39fe56b9e6SYuval Mintz u32 ctrl_data; 40fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 41fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_SHIFT 0 42fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 43fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 44fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_MASK 0x1 45fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_SHIFT 28 46fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 47fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_SHIFT 31 48fe56b9e6SYuval Mintz }; 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz enum qed_coalescing_fsm { 51fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 52fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE 53fe56b9e6SYuval Mintz }; 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz /** 5619198e4eSPrabhakar Kushwaha * qed_int_igu_enable_int(): Enable device interrupts. 57fe56b9e6SYuval Mintz * 5819198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 5919198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 6019198e4eSPrabhakar Kushwaha * @int_mode: Interrupt mode to use. 6119198e4eSPrabhakar Kushwaha * 6219198e4eSPrabhakar Kushwaha * Return: Void. 63fe56b9e6SYuval Mintz */ 64fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 65fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 66fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz /** 6919198e4eSPrabhakar Kushwaha * qed_int_igu_disable_int(): Disable device interrupts. 70fe56b9e6SYuval Mintz * 7119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 7219198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 7319198e4eSPrabhakar Kushwaha * 7419198e4eSPrabhakar Kushwaha * Return: Void. 75fe56b9e6SYuval Mintz */ 76fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 77fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 78fe56b9e6SYuval Mintz 79fe56b9e6SYuval Mintz /** 8019198e4eSPrabhakar Kushwaha * qed_int_igu_read_sisr_reg(): Reads the single isr multiple dpc 81fe56b9e6SYuval Mintz * register from igu. 82fe56b9e6SYuval Mintz * 8319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 84fe56b9e6SYuval Mintz * 8519198e4eSPrabhakar Kushwaha * Return: u64. 86fe56b9e6SYuval Mintz */ 87fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz #define QED_SP_SB_ID 0xffff 90fe56b9e6SYuval Mintz /** 9119198e4eSPrabhakar Kushwaha * qed_int_sb_init(): Initializes the sb_info structure. 92fe56b9e6SYuval Mintz * 9319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 9419198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 9519198e4eSPrabhakar Kushwaha * @sb_info: points to an uninitialized (but allocated) sb_info structure 9619198e4eSPrabhakar Kushwaha * @sb_virt_addr: SB Virtual address. 9719198e4eSPrabhakar Kushwaha * @sb_phy_addr: SB Physial address. 9819198e4eSPrabhakar Kushwaha * @sb_id: the sb_id to be used (zero based in driver) 99fe56b9e6SYuval Mintz * should use QED_SP_SB_ID for SP Status block 100fe56b9e6SYuval Mintz * 10119198e4eSPrabhakar Kushwaha * Return: int. 10219198e4eSPrabhakar Kushwaha * 10319198e4eSPrabhakar Kushwaha * Once the structure is initialized it can be passed to sb related functions. 104fe56b9e6SYuval Mintz */ 105fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 106fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 107fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 108fe56b9e6SYuval Mintz void *sb_virt_addr, 109fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 110fe56b9e6SYuval Mintz u16 sb_id); 111fe56b9e6SYuval Mintz /** 11219198e4eSPrabhakar Kushwaha * qed_int_sb_setup(): Setup the sb. 113fe56b9e6SYuval Mintz * 11419198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 11519198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 11619198e4eSPrabhakar Kushwaha * @sb_info: Initialized sb_info structure. 11719198e4eSPrabhakar Kushwaha * 11819198e4eSPrabhakar Kushwaha * Return: Void. 119fe56b9e6SYuval Mintz */ 120fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 121fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 122fe56b9e6SYuval Mintz struct qed_sb_info *sb_info); 123fe56b9e6SYuval Mintz 124fe56b9e6SYuval Mintz /** 12519198e4eSPrabhakar Kushwaha * qed_int_sb_release(): Releases the sb_info structure. 126fe56b9e6SYuval Mintz * 12719198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 12819198e4eSPrabhakar Kushwaha * @sb_info: Points to an allocated sb_info structure. 12919198e4eSPrabhakar Kushwaha * @sb_id: The sb_id to be used (zero based in driver) 130fe56b9e6SYuval Mintz * should never be equal to QED_SP_SB_ID 13119198e4eSPrabhakar Kushwaha * (SP Status block). 132fe56b9e6SYuval Mintz * 13319198e4eSPrabhakar Kushwaha * Return: int. 13419198e4eSPrabhakar Kushwaha * 13519198e4eSPrabhakar Kushwaha * Once the structure is released, it's memory can be freed. 136fe56b9e6SYuval Mintz */ 137fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 138fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 139fe56b9e6SYuval Mintz u16 sb_id); 140fe56b9e6SYuval Mintz 141fe56b9e6SYuval Mintz /** 14219198e4eSPrabhakar Kushwaha * qed_int_sp_dpc(): To be called when an interrupt is received on the 143fe56b9e6SYuval Mintz * default status block. 144fe56b9e6SYuval Mintz * 14519198e4eSPrabhakar Kushwaha * @t: Tasklet. 14619198e4eSPrabhakar Kushwaha * 14719198e4eSPrabhakar Kushwaha * Return: Void. 148fe56b9e6SYuval Mintz * 149fe56b9e6SYuval Mintz */ 150b5f0a3bfSAllen Pais void qed_int_sp_dpc(struct tasklet_struct *t); 151fe56b9e6SYuval Mintz 152fe56b9e6SYuval Mintz /** 15319198e4eSPrabhakar Kushwaha * qed_int_get_num_sbs(): Get the number of status blocks configured 15419198e4eSPrabhakar Kushwaha * for this funciton in the igu. 155fe56b9e6SYuval Mintz * 15619198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 15719198e4eSPrabhakar Kushwaha * @p_sb_cnt_info: Pointer to SB count info. 158fe56b9e6SYuval Mintz * 15919198e4eSPrabhakar Kushwaha * Return: Void. 160fe56b9e6SYuval Mintz */ 1614ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 1624ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info); 163fe56b9e6SYuval Mintz 164fe56b9e6SYuval Mintz /** 16519198e4eSPrabhakar Kushwaha * qed_int_disable_post_isr_release(): Performs the cleanup post ISR 1668f16bc97SSudarsana Kalluru * release. The API need to be called after releasing all slowpath IRQs 1678f16bc97SSudarsana Kalluru * of the device. 168fe56b9e6SYuval Mintz * 16919198e4eSPrabhakar Kushwaha * @cdev: Qed dev pointer. 1708f16bc97SSudarsana Kalluru * 17119198e4eSPrabhakar Kushwaha * Return: Void. 172fe56b9e6SYuval Mintz */ 1738f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev); 174fe56b9e6SYuval Mintz 175a1b469b8SAriel Elior /** 17619198e4eSPrabhakar Kushwaha * qed_int_attn_clr_enable: Sets whether the general behavior is 177936c7ba4SIgor Russkikh * preventing attentions from being reasserted, or following the 178936c7ba4SIgor Russkikh * attributes of the specific attention. 179936c7ba4SIgor Russkikh * 18019198e4eSPrabhakar Kushwaha * @cdev: Qed dev pointer. 18119198e4eSPrabhakar Kushwaha * @clr_enable: Clear enable 18219198e4eSPrabhakar Kushwaha * 18319198e4eSPrabhakar Kushwaha * Return: Void. 184936c7ba4SIgor Russkikh * 185936c7ba4SIgor Russkikh */ 186936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable); 187936c7ba4SIgor Russkikh 188936c7ba4SIgor Russkikh /** 18919198e4eSPrabhakar Kushwaha * qed_db_rec_handler(): Doorbell Recovery handler. 1909ac6bb14SDenis Bolotin * Run doorbell recovery in case of PF overflow (and flush DORQ if 1919ac6bb14SDenis Bolotin * needed). 192a1b469b8SAriel Elior * 19319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 19419198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 19519198e4eSPrabhakar Kushwaha * 19619198e4eSPrabhakar Kushwaha * Return: Int. 197a1b469b8SAriel Elior */ 198a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 199a1b469b8SAriel Elior 200fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_TIMER_RES 0 201fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_TIMER_RES 0 202fe56b9e6SYuval Mintz 203fe56b9e6SYuval Mintz #define QED_SB_ATT_IDX 0x0001 204fe56b9e6SYuval Mintz #define QED_SB_EVENT_MASK 0x0003 205fe56b9e6SYuval Mintz 206fe56b9e6SYuval Mintz #define SB_ALIGNED_SIZE(p_hwfn) \ 207*fb09a1edSShai Malin ALIGNED_TYPE_SIZE(struct status_block, p_hwfn) 208fe56b9e6SYuval Mintz 209d749dd0dSMintz, Yuval #define QED_SB_INVALID_IDX 0xffff 210d749dd0dSMintz, Yuval 211fe56b9e6SYuval Mintz struct qed_igu_block { 212fe56b9e6SYuval Mintz u8 status; 213fe56b9e6SYuval Mintz #define QED_IGU_STATUS_FREE 0x01 214fe56b9e6SYuval Mintz #define QED_IGU_STATUS_VALID 0x02 215fe56b9e6SYuval Mintz #define QED_IGU_STATUS_PF 0x04 216d749dd0dSMintz, Yuval #define QED_IGU_STATUS_DSB 0x08 217fe56b9e6SYuval Mintz 218fe56b9e6SYuval Mintz u8 vector_number; 219fe56b9e6SYuval Mintz u8 function_id; 220fe56b9e6SYuval Mintz u8 is_pf; 2211ac72433SMintz, Yuval 2221ac72433SMintz, Yuval /* Index inside IGU [meant for back reference] */ 2231ac72433SMintz, Yuval u16 igu_sb_id; 22450a20714SMintz, Yuval 22550a20714SMintz, Yuval struct qed_sb_info *sb_info; 226fe56b9e6SYuval Mintz }; 227fe56b9e6SYuval Mintz 228fe56b9e6SYuval Mintz struct qed_igu_info { 229d749dd0dSMintz, Yuval struct qed_igu_block entry[MAX_TOT_SB_PER_PATH]; 230fe56b9e6SYuval Mintz u16 igu_dsb_id; 231726fdbe9SMintz, Yuval 232726fdbe9SMintz, Yuval struct qed_sb_cnt_info usage; 233726fdbe9SMintz, Yuval 234ebbdcc66SMintz, Yuval bool b_allow_pf_vf_change; 235fe56b9e6SYuval Mintz }; 236fe56b9e6SYuval Mintz 23750a20714SMintz, Yuval /** 23819198e4eSPrabhakar Kushwaha * qed_int_igu_reset_cam(): Make sure the IGU CAM reflects the resources 23919198e4eSPrabhakar Kushwaha * provided by MFW. 240ebbdcc66SMintz, Yuval * 24119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 24219198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 24319198e4eSPrabhakar Kushwaha * 24419198e4eSPrabhakar Kushwaha * Return: Void. 245ebbdcc66SMintz, Yuval */ 246ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 247ebbdcc66SMintz, Yuval 248ebbdcc66SMintz, Yuval /** 24919198e4eSPrabhakar Kushwaha * qed_get_igu_sb_id(): Translate the weakly-defined client sb-id into 25019198e4eSPrabhakar Kushwaha * an IGU sb-id 25150a20714SMintz, Yuval * 25219198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 25319198e4eSPrabhakar Kushwaha * @sb_id: user provided sb_id. 25450a20714SMintz, Yuval * 25519198e4eSPrabhakar Kushwaha * Return: An index inside IGU CAM where the SB resides. 25650a20714SMintz, Yuval */ 25750a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id); 25850a20714SMintz, Yuval 25909b6b147SMintz, Yuval /** 26019198e4eSPrabhakar Kushwaha * qed_get_igu_free_sb(): Return a pointer to an unused valid SB 26109b6b147SMintz, Yuval * 26219198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 26319198e4eSPrabhakar Kushwaha * @b_is_pf: True iff we want a SB belonging to a PF. 26409b6b147SMintz, Yuval * 26519198e4eSPrabhakar Kushwaha * Return: Point to an igu_block, NULL if none is available. 26609b6b147SMintz, Yuval */ 26709b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, 26809b6b147SMintz, Yuval bool b_is_pf); 26909b6b147SMintz, Yuval 270fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 271fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 272fe56b9e6SYuval Mintz bool b_set, 273fe56b9e6SYuval Mintz bool b_slowpath); 274fe56b9e6SYuval Mintz 275fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 276fe56b9e6SYuval Mintz 277fe56b9e6SYuval Mintz /** 27819198e4eSPrabhakar Kushwaha * qed_int_igu_read_cam(): Reads the IGU CAM. 279fe56b9e6SYuval Mintz * This function needs to be called during hardware 280fe56b9e6SYuval Mintz * prepare. It reads the info from igu cam to know which 281fe56b9e6SYuval Mintz * status block is the default / base status block etc. 282fe56b9e6SYuval Mintz * 28319198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 28419198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 285fe56b9e6SYuval Mintz * 28619198e4eSPrabhakar Kushwaha * Return: Int. 287fe56b9e6SYuval Mintz */ 288fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 289fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 290fe56b9e6SYuval Mintz 291fe56b9e6SYuval Mintz typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 292fe56b9e6SYuval Mintz void *cookie); 293fe56b9e6SYuval Mintz /** 29419198e4eSPrabhakar Kushwaha * qed_int_register_cb(): Register callback func for slowhwfn statusblock. 29519198e4eSPrabhakar Kushwaha * 29619198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 29719198e4eSPrabhakar Kushwaha * @comp_cb: Function to be called when there is an 29819198e4eSPrabhakar Kushwaha * interrupt on the sp sb 29919198e4eSPrabhakar Kushwaha * @cookie: Passed to the callback function 30019198e4eSPrabhakar Kushwaha * @sb_idx: (OUT) parameter which gives the chosen index 30119198e4eSPrabhakar Kushwaha * for this protocol. 30219198e4eSPrabhakar Kushwaha * @p_fw_cons: Pointer to the actual address of the 30319198e4eSPrabhakar Kushwaha * consumer for this protocol. 30419198e4eSPrabhakar Kushwaha * 30519198e4eSPrabhakar Kushwaha * Return: Int. 306fe56b9e6SYuval Mintz * 307fe56b9e6SYuval Mintz * Every protocol that uses the slowhwfn status block 308fe56b9e6SYuval Mintz * should register a callback function that will be called 309fe56b9e6SYuval Mintz * once there is an update of the sp status block. 310fe56b9e6SYuval Mintz */ 311fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 312fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 313fe56b9e6SYuval Mintz void *cookie, 314fe56b9e6SYuval Mintz u8 *sb_idx, 315fe56b9e6SYuval Mintz __le16 **p_fw_cons); 316fe56b9e6SYuval Mintz 317fe56b9e6SYuval Mintz /** 31819198e4eSPrabhakar Kushwaha * qed_int_unregister_cb(): Unregisters callback function from sp sb. 31919198e4eSPrabhakar Kushwaha * 32019198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 32119198e4eSPrabhakar Kushwaha * @pi: Producer Index. 32219198e4eSPrabhakar Kushwaha * 32319198e4eSPrabhakar Kushwaha * Return: Int. 32419198e4eSPrabhakar Kushwaha * 325fe56b9e6SYuval Mintz * Partner of qed_int_register_cb -> should be called 326fe56b9e6SYuval Mintz * when no longer required. 327fe56b9e6SYuval Mintz */ 328fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 329fe56b9e6SYuval Mintz u8 pi); 330fe56b9e6SYuval Mintz 331fe56b9e6SYuval Mintz /** 33219198e4eSPrabhakar Kushwaha * qed_int_get_sp_sb_id(): Get the slowhwfn sb id. 333fe56b9e6SYuval Mintz * 33419198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 335fe56b9e6SYuval Mintz * 33619198e4eSPrabhakar Kushwaha * Return: u16. 337fe56b9e6SYuval Mintz */ 338fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 339fe56b9e6SYuval Mintz 340fe56b9e6SYuval Mintz /** 34119198e4eSPrabhakar Kushwaha * qed_int_igu_init_pure_rt_single(): Status block cleanup. 34219198e4eSPrabhakar Kushwaha * Should be called for each status 34319198e4eSPrabhakar Kushwaha * block that will be used -> both PF / VF. 344fe56b9e6SYuval Mintz * 34519198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 34619198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 34719198e4eSPrabhakar Kushwaha * @igu_sb_id: IGU status block id. 34819198e4eSPrabhakar Kushwaha * @opaque: Opaque fid of the sb owner. 34919198e4eSPrabhakar Kushwaha * @b_set: Set(1) / Clear(0). 35019198e4eSPrabhakar Kushwaha * 35119198e4eSPrabhakar Kushwaha * Return: Void. 352fe56b9e6SYuval Mintz */ 353fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 354fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 355d031548eSMintz, Yuval u16 igu_sb_id, 356fe56b9e6SYuval Mintz u16 opaque, 357fe56b9e6SYuval Mintz bool b_set); 358fe56b9e6SYuval Mintz 359fe56b9e6SYuval Mintz /** 36019198e4eSPrabhakar Kushwaha * qed_int_cau_conf_sb(): Configure cau for a given status block. 361fe56b9e6SYuval Mintz * 36219198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 36319198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 36419198e4eSPrabhakar Kushwaha * @sb_phys: SB Physical. 36519198e4eSPrabhakar Kushwaha * @igu_sb_id: IGU status block id. 36619198e4eSPrabhakar Kushwaha * @vf_number: VF number 36719198e4eSPrabhakar Kushwaha * @vf_valid: VF valid or not. 36819198e4eSPrabhakar Kushwaha * 36919198e4eSPrabhakar Kushwaha * Return: Void. 370fe56b9e6SYuval Mintz */ 371fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 372fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 373fe56b9e6SYuval Mintz dma_addr_t sb_phys, 374fe56b9e6SYuval Mintz u16 igu_sb_id, 375fe56b9e6SYuval Mintz u16 vf_number, 376fe56b9e6SYuval Mintz u8 vf_valid); 377fe56b9e6SYuval Mintz 378fe56b9e6SYuval Mintz /** 37919198e4eSPrabhakar Kushwaha * qed_int_alloc(): QED interrupt alloc. 380fe56b9e6SYuval Mintz * 38119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 38219198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 383fe56b9e6SYuval Mintz * 38419198e4eSPrabhakar Kushwaha * Return: Int. 385fe56b9e6SYuval Mintz */ 386fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 387fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 388fe56b9e6SYuval Mintz 389fe56b9e6SYuval Mintz /** 39019198e4eSPrabhakar Kushwaha * qed_int_free(): QED interrupt free. 391fe56b9e6SYuval Mintz * 39219198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 39319198e4eSPrabhakar Kushwaha * 39419198e4eSPrabhakar Kushwaha * Return: Void. 395fe56b9e6SYuval Mintz */ 396fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn); 397fe56b9e6SYuval Mintz 398fe56b9e6SYuval Mintz /** 39919198e4eSPrabhakar Kushwaha * qed_int_setup(): QED interrupt setup. 400fe56b9e6SYuval Mintz * 40119198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 40219198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 40319198e4eSPrabhakar Kushwaha * 40419198e4eSPrabhakar Kushwaha * Return: Void. 405fe56b9e6SYuval Mintz */ 406fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 407fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 408fe56b9e6SYuval Mintz 409fe56b9e6SYuval Mintz /** 41019198e4eSPrabhakar Kushwaha * qed_int_igu_enable(): Enable Interrupt & Attention for hw function. 411fe56b9e6SYuval Mintz * 41219198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 41319198e4eSPrabhakar Kushwaha * @p_ptt: P_ptt. 41419198e4eSPrabhakar Kushwaha * @int_mode: Interrut mode 4158f16bc97SSudarsana Kalluru * 41619198e4eSPrabhakar Kushwaha * Return: Int. 417fe56b9e6SYuval Mintz */ 4188f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 419fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 420fe56b9e6SYuval Mintz 421fe56b9e6SYuval Mintz /** 42219198e4eSPrabhakar Kushwaha * qed_init_cau_sb_entry(): Initialize CAU status block entry. 423fe56b9e6SYuval Mintz * 42419198e4eSPrabhakar Kushwaha * @p_hwfn: HW device data. 42519198e4eSPrabhakar Kushwaha * @p_sb_entry: Pointer SB entry. 42619198e4eSPrabhakar Kushwaha * @pf_id: PF number 42719198e4eSPrabhakar Kushwaha * @vf_number: VF number 42819198e4eSPrabhakar Kushwaha * @vf_valid: VF valid or not. 42919198e4eSPrabhakar Kushwaha * 43019198e4eSPrabhakar Kushwaha * Return: Void. 431fe56b9e6SYuval Mintz */ 432fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 433fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 434fe56b9e6SYuval Mintz u8 pf_id, 435fe56b9e6SYuval Mintz u16 vf_number, 436fe56b9e6SYuval Mintz u8 vf_valid); 437fe56b9e6SYuval Mintz 438722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 439722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx); 440722003acSSudarsana Reddy Kalluru 441fe56b9e6SYuval Mintz #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 442fe56b9e6SYuval Mintz 443eb61c2d6SAlexander Lobakin int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 444eb61c2d6SAlexander Lobakin bool hw_init); 445666db486STomer Tayar 446fe56b9e6SYuval Mintz #endif 447