1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_INT_H 34fe56b9e6SYuval Mintz #define _QED_INT_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/slab.h> 38fe56b9e6SYuval Mintz #include "qed.h" 39fe56b9e6SYuval Mintz 40fe56b9e6SYuval Mintz /* Fields of IGU PF CONFIGRATION REGISTER */ 41fe56b9e6SYuval Mintz #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 42fe56b9e6SYuval Mintz #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 43fe56b9e6SYuval Mintz #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 44fe56b9e6SYuval Mintz #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 45fe56b9e6SYuval Mintz #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 46fe56b9e6SYuval Mintz #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 471408cc1fSYuval Mintz /* Fields of IGU VF CONFIGRATION REGISTER */ 481408cc1fSYuval Mintz #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 491408cc1fSYuval Mintz #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 501408cc1fSYuval Mintz #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 511408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 521408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 53fe56b9e6SYuval Mintz 54fe56b9e6SYuval Mintz /* Igu control commands 55fe56b9e6SYuval Mintz */ 56fe56b9e6SYuval Mintz enum igu_ctrl_cmd { 57fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_RD, 58fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_WR, 59fe56b9e6SYuval Mintz MAX_IGU_CTRL_CMD 60fe56b9e6SYuval Mintz }; 61fe56b9e6SYuval Mintz 62fe56b9e6SYuval Mintz /* Control register for the IGU command register 63fe56b9e6SYuval Mintz */ 64fe56b9e6SYuval Mintz struct igu_ctrl_reg { 65fe56b9e6SYuval Mintz u32 ctrl_data; 66fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 67fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_SHIFT 0 68fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 69fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 70fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_MASK 0x1 71fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_SHIFT 28 72fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 73fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_SHIFT 31 74fe56b9e6SYuval Mintz }; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz enum qed_coalescing_fsm { 77fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 78fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE 79fe56b9e6SYuval Mintz }; 80fe56b9e6SYuval Mintz 81fe56b9e6SYuval Mintz /** 82fe56b9e6SYuval Mintz * @brief qed_int_cau_conf_pi - configure cau for a given 83fe56b9e6SYuval Mintz * status block 84fe56b9e6SYuval Mintz * 85fe56b9e6SYuval Mintz * @param p_hwfn 86fe56b9e6SYuval Mintz * @param p_ptt 87fe56b9e6SYuval Mintz * @param igu_sb_id 88fe56b9e6SYuval Mintz * @param pi_index 89fe56b9e6SYuval Mintz * @param state 90fe56b9e6SYuval Mintz * @param timeset 91fe56b9e6SYuval Mintz */ 92fe56b9e6SYuval Mintz void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 93fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 94fe56b9e6SYuval Mintz u16 igu_sb_id, 95fe56b9e6SYuval Mintz u32 pi_index, 96fe56b9e6SYuval Mintz enum qed_coalescing_fsm coalescing_fsm, 97fe56b9e6SYuval Mintz u8 timeset); 98fe56b9e6SYuval Mintz 99fe56b9e6SYuval Mintz /** 100fe56b9e6SYuval Mintz * @brief qed_int_igu_enable_int - enable device interrupts 101fe56b9e6SYuval Mintz * 102fe56b9e6SYuval Mintz * @param p_hwfn 103fe56b9e6SYuval Mintz * @param p_ptt 104fe56b9e6SYuval Mintz * @param int_mode - interrupt mode to use 105fe56b9e6SYuval Mintz */ 106fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 107fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 108fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 109fe56b9e6SYuval Mintz 110fe56b9e6SYuval Mintz /** 111fe56b9e6SYuval Mintz * @brief qed_int_igu_disable_int - disable device interrupts 112fe56b9e6SYuval Mintz * 113fe56b9e6SYuval Mintz * @param p_hwfn 114fe56b9e6SYuval Mintz * @param p_ptt 115fe56b9e6SYuval Mintz */ 116fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 117fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 118fe56b9e6SYuval Mintz 119fe56b9e6SYuval Mintz /** 120fe56b9e6SYuval Mintz * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 121fe56b9e6SYuval Mintz * register from igu. 122fe56b9e6SYuval Mintz * 123fe56b9e6SYuval Mintz * @param p_hwfn 124fe56b9e6SYuval Mintz * 125fe56b9e6SYuval Mintz * @return u64 126fe56b9e6SYuval Mintz */ 127fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 128fe56b9e6SYuval Mintz 129fe56b9e6SYuval Mintz #define QED_SP_SB_ID 0xffff 130fe56b9e6SYuval Mintz /** 131fe56b9e6SYuval Mintz * @brief qed_int_sb_init - Initializes the sb_info structure. 132fe56b9e6SYuval Mintz * 133fe56b9e6SYuval Mintz * once the structure is initialized it can be passed to sb related functions. 134fe56b9e6SYuval Mintz * 135fe56b9e6SYuval Mintz * @param p_hwfn 136fe56b9e6SYuval Mintz * @param p_ptt 137fe56b9e6SYuval Mintz * @param sb_info points to an uninitialized (but 138fe56b9e6SYuval Mintz * allocated) sb_info structure 139fe56b9e6SYuval Mintz * @param sb_virt_addr 140fe56b9e6SYuval Mintz * @param sb_phy_addr 141fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 142fe56b9e6SYuval Mintz * should use QED_SP_SB_ID for SP Status block 143fe56b9e6SYuval Mintz * 144fe56b9e6SYuval Mintz * @return int 145fe56b9e6SYuval Mintz */ 146fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 147fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 148fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 149fe56b9e6SYuval Mintz void *sb_virt_addr, 150fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 151fe56b9e6SYuval Mintz u16 sb_id); 152fe56b9e6SYuval Mintz /** 153fe56b9e6SYuval Mintz * @brief qed_int_sb_setup - Setup the sb. 154fe56b9e6SYuval Mintz * 155fe56b9e6SYuval Mintz * @param p_hwfn 156fe56b9e6SYuval Mintz * @param p_ptt 157fe56b9e6SYuval Mintz * @param sb_info initialized sb_info structure 158fe56b9e6SYuval Mintz */ 159fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 160fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 161fe56b9e6SYuval Mintz struct qed_sb_info *sb_info); 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz /** 164fe56b9e6SYuval Mintz * @brief qed_int_sb_release - releases the sb_info structure. 165fe56b9e6SYuval Mintz * 166fe56b9e6SYuval Mintz * once the structure is released, it's memory can be freed 167fe56b9e6SYuval Mintz * 168fe56b9e6SYuval Mintz * @param p_hwfn 169fe56b9e6SYuval Mintz * @param sb_info points to an allocated sb_info structure 170fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 171fe56b9e6SYuval Mintz * should never be equal to QED_SP_SB_ID 172fe56b9e6SYuval Mintz * (SP Status block) 173fe56b9e6SYuval Mintz * 174fe56b9e6SYuval Mintz * @return int 175fe56b9e6SYuval Mintz */ 176fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 177fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 178fe56b9e6SYuval Mintz u16 sb_id); 179fe56b9e6SYuval Mintz 180fe56b9e6SYuval Mintz /** 181fe56b9e6SYuval Mintz * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 182fe56b9e6SYuval Mintz * default status block. 183fe56b9e6SYuval Mintz * 184fe56b9e6SYuval Mintz * @param p_hwfn - pointer to hwfn 185fe56b9e6SYuval Mintz * 186fe56b9e6SYuval Mintz */ 187fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie); 188fe56b9e6SYuval Mintz 189fe56b9e6SYuval Mintz /** 190fe56b9e6SYuval Mintz * @brief qed_int_get_num_sbs - get the number of status 191fe56b9e6SYuval Mintz * blocks configured for this funciton in the igu. 192fe56b9e6SYuval Mintz * 193fe56b9e6SYuval Mintz * @param p_hwfn 1944ac801b7SYuval Mintz * @param p_sb_cnt_info 195fe56b9e6SYuval Mintz * 196fe56b9e6SYuval Mintz * @return int - number of status blocks configured 197fe56b9e6SYuval Mintz */ 1984ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 1994ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info); 200fe56b9e6SYuval Mintz 201fe56b9e6SYuval Mintz /** 2028f16bc97SSudarsana Kalluru * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR 2038f16bc97SSudarsana Kalluru * release. The API need to be called after releasing all slowpath IRQs 2048f16bc97SSudarsana Kalluru * of the device. 205fe56b9e6SYuval Mintz * 2068f16bc97SSudarsana Kalluru * @param cdev 2078f16bc97SSudarsana Kalluru * 208fe56b9e6SYuval Mintz */ 2098f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev); 210fe56b9e6SYuval Mintz 211fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_TIMER_RES 0 212fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_TIMER_RES 0 213fe56b9e6SYuval Mintz 214fe56b9e6SYuval Mintz #define QED_SB_ATT_IDX 0x0001 215fe56b9e6SYuval Mintz #define QED_SB_EVENT_MASK 0x0003 216fe56b9e6SYuval Mintz 217fe56b9e6SYuval Mintz #define SB_ALIGNED_SIZE(p_hwfn) \ 218fe56b9e6SYuval Mintz ALIGNED_TYPE_SIZE(struct status_block, p_hwfn) 219fe56b9e6SYuval Mintz 220fe56b9e6SYuval Mintz struct qed_igu_block { 221fe56b9e6SYuval Mintz u8 status; 222fe56b9e6SYuval Mintz #define QED_IGU_STATUS_FREE 0x01 223fe56b9e6SYuval Mintz #define QED_IGU_STATUS_VALID 0x02 224fe56b9e6SYuval Mintz #define QED_IGU_STATUS_PF 0x04 225fe56b9e6SYuval Mintz 226fe56b9e6SYuval Mintz u8 vector_number; 227fe56b9e6SYuval Mintz u8 function_id; 228fe56b9e6SYuval Mintz u8 is_pf; 229fe56b9e6SYuval Mintz }; 230fe56b9e6SYuval Mintz 231fe56b9e6SYuval Mintz struct qed_igu_map { 232fe56b9e6SYuval Mintz struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH]; 233fe56b9e6SYuval Mintz }; 234fe56b9e6SYuval Mintz 235fe56b9e6SYuval Mintz struct qed_igu_info { 236fe56b9e6SYuval Mintz struct qed_igu_map igu_map; 237fe56b9e6SYuval Mintz u16 igu_dsb_id; 238fe56b9e6SYuval Mintz u16 igu_base_sb; 239fe56b9e6SYuval Mintz u16 igu_base_sb_iov; 240fe56b9e6SYuval Mintz u16 igu_sb_cnt; 241fe56b9e6SYuval Mintz u16 igu_sb_cnt_iov; 242fe56b9e6SYuval Mintz u16 free_blks; 243fe56b9e6SYuval Mintz }; 244fe56b9e6SYuval Mintz 245fe56b9e6SYuval Mintz /* TODO Names of function may change... */ 246fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 247fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 248fe56b9e6SYuval Mintz bool b_set, 249fe56b9e6SYuval Mintz bool b_slowpath); 250fe56b9e6SYuval Mintz 251fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 252fe56b9e6SYuval Mintz 253fe56b9e6SYuval Mintz /** 254fe56b9e6SYuval Mintz * @brief qed_int_igu_read_cam - Reads the IGU CAM. 255fe56b9e6SYuval Mintz * This function needs to be called during hardware 256fe56b9e6SYuval Mintz * prepare. It reads the info from igu cam to know which 257fe56b9e6SYuval Mintz * status block is the default / base status block etc. 258fe56b9e6SYuval Mintz * 259fe56b9e6SYuval Mintz * @param p_hwfn 260fe56b9e6SYuval Mintz * @param p_ptt 261fe56b9e6SYuval Mintz * 262fe56b9e6SYuval Mintz * @return int 263fe56b9e6SYuval Mintz */ 264fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 265fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 266fe56b9e6SYuval Mintz 267fe56b9e6SYuval Mintz typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 268fe56b9e6SYuval Mintz void *cookie); 269fe56b9e6SYuval Mintz /** 270fe56b9e6SYuval Mintz * @brief qed_int_register_cb - Register callback func for 271fe56b9e6SYuval Mintz * slowhwfn statusblock. 272fe56b9e6SYuval Mintz * 273fe56b9e6SYuval Mintz * Every protocol that uses the slowhwfn status block 274fe56b9e6SYuval Mintz * should register a callback function that will be called 275fe56b9e6SYuval Mintz * once there is an update of the sp status block. 276fe56b9e6SYuval Mintz * 277fe56b9e6SYuval Mintz * @param p_hwfn 278fe56b9e6SYuval Mintz * @param comp_cb - function to be called when there is an 279fe56b9e6SYuval Mintz * interrupt on the sp sb 280fe56b9e6SYuval Mintz * 281fe56b9e6SYuval Mintz * @param cookie - passed to the callback function 282fe56b9e6SYuval Mintz * @param sb_idx - OUT parameter which gives the chosen index 283fe56b9e6SYuval Mintz * for this protocol. 284fe56b9e6SYuval Mintz * @param p_fw_cons - pointer to the actual address of the 285fe56b9e6SYuval Mintz * consumer for this protocol. 286fe56b9e6SYuval Mintz * 287fe56b9e6SYuval Mintz * @return int 288fe56b9e6SYuval Mintz */ 289fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 290fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 291fe56b9e6SYuval Mintz void *cookie, 292fe56b9e6SYuval Mintz u8 *sb_idx, 293fe56b9e6SYuval Mintz __le16 **p_fw_cons); 294fe56b9e6SYuval Mintz 295fe56b9e6SYuval Mintz /** 296fe56b9e6SYuval Mintz * @brief qed_int_unregister_cb - Unregisters callback 297fe56b9e6SYuval Mintz * function from sp sb. 298fe56b9e6SYuval Mintz * Partner of qed_int_register_cb -> should be called 299fe56b9e6SYuval Mintz * when no longer required. 300fe56b9e6SYuval Mintz * 301fe56b9e6SYuval Mintz * @param p_hwfn 302fe56b9e6SYuval Mintz * @param pi 303fe56b9e6SYuval Mintz * 304fe56b9e6SYuval Mintz * @return int 305fe56b9e6SYuval Mintz */ 306fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 307fe56b9e6SYuval Mintz u8 pi); 308fe56b9e6SYuval Mintz 309fe56b9e6SYuval Mintz /** 310fe56b9e6SYuval Mintz * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 311fe56b9e6SYuval Mintz * 312fe56b9e6SYuval Mintz * @param p_hwfn 313fe56b9e6SYuval Mintz * 314fe56b9e6SYuval Mintz * @return u16 315fe56b9e6SYuval Mintz */ 316fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 317fe56b9e6SYuval Mintz 318fe56b9e6SYuval Mintz /** 319fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 320fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 321fe56b9e6SYuval Mintz * 322fe56b9e6SYuval Mintz * @param p_hwfn 323fe56b9e6SYuval Mintz * @param p_ptt 324fe56b9e6SYuval Mintz * @param sb_id - igu status block id 325fe56b9e6SYuval Mintz * @param opaque - opaque fid of the sb owner. 326b2b897ebSYuval Mintz * @param b_set - set(1) / clear(0) 327fe56b9e6SYuval Mintz */ 328fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 329fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 330fe56b9e6SYuval Mintz u32 sb_id, 331fe56b9e6SYuval Mintz u16 opaque, 332fe56b9e6SYuval Mintz bool b_set); 333fe56b9e6SYuval Mintz 334fe56b9e6SYuval Mintz /** 335fe56b9e6SYuval Mintz * @brief qed_int_cau_conf - configure cau for a given status 336fe56b9e6SYuval Mintz * block 337fe56b9e6SYuval Mintz * 338fe56b9e6SYuval Mintz * @param p_hwfn 339fe56b9e6SYuval Mintz * @param ptt 340fe56b9e6SYuval Mintz * @param sb_phys 341fe56b9e6SYuval Mintz * @param igu_sb_id 342fe56b9e6SYuval Mintz * @param vf_number 343fe56b9e6SYuval Mintz * @param vf_valid 344fe56b9e6SYuval Mintz */ 345fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 346fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 347fe56b9e6SYuval Mintz dma_addr_t sb_phys, 348fe56b9e6SYuval Mintz u16 igu_sb_id, 349fe56b9e6SYuval Mintz u16 vf_number, 350fe56b9e6SYuval Mintz u8 vf_valid); 351fe56b9e6SYuval Mintz 352fe56b9e6SYuval Mintz /** 353fe56b9e6SYuval Mintz * @brief qed_int_alloc 354fe56b9e6SYuval Mintz * 355fe56b9e6SYuval Mintz * @param p_hwfn 356fe56b9e6SYuval Mintz * @param p_ptt 357fe56b9e6SYuval Mintz * 358fe56b9e6SYuval Mintz * @return int 359fe56b9e6SYuval Mintz */ 360fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 361fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 362fe56b9e6SYuval Mintz 363fe56b9e6SYuval Mintz /** 364fe56b9e6SYuval Mintz * @brief qed_int_free 365fe56b9e6SYuval Mintz * 366fe56b9e6SYuval Mintz * @param p_hwfn 367fe56b9e6SYuval Mintz */ 368fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn); 369fe56b9e6SYuval Mintz 370fe56b9e6SYuval Mintz /** 371fe56b9e6SYuval Mintz * @brief qed_int_setup 372fe56b9e6SYuval Mintz * 373fe56b9e6SYuval Mintz * @param p_hwfn 374fe56b9e6SYuval Mintz * @param p_ptt 375fe56b9e6SYuval Mintz */ 376fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 377fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 378fe56b9e6SYuval Mintz 379fe56b9e6SYuval Mintz /** 3801408cc1fSYuval Mintz * @brief - Returns an Rx queue index appropriate for usage with given SB. 3811408cc1fSYuval Mintz * 3821408cc1fSYuval Mintz * @param p_hwfn 3831408cc1fSYuval Mintz * @param sb_id - absolute index of SB 3841408cc1fSYuval Mintz * 3851408cc1fSYuval Mintz * @return index of Rx queue 3861408cc1fSYuval Mintz */ 3871408cc1fSYuval Mintz u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id); 3881408cc1fSYuval Mintz 3891408cc1fSYuval Mintz /** 390fe56b9e6SYuval Mintz * @brief - Enable Interrupt & Attention for hw function 391fe56b9e6SYuval Mintz * 392fe56b9e6SYuval Mintz * @param p_hwfn 393fe56b9e6SYuval Mintz * @param p_ptt 394fe56b9e6SYuval Mintz * @param int_mode 3958f16bc97SSudarsana Kalluru * 3968f16bc97SSudarsana Kalluru * @return int 397fe56b9e6SYuval Mintz */ 3988f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 399fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 400fe56b9e6SYuval Mintz 401fe56b9e6SYuval Mintz /** 402fe56b9e6SYuval Mintz * @brief - Initialize CAU status block entry 403fe56b9e6SYuval Mintz * 404fe56b9e6SYuval Mintz * @param p_hwfn 405fe56b9e6SYuval Mintz * @param p_sb_entry 406fe56b9e6SYuval Mintz * @param pf_id 407fe56b9e6SYuval Mintz * @param vf_number 408fe56b9e6SYuval Mintz * @param vf_valid 409fe56b9e6SYuval Mintz */ 410fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 411fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 412fe56b9e6SYuval Mintz u8 pf_id, 413fe56b9e6SYuval Mintz u16 vf_number, 414fe56b9e6SYuval Mintz u8 vf_valid); 415fe56b9e6SYuval Mintz 416722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 417722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx); 418722003acSSudarsana Reddy Kalluru 419fe56b9e6SYuval Mintz #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 420fe56b9e6SYuval Mintz 421fe56b9e6SYuval Mintz #endif 422