11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #ifndef _QED_INT_H 8fe56b9e6SYuval Mintz #define _QED_INT_H 9fe56b9e6SYuval Mintz 10fe56b9e6SYuval Mintz #include <linux/types.h> 11fe56b9e6SYuval Mintz #include <linux/slab.h> 12fe56b9e6SYuval Mintz #include "qed.h" 13fe56b9e6SYuval Mintz 14c199ce4fSGeert Uytterhoeven /* Fields of IGU PF CONFIGURATION REGISTER */ 15fe56b9e6SYuval Mintz #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 16fe56b9e6SYuval Mintz #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 17fe56b9e6SYuval Mintz #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 18fe56b9e6SYuval Mintz #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 19fe56b9e6SYuval Mintz #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 20fe56b9e6SYuval Mintz #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 21c199ce4fSGeert Uytterhoeven /* Fields of IGU VF CONFIGURATION REGISTER */ 221408cc1fSYuval Mintz #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 231408cc1fSYuval Mintz #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 241408cc1fSYuval Mintz #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 251408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 261408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 27fe56b9e6SYuval Mintz 28fe56b9e6SYuval Mintz /* Igu control commands 29fe56b9e6SYuval Mintz */ 30fe56b9e6SYuval Mintz enum igu_ctrl_cmd { 31fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_RD, 32fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_WR, 33fe56b9e6SYuval Mintz MAX_IGU_CTRL_CMD 34fe56b9e6SYuval Mintz }; 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz /* Control register for the IGU command register 37fe56b9e6SYuval Mintz */ 38fe56b9e6SYuval Mintz struct igu_ctrl_reg { 39fe56b9e6SYuval Mintz u32 ctrl_data; 40fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 41fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_SHIFT 0 42fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 43fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 44fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_MASK 0x1 45fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_SHIFT 28 46fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 47fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_SHIFT 31 48fe56b9e6SYuval Mintz }; 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz enum qed_coalescing_fsm { 51fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 52fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE 53fe56b9e6SYuval Mintz }; 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz /** 56fe56b9e6SYuval Mintz * @brief qed_int_igu_enable_int - enable device interrupts 57fe56b9e6SYuval Mintz * 58fe56b9e6SYuval Mintz * @param p_hwfn 59fe56b9e6SYuval Mintz * @param p_ptt 60fe56b9e6SYuval Mintz * @param int_mode - interrupt mode to use 61fe56b9e6SYuval Mintz */ 62fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 63fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 64fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz /** 67fe56b9e6SYuval Mintz * @brief qed_int_igu_disable_int - disable device interrupts 68fe56b9e6SYuval Mintz * 69fe56b9e6SYuval Mintz * @param p_hwfn 70fe56b9e6SYuval Mintz * @param p_ptt 71fe56b9e6SYuval Mintz */ 72fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 73fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 74fe56b9e6SYuval Mintz 75fe56b9e6SYuval Mintz /** 76fe56b9e6SYuval Mintz * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 77fe56b9e6SYuval Mintz * register from igu. 78fe56b9e6SYuval Mintz * 79fe56b9e6SYuval Mintz * @param p_hwfn 80fe56b9e6SYuval Mintz * 81fe56b9e6SYuval Mintz * @return u64 82fe56b9e6SYuval Mintz */ 83fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 84fe56b9e6SYuval Mintz 85fe56b9e6SYuval Mintz #define QED_SP_SB_ID 0xffff 86fe56b9e6SYuval Mintz /** 87fe56b9e6SYuval Mintz * @brief qed_int_sb_init - Initializes the sb_info structure. 88fe56b9e6SYuval Mintz * 89fe56b9e6SYuval Mintz * once the structure is initialized it can be passed to sb related functions. 90fe56b9e6SYuval Mintz * 91fe56b9e6SYuval Mintz * @param p_hwfn 92fe56b9e6SYuval Mintz * @param p_ptt 93fe56b9e6SYuval Mintz * @param sb_info points to an uninitialized (but 94fe56b9e6SYuval Mintz * allocated) sb_info structure 95fe56b9e6SYuval Mintz * @param sb_virt_addr 96fe56b9e6SYuval Mintz * @param sb_phy_addr 97fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 98fe56b9e6SYuval Mintz * should use QED_SP_SB_ID for SP Status block 99fe56b9e6SYuval Mintz * 100fe56b9e6SYuval Mintz * @return int 101fe56b9e6SYuval Mintz */ 102fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 103fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 104fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 105fe56b9e6SYuval Mintz void *sb_virt_addr, 106fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 107fe56b9e6SYuval Mintz u16 sb_id); 108fe56b9e6SYuval Mintz /** 109fe56b9e6SYuval Mintz * @brief qed_int_sb_setup - Setup the sb. 110fe56b9e6SYuval Mintz * 111fe56b9e6SYuval Mintz * @param p_hwfn 112fe56b9e6SYuval Mintz * @param p_ptt 113fe56b9e6SYuval Mintz * @param sb_info initialized sb_info structure 114fe56b9e6SYuval Mintz */ 115fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 116fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 117fe56b9e6SYuval Mintz struct qed_sb_info *sb_info); 118fe56b9e6SYuval Mintz 119fe56b9e6SYuval Mintz /** 120fe56b9e6SYuval Mintz * @brief qed_int_sb_release - releases the sb_info structure. 121fe56b9e6SYuval Mintz * 122fe56b9e6SYuval Mintz * once the structure is released, it's memory can be freed 123fe56b9e6SYuval Mintz * 124fe56b9e6SYuval Mintz * @param p_hwfn 125fe56b9e6SYuval Mintz * @param sb_info points to an allocated sb_info structure 126fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 127fe56b9e6SYuval Mintz * should never be equal to QED_SP_SB_ID 128fe56b9e6SYuval Mintz * (SP Status block) 129fe56b9e6SYuval Mintz * 130fe56b9e6SYuval Mintz * @return int 131fe56b9e6SYuval Mintz */ 132fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 133fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 134fe56b9e6SYuval Mintz u16 sb_id); 135fe56b9e6SYuval Mintz 136fe56b9e6SYuval Mintz /** 137fe56b9e6SYuval Mintz * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 138fe56b9e6SYuval Mintz * default status block. 139fe56b9e6SYuval Mintz * 140fe56b9e6SYuval Mintz * @param p_hwfn - pointer to hwfn 141fe56b9e6SYuval Mintz * 142fe56b9e6SYuval Mintz */ 143b5f0a3bfSAllen Pais void qed_int_sp_dpc(struct tasklet_struct *t); 144fe56b9e6SYuval Mintz 145fe56b9e6SYuval Mintz /** 146fe56b9e6SYuval Mintz * @brief qed_int_get_num_sbs - get the number of status 147fe56b9e6SYuval Mintz * blocks configured for this funciton in the igu. 148fe56b9e6SYuval Mintz * 149fe56b9e6SYuval Mintz * @param p_hwfn 1504ac801b7SYuval Mintz * @param p_sb_cnt_info 151fe56b9e6SYuval Mintz * 152fe56b9e6SYuval Mintz * @return int - number of status blocks configured 153fe56b9e6SYuval Mintz */ 1544ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 1554ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info); 156fe56b9e6SYuval Mintz 157fe56b9e6SYuval Mintz /** 1588f16bc97SSudarsana Kalluru * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR 1598f16bc97SSudarsana Kalluru * release. The API need to be called after releasing all slowpath IRQs 1608f16bc97SSudarsana Kalluru * of the device. 161fe56b9e6SYuval Mintz * 1628f16bc97SSudarsana Kalluru * @param cdev 1638f16bc97SSudarsana Kalluru * 164fe56b9e6SYuval Mintz */ 1658f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev); 166fe56b9e6SYuval Mintz 167a1b469b8SAriel Elior /** 168936c7ba4SIgor Russkikh * @brief qed_int_attn_clr_enable - sets whether the general behavior is 169936c7ba4SIgor Russkikh * preventing attentions from being reasserted, or following the 170936c7ba4SIgor Russkikh * attributes of the specific attention. 171936c7ba4SIgor Russkikh * 172936c7ba4SIgor Russkikh * @param cdev 173936c7ba4SIgor Russkikh * @param clr_enable 174936c7ba4SIgor Russkikh * 175936c7ba4SIgor Russkikh */ 176936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable); 177936c7ba4SIgor Russkikh 178936c7ba4SIgor Russkikh /** 179a1b469b8SAriel Elior * @brief - Doorbell Recovery handler. 1809ac6bb14SDenis Bolotin * Run doorbell recovery in case of PF overflow (and flush DORQ if 1819ac6bb14SDenis Bolotin * needed). 182a1b469b8SAriel Elior * 183a1b469b8SAriel Elior * @param p_hwfn 184a1b469b8SAriel Elior * @param p_ptt 185a1b469b8SAriel Elior */ 186a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 187a1b469b8SAriel Elior 188fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_TIMER_RES 0 189fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_TIMER_RES 0 190fe56b9e6SYuval Mintz 191fe56b9e6SYuval Mintz #define QED_SB_ATT_IDX 0x0001 192fe56b9e6SYuval Mintz #define QED_SB_EVENT_MASK 0x0003 193fe56b9e6SYuval Mintz 194fe56b9e6SYuval Mintz #define SB_ALIGNED_SIZE(p_hwfn) \ 19521dd79e8STomer Tayar ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn) 196fe56b9e6SYuval Mintz 197d749dd0dSMintz, Yuval #define QED_SB_INVALID_IDX 0xffff 198d749dd0dSMintz, Yuval 199fe56b9e6SYuval Mintz struct qed_igu_block { 200fe56b9e6SYuval Mintz u8 status; 201fe56b9e6SYuval Mintz #define QED_IGU_STATUS_FREE 0x01 202fe56b9e6SYuval Mintz #define QED_IGU_STATUS_VALID 0x02 203fe56b9e6SYuval Mintz #define QED_IGU_STATUS_PF 0x04 204d749dd0dSMintz, Yuval #define QED_IGU_STATUS_DSB 0x08 205fe56b9e6SYuval Mintz 206fe56b9e6SYuval Mintz u8 vector_number; 207fe56b9e6SYuval Mintz u8 function_id; 208fe56b9e6SYuval Mintz u8 is_pf; 2091ac72433SMintz, Yuval 2101ac72433SMintz, Yuval /* Index inside IGU [meant for back reference] */ 2111ac72433SMintz, Yuval u16 igu_sb_id; 21250a20714SMintz, Yuval 21350a20714SMintz, Yuval struct qed_sb_info *sb_info; 214fe56b9e6SYuval Mintz }; 215fe56b9e6SYuval Mintz 216fe56b9e6SYuval Mintz struct qed_igu_info { 217d749dd0dSMintz, Yuval struct qed_igu_block entry[MAX_TOT_SB_PER_PATH]; 218fe56b9e6SYuval Mintz u16 igu_dsb_id; 219726fdbe9SMintz, Yuval 220726fdbe9SMintz, Yuval struct qed_sb_cnt_info usage; 221726fdbe9SMintz, Yuval 222ebbdcc66SMintz, Yuval bool b_allow_pf_vf_change; 223fe56b9e6SYuval Mintz }; 224fe56b9e6SYuval Mintz 22550a20714SMintz, Yuval /** 226ebbdcc66SMintz, Yuval * @brief - Make sure the IGU CAM reflects the resources provided by MFW 227ebbdcc66SMintz, Yuval * 228ebbdcc66SMintz, Yuval * @param p_hwfn 229ebbdcc66SMintz, Yuval * @param p_ptt 230ebbdcc66SMintz, Yuval */ 231ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 232ebbdcc66SMintz, Yuval 233ebbdcc66SMintz, Yuval /** 23450a20714SMintz, Yuval * @brief Translate the weakly-defined client sb-id into an IGU sb-id 23550a20714SMintz, Yuval * 23650a20714SMintz, Yuval * @param p_hwfn 23750a20714SMintz, Yuval * @param sb_id - user provided sb_id 23850a20714SMintz, Yuval * 23950a20714SMintz, Yuval * @return an index inside IGU CAM where the SB resides 24050a20714SMintz, Yuval */ 24150a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id); 24250a20714SMintz, Yuval 24309b6b147SMintz, Yuval /** 24409b6b147SMintz, Yuval * @brief return a pointer to an unused valid SB 24509b6b147SMintz, Yuval * 24609b6b147SMintz, Yuval * @param p_hwfn 24709b6b147SMintz, Yuval * @param b_is_pf - true iff we want a SB belonging to a PF 24809b6b147SMintz, Yuval * 24909b6b147SMintz, Yuval * @return point to an igu_block, NULL if none is available 25009b6b147SMintz, Yuval */ 25109b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, 25209b6b147SMintz, Yuval bool b_is_pf); 25309b6b147SMintz, Yuval 254fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 255fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 256fe56b9e6SYuval Mintz bool b_set, 257fe56b9e6SYuval Mintz bool b_slowpath); 258fe56b9e6SYuval Mintz 259fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 260fe56b9e6SYuval Mintz 261fe56b9e6SYuval Mintz /** 262fe56b9e6SYuval Mintz * @brief qed_int_igu_read_cam - Reads the IGU CAM. 263fe56b9e6SYuval Mintz * This function needs to be called during hardware 264fe56b9e6SYuval Mintz * prepare. It reads the info from igu cam to know which 265fe56b9e6SYuval Mintz * status block is the default / base status block etc. 266fe56b9e6SYuval Mintz * 267fe56b9e6SYuval Mintz * @param p_hwfn 268fe56b9e6SYuval Mintz * @param p_ptt 269fe56b9e6SYuval Mintz * 270fe56b9e6SYuval Mintz * @return int 271fe56b9e6SYuval Mintz */ 272fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 273fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 274fe56b9e6SYuval Mintz 275fe56b9e6SYuval Mintz typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 276fe56b9e6SYuval Mintz void *cookie); 277fe56b9e6SYuval Mintz /** 278fe56b9e6SYuval Mintz * @brief qed_int_register_cb - Register callback func for 279fe56b9e6SYuval Mintz * slowhwfn statusblock. 280fe56b9e6SYuval Mintz * 281fe56b9e6SYuval Mintz * Every protocol that uses the slowhwfn status block 282fe56b9e6SYuval Mintz * should register a callback function that will be called 283fe56b9e6SYuval Mintz * once there is an update of the sp status block. 284fe56b9e6SYuval Mintz * 285fe56b9e6SYuval Mintz * @param p_hwfn 286fe56b9e6SYuval Mintz * @param comp_cb - function to be called when there is an 287fe56b9e6SYuval Mintz * interrupt on the sp sb 288fe56b9e6SYuval Mintz * 289fe56b9e6SYuval Mintz * @param cookie - passed to the callback function 290fe56b9e6SYuval Mintz * @param sb_idx - OUT parameter which gives the chosen index 291fe56b9e6SYuval Mintz * for this protocol. 292fe56b9e6SYuval Mintz * @param p_fw_cons - pointer to the actual address of the 293fe56b9e6SYuval Mintz * consumer for this protocol. 294fe56b9e6SYuval Mintz * 295fe56b9e6SYuval Mintz * @return int 296fe56b9e6SYuval Mintz */ 297fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 298fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 299fe56b9e6SYuval Mintz void *cookie, 300fe56b9e6SYuval Mintz u8 *sb_idx, 301fe56b9e6SYuval Mintz __le16 **p_fw_cons); 302fe56b9e6SYuval Mintz 303fe56b9e6SYuval Mintz /** 304fe56b9e6SYuval Mintz * @brief qed_int_unregister_cb - Unregisters callback 305fe56b9e6SYuval Mintz * function from sp sb. 306fe56b9e6SYuval Mintz * Partner of qed_int_register_cb -> should be called 307fe56b9e6SYuval Mintz * when no longer required. 308fe56b9e6SYuval Mintz * 309fe56b9e6SYuval Mintz * @param p_hwfn 310fe56b9e6SYuval Mintz * @param pi 311fe56b9e6SYuval Mintz * 312fe56b9e6SYuval Mintz * @return int 313fe56b9e6SYuval Mintz */ 314fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 315fe56b9e6SYuval Mintz u8 pi); 316fe56b9e6SYuval Mintz 317fe56b9e6SYuval Mintz /** 318fe56b9e6SYuval Mintz * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 319fe56b9e6SYuval Mintz * 320fe56b9e6SYuval Mintz * @param p_hwfn 321fe56b9e6SYuval Mintz * 322fe56b9e6SYuval Mintz * @return u16 323fe56b9e6SYuval Mintz */ 324fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 325fe56b9e6SYuval Mintz 326fe56b9e6SYuval Mintz /** 327fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 328fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 329fe56b9e6SYuval Mintz * 330fe56b9e6SYuval Mintz * @param p_hwfn 331fe56b9e6SYuval Mintz * @param p_ptt 332d031548eSMintz, Yuval * @param igu_sb_id - igu status block id 333fe56b9e6SYuval Mintz * @param opaque - opaque fid of the sb owner. 334b2b897ebSYuval Mintz * @param b_set - set(1) / clear(0) 335fe56b9e6SYuval Mintz */ 336fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 337fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 338d031548eSMintz, Yuval u16 igu_sb_id, 339fe56b9e6SYuval Mintz u16 opaque, 340fe56b9e6SYuval Mintz bool b_set); 341fe56b9e6SYuval Mintz 342fe56b9e6SYuval Mintz /** 343fe56b9e6SYuval Mintz * @brief qed_int_cau_conf - configure cau for a given status 344fe56b9e6SYuval Mintz * block 345fe56b9e6SYuval Mintz * 346fe56b9e6SYuval Mintz * @param p_hwfn 347fe56b9e6SYuval Mintz * @param ptt 348fe56b9e6SYuval Mintz * @param sb_phys 349fe56b9e6SYuval Mintz * @param igu_sb_id 350fe56b9e6SYuval Mintz * @param vf_number 351fe56b9e6SYuval Mintz * @param vf_valid 352fe56b9e6SYuval Mintz */ 353fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 354fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 355fe56b9e6SYuval Mintz dma_addr_t sb_phys, 356fe56b9e6SYuval Mintz u16 igu_sb_id, 357fe56b9e6SYuval Mintz u16 vf_number, 358fe56b9e6SYuval Mintz u8 vf_valid); 359fe56b9e6SYuval Mintz 360fe56b9e6SYuval Mintz /** 361fe56b9e6SYuval Mintz * @brief qed_int_alloc 362fe56b9e6SYuval Mintz * 363fe56b9e6SYuval Mintz * @param p_hwfn 364fe56b9e6SYuval Mintz * @param p_ptt 365fe56b9e6SYuval Mintz * 366fe56b9e6SYuval Mintz * @return int 367fe56b9e6SYuval Mintz */ 368fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 369fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 370fe56b9e6SYuval Mintz 371fe56b9e6SYuval Mintz /** 372fe56b9e6SYuval Mintz * @brief qed_int_free 373fe56b9e6SYuval Mintz * 374fe56b9e6SYuval Mintz * @param p_hwfn 375fe56b9e6SYuval Mintz */ 376fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn); 377fe56b9e6SYuval Mintz 378fe56b9e6SYuval Mintz /** 379fe56b9e6SYuval Mintz * @brief qed_int_setup 380fe56b9e6SYuval Mintz * 381fe56b9e6SYuval Mintz * @param p_hwfn 382fe56b9e6SYuval Mintz * @param p_ptt 383fe56b9e6SYuval Mintz */ 384fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 385fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 386fe56b9e6SYuval Mintz 387fe56b9e6SYuval Mintz /** 388fe56b9e6SYuval Mintz * @brief - Enable Interrupt & Attention for hw function 389fe56b9e6SYuval Mintz * 390fe56b9e6SYuval Mintz * @param p_hwfn 391fe56b9e6SYuval Mintz * @param p_ptt 392fe56b9e6SYuval Mintz * @param int_mode 3938f16bc97SSudarsana Kalluru * 3948f16bc97SSudarsana Kalluru * @return int 395fe56b9e6SYuval Mintz */ 3968f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 397fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 398fe56b9e6SYuval Mintz 399fe56b9e6SYuval Mintz /** 400fe56b9e6SYuval Mintz * @brief - Initialize CAU status block entry 401fe56b9e6SYuval Mintz * 402fe56b9e6SYuval Mintz * @param p_hwfn 403fe56b9e6SYuval Mintz * @param p_sb_entry 404fe56b9e6SYuval Mintz * @param pf_id 405fe56b9e6SYuval Mintz * @param vf_number 406fe56b9e6SYuval Mintz * @param vf_valid 407fe56b9e6SYuval Mintz */ 408fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 409fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 410fe56b9e6SYuval Mintz u8 pf_id, 411fe56b9e6SYuval Mintz u16 vf_number, 412fe56b9e6SYuval Mintz u8 vf_valid); 413fe56b9e6SYuval Mintz 414722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 415722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx); 416722003acSSudarsana Reddy Kalluru 417fe56b9e6SYuval Mintz #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 418fe56b9e6SYuval Mintz 419eb61c2d6SAlexander Lobakin int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 420eb61c2d6SAlexander Lobakin bool hw_init); 421666db486STomer Tayar 422fe56b9e6SYuval Mintz #endif 423