1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_INT_H 34fe56b9e6SYuval Mintz #define _QED_INT_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/slab.h> 38fe56b9e6SYuval Mintz #include "qed.h" 39fe56b9e6SYuval Mintz 40fe56b9e6SYuval Mintz /* Fields of IGU PF CONFIGRATION REGISTER */ 41fe56b9e6SYuval Mintz #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 42fe56b9e6SYuval Mintz #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 43fe56b9e6SYuval Mintz #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 44fe56b9e6SYuval Mintz #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 45fe56b9e6SYuval Mintz #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 46fe56b9e6SYuval Mintz #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 471408cc1fSYuval Mintz /* Fields of IGU VF CONFIGRATION REGISTER */ 481408cc1fSYuval Mintz #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 491408cc1fSYuval Mintz #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 501408cc1fSYuval Mintz #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 511408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 521408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 53fe56b9e6SYuval Mintz 54fe56b9e6SYuval Mintz /* Igu control commands 55fe56b9e6SYuval Mintz */ 56fe56b9e6SYuval Mintz enum igu_ctrl_cmd { 57fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_RD, 58fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_WR, 59fe56b9e6SYuval Mintz MAX_IGU_CTRL_CMD 60fe56b9e6SYuval Mintz }; 61fe56b9e6SYuval Mintz 62fe56b9e6SYuval Mintz /* Control register for the IGU command register 63fe56b9e6SYuval Mintz */ 64fe56b9e6SYuval Mintz struct igu_ctrl_reg { 65fe56b9e6SYuval Mintz u32 ctrl_data; 66fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 67fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_SHIFT 0 68fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 69fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 70fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_MASK 0x1 71fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_SHIFT 28 72fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 73fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_SHIFT 31 74fe56b9e6SYuval Mintz }; 75fe56b9e6SYuval Mintz 76fe56b9e6SYuval Mintz enum qed_coalescing_fsm { 77fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 78fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE 79fe56b9e6SYuval Mintz }; 80fe56b9e6SYuval Mintz 81fe56b9e6SYuval Mintz /** 82fe56b9e6SYuval Mintz * @brief qed_int_igu_enable_int - enable device interrupts 83fe56b9e6SYuval Mintz * 84fe56b9e6SYuval Mintz * @param p_hwfn 85fe56b9e6SYuval Mintz * @param p_ptt 86fe56b9e6SYuval Mintz * @param int_mode - interrupt mode to use 87fe56b9e6SYuval Mintz */ 88fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 89fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 90fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 91fe56b9e6SYuval Mintz 92fe56b9e6SYuval Mintz /** 93fe56b9e6SYuval Mintz * @brief qed_int_igu_disable_int - disable device interrupts 94fe56b9e6SYuval Mintz * 95fe56b9e6SYuval Mintz * @param p_hwfn 96fe56b9e6SYuval Mintz * @param p_ptt 97fe56b9e6SYuval Mintz */ 98fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 99fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz /** 102fe56b9e6SYuval Mintz * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 103fe56b9e6SYuval Mintz * register from igu. 104fe56b9e6SYuval Mintz * 105fe56b9e6SYuval Mintz * @param p_hwfn 106fe56b9e6SYuval Mintz * 107fe56b9e6SYuval Mintz * @return u64 108fe56b9e6SYuval Mintz */ 109fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz #define QED_SP_SB_ID 0xffff 112fe56b9e6SYuval Mintz /** 113fe56b9e6SYuval Mintz * @brief qed_int_sb_init - Initializes the sb_info structure. 114fe56b9e6SYuval Mintz * 115fe56b9e6SYuval Mintz * once the structure is initialized it can be passed to sb related functions. 116fe56b9e6SYuval Mintz * 117fe56b9e6SYuval Mintz * @param p_hwfn 118fe56b9e6SYuval Mintz * @param p_ptt 119fe56b9e6SYuval Mintz * @param sb_info points to an uninitialized (but 120fe56b9e6SYuval Mintz * allocated) sb_info structure 121fe56b9e6SYuval Mintz * @param sb_virt_addr 122fe56b9e6SYuval Mintz * @param sb_phy_addr 123fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 124fe56b9e6SYuval Mintz * should use QED_SP_SB_ID for SP Status block 125fe56b9e6SYuval Mintz * 126fe56b9e6SYuval Mintz * @return int 127fe56b9e6SYuval Mintz */ 128fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 129fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 130fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 131fe56b9e6SYuval Mintz void *sb_virt_addr, 132fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 133fe56b9e6SYuval Mintz u16 sb_id); 134fe56b9e6SYuval Mintz /** 135fe56b9e6SYuval Mintz * @brief qed_int_sb_setup - Setup the sb. 136fe56b9e6SYuval Mintz * 137fe56b9e6SYuval Mintz * @param p_hwfn 138fe56b9e6SYuval Mintz * @param p_ptt 139fe56b9e6SYuval Mintz * @param sb_info initialized sb_info structure 140fe56b9e6SYuval Mintz */ 141fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 142fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 143fe56b9e6SYuval Mintz struct qed_sb_info *sb_info); 144fe56b9e6SYuval Mintz 145fe56b9e6SYuval Mintz /** 146fe56b9e6SYuval Mintz * @brief qed_int_sb_release - releases the sb_info structure. 147fe56b9e6SYuval Mintz * 148fe56b9e6SYuval Mintz * once the structure is released, it's memory can be freed 149fe56b9e6SYuval Mintz * 150fe56b9e6SYuval Mintz * @param p_hwfn 151fe56b9e6SYuval Mintz * @param sb_info points to an allocated sb_info structure 152fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 153fe56b9e6SYuval Mintz * should never be equal to QED_SP_SB_ID 154fe56b9e6SYuval Mintz * (SP Status block) 155fe56b9e6SYuval Mintz * 156fe56b9e6SYuval Mintz * @return int 157fe56b9e6SYuval Mintz */ 158fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 159fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 160fe56b9e6SYuval Mintz u16 sb_id); 161fe56b9e6SYuval Mintz 162fe56b9e6SYuval Mintz /** 163fe56b9e6SYuval Mintz * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 164fe56b9e6SYuval Mintz * default status block. 165fe56b9e6SYuval Mintz * 166fe56b9e6SYuval Mintz * @param p_hwfn - pointer to hwfn 167fe56b9e6SYuval Mintz * 168fe56b9e6SYuval Mintz */ 169fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie); 170fe56b9e6SYuval Mintz 171fe56b9e6SYuval Mintz /** 172fe56b9e6SYuval Mintz * @brief qed_int_get_num_sbs - get the number of status 173fe56b9e6SYuval Mintz * blocks configured for this funciton in the igu. 174fe56b9e6SYuval Mintz * 175fe56b9e6SYuval Mintz * @param p_hwfn 1764ac801b7SYuval Mintz * @param p_sb_cnt_info 177fe56b9e6SYuval Mintz * 178fe56b9e6SYuval Mintz * @return int - number of status blocks configured 179fe56b9e6SYuval Mintz */ 1804ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 1814ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info); 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz /** 1848f16bc97SSudarsana Kalluru * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR 1858f16bc97SSudarsana Kalluru * release. The API need to be called after releasing all slowpath IRQs 1868f16bc97SSudarsana Kalluru * of the device. 187fe56b9e6SYuval Mintz * 1888f16bc97SSudarsana Kalluru * @param cdev 1898f16bc97SSudarsana Kalluru * 190fe56b9e6SYuval Mintz */ 1918f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev); 192fe56b9e6SYuval Mintz 193a1b469b8SAriel Elior /** 194a1b469b8SAriel Elior * @brief - Doorbell Recovery handler. 195a1b469b8SAriel Elior * Run DB_REAL_DEAL doorbell recovery in case of PF overflow 196a1b469b8SAriel Elior * (and flush DORQ if needed), otherwise run DB_REC_ONCE. 197a1b469b8SAriel Elior * 198a1b469b8SAriel Elior * @param p_hwfn 199a1b469b8SAriel Elior * @param p_ptt 200a1b469b8SAriel Elior */ 201a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 202a1b469b8SAriel Elior 203fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_TIMER_RES 0 204fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_TIMER_RES 0 205fe56b9e6SYuval Mintz 206fe56b9e6SYuval Mintz #define QED_SB_ATT_IDX 0x0001 207fe56b9e6SYuval Mintz #define QED_SB_EVENT_MASK 0x0003 208fe56b9e6SYuval Mintz 209fe56b9e6SYuval Mintz #define SB_ALIGNED_SIZE(p_hwfn) \ 21021dd79e8STomer Tayar ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn) 211fe56b9e6SYuval Mintz 212d749dd0dSMintz, Yuval #define QED_SB_INVALID_IDX 0xffff 213d749dd0dSMintz, Yuval 214fe56b9e6SYuval Mintz struct qed_igu_block { 215fe56b9e6SYuval Mintz u8 status; 216fe56b9e6SYuval Mintz #define QED_IGU_STATUS_FREE 0x01 217fe56b9e6SYuval Mintz #define QED_IGU_STATUS_VALID 0x02 218fe56b9e6SYuval Mintz #define QED_IGU_STATUS_PF 0x04 219d749dd0dSMintz, Yuval #define QED_IGU_STATUS_DSB 0x08 220fe56b9e6SYuval Mintz 221fe56b9e6SYuval Mintz u8 vector_number; 222fe56b9e6SYuval Mintz u8 function_id; 223fe56b9e6SYuval Mintz u8 is_pf; 2241ac72433SMintz, Yuval 2251ac72433SMintz, Yuval /* Index inside IGU [meant for back reference] */ 2261ac72433SMintz, Yuval u16 igu_sb_id; 22750a20714SMintz, Yuval 22850a20714SMintz, Yuval struct qed_sb_info *sb_info; 229fe56b9e6SYuval Mintz }; 230fe56b9e6SYuval Mintz 231fe56b9e6SYuval Mintz struct qed_igu_info { 232d749dd0dSMintz, Yuval struct qed_igu_block entry[MAX_TOT_SB_PER_PATH]; 233fe56b9e6SYuval Mintz u16 igu_dsb_id; 234726fdbe9SMintz, Yuval 235726fdbe9SMintz, Yuval struct qed_sb_cnt_info usage; 236726fdbe9SMintz, Yuval 237ebbdcc66SMintz, Yuval bool b_allow_pf_vf_change; 238fe56b9e6SYuval Mintz }; 239fe56b9e6SYuval Mintz 24050a20714SMintz, Yuval /** 241ebbdcc66SMintz, Yuval * @brief - Make sure the IGU CAM reflects the resources provided by MFW 242ebbdcc66SMintz, Yuval * 243ebbdcc66SMintz, Yuval * @param p_hwfn 244ebbdcc66SMintz, Yuval * @param p_ptt 245ebbdcc66SMintz, Yuval */ 246ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 247ebbdcc66SMintz, Yuval 248ebbdcc66SMintz, Yuval /** 24950a20714SMintz, Yuval * @brief Translate the weakly-defined client sb-id into an IGU sb-id 25050a20714SMintz, Yuval * 25150a20714SMintz, Yuval * @param p_hwfn 25250a20714SMintz, Yuval * @param sb_id - user provided sb_id 25350a20714SMintz, Yuval * 25450a20714SMintz, Yuval * @return an index inside IGU CAM where the SB resides 25550a20714SMintz, Yuval */ 25650a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id); 25750a20714SMintz, Yuval 25809b6b147SMintz, Yuval /** 25909b6b147SMintz, Yuval * @brief return a pointer to an unused valid SB 26009b6b147SMintz, Yuval * 26109b6b147SMintz, Yuval * @param p_hwfn 26209b6b147SMintz, Yuval * @param b_is_pf - true iff we want a SB belonging to a PF 26309b6b147SMintz, Yuval * 26409b6b147SMintz, Yuval * @return point to an igu_block, NULL if none is available 26509b6b147SMintz, Yuval */ 26609b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, 26709b6b147SMintz, Yuval bool b_is_pf); 26809b6b147SMintz, Yuval 269fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 270fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 271fe56b9e6SYuval Mintz bool b_set, 272fe56b9e6SYuval Mintz bool b_slowpath); 273fe56b9e6SYuval Mintz 274fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 275fe56b9e6SYuval Mintz 276fe56b9e6SYuval Mintz /** 277fe56b9e6SYuval Mintz * @brief qed_int_igu_read_cam - Reads the IGU CAM. 278fe56b9e6SYuval Mintz * This function needs to be called during hardware 279fe56b9e6SYuval Mintz * prepare. It reads the info from igu cam to know which 280fe56b9e6SYuval Mintz * status block is the default / base status block etc. 281fe56b9e6SYuval Mintz * 282fe56b9e6SYuval Mintz * @param p_hwfn 283fe56b9e6SYuval Mintz * @param p_ptt 284fe56b9e6SYuval Mintz * 285fe56b9e6SYuval Mintz * @return int 286fe56b9e6SYuval Mintz */ 287fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 288fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 289fe56b9e6SYuval Mintz 290fe56b9e6SYuval Mintz typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 291fe56b9e6SYuval Mintz void *cookie); 292fe56b9e6SYuval Mintz /** 293fe56b9e6SYuval Mintz * @brief qed_int_register_cb - Register callback func for 294fe56b9e6SYuval Mintz * slowhwfn statusblock. 295fe56b9e6SYuval Mintz * 296fe56b9e6SYuval Mintz * Every protocol that uses the slowhwfn status block 297fe56b9e6SYuval Mintz * should register a callback function that will be called 298fe56b9e6SYuval Mintz * once there is an update of the sp status block. 299fe56b9e6SYuval Mintz * 300fe56b9e6SYuval Mintz * @param p_hwfn 301fe56b9e6SYuval Mintz * @param comp_cb - function to be called when there is an 302fe56b9e6SYuval Mintz * interrupt on the sp sb 303fe56b9e6SYuval Mintz * 304fe56b9e6SYuval Mintz * @param cookie - passed to the callback function 305fe56b9e6SYuval Mintz * @param sb_idx - OUT parameter which gives the chosen index 306fe56b9e6SYuval Mintz * for this protocol. 307fe56b9e6SYuval Mintz * @param p_fw_cons - pointer to the actual address of the 308fe56b9e6SYuval Mintz * consumer for this protocol. 309fe56b9e6SYuval Mintz * 310fe56b9e6SYuval Mintz * @return int 311fe56b9e6SYuval Mintz */ 312fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 313fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 314fe56b9e6SYuval Mintz void *cookie, 315fe56b9e6SYuval Mintz u8 *sb_idx, 316fe56b9e6SYuval Mintz __le16 **p_fw_cons); 317fe56b9e6SYuval Mintz 318fe56b9e6SYuval Mintz /** 319fe56b9e6SYuval Mintz * @brief qed_int_unregister_cb - Unregisters callback 320fe56b9e6SYuval Mintz * function from sp sb. 321fe56b9e6SYuval Mintz * Partner of qed_int_register_cb -> should be called 322fe56b9e6SYuval Mintz * when no longer required. 323fe56b9e6SYuval Mintz * 324fe56b9e6SYuval Mintz * @param p_hwfn 325fe56b9e6SYuval Mintz * @param pi 326fe56b9e6SYuval Mintz * 327fe56b9e6SYuval Mintz * @return int 328fe56b9e6SYuval Mintz */ 329fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 330fe56b9e6SYuval Mintz u8 pi); 331fe56b9e6SYuval Mintz 332fe56b9e6SYuval Mintz /** 333fe56b9e6SYuval Mintz * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 334fe56b9e6SYuval Mintz * 335fe56b9e6SYuval Mintz * @param p_hwfn 336fe56b9e6SYuval Mintz * 337fe56b9e6SYuval Mintz * @return u16 338fe56b9e6SYuval Mintz */ 339fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 340fe56b9e6SYuval Mintz 341fe56b9e6SYuval Mintz /** 342fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 343fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 344fe56b9e6SYuval Mintz * 345fe56b9e6SYuval Mintz * @param p_hwfn 346fe56b9e6SYuval Mintz * @param p_ptt 347d031548eSMintz, Yuval * @param igu_sb_id - igu status block id 348fe56b9e6SYuval Mintz * @param opaque - opaque fid of the sb owner. 349b2b897ebSYuval Mintz * @param b_set - set(1) / clear(0) 350fe56b9e6SYuval Mintz */ 351fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 352fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 353d031548eSMintz, Yuval u16 igu_sb_id, 354fe56b9e6SYuval Mintz u16 opaque, 355fe56b9e6SYuval Mintz bool b_set); 356fe56b9e6SYuval Mintz 357fe56b9e6SYuval Mintz /** 358fe56b9e6SYuval Mintz * @brief qed_int_cau_conf - configure cau for a given status 359fe56b9e6SYuval Mintz * block 360fe56b9e6SYuval Mintz * 361fe56b9e6SYuval Mintz * @param p_hwfn 362fe56b9e6SYuval Mintz * @param ptt 363fe56b9e6SYuval Mintz * @param sb_phys 364fe56b9e6SYuval Mintz * @param igu_sb_id 365fe56b9e6SYuval Mintz * @param vf_number 366fe56b9e6SYuval Mintz * @param vf_valid 367fe56b9e6SYuval Mintz */ 368fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 369fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 370fe56b9e6SYuval Mintz dma_addr_t sb_phys, 371fe56b9e6SYuval Mintz u16 igu_sb_id, 372fe56b9e6SYuval Mintz u16 vf_number, 373fe56b9e6SYuval Mintz u8 vf_valid); 374fe56b9e6SYuval Mintz 375fe56b9e6SYuval Mintz /** 376fe56b9e6SYuval Mintz * @brief qed_int_alloc 377fe56b9e6SYuval Mintz * 378fe56b9e6SYuval Mintz * @param p_hwfn 379fe56b9e6SYuval Mintz * @param p_ptt 380fe56b9e6SYuval Mintz * 381fe56b9e6SYuval Mintz * @return int 382fe56b9e6SYuval Mintz */ 383fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 384fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 385fe56b9e6SYuval Mintz 386fe56b9e6SYuval Mintz /** 387fe56b9e6SYuval Mintz * @brief qed_int_free 388fe56b9e6SYuval Mintz * 389fe56b9e6SYuval Mintz * @param p_hwfn 390fe56b9e6SYuval Mintz */ 391fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn); 392fe56b9e6SYuval Mintz 393fe56b9e6SYuval Mintz /** 394fe56b9e6SYuval Mintz * @brief qed_int_setup 395fe56b9e6SYuval Mintz * 396fe56b9e6SYuval Mintz * @param p_hwfn 397fe56b9e6SYuval Mintz * @param p_ptt 398fe56b9e6SYuval Mintz */ 399fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 400fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 401fe56b9e6SYuval Mintz 402fe56b9e6SYuval Mintz /** 403fe56b9e6SYuval Mintz * @brief - Enable Interrupt & Attention for hw function 404fe56b9e6SYuval Mintz * 405fe56b9e6SYuval Mintz * @param p_hwfn 406fe56b9e6SYuval Mintz * @param p_ptt 407fe56b9e6SYuval Mintz * @param int_mode 4088f16bc97SSudarsana Kalluru * 4098f16bc97SSudarsana Kalluru * @return int 410fe56b9e6SYuval Mintz */ 4118f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 412fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 413fe56b9e6SYuval Mintz 414fe56b9e6SYuval Mintz /** 415fe56b9e6SYuval Mintz * @brief - Initialize CAU status block entry 416fe56b9e6SYuval Mintz * 417fe56b9e6SYuval Mintz * @param p_hwfn 418fe56b9e6SYuval Mintz * @param p_sb_entry 419fe56b9e6SYuval Mintz * @param pf_id 420fe56b9e6SYuval Mintz * @param vf_number 421fe56b9e6SYuval Mintz * @param vf_valid 422fe56b9e6SYuval Mintz */ 423fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 424fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 425fe56b9e6SYuval Mintz u8 pf_id, 426fe56b9e6SYuval Mintz u16 vf_number, 427fe56b9e6SYuval Mintz u8 vf_valid); 428fe56b9e6SYuval Mintz 429722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 430722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx); 431722003acSSudarsana Reddy Kalluru 432fe56b9e6SYuval Mintz #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 433fe56b9e6SYuval Mintz 434666db486STomer Tayar int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, 435666db486STomer Tayar struct qed_ptt *p_ptt); 436666db486STomer Tayar 437fe56b9e6SYuval Mintz #endif 438