11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4fe56b9e6SYuval Mintz */ 5fe56b9e6SYuval Mintz 6fe56b9e6SYuval Mintz #ifndef _QED_INT_H 7fe56b9e6SYuval Mintz #define _QED_INT_H 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <linux/slab.h> 11fe56b9e6SYuval Mintz #include "qed.h" 12fe56b9e6SYuval Mintz 13c199ce4fSGeert Uytterhoeven /* Fields of IGU PF CONFIGURATION REGISTER */ 14fe56b9e6SYuval Mintz #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 15fe56b9e6SYuval Mintz #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 16fe56b9e6SYuval Mintz #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 17fe56b9e6SYuval Mintz #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 18fe56b9e6SYuval Mintz #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 19fe56b9e6SYuval Mintz #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 20c199ce4fSGeert Uytterhoeven /* Fields of IGU VF CONFIGURATION REGISTER */ 211408cc1fSYuval Mintz #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 221408cc1fSYuval Mintz #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 231408cc1fSYuval Mintz #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 241408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 251408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 26fe56b9e6SYuval Mintz 27fe56b9e6SYuval Mintz /* Igu control commands 28fe56b9e6SYuval Mintz */ 29fe56b9e6SYuval Mintz enum igu_ctrl_cmd { 30fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_RD, 31fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_WR, 32fe56b9e6SYuval Mintz MAX_IGU_CTRL_CMD 33fe56b9e6SYuval Mintz }; 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz /* Control register for the IGU command register 36fe56b9e6SYuval Mintz */ 37fe56b9e6SYuval Mintz struct igu_ctrl_reg { 38fe56b9e6SYuval Mintz u32 ctrl_data; 39fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 40fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_SHIFT 0 41fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 42fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 43fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_MASK 0x1 44fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_SHIFT 28 45fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 46fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_SHIFT 31 47fe56b9e6SYuval Mintz }; 48fe56b9e6SYuval Mintz 49fe56b9e6SYuval Mintz enum qed_coalescing_fsm { 50fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 51fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE 52fe56b9e6SYuval Mintz }; 53fe56b9e6SYuval Mintz 54fe56b9e6SYuval Mintz /** 55fe56b9e6SYuval Mintz * @brief qed_int_igu_enable_int - enable device interrupts 56fe56b9e6SYuval Mintz * 57fe56b9e6SYuval Mintz * @param p_hwfn 58fe56b9e6SYuval Mintz * @param p_ptt 59fe56b9e6SYuval Mintz * @param int_mode - interrupt mode to use 60fe56b9e6SYuval Mintz */ 61fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 62fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 63fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz /** 66fe56b9e6SYuval Mintz * @brief qed_int_igu_disable_int - disable device interrupts 67fe56b9e6SYuval Mintz * 68fe56b9e6SYuval Mintz * @param p_hwfn 69fe56b9e6SYuval Mintz * @param p_ptt 70fe56b9e6SYuval Mintz */ 71fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 72fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz /** 75fe56b9e6SYuval Mintz * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 76fe56b9e6SYuval Mintz * register from igu. 77fe56b9e6SYuval Mintz * 78fe56b9e6SYuval Mintz * @param p_hwfn 79fe56b9e6SYuval Mintz * 80fe56b9e6SYuval Mintz * @return u64 81fe56b9e6SYuval Mintz */ 82fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 83fe56b9e6SYuval Mintz 84fe56b9e6SYuval Mintz #define QED_SP_SB_ID 0xffff 85fe56b9e6SYuval Mintz /** 86fe56b9e6SYuval Mintz * @brief qed_int_sb_init - Initializes the sb_info structure. 87fe56b9e6SYuval Mintz * 88fe56b9e6SYuval Mintz * once the structure is initialized it can be passed to sb related functions. 89fe56b9e6SYuval Mintz * 90fe56b9e6SYuval Mintz * @param p_hwfn 91fe56b9e6SYuval Mintz * @param p_ptt 92fe56b9e6SYuval Mintz * @param sb_info points to an uninitialized (but 93fe56b9e6SYuval Mintz * allocated) sb_info structure 94fe56b9e6SYuval Mintz * @param sb_virt_addr 95fe56b9e6SYuval Mintz * @param sb_phy_addr 96fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 97fe56b9e6SYuval Mintz * should use QED_SP_SB_ID for SP Status block 98fe56b9e6SYuval Mintz * 99fe56b9e6SYuval Mintz * @return int 100fe56b9e6SYuval Mintz */ 101fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 102fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 103fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 104fe56b9e6SYuval Mintz void *sb_virt_addr, 105fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 106fe56b9e6SYuval Mintz u16 sb_id); 107fe56b9e6SYuval Mintz /** 108fe56b9e6SYuval Mintz * @brief qed_int_sb_setup - Setup the sb. 109fe56b9e6SYuval Mintz * 110fe56b9e6SYuval Mintz * @param p_hwfn 111fe56b9e6SYuval Mintz * @param p_ptt 112fe56b9e6SYuval Mintz * @param sb_info initialized sb_info structure 113fe56b9e6SYuval Mintz */ 114fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 115fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 116fe56b9e6SYuval Mintz struct qed_sb_info *sb_info); 117fe56b9e6SYuval Mintz 118fe56b9e6SYuval Mintz /** 119fe56b9e6SYuval Mintz * @brief qed_int_sb_release - releases the sb_info structure. 120fe56b9e6SYuval Mintz * 121fe56b9e6SYuval Mintz * once the structure is released, it's memory can be freed 122fe56b9e6SYuval Mintz * 123fe56b9e6SYuval Mintz * @param p_hwfn 124fe56b9e6SYuval Mintz * @param sb_info points to an allocated sb_info structure 125fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 126fe56b9e6SYuval Mintz * should never be equal to QED_SP_SB_ID 127fe56b9e6SYuval Mintz * (SP Status block) 128fe56b9e6SYuval Mintz * 129fe56b9e6SYuval Mintz * @return int 130fe56b9e6SYuval Mintz */ 131fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 132fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 133fe56b9e6SYuval Mintz u16 sb_id); 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz /** 136fe56b9e6SYuval Mintz * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 137fe56b9e6SYuval Mintz * default status block. 138fe56b9e6SYuval Mintz * 139fe56b9e6SYuval Mintz * @param p_hwfn - pointer to hwfn 140fe56b9e6SYuval Mintz * 141fe56b9e6SYuval Mintz */ 142fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie); 143fe56b9e6SYuval Mintz 144fe56b9e6SYuval Mintz /** 145fe56b9e6SYuval Mintz * @brief qed_int_get_num_sbs - get the number of status 146fe56b9e6SYuval Mintz * blocks configured for this funciton in the igu. 147fe56b9e6SYuval Mintz * 148fe56b9e6SYuval Mintz * @param p_hwfn 1494ac801b7SYuval Mintz * @param p_sb_cnt_info 150fe56b9e6SYuval Mintz * 151fe56b9e6SYuval Mintz * @return int - number of status blocks configured 152fe56b9e6SYuval Mintz */ 1534ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 1544ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info); 155fe56b9e6SYuval Mintz 156fe56b9e6SYuval Mintz /** 1578f16bc97SSudarsana Kalluru * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR 1588f16bc97SSudarsana Kalluru * release. The API need to be called after releasing all slowpath IRQs 1598f16bc97SSudarsana Kalluru * of the device. 160fe56b9e6SYuval Mintz * 1618f16bc97SSudarsana Kalluru * @param cdev 1628f16bc97SSudarsana Kalluru * 163fe56b9e6SYuval Mintz */ 1648f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev); 165fe56b9e6SYuval Mintz 166a1b469b8SAriel Elior /** 167936c7ba4SIgor Russkikh * @brief qed_int_attn_clr_enable - sets whether the general behavior is 168936c7ba4SIgor Russkikh * preventing attentions from being reasserted, or following the 169936c7ba4SIgor Russkikh * attributes of the specific attention. 170936c7ba4SIgor Russkikh * 171936c7ba4SIgor Russkikh * @param cdev 172936c7ba4SIgor Russkikh * @param clr_enable 173936c7ba4SIgor Russkikh * 174936c7ba4SIgor Russkikh */ 175936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable); 176936c7ba4SIgor Russkikh 177936c7ba4SIgor Russkikh /** 178a1b469b8SAriel Elior * @brief - Doorbell Recovery handler. 1799ac6bb14SDenis Bolotin * Run doorbell recovery in case of PF overflow (and flush DORQ if 1809ac6bb14SDenis Bolotin * needed). 181a1b469b8SAriel Elior * 182a1b469b8SAriel Elior * @param p_hwfn 183a1b469b8SAriel Elior * @param p_ptt 184a1b469b8SAriel Elior */ 185a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 186a1b469b8SAriel Elior 187fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_TIMER_RES 0 188fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_TIMER_RES 0 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz #define QED_SB_ATT_IDX 0x0001 191fe56b9e6SYuval Mintz #define QED_SB_EVENT_MASK 0x0003 192fe56b9e6SYuval Mintz 193fe56b9e6SYuval Mintz #define SB_ALIGNED_SIZE(p_hwfn) \ 19421dd79e8STomer Tayar ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn) 195fe56b9e6SYuval Mintz 196d749dd0dSMintz, Yuval #define QED_SB_INVALID_IDX 0xffff 197d749dd0dSMintz, Yuval 198fe56b9e6SYuval Mintz struct qed_igu_block { 199fe56b9e6SYuval Mintz u8 status; 200fe56b9e6SYuval Mintz #define QED_IGU_STATUS_FREE 0x01 201fe56b9e6SYuval Mintz #define QED_IGU_STATUS_VALID 0x02 202fe56b9e6SYuval Mintz #define QED_IGU_STATUS_PF 0x04 203d749dd0dSMintz, Yuval #define QED_IGU_STATUS_DSB 0x08 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz u8 vector_number; 206fe56b9e6SYuval Mintz u8 function_id; 207fe56b9e6SYuval Mintz u8 is_pf; 2081ac72433SMintz, Yuval 2091ac72433SMintz, Yuval /* Index inside IGU [meant for back reference] */ 2101ac72433SMintz, Yuval u16 igu_sb_id; 21150a20714SMintz, Yuval 21250a20714SMintz, Yuval struct qed_sb_info *sb_info; 213fe56b9e6SYuval Mintz }; 214fe56b9e6SYuval Mintz 215fe56b9e6SYuval Mintz struct qed_igu_info { 216d749dd0dSMintz, Yuval struct qed_igu_block entry[MAX_TOT_SB_PER_PATH]; 217fe56b9e6SYuval Mintz u16 igu_dsb_id; 218726fdbe9SMintz, Yuval 219726fdbe9SMintz, Yuval struct qed_sb_cnt_info usage; 220726fdbe9SMintz, Yuval 221ebbdcc66SMintz, Yuval bool b_allow_pf_vf_change; 222fe56b9e6SYuval Mintz }; 223fe56b9e6SYuval Mintz 22450a20714SMintz, Yuval /** 225ebbdcc66SMintz, Yuval * @brief - Make sure the IGU CAM reflects the resources provided by MFW 226ebbdcc66SMintz, Yuval * 227ebbdcc66SMintz, Yuval * @param p_hwfn 228ebbdcc66SMintz, Yuval * @param p_ptt 229ebbdcc66SMintz, Yuval */ 230ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 231ebbdcc66SMintz, Yuval 232ebbdcc66SMintz, Yuval /** 23350a20714SMintz, Yuval * @brief Translate the weakly-defined client sb-id into an IGU sb-id 23450a20714SMintz, Yuval * 23550a20714SMintz, Yuval * @param p_hwfn 23650a20714SMintz, Yuval * @param sb_id - user provided sb_id 23750a20714SMintz, Yuval * 23850a20714SMintz, Yuval * @return an index inside IGU CAM where the SB resides 23950a20714SMintz, Yuval */ 24050a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id); 24150a20714SMintz, Yuval 24209b6b147SMintz, Yuval /** 24309b6b147SMintz, Yuval * @brief return a pointer to an unused valid SB 24409b6b147SMintz, Yuval * 24509b6b147SMintz, Yuval * @param p_hwfn 24609b6b147SMintz, Yuval * @param b_is_pf - true iff we want a SB belonging to a PF 24709b6b147SMintz, Yuval * 24809b6b147SMintz, Yuval * @return point to an igu_block, NULL if none is available 24909b6b147SMintz, Yuval */ 25009b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, 25109b6b147SMintz, Yuval bool b_is_pf); 25209b6b147SMintz, Yuval 253fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 254fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 255fe56b9e6SYuval Mintz bool b_set, 256fe56b9e6SYuval Mintz bool b_slowpath); 257fe56b9e6SYuval Mintz 258fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 259fe56b9e6SYuval Mintz 260fe56b9e6SYuval Mintz /** 261fe56b9e6SYuval Mintz * @brief qed_int_igu_read_cam - Reads the IGU CAM. 262fe56b9e6SYuval Mintz * This function needs to be called during hardware 263fe56b9e6SYuval Mintz * prepare. It reads the info from igu cam to know which 264fe56b9e6SYuval Mintz * status block is the default / base status block etc. 265fe56b9e6SYuval Mintz * 266fe56b9e6SYuval Mintz * @param p_hwfn 267fe56b9e6SYuval Mintz * @param p_ptt 268fe56b9e6SYuval Mintz * 269fe56b9e6SYuval Mintz * @return int 270fe56b9e6SYuval Mintz */ 271fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 272fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 273fe56b9e6SYuval Mintz 274fe56b9e6SYuval Mintz typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 275fe56b9e6SYuval Mintz void *cookie); 276fe56b9e6SYuval Mintz /** 277fe56b9e6SYuval Mintz * @brief qed_int_register_cb - Register callback func for 278fe56b9e6SYuval Mintz * slowhwfn statusblock. 279fe56b9e6SYuval Mintz * 280fe56b9e6SYuval Mintz * Every protocol that uses the slowhwfn status block 281fe56b9e6SYuval Mintz * should register a callback function that will be called 282fe56b9e6SYuval Mintz * once there is an update of the sp status block. 283fe56b9e6SYuval Mintz * 284fe56b9e6SYuval Mintz * @param p_hwfn 285fe56b9e6SYuval Mintz * @param comp_cb - function to be called when there is an 286fe56b9e6SYuval Mintz * interrupt on the sp sb 287fe56b9e6SYuval Mintz * 288fe56b9e6SYuval Mintz * @param cookie - passed to the callback function 289fe56b9e6SYuval Mintz * @param sb_idx - OUT parameter which gives the chosen index 290fe56b9e6SYuval Mintz * for this protocol. 291fe56b9e6SYuval Mintz * @param p_fw_cons - pointer to the actual address of the 292fe56b9e6SYuval Mintz * consumer for this protocol. 293fe56b9e6SYuval Mintz * 294fe56b9e6SYuval Mintz * @return int 295fe56b9e6SYuval Mintz */ 296fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 297fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 298fe56b9e6SYuval Mintz void *cookie, 299fe56b9e6SYuval Mintz u8 *sb_idx, 300fe56b9e6SYuval Mintz __le16 **p_fw_cons); 301fe56b9e6SYuval Mintz 302fe56b9e6SYuval Mintz /** 303fe56b9e6SYuval Mintz * @brief qed_int_unregister_cb - Unregisters callback 304fe56b9e6SYuval Mintz * function from sp sb. 305fe56b9e6SYuval Mintz * Partner of qed_int_register_cb -> should be called 306fe56b9e6SYuval Mintz * when no longer required. 307fe56b9e6SYuval Mintz * 308fe56b9e6SYuval Mintz * @param p_hwfn 309fe56b9e6SYuval Mintz * @param pi 310fe56b9e6SYuval Mintz * 311fe56b9e6SYuval Mintz * @return int 312fe56b9e6SYuval Mintz */ 313fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 314fe56b9e6SYuval Mintz u8 pi); 315fe56b9e6SYuval Mintz 316fe56b9e6SYuval Mintz /** 317fe56b9e6SYuval Mintz * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 318fe56b9e6SYuval Mintz * 319fe56b9e6SYuval Mintz * @param p_hwfn 320fe56b9e6SYuval Mintz * 321fe56b9e6SYuval Mintz * @return u16 322fe56b9e6SYuval Mintz */ 323fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 324fe56b9e6SYuval Mintz 325fe56b9e6SYuval Mintz /** 326fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 327fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 328fe56b9e6SYuval Mintz * 329fe56b9e6SYuval Mintz * @param p_hwfn 330fe56b9e6SYuval Mintz * @param p_ptt 331d031548eSMintz, Yuval * @param igu_sb_id - igu status block id 332fe56b9e6SYuval Mintz * @param opaque - opaque fid of the sb owner. 333b2b897ebSYuval Mintz * @param b_set - set(1) / clear(0) 334fe56b9e6SYuval Mintz */ 335fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 336fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 337d031548eSMintz, Yuval u16 igu_sb_id, 338fe56b9e6SYuval Mintz u16 opaque, 339fe56b9e6SYuval Mintz bool b_set); 340fe56b9e6SYuval Mintz 341fe56b9e6SYuval Mintz /** 342fe56b9e6SYuval Mintz * @brief qed_int_cau_conf - configure cau for a given status 343fe56b9e6SYuval Mintz * block 344fe56b9e6SYuval Mintz * 345fe56b9e6SYuval Mintz * @param p_hwfn 346fe56b9e6SYuval Mintz * @param ptt 347fe56b9e6SYuval Mintz * @param sb_phys 348fe56b9e6SYuval Mintz * @param igu_sb_id 349fe56b9e6SYuval Mintz * @param vf_number 350fe56b9e6SYuval Mintz * @param vf_valid 351fe56b9e6SYuval Mintz */ 352fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 353fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 354fe56b9e6SYuval Mintz dma_addr_t sb_phys, 355fe56b9e6SYuval Mintz u16 igu_sb_id, 356fe56b9e6SYuval Mintz u16 vf_number, 357fe56b9e6SYuval Mintz u8 vf_valid); 358fe56b9e6SYuval Mintz 359fe56b9e6SYuval Mintz /** 360fe56b9e6SYuval Mintz * @brief qed_int_alloc 361fe56b9e6SYuval Mintz * 362fe56b9e6SYuval Mintz * @param p_hwfn 363fe56b9e6SYuval Mintz * @param p_ptt 364fe56b9e6SYuval Mintz * 365fe56b9e6SYuval Mintz * @return int 366fe56b9e6SYuval Mintz */ 367fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 368fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 369fe56b9e6SYuval Mintz 370fe56b9e6SYuval Mintz /** 371fe56b9e6SYuval Mintz * @brief qed_int_free 372fe56b9e6SYuval Mintz * 373fe56b9e6SYuval Mintz * @param p_hwfn 374fe56b9e6SYuval Mintz */ 375fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn); 376fe56b9e6SYuval Mintz 377fe56b9e6SYuval Mintz /** 378fe56b9e6SYuval Mintz * @brief qed_int_setup 379fe56b9e6SYuval Mintz * 380fe56b9e6SYuval Mintz * @param p_hwfn 381fe56b9e6SYuval Mintz * @param p_ptt 382fe56b9e6SYuval Mintz */ 383fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 384fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 385fe56b9e6SYuval Mintz 386fe56b9e6SYuval Mintz /** 387fe56b9e6SYuval Mintz * @brief - Enable Interrupt & Attention for hw function 388fe56b9e6SYuval Mintz * 389fe56b9e6SYuval Mintz * @param p_hwfn 390fe56b9e6SYuval Mintz * @param p_ptt 391fe56b9e6SYuval Mintz * @param int_mode 3928f16bc97SSudarsana Kalluru * 3938f16bc97SSudarsana Kalluru * @return int 394fe56b9e6SYuval Mintz */ 3958f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 396fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 397fe56b9e6SYuval Mintz 398fe56b9e6SYuval Mintz /** 399fe56b9e6SYuval Mintz * @brief - Initialize CAU status block entry 400fe56b9e6SYuval Mintz * 401fe56b9e6SYuval Mintz * @param p_hwfn 402fe56b9e6SYuval Mintz * @param p_sb_entry 403fe56b9e6SYuval Mintz * @param pf_id 404fe56b9e6SYuval Mintz * @param vf_number 405fe56b9e6SYuval Mintz * @param vf_valid 406fe56b9e6SYuval Mintz */ 407fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 408fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 409fe56b9e6SYuval Mintz u8 pf_id, 410fe56b9e6SYuval Mintz u16 vf_number, 411fe56b9e6SYuval Mintz u8 vf_valid); 412fe56b9e6SYuval Mintz 413722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 414722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx); 415722003acSSudarsana Reddy Kalluru 416fe56b9e6SYuval Mintz #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 417fe56b9e6SYuval Mintz 418666db486STomer Tayar int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, 419666db486STomer Tayar struct qed_ptt *p_ptt); 420666db486STomer Tayar 421fe56b9e6SYuval Mintz #endif 422