1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #ifndef _QED_INT_H 10fe56b9e6SYuval Mintz #define _QED_INT_H 11fe56b9e6SYuval Mintz 12fe56b9e6SYuval Mintz #include <linux/types.h> 13fe56b9e6SYuval Mintz #include <linux/slab.h> 14fe56b9e6SYuval Mintz #include "qed.h" 15fe56b9e6SYuval Mintz 16fe56b9e6SYuval Mintz /* Fields of IGU PF CONFIGRATION REGISTER */ 17fe56b9e6SYuval Mintz #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 18fe56b9e6SYuval Mintz #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 19fe56b9e6SYuval Mintz #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */ 20fe56b9e6SYuval Mintz #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */ 21fe56b9e6SYuval Mintz #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 22fe56b9e6SYuval Mintz #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */ 231408cc1fSYuval Mintz /* Fields of IGU VF CONFIGRATION REGISTER */ 241408cc1fSYuval Mintz #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */ 251408cc1fSYuval Mintz #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */ 261408cc1fSYuval Mintz #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */ 271408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 281408cc1fSYuval Mintz #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz /* Igu control commands 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz enum igu_ctrl_cmd { 33fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_RD, 34fe56b9e6SYuval Mintz IGU_CTRL_CMD_TYPE_WR, 35fe56b9e6SYuval Mintz MAX_IGU_CTRL_CMD 36fe56b9e6SYuval Mintz }; 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz /* Control register for the IGU command register 39fe56b9e6SYuval Mintz */ 40fe56b9e6SYuval Mintz struct igu_ctrl_reg { 41fe56b9e6SYuval Mintz u32 ctrl_data; 42fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 43fe56b9e6SYuval Mintz #define IGU_CTRL_REG_FID_SHIFT 0 44fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 45fe56b9e6SYuval Mintz #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 46fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_MASK 0x1 47fe56b9e6SYuval Mintz #define IGU_CTRL_REG_RESERVED_SHIFT 28 48fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 49fe56b9e6SYuval Mintz #define IGU_CTRL_REG_TYPE_SHIFT 31 50fe56b9e6SYuval Mintz }; 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz enum qed_coalescing_fsm { 53fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 54fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE 55fe56b9e6SYuval Mintz }; 56fe56b9e6SYuval Mintz 57fe56b9e6SYuval Mintz /** 58fe56b9e6SYuval Mintz * @brief qed_int_cau_conf_pi - configure cau for a given 59fe56b9e6SYuval Mintz * status block 60fe56b9e6SYuval Mintz * 61fe56b9e6SYuval Mintz * @param p_hwfn 62fe56b9e6SYuval Mintz * @param p_ptt 63fe56b9e6SYuval Mintz * @param igu_sb_id 64fe56b9e6SYuval Mintz * @param pi_index 65fe56b9e6SYuval Mintz * @param state 66fe56b9e6SYuval Mintz * @param timeset 67fe56b9e6SYuval Mintz */ 68fe56b9e6SYuval Mintz void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 69fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 70fe56b9e6SYuval Mintz u16 igu_sb_id, 71fe56b9e6SYuval Mintz u32 pi_index, 72fe56b9e6SYuval Mintz enum qed_coalescing_fsm coalescing_fsm, 73fe56b9e6SYuval Mintz u8 timeset); 74fe56b9e6SYuval Mintz 75fe56b9e6SYuval Mintz /** 76fe56b9e6SYuval Mintz * @brief qed_int_igu_enable_int - enable device interrupts 77fe56b9e6SYuval Mintz * 78fe56b9e6SYuval Mintz * @param p_hwfn 79fe56b9e6SYuval Mintz * @param p_ptt 80fe56b9e6SYuval Mintz * @param int_mode - interrupt mode to use 81fe56b9e6SYuval Mintz */ 82fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 83fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 84fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 85fe56b9e6SYuval Mintz 86fe56b9e6SYuval Mintz /** 87fe56b9e6SYuval Mintz * @brief qed_int_igu_disable_int - disable device interrupts 88fe56b9e6SYuval Mintz * 89fe56b9e6SYuval Mintz * @param p_hwfn 90fe56b9e6SYuval Mintz * @param p_ptt 91fe56b9e6SYuval Mintz */ 92fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 93fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz /** 96fe56b9e6SYuval Mintz * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc 97fe56b9e6SYuval Mintz * register from igu. 98fe56b9e6SYuval Mintz * 99fe56b9e6SYuval Mintz * @param p_hwfn 100fe56b9e6SYuval Mintz * 101fe56b9e6SYuval Mintz * @return u64 102fe56b9e6SYuval Mintz */ 103fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn); 104fe56b9e6SYuval Mintz 105fe56b9e6SYuval Mintz #define QED_SP_SB_ID 0xffff 106fe56b9e6SYuval Mintz /** 107fe56b9e6SYuval Mintz * @brief qed_int_sb_init - Initializes the sb_info structure. 108fe56b9e6SYuval Mintz * 109fe56b9e6SYuval Mintz * once the structure is initialized it can be passed to sb related functions. 110fe56b9e6SYuval Mintz * 111fe56b9e6SYuval Mintz * @param p_hwfn 112fe56b9e6SYuval Mintz * @param p_ptt 113fe56b9e6SYuval Mintz * @param sb_info points to an uninitialized (but 114fe56b9e6SYuval Mintz * allocated) sb_info structure 115fe56b9e6SYuval Mintz * @param sb_virt_addr 116fe56b9e6SYuval Mintz * @param sb_phy_addr 117fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 118fe56b9e6SYuval Mintz * should use QED_SP_SB_ID for SP Status block 119fe56b9e6SYuval Mintz * 120fe56b9e6SYuval Mintz * @return int 121fe56b9e6SYuval Mintz */ 122fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 123fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 124fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 125fe56b9e6SYuval Mintz void *sb_virt_addr, 126fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 127fe56b9e6SYuval Mintz u16 sb_id); 128fe56b9e6SYuval Mintz /** 129fe56b9e6SYuval Mintz * @brief qed_int_sb_setup - Setup the sb. 130fe56b9e6SYuval Mintz * 131fe56b9e6SYuval Mintz * @param p_hwfn 132fe56b9e6SYuval Mintz * @param p_ptt 133fe56b9e6SYuval Mintz * @param sb_info initialized sb_info structure 134fe56b9e6SYuval Mintz */ 135fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 136fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 137fe56b9e6SYuval Mintz struct qed_sb_info *sb_info); 138fe56b9e6SYuval Mintz 139fe56b9e6SYuval Mintz /** 140fe56b9e6SYuval Mintz * @brief qed_int_sb_release - releases the sb_info structure. 141fe56b9e6SYuval Mintz * 142fe56b9e6SYuval Mintz * once the structure is released, it's memory can be freed 143fe56b9e6SYuval Mintz * 144fe56b9e6SYuval Mintz * @param p_hwfn 145fe56b9e6SYuval Mintz * @param sb_info points to an allocated sb_info structure 146fe56b9e6SYuval Mintz * @param sb_id the sb_id to be used (zero based in driver) 147fe56b9e6SYuval Mintz * should never be equal to QED_SP_SB_ID 148fe56b9e6SYuval Mintz * (SP Status block) 149fe56b9e6SYuval Mintz * 150fe56b9e6SYuval Mintz * @return int 151fe56b9e6SYuval Mintz */ 152fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 153fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 154fe56b9e6SYuval Mintz u16 sb_id); 155fe56b9e6SYuval Mintz 156fe56b9e6SYuval Mintz /** 157fe56b9e6SYuval Mintz * @brief qed_int_sp_dpc - To be called when an interrupt is received on the 158fe56b9e6SYuval Mintz * default status block. 159fe56b9e6SYuval Mintz * 160fe56b9e6SYuval Mintz * @param p_hwfn - pointer to hwfn 161fe56b9e6SYuval Mintz * 162fe56b9e6SYuval Mintz */ 163fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie); 164fe56b9e6SYuval Mintz 165fe56b9e6SYuval Mintz /** 166fe56b9e6SYuval Mintz * @brief qed_int_get_num_sbs - get the number of status 167fe56b9e6SYuval Mintz * blocks configured for this funciton in the igu. 168fe56b9e6SYuval Mintz * 169fe56b9e6SYuval Mintz * @param p_hwfn 1704ac801b7SYuval Mintz * @param p_sb_cnt_info 171fe56b9e6SYuval Mintz * 172fe56b9e6SYuval Mintz * @return int - number of status blocks configured 173fe56b9e6SYuval Mintz */ 1744ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 1754ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info); 176fe56b9e6SYuval Mintz 177fe56b9e6SYuval Mintz /** 1788f16bc97SSudarsana Kalluru * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR 1798f16bc97SSudarsana Kalluru * release. The API need to be called after releasing all slowpath IRQs 1808f16bc97SSudarsana Kalluru * of the device. 181fe56b9e6SYuval Mintz * 1828f16bc97SSudarsana Kalluru * @param cdev 1838f16bc97SSudarsana Kalluru * 184fe56b9e6SYuval Mintz */ 1858f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev); 186fe56b9e6SYuval Mintz 187fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_TIMER_RES 0 188fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_TIMER_RES 0 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz #define QED_SB_ATT_IDX 0x0001 191fe56b9e6SYuval Mintz #define QED_SB_EVENT_MASK 0x0003 192fe56b9e6SYuval Mintz 193fe56b9e6SYuval Mintz #define SB_ALIGNED_SIZE(p_hwfn) \ 194fe56b9e6SYuval Mintz ALIGNED_TYPE_SIZE(struct status_block, p_hwfn) 195fe56b9e6SYuval Mintz 196fe56b9e6SYuval Mintz struct qed_igu_block { 197fe56b9e6SYuval Mintz u8 status; 198fe56b9e6SYuval Mintz #define QED_IGU_STATUS_FREE 0x01 199fe56b9e6SYuval Mintz #define QED_IGU_STATUS_VALID 0x02 200fe56b9e6SYuval Mintz #define QED_IGU_STATUS_PF 0x04 201fe56b9e6SYuval Mintz 202fe56b9e6SYuval Mintz u8 vector_number; 203fe56b9e6SYuval Mintz u8 function_id; 204fe56b9e6SYuval Mintz u8 is_pf; 205fe56b9e6SYuval Mintz }; 206fe56b9e6SYuval Mintz 207fe56b9e6SYuval Mintz struct qed_igu_map { 208fe56b9e6SYuval Mintz struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH]; 209fe56b9e6SYuval Mintz }; 210fe56b9e6SYuval Mintz 211fe56b9e6SYuval Mintz struct qed_igu_info { 212fe56b9e6SYuval Mintz struct qed_igu_map igu_map; 213fe56b9e6SYuval Mintz u16 igu_dsb_id; 214fe56b9e6SYuval Mintz u16 igu_base_sb; 215fe56b9e6SYuval Mintz u16 igu_base_sb_iov; 216fe56b9e6SYuval Mintz u16 igu_sb_cnt; 217fe56b9e6SYuval Mintz u16 igu_sb_cnt_iov; 218fe56b9e6SYuval Mintz u16 free_blks; 219fe56b9e6SYuval Mintz }; 220fe56b9e6SYuval Mintz 221fe56b9e6SYuval Mintz /* TODO Names of function may change... */ 222fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 223fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 224fe56b9e6SYuval Mintz bool b_set, 225fe56b9e6SYuval Mintz bool b_slowpath); 226fe56b9e6SYuval Mintz 227fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn); 228fe56b9e6SYuval Mintz 229fe56b9e6SYuval Mintz /** 230fe56b9e6SYuval Mintz * @brief qed_int_igu_read_cam - Reads the IGU CAM. 231fe56b9e6SYuval Mintz * This function needs to be called during hardware 232fe56b9e6SYuval Mintz * prepare. It reads the info from igu cam to know which 233fe56b9e6SYuval Mintz * status block is the default / base status block etc. 234fe56b9e6SYuval Mintz * 235fe56b9e6SYuval Mintz * @param p_hwfn 236fe56b9e6SYuval Mintz * @param p_ptt 237fe56b9e6SYuval Mintz * 238fe56b9e6SYuval Mintz * @return int 239fe56b9e6SYuval Mintz */ 240fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 241fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 242fe56b9e6SYuval Mintz 243fe56b9e6SYuval Mintz typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn, 244fe56b9e6SYuval Mintz void *cookie); 245fe56b9e6SYuval Mintz /** 246fe56b9e6SYuval Mintz * @brief qed_int_register_cb - Register callback func for 247fe56b9e6SYuval Mintz * slowhwfn statusblock. 248fe56b9e6SYuval Mintz * 249fe56b9e6SYuval Mintz * Every protocol that uses the slowhwfn status block 250fe56b9e6SYuval Mintz * should register a callback function that will be called 251fe56b9e6SYuval Mintz * once there is an update of the sp status block. 252fe56b9e6SYuval Mintz * 253fe56b9e6SYuval Mintz * @param p_hwfn 254fe56b9e6SYuval Mintz * @param comp_cb - function to be called when there is an 255fe56b9e6SYuval Mintz * interrupt on the sp sb 256fe56b9e6SYuval Mintz * 257fe56b9e6SYuval Mintz * @param cookie - passed to the callback function 258fe56b9e6SYuval Mintz * @param sb_idx - OUT parameter which gives the chosen index 259fe56b9e6SYuval Mintz * for this protocol. 260fe56b9e6SYuval Mintz * @param p_fw_cons - pointer to the actual address of the 261fe56b9e6SYuval Mintz * consumer for this protocol. 262fe56b9e6SYuval Mintz * 263fe56b9e6SYuval Mintz * @return int 264fe56b9e6SYuval Mintz */ 265fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 266fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 267fe56b9e6SYuval Mintz void *cookie, 268fe56b9e6SYuval Mintz u8 *sb_idx, 269fe56b9e6SYuval Mintz __le16 **p_fw_cons); 270fe56b9e6SYuval Mintz 271fe56b9e6SYuval Mintz /** 272fe56b9e6SYuval Mintz * @brief qed_int_unregister_cb - Unregisters callback 273fe56b9e6SYuval Mintz * function from sp sb. 274fe56b9e6SYuval Mintz * Partner of qed_int_register_cb -> should be called 275fe56b9e6SYuval Mintz * when no longer required. 276fe56b9e6SYuval Mintz * 277fe56b9e6SYuval Mintz * @param p_hwfn 278fe56b9e6SYuval Mintz * @param pi 279fe56b9e6SYuval Mintz * 280fe56b9e6SYuval Mintz * @return int 281fe56b9e6SYuval Mintz */ 282fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, 283fe56b9e6SYuval Mintz u8 pi); 284fe56b9e6SYuval Mintz 285fe56b9e6SYuval Mintz /** 286fe56b9e6SYuval Mintz * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id. 287fe56b9e6SYuval Mintz * 288fe56b9e6SYuval Mintz * @param p_hwfn 289fe56b9e6SYuval Mintz * 290fe56b9e6SYuval Mintz * @return u16 291fe56b9e6SYuval Mintz */ 292fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn); 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz /** 295fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 296fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 297fe56b9e6SYuval Mintz * 298fe56b9e6SYuval Mintz * @param p_hwfn 299fe56b9e6SYuval Mintz * @param p_ptt 300fe56b9e6SYuval Mintz * @param sb_id - igu status block id 301fe56b9e6SYuval Mintz * @param cleanup_set - set(1) / clear(0) 302fe56b9e6SYuval Mintz * @param opaque_fid - the function for which to perform 303fe56b9e6SYuval Mintz * cleanup, for example a PF on behalf of 304fe56b9e6SYuval Mintz * its VFs. 305fe56b9e6SYuval Mintz */ 306fe56b9e6SYuval Mintz void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 307fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 308fe56b9e6SYuval Mintz u32 sb_id, 309fe56b9e6SYuval Mintz bool cleanup_set, 310fe56b9e6SYuval Mintz u16 opaque_fid); 311fe56b9e6SYuval Mintz 312fe56b9e6SYuval Mintz /** 313fe56b9e6SYuval Mintz * @brief Status block cleanup. Should be called for each status 314fe56b9e6SYuval Mintz * block that will be used -> both PF / VF 315fe56b9e6SYuval Mintz * 316fe56b9e6SYuval Mintz * @param p_hwfn 317fe56b9e6SYuval Mintz * @param p_ptt 318fe56b9e6SYuval Mintz * @param sb_id - igu status block id 319fe56b9e6SYuval Mintz * @param opaque - opaque fid of the sb owner. 320fe56b9e6SYuval Mintz * @param cleanup_set - set(1) / clear(0) 321fe56b9e6SYuval Mintz */ 322fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 323fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 324fe56b9e6SYuval Mintz u32 sb_id, 325fe56b9e6SYuval Mintz u16 opaque, 326fe56b9e6SYuval Mintz bool b_set); 327fe56b9e6SYuval Mintz 328fe56b9e6SYuval Mintz /** 329fe56b9e6SYuval Mintz * @brief qed_int_cau_conf - configure cau for a given status 330fe56b9e6SYuval Mintz * block 331fe56b9e6SYuval Mintz * 332fe56b9e6SYuval Mintz * @param p_hwfn 333fe56b9e6SYuval Mintz * @param ptt 334fe56b9e6SYuval Mintz * @param sb_phys 335fe56b9e6SYuval Mintz * @param igu_sb_id 336fe56b9e6SYuval Mintz * @param vf_number 337fe56b9e6SYuval Mintz * @param vf_valid 338fe56b9e6SYuval Mintz */ 339fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 340fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 341fe56b9e6SYuval Mintz dma_addr_t sb_phys, 342fe56b9e6SYuval Mintz u16 igu_sb_id, 343fe56b9e6SYuval Mintz u16 vf_number, 344fe56b9e6SYuval Mintz u8 vf_valid); 345fe56b9e6SYuval Mintz 346fe56b9e6SYuval Mintz /** 347fe56b9e6SYuval Mintz * @brief qed_int_alloc 348fe56b9e6SYuval Mintz * 349fe56b9e6SYuval Mintz * @param p_hwfn 350fe56b9e6SYuval Mintz * @param p_ptt 351fe56b9e6SYuval Mintz * 352fe56b9e6SYuval Mintz * @return int 353fe56b9e6SYuval Mintz */ 354fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 355fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 356fe56b9e6SYuval Mintz 357fe56b9e6SYuval Mintz /** 358fe56b9e6SYuval Mintz * @brief qed_int_free 359fe56b9e6SYuval Mintz * 360fe56b9e6SYuval Mintz * @param p_hwfn 361fe56b9e6SYuval Mintz */ 362fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn); 363fe56b9e6SYuval Mintz 364fe56b9e6SYuval Mintz /** 365fe56b9e6SYuval Mintz * @brief qed_int_setup 366fe56b9e6SYuval Mintz * 367fe56b9e6SYuval Mintz * @param p_hwfn 368fe56b9e6SYuval Mintz * @param p_ptt 369fe56b9e6SYuval Mintz */ 370fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 371fe56b9e6SYuval Mintz struct qed_ptt *p_ptt); 372fe56b9e6SYuval Mintz 373fe56b9e6SYuval Mintz /** 3741408cc1fSYuval Mintz * @brief - Returns an Rx queue index appropriate for usage with given SB. 3751408cc1fSYuval Mintz * 3761408cc1fSYuval Mintz * @param p_hwfn 3771408cc1fSYuval Mintz * @param sb_id - absolute index of SB 3781408cc1fSYuval Mintz * 3791408cc1fSYuval Mintz * @return index of Rx queue 3801408cc1fSYuval Mintz */ 3811408cc1fSYuval Mintz u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id); 3821408cc1fSYuval Mintz 3831408cc1fSYuval Mintz /** 384fe56b9e6SYuval Mintz * @brief - Enable Interrupt & Attention for hw function 385fe56b9e6SYuval Mintz * 386fe56b9e6SYuval Mintz * @param p_hwfn 387fe56b9e6SYuval Mintz * @param p_ptt 388fe56b9e6SYuval Mintz * @param int_mode 3898f16bc97SSudarsana Kalluru * 3908f16bc97SSudarsana Kalluru * @return int 391fe56b9e6SYuval Mintz */ 3928f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 393fe56b9e6SYuval Mintz enum qed_int_mode int_mode); 394fe56b9e6SYuval Mintz 395fe56b9e6SYuval Mintz /** 396fe56b9e6SYuval Mintz * @brief - Initialize CAU status block entry 397fe56b9e6SYuval Mintz * 398fe56b9e6SYuval Mintz * @param p_hwfn 399fe56b9e6SYuval Mintz * @param p_sb_entry 400fe56b9e6SYuval Mintz * @param pf_id 401fe56b9e6SYuval Mintz * @param vf_number 402fe56b9e6SYuval Mintz * @param vf_valid 403fe56b9e6SYuval Mintz */ 404fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 405fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 406fe56b9e6SYuval Mintz u8 pf_id, 407fe56b9e6SYuval Mintz u16 vf_number, 408fe56b9e6SYuval Mintz u8 vf_valid); 409fe56b9e6SYuval Mintz 410fe56b9e6SYuval Mintz #define QED_MAPPING_MEMORY_SIZE(dev) (NUM_OF_SBS(dev)) 411fe56b9e6SYuval Mintz 412fe56b9e6SYuval Mintz #endif 413