1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/io.h> 36 #include <linux/bitops.h> 37 #include <linux/delay.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/errno.h> 40 #include <linux/interrupt.h> 41 #include <linux/kernel.h> 42 #include <linux/pci.h> 43 #include <linux/slab.h> 44 #include <linux/string.h> 45 #include "qed.h" 46 #include "qed_hsi.h" 47 #include "qed_hw.h" 48 #include "qed_init_ops.h" 49 #include "qed_int.h" 50 #include "qed_mcp.h" 51 #include "qed_reg_addr.h" 52 #include "qed_sp.h" 53 #include "qed_sriov.h" 54 #include "qed_vf.h" 55 56 struct qed_pi_info { 57 qed_int_comp_cb_t comp_cb; 58 void *cookie; 59 }; 60 61 struct qed_sb_sp_info { 62 struct qed_sb_info sb_info; 63 64 /* per protocol index data */ 65 struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 66 }; 67 68 enum qed_attention_type { 69 QED_ATTN_TYPE_ATTN, 70 QED_ATTN_TYPE_PARITY, 71 }; 72 73 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75 76 struct aeu_invert_reg_bit { 77 char bit_name[30]; 78 79 #define ATTENTION_PARITY (1 << 0) 80 81 #define ATTENTION_LENGTH_MASK (0x00000ff0) 82 #define ATTENTION_LENGTH_SHIFT (4) 83 #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 84 ATTENTION_LENGTH_SHIFT) 85 #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 86 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 87 #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 88 ATTENTION_PARITY) 89 90 /* Multiple bits start with this offset */ 91 #define ATTENTION_OFFSET_MASK (0x000ff000) 92 #define ATTENTION_OFFSET_SHIFT (12) 93 94 #define ATTENTION_BB_MASK (0x00700000) 95 #define ATTENTION_BB_SHIFT (20) 96 #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 97 #define ATTENTION_BB_DIFFERENT BIT(23) 98 99 unsigned int flags; 100 101 /* Callback to call if attention will be triggered */ 102 int (*cb)(struct qed_hwfn *p_hwfn); 103 104 enum block_id block_index; 105 }; 106 107 struct aeu_invert_reg { 108 struct aeu_invert_reg_bit bits[32]; 109 }; 110 111 #define MAX_ATTN_GRPS (8) 112 #define NUM_ATTN_REGS (9) 113 114 /* Specific HW attention callbacks */ 115 static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 116 { 117 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 118 119 /* This might occur on certain instances; Log it once then mask it */ 120 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 121 tmp); 122 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 123 0xffffffff); 124 125 return 0; 126 } 127 128 #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 129 #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 130 #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 131 #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 132 #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 133 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 134 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 135 #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 136 #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 137 #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 138 #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 139 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 140 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 141 static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 142 { 143 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 144 PSWHST_REG_INCORRECT_ACCESS_VALID); 145 146 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 147 u32 addr, data, length; 148 149 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 150 PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 151 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 152 PSWHST_REG_INCORRECT_ACCESS_DATA); 153 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 154 PSWHST_REG_INCORRECT_ACCESS_LENGTH); 155 156 DP_INFO(p_hwfn->cdev, 157 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 158 addr, length, 159 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 160 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 161 (u8) GET_FIELD(data, 162 ATTENTION_INCORRECT_ACCESS_VF_VALID), 163 (u8) GET_FIELD(data, 164 ATTENTION_INCORRECT_ACCESS_CLIENT), 165 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 166 (u8) GET_FIELD(data, 167 ATTENTION_INCORRECT_ACCESS_BYTE_EN), 168 data); 169 } 170 171 return 0; 172 } 173 174 #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 175 #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 176 #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 177 #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 178 #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 179 #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 180 #define QED_GRC_ATTENTION_PF_MASK (0xf) 181 #define QED_GRC_ATTENTION_PF_SHIFT (0) 182 #define QED_GRC_ATTENTION_VF_MASK (0xff) 183 #define QED_GRC_ATTENTION_VF_SHIFT (4) 184 #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 185 #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 186 #define QED_GRC_ATTENTION_PRIV_VF (0) 187 static const char *attn_master_to_str(u8 master) 188 { 189 switch (master) { 190 case 1: return "PXP"; 191 case 2: return "MCP"; 192 case 3: return "MSDM"; 193 case 4: return "PSDM"; 194 case 5: return "YSDM"; 195 case 6: return "USDM"; 196 case 7: return "TSDM"; 197 case 8: return "XSDM"; 198 case 9: return "DBU"; 199 case 10: return "DMAE"; 200 default: 201 return "Unknown"; 202 } 203 } 204 205 static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 206 { 207 u32 tmp, tmp2; 208 209 /* We've already cleared the timeout interrupt register, so we learn 210 * of interrupts via the validity register 211 */ 212 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 213 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 214 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 215 goto out; 216 217 /* Read the GRC timeout information */ 218 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 219 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 220 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 221 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 222 223 DP_INFO(p_hwfn->cdev, 224 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 225 tmp2, tmp, 226 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 227 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 228 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 229 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 230 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 231 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 232 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 233 234 out: 235 /* Regardles of anything else, clean the validity bit */ 236 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 237 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 238 return 0; 239 } 240 241 #define PGLUE_ATTENTION_VALID (1 << 29) 242 #define PGLUE_ATTENTION_RD_VALID (1 << 26) 243 #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 244 #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 245 #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 246 #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 247 #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 248 #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 249 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 250 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 251 #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 252 #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 253 #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 254 #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 255 #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 256 #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 257 #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 258 static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn) 259 { 260 u32 tmp; 261 262 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 263 PGLUE_B_REG_TX_ERR_WR_DETAILS2); 264 if (tmp & PGLUE_ATTENTION_VALID) { 265 u32 addr_lo, addr_hi, details; 266 267 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 268 PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 269 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 270 PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 271 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 272 PGLUE_B_REG_TX_ERR_WR_DETAILS); 273 274 DP_INFO(p_hwfn, 275 "Illegal write by chip to [%08x:%08x] blocked.\n" 276 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 277 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 278 addr_hi, addr_lo, details, 279 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 280 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 281 GET_FIELD(details, 282 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 283 tmp, 284 GET_FIELD(tmp, 285 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 286 GET_FIELD(tmp, 287 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 288 GET_FIELD(tmp, 289 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 290 } 291 292 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 293 PGLUE_B_REG_TX_ERR_RD_DETAILS2); 294 if (tmp & PGLUE_ATTENTION_RD_VALID) { 295 u32 addr_lo, addr_hi, details; 296 297 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 298 PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 299 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 300 PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 301 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 302 PGLUE_B_REG_TX_ERR_RD_DETAILS); 303 304 DP_INFO(p_hwfn, 305 "Illegal read by chip from [%08x:%08x] blocked.\n" 306 " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 307 " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 308 addr_hi, addr_lo, details, 309 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 310 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 311 GET_FIELD(details, 312 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 313 tmp, 314 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 315 : 0, 316 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 317 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 318 : 0); 319 } 320 321 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 322 PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 323 if (tmp & PGLUE_ATTENTION_ICPL_VALID) 324 DP_INFO(p_hwfn, "ICPL error - %08x\n", tmp); 325 326 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 327 PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 328 if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 329 u32 addr_hi, addr_lo; 330 331 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 332 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 333 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 334 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 335 336 DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n", 337 tmp, addr_hi, addr_lo); 338 } 339 340 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 341 PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 342 if (tmp & PGLUE_ATTENTION_ILT_VALID) { 343 u32 addr_hi, addr_lo, details; 344 345 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 346 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 347 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 348 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 349 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 350 PGLUE_B_REG_VF_ILT_ERR_DETAILS); 351 352 DP_INFO(p_hwfn, 353 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 354 details, tmp, addr_hi, addr_lo); 355 } 356 357 /* Clear the indications */ 358 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 359 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 360 361 return 0; 362 } 363 364 #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 365 #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 366 #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 367 #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 368 #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 369 370 #define QED_DB_REC_COUNT 1000 371 #define QED_DB_REC_INTERVAL 100 372 373 static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 374 struct qed_ptt *p_ptt) 375 { 376 u32 count = QED_DB_REC_COUNT; 377 u32 usage = 1; 378 379 /* wait for usage to zero or count to run out. This is necessary since 380 * EDPM doorbell transactions can take multiple 64b cycles, and as such 381 * can "split" over the pci. Possibly, the doorbell drop can happen with 382 * half an EDPM in the queue and other half dropped. Another EDPM 383 * doorbell to the same address (from doorbell recovery mechanism or 384 * from the doorbelling entity) could have first half dropped and second 385 * half interpreted as continuation of the first. To prevent such 386 * malformed doorbells from reaching the device, flush the queue before 387 * releasing the overflow sticky indication. 388 */ 389 while (count-- && usage) { 390 usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 391 udelay(QED_DB_REC_INTERVAL); 392 } 393 394 /* should have been depleted by now */ 395 if (usage) { 396 DP_NOTICE(p_hwfn->cdev, 397 "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 398 QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 399 return -EBUSY; 400 } 401 402 return 0; 403 } 404 405 int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 406 { 407 u32 overflow; 408 int rc; 409 410 overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 411 DP_NOTICE(p_hwfn, "PF Overflow sticky 0x%x\n", overflow); 412 if (!overflow) { 413 qed_db_recovery_execute(p_hwfn, DB_REC_ONCE); 414 return 0; 415 } 416 417 if (qed_edpm_enabled(p_hwfn)) { 418 rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 419 if (rc) 420 return rc; 421 } 422 423 /* Flush any pending (e)dpm as they may never arrive */ 424 qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 425 426 /* Release overflow sticky indication (stop silently dropping everything) */ 427 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 428 429 /* Repeat all last doorbells (doorbell drop recovery) */ 430 qed_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL); 431 432 return 0; 433 } 434 435 static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 436 { 437 u32 int_sts, first_drop_reason, details, address, all_drops_reason; 438 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 439 int rc; 440 441 int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 442 DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 443 444 /* int_sts may be zero since all PFs were interrupted for doorbell 445 * overflow but another one already handled it. Can abort here. If 446 * This PF also requires overflow recovery we will be interrupted again. 447 * The masked almost full indication may also be set. Ignoring. 448 */ 449 if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 450 return 0; 451 452 /* check if db_drop or overflow happened */ 453 if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 454 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 455 /* Obtain data about db drop/overflow */ 456 first_drop_reason = qed_rd(p_hwfn, p_ptt, 457 DORQ_REG_DB_DROP_REASON) & 458 QED_DORQ_ATTENTION_REASON_MASK; 459 details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 460 address = qed_rd(p_hwfn, p_ptt, 461 DORQ_REG_DB_DROP_DETAILS_ADDRESS); 462 all_drops_reason = qed_rd(p_hwfn, p_ptt, 463 DORQ_REG_DB_DROP_DETAILS_REASON); 464 465 /* Log info */ 466 DP_NOTICE(p_hwfn->cdev, 467 "Doorbell drop occurred\n" 468 "Address\t\t0x%08x\t(second BAR address)\n" 469 "FID\t\t0x%04x\t\t(Opaque FID)\n" 470 "Size\t\t0x%04x\t\t(in bytes)\n" 471 "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 472 "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 473 address, 474 GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 475 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 476 first_drop_reason, all_drops_reason); 477 478 rc = qed_db_rec_handler(p_hwfn, p_ptt); 479 qed_periodic_db_rec_start(p_hwfn); 480 if (rc) 481 return rc; 482 483 /* Clear the doorbell drop details and prepare for next drop */ 484 qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 485 486 /* Mark interrupt as handled (note: even if drop was due to a different 487 * reason than overflow we mark as handled) 488 */ 489 qed_wr(p_hwfn, 490 p_ptt, 491 DORQ_REG_INT_STS_WR, 492 DORQ_REG_INT_STS_DB_DROP | 493 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 494 495 /* If there are no indications other than drop indications, success */ 496 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 497 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 498 DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 499 return 0; 500 } 501 502 /* Some other indication was present - non recoverable */ 503 DP_INFO(p_hwfn, "DORQ fatal attention\n"); 504 505 return -EINVAL; 506 } 507 508 /* Instead of major changes to the data-structure, we have a some 'special' 509 * identifiers for sources that changed meaning between adapters. 510 */ 511 enum aeu_invert_reg_special_type { 512 AEU_INVERT_REG_SPECIAL_CNIG_0, 513 AEU_INVERT_REG_SPECIAL_CNIG_1, 514 AEU_INVERT_REG_SPECIAL_CNIG_2, 515 AEU_INVERT_REG_SPECIAL_CNIG_3, 516 AEU_INVERT_REG_SPECIAL_MAX, 517 }; 518 519 static struct aeu_invert_reg_bit 520 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 521 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 522 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 523 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 524 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 525 }; 526 527 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 528 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 529 { 530 { /* After Invert 1 */ 531 {"GPIO0 function%d", 532 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 533 } 534 }, 535 536 { 537 { /* After Invert 2 */ 538 {"PGLUE config_space", ATTENTION_SINGLE, 539 NULL, MAX_BLOCK_ID}, 540 {"PGLUE misc_flr", ATTENTION_SINGLE, 541 NULL, MAX_BLOCK_ID}, 542 {"PGLUE B RBC", ATTENTION_PAR_INT, 543 qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 544 {"PGLUE misc_mctp", ATTENTION_SINGLE, 545 NULL, MAX_BLOCK_ID}, 546 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 547 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 548 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 549 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 550 (1 << ATTENTION_OFFSET_SHIFT), 551 NULL, MAX_BLOCK_ID}, 552 {"PCIE glue/PXP VPD %d", 553 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 554 } 555 }, 556 557 { 558 { /* After Invert 3 */ 559 {"General Attention %d", 560 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 561 } 562 }, 563 564 { 565 { /* After Invert 4 */ 566 {"General Attention 32", ATTENTION_SINGLE, 567 NULL, MAX_BLOCK_ID}, 568 {"General Attention %d", 569 (2 << ATTENTION_LENGTH_SHIFT) | 570 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 571 {"General Attention 35", ATTENTION_SINGLE, 572 NULL, MAX_BLOCK_ID}, 573 {"NWS Parity", 574 ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 575 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 576 NULL, BLOCK_NWS}, 577 {"NWS Interrupt", 578 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 579 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 580 NULL, BLOCK_NWS}, 581 {"NWM Parity", 582 ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 583 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 584 NULL, BLOCK_NWM}, 585 {"NWM Interrupt", 586 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 587 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 588 NULL, BLOCK_NWM}, 589 {"MCP CPU", ATTENTION_SINGLE, 590 qed_mcp_attn_cb, MAX_BLOCK_ID}, 591 {"MCP Watchdog timer", ATTENTION_SINGLE, 592 NULL, MAX_BLOCK_ID}, 593 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 594 {"AVS stop status ready", ATTENTION_SINGLE, 595 NULL, MAX_BLOCK_ID}, 596 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 597 {"MSTAT per-path", ATTENTION_PAR_INT, 598 NULL, MAX_BLOCK_ID}, 599 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 600 NULL, MAX_BLOCK_ID}, 601 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 602 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 603 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 604 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 605 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 606 } 607 }, 608 609 { 610 { /* After Invert 5 */ 611 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 612 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 613 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 614 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 615 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 616 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 617 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 618 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 619 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 620 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 621 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 622 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 623 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 624 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 625 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 626 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 627 } 628 }, 629 630 { 631 { /* After Invert 6 */ 632 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 633 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 634 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 635 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 636 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 637 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 638 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 639 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 640 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 641 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 642 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 643 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 644 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 645 {"DORQ", ATTENTION_PAR_INT, 646 qed_dorq_attn_cb, BLOCK_DORQ}, 647 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 648 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 649 } 650 }, 651 652 { 653 { /* After Invert 7 */ 654 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 655 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 656 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 657 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 658 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 659 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 660 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 661 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 662 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 663 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 664 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 665 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 666 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 667 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 668 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 669 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 670 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 671 } 672 }, 673 674 { 675 { /* After Invert 8 */ 676 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 677 NULL, BLOCK_PSWRQ2}, 678 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 679 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 680 NULL, BLOCK_PSWWR2}, 681 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 682 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 683 NULL, BLOCK_PSWRD2}, 684 {"PSWHST", ATTENTION_PAR_INT, 685 qed_pswhst_attn_cb, BLOCK_PSWHST}, 686 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 687 NULL, BLOCK_PSWHST2}, 688 {"GRC", ATTENTION_PAR_INT, 689 qed_grc_attn_cb, BLOCK_GRC}, 690 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 691 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 692 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 693 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 694 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 695 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 696 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 697 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 698 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 699 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 700 NULL, BLOCK_PGLCS}, 701 {"PERST_B assertion", ATTENTION_SINGLE, 702 NULL, MAX_BLOCK_ID}, 703 {"PERST_B deassertion", ATTENTION_SINGLE, 704 NULL, MAX_BLOCK_ID}, 705 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 706 NULL, MAX_BLOCK_ID}, 707 } 708 }, 709 710 { 711 { /* After Invert 9 */ 712 {"MCP Latched memory", ATTENTION_PAR, 713 NULL, MAX_BLOCK_ID}, 714 {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 715 NULL, MAX_BLOCK_ID}, 716 {"MCP Latched ump_tx", ATTENTION_PAR, 717 NULL, MAX_BLOCK_ID}, 718 {"MCP Latched scratchpad", ATTENTION_PAR, 719 NULL, MAX_BLOCK_ID}, 720 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 721 NULL, MAX_BLOCK_ID}, 722 } 723 }, 724 }; 725 726 static struct aeu_invert_reg_bit * 727 qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 728 struct aeu_invert_reg_bit *p_bit) 729 { 730 if (!QED_IS_BB(p_hwfn->cdev)) 731 return p_bit; 732 733 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 734 return p_bit; 735 736 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 737 ATTENTION_BB_SHIFT]; 738 } 739 740 static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 741 struct aeu_invert_reg_bit *p_bit) 742 { 743 return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 744 ATTENTION_PARITY); 745 } 746 747 #define ATTN_STATE_BITS (0xfff) 748 #define ATTN_BITS_MASKABLE (0x3ff) 749 struct qed_sb_attn_info { 750 /* Virtual & Physical address of the SB */ 751 struct atten_status_block *sb_attn; 752 dma_addr_t sb_phys; 753 754 /* Last seen running index */ 755 u16 index; 756 757 /* A mask of the AEU bits resulting in a parity error */ 758 u32 parity_mask[NUM_ATTN_REGS]; 759 760 /* A pointer to the attention description structure */ 761 struct aeu_invert_reg *p_aeu_desc; 762 763 /* Previously asserted attentions, which are still unasserted */ 764 u16 known_attn; 765 766 /* Cleanup address for the link's general hw attention */ 767 u32 mfw_attn_addr; 768 }; 769 770 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 771 struct qed_sb_attn_info *p_sb_desc) 772 { 773 u16 rc = 0, index; 774 775 /* Make certain HW write took affect */ 776 mmiowb(); 777 778 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 779 if (p_sb_desc->index != index) { 780 p_sb_desc->index = index; 781 rc = QED_SB_ATT_IDX; 782 } 783 784 /* Make certain we got a consistent view with HW */ 785 mmiowb(); 786 787 return rc; 788 } 789 790 /** 791 * @brief qed_int_assertion - handles asserted attention bits 792 * 793 * @param p_hwfn 794 * @param asserted_bits newly asserted bits 795 * @return int 796 */ 797 static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 798 { 799 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 800 u32 igu_mask; 801 802 /* Mask the source of the attention in the IGU */ 803 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 804 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 805 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 806 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 807 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 808 809 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 810 "inner known ATTN state: 0x%04x --> 0x%04x\n", 811 sb_attn_sw->known_attn, 812 sb_attn_sw->known_attn | asserted_bits); 813 sb_attn_sw->known_attn |= asserted_bits; 814 815 /* Handle MCP events */ 816 if (asserted_bits & 0x100) { 817 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 818 /* Clean the MCP attention */ 819 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 820 sb_attn_sw->mfw_attn_addr, 0); 821 } 822 823 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 824 GTT_BAR0_MAP_REG_IGU_CMD + 825 ((IGU_CMD_ATTN_BIT_SET_UPPER - 826 IGU_CMD_INT_ACK_BASE) << 3), 827 (u32)asserted_bits); 828 829 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 830 asserted_bits); 831 832 return 0; 833 } 834 835 static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 836 enum block_id id, 837 enum dbg_attn_type type, bool b_clear) 838 { 839 struct dbg_attn_block_result attn_results; 840 enum dbg_status status; 841 842 memset(&attn_results, 0, sizeof(attn_results)); 843 844 status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 845 b_clear, &attn_results); 846 if (status != DBG_STATUS_OK) 847 DP_NOTICE(p_hwfn, 848 "Failed to parse attention information [status: %s]\n", 849 qed_dbg_get_status_str(status)); 850 else 851 qed_dbg_parse_attn(p_hwfn, &attn_results); 852 } 853 854 /** 855 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 856 * cause of the attention 857 * 858 * @param p_hwfn 859 * @param p_aeu - descriptor of an AEU bit which caused the attention 860 * @param aeu_en_reg - register offset of the AEU enable reg. which configured 861 * this bit to this group. 862 * @param bit_index - index of this bit in the aeu_en_reg 863 * 864 * @return int 865 */ 866 static int 867 qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 868 struct aeu_invert_reg_bit *p_aeu, 869 u32 aeu_en_reg, 870 const char *p_bit_name, u32 bitmask) 871 { 872 bool b_fatal = false; 873 int rc = -EINVAL; 874 u32 val; 875 876 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 877 p_bit_name, bitmask); 878 879 /* Call callback before clearing the interrupt status */ 880 if (p_aeu->cb) { 881 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 882 p_bit_name); 883 rc = p_aeu->cb(p_hwfn); 884 } 885 886 if (rc) 887 b_fatal = true; 888 889 /* Print HW block interrupt registers */ 890 if (p_aeu->block_index != MAX_BLOCK_ID) 891 qed_int_attn_print(p_hwfn, p_aeu->block_index, 892 ATTN_TYPE_INTERRUPT, !b_fatal); 893 894 895 /* If the attention is benign, no need to prevent it */ 896 if (!rc) 897 goto out; 898 899 /* Prevent this Attention from being asserted in the future */ 900 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 901 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 902 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 903 p_bit_name); 904 905 out: 906 return rc; 907 } 908 909 /** 910 * @brief qed_int_deassertion_parity - handle a single parity AEU source 911 * 912 * @param p_hwfn 913 * @param p_aeu - descriptor of an AEU bit which caused the parity 914 * @param aeu_en_reg - address of the AEU enable register 915 * @param bit_index 916 */ 917 static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 918 struct aeu_invert_reg_bit *p_aeu, 919 u32 aeu_en_reg, u8 bit_index) 920 { 921 u32 block_id = p_aeu->block_index, mask, val; 922 923 DP_NOTICE(p_hwfn->cdev, 924 "%s parity attention is set [address 0x%08x, bit %d]\n", 925 p_aeu->bit_name, aeu_en_reg, bit_index); 926 927 if (block_id != MAX_BLOCK_ID) { 928 qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 929 930 /* In BB, there's a single parity bit for several blocks */ 931 if (block_id == BLOCK_BTB) { 932 qed_int_attn_print(p_hwfn, BLOCK_OPTE, 933 ATTN_TYPE_PARITY, false); 934 qed_int_attn_print(p_hwfn, BLOCK_MCP, 935 ATTN_TYPE_PARITY, false); 936 } 937 } 938 939 /* Prevent this parity error from being re-asserted */ 940 mask = ~BIT(bit_index); 941 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 942 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 943 DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 944 p_aeu->bit_name); 945 } 946 947 /** 948 * @brief - handles deassertion of previously asserted attentions. 949 * 950 * @param p_hwfn 951 * @param deasserted_bits - newly deasserted bits 952 * @return int 953 * 954 */ 955 static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 956 u16 deasserted_bits) 957 { 958 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 959 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 960 u8 i, j, k, bit_idx; 961 int rc = 0; 962 963 /* Read the attention registers in the AEU */ 964 for (i = 0; i < NUM_ATTN_REGS; i++) { 965 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 966 MISC_REG_AEU_AFTER_INVERT_1_IGU + 967 i * 0x4); 968 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 969 "Deasserted bits [%d]: %08x\n", 970 i, aeu_inv_arr[i]); 971 } 972 973 /* Find parity attentions first */ 974 for (i = 0; i < NUM_ATTN_REGS; i++) { 975 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 976 u32 parities; 977 978 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 979 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 980 981 /* Skip register in which no parity bit is currently set */ 982 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 983 if (!parities) 984 continue; 985 986 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 987 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 988 989 if (qed_int_is_parity_flag(p_hwfn, p_bit) && 990 !!(parities & BIT(bit_idx))) 991 qed_int_deassertion_parity(p_hwfn, p_bit, 992 aeu_en, bit_idx); 993 994 bit_idx += ATTENTION_LENGTH(p_bit->flags); 995 } 996 } 997 998 /* Find non-parity cause for attention and act */ 999 for (k = 0; k < MAX_ATTN_GRPS; k++) { 1000 struct aeu_invert_reg_bit *p_aeu; 1001 1002 /* Handle only groups whose attention is currently deasserted */ 1003 if (!(deasserted_bits & (1 << k))) 1004 continue; 1005 1006 for (i = 0; i < NUM_ATTN_REGS; i++) { 1007 u32 bits; 1008 1009 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 1010 i * sizeof(u32) + 1011 k * sizeof(u32) * NUM_ATTN_REGS; 1012 1013 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 1014 bits = aeu_inv_arr[i] & en; 1015 1016 /* Skip if no bit from this group is currently set */ 1017 if (!bits) 1018 continue; 1019 1020 /* Find all set bits from current register which belong 1021 * to current group, making them responsible for the 1022 * previous assertion. 1023 */ 1024 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 1025 long unsigned int bitmask; 1026 u8 bit, bit_len; 1027 1028 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1029 p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 1030 1031 bit = bit_idx; 1032 bit_len = ATTENTION_LENGTH(p_aeu->flags); 1033 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 1034 /* Skip Parity */ 1035 bit++; 1036 bit_len--; 1037 } 1038 1039 bitmask = bits & (((1 << bit_len) - 1) << bit); 1040 bitmask >>= bit; 1041 1042 if (bitmask) { 1043 u32 flags = p_aeu->flags; 1044 char bit_name[30]; 1045 u8 num; 1046 1047 num = (u8)find_first_bit(&bitmask, 1048 bit_len); 1049 1050 /* Some bits represent more than a 1051 * a single interrupt. Correctly print 1052 * their name. 1053 */ 1054 if (ATTENTION_LENGTH(flags) > 2 || 1055 ((flags & ATTENTION_PAR_INT) && 1056 ATTENTION_LENGTH(flags) > 1)) 1057 snprintf(bit_name, 30, 1058 p_aeu->bit_name, num); 1059 else 1060 strncpy(bit_name, 1061 p_aeu->bit_name, 30); 1062 1063 /* We now need to pass bitmask in its 1064 * correct position. 1065 */ 1066 bitmask <<= bit; 1067 1068 /* Handle source of the attention */ 1069 qed_int_deassertion_aeu_bit(p_hwfn, 1070 p_aeu, 1071 aeu_en, 1072 bit_name, 1073 bitmask); 1074 } 1075 1076 bit_idx += ATTENTION_LENGTH(p_aeu->flags); 1077 } 1078 } 1079 } 1080 1081 /* Clear IGU indication for the deasserted bits */ 1082 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1083 GTT_BAR0_MAP_REG_IGU_CMD + 1084 ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1085 IGU_CMD_INT_ACK_BASE) << 3), 1086 ~((u32)deasserted_bits)); 1087 1088 /* Unmask deasserted attentions in IGU */ 1089 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1090 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1091 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1092 1093 /* Clear deassertion from inner state */ 1094 sb_attn_sw->known_attn &= ~deasserted_bits; 1095 1096 return rc; 1097 } 1098 1099 static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1100 { 1101 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1102 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1103 u32 attn_bits = 0, attn_acks = 0; 1104 u16 asserted_bits, deasserted_bits; 1105 __le16 index; 1106 int rc = 0; 1107 1108 /* Read current attention bits/acks - safeguard against attentions 1109 * by guaranting work on a synchronized timeframe 1110 */ 1111 do { 1112 index = p_sb_attn->sb_index; 1113 /* finish reading index before the loop condition */ 1114 dma_rmb(); 1115 attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1116 attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1117 } while (index != p_sb_attn->sb_index); 1118 p_sb_attn->sb_index = index; 1119 1120 /* Attention / Deassertion are meaningful (and in correct state) 1121 * only when they differ and consistent with known state - deassertion 1122 * when previous attention & current ack, and assertion when current 1123 * attention with no previous attention 1124 */ 1125 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1126 ~p_sb_attn_sw->known_attn; 1127 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1128 p_sb_attn_sw->known_attn; 1129 1130 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1131 DP_INFO(p_hwfn, 1132 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1133 index, attn_bits, attn_acks, asserted_bits, 1134 deasserted_bits, p_sb_attn_sw->known_attn); 1135 } else if (asserted_bits == 0x100) { 1136 DP_INFO(p_hwfn, "MFW indication via attention\n"); 1137 } else { 1138 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1139 "MFW indication [deassertion]\n"); 1140 } 1141 1142 if (asserted_bits) { 1143 rc = qed_int_assertion(p_hwfn, asserted_bits); 1144 if (rc) 1145 return rc; 1146 } 1147 1148 if (deasserted_bits) 1149 rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1150 1151 return rc; 1152 } 1153 1154 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 1155 void __iomem *igu_addr, u32 ack_cons) 1156 { 1157 struct igu_prod_cons_update igu_ack = { 0 }; 1158 1159 igu_ack.sb_id_and_flags = 1160 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1161 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1162 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1163 (IGU_SEG_ACCESS_ATTN << 1164 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1165 1166 DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1167 1168 /* Both segments (interrupts & acks) are written to same place address; 1169 * Need to guarantee all commands will be received (in-order) by HW. 1170 */ 1171 mmiowb(); 1172 barrier(); 1173 } 1174 1175 void qed_int_sp_dpc(unsigned long hwfn_cookie) 1176 { 1177 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1178 struct qed_pi_info *pi_info = NULL; 1179 struct qed_sb_attn_info *sb_attn; 1180 struct qed_sb_info *sb_info; 1181 int arr_size; 1182 u16 rc = 0; 1183 1184 if (!p_hwfn->p_sp_sb) { 1185 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1186 return; 1187 } 1188 1189 sb_info = &p_hwfn->p_sp_sb->sb_info; 1190 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1191 if (!sb_info) { 1192 DP_ERR(p_hwfn->cdev, 1193 "Status block is NULL - cannot ack interrupts\n"); 1194 return; 1195 } 1196 1197 if (!p_hwfn->p_sb_attn) { 1198 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1199 return; 1200 } 1201 sb_attn = p_hwfn->p_sb_attn; 1202 1203 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1204 p_hwfn, p_hwfn->my_id); 1205 1206 /* Disable ack for def status block. Required both for msix + 1207 * inta in non-mask mode, in inta does no harm. 1208 */ 1209 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1210 1211 /* Gather Interrupts/Attentions information */ 1212 if (!sb_info->sb_virt) { 1213 DP_ERR(p_hwfn->cdev, 1214 "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1215 } else { 1216 u32 tmp_index = sb_info->sb_ack; 1217 1218 rc = qed_sb_update_sb_idx(sb_info); 1219 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1220 "Interrupt indices: 0x%08x --> 0x%08x\n", 1221 tmp_index, sb_info->sb_ack); 1222 } 1223 1224 if (!sb_attn || !sb_attn->sb_attn) { 1225 DP_ERR(p_hwfn->cdev, 1226 "Attentions Status block is NULL - cannot check for new attentions!\n"); 1227 } else { 1228 u16 tmp_index = sb_attn->index; 1229 1230 rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1231 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1232 "Attention indices: 0x%08x --> 0x%08x\n", 1233 tmp_index, sb_attn->index); 1234 } 1235 1236 /* Check if we expect interrupts at this time. if not just ack them */ 1237 if (!(rc & QED_SB_EVENT_MASK)) { 1238 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1239 return; 1240 } 1241 1242 /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1243 if (!p_hwfn->p_dpc_ptt) { 1244 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1245 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1246 return; 1247 } 1248 1249 if (rc & QED_SB_ATT_IDX) 1250 qed_int_attentions(p_hwfn); 1251 1252 if (rc & QED_SB_IDX) { 1253 int pi; 1254 1255 /* Look for a free index */ 1256 for (pi = 0; pi < arr_size; pi++) { 1257 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1258 if (pi_info->comp_cb) 1259 pi_info->comp_cb(p_hwfn, pi_info->cookie); 1260 } 1261 } 1262 1263 if (sb_attn && (rc & QED_SB_ATT_IDX)) 1264 /* This should be done before the interrupts are enabled, 1265 * since otherwise a new attention will be generated. 1266 */ 1267 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1268 1269 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1270 } 1271 1272 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1273 { 1274 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1275 1276 if (!p_sb) 1277 return; 1278 1279 if (p_sb->sb_attn) 1280 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1281 SB_ATTN_ALIGNED_SIZE(p_hwfn), 1282 p_sb->sb_attn, p_sb->sb_phys); 1283 kfree(p_sb); 1284 p_hwfn->p_sb_attn = NULL; 1285 } 1286 1287 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1288 struct qed_ptt *p_ptt) 1289 { 1290 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1291 1292 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1293 1294 sb_info->index = 0; 1295 sb_info->known_attn = 0; 1296 1297 /* Configure Attention Status Block in IGU */ 1298 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1299 lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1300 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1301 upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1302 } 1303 1304 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1305 struct qed_ptt *p_ptt, 1306 void *sb_virt_addr, dma_addr_t sb_phy_addr) 1307 { 1308 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1309 int i, j, k; 1310 1311 sb_info->sb_attn = sb_virt_addr; 1312 sb_info->sb_phys = sb_phy_addr; 1313 1314 /* Set the pointer to the AEU descriptors */ 1315 sb_info->p_aeu_desc = aeu_descs; 1316 1317 /* Calculate Parity Masks */ 1318 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 1319 for (i = 0; i < NUM_ATTN_REGS; i++) { 1320 /* j is array index, k is bit index */ 1321 for (j = 0, k = 0; k < 32; j++) { 1322 struct aeu_invert_reg_bit *p_aeu; 1323 1324 p_aeu = &aeu_descs[i].bits[j]; 1325 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 1326 sb_info->parity_mask[i] |= 1 << k; 1327 1328 k += ATTENTION_LENGTH(p_aeu->flags); 1329 } 1330 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1331 "Attn Mask [Reg %d]: 0x%08x\n", 1332 i, sb_info->parity_mask[i]); 1333 } 1334 1335 /* Set the address of cleanup for the mcp attention */ 1336 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1337 MISC_REG_AEU_GENERAL_ATTN_0; 1338 1339 qed_int_sb_attn_setup(p_hwfn, p_ptt); 1340 } 1341 1342 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1343 struct qed_ptt *p_ptt) 1344 { 1345 struct qed_dev *cdev = p_hwfn->cdev; 1346 struct qed_sb_attn_info *p_sb; 1347 dma_addr_t p_phys = 0; 1348 void *p_virt; 1349 1350 /* SB struct */ 1351 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 1352 if (!p_sb) 1353 return -ENOMEM; 1354 1355 /* SB ring */ 1356 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1357 SB_ATTN_ALIGNED_SIZE(p_hwfn), 1358 &p_phys, GFP_KERNEL); 1359 1360 if (!p_virt) { 1361 kfree(p_sb); 1362 return -ENOMEM; 1363 } 1364 1365 /* Attention setup */ 1366 p_hwfn->p_sb_attn = p_sb; 1367 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1368 1369 return 0; 1370 } 1371 1372 /* coalescing timeout = timeset << (timer_res + 1) */ 1373 #define QED_CAU_DEF_RX_USECS 24 1374 #define QED_CAU_DEF_TX_USECS 48 1375 1376 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1377 struct cau_sb_entry *p_sb_entry, 1378 u8 pf_id, u16 vf_number, u8 vf_valid) 1379 { 1380 struct qed_dev *cdev = p_hwfn->cdev; 1381 u32 cau_state; 1382 u8 timer_res; 1383 1384 memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1385 1386 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1387 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1388 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1389 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1390 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1391 1392 cau_state = CAU_HC_DISABLE_STATE; 1393 1394 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1395 cau_state = CAU_HC_ENABLE_STATE; 1396 if (!cdev->rx_coalesce_usecs) 1397 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 1398 if (!cdev->tx_coalesce_usecs) 1399 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1400 } 1401 1402 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1403 if (cdev->rx_coalesce_usecs <= 0x7F) 1404 timer_res = 0; 1405 else if (cdev->rx_coalesce_usecs <= 0xFF) 1406 timer_res = 1; 1407 else 1408 timer_res = 2; 1409 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1410 1411 if (cdev->tx_coalesce_usecs <= 0x7F) 1412 timer_res = 0; 1413 else if (cdev->tx_coalesce_usecs <= 0xFF) 1414 timer_res = 1; 1415 else 1416 timer_res = 2; 1417 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1418 1419 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1420 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1421 } 1422 1423 static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 1424 struct qed_ptt *p_ptt, 1425 u16 igu_sb_id, 1426 u32 pi_index, 1427 enum qed_coalescing_fsm coalescing_fsm, 1428 u8 timeset) 1429 { 1430 struct cau_pi_entry pi_entry; 1431 u32 sb_offset, pi_offset; 1432 1433 if (IS_VF(p_hwfn->cdev)) 1434 return; 1435 1436 sb_offset = igu_sb_id * PIS_PER_SB_E4; 1437 memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 1438 1439 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 1440 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 1441 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 1442 else 1443 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 1444 1445 pi_offset = sb_offset + pi_index; 1446 if (p_hwfn->hw_init_done) { 1447 qed_wr(p_hwfn, p_ptt, 1448 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 1449 *((u32 *)&(pi_entry))); 1450 } else { 1451 STORE_RT_REG(p_hwfn, 1452 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 1453 *((u32 *)&(pi_entry))); 1454 } 1455 } 1456 1457 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1458 struct qed_ptt *p_ptt, 1459 dma_addr_t sb_phys, 1460 u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1461 { 1462 struct cau_sb_entry sb_entry; 1463 1464 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1465 vf_number, vf_valid); 1466 1467 if (p_hwfn->hw_init_done) { 1468 /* Wide-bus, initialize via DMAE */ 1469 u64 phys_addr = (u64)sb_phys; 1470 1471 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 1472 CAU_REG_SB_ADDR_MEMORY + 1473 igu_sb_id * sizeof(u64), 2, 0); 1474 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 1475 CAU_REG_SB_VAR_MEMORY + 1476 igu_sb_id * sizeof(u64), 2, 0); 1477 } else { 1478 /* Initialize Status Block Address */ 1479 STORE_RT_REG_AGG(p_hwfn, 1480 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1481 igu_sb_id * 2, 1482 sb_phys); 1483 1484 STORE_RT_REG_AGG(p_hwfn, 1485 CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1486 igu_sb_id * 2, 1487 sb_entry); 1488 } 1489 1490 /* Configure pi coalescing if set */ 1491 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1492 u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1493 u8 timeset, timer_res; 1494 u8 i; 1495 1496 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1497 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1498 timer_res = 0; 1499 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1500 timer_res = 1; 1501 else 1502 timer_res = 2; 1503 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1504 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 1505 QED_COAL_RX_STATE_MACHINE, timeset); 1506 1507 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1508 timer_res = 0; 1509 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1510 timer_res = 1; 1511 else 1512 timer_res = 2; 1513 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1514 for (i = 0; i < num_tc; i++) { 1515 qed_int_cau_conf_pi(p_hwfn, p_ptt, 1516 igu_sb_id, TX_PI(i), 1517 QED_COAL_TX_STATE_MACHINE, 1518 timeset); 1519 } 1520 } 1521 } 1522 1523 void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 1524 struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1525 { 1526 /* zero status block and ack counter */ 1527 sb_info->sb_ack = 0; 1528 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1529 1530 if (IS_PF(p_hwfn->cdev)) 1531 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1532 sb_info->igu_sb_id, 0, 0); 1533 } 1534 1535 struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 1536 { 1537 struct qed_igu_block *p_block; 1538 u16 igu_id; 1539 1540 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1541 igu_id++) { 1542 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1543 1544 if (!(p_block->status & QED_IGU_STATUS_VALID) || 1545 !(p_block->status & QED_IGU_STATUS_FREE)) 1546 continue; 1547 1548 if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 1549 return p_block; 1550 } 1551 1552 return NULL; 1553 } 1554 1555 static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1556 { 1557 struct qed_igu_block *p_block; 1558 u16 igu_id; 1559 1560 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1561 igu_id++) { 1562 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1563 1564 if (!(p_block->status & QED_IGU_STATUS_VALID) || 1565 !p_block->is_pf || 1566 p_block->vector_number != vector_id) 1567 continue; 1568 1569 return igu_id; 1570 } 1571 1572 return QED_SB_INVALID_IDX; 1573 } 1574 1575 u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1576 { 1577 u16 igu_sb_id; 1578 1579 /* Assuming continuous set of IGU SBs dedicated for given PF */ 1580 if (sb_id == QED_SP_SB_ID) 1581 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 1582 else if (IS_PF(p_hwfn->cdev)) 1583 igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 1584 else 1585 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1586 1587 if (sb_id == QED_SP_SB_ID) 1588 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1589 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1590 else 1591 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1592 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1593 1594 return igu_sb_id; 1595 } 1596 1597 int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1598 struct qed_ptt *p_ptt, 1599 struct qed_sb_info *sb_info, 1600 void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1601 { 1602 sb_info->sb_virt = sb_virt_addr; 1603 sb_info->sb_phys = sb_phy_addr; 1604 1605 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1606 1607 if (sb_id != QED_SP_SB_ID) { 1608 if (IS_PF(p_hwfn->cdev)) { 1609 struct qed_igu_info *p_info; 1610 struct qed_igu_block *p_block; 1611 1612 p_info = p_hwfn->hw_info.p_igu_info; 1613 p_block = &p_info->entry[sb_info->igu_sb_id]; 1614 1615 p_block->sb_info = sb_info; 1616 p_block->status &= ~QED_IGU_STATUS_FREE; 1617 p_info->usage.free_cnt--; 1618 } else { 1619 qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 1620 } 1621 } 1622 1623 sb_info->cdev = p_hwfn->cdev; 1624 1625 /* The igu address will hold the absolute address that needs to be 1626 * written to for a specific status block 1627 */ 1628 if (IS_PF(p_hwfn->cdev)) { 1629 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1630 GTT_BAR0_MAP_REG_IGU_CMD + 1631 (sb_info->igu_sb_id << 3); 1632 } else { 1633 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1634 PXP_VF_BAR0_START_IGU + 1635 ((IGU_CMD_INT_ACK_BASE + 1636 sb_info->igu_sb_id) << 3); 1637 } 1638 1639 sb_info->flags |= QED_SB_INFO_INIT; 1640 1641 qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1642 1643 return 0; 1644 } 1645 1646 int qed_int_sb_release(struct qed_hwfn *p_hwfn, 1647 struct qed_sb_info *sb_info, u16 sb_id) 1648 { 1649 struct qed_igu_block *p_block; 1650 struct qed_igu_info *p_info; 1651 1652 if (!sb_info) 1653 return 0; 1654 1655 /* zero status block and ack counter */ 1656 sb_info->sb_ack = 0; 1657 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1658 1659 if (IS_VF(p_hwfn->cdev)) { 1660 qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 1661 return 0; 1662 } 1663 1664 p_info = p_hwfn->hw_info.p_igu_info; 1665 p_block = &p_info->entry[sb_info->igu_sb_id]; 1666 1667 /* Vector 0 is reserved to Default SB */ 1668 if (!p_block->vector_number) { 1669 DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 1670 return -EINVAL; 1671 } 1672 1673 /* Lose reference to client's SB info, and fix counters */ 1674 p_block->sb_info = NULL; 1675 p_block->status |= QED_IGU_STATUS_FREE; 1676 p_info->usage.free_cnt++; 1677 1678 return 0; 1679 } 1680 1681 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1682 { 1683 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1684 1685 if (!p_sb) 1686 return; 1687 1688 if (p_sb->sb_info.sb_virt) 1689 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1690 SB_ALIGNED_SIZE(p_hwfn), 1691 p_sb->sb_info.sb_virt, 1692 p_sb->sb_info.sb_phys); 1693 kfree(p_sb); 1694 p_hwfn->p_sp_sb = NULL; 1695 } 1696 1697 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1698 { 1699 struct qed_sb_sp_info *p_sb; 1700 dma_addr_t p_phys = 0; 1701 void *p_virt; 1702 1703 /* SB struct */ 1704 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 1705 if (!p_sb) 1706 return -ENOMEM; 1707 1708 /* SB ring */ 1709 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1710 SB_ALIGNED_SIZE(p_hwfn), 1711 &p_phys, GFP_KERNEL); 1712 if (!p_virt) { 1713 kfree(p_sb); 1714 return -ENOMEM; 1715 } 1716 1717 /* Status Block setup */ 1718 p_hwfn->p_sp_sb = p_sb; 1719 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1720 p_phys, QED_SP_SB_ID); 1721 1722 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1723 1724 return 0; 1725 } 1726 1727 int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1728 qed_int_comp_cb_t comp_cb, 1729 void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1730 { 1731 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1732 int rc = -ENOMEM; 1733 u8 pi; 1734 1735 /* Look for a free index */ 1736 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 1737 if (p_sp_sb->pi_info_arr[pi].comp_cb) 1738 continue; 1739 1740 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1741 p_sp_sb->pi_info_arr[pi].cookie = cookie; 1742 *sb_idx = pi; 1743 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 1744 rc = 0; 1745 break; 1746 } 1747 1748 return rc; 1749 } 1750 1751 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1752 { 1753 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1754 1755 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 1756 return -ENOMEM; 1757 1758 p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1759 p_sp_sb->pi_info_arr[pi].cookie = NULL; 1760 1761 return 0; 1762 } 1763 1764 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1765 { 1766 return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1767 } 1768 1769 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 1770 struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1771 { 1772 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1773 1774 p_hwfn->cdev->int_mode = int_mode; 1775 switch (p_hwfn->cdev->int_mode) { 1776 case QED_INT_MODE_INTA: 1777 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1778 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1779 break; 1780 1781 case QED_INT_MODE_MSI: 1782 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1783 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1784 break; 1785 1786 case QED_INT_MODE_MSIX: 1787 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1788 break; 1789 case QED_INT_MODE_POLL: 1790 break; 1791 } 1792 1793 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1794 } 1795 1796 static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1797 struct qed_ptt *p_ptt) 1798 { 1799 1800 /* Configure AEU signal change to produce attentions */ 1801 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1802 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1803 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 1804 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1805 1806 /* Flush the writes to IGU */ 1807 mmiowb(); 1808 1809 /* Unmask AEU signals toward IGU */ 1810 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1811 } 1812 1813 int 1814 qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1815 struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1816 { 1817 int rc = 0; 1818 1819 qed_int_igu_enable_attn(p_hwfn, p_ptt); 1820 1821 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 1822 rc = qed_slowpath_irq_req(p_hwfn); 1823 if (rc) { 1824 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 1825 return -EINVAL; 1826 } 1827 p_hwfn->b_int_requested = true; 1828 } 1829 /* Enable interrupt Generation */ 1830 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 1831 p_hwfn->b_int_enabled = 1; 1832 1833 return rc; 1834 } 1835 1836 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1837 { 1838 p_hwfn->b_int_enabled = 0; 1839 1840 if (IS_VF(p_hwfn->cdev)) 1841 return; 1842 1843 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1844 } 1845 1846 #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1847 static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1848 struct qed_ptt *p_ptt, 1849 u16 igu_sb_id, 1850 bool cleanup_set, u16 opaque_fid) 1851 { 1852 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1853 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1854 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1855 1856 /* Set the data field */ 1857 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1858 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1859 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1860 1861 /* Set the control register */ 1862 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1863 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1864 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1865 1866 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1867 1868 barrier(); 1869 1870 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1871 1872 /* Flush the write to IGU */ 1873 mmiowb(); 1874 1875 /* calculate where to read the status bit from */ 1876 sb_bit = 1 << (igu_sb_id % 32); 1877 sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1878 1879 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1880 1881 /* Now wait for the command to complete */ 1882 do { 1883 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1884 1885 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1886 break; 1887 1888 usleep_range(5000, 10000); 1889 } while (--sleep_cnt); 1890 1891 if (!sleep_cnt) 1892 DP_NOTICE(p_hwfn, 1893 "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1894 val, igu_sb_id); 1895 } 1896 1897 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1898 struct qed_ptt *p_ptt, 1899 u16 igu_sb_id, u16 opaque, bool b_set) 1900 { 1901 struct qed_igu_block *p_block; 1902 int pi, i; 1903 1904 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 1905 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1906 "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 1907 igu_sb_id, 1908 p_block->function_id, 1909 p_block->is_pf, p_block->vector_number); 1910 1911 /* Set */ 1912 if (b_set) 1913 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1914 1915 /* Clear */ 1916 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1917 1918 /* Wait for the IGU SB to cleanup */ 1919 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1920 u32 val; 1921 1922 val = qed_rd(p_hwfn, p_ptt, 1923 IGU_REG_WRITE_DONE_PENDING + 1924 ((igu_sb_id / 32) * 4)); 1925 if (val & BIT((igu_sb_id % 32))) 1926 usleep_range(10, 20); 1927 else 1928 break; 1929 } 1930 if (i == IGU_CLEANUP_SLEEP_LENGTH) 1931 DP_NOTICE(p_hwfn, 1932 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1933 igu_sb_id); 1934 1935 /* Clear the CAU for the SB */ 1936 for (pi = 0; pi < 12; pi++) 1937 qed_wr(p_hwfn, p_ptt, 1938 CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1939 } 1940 1941 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1942 struct qed_ptt *p_ptt, 1943 bool b_set, bool b_slowpath) 1944 { 1945 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 1946 struct qed_igu_block *p_block; 1947 u16 igu_sb_id = 0; 1948 u32 val = 0; 1949 1950 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1951 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1952 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1953 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1954 1955 for (igu_sb_id = 0; 1956 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 1957 p_block = &p_info->entry[igu_sb_id]; 1958 1959 if (!(p_block->status & QED_IGU_STATUS_VALID) || 1960 !p_block->is_pf || 1961 (p_block->status & QED_IGU_STATUS_DSB)) 1962 continue; 1963 1964 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 1965 p_hwfn->hw_info.opaque_fid, 1966 b_set); 1967 } 1968 1969 if (b_slowpath) 1970 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 1971 p_info->igu_dsb_id, 1972 p_hwfn->hw_info.opaque_fid, 1973 b_set); 1974 } 1975 1976 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1977 { 1978 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 1979 struct qed_igu_block *p_block; 1980 int pf_sbs, vf_sbs; 1981 u16 igu_sb_id; 1982 u32 val, rval; 1983 1984 if (!RESC_NUM(p_hwfn, QED_SB)) { 1985 p_info->b_allow_pf_vf_change = false; 1986 } else { 1987 /* Use the numbers the MFW have provided - 1988 * don't forget MFW accounts for the default SB as well. 1989 */ 1990 p_info->b_allow_pf_vf_change = true; 1991 1992 if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 1993 DP_INFO(p_hwfn, 1994 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 1995 RESC_NUM(p_hwfn, QED_SB) - 1, 1996 p_info->usage.cnt); 1997 p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 1998 } 1999 2000 if (IS_PF_SRIOV(p_hwfn)) { 2001 u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2002 2003 if (vfs != p_info->usage.iov_cnt) 2004 DP_VERBOSE(p_hwfn, 2005 NETIF_MSG_INTR, 2006 "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2007 p_info->usage.iov_cnt, vfs); 2008 2009 /* At this point we know how many SBs we have totally 2010 * in IGU + number of PF SBs. So we can validate that 2011 * we'd have sufficient for VF. 2012 */ 2013 if (vfs > p_info->usage.free_cnt + 2014 p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2015 DP_NOTICE(p_hwfn, 2016 "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2017 p_info->usage.free_cnt + 2018 p_info->usage.free_cnt_iov, 2019 p_info->usage.cnt, vfs); 2020 return -EINVAL; 2021 } 2022 2023 /* Currently cap the number of VFs SBs by the 2024 * number of VFs. 2025 */ 2026 p_info->usage.iov_cnt = vfs; 2027 } 2028 } 2029 2030 /* Mark all SBs as free, now in the right PF/VFs division */ 2031 p_info->usage.free_cnt = p_info->usage.cnt; 2032 p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2033 p_info->usage.orig = p_info->usage.cnt; 2034 p_info->usage.iov_orig = p_info->usage.iov_cnt; 2035 2036 /* We now proceed to re-configure the IGU cam to reflect the initial 2037 * configuration. We can start with the Default SB. 2038 */ 2039 pf_sbs = p_info->usage.cnt; 2040 vf_sbs = p_info->usage.iov_cnt; 2041 2042 for (igu_sb_id = p_info->igu_dsb_id; 2043 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2044 p_block = &p_info->entry[igu_sb_id]; 2045 val = 0; 2046 2047 if (!(p_block->status & QED_IGU_STATUS_VALID)) 2048 continue; 2049 2050 if (p_block->status & QED_IGU_STATUS_DSB) { 2051 p_block->function_id = p_hwfn->rel_pf_id; 2052 p_block->is_pf = 1; 2053 p_block->vector_number = 0; 2054 p_block->status = QED_IGU_STATUS_VALID | 2055 QED_IGU_STATUS_PF | 2056 QED_IGU_STATUS_DSB; 2057 } else if (pf_sbs) { 2058 pf_sbs--; 2059 p_block->function_id = p_hwfn->rel_pf_id; 2060 p_block->is_pf = 1; 2061 p_block->vector_number = p_info->usage.cnt - pf_sbs; 2062 p_block->status = QED_IGU_STATUS_VALID | 2063 QED_IGU_STATUS_PF | 2064 QED_IGU_STATUS_FREE; 2065 } else if (vf_sbs) { 2066 p_block->function_id = 2067 p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2068 p_info->usage.iov_cnt - vf_sbs; 2069 p_block->is_pf = 0; 2070 p_block->vector_number = 0; 2071 p_block->status = QED_IGU_STATUS_VALID | 2072 QED_IGU_STATUS_FREE; 2073 vf_sbs--; 2074 } else { 2075 p_block->function_id = 0; 2076 p_block->is_pf = 0; 2077 p_block->vector_number = 0; 2078 } 2079 2080 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2081 p_block->function_id); 2082 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2083 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2084 p_block->vector_number); 2085 2086 /* VF entries would be enabled when VF is initializaed */ 2087 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2088 2089 rval = qed_rd(p_hwfn, p_ptt, 2090 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2091 2092 if (rval != val) { 2093 qed_wr(p_hwfn, p_ptt, 2094 IGU_REG_MAPPING_MEMORY + 2095 sizeof(u32) * igu_sb_id, val); 2096 2097 DP_VERBOSE(p_hwfn, 2098 NETIF_MSG_INTR, 2099 "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2100 igu_sb_id, 2101 p_block->function_id, 2102 p_block->is_pf, 2103 p_block->vector_number, rval, val); 2104 } 2105 } 2106 2107 return 0; 2108 } 2109 2110 static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2111 struct qed_ptt *p_ptt, u16 igu_sb_id) 2112 { 2113 u32 val = qed_rd(p_hwfn, p_ptt, 2114 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2115 struct qed_igu_block *p_block; 2116 2117 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 2118 2119 /* Fill the block information */ 2120 p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 2121 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2122 p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 2123 p_block->igu_sb_id = igu_sb_id; 2124 } 2125 2126 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2127 { 2128 struct qed_igu_info *p_igu_info; 2129 struct qed_igu_block *p_block; 2130 u32 min_vf = 0, max_vf = 0; 2131 u16 igu_sb_id; 2132 2133 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2134 if (!p_hwfn->hw_info.p_igu_info) 2135 return -ENOMEM; 2136 2137 p_igu_info = p_hwfn->hw_info.p_igu_info; 2138 2139 /* Distinguish between existent and non-existent default SB */ 2140 p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2141 2142 /* Find the range of VF ids whose SB belong to this PF */ 2143 if (p_hwfn->cdev->p_iov_info) { 2144 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 2145 2146 min_vf = p_iov->first_vf_in_pf; 2147 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 2148 } 2149 2150 for (igu_sb_id = 0; 2151 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2152 /* Read current entry; Notice it might not belong to this PF */ 2153 qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2154 p_block = &p_igu_info->entry[igu_sb_id]; 2155 2156 if ((p_block->is_pf) && 2157 (p_block->function_id == p_hwfn->rel_pf_id)) { 2158 p_block->status = QED_IGU_STATUS_PF | 2159 QED_IGU_STATUS_VALID | 2160 QED_IGU_STATUS_FREE; 2161 2162 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2163 p_igu_info->usage.cnt++; 2164 } else if (!(p_block->is_pf) && 2165 (p_block->function_id >= min_vf) && 2166 (p_block->function_id < max_vf)) { 2167 /* Available for VFs of this PF */ 2168 p_block->status = QED_IGU_STATUS_VALID | 2169 QED_IGU_STATUS_FREE; 2170 2171 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2172 p_igu_info->usage.iov_cnt++; 2173 } 2174 2175 /* Mark the First entry belonging to the PF or its VFs 2176 * as the default SB [we'll reset IGU prior to first usage]. 2177 */ 2178 if ((p_block->status & QED_IGU_STATUS_VALID) && 2179 (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2180 p_igu_info->igu_dsb_id = igu_sb_id; 2181 p_block->status |= QED_IGU_STATUS_DSB; 2182 } 2183 2184 /* limit number of prints by having each PF print only its 2185 * entries with the exception of PF0 which would print 2186 * everything. 2187 */ 2188 if ((p_block->status & QED_IGU_STATUS_VALID) || 2189 (p_hwfn->abs_pf_id == 0)) { 2190 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2191 "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2192 igu_sb_id, p_block->function_id, 2193 p_block->is_pf, p_block->vector_number); 2194 } 2195 } 2196 2197 if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 2198 DP_NOTICE(p_hwfn, 2199 "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2200 p_igu_info->igu_dsb_id); 2201 return -EINVAL; 2202 } 2203 2204 /* All non default SB are considered free at this point */ 2205 p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2206 p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2207 2208 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2209 "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2210 p_igu_info->igu_dsb_id, 2211 p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2212 2213 return 0; 2214 } 2215 2216 /** 2217 * @brief Initialize igu runtime registers 2218 * 2219 * @param p_hwfn 2220 */ 2221 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2222 { 2223 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2224 2225 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2226 } 2227 2228 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2229 { 2230 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2231 IGU_CMD_INT_ACK_BASE; 2232 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2233 IGU_CMD_INT_ACK_BASE; 2234 u32 intr_status_hi = 0, intr_status_lo = 0; 2235 u64 intr_status = 0; 2236 2237 intr_status_lo = REG_RD(p_hwfn, 2238 GTT_BAR0_MAP_REG_IGU_CMD + 2239 lsb_igu_cmd_addr * 8); 2240 intr_status_hi = REG_RD(p_hwfn, 2241 GTT_BAR0_MAP_REG_IGU_CMD + 2242 msb_igu_cmd_addr * 8); 2243 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2244 2245 return intr_status; 2246 } 2247 2248 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2249 { 2250 tasklet_init(p_hwfn->sp_dpc, 2251 qed_int_sp_dpc, (unsigned long)p_hwfn); 2252 p_hwfn->b_sp_dpc_enabled = true; 2253 } 2254 2255 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2256 { 2257 p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2258 if (!p_hwfn->sp_dpc) 2259 return -ENOMEM; 2260 2261 return 0; 2262 } 2263 2264 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2265 { 2266 kfree(p_hwfn->sp_dpc); 2267 p_hwfn->sp_dpc = NULL; 2268 } 2269 2270 int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2271 { 2272 int rc = 0; 2273 2274 rc = qed_int_sp_dpc_alloc(p_hwfn); 2275 if (rc) 2276 return rc; 2277 2278 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 2279 if (rc) 2280 return rc; 2281 2282 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 2283 2284 return rc; 2285 } 2286 2287 void qed_int_free(struct qed_hwfn *p_hwfn) 2288 { 2289 qed_int_sp_sb_free(p_hwfn); 2290 qed_int_sb_attn_free(p_hwfn); 2291 qed_int_sp_dpc_free(p_hwfn); 2292 } 2293 2294 void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2295 { 2296 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 2297 qed_int_sb_attn_setup(p_hwfn, p_ptt); 2298 qed_int_sp_dpc_setup(p_hwfn); 2299 } 2300 2301 void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 2302 struct qed_sb_cnt_info *p_sb_cnt_info) 2303 { 2304 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2305 2306 if (!info || !p_sb_cnt_info) 2307 return; 2308 2309 memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2310 } 2311 2312 void qed_int_disable_post_isr_release(struct qed_dev *cdev) 2313 { 2314 int i; 2315 2316 for_each_hwfn(cdev, i) 2317 cdev->hwfns[i].b_int_requested = false; 2318 } 2319 2320 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2321 u8 timer_res, u16 sb_id, bool tx) 2322 { 2323 struct cau_sb_entry sb_entry; 2324 int rc; 2325 2326 if (!p_hwfn->hw_init_done) { 2327 DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2328 return -EINVAL; 2329 } 2330 2331 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2332 sb_id * sizeof(u64), 2333 (u64)(uintptr_t)&sb_entry, 2, 0); 2334 if (rc) { 2335 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2336 return rc; 2337 } 2338 2339 if (tx) 2340 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2341 else 2342 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2343 2344 rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2345 (u64)(uintptr_t)&sb_entry, 2346 CAU_REG_SB_VAR_MEMORY + 2347 sb_id * sizeof(u64), 2, 0); 2348 if (rc) { 2349 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2350 return rc; 2351 } 2352 2353 return rc; 2354 } 2355