1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/io.h> 36 #include <linux/bitops.h> 37 #include <linux/delay.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/errno.h> 40 #include <linux/interrupt.h> 41 #include <linux/kernel.h> 42 #include <linux/pci.h> 43 #include <linux/slab.h> 44 #include <linux/string.h> 45 #include "qed.h" 46 #include "qed_hsi.h" 47 #include "qed_hw.h" 48 #include "qed_init_ops.h" 49 #include "qed_int.h" 50 #include "qed_mcp.h" 51 #include "qed_reg_addr.h" 52 #include "qed_sp.h" 53 #include "qed_sriov.h" 54 #include "qed_vf.h" 55 56 struct qed_pi_info { 57 qed_int_comp_cb_t comp_cb; 58 void *cookie; 59 }; 60 61 struct qed_sb_sp_info { 62 struct qed_sb_info sb_info; 63 64 /* per protocol index data */ 65 struct qed_pi_info pi_info_arr[PIS_PER_SB]; 66 }; 67 68 enum qed_attention_type { 69 QED_ATTN_TYPE_ATTN, 70 QED_ATTN_TYPE_PARITY, 71 }; 72 73 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75 76 struct aeu_invert_reg_bit { 77 char bit_name[30]; 78 79 #define ATTENTION_PARITY (1 << 0) 80 81 #define ATTENTION_LENGTH_MASK (0x00000ff0) 82 #define ATTENTION_LENGTH_SHIFT (4) 83 #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 84 ATTENTION_LENGTH_SHIFT) 85 #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT) 86 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 87 #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 88 ATTENTION_PARITY) 89 90 /* Multiple bits start with this offset */ 91 #define ATTENTION_OFFSET_MASK (0x000ff000) 92 #define ATTENTION_OFFSET_SHIFT (12) 93 94 #define ATTENTION_BB_MASK (0x00700000) 95 #define ATTENTION_BB_SHIFT (20) 96 #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 97 #define ATTENTION_BB_DIFFERENT BIT(23) 98 99 unsigned int flags; 100 101 /* Callback to call if attention will be triggered */ 102 int (*cb)(struct qed_hwfn *p_hwfn); 103 104 enum block_id block_index; 105 }; 106 107 struct aeu_invert_reg { 108 struct aeu_invert_reg_bit bits[32]; 109 }; 110 111 #define MAX_ATTN_GRPS (8) 112 #define NUM_ATTN_REGS (9) 113 114 /* Specific HW attention callbacks */ 115 static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 116 { 117 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 118 119 /* This might occur on certain instances; Log it once then mask it */ 120 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 121 tmp); 122 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 123 0xffffffff); 124 125 return 0; 126 } 127 128 #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 129 #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 130 #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 131 #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 132 #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 133 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 134 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 135 #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 136 #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 137 #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 138 #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 139 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 140 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 141 static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 142 { 143 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 144 PSWHST_REG_INCORRECT_ACCESS_VALID); 145 146 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 147 u32 addr, data, length; 148 149 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 150 PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 151 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 152 PSWHST_REG_INCORRECT_ACCESS_DATA); 153 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 154 PSWHST_REG_INCORRECT_ACCESS_LENGTH); 155 156 DP_INFO(p_hwfn->cdev, 157 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 158 addr, length, 159 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 160 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 161 (u8) GET_FIELD(data, 162 ATTENTION_INCORRECT_ACCESS_VF_VALID), 163 (u8) GET_FIELD(data, 164 ATTENTION_INCORRECT_ACCESS_CLIENT), 165 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 166 (u8) GET_FIELD(data, 167 ATTENTION_INCORRECT_ACCESS_BYTE_EN), 168 data); 169 } 170 171 return 0; 172 } 173 174 #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 175 #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 176 #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 177 #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 178 #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 179 #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 180 #define QED_GRC_ATTENTION_PF_MASK (0xf) 181 #define QED_GRC_ATTENTION_PF_SHIFT (0) 182 #define QED_GRC_ATTENTION_VF_MASK (0xff) 183 #define QED_GRC_ATTENTION_VF_SHIFT (4) 184 #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 185 #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 186 #define QED_GRC_ATTENTION_PRIV_VF (0) 187 static const char *attn_master_to_str(u8 master) 188 { 189 switch (master) { 190 case 1: return "PXP"; 191 case 2: return "MCP"; 192 case 3: return "MSDM"; 193 case 4: return "PSDM"; 194 case 5: return "YSDM"; 195 case 6: return "USDM"; 196 case 7: return "TSDM"; 197 case 8: return "XSDM"; 198 case 9: return "DBU"; 199 case 10: return "DMAE"; 200 default: 201 return "Unknown"; 202 } 203 } 204 205 static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 206 { 207 u32 tmp, tmp2; 208 209 /* We've already cleared the timeout interrupt register, so we learn 210 * of interrupts via the validity register 211 */ 212 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 213 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 214 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 215 goto out; 216 217 /* Read the GRC timeout information */ 218 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 219 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 220 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 221 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 222 223 DP_INFO(p_hwfn->cdev, 224 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 225 tmp2, tmp, 226 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 227 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 228 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 229 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 230 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 231 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Ireelevant)", 232 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 233 234 out: 235 /* Regardles of anything else, clean the validity bit */ 236 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 237 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 238 return 0; 239 } 240 241 #define PGLUE_ATTENTION_VALID (1 << 29) 242 #define PGLUE_ATTENTION_RD_VALID (1 << 26) 243 #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 244 #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 245 #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 246 #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 247 #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 248 #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 249 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 250 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 251 #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 252 #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 253 #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 254 #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 255 #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 256 #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 257 #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 258 static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn) 259 { 260 u32 tmp; 261 262 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 263 PGLUE_B_REG_TX_ERR_WR_DETAILS2); 264 if (tmp & PGLUE_ATTENTION_VALID) { 265 u32 addr_lo, addr_hi, details; 266 267 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 268 PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 269 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 270 PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 271 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 272 PGLUE_B_REG_TX_ERR_WR_DETAILS); 273 274 DP_INFO(p_hwfn, 275 "Illegal write by chip to [%08x:%08x] blocked.\n" 276 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 277 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 278 addr_hi, addr_lo, details, 279 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 280 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 281 GET_FIELD(details, 282 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 283 tmp, 284 GET_FIELD(tmp, 285 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 286 GET_FIELD(tmp, 287 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 288 GET_FIELD(tmp, 289 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 290 } 291 292 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 293 PGLUE_B_REG_TX_ERR_RD_DETAILS2); 294 if (tmp & PGLUE_ATTENTION_RD_VALID) { 295 u32 addr_lo, addr_hi, details; 296 297 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 298 PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 299 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 300 PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 301 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 302 PGLUE_B_REG_TX_ERR_RD_DETAILS); 303 304 DP_INFO(p_hwfn, 305 "Illegal read by chip from [%08x:%08x] blocked.\n" 306 " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 307 " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 308 addr_hi, addr_lo, details, 309 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 310 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 311 GET_FIELD(details, 312 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 313 tmp, 314 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 315 : 0, 316 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 317 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 318 : 0); 319 } 320 321 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 322 PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 323 if (tmp & PGLUE_ATTENTION_ICPL_VALID) 324 DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp); 325 326 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 327 PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 328 if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 329 u32 addr_hi, addr_lo; 330 331 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 332 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 333 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 334 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 335 336 DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n", 337 tmp, addr_hi, addr_lo); 338 } 339 340 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 341 PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 342 if (tmp & PGLUE_ATTENTION_ILT_VALID) { 343 u32 addr_hi, addr_lo, details; 344 345 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 346 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 347 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 348 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 349 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 350 PGLUE_B_REG_VF_ILT_ERR_DETAILS); 351 352 DP_INFO(p_hwfn, 353 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 354 details, tmp, addr_hi, addr_lo); 355 } 356 357 /* Clear the indications */ 358 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 359 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 360 361 return 0; 362 } 363 364 #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 365 #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 366 #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 367 #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 368 static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 369 { 370 u32 reason; 371 372 reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) & 373 QED_DORQ_ATTENTION_REASON_MASK; 374 if (reason) { 375 u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 376 DORQ_REG_DB_DROP_DETAILS); 377 378 DP_INFO(p_hwfn->cdev, 379 "DORQ db_drop: address 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n", 380 qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 381 DORQ_REG_DB_DROP_DETAILS_ADDRESS), 382 (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK), 383 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 384 reason); 385 } 386 387 return -EINVAL; 388 } 389 390 /* Instead of major changes to the data-structure, we have a some 'special' 391 * identifiers for sources that changed meaning between adapters. 392 */ 393 enum aeu_invert_reg_special_type { 394 AEU_INVERT_REG_SPECIAL_CNIG_0, 395 AEU_INVERT_REG_SPECIAL_CNIG_1, 396 AEU_INVERT_REG_SPECIAL_CNIG_2, 397 AEU_INVERT_REG_SPECIAL_CNIG_3, 398 AEU_INVERT_REG_SPECIAL_MAX, 399 }; 400 401 static struct aeu_invert_reg_bit 402 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 403 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 404 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 405 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 406 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 407 }; 408 409 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 410 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 411 { 412 { /* After Invert 1 */ 413 {"GPIO0 function%d", 414 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 415 } 416 }, 417 418 { 419 { /* After Invert 2 */ 420 {"PGLUE config_space", ATTENTION_SINGLE, 421 NULL, MAX_BLOCK_ID}, 422 {"PGLUE misc_flr", ATTENTION_SINGLE, 423 NULL, MAX_BLOCK_ID}, 424 {"PGLUE B RBC", ATTENTION_PAR_INT, 425 qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 426 {"PGLUE misc_mctp", ATTENTION_SINGLE, 427 NULL, MAX_BLOCK_ID}, 428 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 429 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 430 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 431 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 432 (1 << ATTENTION_OFFSET_SHIFT), 433 NULL, MAX_BLOCK_ID}, 434 {"PCIE glue/PXP VPD %d", 435 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 436 } 437 }, 438 439 { 440 { /* After Invert 3 */ 441 {"General Attention %d", 442 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 443 } 444 }, 445 446 { 447 { /* After Invert 4 */ 448 {"General Attention 32", ATTENTION_SINGLE, 449 NULL, MAX_BLOCK_ID}, 450 {"General Attention %d", 451 (2 << ATTENTION_LENGTH_SHIFT) | 452 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 453 {"General Attention 35", ATTENTION_SINGLE, 454 NULL, MAX_BLOCK_ID}, 455 {"NWS Parity", 456 ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 457 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 458 NULL, BLOCK_NWS}, 459 {"NWS Interrupt", 460 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 461 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 462 NULL, BLOCK_NWS}, 463 {"NWM Parity", 464 ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 465 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 466 NULL, BLOCK_NWM}, 467 {"NWM Interrupt", 468 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 469 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 470 NULL, BLOCK_NWM}, 471 {"MCP CPU", ATTENTION_SINGLE, 472 qed_mcp_attn_cb, MAX_BLOCK_ID}, 473 {"MCP Watchdog timer", ATTENTION_SINGLE, 474 NULL, MAX_BLOCK_ID}, 475 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 476 {"AVS stop status ready", ATTENTION_SINGLE, 477 NULL, MAX_BLOCK_ID}, 478 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 479 {"MSTAT per-path", ATTENTION_PAR_INT, 480 NULL, MAX_BLOCK_ID}, 481 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 482 NULL, MAX_BLOCK_ID}, 483 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 484 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 485 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 486 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 487 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 488 } 489 }, 490 491 { 492 { /* After Invert 5 */ 493 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 494 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 495 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 496 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 497 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 498 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 499 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 500 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 501 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 502 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 503 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 504 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 505 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 506 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 507 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 508 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 509 } 510 }, 511 512 { 513 { /* After Invert 6 */ 514 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 515 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 516 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 517 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 518 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 519 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 520 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 521 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 522 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 523 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 524 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 525 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 526 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 527 {"DORQ", ATTENTION_PAR_INT, 528 qed_dorq_attn_cb, BLOCK_DORQ}, 529 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 530 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 531 } 532 }, 533 534 { 535 { /* After Invert 7 */ 536 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 537 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 538 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 539 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 540 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 541 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 542 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 543 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 544 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 545 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 546 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 547 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 548 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 549 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 550 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 551 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 552 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 553 } 554 }, 555 556 { 557 { /* After Invert 8 */ 558 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 559 NULL, BLOCK_PSWRQ2}, 560 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 561 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 562 NULL, BLOCK_PSWWR2}, 563 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 564 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 565 NULL, BLOCK_PSWRD2}, 566 {"PSWHST", ATTENTION_PAR_INT, 567 qed_pswhst_attn_cb, BLOCK_PSWHST}, 568 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 569 NULL, BLOCK_PSWHST2}, 570 {"GRC", ATTENTION_PAR_INT, 571 qed_grc_attn_cb, BLOCK_GRC}, 572 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 573 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 574 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 575 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 576 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 577 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 578 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 579 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 580 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 581 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 582 NULL, BLOCK_PGLCS}, 583 {"PERST_B assertion", ATTENTION_SINGLE, 584 NULL, MAX_BLOCK_ID}, 585 {"PERST_B deassertion", ATTENTION_SINGLE, 586 NULL, MAX_BLOCK_ID}, 587 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 588 NULL, MAX_BLOCK_ID}, 589 } 590 }, 591 592 { 593 { /* After Invert 9 */ 594 {"MCP Latched memory", ATTENTION_PAR, 595 NULL, MAX_BLOCK_ID}, 596 {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 597 NULL, MAX_BLOCK_ID}, 598 {"MCP Latched ump_tx", ATTENTION_PAR, 599 NULL, MAX_BLOCK_ID}, 600 {"MCP Latched scratchpad", ATTENTION_PAR, 601 NULL, MAX_BLOCK_ID}, 602 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 603 NULL, MAX_BLOCK_ID}, 604 } 605 }, 606 }; 607 608 static struct aeu_invert_reg_bit * 609 qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 610 struct aeu_invert_reg_bit *p_bit) 611 { 612 if (!QED_IS_BB(p_hwfn->cdev)) 613 return p_bit; 614 615 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 616 return p_bit; 617 618 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 619 ATTENTION_BB_SHIFT]; 620 } 621 622 static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 623 struct aeu_invert_reg_bit *p_bit) 624 { 625 return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 626 ATTENTION_PARITY); 627 } 628 629 #define ATTN_STATE_BITS (0xfff) 630 #define ATTN_BITS_MASKABLE (0x3ff) 631 struct qed_sb_attn_info { 632 /* Virtual & Physical address of the SB */ 633 struct atten_status_block *sb_attn; 634 dma_addr_t sb_phys; 635 636 /* Last seen running index */ 637 u16 index; 638 639 /* A mask of the AEU bits resulting in a parity error */ 640 u32 parity_mask[NUM_ATTN_REGS]; 641 642 /* A pointer to the attention description structure */ 643 struct aeu_invert_reg *p_aeu_desc; 644 645 /* Previously asserted attentions, which are still unasserted */ 646 u16 known_attn; 647 648 /* Cleanup address for the link's general hw attention */ 649 u32 mfw_attn_addr; 650 }; 651 652 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 653 struct qed_sb_attn_info *p_sb_desc) 654 { 655 u16 rc = 0, index; 656 657 /* Make certain HW write took affect */ 658 mmiowb(); 659 660 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 661 if (p_sb_desc->index != index) { 662 p_sb_desc->index = index; 663 rc = QED_SB_ATT_IDX; 664 } 665 666 /* Make certain we got a consistent view with HW */ 667 mmiowb(); 668 669 return rc; 670 } 671 672 /** 673 * @brief qed_int_assertion - handles asserted attention bits 674 * 675 * @param p_hwfn 676 * @param asserted_bits newly asserted bits 677 * @return int 678 */ 679 static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 680 { 681 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 682 u32 igu_mask; 683 684 /* Mask the source of the attention in the IGU */ 685 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 686 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 687 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 688 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 689 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 690 691 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 692 "inner known ATTN state: 0x%04x --> 0x%04x\n", 693 sb_attn_sw->known_attn, 694 sb_attn_sw->known_attn | asserted_bits); 695 sb_attn_sw->known_attn |= asserted_bits; 696 697 /* Handle MCP events */ 698 if (asserted_bits & 0x100) { 699 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 700 /* Clean the MCP attention */ 701 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 702 sb_attn_sw->mfw_attn_addr, 0); 703 } 704 705 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 706 GTT_BAR0_MAP_REG_IGU_CMD + 707 ((IGU_CMD_ATTN_BIT_SET_UPPER - 708 IGU_CMD_INT_ACK_BASE) << 3), 709 (u32)asserted_bits); 710 711 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 712 asserted_bits); 713 714 return 0; 715 } 716 717 static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 718 enum block_id id, 719 enum dbg_attn_type type, bool b_clear) 720 { 721 struct dbg_attn_block_result attn_results; 722 enum dbg_status status; 723 724 memset(&attn_results, 0, sizeof(attn_results)); 725 726 status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 727 b_clear, &attn_results); 728 if (status != DBG_STATUS_OK) 729 DP_NOTICE(p_hwfn, 730 "Failed to parse attention information [status: %s]\n", 731 qed_dbg_get_status_str(status)); 732 else 733 qed_dbg_parse_attn(p_hwfn, &attn_results); 734 } 735 736 /** 737 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 738 * cause of the attention 739 * 740 * @param p_hwfn 741 * @param p_aeu - descriptor of an AEU bit which caused the attention 742 * @param aeu_en_reg - register offset of the AEU enable reg. which configured 743 * this bit to this group. 744 * @param bit_index - index of this bit in the aeu_en_reg 745 * 746 * @return int 747 */ 748 static int 749 qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 750 struct aeu_invert_reg_bit *p_aeu, 751 u32 aeu_en_reg, 752 const char *p_bit_name, u32 bitmask) 753 { 754 bool b_fatal = false; 755 int rc = -EINVAL; 756 u32 val; 757 758 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 759 p_bit_name, bitmask); 760 761 /* Call callback before clearing the interrupt status */ 762 if (p_aeu->cb) { 763 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 764 p_bit_name); 765 rc = p_aeu->cb(p_hwfn); 766 } 767 768 if (rc) 769 b_fatal = true; 770 771 /* Print HW block interrupt registers */ 772 if (p_aeu->block_index != MAX_BLOCK_ID) 773 qed_int_attn_print(p_hwfn, p_aeu->block_index, 774 ATTN_TYPE_INTERRUPT, !b_fatal); 775 776 777 /* If the attention is benign, no need to prevent it */ 778 if (!rc) 779 goto out; 780 781 /* Prevent this Attention from being asserted in the future */ 782 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 783 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 784 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 785 p_bit_name); 786 787 out: 788 return rc; 789 } 790 791 /** 792 * @brief qed_int_deassertion_parity - handle a single parity AEU source 793 * 794 * @param p_hwfn 795 * @param p_aeu - descriptor of an AEU bit which caused the parity 796 * @param aeu_en_reg - address of the AEU enable register 797 * @param bit_index 798 */ 799 static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 800 struct aeu_invert_reg_bit *p_aeu, 801 u32 aeu_en_reg, u8 bit_index) 802 { 803 u32 block_id = p_aeu->block_index, mask, val; 804 805 DP_NOTICE(p_hwfn->cdev, 806 "%s parity attention is set [address 0x%08x, bit %d]\n", 807 p_aeu->bit_name, aeu_en_reg, bit_index); 808 809 if (block_id != MAX_BLOCK_ID) { 810 qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 811 812 /* In BB, there's a single parity bit for several blocks */ 813 if (block_id == BLOCK_BTB) { 814 qed_int_attn_print(p_hwfn, BLOCK_OPTE, 815 ATTN_TYPE_PARITY, false); 816 qed_int_attn_print(p_hwfn, BLOCK_MCP, 817 ATTN_TYPE_PARITY, false); 818 } 819 } 820 821 /* Prevent this parity error from being re-asserted */ 822 mask = ~BIT(bit_index); 823 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 824 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 825 DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 826 p_aeu->bit_name); 827 } 828 829 /** 830 * @brief - handles deassertion of previously asserted attentions. 831 * 832 * @param p_hwfn 833 * @param deasserted_bits - newly deasserted bits 834 * @return int 835 * 836 */ 837 static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 838 u16 deasserted_bits) 839 { 840 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 841 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 842 u8 i, j, k, bit_idx; 843 int rc = 0; 844 845 /* Read the attention registers in the AEU */ 846 for (i = 0; i < NUM_ATTN_REGS; i++) { 847 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 848 MISC_REG_AEU_AFTER_INVERT_1_IGU + 849 i * 0x4); 850 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 851 "Deasserted bits [%d]: %08x\n", 852 i, aeu_inv_arr[i]); 853 } 854 855 /* Find parity attentions first */ 856 for (i = 0; i < NUM_ATTN_REGS; i++) { 857 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 858 u32 parities; 859 860 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 861 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 862 863 /* Skip register in which no parity bit is currently set */ 864 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 865 if (!parities) 866 continue; 867 868 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 869 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 870 871 if (qed_int_is_parity_flag(p_hwfn, p_bit) && 872 !!(parities & BIT(bit_idx))) 873 qed_int_deassertion_parity(p_hwfn, p_bit, 874 aeu_en, bit_idx); 875 876 bit_idx += ATTENTION_LENGTH(p_bit->flags); 877 } 878 } 879 880 /* Find non-parity cause for attention and act */ 881 for (k = 0; k < MAX_ATTN_GRPS; k++) { 882 struct aeu_invert_reg_bit *p_aeu; 883 884 /* Handle only groups whose attention is currently deasserted */ 885 if (!(deasserted_bits & (1 << k))) 886 continue; 887 888 for (i = 0; i < NUM_ATTN_REGS; i++) { 889 u32 bits; 890 891 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 892 i * sizeof(u32) + 893 k * sizeof(u32) * NUM_ATTN_REGS; 894 895 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 896 bits = aeu_inv_arr[i] & en; 897 898 /* Skip if no bit from this group is currently set */ 899 if (!bits) 900 continue; 901 902 /* Find all set bits from current register which belong 903 * to current group, making them responsible for the 904 * previous assertion. 905 */ 906 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 907 long unsigned int bitmask; 908 u8 bit, bit_len; 909 910 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 911 p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 912 913 bit = bit_idx; 914 bit_len = ATTENTION_LENGTH(p_aeu->flags); 915 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 916 /* Skip Parity */ 917 bit++; 918 bit_len--; 919 } 920 921 bitmask = bits & (((1 << bit_len) - 1) << bit); 922 bitmask >>= bit; 923 924 if (bitmask) { 925 u32 flags = p_aeu->flags; 926 char bit_name[30]; 927 u8 num; 928 929 num = (u8)find_first_bit(&bitmask, 930 bit_len); 931 932 /* Some bits represent more than a 933 * a single interrupt. Correctly print 934 * their name. 935 */ 936 if (ATTENTION_LENGTH(flags) > 2 || 937 ((flags & ATTENTION_PAR_INT) && 938 ATTENTION_LENGTH(flags) > 1)) 939 snprintf(bit_name, 30, 940 p_aeu->bit_name, num); 941 else 942 strncpy(bit_name, 943 p_aeu->bit_name, 30); 944 945 /* We now need to pass bitmask in its 946 * correct position. 947 */ 948 bitmask <<= bit; 949 950 /* Handle source of the attention */ 951 qed_int_deassertion_aeu_bit(p_hwfn, 952 p_aeu, 953 aeu_en, 954 bit_name, 955 bitmask); 956 } 957 958 bit_idx += ATTENTION_LENGTH(p_aeu->flags); 959 } 960 } 961 } 962 963 /* Clear IGU indication for the deasserted bits */ 964 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 965 GTT_BAR0_MAP_REG_IGU_CMD + 966 ((IGU_CMD_ATTN_BIT_CLR_UPPER - 967 IGU_CMD_INT_ACK_BASE) << 3), 968 ~((u32)deasserted_bits)); 969 970 /* Unmask deasserted attentions in IGU */ 971 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 972 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 973 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 974 975 /* Clear deassertion from inner state */ 976 sb_attn_sw->known_attn &= ~deasserted_bits; 977 978 return rc; 979 } 980 981 static int qed_int_attentions(struct qed_hwfn *p_hwfn) 982 { 983 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 984 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 985 u32 attn_bits = 0, attn_acks = 0; 986 u16 asserted_bits, deasserted_bits; 987 __le16 index; 988 int rc = 0; 989 990 /* Read current attention bits/acks - safeguard against attentions 991 * by guaranting work on a synchronized timeframe 992 */ 993 do { 994 index = p_sb_attn->sb_index; 995 attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 996 attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 997 } while (index != p_sb_attn->sb_index); 998 p_sb_attn->sb_index = index; 999 1000 /* Attention / Deassertion are meaningful (and in correct state) 1001 * only when they differ and consistent with known state - deassertion 1002 * when previous attention & current ack, and assertion when current 1003 * attention with no previous attention 1004 */ 1005 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1006 ~p_sb_attn_sw->known_attn; 1007 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1008 p_sb_attn_sw->known_attn; 1009 1010 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1011 DP_INFO(p_hwfn, 1012 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1013 index, attn_bits, attn_acks, asserted_bits, 1014 deasserted_bits, p_sb_attn_sw->known_attn); 1015 } else if (asserted_bits == 0x100) { 1016 DP_INFO(p_hwfn, "MFW indication via attention\n"); 1017 } else { 1018 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1019 "MFW indication [deassertion]\n"); 1020 } 1021 1022 if (asserted_bits) { 1023 rc = qed_int_assertion(p_hwfn, asserted_bits); 1024 if (rc) 1025 return rc; 1026 } 1027 1028 if (deasserted_bits) 1029 rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1030 1031 return rc; 1032 } 1033 1034 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 1035 void __iomem *igu_addr, u32 ack_cons) 1036 { 1037 struct igu_prod_cons_update igu_ack = { 0 }; 1038 1039 igu_ack.sb_id_and_flags = 1040 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1041 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1042 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1043 (IGU_SEG_ACCESS_ATTN << 1044 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1045 1046 DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1047 1048 /* Both segments (interrupts & acks) are written to same place address; 1049 * Need to guarantee all commands will be received (in-order) by HW. 1050 */ 1051 mmiowb(); 1052 barrier(); 1053 } 1054 1055 void qed_int_sp_dpc(unsigned long hwfn_cookie) 1056 { 1057 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1058 struct qed_pi_info *pi_info = NULL; 1059 struct qed_sb_attn_info *sb_attn; 1060 struct qed_sb_info *sb_info; 1061 int arr_size; 1062 u16 rc = 0; 1063 1064 if (!p_hwfn->p_sp_sb) { 1065 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1066 return; 1067 } 1068 1069 sb_info = &p_hwfn->p_sp_sb->sb_info; 1070 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1071 if (!sb_info) { 1072 DP_ERR(p_hwfn->cdev, 1073 "Status block is NULL - cannot ack interrupts\n"); 1074 return; 1075 } 1076 1077 if (!p_hwfn->p_sb_attn) { 1078 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1079 return; 1080 } 1081 sb_attn = p_hwfn->p_sb_attn; 1082 1083 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1084 p_hwfn, p_hwfn->my_id); 1085 1086 /* Disable ack for def status block. Required both for msix + 1087 * inta in non-mask mode, in inta does no harm. 1088 */ 1089 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1090 1091 /* Gather Interrupts/Attentions information */ 1092 if (!sb_info->sb_virt) { 1093 DP_ERR(p_hwfn->cdev, 1094 "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1095 } else { 1096 u32 tmp_index = sb_info->sb_ack; 1097 1098 rc = qed_sb_update_sb_idx(sb_info); 1099 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1100 "Interrupt indices: 0x%08x --> 0x%08x\n", 1101 tmp_index, sb_info->sb_ack); 1102 } 1103 1104 if (!sb_attn || !sb_attn->sb_attn) { 1105 DP_ERR(p_hwfn->cdev, 1106 "Attentions Status block is NULL - cannot check for new attentions!\n"); 1107 } else { 1108 u16 tmp_index = sb_attn->index; 1109 1110 rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1111 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1112 "Attention indices: 0x%08x --> 0x%08x\n", 1113 tmp_index, sb_attn->index); 1114 } 1115 1116 /* Check if we expect interrupts at this time. if not just ack them */ 1117 if (!(rc & QED_SB_EVENT_MASK)) { 1118 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1119 return; 1120 } 1121 1122 /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1123 if (!p_hwfn->p_dpc_ptt) { 1124 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1125 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1126 return; 1127 } 1128 1129 if (rc & QED_SB_ATT_IDX) 1130 qed_int_attentions(p_hwfn); 1131 1132 if (rc & QED_SB_IDX) { 1133 int pi; 1134 1135 /* Look for a free index */ 1136 for (pi = 0; pi < arr_size; pi++) { 1137 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1138 if (pi_info->comp_cb) 1139 pi_info->comp_cb(p_hwfn, pi_info->cookie); 1140 } 1141 } 1142 1143 if (sb_attn && (rc & QED_SB_ATT_IDX)) 1144 /* This should be done before the interrupts are enabled, 1145 * since otherwise a new attention will be generated. 1146 */ 1147 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1148 1149 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1150 } 1151 1152 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1153 { 1154 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1155 1156 if (!p_sb) 1157 return; 1158 1159 if (p_sb->sb_attn) 1160 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1161 SB_ATTN_ALIGNED_SIZE(p_hwfn), 1162 p_sb->sb_attn, p_sb->sb_phys); 1163 kfree(p_sb); 1164 p_hwfn->p_sb_attn = NULL; 1165 } 1166 1167 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1168 struct qed_ptt *p_ptt) 1169 { 1170 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1171 1172 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1173 1174 sb_info->index = 0; 1175 sb_info->known_attn = 0; 1176 1177 /* Configure Attention Status Block in IGU */ 1178 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1179 lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1180 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1181 upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1182 } 1183 1184 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1185 struct qed_ptt *p_ptt, 1186 void *sb_virt_addr, dma_addr_t sb_phy_addr) 1187 { 1188 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1189 int i, j, k; 1190 1191 sb_info->sb_attn = sb_virt_addr; 1192 sb_info->sb_phys = sb_phy_addr; 1193 1194 /* Set the pointer to the AEU descriptors */ 1195 sb_info->p_aeu_desc = aeu_descs; 1196 1197 /* Calculate Parity Masks */ 1198 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 1199 for (i = 0; i < NUM_ATTN_REGS; i++) { 1200 /* j is array index, k is bit index */ 1201 for (j = 0, k = 0; k < 32; j++) { 1202 struct aeu_invert_reg_bit *p_aeu; 1203 1204 p_aeu = &aeu_descs[i].bits[j]; 1205 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 1206 sb_info->parity_mask[i] |= 1 << k; 1207 1208 k += ATTENTION_LENGTH(p_aeu->flags); 1209 } 1210 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1211 "Attn Mask [Reg %d]: 0x%08x\n", 1212 i, sb_info->parity_mask[i]); 1213 } 1214 1215 /* Set the address of cleanup for the mcp attention */ 1216 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1217 MISC_REG_AEU_GENERAL_ATTN_0; 1218 1219 qed_int_sb_attn_setup(p_hwfn, p_ptt); 1220 } 1221 1222 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1223 struct qed_ptt *p_ptt) 1224 { 1225 struct qed_dev *cdev = p_hwfn->cdev; 1226 struct qed_sb_attn_info *p_sb; 1227 dma_addr_t p_phys = 0; 1228 void *p_virt; 1229 1230 /* SB struct */ 1231 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 1232 if (!p_sb) 1233 return -ENOMEM; 1234 1235 /* SB ring */ 1236 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1237 SB_ATTN_ALIGNED_SIZE(p_hwfn), 1238 &p_phys, GFP_KERNEL); 1239 1240 if (!p_virt) { 1241 kfree(p_sb); 1242 return -ENOMEM; 1243 } 1244 1245 /* Attention setup */ 1246 p_hwfn->p_sb_attn = p_sb; 1247 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1248 1249 return 0; 1250 } 1251 1252 /* coalescing timeout = timeset << (timer_res + 1) */ 1253 #define QED_CAU_DEF_RX_USECS 24 1254 #define QED_CAU_DEF_TX_USECS 48 1255 1256 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1257 struct cau_sb_entry *p_sb_entry, 1258 u8 pf_id, u16 vf_number, u8 vf_valid) 1259 { 1260 struct qed_dev *cdev = p_hwfn->cdev; 1261 u32 cau_state; 1262 u8 timer_res; 1263 1264 memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1265 1266 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1267 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1268 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1269 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1270 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1271 1272 cau_state = CAU_HC_DISABLE_STATE; 1273 1274 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1275 cau_state = CAU_HC_ENABLE_STATE; 1276 if (!cdev->rx_coalesce_usecs) 1277 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 1278 if (!cdev->tx_coalesce_usecs) 1279 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1280 } 1281 1282 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1283 if (cdev->rx_coalesce_usecs <= 0x7F) 1284 timer_res = 0; 1285 else if (cdev->rx_coalesce_usecs <= 0xFF) 1286 timer_res = 1; 1287 else 1288 timer_res = 2; 1289 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1290 1291 if (cdev->tx_coalesce_usecs <= 0x7F) 1292 timer_res = 0; 1293 else if (cdev->tx_coalesce_usecs <= 0xFF) 1294 timer_res = 1; 1295 else 1296 timer_res = 2; 1297 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1298 1299 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1300 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1301 } 1302 1303 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1304 struct qed_ptt *p_ptt, 1305 dma_addr_t sb_phys, 1306 u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1307 { 1308 struct cau_sb_entry sb_entry; 1309 1310 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1311 vf_number, vf_valid); 1312 1313 if (p_hwfn->hw_init_done) { 1314 /* Wide-bus, initialize via DMAE */ 1315 u64 phys_addr = (u64)sb_phys; 1316 1317 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 1318 CAU_REG_SB_ADDR_MEMORY + 1319 igu_sb_id * sizeof(u64), 2, 0); 1320 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 1321 CAU_REG_SB_VAR_MEMORY + 1322 igu_sb_id * sizeof(u64), 2, 0); 1323 } else { 1324 /* Initialize Status Block Address */ 1325 STORE_RT_REG_AGG(p_hwfn, 1326 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1327 igu_sb_id * 2, 1328 sb_phys); 1329 1330 STORE_RT_REG_AGG(p_hwfn, 1331 CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1332 igu_sb_id * 2, 1333 sb_entry); 1334 } 1335 1336 /* Configure pi coalescing if set */ 1337 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1338 u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1339 u8 timeset, timer_res; 1340 u8 i; 1341 1342 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1343 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1344 timer_res = 0; 1345 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1346 timer_res = 1; 1347 else 1348 timer_res = 2; 1349 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1350 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 1351 QED_COAL_RX_STATE_MACHINE, timeset); 1352 1353 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1354 timer_res = 0; 1355 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1356 timer_res = 1; 1357 else 1358 timer_res = 2; 1359 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1360 for (i = 0; i < num_tc; i++) { 1361 qed_int_cau_conf_pi(p_hwfn, p_ptt, 1362 igu_sb_id, TX_PI(i), 1363 QED_COAL_TX_STATE_MACHINE, 1364 timeset); 1365 } 1366 } 1367 } 1368 1369 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 1370 struct qed_ptt *p_ptt, 1371 u16 igu_sb_id, 1372 u32 pi_index, 1373 enum qed_coalescing_fsm coalescing_fsm, 1374 u8 timeset) 1375 { 1376 struct cau_pi_entry pi_entry; 1377 u32 sb_offset, pi_offset; 1378 1379 if (IS_VF(p_hwfn->cdev)) 1380 return; 1381 1382 sb_offset = igu_sb_id * PIS_PER_SB; 1383 memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 1384 1385 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 1386 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 1387 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 1388 else 1389 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 1390 1391 pi_offset = sb_offset + pi_index; 1392 if (p_hwfn->hw_init_done) { 1393 qed_wr(p_hwfn, p_ptt, 1394 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 1395 *((u32 *)&(pi_entry))); 1396 } else { 1397 STORE_RT_REG(p_hwfn, 1398 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 1399 *((u32 *)&(pi_entry))); 1400 } 1401 } 1402 1403 void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 1404 struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1405 { 1406 /* zero status block and ack counter */ 1407 sb_info->sb_ack = 0; 1408 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1409 1410 if (IS_PF(p_hwfn->cdev)) 1411 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1412 sb_info->igu_sb_id, 0, 0); 1413 } 1414 1415 /** 1416 * @brief qed_get_igu_sb_id - given a sw sb_id return the 1417 * igu_sb_id 1418 * 1419 * @param p_hwfn 1420 * @param sb_id 1421 * 1422 * @return u16 1423 */ 1424 static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1425 { 1426 u16 igu_sb_id; 1427 1428 /* Assuming continuous set of IGU SBs dedicated for given PF */ 1429 if (sb_id == QED_SP_SB_ID) 1430 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 1431 else if (IS_PF(p_hwfn->cdev)) 1432 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb; 1433 else 1434 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1435 1436 if (sb_id == QED_SP_SB_ID) 1437 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1438 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1439 else 1440 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1441 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1442 1443 return igu_sb_id; 1444 } 1445 1446 int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1447 struct qed_ptt *p_ptt, 1448 struct qed_sb_info *sb_info, 1449 void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1450 { 1451 sb_info->sb_virt = sb_virt_addr; 1452 sb_info->sb_phys = sb_phy_addr; 1453 1454 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1455 1456 if (sb_id != QED_SP_SB_ID) { 1457 p_hwfn->sbs_info[sb_id] = sb_info; 1458 p_hwfn->num_sbs++; 1459 } 1460 1461 sb_info->cdev = p_hwfn->cdev; 1462 1463 /* The igu address will hold the absolute address that needs to be 1464 * written to for a specific status block 1465 */ 1466 if (IS_PF(p_hwfn->cdev)) { 1467 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1468 GTT_BAR0_MAP_REG_IGU_CMD + 1469 (sb_info->igu_sb_id << 3); 1470 } else { 1471 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1472 PXP_VF_BAR0_START_IGU + 1473 ((IGU_CMD_INT_ACK_BASE + 1474 sb_info->igu_sb_id) << 3); 1475 } 1476 1477 sb_info->flags |= QED_SB_INFO_INIT; 1478 1479 qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1480 1481 return 0; 1482 } 1483 1484 int qed_int_sb_release(struct qed_hwfn *p_hwfn, 1485 struct qed_sb_info *sb_info, u16 sb_id) 1486 { 1487 if (sb_id == QED_SP_SB_ID) { 1488 DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 1489 return -EINVAL; 1490 } 1491 1492 /* zero status block and ack counter */ 1493 sb_info->sb_ack = 0; 1494 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1495 1496 if (p_hwfn->sbs_info[sb_id] != NULL) { 1497 p_hwfn->sbs_info[sb_id] = NULL; 1498 p_hwfn->num_sbs--; 1499 } 1500 1501 return 0; 1502 } 1503 1504 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1505 { 1506 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1507 1508 if (!p_sb) 1509 return; 1510 1511 if (p_sb->sb_info.sb_virt) 1512 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1513 SB_ALIGNED_SIZE(p_hwfn), 1514 p_sb->sb_info.sb_virt, 1515 p_sb->sb_info.sb_phys); 1516 kfree(p_sb); 1517 p_hwfn->p_sp_sb = NULL; 1518 } 1519 1520 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1521 { 1522 struct qed_sb_sp_info *p_sb; 1523 dma_addr_t p_phys = 0; 1524 void *p_virt; 1525 1526 /* SB struct */ 1527 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 1528 if (!p_sb) 1529 return -ENOMEM; 1530 1531 /* SB ring */ 1532 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1533 SB_ALIGNED_SIZE(p_hwfn), 1534 &p_phys, GFP_KERNEL); 1535 if (!p_virt) { 1536 kfree(p_sb); 1537 return -ENOMEM; 1538 } 1539 1540 /* Status Block setup */ 1541 p_hwfn->p_sp_sb = p_sb; 1542 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1543 p_phys, QED_SP_SB_ID); 1544 1545 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1546 1547 return 0; 1548 } 1549 1550 int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1551 qed_int_comp_cb_t comp_cb, 1552 void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1553 { 1554 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1555 int rc = -ENOMEM; 1556 u8 pi; 1557 1558 /* Look for a free index */ 1559 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 1560 if (p_sp_sb->pi_info_arr[pi].comp_cb) 1561 continue; 1562 1563 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1564 p_sp_sb->pi_info_arr[pi].cookie = cookie; 1565 *sb_idx = pi; 1566 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 1567 rc = 0; 1568 break; 1569 } 1570 1571 return rc; 1572 } 1573 1574 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1575 { 1576 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1577 1578 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 1579 return -ENOMEM; 1580 1581 p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1582 p_sp_sb->pi_info_arr[pi].cookie = NULL; 1583 1584 return 0; 1585 } 1586 1587 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1588 { 1589 return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1590 } 1591 1592 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 1593 struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1594 { 1595 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1596 1597 p_hwfn->cdev->int_mode = int_mode; 1598 switch (p_hwfn->cdev->int_mode) { 1599 case QED_INT_MODE_INTA: 1600 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1601 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1602 break; 1603 1604 case QED_INT_MODE_MSI: 1605 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1606 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1607 break; 1608 1609 case QED_INT_MODE_MSIX: 1610 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1611 break; 1612 case QED_INT_MODE_POLL: 1613 break; 1614 } 1615 1616 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1617 } 1618 1619 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1620 enum qed_int_mode int_mode) 1621 { 1622 int rc = 0; 1623 1624 /* Configure AEU signal change to produce attentions */ 1625 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1626 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1627 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 1628 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1629 1630 /* Flush the writes to IGU */ 1631 mmiowb(); 1632 1633 /* Unmask AEU signals toward IGU */ 1634 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1635 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 1636 rc = qed_slowpath_irq_req(p_hwfn); 1637 if (rc) { 1638 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 1639 return -EINVAL; 1640 } 1641 p_hwfn->b_int_requested = true; 1642 } 1643 /* Enable interrupt Generation */ 1644 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 1645 p_hwfn->b_int_enabled = 1; 1646 1647 return rc; 1648 } 1649 1650 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1651 { 1652 p_hwfn->b_int_enabled = 0; 1653 1654 if (IS_VF(p_hwfn->cdev)) 1655 return; 1656 1657 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1658 } 1659 1660 #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1661 static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1662 struct qed_ptt *p_ptt, 1663 u32 sb_id, bool cleanup_set, u16 opaque_fid) 1664 { 1665 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1666 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id; 1667 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1668 1669 /* Set the data field */ 1670 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1671 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1672 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1673 1674 /* Set the control register */ 1675 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1676 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1677 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1678 1679 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1680 1681 barrier(); 1682 1683 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1684 1685 /* Flush the write to IGU */ 1686 mmiowb(); 1687 1688 /* calculate where to read the status bit from */ 1689 sb_bit = 1 << (sb_id % 32); 1690 sb_bit_addr = sb_id / 32 * sizeof(u32); 1691 1692 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1693 1694 /* Now wait for the command to complete */ 1695 do { 1696 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1697 1698 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1699 break; 1700 1701 usleep_range(5000, 10000); 1702 } while (--sleep_cnt); 1703 1704 if (!sleep_cnt) 1705 DP_NOTICE(p_hwfn, 1706 "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1707 val, sb_id); 1708 } 1709 1710 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1711 struct qed_ptt *p_ptt, 1712 u32 sb_id, u16 opaque, bool b_set) 1713 { 1714 int pi, i; 1715 1716 /* Set */ 1717 if (b_set) 1718 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque); 1719 1720 /* Clear */ 1721 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque); 1722 1723 /* Wait for the IGU SB to cleanup */ 1724 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1725 u32 val; 1726 1727 val = qed_rd(p_hwfn, p_ptt, 1728 IGU_REG_WRITE_DONE_PENDING + ((sb_id / 32) * 4)); 1729 if (val & (1 << (sb_id % 32))) 1730 usleep_range(10, 20); 1731 else 1732 break; 1733 } 1734 if (i == IGU_CLEANUP_SLEEP_LENGTH) 1735 DP_NOTICE(p_hwfn, 1736 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1737 sb_id); 1738 1739 /* Clear the CAU for the SB */ 1740 for (pi = 0; pi < 12; pi++) 1741 qed_wr(p_hwfn, p_ptt, 1742 CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0); 1743 } 1744 1745 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1746 struct qed_ptt *p_ptt, 1747 bool b_set, bool b_slowpath) 1748 { 1749 u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb; 1750 u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt; 1751 u32 sb_id = 0, val = 0; 1752 1753 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1754 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1755 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1756 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1757 1758 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1759 "IGU cleaning SBs [%d,...,%d]\n", 1760 igu_base_sb, igu_base_sb + igu_sb_cnt - 1); 1761 1762 for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++) 1763 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 1764 p_hwfn->hw_info.opaque_fid, 1765 b_set); 1766 1767 if (!b_slowpath) 1768 return; 1769 1770 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 1771 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1772 "IGU cleaning slowpath SB [%d]\n", sb_id); 1773 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 1774 p_hwfn->hw_info.opaque_fid, b_set); 1775 } 1776 1777 static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 1778 struct qed_ptt *p_ptt, u16 sb_id) 1779 { 1780 u32 val = qed_rd(p_hwfn, p_ptt, 1781 IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id); 1782 struct qed_igu_block *p_block; 1783 1784 p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id]; 1785 1786 /* stop scanning when hit first invalid PF entry */ 1787 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 1788 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 1789 goto out; 1790 1791 /* Fill the block information */ 1792 p_block->status = QED_IGU_STATUS_VALID; 1793 p_block->function_id = GET_FIELD(val, 1794 IGU_MAPPING_LINE_FUNCTION_NUMBER); 1795 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 1796 p_block->vector_number = GET_FIELD(val, 1797 IGU_MAPPING_LINE_VECTOR_NUMBER); 1798 1799 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1800 "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n", 1801 sb_id, val, p_block->function_id, 1802 p_block->is_pf, p_block->vector_number); 1803 1804 out: 1805 return val; 1806 } 1807 1808 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1809 { 1810 struct qed_igu_info *p_igu_info; 1811 u32 val, min_vf = 0, max_vf = 0; 1812 u16 sb_id, last_iov_sb_id = 0; 1813 struct qed_igu_block *blk; 1814 u16 prev_sb_id = 0xFF; 1815 1816 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 1817 if (!p_hwfn->hw_info.p_igu_info) 1818 return -ENOMEM; 1819 1820 p_igu_info = p_hwfn->hw_info.p_igu_info; 1821 1822 /* Initialize base sb / sb cnt for PFs and VFs */ 1823 p_igu_info->igu_base_sb = 0xffff; 1824 p_igu_info->igu_sb_cnt = 0; 1825 p_igu_info->igu_dsb_id = 0xffff; 1826 p_igu_info->igu_base_sb_iov = 0xffff; 1827 1828 if (p_hwfn->cdev->p_iov_info) { 1829 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 1830 1831 min_vf = p_iov->first_vf_in_pf; 1832 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 1833 } 1834 1835 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1836 sb_id++) { 1837 blk = &p_igu_info->igu_map.igu_blocks[sb_id]; 1838 1839 val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id); 1840 1841 /* stop scanning when hit first invalid PF entry */ 1842 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 1843 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 1844 break; 1845 1846 if (blk->is_pf) { 1847 if (blk->function_id == p_hwfn->rel_pf_id) { 1848 blk->status |= QED_IGU_STATUS_PF; 1849 1850 if (blk->vector_number == 0) { 1851 if (p_igu_info->igu_dsb_id == 0xffff) 1852 p_igu_info->igu_dsb_id = sb_id; 1853 } else { 1854 if (p_igu_info->igu_base_sb == 1855 0xffff) { 1856 p_igu_info->igu_base_sb = sb_id; 1857 } else if (prev_sb_id != sb_id - 1) { 1858 DP_NOTICE(p_hwfn->cdev, 1859 "consecutive igu vectors for HWFN %x broken", 1860 p_hwfn->rel_pf_id); 1861 break; 1862 } 1863 prev_sb_id = sb_id; 1864 /* we don't count the default */ 1865 (p_igu_info->igu_sb_cnt)++; 1866 } 1867 } 1868 } else { 1869 if ((blk->function_id >= min_vf) && 1870 (blk->function_id < max_vf)) { 1871 /* Available for VFs of this PF */ 1872 if (p_igu_info->igu_base_sb_iov == 0xffff) { 1873 p_igu_info->igu_base_sb_iov = sb_id; 1874 } else if (last_iov_sb_id != sb_id - 1) { 1875 if (!val) { 1876 DP_VERBOSE(p_hwfn->cdev, 1877 NETIF_MSG_INTR, 1878 "First uninitialized IGU CAM entry at index 0x%04x\n", 1879 sb_id); 1880 } else { 1881 DP_NOTICE(p_hwfn->cdev, 1882 "Consecutive igu vectors for HWFN %x vfs is broken [jumps from %04x to %04x]\n", 1883 p_hwfn->rel_pf_id, 1884 last_iov_sb_id, 1885 sb_id); } 1886 break; 1887 } 1888 blk->status |= QED_IGU_STATUS_FREE; 1889 p_hwfn->hw_info.p_igu_info->free_blks++; 1890 last_iov_sb_id = sb_id; 1891 } 1892 } 1893 } 1894 1895 /* There's a possibility the igu_sb_cnt_iov doesn't properly reflect 1896 * the number of VF SBs [especially for first VF on engine, as we can't 1897 * differentiate between empty entries and its entries]. 1898 * Since we don't really support more SBs than VFs today, prevent any 1899 * such configuration by sanitizing the number of SBs to equal the 1900 * number of VFs. 1901 */ 1902 if (IS_PF_SRIOV(p_hwfn)) { 1903 u16 total_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 1904 1905 if (total_vfs < p_igu_info->free_blks) { 1906 DP_VERBOSE(p_hwfn, 1907 (NETIF_MSG_INTR | QED_MSG_IOV), 1908 "Limiting number of SBs for IOV - %04x --> %04x\n", 1909 p_igu_info->free_blks, 1910 p_hwfn->cdev->p_iov_info->total_vfs); 1911 p_igu_info->free_blks = total_vfs; 1912 } else if (total_vfs > p_igu_info->free_blks) { 1913 DP_NOTICE(p_hwfn, 1914 "IGU has only %04x SBs for VFs while the device has %04x VFs\n", 1915 p_igu_info->free_blks, total_vfs); 1916 return -EINVAL; 1917 } 1918 } 1919 p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks; 1920 1921 DP_VERBOSE( 1922 p_hwfn, 1923 NETIF_MSG_INTR, 1924 "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] igu_dsb_id=0x%x\n", 1925 p_igu_info->igu_base_sb, 1926 p_igu_info->igu_base_sb_iov, 1927 p_igu_info->igu_sb_cnt, 1928 p_igu_info->igu_sb_cnt_iov, 1929 p_igu_info->igu_dsb_id); 1930 1931 if (p_igu_info->igu_base_sb == 0xffff || 1932 p_igu_info->igu_dsb_id == 0xffff || 1933 p_igu_info->igu_sb_cnt == 0) { 1934 DP_NOTICE(p_hwfn, 1935 "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n", 1936 p_igu_info->igu_base_sb, 1937 p_igu_info->igu_sb_cnt, 1938 p_igu_info->igu_dsb_id); 1939 return -EINVAL; 1940 } 1941 1942 return 0; 1943 } 1944 1945 /** 1946 * @brief Initialize igu runtime registers 1947 * 1948 * @param p_hwfn 1949 */ 1950 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 1951 { 1952 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 1953 1954 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 1955 } 1956 1957 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 1958 { 1959 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 1960 IGU_CMD_INT_ACK_BASE; 1961 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 1962 IGU_CMD_INT_ACK_BASE; 1963 u32 intr_status_hi = 0, intr_status_lo = 0; 1964 u64 intr_status = 0; 1965 1966 intr_status_lo = REG_RD(p_hwfn, 1967 GTT_BAR0_MAP_REG_IGU_CMD + 1968 lsb_igu_cmd_addr * 8); 1969 intr_status_hi = REG_RD(p_hwfn, 1970 GTT_BAR0_MAP_REG_IGU_CMD + 1971 msb_igu_cmd_addr * 8); 1972 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 1973 1974 return intr_status; 1975 } 1976 1977 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 1978 { 1979 tasklet_init(p_hwfn->sp_dpc, 1980 qed_int_sp_dpc, (unsigned long)p_hwfn); 1981 p_hwfn->b_sp_dpc_enabled = true; 1982 } 1983 1984 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 1985 { 1986 p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 1987 if (!p_hwfn->sp_dpc) 1988 return -ENOMEM; 1989 1990 return 0; 1991 } 1992 1993 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 1994 { 1995 kfree(p_hwfn->sp_dpc); 1996 p_hwfn->sp_dpc = NULL; 1997 } 1998 1999 int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2000 { 2001 int rc = 0; 2002 2003 rc = qed_int_sp_dpc_alloc(p_hwfn); 2004 if (rc) 2005 return rc; 2006 2007 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 2008 if (rc) 2009 return rc; 2010 2011 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 2012 2013 return rc; 2014 } 2015 2016 void qed_int_free(struct qed_hwfn *p_hwfn) 2017 { 2018 qed_int_sp_sb_free(p_hwfn); 2019 qed_int_sb_attn_free(p_hwfn); 2020 qed_int_sp_dpc_free(p_hwfn); 2021 } 2022 2023 void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2024 { 2025 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 2026 qed_int_sb_attn_setup(p_hwfn, p_ptt); 2027 qed_int_sp_dpc_setup(p_hwfn); 2028 } 2029 2030 void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 2031 struct qed_sb_cnt_info *p_sb_cnt_info) 2032 { 2033 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2034 2035 if (!info || !p_sb_cnt_info) 2036 return; 2037 2038 p_sb_cnt_info->sb_cnt = info->igu_sb_cnt; 2039 p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov; 2040 p_sb_cnt_info->sb_free_blk = info->free_blks; 2041 } 2042 2043 u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 2044 { 2045 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2046 2047 /* Determine origin of SB id */ 2048 if ((sb_id >= p_info->igu_base_sb) && 2049 (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) { 2050 return sb_id - p_info->igu_base_sb; 2051 } else if ((sb_id >= p_info->igu_base_sb_iov) && 2052 (sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) { 2053 /* We want the first VF queue to be adjacent to the 2054 * last PF queue. Since L2 queues can be partial to 2055 * SBs, we'll use the feature instead. 2056 */ 2057 return sb_id - p_info->igu_base_sb_iov + 2058 FEAT_NUM(p_hwfn, QED_PF_L2_QUE); 2059 } else { 2060 DP_NOTICE(p_hwfn, "SB %d not in range for function\n", sb_id); 2061 return 0; 2062 } 2063 } 2064 2065 void qed_int_disable_post_isr_release(struct qed_dev *cdev) 2066 { 2067 int i; 2068 2069 for_each_hwfn(cdev, i) 2070 cdev->hwfns[i].b_int_requested = false; 2071 } 2072 2073 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2074 u8 timer_res, u16 sb_id, bool tx) 2075 { 2076 struct cau_sb_entry sb_entry; 2077 int rc; 2078 2079 if (!p_hwfn->hw_init_done) { 2080 DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2081 return -EINVAL; 2082 } 2083 2084 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2085 sb_id * sizeof(u64), 2086 (u64)(uintptr_t)&sb_entry, 2, 0); 2087 if (rc) { 2088 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2089 return rc; 2090 } 2091 2092 if (tx) 2093 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2094 else 2095 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2096 2097 rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2098 (u64)(uintptr_t)&sb_entry, 2099 CAU_REG_SB_VAR_MEMORY + 2100 sb_id * sizeof(u64), 2, 0); 2101 if (rc) { 2102 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2103 return rc; 2104 } 2105 2106 return rc; 2107 } 2108