1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <linux/io.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/errno.h> 16 #include <linux/interrupt.h> 17 #include <linux/kernel.h> 18 #include <linux/pci.h> 19 #include <linux/slab.h> 20 #include <linux/string.h> 21 #include "qed.h" 22 #include "qed_hsi.h" 23 #include "qed_hw.h" 24 #include "qed_init_ops.h" 25 #include "qed_int.h" 26 #include "qed_mcp.h" 27 #include "qed_reg_addr.h" 28 #include "qed_sp.h" 29 30 struct qed_pi_info { 31 qed_int_comp_cb_t comp_cb; 32 void *cookie; 33 }; 34 35 struct qed_sb_sp_info { 36 struct qed_sb_info sb_info; 37 38 /* per protocol index data */ 39 struct qed_pi_info pi_info_arr[PIS_PER_SB]; 40 }; 41 42 enum qed_attention_type { 43 QED_ATTN_TYPE_ATTN, 44 QED_ATTN_TYPE_PARITY, 45 }; 46 47 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 48 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 49 50 struct aeu_invert_reg_bit { 51 char bit_name[30]; 52 53 #define ATTENTION_PARITY (1 << 0) 54 55 #define ATTENTION_LENGTH_MASK (0x00000ff0) 56 #define ATTENTION_LENGTH_SHIFT (4) 57 #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 58 ATTENTION_LENGTH_SHIFT) 59 #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT) 60 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 61 #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 62 ATTENTION_PARITY) 63 64 /* Multiple bits start with this offset */ 65 #define ATTENTION_OFFSET_MASK (0x000ff000) 66 #define ATTENTION_OFFSET_SHIFT (12) 67 unsigned int flags; 68 69 /* Callback to call if attention will be triggered */ 70 int (*cb)(struct qed_hwfn *p_hwfn); 71 72 enum block_id block_index; 73 }; 74 75 struct aeu_invert_reg { 76 struct aeu_invert_reg_bit bits[32]; 77 }; 78 79 #define MAX_ATTN_GRPS (8) 80 #define NUM_ATTN_REGS (9) 81 82 /* HW Attention register */ 83 struct attn_hw_reg { 84 u16 reg_idx; /* Index of this register in its block */ 85 u16 num_of_bits; /* number of valid attention bits */ 86 u32 sts_addr; /* Address of the STS register */ 87 u32 sts_clr_addr; /* Address of the STS_CLR register */ 88 u32 sts_wr_addr; /* Address of the STS_WR register */ 89 u32 mask_addr; /* Address of the MASK register */ 90 }; 91 92 /* HW block attention registers */ 93 struct attn_hw_regs { 94 u16 num_of_int_regs; /* Number of interrupt regs */ 95 u16 num_of_prty_regs; /* Number of parity regs */ 96 struct attn_hw_reg **int_regs; /* interrupt regs */ 97 struct attn_hw_reg **prty_regs; /* parity regs */ 98 }; 99 100 /* HW block attention registers */ 101 struct attn_hw_block { 102 const char *name; /* Block name */ 103 struct attn_hw_regs chip_regs[1]; 104 }; 105 106 static struct attn_hw_reg grc_int0_bb_b0 = { 107 0, 4, 0x50180, 0x5018c, 0x50188, 0x50184}; 108 109 static struct attn_hw_reg *grc_int_bb_b0_regs[1] = { 110 &grc_int0_bb_b0}; 111 112 static struct attn_hw_reg grc_prty1_bb_b0 = { 113 0, 2, 0x50200, 0x5020c, 0x50208, 0x50204}; 114 115 static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = { 116 &grc_prty1_bb_b0}; 117 118 static struct attn_hw_reg miscs_int0_bb_b0 = { 119 0, 3, 0x9180, 0x918c, 0x9188, 0x9184}; 120 121 static struct attn_hw_reg miscs_int1_bb_b0 = { 122 1, 11, 0x9190, 0x919c, 0x9198, 0x9194}; 123 124 static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = { 125 &miscs_int0_bb_b0, &miscs_int1_bb_b0}; 126 127 static struct attn_hw_reg miscs_prty0_bb_b0 = { 128 0, 1, 0x91a0, 0x91ac, 0x91a8, 0x91a4}; 129 130 static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = { 131 &miscs_prty0_bb_b0}; 132 133 static struct attn_hw_reg misc_int0_bb_b0 = { 134 0, 1, 0x8180, 0x818c, 0x8188, 0x8184}; 135 136 static struct attn_hw_reg *misc_int_bb_b0_regs[1] = { 137 &misc_int0_bb_b0}; 138 139 static struct attn_hw_reg pglue_b_int0_bb_b0 = { 140 0, 23, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184}; 141 142 static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = { 143 &pglue_b_int0_bb_b0}; 144 145 static struct attn_hw_reg pglue_b_prty0_bb_b0 = { 146 0, 1, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194}; 147 148 static struct attn_hw_reg pglue_b_prty1_bb_b0 = { 149 1, 22, 0x2a8200, 0x2a820c, 0x2a8208, 0x2a8204}; 150 151 static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = { 152 &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0}; 153 154 static struct attn_hw_reg cnig_int0_bb_b0 = { 155 0, 6, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec}; 156 157 static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = { 158 &cnig_int0_bb_b0}; 159 160 static struct attn_hw_reg cnig_prty0_bb_b0 = { 161 0, 2, 0x218348, 0x218354, 0x218350, 0x21834c}; 162 163 static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = { 164 &cnig_prty0_bb_b0}; 165 166 static struct attn_hw_reg cpmu_int0_bb_b0 = { 167 0, 1, 0x303e0, 0x303ec, 0x303e8, 0x303e4}; 168 169 static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = { 170 &cpmu_int0_bb_b0}; 171 172 static struct attn_hw_reg ncsi_int0_bb_b0 = { 173 0, 1, 0x404cc, 0x404d8, 0x404d4, 0x404d0}; 174 175 static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = { 176 &ncsi_int0_bb_b0}; 177 178 static struct attn_hw_reg ncsi_prty1_bb_b0 = { 179 0, 1, 0x40000, 0x4000c, 0x40008, 0x40004}; 180 181 static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = { 182 &ncsi_prty1_bb_b0}; 183 184 static struct attn_hw_reg opte_prty1_bb_b0 = { 185 0, 11, 0x53000, 0x5300c, 0x53008, 0x53004}; 186 187 static struct attn_hw_reg opte_prty0_bb_b0 = { 188 1, 1, 0x53208, 0x53214, 0x53210, 0x5320c}; 189 190 static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = { 191 &opte_prty1_bb_b0, &opte_prty0_bb_b0}; 192 193 static struct attn_hw_reg bmb_int0_bb_b0 = { 194 0, 16, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4}; 195 196 static struct attn_hw_reg bmb_int1_bb_b0 = { 197 1, 28, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc}; 198 199 static struct attn_hw_reg bmb_int2_bb_b0 = { 200 2, 26, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4}; 201 202 static struct attn_hw_reg bmb_int3_bb_b0 = { 203 3, 31, 0x540108, 0x540114, 0x540110, 0x54010c}; 204 205 static struct attn_hw_reg bmb_int4_bb_b0 = { 206 4, 27, 0x540120, 0x54012c, 0x540128, 0x540124}; 207 208 static struct attn_hw_reg bmb_int5_bb_b0 = { 209 5, 29, 0x540138, 0x540144, 0x540140, 0x54013c}; 210 211 static struct attn_hw_reg bmb_int6_bb_b0 = { 212 6, 30, 0x540150, 0x54015c, 0x540158, 0x540154}; 213 214 static struct attn_hw_reg bmb_int7_bb_b0 = { 215 7, 32, 0x540168, 0x540174, 0x540170, 0x54016c}; 216 217 static struct attn_hw_reg bmb_int8_bb_b0 = { 218 8, 32, 0x540184, 0x540190, 0x54018c, 0x540188}; 219 220 static struct attn_hw_reg bmb_int9_bb_b0 = { 221 9, 32, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0}; 222 223 static struct attn_hw_reg bmb_int10_bb_b0 = { 224 10, 3, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8}; 225 226 static struct attn_hw_reg bmb_int11_bb_b0 = { 227 11, 4, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0}; 228 229 static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = { 230 &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0, 231 &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0, 232 &bmb_int8_bb_b0, &bmb_int9_bb_b0, &bmb_int10_bb_b0, &bmb_int11_bb_b0}; 233 234 static struct attn_hw_reg bmb_prty0_bb_b0 = { 235 0, 5, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0}; 236 237 static struct attn_hw_reg bmb_prty1_bb_b0 = { 238 1, 31, 0x540400, 0x54040c, 0x540408, 0x540404}; 239 240 static struct attn_hw_reg bmb_prty2_bb_b0 = { 241 2, 15, 0x540410, 0x54041c, 0x540418, 0x540414}; 242 243 static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = { 244 &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0}; 245 246 static struct attn_hw_reg pcie_prty1_bb_b0 = { 247 0, 17, 0x54000, 0x5400c, 0x54008, 0x54004}; 248 249 static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = { 250 &pcie_prty1_bb_b0}; 251 252 static struct attn_hw_reg mcp2_prty0_bb_b0 = { 253 0, 1, 0x52040, 0x5204c, 0x52048, 0x52044}; 254 255 static struct attn_hw_reg mcp2_prty1_bb_b0 = { 256 1, 12, 0x52204, 0x52210, 0x5220c, 0x52208}; 257 258 static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = { 259 &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0}; 260 261 static struct attn_hw_reg pswhst_int0_bb_b0 = { 262 0, 18, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184}; 263 264 static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = { 265 &pswhst_int0_bb_b0}; 266 267 static struct attn_hw_reg pswhst_prty0_bb_b0 = { 268 0, 1, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194}; 269 270 static struct attn_hw_reg pswhst_prty1_bb_b0 = { 271 1, 17, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204}; 272 273 static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = { 274 &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0}; 275 276 static struct attn_hw_reg pswhst2_int0_bb_b0 = { 277 0, 5, 0x29e180, 0x29e18c, 0x29e188, 0x29e184}; 278 279 static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = { 280 &pswhst2_int0_bb_b0}; 281 282 static struct attn_hw_reg pswhst2_prty0_bb_b0 = { 283 0, 1, 0x29e190, 0x29e19c, 0x29e198, 0x29e194}; 284 285 static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = { 286 &pswhst2_prty0_bb_b0}; 287 288 static struct attn_hw_reg pswrd_int0_bb_b0 = { 289 0, 3, 0x29c180, 0x29c18c, 0x29c188, 0x29c184}; 290 291 static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = { 292 &pswrd_int0_bb_b0}; 293 294 static struct attn_hw_reg pswrd_prty0_bb_b0 = { 295 0, 1, 0x29c190, 0x29c19c, 0x29c198, 0x29c194}; 296 297 static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = { 298 &pswrd_prty0_bb_b0}; 299 300 static struct attn_hw_reg pswrd2_int0_bb_b0 = { 301 0, 5, 0x29d180, 0x29d18c, 0x29d188, 0x29d184}; 302 303 static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = { 304 &pswrd2_int0_bb_b0}; 305 306 static struct attn_hw_reg pswrd2_prty0_bb_b0 = { 307 0, 1, 0x29d190, 0x29d19c, 0x29d198, 0x29d194}; 308 309 static struct attn_hw_reg pswrd2_prty1_bb_b0 = { 310 1, 31, 0x29d200, 0x29d20c, 0x29d208, 0x29d204}; 311 312 static struct attn_hw_reg pswrd2_prty2_bb_b0 = { 313 2, 3, 0x29d210, 0x29d21c, 0x29d218, 0x29d214}; 314 315 static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = { 316 &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0}; 317 318 static struct attn_hw_reg pswwr_int0_bb_b0 = { 319 0, 16, 0x29a180, 0x29a18c, 0x29a188, 0x29a184}; 320 321 static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = { 322 &pswwr_int0_bb_b0}; 323 324 static struct attn_hw_reg pswwr_prty0_bb_b0 = { 325 0, 1, 0x29a190, 0x29a19c, 0x29a198, 0x29a194}; 326 327 static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = { 328 &pswwr_prty0_bb_b0}; 329 330 static struct attn_hw_reg pswwr2_int0_bb_b0 = { 331 0, 19, 0x29b180, 0x29b18c, 0x29b188, 0x29b184}; 332 333 static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = { 334 &pswwr2_int0_bb_b0}; 335 336 static struct attn_hw_reg pswwr2_prty0_bb_b0 = { 337 0, 1, 0x29b190, 0x29b19c, 0x29b198, 0x29b194}; 338 339 static struct attn_hw_reg pswwr2_prty1_bb_b0 = { 340 1, 31, 0x29b200, 0x29b20c, 0x29b208, 0x29b204}; 341 342 static struct attn_hw_reg pswwr2_prty2_bb_b0 = { 343 2, 31, 0x29b210, 0x29b21c, 0x29b218, 0x29b214}; 344 345 static struct attn_hw_reg pswwr2_prty3_bb_b0 = { 346 3, 31, 0x29b220, 0x29b22c, 0x29b228, 0x29b224}; 347 348 static struct attn_hw_reg pswwr2_prty4_bb_b0 = { 349 4, 20, 0x29b230, 0x29b23c, 0x29b238, 0x29b234}; 350 351 static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = { 352 &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0, 353 &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0}; 354 355 static struct attn_hw_reg pswrq_int0_bb_b0 = { 356 0, 21, 0x280180, 0x28018c, 0x280188, 0x280184}; 357 358 static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = { 359 &pswrq_int0_bb_b0}; 360 361 static struct attn_hw_reg pswrq_prty0_bb_b0 = { 362 0, 1, 0x280190, 0x28019c, 0x280198, 0x280194}; 363 364 static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = { 365 &pswrq_prty0_bb_b0}; 366 367 static struct attn_hw_reg pswrq2_int0_bb_b0 = { 368 0, 15, 0x240180, 0x24018c, 0x240188, 0x240184}; 369 370 static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = { 371 &pswrq2_int0_bb_b0}; 372 373 static struct attn_hw_reg pswrq2_prty1_bb_b0 = { 374 0, 9, 0x240200, 0x24020c, 0x240208, 0x240204}; 375 376 static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = { 377 &pswrq2_prty1_bb_b0}; 378 379 static struct attn_hw_reg pglcs_int0_bb_b0 = { 380 0, 1, 0x1d00, 0x1d0c, 0x1d08, 0x1d04}; 381 382 static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = { 383 &pglcs_int0_bb_b0}; 384 385 static struct attn_hw_reg dmae_int0_bb_b0 = { 386 0, 2, 0xc180, 0xc18c, 0xc188, 0xc184}; 387 388 static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = { 389 &dmae_int0_bb_b0}; 390 391 static struct attn_hw_reg dmae_prty1_bb_b0 = { 392 0, 3, 0xc200, 0xc20c, 0xc208, 0xc204}; 393 394 static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = { 395 &dmae_prty1_bb_b0}; 396 397 static struct attn_hw_reg ptu_int0_bb_b0 = { 398 0, 8, 0x560180, 0x56018c, 0x560188, 0x560184}; 399 400 static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = { 401 &ptu_int0_bb_b0}; 402 403 static struct attn_hw_reg ptu_prty1_bb_b0 = { 404 0, 18, 0x560200, 0x56020c, 0x560208, 0x560204}; 405 406 static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = { 407 &ptu_prty1_bb_b0}; 408 409 static struct attn_hw_reg tcm_int0_bb_b0 = { 410 0, 8, 0x1180180, 0x118018c, 0x1180188, 0x1180184}; 411 412 static struct attn_hw_reg tcm_int1_bb_b0 = { 413 1, 32, 0x1180190, 0x118019c, 0x1180198, 0x1180194}; 414 415 static struct attn_hw_reg tcm_int2_bb_b0 = { 416 2, 1, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4}; 417 418 static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = { 419 &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0}; 420 421 static struct attn_hw_reg tcm_prty1_bb_b0 = { 422 0, 31, 0x1180200, 0x118020c, 0x1180208, 0x1180204}; 423 424 static struct attn_hw_reg tcm_prty2_bb_b0 = { 425 1, 2, 0x1180210, 0x118021c, 0x1180218, 0x1180214}; 426 427 static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = { 428 &tcm_prty1_bb_b0, &tcm_prty2_bb_b0}; 429 430 static struct attn_hw_reg mcm_int0_bb_b0 = { 431 0, 14, 0x1200180, 0x120018c, 0x1200188, 0x1200184}; 432 433 static struct attn_hw_reg mcm_int1_bb_b0 = { 434 1, 26, 0x1200190, 0x120019c, 0x1200198, 0x1200194}; 435 436 static struct attn_hw_reg mcm_int2_bb_b0 = { 437 2, 1, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4}; 438 439 static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = { 440 &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0}; 441 442 static struct attn_hw_reg mcm_prty1_bb_b0 = { 443 0, 31, 0x1200200, 0x120020c, 0x1200208, 0x1200204}; 444 445 static struct attn_hw_reg mcm_prty2_bb_b0 = { 446 1, 4, 0x1200210, 0x120021c, 0x1200218, 0x1200214}; 447 448 static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = { 449 &mcm_prty1_bb_b0, &mcm_prty2_bb_b0}; 450 451 static struct attn_hw_reg ucm_int0_bb_b0 = { 452 0, 17, 0x1280180, 0x128018c, 0x1280188, 0x1280184}; 453 454 static struct attn_hw_reg ucm_int1_bb_b0 = { 455 1, 29, 0x1280190, 0x128019c, 0x1280198, 0x1280194}; 456 457 static struct attn_hw_reg ucm_int2_bb_b0 = { 458 2, 1, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4}; 459 460 static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = { 461 &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0}; 462 463 static struct attn_hw_reg ucm_prty1_bb_b0 = { 464 0, 31, 0x1280200, 0x128020c, 0x1280208, 0x1280204}; 465 466 static struct attn_hw_reg ucm_prty2_bb_b0 = { 467 1, 7, 0x1280210, 0x128021c, 0x1280218, 0x1280214}; 468 469 static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = { 470 &ucm_prty1_bb_b0, &ucm_prty2_bb_b0}; 471 472 static struct attn_hw_reg xcm_int0_bb_b0 = { 473 0, 16, 0x1000180, 0x100018c, 0x1000188, 0x1000184}; 474 475 static struct attn_hw_reg xcm_int1_bb_b0 = { 476 1, 25, 0x1000190, 0x100019c, 0x1000198, 0x1000194}; 477 478 static struct attn_hw_reg xcm_int2_bb_b0 = { 479 2, 8, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4}; 480 481 static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = { 482 &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0}; 483 484 static struct attn_hw_reg xcm_prty1_bb_b0 = { 485 0, 31, 0x1000200, 0x100020c, 0x1000208, 0x1000204}; 486 487 static struct attn_hw_reg xcm_prty2_bb_b0 = { 488 1, 11, 0x1000210, 0x100021c, 0x1000218, 0x1000214}; 489 490 static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = { 491 &xcm_prty1_bb_b0, &xcm_prty2_bb_b0}; 492 493 static struct attn_hw_reg ycm_int0_bb_b0 = { 494 0, 13, 0x1080180, 0x108018c, 0x1080188, 0x1080184}; 495 496 static struct attn_hw_reg ycm_int1_bb_b0 = { 497 1, 23, 0x1080190, 0x108019c, 0x1080198, 0x1080194}; 498 499 static struct attn_hw_reg ycm_int2_bb_b0 = { 500 2, 1, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4}; 501 502 static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = { 503 &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0}; 504 505 static struct attn_hw_reg ycm_prty1_bb_b0 = { 506 0, 31, 0x1080200, 0x108020c, 0x1080208, 0x1080204}; 507 508 static struct attn_hw_reg ycm_prty2_bb_b0 = { 509 1, 3, 0x1080210, 0x108021c, 0x1080218, 0x1080214}; 510 511 static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = { 512 &ycm_prty1_bb_b0, &ycm_prty2_bb_b0}; 513 514 static struct attn_hw_reg pcm_int0_bb_b0 = { 515 0, 5, 0x1100180, 0x110018c, 0x1100188, 0x1100184}; 516 517 static struct attn_hw_reg pcm_int1_bb_b0 = { 518 1, 14, 0x1100190, 0x110019c, 0x1100198, 0x1100194}; 519 520 static struct attn_hw_reg pcm_int2_bb_b0 = { 521 2, 1, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4}; 522 523 static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = { 524 &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0}; 525 526 static struct attn_hw_reg pcm_prty1_bb_b0 = { 527 0, 11, 0x1100200, 0x110020c, 0x1100208, 0x1100204}; 528 529 static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = { 530 &pcm_prty1_bb_b0}; 531 532 static struct attn_hw_reg qm_int0_bb_b0 = { 533 0, 22, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184}; 534 535 static struct attn_hw_reg *qm_int_bb_b0_regs[1] = { 536 &qm_int0_bb_b0}; 537 538 static struct attn_hw_reg qm_prty0_bb_b0 = { 539 0, 11, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194}; 540 541 static struct attn_hw_reg qm_prty1_bb_b0 = { 542 1, 31, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204}; 543 544 static struct attn_hw_reg qm_prty2_bb_b0 = { 545 2, 31, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214}; 546 547 static struct attn_hw_reg qm_prty3_bb_b0 = { 548 3, 11, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224}; 549 550 static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = { 551 &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0}; 552 553 static struct attn_hw_reg tm_int0_bb_b0 = { 554 0, 32, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184}; 555 556 static struct attn_hw_reg tm_int1_bb_b0 = { 557 1, 11, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194}; 558 559 static struct attn_hw_reg *tm_int_bb_b0_regs[2] = { 560 &tm_int0_bb_b0, &tm_int1_bb_b0}; 561 562 static struct attn_hw_reg tm_prty1_bb_b0 = { 563 0, 17, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204}; 564 565 static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = { 566 &tm_prty1_bb_b0}; 567 568 static struct attn_hw_reg dorq_int0_bb_b0 = { 569 0, 9, 0x100180, 0x10018c, 0x100188, 0x100184}; 570 571 static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = { 572 &dorq_int0_bb_b0}; 573 574 static struct attn_hw_reg dorq_prty0_bb_b0 = { 575 0, 1, 0x100190, 0x10019c, 0x100198, 0x100194}; 576 577 static struct attn_hw_reg dorq_prty1_bb_b0 = { 578 1, 6, 0x100200, 0x10020c, 0x100208, 0x100204}; 579 580 static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = { 581 &dorq_prty0_bb_b0, &dorq_prty1_bb_b0}; 582 583 static struct attn_hw_reg brb_int0_bb_b0 = { 584 0, 32, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4}; 585 586 static struct attn_hw_reg brb_int1_bb_b0 = { 587 1, 30, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc}; 588 589 static struct attn_hw_reg brb_int2_bb_b0 = { 590 2, 28, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4}; 591 592 static struct attn_hw_reg brb_int3_bb_b0 = { 593 3, 31, 0x340108, 0x340114, 0x340110, 0x34010c}; 594 595 static struct attn_hw_reg brb_int4_bb_b0 = { 596 4, 27, 0x340120, 0x34012c, 0x340128, 0x340124}; 597 598 static struct attn_hw_reg brb_int5_bb_b0 = { 599 5, 1, 0x340138, 0x340144, 0x340140, 0x34013c}; 600 601 static struct attn_hw_reg brb_int6_bb_b0 = { 602 6, 8, 0x340150, 0x34015c, 0x340158, 0x340154}; 603 604 static struct attn_hw_reg brb_int7_bb_b0 = { 605 7, 32, 0x340168, 0x340174, 0x340170, 0x34016c}; 606 607 static struct attn_hw_reg brb_int8_bb_b0 = { 608 8, 17, 0x340184, 0x340190, 0x34018c, 0x340188}; 609 610 static struct attn_hw_reg brb_int9_bb_b0 = { 611 9, 1, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0}; 612 613 static struct attn_hw_reg brb_int10_bb_b0 = { 614 10, 14, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8}; 615 616 static struct attn_hw_reg brb_int11_bb_b0 = { 617 11, 8, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0}; 618 619 static struct attn_hw_reg *brb_int_bb_b0_regs[12] = { 620 &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0, 621 &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0, 622 &brb_int8_bb_b0, &brb_int9_bb_b0, &brb_int10_bb_b0, &brb_int11_bb_b0}; 623 624 static struct attn_hw_reg brb_prty0_bb_b0 = { 625 0, 5, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0}; 626 627 static struct attn_hw_reg brb_prty1_bb_b0 = { 628 1, 31, 0x340400, 0x34040c, 0x340408, 0x340404}; 629 630 static struct attn_hw_reg brb_prty2_bb_b0 = { 631 2, 14, 0x340410, 0x34041c, 0x340418, 0x340414}; 632 633 static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = { 634 &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0}; 635 636 static struct attn_hw_reg src_int0_bb_b0 = { 637 0, 1, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4}; 638 639 static struct attn_hw_reg *src_int_bb_b0_regs[1] = { 640 &src_int0_bb_b0}; 641 642 static struct attn_hw_reg prs_int0_bb_b0 = { 643 0, 2, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044}; 644 645 static struct attn_hw_reg *prs_int_bb_b0_regs[1] = { 646 &prs_int0_bb_b0}; 647 648 static struct attn_hw_reg prs_prty0_bb_b0 = { 649 0, 2, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054}; 650 651 static struct attn_hw_reg prs_prty1_bb_b0 = { 652 1, 31, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208}; 653 654 static struct attn_hw_reg prs_prty2_bb_b0 = { 655 2, 5, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218}; 656 657 static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = { 658 &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0}; 659 660 static struct attn_hw_reg tsdm_int0_bb_b0 = { 661 0, 26, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044}; 662 663 static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = { 664 &tsdm_int0_bb_b0}; 665 666 static struct attn_hw_reg tsdm_prty1_bb_b0 = { 667 0, 10, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204}; 668 669 static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = { 670 &tsdm_prty1_bb_b0}; 671 672 static struct attn_hw_reg msdm_int0_bb_b0 = { 673 0, 26, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044}; 674 675 static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = { 676 &msdm_int0_bb_b0}; 677 678 static struct attn_hw_reg msdm_prty1_bb_b0 = { 679 0, 11, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204}; 680 681 static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = { 682 &msdm_prty1_bb_b0}; 683 684 static struct attn_hw_reg usdm_int0_bb_b0 = { 685 0, 26, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044}; 686 687 static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = { 688 &usdm_int0_bb_b0}; 689 690 static struct attn_hw_reg usdm_prty1_bb_b0 = { 691 0, 10, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204}; 692 693 static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = { 694 &usdm_prty1_bb_b0}; 695 696 static struct attn_hw_reg xsdm_int0_bb_b0 = { 697 0, 26, 0xf80040, 0xf8004c, 0xf80048, 0xf80044}; 698 699 static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = { 700 &xsdm_int0_bb_b0}; 701 702 static struct attn_hw_reg xsdm_prty1_bb_b0 = { 703 0, 10, 0xf80200, 0xf8020c, 0xf80208, 0xf80204}; 704 705 static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = { 706 &xsdm_prty1_bb_b0}; 707 708 static struct attn_hw_reg ysdm_int0_bb_b0 = { 709 0, 26, 0xf90040, 0xf9004c, 0xf90048, 0xf90044}; 710 711 static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = { 712 &ysdm_int0_bb_b0}; 713 714 static struct attn_hw_reg ysdm_prty1_bb_b0 = { 715 0, 9, 0xf90200, 0xf9020c, 0xf90208, 0xf90204}; 716 717 static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = { 718 &ysdm_prty1_bb_b0}; 719 720 static struct attn_hw_reg psdm_int0_bb_b0 = { 721 0, 26, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044}; 722 723 static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = { 724 &psdm_int0_bb_b0}; 725 726 static struct attn_hw_reg psdm_prty1_bb_b0 = { 727 0, 9, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204}; 728 729 static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = { 730 &psdm_prty1_bb_b0}; 731 732 static struct attn_hw_reg tsem_int0_bb_b0 = { 733 0, 32, 0x1700040, 0x170004c, 0x1700048, 0x1700044}; 734 735 static struct attn_hw_reg tsem_int1_bb_b0 = { 736 1, 13, 0x1700050, 0x170005c, 0x1700058, 0x1700054}; 737 738 static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = { 739 2, 1, 0x1740040, 0x174004c, 0x1740048, 0x1740044}; 740 741 static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = { 742 &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0}; 743 744 static struct attn_hw_reg tsem_prty0_bb_b0 = { 745 0, 3, 0x17000c8, 0x17000d4, 0x17000d0, 0x17000cc}; 746 747 static struct attn_hw_reg tsem_prty1_bb_b0 = { 748 1, 6, 0x1700200, 0x170020c, 0x1700208, 0x1700204}; 749 750 static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = { 751 2, 6, 0x174a200, 0x174a20c, 0x174a208, 0x174a204}; 752 753 static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = { 754 &tsem_prty0_bb_b0, &tsem_prty1_bb_b0, 755 &tsem_fast_memory_vfc_config_prty1_bb_b0}; 756 757 static struct attn_hw_reg msem_int0_bb_b0 = { 758 0, 32, 0x1800040, 0x180004c, 0x1800048, 0x1800044}; 759 760 static struct attn_hw_reg msem_int1_bb_b0 = { 761 1, 13, 0x1800050, 0x180005c, 0x1800058, 0x1800054}; 762 763 static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = { 764 2, 1, 0x1840040, 0x184004c, 0x1840048, 0x1840044}; 765 766 static struct attn_hw_reg *msem_int_bb_b0_regs[3] = { 767 &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0}; 768 769 static struct attn_hw_reg msem_prty0_bb_b0 = { 770 0, 3, 0x18000c8, 0x18000d4, 0x18000d0, 0x18000cc}; 771 772 static struct attn_hw_reg msem_prty1_bb_b0 = { 773 1, 6, 0x1800200, 0x180020c, 0x1800208, 0x1800204}; 774 775 static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = { 776 &msem_prty0_bb_b0, &msem_prty1_bb_b0}; 777 778 static struct attn_hw_reg usem_int0_bb_b0 = { 779 0, 32, 0x1900040, 0x190004c, 0x1900048, 0x1900044}; 780 781 static struct attn_hw_reg usem_int1_bb_b0 = { 782 1, 13, 0x1900050, 0x190005c, 0x1900058, 0x1900054}; 783 784 static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = { 785 2, 1, 0x1940040, 0x194004c, 0x1940048, 0x1940044}; 786 787 static struct attn_hw_reg *usem_int_bb_b0_regs[3] = { 788 &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0}; 789 790 static struct attn_hw_reg usem_prty0_bb_b0 = { 791 0, 3, 0x19000c8, 0x19000d4, 0x19000d0, 0x19000cc}; 792 793 static struct attn_hw_reg usem_prty1_bb_b0 = { 794 1, 6, 0x1900200, 0x190020c, 0x1900208, 0x1900204}; 795 796 static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = { 797 &usem_prty0_bb_b0, &usem_prty1_bb_b0}; 798 799 static struct attn_hw_reg xsem_int0_bb_b0 = { 800 0, 32, 0x1400040, 0x140004c, 0x1400048, 0x1400044}; 801 802 static struct attn_hw_reg xsem_int1_bb_b0 = { 803 1, 13, 0x1400050, 0x140005c, 0x1400058, 0x1400054}; 804 805 static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = { 806 2, 1, 0x1440040, 0x144004c, 0x1440048, 0x1440044}; 807 808 static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = { 809 &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0}; 810 811 static struct attn_hw_reg xsem_prty0_bb_b0 = { 812 0, 3, 0x14000c8, 0x14000d4, 0x14000d0, 0x14000cc}; 813 814 static struct attn_hw_reg xsem_prty1_bb_b0 = { 815 1, 7, 0x1400200, 0x140020c, 0x1400208, 0x1400204}; 816 817 static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = { 818 &xsem_prty0_bb_b0, &xsem_prty1_bb_b0}; 819 820 static struct attn_hw_reg ysem_int0_bb_b0 = { 821 0, 32, 0x1500040, 0x150004c, 0x1500048, 0x1500044}; 822 823 static struct attn_hw_reg ysem_int1_bb_b0 = { 824 1, 13, 0x1500050, 0x150005c, 0x1500058, 0x1500054}; 825 826 static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = { 827 2, 1, 0x1540040, 0x154004c, 0x1540048, 0x1540044}; 828 829 static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = { 830 &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0}; 831 832 static struct attn_hw_reg ysem_prty0_bb_b0 = { 833 0, 3, 0x15000c8, 0x15000d4, 0x15000d0, 0x15000cc}; 834 835 static struct attn_hw_reg ysem_prty1_bb_b0 = { 836 1, 7, 0x1500200, 0x150020c, 0x1500208, 0x1500204}; 837 838 static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = { 839 &ysem_prty0_bb_b0, &ysem_prty1_bb_b0}; 840 841 static struct attn_hw_reg psem_int0_bb_b0 = { 842 0, 32, 0x1600040, 0x160004c, 0x1600048, 0x1600044}; 843 844 static struct attn_hw_reg psem_int1_bb_b0 = { 845 1, 13, 0x1600050, 0x160005c, 0x1600058, 0x1600054}; 846 847 static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = { 848 2, 1, 0x1640040, 0x164004c, 0x1640048, 0x1640044}; 849 850 static struct attn_hw_reg *psem_int_bb_b0_regs[3] = { 851 &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0}; 852 853 static struct attn_hw_reg psem_prty0_bb_b0 = { 854 0, 3, 0x16000c8, 0x16000d4, 0x16000d0, 0x16000cc}; 855 856 static struct attn_hw_reg psem_prty1_bb_b0 = { 857 1, 6, 0x1600200, 0x160020c, 0x1600208, 0x1600204}; 858 859 static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = { 860 2, 6, 0x164a200, 0x164a20c, 0x164a208, 0x164a204}; 861 862 static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = { 863 &psem_prty0_bb_b0, &psem_prty1_bb_b0, 864 &psem_fast_memory_vfc_config_prty1_bb_b0}; 865 866 static struct attn_hw_reg rss_int0_bb_b0 = { 867 0, 12, 0x238980, 0x23898c, 0x238988, 0x238984}; 868 869 static struct attn_hw_reg *rss_int_bb_b0_regs[1] = { 870 &rss_int0_bb_b0}; 871 872 static struct attn_hw_reg rss_prty1_bb_b0 = { 873 0, 4, 0x238a00, 0x238a0c, 0x238a08, 0x238a04}; 874 875 static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = { 876 &rss_prty1_bb_b0}; 877 878 static struct attn_hw_reg tmld_int0_bb_b0 = { 879 0, 6, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184}; 880 881 static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = { 882 &tmld_int0_bb_b0}; 883 884 static struct attn_hw_reg tmld_prty1_bb_b0 = { 885 0, 8, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204}; 886 887 static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = { 888 &tmld_prty1_bb_b0}; 889 890 static struct attn_hw_reg muld_int0_bb_b0 = { 891 0, 6, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184}; 892 893 static struct attn_hw_reg *muld_int_bb_b0_regs[1] = { 894 &muld_int0_bb_b0}; 895 896 static struct attn_hw_reg muld_prty1_bb_b0 = { 897 0, 10, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204}; 898 899 static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = { 900 &muld_prty1_bb_b0}; 901 902 static struct attn_hw_reg yuld_int0_bb_b0 = { 903 0, 6, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184}; 904 905 static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = { 906 &yuld_int0_bb_b0}; 907 908 static struct attn_hw_reg yuld_prty1_bb_b0 = { 909 0, 6, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204}; 910 911 static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = { 912 &yuld_prty1_bb_b0}; 913 914 static struct attn_hw_reg xyld_int0_bb_b0 = { 915 0, 6, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184}; 916 917 static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = { 918 &xyld_int0_bb_b0}; 919 920 static struct attn_hw_reg xyld_prty1_bb_b0 = { 921 0, 9, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204}; 922 923 static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = { 924 &xyld_prty1_bb_b0}; 925 926 static struct attn_hw_reg prm_int0_bb_b0 = { 927 0, 11, 0x230040, 0x23004c, 0x230048, 0x230044}; 928 929 static struct attn_hw_reg *prm_int_bb_b0_regs[1] = { 930 &prm_int0_bb_b0}; 931 932 static struct attn_hw_reg prm_prty0_bb_b0 = { 933 0, 1, 0x230050, 0x23005c, 0x230058, 0x230054}; 934 935 static struct attn_hw_reg prm_prty1_bb_b0 = { 936 1, 24, 0x230200, 0x23020c, 0x230208, 0x230204}; 937 938 static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = { 939 &prm_prty0_bb_b0, &prm_prty1_bb_b0}; 940 941 static struct attn_hw_reg pbf_pb1_int0_bb_b0 = { 942 0, 9, 0xda0040, 0xda004c, 0xda0048, 0xda0044}; 943 944 static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = { 945 &pbf_pb1_int0_bb_b0}; 946 947 static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = { 948 0, 1, 0xda0050, 0xda005c, 0xda0058, 0xda0054}; 949 950 static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = { 951 &pbf_pb1_prty0_bb_b0}; 952 953 static struct attn_hw_reg pbf_pb2_int0_bb_b0 = { 954 0, 9, 0xda4040, 0xda404c, 0xda4048, 0xda4044}; 955 956 static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = { 957 &pbf_pb2_int0_bb_b0}; 958 959 static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = { 960 0, 1, 0xda4050, 0xda405c, 0xda4058, 0xda4054}; 961 962 static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = { 963 &pbf_pb2_prty0_bb_b0}; 964 965 static struct attn_hw_reg rpb_int0_bb_b0 = { 966 0, 9, 0x23c040, 0x23c04c, 0x23c048, 0x23c044}; 967 968 static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = { 969 &rpb_int0_bb_b0}; 970 971 static struct attn_hw_reg rpb_prty0_bb_b0 = { 972 0, 1, 0x23c050, 0x23c05c, 0x23c058, 0x23c054}; 973 974 static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = { 975 &rpb_prty0_bb_b0}; 976 977 static struct attn_hw_reg btb_int0_bb_b0 = { 978 0, 16, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4}; 979 980 static struct attn_hw_reg btb_int1_bb_b0 = { 981 1, 16, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc}; 982 983 static struct attn_hw_reg btb_int2_bb_b0 = { 984 2, 4, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4}; 985 986 static struct attn_hw_reg btb_int3_bb_b0 = { 987 3, 32, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c}; 988 989 static struct attn_hw_reg btb_int4_bb_b0 = { 990 4, 23, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124}; 991 992 static struct attn_hw_reg btb_int5_bb_b0 = { 993 5, 32, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c}; 994 995 static struct attn_hw_reg btb_int6_bb_b0 = { 996 6, 1, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154}; 997 998 static struct attn_hw_reg btb_int8_bb_b0 = { 999 7, 1, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188}; 1000 1001 static struct attn_hw_reg btb_int9_bb_b0 = { 1002 8, 1, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0}; 1003 1004 static struct attn_hw_reg btb_int10_bb_b0 = { 1005 9, 1, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8}; 1006 1007 static struct attn_hw_reg btb_int11_bb_b0 = { 1008 10, 2, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0}; 1009 1010 static struct attn_hw_reg *btb_int_bb_b0_regs[11] = { 1011 &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0, 1012 &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0, 1013 &btb_int9_bb_b0, &btb_int10_bb_b0, &btb_int11_bb_b0}; 1014 1015 static struct attn_hw_reg btb_prty0_bb_b0 = { 1016 0, 5, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0}; 1017 1018 static struct attn_hw_reg btb_prty1_bb_b0 = { 1019 1, 23, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404}; 1020 1021 static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = { 1022 &btb_prty0_bb_b0, &btb_prty1_bb_b0}; 1023 1024 static struct attn_hw_reg pbf_int0_bb_b0 = { 1025 0, 1, 0xd80180, 0xd8018c, 0xd80188, 0xd80184}; 1026 1027 static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = { 1028 &pbf_int0_bb_b0}; 1029 1030 static struct attn_hw_reg pbf_prty0_bb_b0 = { 1031 0, 1, 0xd80190, 0xd8019c, 0xd80198, 0xd80194}; 1032 1033 static struct attn_hw_reg pbf_prty1_bb_b0 = { 1034 1, 31, 0xd80200, 0xd8020c, 0xd80208, 0xd80204}; 1035 1036 static struct attn_hw_reg pbf_prty2_bb_b0 = { 1037 2, 27, 0xd80210, 0xd8021c, 0xd80218, 0xd80214}; 1038 1039 static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = { 1040 &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0}; 1041 1042 static struct attn_hw_reg rdif_int0_bb_b0 = { 1043 0, 8, 0x300180, 0x30018c, 0x300188, 0x300184}; 1044 1045 static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = { 1046 &rdif_int0_bb_b0}; 1047 1048 static struct attn_hw_reg rdif_prty0_bb_b0 = { 1049 0, 1, 0x300190, 0x30019c, 0x300198, 0x300194}; 1050 1051 static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = { 1052 &rdif_prty0_bb_b0}; 1053 1054 static struct attn_hw_reg tdif_int0_bb_b0 = { 1055 0, 8, 0x310180, 0x31018c, 0x310188, 0x310184}; 1056 1057 static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = { 1058 &tdif_int0_bb_b0}; 1059 1060 static struct attn_hw_reg tdif_prty0_bb_b0 = { 1061 0, 1, 0x310190, 0x31019c, 0x310198, 0x310194}; 1062 1063 static struct attn_hw_reg tdif_prty1_bb_b0 = { 1064 1, 11, 0x310200, 0x31020c, 0x310208, 0x310204}; 1065 1066 static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = { 1067 &tdif_prty0_bb_b0, &tdif_prty1_bb_b0}; 1068 1069 static struct attn_hw_reg cdu_int0_bb_b0 = { 1070 0, 8, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc}; 1071 1072 static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = { 1073 &cdu_int0_bb_b0}; 1074 1075 static struct attn_hw_reg cdu_prty1_bb_b0 = { 1076 0, 5, 0x580200, 0x58020c, 0x580208, 0x580204}; 1077 1078 static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = { 1079 &cdu_prty1_bb_b0}; 1080 1081 static struct attn_hw_reg ccfc_int0_bb_b0 = { 1082 0, 2, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184}; 1083 1084 static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = { 1085 &ccfc_int0_bb_b0}; 1086 1087 static struct attn_hw_reg ccfc_prty1_bb_b0 = { 1088 0, 2, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204}; 1089 1090 static struct attn_hw_reg ccfc_prty0_bb_b0 = { 1091 1, 6, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8}; 1092 1093 static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = { 1094 &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0}; 1095 1096 static struct attn_hw_reg tcfc_int0_bb_b0 = { 1097 0, 2, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184}; 1098 1099 static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = { 1100 &tcfc_int0_bb_b0}; 1101 1102 static struct attn_hw_reg tcfc_prty1_bb_b0 = { 1103 0, 2, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204}; 1104 1105 static struct attn_hw_reg tcfc_prty0_bb_b0 = { 1106 1, 6, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8}; 1107 1108 static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = { 1109 &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0}; 1110 1111 static struct attn_hw_reg igu_int0_bb_b0 = { 1112 0, 11, 0x180180, 0x18018c, 0x180188, 0x180184}; 1113 1114 static struct attn_hw_reg *igu_int_bb_b0_regs[1] = { 1115 &igu_int0_bb_b0}; 1116 1117 static struct attn_hw_reg igu_prty0_bb_b0 = { 1118 0, 1, 0x180190, 0x18019c, 0x180198, 0x180194}; 1119 1120 static struct attn_hw_reg igu_prty1_bb_b0 = { 1121 1, 31, 0x180200, 0x18020c, 0x180208, 0x180204}; 1122 1123 static struct attn_hw_reg igu_prty2_bb_b0 = { 1124 2, 1, 0x180210, 0x18021c, 0x180218, 0x180214}; 1125 1126 static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = { 1127 &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0}; 1128 1129 static struct attn_hw_reg cau_int0_bb_b0 = { 1130 0, 11, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0}; 1131 1132 static struct attn_hw_reg *cau_int_bb_b0_regs[1] = { 1133 &cau_int0_bb_b0}; 1134 1135 static struct attn_hw_reg cau_prty1_bb_b0 = { 1136 0, 13, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204}; 1137 1138 static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = { 1139 &cau_prty1_bb_b0}; 1140 1141 static struct attn_hw_reg dbg_int0_bb_b0 = { 1142 0, 1, 0x10180, 0x1018c, 0x10188, 0x10184}; 1143 1144 static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = { 1145 &dbg_int0_bb_b0}; 1146 1147 static struct attn_hw_reg dbg_prty1_bb_b0 = { 1148 0, 1, 0x10200, 0x1020c, 0x10208, 0x10204}; 1149 1150 static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = { 1151 &dbg_prty1_bb_b0}; 1152 1153 static struct attn_hw_reg nig_int0_bb_b0 = { 1154 0, 12, 0x500040, 0x50004c, 0x500048, 0x500044}; 1155 1156 static struct attn_hw_reg nig_int1_bb_b0 = { 1157 1, 32, 0x500050, 0x50005c, 0x500058, 0x500054}; 1158 1159 static struct attn_hw_reg nig_int2_bb_b0 = { 1160 2, 20, 0x500060, 0x50006c, 0x500068, 0x500064}; 1161 1162 static struct attn_hw_reg nig_int3_bb_b0 = { 1163 3, 18, 0x500070, 0x50007c, 0x500078, 0x500074}; 1164 1165 static struct attn_hw_reg nig_int4_bb_b0 = { 1166 4, 20, 0x500080, 0x50008c, 0x500088, 0x500084}; 1167 1168 static struct attn_hw_reg nig_int5_bb_b0 = { 1169 5, 18, 0x500090, 0x50009c, 0x500098, 0x500094}; 1170 1171 static struct attn_hw_reg *nig_int_bb_b0_regs[6] = { 1172 &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0, 1173 &nig_int4_bb_b0, &nig_int5_bb_b0}; 1174 1175 static struct attn_hw_reg nig_prty0_bb_b0 = { 1176 0, 1, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4}; 1177 1178 static struct attn_hw_reg nig_prty1_bb_b0 = { 1179 1, 31, 0x500200, 0x50020c, 0x500208, 0x500204}; 1180 1181 static struct attn_hw_reg nig_prty2_bb_b0 = { 1182 2, 31, 0x500210, 0x50021c, 0x500218, 0x500214}; 1183 1184 static struct attn_hw_reg nig_prty3_bb_b0 = { 1185 3, 31, 0x500220, 0x50022c, 0x500228, 0x500224}; 1186 1187 static struct attn_hw_reg nig_prty4_bb_b0 = { 1188 4, 17, 0x500230, 0x50023c, 0x500238, 0x500234}; 1189 1190 static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = { 1191 &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0, 1192 &nig_prty3_bb_b0, &nig_prty4_bb_b0}; 1193 1194 static struct attn_hw_reg ipc_int0_bb_b0 = { 1195 0, 13, 0x2050c, 0x20518, 0x20514, 0x20510}; 1196 1197 static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = { 1198 &ipc_int0_bb_b0}; 1199 1200 static struct attn_hw_reg ipc_prty0_bb_b0 = { 1201 0, 1, 0x2051c, 0x20528, 0x20524, 0x20520}; 1202 1203 static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = { 1204 &ipc_prty0_bb_b0}; 1205 1206 static struct attn_hw_block attn_blocks[] = { 1207 {"grc", {{1, 1, grc_int_bb_b0_regs, grc_prty_bb_b0_regs} } }, 1208 {"miscs", {{2, 1, miscs_int_bb_b0_regs, miscs_prty_bb_b0_regs} } }, 1209 {"misc", {{1, 0, misc_int_bb_b0_regs, NULL} } }, 1210 {"dbu", {{0, 0, NULL, NULL} } }, 1211 {"pglue_b", {{1, 2, pglue_b_int_bb_b0_regs, 1212 pglue_b_prty_bb_b0_regs} } }, 1213 {"cnig", {{1, 1, cnig_int_bb_b0_regs, cnig_prty_bb_b0_regs} } }, 1214 {"cpmu", {{1, 0, cpmu_int_bb_b0_regs, NULL} } }, 1215 {"ncsi", {{1, 1, ncsi_int_bb_b0_regs, ncsi_prty_bb_b0_regs} } }, 1216 {"opte", {{0, 2, NULL, opte_prty_bb_b0_regs} } }, 1217 {"bmb", {{12, 3, bmb_int_bb_b0_regs, bmb_prty_bb_b0_regs} } }, 1218 {"pcie", {{0, 1, NULL, pcie_prty_bb_b0_regs} } }, 1219 {"mcp", {{0, 0, NULL, NULL} } }, 1220 {"mcp2", {{0, 2, NULL, mcp2_prty_bb_b0_regs} } }, 1221 {"pswhst", {{1, 2, pswhst_int_bb_b0_regs, pswhst_prty_bb_b0_regs} } }, 1222 {"pswhst2", {{1, 1, pswhst2_int_bb_b0_regs, 1223 pswhst2_prty_bb_b0_regs} } }, 1224 {"pswrd", {{1, 1, pswrd_int_bb_b0_regs, pswrd_prty_bb_b0_regs} } }, 1225 {"pswrd2", {{1, 3, pswrd2_int_bb_b0_regs, pswrd2_prty_bb_b0_regs} } }, 1226 {"pswwr", {{1, 1, pswwr_int_bb_b0_regs, pswwr_prty_bb_b0_regs} } }, 1227 {"pswwr2", {{1, 5, pswwr2_int_bb_b0_regs, pswwr2_prty_bb_b0_regs} } }, 1228 {"pswrq", {{1, 1, pswrq_int_bb_b0_regs, pswrq_prty_bb_b0_regs} } }, 1229 {"pswrq2", {{1, 1, pswrq2_int_bb_b0_regs, pswrq2_prty_bb_b0_regs} } }, 1230 {"pglcs", {{1, 0, pglcs_int_bb_b0_regs, NULL} } }, 1231 {"dmae", {{1, 1, dmae_int_bb_b0_regs, dmae_prty_bb_b0_regs} } }, 1232 {"ptu", {{1, 1, ptu_int_bb_b0_regs, ptu_prty_bb_b0_regs} } }, 1233 {"tcm", {{3, 2, tcm_int_bb_b0_regs, tcm_prty_bb_b0_regs} } }, 1234 {"mcm", {{3, 2, mcm_int_bb_b0_regs, mcm_prty_bb_b0_regs} } }, 1235 {"ucm", {{3, 2, ucm_int_bb_b0_regs, ucm_prty_bb_b0_regs} } }, 1236 {"xcm", {{3, 2, xcm_int_bb_b0_regs, xcm_prty_bb_b0_regs} } }, 1237 {"ycm", {{3, 2, ycm_int_bb_b0_regs, ycm_prty_bb_b0_regs} } }, 1238 {"pcm", {{3, 1, pcm_int_bb_b0_regs, pcm_prty_bb_b0_regs} } }, 1239 {"qm", {{1, 4, qm_int_bb_b0_regs, qm_prty_bb_b0_regs} } }, 1240 {"tm", {{2, 1, tm_int_bb_b0_regs, tm_prty_bb_b0_regs} } }, 1241 {"dorq", {{1, 2, dorq_int_bb_b0_regs, dorq_prty_bb_b0_regs} } }, 1242 {"brb", {{12, 3, brb_int_bb_b0_regs, brb_prty_bb_b0_regs} } }, 1243 {"src", {{1, 0, src_int_bb_b0_regs, NULL} } }, 1244 {"prs", {{1, 3, prs_int_bb_b0_regs, prs_prty_bb_b0_regs} } }, 1245 {"tsdm", {{1, 1, tsdm_int_bb_b0_regs, tsdm_prty_bb_b0_regs} } }, 1246 {"msdm", {{1, 1, msdm_int_bb_b0_regs, msdm_prty_bb_b0_regs} } }, 1247 {"usdm", {{1, 1, usdm_int_bb_b0_regs, usdm_prty_bb_b0_regs} } }, 1248 {"xsdm", {{1, 1, xsdm_int_bb_b0_regs, xsdm_prty_bb_b0_regs} } }, 1249 {"ysdm", {{1, 1, ysdm_int_bb_b0_regs, ysdm_prty_bb_b0_regs} } }, 1250 {"psdm", {{1, 1, psdm_int_bb_b0_regs, psdm_prty_bb_b0_regs} } }, 1251 {"tsem", {{3, 3, tsem_int_bb_b0_regs, tsem_prty_bb_b0_regs} } }, 1252 {"msem", {{3, 2, msem_int_bb_b0_regs, msem_prty_bb_b0_regs} } }, 1253 {"usem", {{3, 2, usem_int_bb_b0_regs, usem_prty_bb_b0_regs} } }, 1254 {"xsem", {{3, 2, xsem_int_bb_b0_regs, xsem_prty_bb_b0_regs} } }, 1255 {"ysem", {{3, 2, ysem_int_bb_b0_regs, ysem_prty_bb_b0_regs} } }, 1256 {"psem", {{3, 3, psem_int_bb_b0_regs, psem_prty_bb_b0_regs} } }, 1257 {"rss", {{1, 1, rss_int_bb_b0_regs, rss_prty_bb_b0_regs} } }, 1258 {"tmld", {{1, 1, tmld_int_bb_b0_regs, tmld_prty_bb_b0_regs} } }, 1259 {"muld", {{1, 1, muld_int_bb_b0_regs, muld_prty_bb_b0_regs} } }, 1260 {"yuld", {{1, 1, yuld_int_bb_b0_regs, yuld_prty_bb_b0_regs} } }, 1261 {"xyld", {{1, 1, xyld_int_bb_b0_regs, xyld_prty_bb_b0_regs} } }, 1262 {"prm", {{1, 2, prm_int_bb_b0_regs, prm_prty_bb_b0_regs} } }, 1263 {"pbf_pb1", {{1, 1, pbf_pb1_int_bb_b0_regs, 1264 pbf_pb1_prty_bb_b0_regs} } }, 1265 {"pbf_pb2", {{1, 1, pbf_pb2_int_bb_b0_regs, 1266 pbf_pb2_prty_bb_b0_regs} } }, 1267 {"rpb", { {1, 1, rpb_int_bb_b0_regs, rpb_prty_bb_b0_regs} } }, 1268 {"btb", { {11, 2, btb_int_bb_b0_regs, btb_prty_bb_b0_regs} } }, 1269 {"pbf", { {1, 3, pbf_int_bb_b0_regs, pbf_prty_bb_b0_regs} } }, 1270 {"rdif", { {1, 1, rdif_int_bb_b0_regs, rdif_prty_bb_b0_regs} } }, 1271 {"tdif", { {1, 2, tdif_int_bb_b0_regs, tdif_prty_bb_b0_regs} } }, 1272 {"cdu", { {1, 1, cdu_int_bb_b0_regs, cdu_prty_bb_b0_regs} } }, 1273 {"ccfc", { {1, 2, ccfc_int_bb_b0_regs, ccfc_prty_bb_b0_regs} } }, 1274 {"tcfc", { {1, 2, tcfc_int_bb_b0_regs, tcfc_prty_bb_b0_regs} } }, 1275 {"igu", { {1, 3, igu_int_bb_b0_regs, igu_prty_bb_b0_regs} } }, 1276 {"cau", { {1, 1, cau_int_bb_b0_regs, cau_prty_bb_b0_regs} } }, 1277 {"umac", { {0, 0, NULL, NULL} } }, 1278 {"xmac", { {0, 0, NULL, NULL} } }, 1279 {"dbg", { {1, 1, dbg_int_bb_b0_regs, dbg_prty_bb_b0_regs} } }, 1280 {"nig", { {6, 5, nig_int_bb_b0_regs, nig_prty_bb_b0_regs} } }, 1281 {"wol", { {0, 0, NULL, NULL} } }, 1282 {"bmbn", { {0, 0, NULL, NULL} } }, 1283 {"ipc", { {1, 1, ipc_int_bb_b0_regs, ipc_prty_bb_b0_regs} } }, 1284 {"nwm", { {0, 0, NULL, NULL} } }, 1285 {"nws", { {0, 0, NULL, NULL} } }, 1286 {"ms", { {0, 0, NULL, NULL} } }, 1287 {"phy_pcie", { {0, 0, NULL, NULL} } }, 1288 {"misc_aeu", { {0, 0, NULL, NULL} } }, 1289 {"bar0_map", { {0, 0, NULL, NULL} } },}; 1290 1291 /* Specific HW attention callbacks */ 1292 static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 1293 { 1294 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 1295 1296 /* This might occur on certain instances; Log it once then mask it */ 1297 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 1298 tmp); 1299 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 1300 0xffffffff); 1301 1302 return 0; 1303 } 1304 1305 #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 1306 #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 1307 #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 1308 #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 1309 #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 1310 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 1311 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 1312 #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 1313 #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 1314 #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 1315 #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 1316 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 1317 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 1318 static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 1319 { 1320 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1321 PSWHST_REG_INCORRECT_ACCESS_VALID); 1322 1323 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 1324 u32 addr, data, length; 1325 1326 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1327 PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 1328 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1329 PSWHST_REG_INCORRECT_ACCESS_DATA); 1330 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1331 PSWHST_REG_INCORRECT_ACCESS_LENGTH); 1332 1333 DP_INFO(p_hwfn->cdev, 1334 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 1335 addr, length, 1336 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 1337 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 1338 (u8) GET_FIELD(data, 1339 ATTENTION_INCORRECT_ACCESS_VF_VALID), 1340 (u8) GET_FIELD(data, 1341 ATTENTION_INCORRECT_ACCESS_CLIENT), 1342 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 1343 (u8) GET_FIELD(data, 1344 ATTENTION_INCORRECT_ACCESS_BYTE_EN), 1345 data); 1346 } 1347 1348 return 0; 1349 } 1350 1351 #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 1352 #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 1353 #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 1354 #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 1355 #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 1356 #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 1357 #define QED_GRC_ATTENTION_PF_MASK (0xf) 1358 #define QED_GRC_ATTENTION_PF_SHIFT (0) 1359 #define QED_GRC_ATTENTION_VF_MASK (0xff) 1360 #define QED_GRC_ATTENTION_VF_SHIFT (4) 1361 #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 1362 #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 1363 #define QED_GRC_ATTENTION_PRIV_VF (0) 1364 static const char *attn_master_to_str(u8 master) 1365 { 1366 switch (master) { 1367 case 1: return "PXP"; 1368 case 2: return "MCP"; 1369 case 3: return "MSDM"; 1370 case 4: return "PSDM"; 1371 case 5: return "YSDM"; 1372 case 6: return "USDM"; 1373 case 7: return "TSDM"; 1374 case 8: return "XSDM"; 1375 case 9: return "DBU"; 1376 case 10: return "DMAE"; 1377 default: 1378 return "Unkown"; 1379 } 1380 } 1381 1382 static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 1383 { 1384 u32 tmp, tmp2; 1385 1386 /* We've already cleared the timeout interrupt register, so we learn 1387 * of interrupts via the validity register 1388 */ 1389 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1390 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 1391 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 1392 goto out; 1393 1394 /* Read the GRC timeout information */ 1395 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1396 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 1397 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1398 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 1399 1400 DP_INFO(p_hwfn->cdev, 1401 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 1402 tmp2, tmp, 1403 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 1404 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 1405 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 1406 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 1407 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 1408 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Ireelevant)", 1409 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 1410 1411 out: 1412 /* Regardles of anything else, clean the validity bit */ 1413 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1414 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 1415 return 0; 1416 } 1417 1418 #define PGLUE_ATTENTION_VALID (1 << 29) 1419 #define PGLUE_ATTENTION_RD_VALID (1 << 26) 1420 #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 1421 #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 1422 #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 1423 #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 1424 #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 1425 #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 1426 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 1427 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 1428 #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 1429 #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 1430 #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 1431 #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 1432 #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 1433 #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 1434 #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 1435 static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn) 1436 { 1437 u32 tmp; 1438 1439 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1440 PGLUE_B_REG_TX_ERR_WR_DETAILS2); 1441 if (tmp & PGLUE_ATTENTION_VALID) { 1442 u32 addr_lo, addr_hi, details; 1443 1444 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1445 PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 1446 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1447 PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 1448 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1449 PGLUE_B_REG_TX_ERR_WR_DETAILS); 1450 1451 DP_INFO(p_hwfn, 1452 "Illegal write by chip to [%08x:%08x] blocked.\n" 1453 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 1454 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 1455 addr_hi, addr_lo, details, 1456 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 1457 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 1458 GET_FIELD(details, 1459 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 1460 tmp, 1461 GET_FIELD(tmp, 1462 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 1463 GET_FIELD(tmp, 1464 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 1465 GET_FIELD(tmp, 1466 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 1467 } 1468 1469 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1470 PGLUE_B_REG_TX_ERR_RD_DETAILS2); 1471 if (tmp & PGLUE_ATTENTION_RD_VALID) { 1472 u32 addr_lo, addr_hi, details; 1473 1474 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1475 PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 1476 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1477 PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 1478 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1479 PGLUE_B_REG_TX_ERR_RD_DETAILS); 1480 1481 DP_INFO(p_hwfn, 1482 "Illegal read by chip from [%08x:%08x] blocked.\n" 1483 " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 1484 " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 1485 addr_hi, addr_lo, details, 1486 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 1487 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 1488 GET_FIELD(details, 1489 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 1490 tmp, 1491 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 1492 : 0, 1493 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 1494 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 1495 : 0); 1496 } 1497 1498 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1499 PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 1500 if (tmp & PGLUE_ATTENTION_ICPL_VALID) 1501 DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp); 1502 1503 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1504 PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 1505 if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 1506 u32 addr_hi, addr_lo; 1507 1508 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1509 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 1510 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1511 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 1512 1513 DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n", 1514 tmp, addr_hi, addr_lo); 1515 } 1516 1517 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1518 PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 1519 if (tmp & PGLUE_ATTENTION_ILT_VALID) { 1520 u32 addr_hi, addr_lo, details; 1521 1522 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1523 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 1524 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1525 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 1526 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1527 PGLUE_B_REG_VF_ILT_ERR_DETAILS); 1528 1529 DP_INFO(p_hwfn, 1530 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 1531 details, tmp, addr_hi, addr_lo); 1532 } 1533 1534 /* Clear the indications */ 1535 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1536 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 1537 1538 return 0; 1539 } 1540 1541 #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 1542 #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 1543 #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 1544 #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 1545 static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 1546 { 1547 u32 reason; 1548 1549 reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) & 1550 QED_DORQ_ATTENTION_REASON_MASK; 1551 if (reason) { 1552 u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1553 DORQ_REG_DB_DROP_DETAILS); 1554 1555 DP_INFO(p_hwfn->cdev, 1556 "DORQ db_drop: adress 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n", 1557 qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1558 DORQ_REG_DB_DROP_DETAILS_ADDRESS), 1559 (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK), 1560 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 1561 reason); 1562 } 1563 1564 return -EINVAL; 1565 } 1566 1567 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 1568 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 1569 { 1570 { /* After Invert 1 */ 1571 {"GPIO0 function%d", 1572 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 1573 } 1574 }, 1575 1576 { 1577 { /* After Invert 2 */ 1578 {"PGLUE config_space", ATTENTION_SINGLE, 1579 NULL, MAX_BLOCK_ID}, 1580 {"PGLUE misc_flr", ATTENTION_SINGLE, 1581 NULL, MAX_BLOCK_ID}, 1582 {"PGLUE B RBC", ATTENTION_PAR_INT, 1583 qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 1584 {"PGLUE misc_mctp", ATTENTION_SINGLE, 1585 NULL, MAX_BLOCK_ID}, 1586 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1587 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1588 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1589 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 1590 (1 << ATTENTION_OFFSET_SHIFT), 1591 NULL, MAX_BLOCK_ID}, 1592 {"PCIE glue/PXP VPD %d", 1593 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 1594 } 1595 }, 1596 1597 { 1598 { /* After Invert 3 */ 1599 {"General Attention %d", 1600 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 1601 } 1602 }, 1603 1604 { 1605 { /* After Invert 4 */ 1606 {"General Attention 32", ATTENTION_SINGLE, 1607 NULL, MAX_BLOCK_ID}, 1608 {"General Attention %d", 1609 (2 << ATTENTION_LENGTH_SHIFT) | 1610 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 1611 {"General Attention 35", ATTENTION_SINGLE, 1612 NULL, MAX_BLOCK_ID}, 1613 {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), 1614 NULL, BLOCK_CNIG}, 1615 {"MCP CPU", ATTENTION_SINGLE, 1616 qed_mcp_attn_cb, MAX_BLOCK_ID}, 1617 {"MCP Watchdog timer", ATTENTION_SINGLE, 1618 NULL, MAX_BLOCK_ID}, 1619 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1620 {"AVS stop status ready", ATTENTION_SINGLE, 1621 NULL, MAX_BLOCK_ID}, 1622 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 1623 {"MSTAT per-path", ATTENTION_PAR_INT, 1624 NULL, MAX_BLOCK_ID}, 1625 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 1626 NULL, MAX_BLOCK_ID}, 1627 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 1628 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 1629 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 1630 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 1631 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 1632 } 1633 }, 1634 1635 { 1636 { /* After Invert 5 */ 1637 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 1638 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 1639 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 1640 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 1641 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 1642 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 1643 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 1644 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 1645 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 1646 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 1647 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 1648 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 1649 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 1650 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 1651 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 1652 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 1653 } 1654 }, 1655 1656 { 1657 { /* After Invert 6 */ 1658 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 1659 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 1660 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 1661 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 1662 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 1663 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 1664 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 1665 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 1666 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 1667 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 1668 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 1669 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 1670 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 1671 {"DORQ", ATTENTION_PAR_INT, 1672 qed_dorq_attn_cb, BLOCK_DORQ}, 1673 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 1674 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 1675 } 1676 }, 1677 1678 { 1679 { /* After Invert 7 */ 1680 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 1681 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 1682 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 1683 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 1684 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 1685 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 1686 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 1687 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 1688 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 1689 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 1690 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 1691 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 1692 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 1693 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 1694 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 1695 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 1696 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 1697 } 1698 }, 1699 1700 { 1701 { /* After Invert 8 */ 1702 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 1703 NULL, BLOCK_PSWRQ2}, 1704 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 1705 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 1706 NULL, BLOCK_PSWWR2}, 1707 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 1708 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 1709 NULL, BLOCK_PSWRD2}, 1710 {"PSWHST", ATTENTION_PAR_INT, 1711 qed_pswhst_attn_cb, BLOCK_PSWHST}, 1712 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 1713 NULL, BLOCK_PSWHST2}, 1714 {"GRC", ATTENTION_PAR_INT, 1715 qed_grc_attn_cb, BLOCK_GRC}, 1716 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 1717 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 1718 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1719 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1720 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1721 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1722 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1723 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1724 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 1725 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 1726 NULL, BLOCK_PGLCS}, 1727 {"PERST_B assertion", ATTENTION_SINGLE, 1728 NULL, MAX_BLOCK_ID}, 1729 {"PERST_B deassertion", ATTENTION_SINGLE, 1730 NULL, MAX_BLOCK_ID}, 1731 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 1732 NULL, MAX_BLOCK_ID}, 1733 } 1734 }, 1735 1736 { 1737 { /* After Invert 9 */ 1738 {"MCP Latched memory", ATTENTION_PAR, 1739 NULL, MAX_BLOCK_ID}, 1740 {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 1741 NULL, MAX_BLOCK_ID}, 1742 {"MCP Latched ump_tx", ATTENTION_PAR, 1743 NULL, MAX_BLOCK_ID}, 1744 {"MCP Latched scratchpad", ATTENTION_PAR, 1745 NULL, MAX_BLOCK_ID}, 1746 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 1747 NULL, MAX_BLOCK_ID}, 1748 } 1749 }, 1750 }; 1751 1752 #define ATTN_STATE_BITS (0xfff) 1753 #define ATTN_BITS_MASKABLE (0x3ff) 1754 struct qed_sb_attn_info { 1755 /* Virtual & Physical address of the SB */ 1756 struct atten_status_block *sb_attn; 1757 dma_addr_t sb_phys; 1758 1759 /* Last seen running index */ 1760 u16 index; 1761 1762 /* A mask of the AEU bits resulting in a parity error */ 1763 u32 parity_mask[NUM_ATTN_REGS]; 1764 1765 /* A pointer to the attention description structure */ 1766 struct aeu_invert_reg *p_aeu_desc; 1767 1768 /* Previously asserted attentions, which are still unasserted */ 1769 u16 known_attn; 1770 1771 /* Cleanup address for the link's general hw attention */ 1772 u32 mfw_attn_addr; 1773 }; 1774 1775 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 1776 struct qed_sb_attn_info *p_sb_desc) 1777 { 1778 u16 rc = 0; 1779 u16 index; 1780 1781 /* Make certain HW write took affect */ 1782 mmiowb(); 1783 1784 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 1785 if (p_sb_desc->index != index) { 1786 p_sb_desc->index = index; 1787 rc = QED_SB_ATT_IDX; 1788 } 1789 1790 /* Make certain we got a consistent view with HW */ 1791 mmiowb(); 1792 1793 return rc; 1794 } 1795 1796 /** 1797 * @brief qed_int_assertion - handles asserted attention bits 1798 * 1799 * @param p_hwfn 1800 * @param asserted_bits newly asserted bits 1801 * @return int 1802 */ 1803 static int qed_int_assertion(struct qed_hwfn *p_hwfn, 1804 u16 asserted_bits) 1805 { 1806 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 1807 u32 igu_mask; 1808 1809 /* Mask the source of the attention in the IGU */ 1810 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1811 IGU_REG_ATTENTION_ENABLE); 1812 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 1813 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 1814 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 1815 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 1816 1817 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1818 "inner known ATTN state: 0x%04x --> 0x%04x\n", 1819 sb_attn_sw->known_attn, 1820 sb_attn_sw->known_attn | asserted_bits); 1821 sb_attn_sw->known_attn |= asserted_bits; 1822 1823 /* Handle MCP events */ 1824 if (asserted_bits & 0x100) { 1825 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 1826 /* Clean the MCP attention */ 1827 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1828 sb_attn_sw->mfw_attn_addr, 0); 1829 } 1830 1831 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1832 GTT_BAR0_MAP_REG_IGU_CMD + 1833 ((IGU_CMD_ATTN_BIT_SET_UPPER - 1834 IGU_CMD_INT_ACK_BASE) << 3), 1835 (u32)asserted_bits); 1836 1837 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 1838 asserted_bits); 1839 1840 return 0; 1841 } 1842 1843 static void qed_int_deassertion_print_bit(struct qed_hwfn *p_hwfn, 1844 struct attn_hw_reg *p_reg_desc, 1845 struct attn_hw_block *p_block, 1846 enum qed_attention_type type, 1847 u32 val, u32 mask) 1848 { 1849 int j; 1850 1851 for (j = 0; j < p_reg_desc->num_of_bits; j++) { 1852 if (!(val & (1 << j))) 1853 continue; 1854 1855 DP_NOTICE(p_hwfn, 1856 "%s (%s): reg %d [0x%08x], bit %d [%s]\n", 1857 p_block->name, 1858 type == QED_ATTN_TYPE_ATTN ? "Interrupt" : 1859 "Parity", 1860 p_reg_desc->reg_idx, p_reg_desc->sts_addr, 1861 j, (mask & (1 << j)) ? " [MASKED]" : ""); 1862 } 1863 } 1864 1865 /** 1866 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 1867 * cause of the attention 1868 * 1869 * @param p_hwfn 1870 * @param p_aeu - descriptor of an AEU bit which caused the attention 1871 * @param aeu_en_reg - register offset of the AEU enable reg. which configured 1872 * this bit to this group. 1873 * @param bit_index - index of this bit in the aeu_en_reg 1874 * 1875 * @return int 1876 */ 1877 static int 1878 qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 1879 struct aeu_invert_reg_bit *p_aeu, 1880 u32 aeu_en_reg, 1881 u32 bitmask) 1882 { 1883 int rc = -EINVAL; 1884 u32 val; 1885 1886 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 1887 p_aeu->bit_name, bitmask); 1888 1889 /* Call callback before clearing the interrupt status */ 1890 if (p_aeu->cb) { 1891 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 1892 p_aeu->bit_name); 1893 rc = p_aeu->cb(p_hwfn); 1894 } 1895 1896 /* Handle HW block interrupt registers */ 1897 if (p_aeu->block_index != MAX_BLOCK_ID) { 1898 struct attn_hw_block *p_block; 1899 u32 mask; 1900 int i; 1901 1902 p_block = &attn_blocks[p_aeu->block_index]; 1903 1904 /* Handle each interrupt register */ 1905 for (i = 0; i < p_block->chip_regs[0].num_of_int_regs; i++) { 1906 struct attn_hw_reg *p_reg_desc; 1907 u32 sts_addr; 1908 1909 p_reg_desc = p_block->chip_regs[0].int_regs[i]; 1910 1911 /* In case of fatal attention, don't clear the status 1912 * so it would appear in following idle check. 1913 */ 1914 if (rc == 0) 1915 sts_addr = p_reg_desc->sts_clr_addr; 1916 else 1917 sts_addr = p_reg_desc->sts_addr; 1918 1919 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr); 1920 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1921 p_reg_desc->mask_addr); 1922 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc, 1923 p_block, 1924 QED_ATTN_TYPE_ATTN, 1925 val, mask); 1926 } 1927 } 1928 1929 /* If the attention is benign, no need to prevent it */ 1930 if (!rc) 1931 goto out; 1932 1933 /* Prevent this Attention from being asserted in the future */ 1934 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 1935 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 1936 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 1937 p_aeu->bit_name); 1938 1939 out: 1940 return rc; 1941 } 1942 1943 static void qed_int_parity_print(struct qed_hwfn *p_hwfn, 1944 struct aeu_invert_reg_bit *p_aeu, 1945 struct attn_hw_block *p_block, 1946 u8 bit_index) 1947 { 1948 int i; 1949 1950 for (i = 0; i < p_block->chip_regs[0].num_of_prty_regs; i++) { 1951 struct attn_hw_reg *p_reg_desc; 1952 u32 val, mask; 1953 1954 p_reg_desc = p_block->chip_regs[0].prty_regs[i]; 1955 1956 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1957 p_reg_desc->sts_clr_addr); 1958 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1959 p_reg_desc->mask_addr); 1960 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc, 1961 p_block, 1962 QED_ATTN_TYPE_PARITY, 1963 val, mask); 1964 } 1965 } 1966 1967 /** 1968 * @brief qed_int_deassertion_parity - handle a single parity AEU source 1969 * 1970 * @param p_hwfn 1971 * @param p_aeu - descriptor of an AEU bit which caused the parity 1972 * @param bit_index 1973 */ 1974 static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 1975 struct aeu_invert_reg_bit *p_aeu, 1976 u8 bit_index) 1977 { 1978 u32 block_id = p_aeu->block_index; 1979 1980 DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n", 1981 p_aeu->bit_name, bit_index); 1982 1983 if (block_id != MAX_BLOCK_ID) { 1984 qed_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id], 1985 bit_index); 1986 1987 /* In BB, there's a single parity bit for several blocks */ 1988 if (block_id == BLOCK_BTB) { 1989 qed_int_parity_print(p_hwfn, p_aeu, 1990 &attn_blocks[BLOCK_OPTE], 1991 bit_index); 1992 qed_int_parity_print(p_hwfn, p_aeu, 1993 &attn_blocks[BLOCK_MCP], 1994 bit_index); 1995 } 1996 } 1997 } 1998 1999 /** 2000 * @brief - handles deassertion of previously asserted attentions. 2001 * 2002 * @param p_hwfn 2003 * @param deasserted_bits - newly deasserted bits 2004 * @return int 2005 * 2006 */ 2007 static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 2008 u16 deasserted_bits) 2009 { 2010 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 2011 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask; 2012 u8 i, j, k, bit_idx; 2013 int rc = 0; 2014 2015 /* Read the attention registers in the AEU */ 2016 for (i = 0; i < NUM_ATTN_REGS; i++) { 2017 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 2018 MISC_REG_AEU_AFTER_INVERT_1_IGU + 2019 i * 0x4); 2020 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2021 "Deasserted bits [%d]: %08x\n", 2022 i, aeu_inv_arr[i]); 2023 } 2024 2025 /* Find parity attentions first */ 2026 for (i = 0; i < NUM_ATTN_REGS; i++) { 2027 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 2028 u32 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 2029 MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 2030 i * sizeof(u32)); 2031 u32 parities; 2032 2033 /* Skip register in which no parity bit is currently set */ 2034 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 2035 if (!parities) 2036 continue; 2037 2038 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 2039 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 2040 2041 if ((p_bit->flags & ATTENTION_PARITY) && 2042 !!(parities & (1 << bit_idx))) 2043 qed_int_deassertion_parity(p_hwfn, p_bit, 2044 bit_idx); 2045 2046 bit_idx += ATTENTION_LENGTH(p_bit->flags); 2047 } 2048 } 2049 2050 /* Find non-parity cause for attention and act */ 2051 for (k = 0; k < MAX_ATTN_GRPS; k++) { 2052 struct aeu_invert_reg_bit *p_aeu; 2053 2054 /* Handle only groups whose attention is currently deasserted */ 2055 if (!(deasserted_bits & (1 << k))) 2056 continue; 2057 2058 for (i = 0; i < NUM_ATTN_REGS; i++) { 2059 u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 2060 i * sizeof(u32) + 2061 k * sizeof(u32) * NUM_ATTN_REGS; 2062 u32 en, bits; 2063 2064 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 2065 bits = aeu_inv_arr[i] & en; 2066 2067 /* Skip if no bit from this group is currently set */ 2068 if (!bits) 2069 continue; 2070 2071 /* Find all set bits from current register which belong 2072 * to current group, making them responsible for the 2073 * previous assertion. 2074 */ 2075 for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 2076 u8 bit, bit_len; 2077 u32 bitmask; 2078 2079 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 2080 2081 /* No need to handle parity-only bits */ 2082 if (p_aeu->flags == ATTENTION_PAR) 2083 continue; 2084 2085 bit = bit_idx; 2086 bit_len = ATTENTION_LENGTH(p_aeu->flags); 2087 if (p_aeu->flags & ATTENTION_PAR_INT) { 2088 /* Skip Parity */ 2089 bit++; 2090 bit_len--; 2091 } 2092 2093 bitmask = bits & (((1 << bit_len) - 1) << bit); 2094 if (bitmask) { 2095 /* Handle source of the attention */ 2096 qed_int_deassertion_aeu_bit(p_hwfn, 2097 p_aeu, 2098 aeu_en, 2099 bitmask); 2100 } 2101 2102 bit_idx += ATTENTION_LENGTH(p_aeu->flags); 2103 } 2104 } 2105 } 2106 2107 /* Clear IGU indication for the deasserted bits */ 2108 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 2109 GTT_BAR0_MAP_REG_IGU_CMD + 2110 ((IGU_CMD_ATTN_BIT_CLR_UPPER - 2111 IGU_CMD_INT_ACK_BASE) << 3), 2112 ~((u32)deasserted_bits)); 2113 2114 /* Unmask deasserted attentions in IGU */ 2115 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 2116 IGU_REG_ATTENTION_ENABLE); 2117 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 2118 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 2119 2120 /* Clear deassertion from inner state */ 2121 sb_attn_sw->known_attn &= ~deasserted_bits; 2122 2123 return rc; 2124 } 2125 2126 static int qed_int_attentions(struct qed_hwfn *p_hwfn) 2127 { 2128 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 2129 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 2130 u32 attn_bits = 0, attn_acks = 0; 2131 u16 asserted_bits, deasserted_bits; 2132 __le16 index; 2133 int rc = 0; 2134 2135 /* Read current attention bits/acks - safeguard against attentions 2136 * by guaranting work on a synchronized timeframe 2137 */ 2138 do { 2139 index = p_sb_attn->sb_index; 2140 attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 2141 attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 2142 } while (index != p_sb_attn->sb_index); 2143 p_sb_attn->sb_index = index; 2144 2145 /* Attention / Deassertion are meaningful (and in correct state) 2146 * only when they differ and consistent with known state - deassertion 2147 * when previous attention & current ack, and assertion when current 2148 * attention with no previous attention 2149 */ 2150 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 2151 ~p_sb_attn_sw->known_attn; 2152 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 2153 p_sb_attn_sw->known_attn; 2154 2155 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 2156 DP_INFO(p_hwfn, 2157 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 2158 index, attn_bits, attn_acks, asserted_bits, 2159 deasserted_bits, p_sb_attn_sw->known_attn); 2160 } else if (asserted_bits == 0x100) { 2161 DP_INFO(p_hwfn, 2162 "MFW indication via attention\n"); 2163 } else { 2164 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2165 "MFW indication [deassertion]\n"); 2166 } 2167 2168 if (asserted_bits) { 2169 rc = qed_int_assertion(p_hwfn, asserted_bits); 2170 if (rc) 2171 return rc; 2172 } 2173 2174 if (deasserted_bits) { 2175 rc = qed_int_deassertion(p_hwfn, deasserted_bits); 2176 if (rc) 2177 return rc; 2178 } 2179 2180 return rc; 2181 } 2182 2183 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 2184 void __iomem *igu_addr, 2185 u32 ack_cons) 2186 { 2187 struct igu_prod_cons_update igu_ack = { 0 }; 2188 2189 igu_ack.sb_id_and_flags = 2190 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 2191 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 2192 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 2193 (IGU_SEG_ACCESS_ATTN << 2194 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 2195 2196 DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 2197 2198 /* Both segments (interrupts & acks) are written to same place address; 2199 * Need to guarantee all commands will be received (in-order) by HW. 2200 */ 2201 mmiowb(); 2202 barrier(); 2203 } 2204 2205 void qed_int_sp_dpc(unsigned long hwfn_cookie) 2206 { 2207 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 2208 struct qed_pi_info *pi_info = NULL; 2209 struct qed_sb_attn_info *sb_attn; 2210 struct qed_sb_info *sb_info; 2211 int arr_size; 2212 u16 rc = 0; 2213 2214 if (!p_hwfn->p_sp_sb) { 2215 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 2216 return; 2217 } 2218 2219 sb_info = &p_hwfn->p_sp_sb->sb_info; 2220 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 2221 if (!sb_info) { 2222 DP_ERR(p_hwfn->cdev, 2223 "Status block is NULL - cannot ack interrupts\n"); 2224 return; 2225 } 2226 2227 if (!p_hwfn->p_sb_attn) { 2228 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 2229 return; 2230 } 2231 sb_attn = p_hwfn->p_sb_attn; 2232 2233 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 2234 p_hwfn, p_hwfn->my_id); 2235 2236 /* Disable ack for def status block. Required both for msix + 2237 * inta in non-mask mode, in inta does no harm. 2238 */ 2239 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 2240 2241 /* Gather Interrupts/Attentions information */ 2242 if (!sb_info->sb_virt) { 2243 DP_ERR( 2244 p_hwfn->cdev, 2245 "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 2246 } else { 2247 u32 tmp_index = sb_info->sb_ack; 2248 2249 rc = qed_sb_update_sb_idx(sb_info); 2250 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 2251 "Interrupt indices: 0x%08x --> 0x%08x\n", 2252 tmp_index, sb_info->sb_ack); 2253 } 2254 2255 if (!sb_attn || !sb_attn->sb_attn) { 2256 DP_ERR( 2257 p_hwfn->cdev, 2258 "Attentions Status block is NULL - cannot check for new attentions!\n"); 2259 } else { 2260 u16 tmp_index = sb_attn->index; 2261 2262 rc |= qed_attn_update_idx(p_hwfn, sb_attn); 2263 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 2264 "Attention indices: 0x%08x --> 0x%08x\n", 2265 tmp_index, sb_attn->index); 2266 } 2267 2268 /* Check if we expect interrupts at this time. if not just ack them */ 2269 if (!(rc & QED_SB_EVENT_MASK)) { 2270 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2271 return; 2272 } 2273 2274 /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 2275 if (!p_hwfn->p_dpc_ptt) { 2276 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 2277 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2278 return; 2279 } 2280 2281 if (rc & QED_SB_ATT_IDX) 2282 qed_int_attentions(p_hwfn); 2283 2284 if (rc & QED_SB_IDX) { 2285 int pi; 2286 2287 /* Look for a free index */ 2288 for (pi = 0; pi < arr_size; pi++) { 2289 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 2290 if (pi_info->comp_cb) 2291 pi_info->comp_cb(p_hwfn, pi_info->cookie); 2292 } 2293 } 2294 2295 if (sb_attn && (rc & QED_SB_ATT_IDX)) 2296 /* This should be done before the interrupts are enabled, 2297 * since otherwise a new attention will be generated. 2298 */ 2299 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 2300 2301 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2302 } 2303 2304 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 2305 { 2306 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 2307 2308 if (!p_sb) 2309 return; 2310 2311 if (p_sb->sb_attn) 2312 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2313 SB_ATTN_ALIGNED_SIZE(p_hwfn), 2314 p_sb->sb_attn, 2315 p_sb->sb_phys); 2316 kfree(p_sb); 2317 } 2318 2319 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 2320 struct qed_ptt *p_ptt) 2321 { 2322 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 2323 2324 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 2325 2326 sb_info->index = 0; 2327 sb_info->known_attn = 0; 2328 2329 /* Configure Attention Status Block in IGU */ 2330 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 2331 lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 2332 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 2333 upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 2334 } 2335 2336 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 2337 struct qed_ptt *p_ptt, 2338 void *sb_virt_addr, 2339 dma_addr_t sb_phy_addr) 2340 { 2341 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 2342 int i, j, k; 2343 2344 sb_info->sb_attn = sb_virt_addr; 2345 sb_info->sb_phys = sb_phy_addr; 2346 2347 /* Set the pointer to the AEU descriptors */ 2348 sb_info->p_aeu_desc = aeu_descs; 2349 2350 /* Calculate Parity Masks */ 2351 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 2352 for (i = 0; i < NUM_ATTN_REGS; i++) { 2353 /* j is array index, k is bit index */ 2354 for (j = 0, k = 0; k < 32; j++) { 2355 unsigned int flags = aeu_descs[i].bits[j].flags; 2356 2357 if (flags & ATTENTION_PARITY) 2358 sb_info->parity_mask[i] |= 1 << k; 2359 2360 k += ATTENTION_LENGTH(flags); 2361 } 2362 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2363 "Attn Mask [Reg %d]: 0x%08x\n", 2364 i, sb_info->parity_mask[i]); 2365 } 2366 2367 /* Set the address of cleanup for the mcp attention */ 2368 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 2369 MISC_REG_AEU_GENERAL_ATTN_0; 2370 2371 qed_int_sb_attn_setup(p_hwfn, p_ptt); 2372 } 2373 2374 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 2375 struct qed_ptt *p_ptt) 2376 { 2377 struct qed_dev *cdev = p_hwfn->cdev; 2378 struct qed_sb_attn_info *p_sb; 2379 void *p_virt; 2380 dma_addr_t p_phys = 0; 2381 2382 /* SB struct */ 2383 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 2384 if (!p_sb) { 2385 DP_NOTICE(cdev, "Failed to allocate `struct qed_sb_attn_info'\n"); 2386 return -ENOMEM; 2387 } 2388 2389 /* SB ring */ 2390 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2391 SB_ATTN_ALIGNED_SIZE(p_hwfn), 2392 &p_phys, GFP_KERNEL); 2393 2394 if (!p_virt) { 2395 DP_NOTICE(cdev, "Failed to allocate status block (attentions)\n"); 2396 kfree(p_sb); 2397 return -ENOMEM; 2398 } 2399 2400 /* Attention setup */ 2401 p_hwfn->p_sb_attn = p_sb; 2402 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 2403 2404 return 0; 2405 } 2406 2407 /* coalescing timeout = timeset << (timer_res + 1) */ 2408 #define QED_CAU_DEF_RX_USECS 24 2409 #define QED_CAU_DEF_TX_USECS 48 2410 2411 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 2412 struct cau_sb_entry *p_sb_entry, 2413 u8 pf_id, 2414 u16 vf_number, 2415 u8 vf_valid) 2416 { 2417 struct qed_dev *cdev = p_hwfn->cdev; 2418 u32 cau_state; 2419 2420 memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 2421 2422 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 2423 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 2424 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 2425 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 2426 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 2427 2428 /* setting the time resultion to a fixed value ( = 1) */ 2429 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, 2430 QED_CAU_DEF_RX_TIMER_RES); 2431 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, 2432 QED_CAU_DEF_TX_TIMER_RES); 2433 2434 cau_state = CAU_HC_DISABLE_STATE; 2435 2436 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 2437 cau_state = CAU_HC_ENABLE_STATE; 2438 if (!cdev->rx_coalesce_usecs) 2439 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 2440 if (!cdev->tx_coalesce_usecs) 2441 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 2442 } 2443 2444 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 2445 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 2446 } 2447 2448 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 2449 struct qed_ptt *p_ptt, 2450 dma_addr_t sb_phys, 2451 u16 igu_sb_id, 2452 u16 vf_number, 2453 u8 vf_valid) 2454 { 2455 struct cau_sb_entry sb_entry; 2456 2457 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 2458 vf_number, vf_valid); 2459 2460 if (p_hwfn->hw_init_done) { 2461 /* Wide-bus, initialize via DMAE */ 2462 u64 phys_addr = (u64)sb_phys; 2463 2464 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 2465 CAU_REG_SB_ADDR_MEMORY + 2466 igu_sb_id * sizeof(u64), 2, 0); 2467 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 2468 CAU_REG_SB_VAR_MEMORY + 2469 igu_sb_id * sizeof(u64), 2, 0); 2470 } else { 2471 /* Initialize Status Block Address */ 2472 STORE_RT_REG_AGG(p_hwfn, 2473 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 2474 igu_sb_id * 2, 2475 sb_phys); 2476 2477 STORE_RT_REG_AGG(p_hwfn, 2478 CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 2479 igu_sb_id * 2, 2480 sb_entry); 2481 } 2482 2483 /* Configure pi coalescing if set */ 2484 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 2485 u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >> 2486 (QED_CAU_DEF_RX_TIMER_RES + 1); 2487 u8 num_tc = 1, i; 2488 2489 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 2490 QED_COAL_RX_STATE_MACHINE, 2491 timeset); 2492 2493 timeset = p_hwfn->cdev->tx_coalesce_usecs >> 2494 (QED_CAU_DEF_TX_TIMER_RES + 1); 2495 2496 for (i = 0; i < num_tc; i++) { 2497 qed_int_cau_conf_pi(p_hwfn, p_ptt, 2498 igu_sb_id, TX_PI(i), 2499 QED_COAL_TX_STATE_MACHINE, 2500 timeset); 2501 } 2502 } 2503 } 2504 2505 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 2506 struct qed_ptt *p_ptt, 2507 u16 igu_sb_id, 2508 u32 pi_index, 2509 enum qed_coalescing_fsm coalescing_fsm, 2510 u8 timeset) 2511 { 2512 struct cau_pi_entry pi_entry; 2513 u32 sb_offset; 2514 u32 pi_offset; 2515 2516 sb_offset = igu_sb_id * PIS_PER_SB; 2517 memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 2518 2519 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 2520 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 2521 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 2522 else 2523 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 2524 2525 pi_offset = sb_offset + pi_index; 2526 if (p_hwfn->hw_init_done) { 2527 qed_wr(p_hwfn, p_ptt, 2528 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 2529 *((u32 *)&(pi_entry))); 2530 } else { 2531 STORE_RT_REG(p_hwfn, 2532 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 2533 *((u32 *)&(pi_entry))); 2534 } 2535 } 2536 2537 void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 2538 struct qed_ptt *p_ptt, 2539 struct qed_sb_info *sb_info) 2540 { 2541 /* zero status block and ack counter */ 2542 sb_info->sb_ack = 0; 2543 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 2544 2545 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 2546 sb_info->igu_sb_id, 0, 0); 2547 } 2548 2549 /** 2550 * @brief qed_get_igu_sb_id - given a sw sb_id return the 2551 * igu_sb_id 2552 * 2553 * @param p_hwfn 2554 * @param sb_id 2555 * 2556 * @return u16 2557 */ 2558 static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, 2559 u16 sb_id) 2560 { 2561 u16 igu_sb_id; 2562 2563 /* Assuming continuous set of IGU SBs dedicated for given PF */ 2564 if (sb_id == QED_SP_SB_ID) 2565 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 2566 else 2567 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb; 2568 2569 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "SB [%s] index is 0x%04x\n", 2570 (sb_id == QED_SP_SB_ID) ? "DSB" : "non-DSB", igu_sb_id); 2571 2572 return igu_sb_id; 2573 } 2574 2575 int qed_int_sb_init(struct qed_hwfn *p_hwfn, 2576 struct qed_ptt *p_ptt, 2577 struct qed_sb_info *sb_info, 2578 void *sb_virt_addr, 2579 dma_addr_t sb_phy_addr, 2580 u16 sb_id) 2581 { 2582 sb_info->sb_virt = sb_virt_addr; 2583 sb_info->sb_phys = sb_phy_addr; 2584 2585 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 2586 2587 if (sb_id != QED_SP_SB_ID) { 2588 p_hwfn->sbs_info[sb_id] = sb_info; 2589 p_hwfn->num_sbs++; 2590 } 2591 2592 sb_info->cdev = p_hwfn->cdev; 2593 2594 /* The igu address will hold the absolute address that needs to be 2595 * written to for a specific status block 2596 */ 2597 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 2598 GTT_BAR0_MAP_REG_IGU_CMD + 2599 (sb_info->igu_sb_id << 3); 2600 2601 sb_info->flags |= QED_SB_INFO_INIT; 2602 2603 qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 2604 2605 return 0; 2606 } 2607 2608 int qed_int_sb_release(struct qed_hwfn *p_hwfn, 2609 struct qed_sb_info *sb_info, 2610 u16 sb_id) 2611 { 2612 if (sb_id == QED_SP_SB_ID) { 2613 DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 2614 return -EINVAL; 2615 } 2616 2617 /* zero status block and ack counter */ 2618 sb_info->sb_ack = 0; 2619 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 2620 2621 if (p_hwfn->sbs_info[sb_id] != NULL) { 2622 p_hwfn->sbs_info[sb_id] = NULL; 2623 p_hwfn->num_sbs--; 2624 } 2625 2626 return 0; 2627 } 2628 2629 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 2630 { 2631 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 2632 2633 if (!p_sb) 2634 return; 2635 2636 if (p_sb->sb_info.sb_virt) 2637 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2638 SB_ALIGNED_SIZE(p_hwfn), 2639 p_sb->sb_info.sb_virt, 2640 p_sb->sb_info.sb_phys); 2641 kfree(p_sb); 2642 } 2643 2644 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, 2645 struct qed_ptt *p_ptt) 2646 { 2647 struct qed_sb_sp_info *p_sb; 2648 dma_addr_t p_phys = 0; 2649 void *p_virt; 2650 2651 /* SB struct */ 2652 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 2653 if (!p_sb) { 2654 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sb_info'\n"); 2655 return -ENOMEM; 2656 } 2657 2658 /* SB ring */ 2659 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2660 SB_ALIGNED_SIZE(p_hwfn), 2661 &p_phys, GFP_KERNEL); 2662 if (!p_virt) { 2663 DP_NOTICE(p_hwfn, "Failed to allocate status block\n"); 2664 kfree(p_sb); 2665 return -ENOMEM; 2666 } 2667 2668 /* Status Block setup */ 2669 p_hwfn->p_sp_sb = p_sb; 2670 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 2671 p_phys, QED_SP_SB_ID); 2672 2673 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 2674 2675 return 0; 2676 } 2677 2678 int qed_int_register_cb(struct qed_hwfn *p_hwfn, 2679 qed_int_comp_cb_t comp_cb, 2680 void *cookie, 2681 u8 *sb_idx, 2682 __le16 **p_fw_cons) 2683 { 2684 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 2685 int rc = -ENOMEM; 2686 u8 pi; 2687 2688 /* Look for a free index */ 2689 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 2690 if (p_sp_sb->pi_info_arr[pi].comp_cb) 2691 continue; 2692 2693 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 2694 p_sp_sb->pi_info_arr[pi].cookie = cookie; 2695 *sb_idx = pi; 2696 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 2697 rc = 0; 2698 break; 2699 } 2700 2701 return rc; 2702 } 2703 2704 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 2705 { 2706 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 2707 2708 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 2709 return -ENOMEM; 2710 2711 p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 2712 p_sp_sb->pi_info_arr[pi].cookie = NULL; 2713 2714 return 0; 2715 } 2716 2717 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 2718 { 2719 return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 2720 } 2721 2722 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 2723 struct qed_ptt *p_ptt, 2724 enum qed_int_mode int_mode) 2725 { 2726 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 2727 2728 p_hwfn->cdev->int_mode = int_mode; 2729 switch (p_hwfn->cdev->int_mode) { 2730 case QED_INT_MODE_INTA: 2731 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 2732 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 2733 break; 2734 2735 case QED_INT_MODE_MSI: 2736 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 2737 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 2738 break; 2739 2740 case QED_INT_MODE_MSIX: 2741 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 2742 break; 2743 case QED_INT_MODE_POLL: 2744 break; 2745 } 2746 2747 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 2748 } 2749 2750 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2751 enum qed_int_mode int_mode) 2752 { 2753 int rc; 2754 2755 /* Configure AEU signal change to produce attentions */ 2756 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 2757 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 2758 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 2759 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 2760 2761 /* Flush the writes to IGU */ 2762 mmiowb(); 2763 2764 /* Unmask AEU signals toward IGU */ 2765 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 2766 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 2767 rc = qed_slowpath_irq_req(p_hwfn); 2768 if (rc != 0) { 2769 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 2770 return -EINVAL; 2771 } 2772 p_hwfn->b_int_requested = true; 2773 } 2774 /* Enable interrupt Generation */ 2775 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 2776 p_hwfn->b_int_enabled = 1; 2777 2778 return rc; 2779 } 2780 2781 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 2782 struct qed_ptt *p_ptt) 2783 { 2784 p_hwfn->b_int_enabled = 0; 2785 2786 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 2787 } 2788 2789 #define IGU_CLEANUP_SLEEP_LENGTH (1000) 2790 void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 2791 struct qed_ptt *p_ptt, 2792 u32 sb_id, 2793 bool cleanup_set, 2794 u16 opaque_fid 2795 ) 2796 { 2797 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id; 2798 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 2799 u32 data = 0; 2800 u32 cmd_ctrl = 0; 2801 u32 val = 0; 2802 u32 sb_bit = 0; 2803 u32 sb_bit_addr = 0; 2804 2805 /* Set the data field */ 2806 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 2807 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 2808 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 2809 2810 /* Set the control register */ 2811 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 2812 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 2813 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 2814 2815 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 2816 2817 barrier(); 2818 2819 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 2820 2821 /* Flush the write to IGU */ 2822 mmiowb(); 2823 2824 /* calculate where to read the status bit from */ 2825 sb_bit = 1 << (sb_id % 32); 2826 sb_bit_addr = sb_id / 32 * sizeof(u32); 2827 2828 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 2829 2830 /* Now wait for the command to complete */ 2831 do { 2832 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 2833 2834 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 2835 break; 2836 2837 usleep_range(5000, 10000); 2838 } while (--sleep_cnt); 2839 2840 if (!sleep_cnt) 2841 DP_NOTICE(p_hwfn, 2842 "Timeout waiting for clear status 0x%08x [for sb %d]\n", 2843 val, sb_id); 2844 } 2845 2846 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 2847 struct qed_ptt *p_ptt, 2848 u32 sb_id, 2849 u16 opaque, 2850 bool b_set) 2851 { 2852 int pi; 2853 2854 /* Set */ 2855 if (b_set) 2856 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque); 2857 2858 /* Clear */ 2859 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque); 2860 2861 /* Clear the CAU for the SB */ 2862 for (pi = 0; pi < 12; pi++) 2863 qed_wr(p_hwfn, p_ptt, 2864 CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0); 2865 } 2866 2867 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 2868 struct qed_ptt *p_ptt, 2869 bool b_set, 2870 bool b_slowpath) 2871 { 2872 u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb; 2873 u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt; 2874 u32 sb_id = 0; 2875 u32 val = 0; 2876 2877 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 2878 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 2879 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 2880 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 2881 2882 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2883 "IGU cleaning SBs [%d,...,%d]\n", 2884 igu_base_sb, igu_base_sb + igu_sb_cnt - 1); 2885 2886 for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++) 2887 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 2888 p_hwfn->hw_info.opaque_fid, 2889 b_set); 2890 2891 if (b_slowpath) { 2892 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 2893 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2894 "IGU cleaning slowpath SB [%d]\n", sb_id); 2895 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 2896 p_hwfn->hw_info.opaque_fid, 2897 b_set); 2898 } 2899 } 2900 2901 static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2902 struct qed_ptt *p_ptt, 2903 u16 sb_id) 2904 { 2905 u32 val = qed_rd(p_hwfn, p_ptt, 2906 IGU_REG_MAPPING_MEMORY + 2907 sizeof(u32) * sb_id); 2908 struct qed_igu_block *p_block; 2909 2910 p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id]; 2911 2912 /* stop scanning when hit first invalid PF entry */ 2913 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 2914 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 2915 goto out; 2916 2917 /* Fill the block information */ 2918 p_block->status = QED_IGU_STATUS_VALID; 2919 p_block->function_id = GET_FIELD(val, 2920 IGU_MAPPING_LINE_FUNCTION_NUMBER); 2921 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2922 p_block->vector_number = GET_FIELD(val, 2923 IGU_MAPPING_LINE_VECTOR_NUMBER); 2924 2925 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2926 "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2927 sb_id, val, p_block->function_id, 2928 p_block->is_pf, p_block->vector_number); 2929 2930 out: 2931 return val; 2932 } 2933 2934 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 2935 struct qed_ptt *p_ptt) 2936 { 2937 struct qed_igu_info *p_igu_info; 2938 struct qed_igu_block *blk; 2939 u32 val; 2940 u16 sb_id; 2941 u16 prev_sb_id = 0xFF; 2942 2943 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2944 2945 if (!p_hwfn->hw_info.p_igu_info) 2946 return -ENOMEM; 2947 2948 p_igu_info = p_hwfn->hw_info.p_igu_info; 2949 2950 /* Initialize base sb / sb cnt for PFs */ 2951 p_igu_info->igu_base_sb = 0xffff; 2952 p_igu_info->igu_sb_cnt = 0; 2953 p_igu_info->igu_dsb_id = 0xffff; 2954 p_igu_info->igu_base_sb_iov = 0xffff; 2955 2956 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 2957 sb_id++) { 2958 blk = &p_igu_info->igu_map.igu_blocks[sb_id]; 2959 2960 val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id); 2961 2962 /* stop scanning when hit first invalid PF entry */ 2963 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 2964 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 2965 break; 2966 2967 if (blk->is_pf) { 2968 if (blk->function_id == p_hwfn->rel_pf_id) { 2969 blk->status |= QED_IGU_STATUS_PF; 2970 2971 if (blk->vector_number == 0) { 2972 if (p_igu_info->igu_dsb_id == 0xffff) 2973 p_igu_info->igu_dsb_id = sb_id; 2974 } else { 2975 if (p_igu_info->igu_base_sb == 2976 0xffff) { 2977 p_igu_info->igu_base_sb = sb_id; 2978 } else if (prev_sb_id != sb_id - 1) { 2979 DP_NOTICE(p_hwfn->cdev, 2980 "consecutive igu vectors for HWFN %x broken", 2981 p_hwfn->rel_pf_id); 2982 break; 2983 } 2984 prev_sb_id = sb_id; 2985 /* we don't count the default */ 2986 (p_igu_info->igu_sb_cnt)++; 2987 } 2988 } 2989 } 2990 } 2991 2992 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2993 "IGU igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n", 2994 p_igu_info->igu_base_sb, 2995 p_igu_info->igu_sb_cnt, 2996 p_igu_info->igu_dsb_id); 2997 2998 if (p_igu_info->igu_base_sb == 0xffff || 2999 p_igu_info->igu_dsb_id == 0xffff || 3000 p_igu_info->igu_sb_cnt == 0) { 3001 DP_NOTICE(p_hwfn, 3002 "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n", 3003 p_igu_info->igu_base_sb, 3004 p_igu_info->igu_sb_cnt, 3005 p_igu_info->igu_dsb_id); 3006 return -EINVAL; 3007 } 3008 3009 return 0; 3010 } 3011 3012 /** 3013 * @brief Initialize igu runtime registers 3014 * 3015 * @param p_hwfn 3016 */ 3017 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 3018 { 3019 u32 igu_pf_conf = 0; 3020 3021 igu_pf_conf |= IGU_PF_CONF_FUNC_EN; 3022 3023 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 3024 } 3025 3026 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 3027 { 3028 u64 intr_status = 0; 3029 u32 intr_status_lo = 0; 3030 u32 intr_status_hi = 0; 3031 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 3032 IGU_CMD_INT_ACK_BASE; 3033 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 3034 IGU_CMD_INT_ACK_BASE; 3035 3036 intr_status_lo = REG_RD(p_hwfn, 3037 GTT_BAR0_MAP_REG_IGU_CMD + 3038 lsb_igu_cmd_addr * 8); 3039 intr_status_hi = REG_RD(p_hwfn, 3040 GTT_BAR0_MAP_REG_IGU_CMD + 3041 msb_igu_cmd_addr * 8); 3042 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 3043 3044 return intr_status; 3045 } 3046 3047 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 3048 { 3049 tasklet_init(p_hwfn->sp_dpc, 3050 qed_int_sp_dpc, (unsigned long)p_hwfn); 3051 p_hwfn->b_sp_dpc_enabled = true; 3052 } 3053 3054 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 3055 { 3056 p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 3057 if (!p_hwfn->sp_dpc) 3058 return -ENOMEM; 3059 3060 return 0; 3061 } 3062 3063 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 3064 { 3065 kfree(p_hwfn->sp_dpc); 3066 } 3067 3068 int qed_int_alloc(struct qed_hwfn *p_hwfn, 3069 struct qed_ptt *p_ptt) 3070 { 3071 int rc = 0; 3072 3073 rc = qed_int_sp_dpc_alloc(p_hwfn); 3074 if (rc) { 3075 DP_ERR(p_hwfn->cdev, "Failed to allocate sp dpc mem\n"); 3076 return rc; 3077 } 3078 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 3079 if (rc) { 3080 DP_ERR(p_hwfn->cdev, "Failed to allocate sp sb mem\n"); 3081 return rc; 3082 } 3083 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 3084 if (rc) { 3085 DP_ERR(p_hwfn->cdev, "Failed to allocate sb attn mem\n"); 3086 return rc; 3087 } 3088 return rc; 3089 } 3090 3091 void qed_int_free(struct qed_hwfn *p_hwfn) 3092 { 3093 qed_int_sp_sb_free(p_hwfn); 3094 qed_int_sb_attn_free(p_hwfn); 3095 qed_int_sp_dpc_free(p_hwfn); 3096 } 3097 3098 void qed_int_setup(struct qed_hwfn *p_hwfn, 3099 struct qed_ptt *p_ptt) 3100 { 3101 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 3102 qed_int_sb_attn_setup(p_hwfn, p_ptt); 3103 qed_int_sp_dpc_setup(p_hwfn); 3104 } 3105 3106 void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 3107 struct qed_sb_cnt_info *p_sb_cnt_info) 3108 { 3109 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 3110 3111 if (!info || !p_sb_cnt_info) 3112 return; 3113 3114 p_sb_cnt_info->sb_cnt = info->igu_sb_cnt; 3115 p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov; 3116 p_sb_cnt_info->sb_free_blk = info->free_blks; 3117 } 3118 3119 void qed_int_disable_post_isr_release(struct qed_dev *cdev) 3120 { 3121 int i; 3122 3123 for_each_hwfn(cdev, i) 3124 cdev->hwfns[i].b_int_requested = false; 3125 } 3126