1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/bitops.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 39fe56b9e6SYuval Mintz #include <linux/errno.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/kernel.h> 42fe56b9e6SYuval Mintz #include <linux/pci.h> 43fe56b9e6SYuval Mintz #include <linux/slab.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include "qed.h" 46fe56b9e6SYuval Mintz #include "qed_hsi.h" 47fe56b9e6SYuval Mintz #include "qed_hw.h" 48fe56b9e6SYuval Mintz #include "qed_init_ops.h" 49fe56b9e6SYuval Mintz #include "qed_int.h" 50fe56b9e6SYuval Mintz #include "qed_mcp.h" 51fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 52fe56b9e6SYuval Mintz #include "qed_sp.h" 531408cc1fSYuval Mintz #include "qed_sriov.h" 541408cc1fSYuval Mintz #include "qed_vf.h" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz struct qed_pi_info { 57fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 58fe56b9e6SYuval Mintz void *cookie; 59fe56b9e6SYuval Mintz }; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz struct qed_sb_sp_info { 62fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz /* per protocol index data */ 6521dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 66fe56b9e6SYuval Mintz }; 67fe56b9e6SYuval Mintz 68ff38577aSYuval Mintz enum qed_attention_type { 69ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 70ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 71ff38577aSYuval Mintz }; 72ff38577aSYuval Mintz 73cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75cc875c2eSYuval Mintz 760d956e8aSYuval Mintz struct aeu_invert_reg_bit { 770d956e8aSYuval Mintz char bit_name[30]; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 820d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 830d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 840d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 85a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 860d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 870d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 880d956e8aSYuval Mintz ATTENTION_PARITY) 890d956e8aSYuval Mintz 900d956e8aSYuval Mintz /* Multiple bits start with this offset */ 910d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 920d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 93ba36f718SMintz, Yuval 94ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 95ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 96ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 97ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 98ba36f718SMintz, Yuval 990d956e8aSYuval Mintz unsigned int flags; 100ff38577aSYuval Mintz 101b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 102b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 103b4149dc7SYuval Mintz 104ff38577aSYuval Mintz enum block_id block_index; 1050d956e8aSYuval Mintz }; 1060d956e8aSYuval Mintz 1070d956e8aSYuval Mintz struct aeu_invert_reg { 1080d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 1090d956e8aSYuval Mintz }; 1100d956e8aSYuval Mintz 1110d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 1120d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 1130d956e8aSYuval Mintz 114b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 115b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 116b4149dc7SYuval Mintz { 117b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 118b4149dc7SYuval Mintz 119b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 120b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 121b4149dc7SYuval Mintz tmp); 122b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 123b4149dc7SYuval Mintz 0xffffffff); 124b4149dc7SYuval Mintz 125b4149dc7SYuval Mintz return 0; 126b4149dc7SYuval Mintz } 127b4149dc7SYuval Mintz 128b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 129b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 130b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 131b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 132b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 133b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 134b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 135b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 136b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 137b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 138b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 139b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 140b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 141b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 142b4149dc7SYuval Mintz { 143b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 144b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 145b4149dc7SYuval Mintz 146b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 147b4149dc7SYuval Mintz u32 addr, data, length; 148b4149dc7SYuval Mintz 149b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 150b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 151b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 152b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 153b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 154b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 155b4149dc7SYuval Mintz 156b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 157b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 158b4149dc7SYuval Mintz addr, length, 159b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 160b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 161b4149dc7SYuval Mintz (u8) GET_FIELD(data, 162b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 163b4149dc7SYuval Mintz (u8) GET_FIELD(data, 164b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 165b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 166b4149dc7SYuval Mintz (u8) GET_FIELD(data, 167b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 168b4149dc7SYuval Mintz data); 169b4149dc7SYuval Mintz } 170b4149dc7SYuval Mintz 171b4149dc7SYuval Mintz return 0; 172b4149dc7SYuval Mintz } 173b4149dc7SYuval Mintz 174b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 175b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 176b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 177b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 178b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 179b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 180b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 181b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 182b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 183b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 184b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 185b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 186b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 187b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 188b4149dc7SYuval Mintz { 189b4149dc7SYuval Mintz switch (master) { 190b4149dc7SYuval Mintz case 1: return "PXP"; 191b4149dc7SYuval Mintz case 2: return "MCP"; 192b4149dc7SYuval Mintz case 3: return "MSDM"; 193b4149dc7SYuval Mintz case 4: return "PSDM"; 194b4149dc7SYuval Mintz case 5: return "YSDM"; 195b4149dc7SYuval Mintz case 6: return "USDM"; 196b4149dc7SYuval Mintz case 7: return "TSDM"; 197b4149dc7SYuval Mintz case 8: return "XSDM"; 198b4149dc7SYuval Mintz case 9: return "DBU"; 199b4149dc7SYuval Mintz case 10: return "DMAE"; 200b4149dc7SYuval Mintz default: 2019165dabbSMasanari Iida return "Unknown"; 202b4149dc7SYuval Mintz } 203b4149dc7SYuval Mintz } 204b4149dc7SYuval Mintz 205b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 206b4149dc7SYuval Mintz { 207b4149dc7SYuval Mintz u32 tmp, tmp2; 208b4149dc7SYuval Mintz 209b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 210b4149dc7SYuval Mintz * of interrupts via the validity register 211b4149dc7SYuval Mintz */ 212b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 213b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 214b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 215b4149dc7SYuval Mintz goto out; 216b4149dc7SYuval Mintz 217b4149dc7SYuval Mintz /* Read the GRC timeout information */ 218b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 219b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 220b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 221b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 222b4149dc7SYuval Mintz 223b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 224b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 225b4149dc7SYuval Mintz tmp2, tmp, 226b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 227b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 228b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 229b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 230b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 231fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 232b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 233b4149dc7SYuval Mintz 234b4149dc7SYuval Mintz out: 235b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 236b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 237b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 238b4149dc7SYuval Mintz return 0; 239b4149dc7SYuval Mintz } 240b4149dc7SYuval Mintz 241b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 242b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 243b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 244b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 245b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 246b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 247b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 248b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 249b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 250b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 251b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 252b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 253b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 254b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 255b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 256b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 257b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 258b4149dc7SYuval Mintz static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn) 259b4149dc7SYuval Mintz { 260b4149dc7SYuval Mintz u32 tmp; 261b4149dc7SYuval Mintz 262b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 263b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS2); 264b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 265b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 266b4149dc7SYuval Mintz 267b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 268b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 269b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 270b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 271b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 272b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 273b4149dc7SYuval Mintz 274b4149dc7SYuval Mintz DP_INFO(p_hwfn, 275b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 276b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 277b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 278b4149dc7SYuval Mintz addr_hi, addr_lo, details, 279b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 280b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 281b4149dc7SYuval Mintz GET_FIELD(details, 282b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 283b4149dc7SYuval Mintz tmp, 284b4149dc7SYuval Mintz GET_FIELD(tmp, 285b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 286b4149dc7SYuval Mintz GET_FIELD(tmp, 287b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 288b4149dc7SYuval Mintz GET_FIELD(tmp, 289b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 290b4149dc7SYuval Mintz } 291b4149dc7SYuval Mintz 292b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 293b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS2); 294b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 295b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 296b4149dc7SYuval Mintz 297b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 298b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 299b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 300b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 301b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 302b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 303b4149dc7SYuval Mintz 304b4149dc7SYuval Mintz DP_INFO(p_hwfn, 305b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 306b4149dc7SYuval Mintz " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 307b4149dc7SYuval Mintz " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 308b4149dc7SYuval Mintz addr_hi, addr_lo, details, 309b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 310b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 311b4149dc7SYuval Mintz GET_FIELD(details, 312b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 313b4149dc7SYuval Mintz tmp, 314b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 315b4149dc7SYuval Mintz : 0, 316b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 317b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 318b4149dc7SYuval Mintz : 0); 319b4149dc7SYuval Mintz } 320b4149dc7SYuval Mintz 321b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 322b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 323b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 324bc8282a7SMasanari Iida DP_INFO(p_hwfn, "ICPL error - %08x\n", tmp); 325b4149dc7SYuval Mintz 326b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 327b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 328b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 329b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 330b4149dc7SYuval Mintz 331b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 332b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 333b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 334b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 335b4149dc7SYuval Mintz 336b4149dc7SYuval Mintz DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n", 337b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 338b4149dc7SYuval Mintz } 339b4149dc7SYuval Mintz 340b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 341b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 342b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 343b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 344b4149dc7SYuval Mintz 345b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 346b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 347b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 348b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 349b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 350b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 351b4149dc7SYuval Mintz 352b4149dc7SYuval Mintz DP_INFO(p_hwfn, 353b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 354b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 355b4149dc7SYuval Mintz } 356b4149dc7SYuval Mintz 357b4149dc7SYuval Mintz /* Clear the indications */ 358b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 359b4149dc7SYuval Mintz PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 360b4149dc7SYuval Mintz 361b4149dc7SYuval Mintz return 0; 362b4149dc7SYuval Mintz } 363b4149dc7SYuval Mintz 364b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 365b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 366b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 367b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 368b4149dc7SYuval Mintz static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 369b4149dc7SYuval Mintz { 370b4149dc7SYuval Mintz u32 reason; 371b4149dc7SYuval Mintz 372b4149dc7SYuval Mintz reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) & 373b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 374b4149dc7SYuval Mintz if (reason) { 375b4149dc7SYuval Mintz u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 376b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS); 377b4149dc7SYuval Mintz 378b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 3799165dabbSMasanari Iida "DORQ db_drop: address 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n", 380b4149dc7SYuval Mintz qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 381b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS_ADDRESS), 382b4149dc7SYuval Mintz (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK), 383b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 384b4149dc7SYuval Mintz reason); 385b4149dc7SYuval Mintz } 386b4149dc7SYuval Mintz 387b4149dc7SYuval Mintz return -EINVAL; 388b4149dc7SYuval Mintz } 389b4149dc7SYuval Mintz 390ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 391ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 392ba36f718SMintz, Yuval */ 393ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 394ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 395ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 396ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 397ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 398ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 399ba36f718SMintz, Yuval }; 400ba36f718SMintz, Yuval 401ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 402ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 403ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 404ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 405ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 406ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 407ba36f718SMintz, Yuval }; 408ba36f718SMintz, Yuval 4090d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 4100d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 4110d956e8aSYuval Mintz { 4120d956e8aSYuval Mintz { /* After Invert 1 */ 4130d956e8aSYuval Mintz {"GPIO0 function%d", 414b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 4150d956e8aSYuval Mintz } 4160d956e8aSYuval Mintz }, 4170d956e8aSYuval Mintz 4180d956e8aSYuval Mintz { 4190d956e8aSYuval Mintz { /* After Invert 2 */ 420b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 421b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 422b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 423b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 424b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 425b4149dc7SYuval Mintz qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 426b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 427b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 428b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 429b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 430b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 4310d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 432ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 433b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 4340d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 435b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 4360d956e8aSYuval Mintz } 4370d956e8aSYuval Mintz }, 4380d956e8aSYuval Mintz 4390d956e8aSYuval Mintz { 4400d956e8aSYuval Mintz { /* After Invert 3 */ 4410d956e8aSYuval Mintz {"General Attention %d", 442b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 4430d956e8aSYuval Mintz } 4440d956e8aSYuval Mintz }, 4450d956e8aSYuval Mintz 4460d956e8aSYuval Mintz { 4470d956e8aSYuval Mintz { /* After Invert 4 */ 448ff38577aSYuval Mintz {"General Attention 32", ATTENTION_SINGLE, 449b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 4500d956e8aSYuval Mintz {"General Attention %d", 4510d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 452b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 453ff38577aSYuval Mintz {"General Attention 35", ATTENTION_SINGLE, 454b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 455ba36f718SMintz, Yuval {"NWS Parity", 456ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 457ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 458ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 459ba36f718SMintz, Yuval {"NWS Interrupt", 460ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 461ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 462ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 463ba36f718SMintz, Yuval {"NWM Parity", 464ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 465ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 466ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 467ba36f718SMintz, Yuval {"NWM Interrupt", 468ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 469ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 470ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 471b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 472b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 473b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 474b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 475b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 476ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 477b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 478b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 479b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 480b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 481ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 482b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 483b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 484b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 485b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 486b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 487b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 4880d956e8aSYuval Mintz } 4890d956e8aSYuval Mintz }, 4900d956e8aSYuval Mintz 4910d956e8aSYuval Mintz { 4920d956e8aSYuval Mintz { /* After Invert 5 */ 493b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 494b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 495b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 496b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 497b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 498b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 499b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 500b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 501b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 502b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 503b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 504b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 505b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 506b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 507b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 508b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 5090d956e8aSYuval Mintz } 5100d956e8aSYuval Mintz }, 5110d956e8aSYuval Mintz 5120d956e8aSYuval Mintz { 5130d956e8aSYuval Mintz { /* After Invert 6 */ 514b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 515b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 516b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 517b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 518b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 519b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 520b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 521b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 522b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 523b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 524b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 525b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 526b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 527b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 528b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 529b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 530b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 5310d956e8aSYuval Mintz } 5320d956e8aSYuval Mintz }, 5330d956e8aSYuval Mintz 5340d956e8aSYuval Mintz { 5350d956e8aSYuval Mintz { /* After Invert 7 */ 536b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 537b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 538b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 539b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 540b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 541b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 542b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 543b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 544b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 545b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 546b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 547b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 548b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 549b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 550b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 551b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 552b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 5530d956e8aSYuval Mintz } 5540d956e8aSYuval Mintz }, 5550d956e8aSYuval Mintz 5560d956e8aSYuval Mintz { 5570d956e8aSYuval Mintz { /* After Invert 8 */ 558b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 559b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 560b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 561b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 562b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 563b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 564b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 565b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 566b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 567b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 568b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 569b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 570b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 571b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 572b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 573b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 574b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 575b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 576b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 577b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 578b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 579b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 580b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 581ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 582b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 583b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 584b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 585ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 586b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 587ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 588b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5890d956e8aSYuval Mintz } 5900d956e8aSYuval Mintz }, 5910d956e8aSYuval Mintz 5920d956e8aSYuval Mintz { 5930d956e8aSYuval Mintz { /* After Invert 9 */ 594b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 595b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 596ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 597b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 598b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 599b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 600ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 601b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 602ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 603b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 6040d956e8aSYuval Mintz } 6050d956e8aSYuval Mintz }, 6060d956e8aSYuval Mintz }; 6070d956e8aSYuval Mintz 608ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 609ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 610ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 611ba36f718SMintz, Yuval { 612ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 613ba36f718SMintz, Yuval return p_bit; 614ba36f718SMintz, Yuval 615ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 616ba36f718SMintz, Yuval return p_bit; 617ba36f718SMintz, Yuval 618ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 619ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 620ba36f718SMintz, Yuval } 621ba36f718SMintz, Yuval 622ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 623ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 624ba36f718SMintz, Yuval { 625ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 626ba36f718SMintz, Yuval ATTENTION_PARITY); 627ba36f718SMintz, Yuval } 628ba36f718SMintz, Yuval 629cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 630cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 631cc875c2eSYuval Mintz struct qed_sb_attn_info { 632cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 633cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 634cc875c2eSYuval Mintz dma_addr_t sb_phys; 635cc875c2eSYuval Mintz 636cc875c2eSYuval Mintz /* Last seen running index */ 637cc875c2eSYuval Mintz u16 index; 638cc875c2eSYuval Mintz 6390d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 6400d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 6410d956e8aSYuval Mintz 6420d956e8aSYuval Mintz /* A pointer to the attention description structure */ 6430d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 6440d956e8aSYuval Mintz 645cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 646cc875c2eSYuval Mintz u16 known_attn; 647cc875c2eSYuval Mintz 648cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 649cc875c2eSYuval Mintz u32 mfw_attn_addr; 650cc875c2eSYuval Mintz }; 651cc875c2eSYuval Mintz 652cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 653cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 654cc875c2eSYuval Mintz { 6551a635e48SYuval Mintz u16 rc = 0, index; 656cc875c2eSYuval Mintz 657cc875c2eSYuval Mintz /* Make certain HW write took affect */ 658cc875c2eSYuval Mintz mmiowb(); 659cc875c2eSYuval Mintz 660cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 661cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 662cc875c2eSYuval Mintz p_sb_desc->index = index; 663cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 664cc875c2eSYuval Mintz } 665cc875c2eSYuval Mintz 666cc875c2eSYuval Mintz /* Make certain we got a consistent view with HW */ 667cc875c2eSYuval Mintz mmiowb(); 668cc875c2eSYuval Mintz 669cc875c2eSYuval Mintz return rc; 670cc875c2eSYuval Mintz } 671cc875c2eSYuval Mintz 672cc875c2eSYuval Mintz /** 673cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 674cc875c2eSYuval Mintz * 675cc875c2eSYuval Mintz * @param p_hwfn 676cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 677cc875c2eSYuval Mintz * @return int 678cc875c2eSYuval Mintz */ 6791a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 680cc875c2eSYuval Mintz { 681cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 682cc875c2eSYuval Mintz u32 igu_mask; 683cc875c2eSYuval Mintz 684cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 6851a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 686cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 687cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 688cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 689cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 690cc875c2eSYuval Mintz 691cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 692cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 693cc875c2eSYuval Mintz sb_attn_sw->known_attn, 694cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 695cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 696cc875c2eSYuval Mintz 697cc875c2eSYuval Mintz /* Handle MCP events */ 698cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 699cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 700cc875c2eSYuval Mintz /* Clean the MCP attention */ 701cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 702cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 703cc875c2eSYuval Mintz } 704cc875c2eSYuval Mintz 705cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 706cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 707cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 708cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 709cc875c2eSYuval Mintz (u32)asserted_bits); 710cc875c2eSYuval Mintz 711cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 712cc875c2eSYuval Mintz asserted_bits); 713cc875c2eSYuval Mintz 714cc875c2eSYuval Mintz return 0; 715cc875c2eSYuval Mintz } 716cc875c2eSYuval Mintz 7170ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 7180ebbd1c8SMintz, Yuval enum block_id id, 7190ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 720ff38577aSYuval Mintz { 7210ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 7220ebbd1c8SMintz, Yuval enum dbg_status status; 723ff38577aSYuval Mintz 7240ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 725ff38577aSYuval Mintz 7260ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 7270ebbd1c8SMintz, Yuval b_clear, &attn_results); 7280ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 729ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 7300ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 7310ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 7320ebbd1c8SMintz, Yuval else 7330ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 734ff38577aSYuval Mintz } 735ff38577aSYuval Mintz 736cc875c2eSYuval Mintz /** 7370d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 7380d956e8aSYuval Mintz * cause of the attention 7390d956e8aSYuval Mintz * 7400d956e8aSYuval Mintz * @param p_hwfn 7410d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 7420d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 7430d956e8aSYuval Mintz * this bit to this group. 7440d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 7450d956e8aSYuval Mintz * 7460d956e8aSYuval Mintz * @return int 7470d956e8aSYuval Mintz */ 7480d956e8aSYuval Mintz static int 7490d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 7500d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 7510d956e8aSYuval Mintz u32 aeu_en_reg, 7526010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 7530d956e8aSYuval Mintz { 7540ebbd1c8SMintz, Yuval bool b_fatal = false; 7550d956e8aSYuval Mintz int rc = -EINVAL; 756b4149dc7SYuval Mintz u32 val; 7570d956e8aSYuval Mintz 7580d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 7596010179dSMintz, Yuval p_bit_name, bitmask); 7600d956e8aSYuval Mintz 761b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 762b4149dc7SYuval Mintz if (p_aeu->cb) { 763b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 7646010179dSMintz, Yuval p_bit_name); 765b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 766b4149dc7SYuval Mintz } 767b4149dc7SYuval Mintz 7680ebbd1c8SMintz, Yuval if (rc) 7690ebbd1c8SMintz, Yuval b_fatal = true; 770ff38577aSYuval Mintz 7710ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 7720ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 7730ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 7740ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 775ff38577aSYuval Mintz 776ff38577aSYuval Mintz 777b4149dc7SYuval Mintz /* If the attention is benign, no need to prevent it */ 778b4149dc7SYuval Mintz if (!rc) 779b4149dc7SYuval Mintz goto out; 780b4149dc7SYuval Mintz 7810d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 7820d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 783b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 7840d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 7856010179dSMintz, Yuval p_bit_name); 7860d956e8aSYuval Mintz 787b4149dc7SYuval Mintz out: 7880d956e8aSYuval Mintz return rc; 7890d956e8aSYuval Mintz } 7900d956e8aSYuval Mintz 791ff38577aSYuval Mintz /** 792ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 793ff38577aSYuval Mintz * 794ff38577aSYuval Mintz * @param p_hwfn 795ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 7969790c35eSMintz, Yuval * @param aeu_en_reg - address of the AEU enable register 797ff38577aSYuval Mintz * @param bit_index 798ff38577aSYuval Mintz */ 799ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 800ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 8019790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 802ff38577aSYuval Mintz { 8039790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 804ff38577aSYuval Mintz 8059790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 8069790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 8079790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 808ff38577aSYuval Mintz 809ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 8100ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 811ff38577aSYuval Mintz 812ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 813ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 8140ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 8150ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 8160ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 8170ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 818ff38577aSYuval Mintz } 819ff38577aSYuval Mintz } 8209790c35eSMintz, Yuval 8219790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 8229790c35eSMintz, Yuval mask = ~BIT(bit_index); 8239790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 8249790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 8259790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 8269790c35eSMintz, Yuval p_aeu->bit_name); 827ff38577aSYuval Mintz } 828ff38577aSYuval Mintz 8290d956e8aSYuval Mintz /** 830cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 831cc875c2eSYuval Mintz * 832cc875c2eSYuval Mintz * @param p_hwfn 833cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 834cc875c2eSYuval Mintz * @return int 835cc875c2eSYuval Mintz * 836cc875c2eSYuval Mintz */ 837cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 838cc875c2eSYuval Mintz u16 deasserted_bits) 839cc875c2eSYuval Mintz { 840cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 8419790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 8420d956e8aSYuval Mintz u8 i, j, k, bit_idx; 8430d956e8aSYuval Mintz int rc = 0; 844cc875c2eSYuval Mintz 8450d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 8460d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 8470d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 8480d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 8490d956e8aSYuval Mintz i * 0x4); 8500d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 8510d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 8520d956e8aSYuval Mintz i, aeu_inv_arr[i]); 8530d956e8aSYuval Mintz } 8540d956e8aSYuval Mintz 8550d956e8aSYuval Mintz /* Find parity attentions first */ 8560d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 8570d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 8580d956e8aSYuval Mintz u32 parities; 8590d956e8aSYuval Mintz 8609790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 8619790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 8629790c35eSMintz, Yuval 8630d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 8640d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 8650d956e8aSYuval Mintz if (!parities) 8660d956e8aSYuval Mintz continue; 8670d956e8aSYuval Mintz 8680d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 8690d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 8700d956e8aSYuval Mintz 871ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 8721a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 873ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 8749790c35eSMintz, Yuval aeu_en, bit_idx); 8750d956e8aSYuval Mintz 8760d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 8770d956e8aSYuval Mintz } 8780d956e8aSYuval Mintz } 8790d956e8aSYuval Mintz 8800d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 8810d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 8820d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 8830d956e8aSYuval Mintz 8840d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 8850d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 8860d956e8aSYuval Mintz continue; 8870d956e8aSYuval Mintz 8880d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 8899790c35eSMintz, Yuval u32 bits; 8909790c35eSMintz, Yuval 8919790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 8920d956e8aSYuval Mintz i * sizeof(u32) + 8930d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 8940d956e8aSYuval Mintz 8950d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 8960d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 8970d956e8aSYuval Mintz 8980d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 8990d956e8aSYuval Mintz if (!bits) 9000d956e8aSYuval Mintz continue; 9010d956e8aSYuval Mintz 9020d956e8aSYuval Mintz /* Find all set bits from current register which belong 9030d956e8aSYuval Mintz * to current group, making them responsible for the 9040d956e8aSYuval Mintz * previous assertion. 9050d956e8aSYuval Mintz */ 9060d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 9076010179dSMintz, Yuval long unsigned int bitmask; 9080d956e8aSYuval Mintz u8 bit, bit_len; 9090d956e8aSYuval Mintz 9100d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 911ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 9120d956e8aSYuval Mintz 9130d956e8aSYuval Mintz bit = bit_idx; 9140d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 915ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 9160d956e8aSYuval Mintz /* Skip Parity */ 9170d956e8aSYuval Mintz bit++; 9180d956e8aSYuval Mintz bit_len--; 9190d956e8aSYuval Mintz } 9200d956e8aSYuval Mintz 9210d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 9226010179dSMintz, Yuval bitmask >>= bit; 9236010179dSMintz, Yuval 9240d956e8aSYuval Mintz if (bitmask) { 9256010179dSMintz, Yuval u32 flags = p_aeu->flags; 9266010179dSMintz, Yuval char bit_name[30]; 9276010179dSMintz, Yuval u8 num; 9286010179dSMintz, Yuval 9296010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 9306010179dSMintz, Yuval bit_len); 9316010179dSMintz, Yuval 9326010179dSMintz, Yuval /* Some bits represent more than a 9336010179dSMintz, Yuval * a single interrupt. Correctly print 9346010179dSMintz, Yuval * their name. 9356010179dSMintz, Yuval */ 9366010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 9376010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 9386010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 9396010179dSMintz, Yuval snprintf(bit_name, 30, 9406010179dSMintz, Yuval p_aeu->bit_name, num); 9416010179dSMintz, Yuval else 9426010179dSMintz, Yuval strncpy(bit_name, 9436010179dSMintz, Yuval p_aeu->bit_name, 30); 9446010179dSMintz, Yuval 9456010179dSMintz, Yuval /* We now need to pass bitmask in its 9466010179dSMintz, Yuval * correct position. 9476010179dSMintz, Yuval */ 9486010179dSMintz, Yuval bitmask <<= bit; 9496010179dSMintz, Yuval 9500d956e8aSYuval Mintz /* Handle source of the attention */ 9510d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 9520d956e8aSYuval Mintz p_aeu, 9530d956e8aSYuval Mintz aeu_en, 9546010179dSMintz, Yuval bit_name, 9550d956e8aSYuval Mintz bitmask); 9560d956e8aSYuval Mintz } 9570d956e8aSYuval Mintz 9580d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 9590d956e8aSYuval Mintz } 9600d956e8aSYuval Mintz } 9610d956e8aSYuval Mintz } 962cc875c2eSYuval Mintz 963cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 964cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 965cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 966cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 967cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 968cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 969cc875c2eSYuval Mintz 970cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 9711a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 972cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 973cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 974cc875c2eSYuval Mintz 975cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 976cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 977cc875c2eSYuval Mintz 9780d956e8aSYuval Mintz return rc; 979cc875c2eSYuval Mintz } 980cc875c2eSYuval Mintz 981cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 982cc875c2eSYuval Mintz { 983cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 984cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 985cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 986cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 987cc875c2eSYuval Mintz __le16 index; 988cc875c2eSYuval Mintz int rc = 0; 989cc875c2eSYuval Mintz 990cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 991cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 992cc875c2eSYuval Mintz */ 993cc875c2eSYuval Mintz do { 994cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 995ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 996ed4eac20SDenis Bolotin dma_rmb(); 997cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 998cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 999cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1000cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1001cc875c2eSYuval Mintz 1002cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1003cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1004cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1005cc875c2eSYuval Mintz * attention with no previous attention 1006cc875c2eSYuval Mintz */ 1007cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1008cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1009cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1010cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1011cc875c2eSYuval Mintz 1012cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1013cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1014cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1015cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1016cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1017cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 10181a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 1019cc875c2eSYuval Mintz } else { 1020cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1021cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1022cc875c2eSYuval Mintz } 1023cc875c2eSYuval Mintz 1024cc875c2eSYuval Mintz if (asserted_bits) { 1025cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1026cc875c2eSYuval Mintz if (rc) 1027cc875c2eSYuval Mintz return rc; 1028cc875c2eSYuval Mintz } 1029cc875c2eSYuval Mintz 10301a635e48SYuval Mintz if (deasserted_bits) 1031cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1032cc875c2eSYuval Mintz 1033cc875c2eSYuval Mintz return rc; 1034cc875c2eSYuval Mintz } 1035cc875c2eSYuval Mintz 1036cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 10371a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1038cc875c2eSYuval Mintz { 1039cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1040cc875c2eSYuval Mintz 1041cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 1042cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1043cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1044cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1045cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1046cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1047cc875c2eSYuval Mintz 1048cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1049cc875c2eSYuval Mintz 1050cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1051cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1052cc875c2eSYuval Mintz */ 1053cc875c2eSYuval Mintz mmiowb(); 1054cc875c2eSYuval Mintz barrier(); 1055cc875c2eSYuval Mintz } 1056cc875c2eSYuval Mintz 1057fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 1058fe56b9e6SYuval Mintz { 1059fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1060fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1061cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1062fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1063fe56b9e6SYuval Mintz int arr_size; 1064fe56b9e6SYuval Mintz u16 rc = 0; 1065fe56b9e6SYuval Mintz 1066fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1067fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1068fe56b9e6SYuval Mintz return; 1069fe56b9e6SYuval Mintz } 1070fe56b9e6SYuval Mintz 1071fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1072fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1073fe56b9e6SYuval Mintz if (!sb_info) { 1074fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1075fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1076fe56b9e6SYuval Mintz return; 1077fe56b9e6SYuval Mintz } 1078fe56b9e6SYuval Mintz 1079cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1080cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1081cc875c2eSYuval Mintz return; 1082cc875c2eSYuval Mintz } 1083cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1084cc875c2eSYuval Mintz 1085fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1086fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1087fe56b9e6SYuval Mintz 1088fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1089fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1090fe56b9e6SYuval Mintz */ 1091fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1092fe56b9e6SYuval Mintz 1093fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1094fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 10951a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1096fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1097fe56b9e6SYuval Mintz } else { 1098fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1099fe56b9e6SYuval Mintz 1100fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1101fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1102fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1103fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1104fe56b9e6SYuval Mintz } 1105fe56b9e6SYuval Mintz 1106cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 11071a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1108cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1109cc875c2eSYuval Mintz } else { 1110cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1111cc875c2eSYuval Mintz 1112cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1113cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1114cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1115cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1116cc875c2eSYuval Mintz } 1117cc875c2eSYuval Mintz 1118fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1119fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1120fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1121fe56b9e6SYuval Mintz return; 1122fe56b9e6SYuval Mintz } 1123fe56b9e6SYuval Mintz 1124fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1125fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1126fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1127fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1128fe56b9e6SYuval Mintz return; 1129fe56b9e6SYuval Mintz } 1130fe56b9e6SYuval Mintz 1131cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1132cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1133cc875c2eSYuval Mintz 1134fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1135fe56b9e6SYuval Mintz int pi; 1136fe56b9e6SYuval Mintz 1137fe56b9e6SYuval Mintz /* Look for a free index */ 1138fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1139fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1140fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1141fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1142fe56b9e6SYuval Mintz } 1143fe56b9e6SYuval Mintz } 1144fe56b9e6SYuval Mintz 1145cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1146cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1147cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1148cc875c2eSYuval Mintz */ 1149cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1150cc875c2eSYuval Mintz 1151fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1152fe56b9e6SYuval Mintz } 1153fe56b9e6SYuval Mintz 1154cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1155cc875c2eSYuval Mintz { 1156cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1157cc875c2eSYuval Mintz 11584ac801b7SYuval Mintz if (!p_sb) 11594ac801b7SYuval Mintz return; 11604ac801b7SYuval Mintz 1161cc875c2eSYuval Mintz if (p_sb->sb_attn) 11624ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1163cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 11641a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1165cc875c2eSYuval Mintz kfree(p_sb); 11663587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1167cc875c2eSYuval Mintz } 1168cc875c2eSYuval Mintz 1169cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1170cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1171cc875c2eSYuval Mintz { 1172cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1173cc875c2eSYuval Mintz 1174cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1175cc875c2eSYuval Mintz 1176cc875c2eSYuval Mintz sb_info->index = 0; 1177cc875c2eSYuval Mintz sb_info->known_attn = 0; 1178cc875c2eSYuval Mintz 1179cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1180cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1181cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1182cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1183cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1184cc875c2eSYuval Mintz } 1185cc875c2eSYuval Mintz 1186cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1187cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 11881a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1189cc875c2eSYuval Mintz { 1190cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 11910d956e8aSYuval Mintz int i, j, k; 1192cc875c2eSYuval Mintz 1193cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1194cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1195cc875c2eSYuval Mintz 11960d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 11970d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 11980d956e8aSYuval Mintz 11990d956e8aSYuval Mintz /* Calculate Parity Masks */ 12000d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 12010d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 12020d956e8aSYuval Mintz /* j is array index, k is bit index */ 12030d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1204ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 12050d956e8aSYuval Mintz 1206ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1207ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 12080d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 12090d956e8aSYuval Mintz 1210ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 12110d956e8aSYuval Mintz } 12120d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 12130d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 12140d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 12150d956e8aSYuval Mintz } 12160d956e8aSYuval Mintz 1217cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1218cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1219cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1220cc875c2eSYuval Mintz 1221cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1222cc875c2eSYuval Mintz } 1223cc875c2eSYuval Mintz 1224cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1225cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1226cc875c2eSYuval Mintz { 1227cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1228cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1229cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 12301a635e48SYuval Mintz void *p_virt; 1231cc875c2eSYuval Mintz 1232cc875c2eSYuval Mintz /* SB struct */ 123360fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 12342591c280SJoe Perches if (!p_sb) 1235cc875c2eSYuval Mintz return -ENOMEM; 1236cc875c2eSYuval Mintz 1237cc875c2eSYuval Mintz /* SB ring */ 1238cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1239cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1240cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1241cc875c2eSYuval Mintz 1242cc875c2eSYuval Mintz if (!p_virt) { 1243cc875c2eSYuval Mintz kfree(p_sb); 1244cc875c2eSYuval Mintz return -ENOMEM; 1245cc875c2eSYuval Mintz } 1246cc875c2eSYuval Mintz 1247cc875c2eSYuval Mintz /* Attention setup */ 1248cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1249cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1250cc875c2eSYuval Mintz 1251cc875c2eSYuval Mintz return 0; 1252cc875c2eSYuval Mintz } 1253cc875c2eSYuval Mintz 1254fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1255fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1256fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1257fe56b9e6SYuval Mintz 1258fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1259fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 12601a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1261fe56b9e6SYuval Mintz { 12624ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1263fe56b9e6SYuval Mintz u32 cau_state; 1264722003acSSudarsana Reddy Kalluru u8 timer_res; 1265fe56b9e6SYuval Mintz 1266fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1267fe56b9e6SYuval Mintz 1268fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1269fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1270fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1271fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1272fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1273fe56b9e6SYuval Mintz 1274fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1275fe56b9e6SYuval Mintz 12764ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1277fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 12784ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 12794ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 12804ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 12814ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1282fe56b9e6SYuval Mintz } 1283fe56b9e6SYuval Mintz 1284722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1285722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1286722003acSSudarsana Reddy Kalluru timer_res = 0; 1287722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1288722003acSSudarsana Reddy Kalluru timer_res = 1; 1289722003acSSudarsana Reddy Kalluru else 1290722003acSSudarsana Reddy Kalluru timer_res = 2; 1291722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1292722003acSSudarsana Reddy Kalluru 1293722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1294722003acSSudarsana Reddy Kalluru timer_res = 0; 1295722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1296722003acSSudarsana Reddy Kalluru timer_res = 1; 1297722003acSSudarsana Reddy Kalluru else 1298722003acSSudarsana Reddy Kalluru timer_res = 2; 1299722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1300722003acSSudarsana Reddy Kalluru 1301fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1302fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1303fe56b9e6SYuval Mintz } 1304fe56b9e6SYuval Mintz 13058befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 13068befd73cSMintz, Yuval struct qed_ptt *p_ptt, 13078befd73cSMintz, Yuval u16 igu_sb_id, 13088befd73cSMintz, Yuval u32 pi_index, 13098befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 13108befd73cSMintz, Yuval u8 timeset) 13118befd73cSMintz, Yuval { 13128befd73cSMintz, Yuval struct cau_pi_entry pi_entry; 13138befd73cSMintz, Yuval u32 sb_offset, pi_offset; 13148befd73cSMintz, Yuval 13158befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 13168befd73cSMintz, Yuval return; 13178befd73cSMintz, Yuval 131821dd79e8STomer Tayar sb_offset = igu_sb_id * PIS_PER_SB_E4; 13198befd73cSMintz, Yuval memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 13208befd73cSMintz, Yuval 13218befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 13228befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 13238befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 13248befd73cSMintz, Yuval else 13258befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 13268befd73cSMintz, Yuval 13278befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 13288befd73cSMintz, Yuval if (p_hwfn->hw_init_done) { 13298befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 13308befd73cSMintz, Yuval CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 13318befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 13328befd73cSMintz, Yuval } else { 13338befd73cSMintz, Yuval STORE_RT_REG(p_hwfn, 13348befd73cSMintz, Yuval CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 13358befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 13368befd73cSMintz, Yuval } 13378befd73cSMintz, Yuval } 13388befd73cSMintz, Yuval 1339fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1340fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1341fe56b9e6SYuval Mintz dma_addr_t sb_phys, 13421a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1343fe56b9e6SYuval Mintz { 1344fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1345fe56b9e6SYuval Mintz 1346fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1347fe56b9e6SYuval Mintz vf_number, vf_valid); 1348fe56b9e6SYuval Mintz 1349fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 13500a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 13510a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1352fe56b9e6SYuval Mintz 13530a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 13540a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 13550a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 13560a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 13570a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 13580a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 1359fe56b9e6SYuval Mintz } else { 1360fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1361fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1362fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1363fe56b9e6SYuval Mintz igu_sb_id * 2, 1364fe56b9e6SYuval Mintz sb_phys); 1365fe56b9e6SYuval Mintz 1366fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1367fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1368fe56b9e6SYuval Mintz igu_sb_id * 2, 1369fe56b9e6SYuval Mintz sb_entry); 1370fe56b9e6SYuval Mintz } 1371fe56b9e6SYuval Mintz 1372fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1373fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1374b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1375722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1376b5a9ee7cSAriel Elior u8 i; 1377fe56b9e6SYuval Mintz 1378722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1379722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1380722003acSSudarsana Reddy Kalluru timer_res = 0; 1381722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1382722003acSSudarsana Reddy Kalluru timer_res = 1; 1383722003acSSudarsana Reddy Kalluru else 1384722003acSSudarsana Reddy Kalluru timer_res = 2; 1385722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1386fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 13871a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1388fe56b9e6SYuval Mintz 1389722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1390722003acSSudarsana Reddy Kalluru timer_res = 0; 1391722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1392722003acSSudarsana Reddy Kalluru timer_res = 1; 1393722003acSSudarsana Reddy Kalluru else 1394722003acSSudarsana Reddy Kalluru timer_res = 2; 1395722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1396fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1397fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1398fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1399fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1400fe56b9e6SYuval Mintz timeset); 1401fe56b9e6SYuval Mintz } 1402fe56b9e6SYuval Mintz } 1403fe56b9e6SYuval Mintz } 1404fe56b9e6SYuval Mintz 1405fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 14061a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1407fe56b9e6SYuval Mintz { 1408fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1409fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1410fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1411fe56b9e6SYuval Mintz 14121408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1413fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1414fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1415fe56b9e6SYuval Mintz } 1416fe56b9e6SYuval Mintz 141709b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 141809b6b147SMintz, Yuval { 141909b6b147SMintz, Yuval struct qed_igu_block *p_block; 142009b6b147SMintz, Yuval u16 igu_id; 142109b6b147SMintz, Yuval 142209b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 142309b6b147SMintz, Yuval igu_id++) { 142409b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 142509b6b147SMintz, Yuval 142609b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 142709b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 142809b6b147SMintz, Yuval continue; 142909b6b147SMintz, Yuval 143009b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 143109b6b147SMintz, Yuval return p_block; 143209b6b147SMintz, Yuval } 143309b6b147SMintz, Yuval 143409b6b147SMintz, Yuval return NULL; 143509b6b147SMintz, Yuval } 143609b6b147SMintz, Yuval 1437a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1438a333f7f3SMintz, Yuval { 1439a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1440a333f7f3SMintz, Yuval u16 igu_id; 1441a333f7f3SMintz, Yuval 1442a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1443a333f7f3SMintz, Yuval igu_id++) { 1444a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1445a333f7f3SMintz, Yuval 1446a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1447a333f7f3SMintz, Yuval !p_block->is_pf || 1448a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1449a333f7f3SMintz, Yuval continue; 1450a333f7f3SMintz, Yuval 1451a333f7f3SMintz, Yuval return igu_id; 1452a333f7f3SMintz, Yuval } 1453a333f7f3SMintz, Yuval 1454a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1455a333f7f3SMintz, Yuval } 1456a333f7f3SMintz, Yuval 145750a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1458fe56b9e6SYuval Mintz { 1459fe56b9e6SYuval Mintz u16 igu_sb_id; 1460fe56b9e6SYuval Mintz 1461fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1462fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1463fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 14641408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1465a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 14661408cc1fSYuval Mintz else 14671408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1468fe56b9e6SYuval Mintz 1469525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1470525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1471525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1472525ef5c0SYuval Mintz else 1473525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1474525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1475fe56b9e6SYuval Mintz 1476fe56b9e6SYuval Mintz return igu_sb_id; 1477fe56b9e6SYuval Mintz } 1478fe56b9e6SYuval Mintz 1479fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1480fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1481fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 14821a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1483fe56b9e6SYuval Mintz { 1484fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1485fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1486fe56b9e6SYuval Mintz 1487fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1488fe56b9e6SYuval Mintz 1489fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 149050a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 149150a20714SMintz, Yuval struct qed_igu_info *p_info; 149250a20714SMintz, Yuval struct qed_igu_block *p_block; 149350a20714SMintz, Yuval 149450a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 149550a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 149650a20714SMintz, Yuval 149750a20714SMintz, Yuval p_block->sb_info = sb_info; 149850a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 149950a20714SMintz, Yuval p_info->usage.free_cnt--; 150050a20714SMintz, Yuval } else { 150150a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 150250a20714SMintz, Yuval } 1503fe56b9e6SYuval Mintz } 1504fe56b9e6SYuval Mintz 1505fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1506fe56b9e6SYuval Mintz 1507fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1508fe56b9e6SYuval Mintz * written to for a specific status block 1509fe56b9e6SYuval Mintz */ 15101408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1511fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1512fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1513fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 15141408cc1fSYuval Mintz } else { 15151408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 15161408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 15171408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 15181408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 15191408cc1fSYuval Mintz } 1520fe56b9e6SYuval Mintz 1521fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1522fe56b9e6SYuval Mintz 1523fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1524fe56b9e6SYuval Mintz 1525fe56b9e6SYuval Mintz return 0; 1526fe56b9e6SYuval Mintz } 1527fe56b9e6SYuval Mintz 1528fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 15291a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1530fe56b9e6SYuval Mintz { 153150a20714SMintz, Yuval struct qed_igu_block *p_block; 153250a20714SMintz, Yuval struct qed_igu_info *p_info; 153350a20714SMintz, Yuval 153450a20714SMintz, Yuval if (!sb_info) 153550a20714SMintz, Yuval return 0; 1536fe56b9e6SYuval Mintz 1537fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1538fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1539fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1540fe56b9e6SYuval Mintz 154150a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 154250a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 154350a20714SMintz, Yuval return 0; 15444ac801b7SYuval Mintz } 1545fe56b9e6SYuval Mintz 154650a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 154750a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 154850a20714SMintz, Yuval 154950a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 155050a20714SMintz, Yuval if (!p_block->vector_number) { 155150a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 155250a20714SMintz, Yuval return -EINVAL; 155350a20714SMintz, Yuval } 155450a20714SMintz, Yuval 155550a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 155650a20714SMintz, Yuval p_block->sb_info = NULL; 155750a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 155850a20714SMintz, Yuval p_info->usage.free_cnt++; 155950a20714SMintz, Yuval 1560fe56b9e6SYuval Mintz return 0; 1561fe56b9e6SYuval Mintz } 1562fe56b9e6SYuval Mintz 1563fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1564fe56b9e6SYuval Mintz { 1565fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1566fe56b9e6SYuval Mintz 15674ac801b7SYuval Mintz if (!p_sb) 15684ac801b7SYuval Mintz return; 15694ac801b7SYuval Mintz 1570fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1571fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1572fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1573fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1574fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1575fe56b9e6SYuval Mintz kfree(p_sb); 15763587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1577fe56b9e6SYuval Mintz } 1578fe56b9e6SYuval Mintz 15791a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1580fe56b9e6SYuval Mintz { 1581fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1582fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1583fe56b9e6SYuval Mintz void *p_virt; 1584fe56b9e6SYuval Mintz 1585fe56b9e6SYuval Mintz /* SB struct */ 158660fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 15872591c280SJoe Perches if (!p_sb) 1588fe56b9e6SYuval Mintz return -ENOMEM; 1589fe56b9e6SYuval Mintz 1590fe56b9e6SYuval Mintz /* SB ring */ 1591fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1592fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1593fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1594fe56b9e6SYuval Mintz if (!p_virt) { 1595fe56b9e6SYuval Mintz kfree(p_sb); 1596fe56b9e6SYuval Mintz return -ENOMEM; 1597fe56b9e6SYuval Mintz } 1598fe56b9e6SYuval Mintz 1599fe56b9e6SYuval Mintz /* Status Block setup */ 1600fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1601fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1602fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1603fe56b9e6SYuval Mintz 1604fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1605fe56b9e6SYuval Mintz 1606fe56b9e6SYuval Mintz return 0; 1607fe56b9e6SYuval Mintz } 1608fe56b9e6SYuval Mintz 1609fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1610fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 16111a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1612fe56b9e6SYuval Mintz { 1613fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 16144ac801b7SYuval Mintz int rc = -ENOMEM; 1615fe56b9e6SYuval Mintz u8 pi; 1616fe56b9e6SYuval Mintz 1617fe56b9e6SYuval Mintz /* Look for a free index */ 1618fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 16194ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 16204ac801b7SYuval Mintz continue; 16214ac801b7SYuval Mintz 1622fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1623fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1624fe56b9e6SYuval Mintz *sb_idx = pi; 1625fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 16264ac801b7SYuval Mintz rc = 0; 1627fe56b9e6SYuval Mintz break; 1628fe56b9e6SYuval Mintz } 1629fe56b9e6SYuval Mintz 16304ac801b7SYuval Mintz return rc; 1631fe56b9e6SYuval Mintz } 1632fe56b9e6SYuval Mintz 1633fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1634fe56b9e6SYuval Mintz { 1635fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1636fe56b9e6SYuval Mintz 16374ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 16384ac801b7SYuval Mintz return -ENOMEM; 16394ac801b7SYuval Mintz 1640fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1641fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1642fe56b9e6SYuval Mintz 16434ac801b7SYuval Mintz return 0; 1644fe56b9e6SYuval Mintz } 1645fe56b9e6SYuval Mintz 1646fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1647fe56b9e6SYuval Mintz { 1648fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1649fe56b9e6SYuval Mintz } 1650fe56b9e6SYuval Mintz 1651fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 16521a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1653fe56b9e6SYuval Mintz { 1654cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1655fe56b9e6SYuval Mintz 1656fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1657fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1658fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1659fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1660fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1661fe56b9e6SYuval Mintz break; 1662fe56b9e6SYuval Mintz 1663fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1664fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1665fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1666fe56b9e6SYuval Mintz break; 1667fe56b9e6SYuval Mintz 1668fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1669fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1670fe56b9e6SYuval Mintz break; 1671fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1672fe56b9e6SYuval Mintz break; 1673fe56b9e6SYuval Mintz } 1674fe56b9e6SYuval Mintz 1675fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1676fe56b9e6SYuval Mintz } 1677fe56b9e6SYuval Mintz 1678979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1679979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1680fe56b9e6SYuval Mintz { 1681fe56b9e6SYuval Mintz 16820d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 16830d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1684cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1685cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 16860d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1687cc875c2eSYuval Mintz 1688fe56b9e6SYuval Mintz /* Flush the writes to IGU */ 1689fe56b9e6SYuval Mintz mmiowb(); 1690cc875c2eSYuval Mintz 1691cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1692cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1693979cead3SMintz, Yuval } 1694979cead3SMintz, Yuval 1695979cead3SMintz, Yuval int 1696979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1697979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1698979cead3SMintz, Yuval { 1699979cead3SMintz, Yuval int rc = 0; 1700979cead3SMintz, Yuval 1701979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1702979cead3SMintz, Yuval 17038f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 17048f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 17051a635e48SYuval Mintz if (rc) { 17068f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 17078f16bc97SSudarsana Kalluru return -EINVAL; 17088f16bc97SSudarsana Kalluru } 17098f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 17108f16bc97SSudarsana Kalluru } 17118f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 17128f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 17138f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 17148f16bc97SSudarsana Kalluru 17158f16bc97SSudarsana Kalluru return rc; 1716fe56b9e6SYuval Mintz } 1717fe56b9e6SYuval Mintz 17181a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1719fe56b9e6SYuval Mintz { 1720fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1721fe56b9e6SYuval Mintz 17221408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 17231408cc1fSYuval Mintz return; 17241408cc1fSYuval Mintz 1725fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1726fe56b9e6SYuval Mintz } 1727fe56b9e6SYuval Mintz 1728fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1729b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1730fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1731d031548eSMintz, Yuval u16 igu_sb_id, 1732d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1733fe56b9e6SYuval Mintz { 1734b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1735d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1736fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1737fe56b9e6SYuval Mintz 1738fe56b9e6SYuval Mintz /* Set the data field */ 1739fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1740fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1741fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1742fe56b9e6SYuval Mintz 1743fe56b9e6SYuval Mintz /* Set the control register */ 1744fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1745fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1746fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1747fe56b9e6SYuval Mintz 1748fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1749fe56b9e6SYuval Mintz 1750fe56b9e6SYuval Mintz barrier(); 1751fe56b9e6SYuval Mintz 1752fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1753fe56b9e6SYuval Mintz 1754fe56b9e6SYuval Mintz /* Flush the write to IGU */ 1755fe56b9e6SYuval Mintz mmiowb(); 1756fe56b9e6SYuval Mintz 1757fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1758d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1759d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1760fe56b9e6SYuval Mintz 1761fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1762fe56b9e6SYuval Mintz 1763fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1764fe56b9e6SYuval Mintz do { 1765fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1766fe56b9e6SYuval Mintz 1767fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1768fe56b9e6SYuval Mintz break; 1769fe56b9e6SYuval Mintz 1770fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1771fe56b9e6SYuval Mintz } while (--sleep_cnt); 1772fe56b9e6SYuval Mintz 1773fe56b9e6SYuval Mintz if (!sleep_cnt) 1774fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1775fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1776d031548eSMintz, Yuval val, igu_sb_id); 1777fe56b9e6SYuval Mintz } 1778fe56b9e6SYuval Mintz 1779fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1780fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1781d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1782fe56b9e6SYuval Mintz { 17831ac72433SMintz, Yuval struct qed_igu_block *p_block; 1784b2b897ebSYuval Mintz int pi, i; 1785fe56b9e6SYuval Mintz 17861ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 17871ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 17881ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 17891ac72433SMintz, Yuval igu_sb_id, 17901ac72433SMintz, Yuval p_block->function_id, 17911ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 17921ac72433SMintz, Yuval 1793fe56b9e6SYuval Mintz /* Set */ 1794fe56b9e6SYuval Mintz if (b_set) 1795d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1796fe56b9e6SYuval Mintz 1797fe56b9e6SYuval Mintz /* Clear */ 1798d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1799fe56b9e6SYuval Mintz 1800b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1801b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1802b2b897ebSYuval Mintz u32 val; 1803b2b897ebSYuval Mintz 1804b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1805d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1806d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1807d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1808b2b897ebSYuval Mintz usleep_range(10, 20); 1809b2b897ebSYuval Mintz else 1810b2b897ebSYuval Mintz break; 1811b2b897ebSYuval Mintz } 1812b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1813b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1814b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1815d031548eSMintz, Yuval igu_sb_id); 1816b2b897ebSYuval Mintz 1817fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1818fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1819fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1820d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1821fe56b9e6SYuval Mintz } 1822fe56b9e6SYuval Mintz 1823fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1824fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1825b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1826fe56b9e6SYuval Mintz { 18271ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 18281ac72433SMintz, Yuval struct qed_igu_block *p_block; 18291ac72433SMintz, Yuval u16 igu_sb_id = 0; 18301ac72433SMintz, Yuval u32 val = 0; 1831fe56b9e6SYuval Mintz 1832fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1833fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1834fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1835fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1836fe56b9e6SYuval Mintz 18371ac72433SMintz, Yuval for (igu_sb_id = 0; 18381ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 18391ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 1840fe56b9e6SYuval Mintz 18411ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 18421ac72433SMintz, Yuval !p_block->is_pf || 18431ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 18441ac72433SMintz, Yuval continue; 18451ac72433SMintz, Yuval 1846d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 1847fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 1848fe56b9e6SYuval Mintz b_set); 18491ac72433SMintz, Yuval } 1850fe56b9e6SYuval Mintz 18511ac72433SMintz, Yuval if (b_slowpath) 18521ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 18531ac72433SMintz, Yuval p_info->igu_dsb_id, 18541ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 18551ac72433SMintz, Yuval b_set); 1856fe56b9e6SYuval Mintz } 1857fe56b9e6SYuval Mintz 1858ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1859ebbdcc66SMintz, Yuval { 1860ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 1861ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 1862ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 1863ebbdcc66SMintz, Yuval u16 igu_sb_id; 1864ebbdcc66SMintz, Yuval u32 val, rval; 1865ebbdcc66SMintz, Yuval 1866ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 1867ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 1868ebbdcc66SMintz, Yuval } else { 1869ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 1870ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 1871ebbdcc66SMintz, Yuval */ 1872ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 1873ebbdcc66SMintz, Yuval 1874ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 1875ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 1876ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 1877ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 1878ebbdcc66SMintz, Yuval p_info->usage.cnt); 1879ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 1880ebbdcc66SMintz, Yuval } 1881ebbdcc66SMintz, Yuval 1882ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 1883ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 1884ebbdcc66SMintz, Yuval 1885ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 1886ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 1887ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 1888ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 1889ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 1890ebbdcc66SMintz, Yuval 1891ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 1892ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 1893ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 1894ebbdcc66SMintz, Yuval */ 1895ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 1896ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 1897ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 1898ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 1899ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 1900ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 1901ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 1902ebbdcc66SMintz, Yuval return -EINVAL; 1903ebbdcc66SMintz, Yuval } 1904ebbdcc66SMintz, Yuval 1905ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 1906ebbdcc66SMintz, Yuval * number of VFs. 1907ebbdcc66SMintz, Yuval */ 1908ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 1909ebbdcc66SMintz, Yuval } 1910ebbdcc66SMintz, Yuval } 1911ebbdcc66SMintz, Yuval 1912ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 1913ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 1914ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 1915ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 1916ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 1917ebbdcc66SMintz, Yuval 1918ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 1919ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 1920ebbdcc66SMintz, Yuval */ 1921ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 1922ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 1923ebbdcc66SMintz, Yuval 1924ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 1925ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 1926ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 1927ebbdcc66SMintz, Yuval val = 0; 1928ebbdcc66SMintz, Yuval 1929ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 1930ebbdcc66SMintz, Yuval continue; 1931ebbdcc66SMintz, Yuval 1932ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 1933ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 1934ebbdcc66SMintz, Yuval p_block->is_pf = 1; 1935ebbdcc66SMintz, Yuval p_block->vector_number = 0; 1936ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 1937ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 1938ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 1939ebbdcc66SMintz, Yuval } else if (pf_sbs) { 1940ebbdcc66SMintz, Yuval pf_sbs--; 1941ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 1942ebbdcc66SMintz, Yuval p_block->is_pf = 1; 1943ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 1944ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 1945ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 1946ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 1947ebbdcc66SMintz, Yuval } else if (vf_sbs) { 1948ebbdcc66SMintz, Yuval p_block->function_id = 1949ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 1950ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 1951ebbdcc66SMintz, Yuval p_block->is_pf = 0; 1952ebbdcc66SMintz, Yuval p_block->vector_number = 0; 1953ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 1954ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 1955ebbdcc66SMintz, Yuval vf_sbs--; 1956ebbdcc66SMintz, Yuval } else { 1957ebbdcc66SMintz, Yuval p_block->function_id = 0; 1958ebbdcc66SMintz, Yuval p_block->is_pf = 0; 1959ebbdcc66SMintz, Yuval p_block->vector_number = 0; 1960ebbdcc66SMintz, Yuval } 1961ebbdcc66SMintz, Yuval 1962ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 1963ebbdcc66SMintz, Yuval p_block->function_id); 1964ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 1965ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 1966ebbdcc66SMintz, Yuval p_block->vector_number); 1967ebbdcc66SMintz, Yuval 1968ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 1969ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 1970ebbdcc66SMintz, Yuval 1971ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 1972ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 1973ebbdcc66SMintz, Yuval 1974ebbdcc66SMintz, Yuval if (rval != val) { 1975ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 1976ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 1977ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 1978ebbdcc66SMintz, Yuval 1979ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 1980ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 1981ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 1982ebbdcc66SMintz, Yuval igu_sb_id, 1983ebbdcc66SMintz, Yuval p_block->function_id, 1984ebbdcc66SMintz, Yuval p_block->is_pf, 1985ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 1986ebbdcc66SMintz, Yuval } 1987ebbdcc66SMintz, Yuval } 1988ebbdcc66SMintz, Yuval 1989ebbdcc66SMintz, Yuval return 0; 1990ebbdcc66SMintz, Yuval } 1991ebbdcc66SMintz, Yuval 1992d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 1993d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 19944ac801b7SYuval Mintz { 19954ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 1996d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 19974ac801b7SYuval Mintz struct qed_igu_block *p_block; 19984ac801b7SYuval Mintz 1999d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 20004ac801b7SYuval Mintz 20014ac801b7SYuval Mintz /* Fill the block information */ 2002d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 20034ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2004d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 20051ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 20064ac801b7SYuval Mintz } 20074ac801b7SYuval Mintz 20081a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2009fe56b9e6SYuval Mintz { 2010fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2011d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2012d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2013d749dd0dSMintz, Yuval u16 igu_sb_id; 2014fe56b9e6SYuval Mintz 201560fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2016fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2017fe56b9e6SYuval Mintz return -ENOMEM; 2018fe56b9e6SYuval Mintz 2019fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2020fe56b9e6SYuval Mintz 2021d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2022d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2023d749dd0dSMintz, Yuval 2024d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 20251408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 20261408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 20271408cc1fSYuval Mintz 20281408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 20291408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 20301408cc1fSYuval Mintz } 20311408cc1fSYuval Mintz 2032d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2033d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2034d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2035d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2036d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2037fe56b9e6SYuval Mintz 2038d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2039d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2040d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2041d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2042d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2043fe56b9e6SYuval Mintz 20441ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2045726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2046d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2047d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2048d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 20491408cc1fSYuval Mintz /* Available for VFs of this PF */ 2050d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2051d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2052d749dd0dSMintz, Yuval 20531ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2054726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 20551408cc1fSYuval Mintz } 20565a1f965aSMintz, Yuval 2057d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2058ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 20595a1f965aSMintz, Yuval */ 2060d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2061d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2062d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2063d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2064d749dd0dSMintz, Yuval } 20655a1f965aSMintz, Yuval 2066d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2067d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2068d749dd0dSMintz, Yuval * everything. 2069d749dd0dSMintz, Yuval */ 2070d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2071d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2072d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2073d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2074d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2075d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2076d749dd0dSMintz, Yuval } 2077d749dd0dSMintz, Yuval } 2078d749dd0dSMintz, Yuval 2079d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 20805a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2081d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2082d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 20835a1f965aSMintz, Yuval return -EINVAL; 20845a1f965aSMintz, Yuval } 2085d749dd0dSMintz, Yuval 2086d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2087726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2088726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2089fe56b9e6SYuval Mintz 2090d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2091ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2092d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2093726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2094fe56b9e6SYuval Mintz 2095fe56b9e6SYuval Mintz return 0; 2096fe56b9e6SYuval Mintz } 2097fe56b9e6SYuval Mintz 2098fe56b9e6SYuval Mintz /** 2099fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 2100fe56b9e6SYuval Mintz * 2101fe56b9e6SYuval Mintz * @param p_hwfn 2102fe56b9e6SYuval Mintz */ 2103fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2104fe56b9e6SYuval Mintz { 21051a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2106fe56b9e6SYuval Mintz 2107fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2108fe56b9e6SYuval Mintz } 2109fe56b9e6SYuval Mintz 2110fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2111fe56b9e6SYuval Mintz { 2112fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2113fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2114fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2115fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 21161a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 21171a635e48SYuval Mintz u64 intr_status = 0; 2118fe56b9e6SYuval Mintz 2119fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2120fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2121fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2122fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2123fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2124fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2125fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2126fe56b9e6SYuval Mintz 2127fe56b9e6SYuval Mintz return intr_status; 2128fe56b9e6SYuval Mintz } 2129fe56b9e6SYuval Mintz 2130fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2131fe56b9e6SYuval Mintz { 2132fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 2133fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 2134fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2135fe56b9e6SYuval Mintz } 2136fe56b9e6SYuval Mintz 2137fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2138fe56b9e6SYuval Mintz { 213960fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2140fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 2141fe56b9e6SYuval Mintz return -ENOMEM; 2142fe56b9e6SYuval Mintz 2143fe56b9e6SYuval Mintz return 0; 2144fe56b9e6SYuval Mintz } 2145fe56b9e6SYuval Mintz 2146fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2147fe56b9e6SYuval Mintz { 2148fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 21493587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 2150fe56b9e6SYuval Mintz } 2151fe56b9e6SYuval Mintz 21521a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2153fe56b9e6SYuval Mintz { 2154fe56b9e6SYuval Mintz int rc = 0; 2155fe56b9e6SYuval Mintz 2156fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 215783aeb933SYuval Mintz if (rc) 21582591c280SJoe Perches return rc; 21592591c280SJoe Perches 21602591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 21612591c280SJoe Perches if (rc) 21622591c280SJoe Perches return rc; 21632591c280SJoe Perches 21642591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 216583aeb933SYuval Mintz 2166fe56b9e6SYuval Mintz return rc; 2167fe56b9e6SYuval Mintz } 2168fe56b9e6SYuval Mintz 2169fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2170fe56b9e6SYuval Mintz { 2171fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2172cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2173fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 2174fe56b9e6SYuval Mintz } 2175fe56b9e6SYuval Mintz 21761a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2177fe56b9e6SYuval Mintz { 21780d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 21790d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2180fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2181fe56b9e6SYuval Mintz } 2182fe56b9e6SYuval Mintz 21834ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 21844ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2185fe56b9e6SYuval Mintz { 2186fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2187fe56b9e6SYuval Mintz 21884ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 21894ac801b7SYuval Mintz return; 2190fe56b9e6SYuval Mintz 2191726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2192fe56b9e6SYuval Mintz } 21938f16bc97SSudarsana Kalluru 21948f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 21958f16bc97SSudarsana Kalluru { 21968f16bc97SSudarsana Kalluru int i; 21978f16bc97SSudarsana Kalluru 21988f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 21998f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 22008f16bc97SSudarsana Kalluru } 2201722003acSSudarsana Reddy Kalluru 2202722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2203722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2204722003acSSudarsana Reddy Kalluru { 2205722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 2206722003acSSudarsana Reddy Kalluru int rc; 2207722003acSSudarsana Reddy Kalluru 2208722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2209722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2210722003acSSudarsana Reddy Kalluru return -EINVAL; 2211722003acSSudarsana Reddy Kalluru } 2212722003acSSudarsana Reddy Kalluru 2213722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2214722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2215722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2, 0); 2216722003acSSudarsana Reddy Kalluru if (rc) { 2217722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2218722003acSSudarsana Reddy Kalluru return rc; 2219722003acSSudarsana Reddy Kalluru } 2220722003acSSudarsana Reddy Kalluru 2221722003acSSudarsana Reddy Kalluru if (tx) 2222722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2223722003acSSudarsana Reddy Kalluru else 2224722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2225722003acSSudarsana Reddy Kalluru 2226722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2227722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2228722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 2229722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2, 0); 2230722003acSSudarsana Reddy Kalluru if (rc) { 2231722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2232722003acSSudarsana Reddy Kalluru return rc; 2233722003acSSudarsana Reddy Kalluru } 2234722003acSSudarsana Reddy Kalluru 2235722003acSSudarsana Reddy Kalluru return rc; 2236722003acSSudarsana Reddy Kalluru } 2237