1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/bitops.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 39fe56b9e6SYuval Mintz #include <linux/errno.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/kernel.h> 42fe56b9e6SYuval Mintz #include <linux/pci.h> 43fe56b9e6SYuval Mintz #include <linux/slab.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include "qed.h" 46fe56b9e6SYuval Mintz #include "qed_hsi.h" 47fe56b9e6SYuval Mintz #include "qed_hw.h" 48fe56b9e6SYuval Mintz #include "qed_init_ops.h" 49fe56b9e6SYuval Mintz #include "qed_int.h" 50fe56b9e6SYuval Mintz #include "qed_mcp.h" 51fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 52fe56b9e6SYuval Mintz #include "qed_sp.h" 531408cc1fSYuval Mintz #include "qed_sriov.h" 541408cc1fSYuval Mintz #include "qed_vf.h" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz struct qed_pi_info { 57fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 58fe56b9e6SYuval Mintz void *cookie; 59fe56b9e6SYuval Mintz }; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz struct qed_sb_sp_info { 62fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz /* per protocol index data */ 6521dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 66fe56b9e6SYuval Mintz }; 67fe56b9e6SYuval Mintz 68ff38577aSYuval Mintz enum qed_attention_type { 69ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 70ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 71ff38577aSYuval Mintz }; 72ff38577aSYuval Mintz 73cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75cc875c2eSYuval Mintz 760d956e8aSYuval Mintz struct aeu_invert_reg_bit { 770d956e8aSYuval Mintz char bit_name[30]; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 820d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 830d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 840d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 85a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 860d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 870d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 880d956e8aSYuval Mintz ATTENTION_PARITY) 890d956e8aSYuval Mintz 900d956e8aSYuval Mintz /* Multiple bits start with this offset */ 910d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 920d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 93ba36f718SMintz, Yuval 94ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 95ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 96ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 97ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 98ba36f718SMintz, Yuval 99936c7ba4SIgor Russkikh #define ATTENTION_CLEAR_ENABLE BIT(28) 1000d956e8aSYuval Mintz unsigned int flags; 101ff38577aSYuval Mintz 102b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 103b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 104b4149dc7SYuval Mintz 105ff38577aSYuval Mintz enum block_id block_index; 1060d956e8aSYuval Mintz }; 1070d956e8aSYuval Mintz 1080d956e8aSYuval Mintz struct aeu_invert_reg { 1090d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 1100d956e8aSYuval Mintz }; 1110d956e8aSYuval Mintz 1120d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 1130d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 1140d956e8aSYuval Mintz 115b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 116b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 117b4149dc7SYuval Mintz { 118b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 119b4149dc7SYuval Mintz 120b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 121b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 122b4149dc7SYuval Mintz tmp); 123b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 124b4149dc7SYuval Mintz 0xffffffff); 125b4149dc7SYuval Mintz 126b4149dc7SYuval Mintz return 0; 127b4149dc7SYuval Mintz } 128b4149dc7SYuval Mintz 129b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 130b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 131b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 132b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 133b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 134b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 135b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 136b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 137b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 138b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 139b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 140b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 141b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 142b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 143b4149dc7SYuval Mintz { 144b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 145b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 146b4149dc7SYuval Mintz 147b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 148b4149dc7SYuval Mintz u32 addr, data, length; 149b4149dc7SYuval Mintz 150b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 151b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 152b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 153b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 154b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 155b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 156b4149dc7SYuval Mintz 157b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 158b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 159b4149dc7SYuval Mintz addr, length, 160b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 161b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 162b4149dc7SYuval Mintz (u8) GET_FIELD(data, 163b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 164b4149dc7SYuval Mintz (u8) GET_FIELD(data, 165b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 166b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 167b4149dc7SYuval Mintz (u8) GET_FIELD(data, 168b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 169b4149dc7SYuval Mintz data); 170b4149dc7SYuval Mintz } 171b4149dc7SYuval Mintz 172b4149dc7SYuval Mintz return 0; 173b4149dc7SYuval Mintz } 174b4149dc7SYuval Mintz 175b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 176b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 177b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 178b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 179b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 180b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 181b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 182b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 183b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 184b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 185b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 186b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 187b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 188b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 189b4149dc7SYuval Mintz { 190b4149dc7SYuval Mintz switch (master) { 191b4149dc7SYuval Mintz case 1: return "PXP"; 192b4149dc7SYuval Mintz case 2: return "MCP"; 193b4149dc7SYuval Mintz case 3: return "MSDM"; 194b4149dc7SYuval Mintz case 4: return "PSDM"; 195b4149dc7SYuval Mintz case 5: return "YSDM"; 196b4149dc7SYuval Mintz case 6: return "USDM"; 197b4149dc7SYuval Mintz case 7: return "TSDM"; 198b4149dc7SYuval Mintz case 8: return "XSDM"; 199b4149dc7SYuval Mintz case 9: return "DBU"; 200b4149dc7SYuval Mintz case 10: return "DMAE"; 201b4149dc7SYuval Mintz default: 2029165dabbSMasanari Iida return "Unknown"; 203b4149dc7SYuval Mintz } 204b4149dc7SYuval Mintz } 205b4149dc7SYuval Mintz 206b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 207b4149dc7SYuval Mintz { 208b4149dc7SYuval Mintz u32 tmp, tmp2; 209b4149dc7SYuval Mintz 210b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 211b4149dc7SYuval Mintz * of interrupts via the validity register 212b4149dc7SYuval Mintz */ 213b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 214b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 215b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 216b4149dc7SYuval Mintz goto out; 217b4149dc7SYuval Mintz 218b4149dc7SYuval Mintz /* Read the GRC timeout information */ 219b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 220b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 221b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 222b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 223b4149dc7SYuval Mintz 224b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 225b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 226b4149dc7SYuval Mintz tmp2, tmp, 227b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 228b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 229b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 230b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 231b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 232fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 233b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 234b4149dc7SYuval Mintz 235b4149dc7SYuval Mintz out: 236b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 237b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 238b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 239b4149dc7SYuval Mintz return 0; 240b4149dc7SYuval Mintz } 241b4149dc7SYuval Mintz 242b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 243b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 244b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 245b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 246b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 247b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 248b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 249b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 250b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 251b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 252b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 253b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 254b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 255b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 256b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 257b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 258b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 259666db486STomer Tayar 260eb61c2d6SAlexander Lobakin int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 261eb61c2d6SAlexander Lobakin bool hw_init) 262b4149dc7SYuval Mintz { 263eb61c2d6SAlexander Lobakin char msg[256]; 264b4149dc7SYuval Mintz u32 tmp; 265b4149dc7SYuval Mintz 266666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 267b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 268b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 269b4149dc7SYuval Mintz 270666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 271b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 272666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 273b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 274666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 275b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 276b4149dc7SYuval Mintz 277eb61c2d6SAlexander Lobakin snprintf(msg, sizeof(msg), 278b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 279b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 280eb61c2d6SAlexander Lobakin "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]", 281b4149dc7SYuval Mintz addr_hi, addr_lo, details, 282b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 283b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 284eb61c2d6SAlexander Lobakin !!GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VF_VALID), 285b4149dc7SYuval Mintz tmp, 286eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR), 287eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME), 288eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN)); 289eb61c2d6SAlexander Lobakin 290eb61c2d6SAlexander Lobakin if (hw_init) 291eb61c2d6SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg); 292eb61c2d6SAlexander Lobakin else 293eb61c2d6SAlexander Lobakin DP_NOTICE(p_hwfn, "%s\n", msg); 294b4149dc7SYuval Mintz } 295b4149dc7SYuval Mintz 296666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 297b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 298b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 299b4149dc7SYuval Mintz 300666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 301b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 302666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 303b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 304666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 305b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 306b4149dc7SYuval Mintz 307666db486STomer Tayar DP_NOTICE(p_hwfn, 308b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 309b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 310b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 311b4149dc7SYuval Mintz addr_hi, addr_lo, details, 312b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 313b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 314b4149dc7SYuval Mintz GET_FIELD(details, 315b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 316b4149dc7SYuval Mintz tmp, 317666db486STomer Tayar GET_FIELD(tmp, 318666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 319666db486STomer Tayar GET_FIELD(tmp, 320666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 321666db486STomer Tayar GET_FIELD(tmp, 322666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 323b4149dc7SYuval Mintz } 324b4149dc7SYuval Mintz 325666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 326eb61c2d6SAlexander Lobakin if (tmp & PGLUE_ATTENTION_ICPL_VALID) { 327eb61c2d6SAlexander Lobakin snprintf(msg, sizeof(msg), "ICPL error - %08x", tmp); 328eb61c2d6SAlexander Lobakin 329eb61c2d6SAlexander Lobakin if (hw_init) 330eb61c2d6SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg); 331eb61c2d6SAlexander Lobakin else 332eb61c2d6SAlexander Lobakin DP_NOTICE(p_hwfn, "%s\n", msg); 333eb61c2d6SAlexander Lobakin } 334b4149dc7SYuval Mintz 335666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 336b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 337b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 338b4149dc7SYuval Mintz 339666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 340b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 341666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 342b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 343b4149dc7SYuval Mintz 344666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 345b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 346b4149dc7SYuval Mintz } 347b4149dc7SYuval Mintz 348666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 349b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 350b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 351b4149dc7SYuval Mintz 352666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 353b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 354666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 355b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 356666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 357b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 358b4149dc7SYuval Mintz 359666db486STomer Tayar DP_NOTICE(p_hwfn, 360b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 361b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 362b4149dc7SYuval Mintz } 363b4149dc7SYuval Mintz 364b4149dc7SYuval Mintz /* Clear the indications */ 365666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 366b4149dc7SYuval Mintz 367b4149dc7SYuval Mintz return 0; 368b4149dc7SYuval Mintz } 369b4149dc7SYuval Mintz 370666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 371666db486STomer Tayar { 372eb61c2d6SAlexander Lobakin return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false); 373666db486STomer Tayar } 374666db486STomer Tayar 3752ec276d5SIgor Russkikh static int qed_fw_assertion(struct qed_hwfn *p_hwfn) 3762ec276d5SIgor Russkikh { 3772ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT, 3782ec276d5SIgor Russkikh "FW assertion!\n"); 3792ec276d5SIgor Russkikh 3802ec276d5SIgor Russkikh return -EINVAL; 3812ec276d5SIgor Russkikh } 3822ec276d5SIgor Russkikh 383936c7ba4SIgor Russkikh static int qed_general_attention_35(struct qed_hwfn *p_hwfn) 384936c7ba4SIgor Russkikh { 385936c7ba4SIgor Russkikh DP_INFO(p_hwfn, "General attention 35!\n"); 386936c7ba4SIgor Russkikh 387936c7ba4SIgor Russkikh return 0; 388936c7ba4SIgor Russkikh } 389936c7ba4SIgor Russkikh 390b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 391b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 392a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 393b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 394b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 395a1b469b8SAriel Elior 396a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000 397a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100 398a1b469b8SAriel Elior 399a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 400a1b469b8SAriel Elior struct qed_ptt *p_ptt) 401a1b469b8SAriel Elior { 402a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT; 403a1b469b8SAriel Elior u32 usage = 1; 404a1b469b8SAriel Elior 4050d72c2acSDenis Bolotin /* Flush any pending (e)dpms as they may never arrive */ 4060d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 4070d72c2acSDenis Bolotin 408a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since 409a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such 410a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with 411a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM 412a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or 413a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second 414a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such 415a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before 416a1b469b8SAriel Elior * releasing the overflow sticky indication. 417a1b469b8SAriel Elior */ 418a1b469b8SAriel Elior while (count-- && usage) { 419a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 420a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL); 421a1b469b8SAriel Elior } 422a1b469b8SAriel Elior 423a1b469b8SAriel Elior /* should have been depleted by now */ 424a1b469b8SAriel Elior if (usage) { 425a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 426a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 427a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 428a1b469b8SAriel Elior return -EBUSY; 429a1b469b8SAriel Elior } 430a1b469b8SAriel Elior 431a1b469b8SAriel Elior return 0; 432a1b469b8SAriel Elior } 433a1b469b8SAriel Elior 434a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 435a1b469b8SAriel Elior { 4360d72c2acSDenis Bolotin u32 attn_ovfl, cur_ovfl; 437a1b469b8SAriel Elior int rc; 438a1b469b8SAriel Elior 4390d72c2acSDenis Bolotin attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT, 4400d72c2acSDenis Bolotin &p_hwfn->db_recovery_info.overflow); 4410d72c2acSDenis Bolotin cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4420d72c2acSDenis Bolotin if (!cur_ovfl && !attn_ovfl) 443a1b469b8SAriel Elior return 0; 444a1b469b8SAriel Elior 4450d72c2acSDenis Bolotin DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n", 4460d72c2acSDenis Bolotin attn_ovfl, cur_ovfl); 4470d72c2acSDenis Bolotin 4480d72c2acSDenis Bolotin if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { 449a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 450a1b469b8SAriel Elior if (rc) 451a1b469b8SAriel Elior return rc; 452a1b469b8SAriel Elior } 453a1b469b8SAriel Elior 454a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */ 455a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 456a1b469b8SAriel Elior 457a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */ 4589ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn); 459a1b469b8SAriel Elior 460a1b469b8SAriel Elior return 0; 461a1b469b8SAriel Elior } 462a1b469b8SAriel Elior 4630d72c2acSDenis Bolotin static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) 4640d72c2acSDenis Bolotin { 4650d72c2acSDenis Bolotin struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 4660d72c2acSDenis Bolotin u32 overflow; 4670d72c2acSDenis Bolotin int rc; 4680d72c2acSDenis Bolotin 4690d72c2acSDenis Bolotin overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4700d72c2acSDenis Bolotin if (!overflow) 4710d72c2acSDenis Bolotin goto out; 4720d72c2acSDenis Bolotin 4730d72c2acSDenis Bolotin /* Run PF doorbell recovery in next periodic handler */ 4740d72c2acSDenis Bolotin set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); 4750d72c2acSDenis Bolotin 4760d72c2acSDenis Bolotin if (!p_hwfn->db_bar_no_edpm) { 4770d72c2acSDenis Bolotin rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 4780d72c2acSDenis Bolotin if (rc) 4790d72c2acSDenis Bolotin goto out; 4800d72c2acSDenis Bolotin } 4810d72c2acSDenis Bolotin 4820d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 4830d72c2acSDenis Bolotin out: 4840d72c2acSDenis Bolotin /* Schedule the handler even if overflow was not detected */ 4850d72c2acSDenis Bolotin qed_periodic_db_rec_start(p_hwfn); 4860d72c2acSDenis Bolotin } 4870d72c2acSDenis Bolotin 4880d72c2acSDenis Bolotin static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) 489b4149dc7SYuval Mintz { 490a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason; 491a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 492a1b469b8SAriel Elior 493a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell 494a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If 495a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again. 496a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring. 497a1b469b8SAriel Elior */ 498d4476b8aSDenis Bolotin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 499a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 500a1b469b8SAriel Elior return 0; 501a1b469b8SAriel Elior 502d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 503d4476b8aSDenis Bolotin 504a1b469b8SAriel Elior /* check if db_drop or overflow happened */ 505a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 506a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 507a1b469b8SAriel Elior /* Obtain data about db drop/overflow */ 508a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt, 509a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) & 510b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 511a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 512a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt, 513a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS); 514a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt, 515a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON); 516b4149dc7SYuval Mintz 517a1b469b8SAriel Elior /* Log info */ 518a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 519a1b469b8SAriel Elior "Doorbell drop occurred\n" 520a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n" 521a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n" 522a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n" 523a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 524a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 525a1b469b8SAriel Elior address, 526a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 527b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 528a1b469b8SAriel Elior first_drop_reason, all_drops_reason); 529a1b469b8SAriel Elior 530a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */ 531a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 532a1b469b8SAriel Elior 533a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different 534a1b469b8SAriel Elior * reason than overflow we mark as handled) 535a1b469b8SAriel Elior */ 536a1b469b8SAriel Elior qed_wr(p_hwfn, 537a1b469b8SAriel Elior p_ptt, 538a1b469b8SAriel Elior DORQ_REG_INT_STS_WR, 539a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP | 540a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 541a1b469b8SAriel Elior 542a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */ 543a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 544a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 545a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 546a1b469b8SAriel Elior return 0; 547b4149dc7SYuval Mintz } 548b4149dc7SYuval Mintz 549a1b469b8SAriel Elior /* Some other indication was present - non recoverable */ 550a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n"); 551a1b469b8SAriel Elior 552b4149dc7SYuval Mintz return -EINVAL; 553b4149dc7SYuval Mintz } 554b4149dc7SYuval Mintz 5550d72c2acSDenis Bolotin static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 5560d72c2acSDenis Bolotin { 5570d72c2acSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true; 5580d72c2acSDenis Bolotin qed_dorq_attn_overflow(p_hwfn); 5590d72c2acSDenis Bolotin 5600d72c2acSDenis Bolotin return qed_dorq_attn_int_sts(p_hwfn); 5610d72c2acSDenis Bolotin } 5620d72c2acSDenis Bolotin 563d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 564d4476b8aSDenis Bolotin { 565d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn) 566d4476b8aSDenis Bolotin goto out; 567d4476b8aSDenis Bolotin 568d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */ 569d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn); 570d4476b8aSDenis Bolotin out: 571d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false; 572d4476b8aSDenis Bolotin } 573d4476b8aSDenis Bolotin 574ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 575ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 576ba36f718SMintz, Yuval */ 577ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 578ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 579ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 580ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 581ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 582ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 583ba36f718SMintz, Yuval }; 584ba36f718SMintz, Yuval 585ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 586ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 587ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 588ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 589ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 590ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 591ba36f718SMintz, Yuval }; 592ba36f718SMintz, Yuval 5930d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 5940d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 5950d956e8aSYuval Mintz { 5960d956e8aSYuval Mintz { /* After Invert 1 */ 5970d956e8aSYuval Mintz {"GPIO0 function%d", 598b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5990d956e8aSYuval Mintz } 6000d956e8aSYuval Mintz }, 6010d956e8aSYuval Mintz 6020d956e8aSYuval Mintz { 6030d956e8aSYuval Mintz { /* After Invert 2 */ 604b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 605b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 606b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 607b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 608b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 609666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 610b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 611b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 612b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 613b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 614b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 6150d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 616ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 617b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 6180d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 619b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 6200d956e8aSYuval Mintz } 6210d956e8aSYuval Mintz }, 6220d956e8aSYuval Mintz 6230d956e8aSYuval Mintz { 6240d956e8aSYuval Mintz { /* After Invert 3 */ 6250d956e8aSYuval Mintz {"General Attention %d", 626b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 6270d956e8aSYuval Mintz } 6280d956e8aSYuval Mintz }, 6290d956e8aSYuval Mintz 6300d956e8aSYuval Mintz { 6310d956e8aSYuval Mintz { /* After Invert 4 */ 632936c7ba4SIgor Russkikh {"General Attention 32", ATTENTION_SINGLE | 633936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_fw_assertion, 6342ec276d5SIgor Russkikh MAX_BLOCK_ID}, 6350d956e8aSYuval Mintz {"General Attention %d", 6360d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 637b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 638936c7ba4SIgor Russkikh {"General Attention 35", ATTENTION_SINGLE | 639936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_general_attention_35, 640936c7ba4SIgor Russkikh MAX_BLOCK_ID}, 641ba36f718SMintz, Yuval {"NWS Parity", 642ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 643ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 644ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 645ba36f718SMintz, Yuval {"NWS Interrupt", 646ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 647ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 648ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 649ba36f718SMintz, Yuval {"NWM Parity", 650ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 651ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 652ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 653ba36f718SMintz, Yuval {"NWM Interrupt", 654ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 655ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 656ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 657b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 658b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 659b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 660b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 661b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 662ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 663b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 664b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 665b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 666b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 667ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 668b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 669b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 670b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 671b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 672b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 673b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 6740d956e8aSYuval Mintz } 6750d956e8aSYuval Mintz }, 6760d956e8aSYuval Mintz 6770d956e8aSYuval Mintz { 6780d956e8aSYuval Mintz { /* After Invert 5 */ 679b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 680b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 681b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 682b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 683b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 684b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 685b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 686b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 687b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 688b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 689b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 690b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 691b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 692b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 693b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 694b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 6950d956e8aSYuval Mintz } 6960d956e8aSYuval Mintz }, 6970d956e8aSYuval Mintz 6980d956e8aSYuval Mintz { 6990d956e8aSYuval Mintz { /* After Invert 6 */ 700b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 701b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 702b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 703b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 704b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 705b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 706b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 707b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 708b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 709b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 710b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 711b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 712b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 713b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 714b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 715b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 716b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 7170d956e8aSYuval Mintz } 7180d956e8aSYuval Mintz }, 7190d956e8aSYuval Mintz 7200d956e8aSYuval Mintz { 7210d956e8aSYuval Mintz { /* After Invert 7 */ 722b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 723b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 724b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 725b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 726b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 727b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 728b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 729b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 730b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 731b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 732b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 733b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 734b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 735b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 736b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 737b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 738b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 7390d956e8aSYuval Mintz } 7400d956e8aSYuval Mintz }, 7410d956e8aSYuval Mintz 7420d956e8aSYuval Mintz { 7430d956e8aSYuval Mintz { /* After Invert 8 */ 744b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 745b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 746b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 747b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 748b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 749b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 750b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 751b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 752b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 753b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 754b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 755b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 756b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 757b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 758b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 759b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 760b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 761b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 762b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 763b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 764b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 765b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 766b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 767ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 768b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 769b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 770b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 771ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 772b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 773ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 774b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7750d956e8aSYuval Mintz } 7760d956e8aSYuval Mintz }, 7770d956e8aSYuval Mintz 7780d956e8aSYuval Mintz { 7790d956e8aSYuval Mintz { /* After Invert 9 */ 780b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 781b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 782ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 783b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 784b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 785b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 786ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 787b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 788ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 789b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7900d956e8aSYuval Mintz } 7910d956e8aSYuval Mintz }, 7920d956e8aSYuval Mintz }; 7930d956e8aSYuval Mintz 794ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 795ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 796ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 797ba36f718SMintz, Yuval { 798ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 799ba36f718SMintz, Yuval return p_bit; 800ba36f718SMintz, Yuval 801ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 802ba36f718SMintz, Yuval return p_bit; 803ba36f718SMintz, Yuval 804ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 805ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 806ba36f718SMintz, Yuval } 807ba36f718SMintz, Yuval 808ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 809ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 810ba36f718SMintz, Yuval { 811ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 812ba36f718SMintz, Yuval ATTENTION_PARITY); 813ba36f718SMintz, Yuval } 814ba36f718SMintz, Yuval 815cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 816cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 817cc875c2eSYuval Mintz struct qed_sb_attn_info { 818cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 819cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 820cc875c2eSYuval Mintz dma_addr_t sb_phys; 821cc875c2eSYuval Mintz 822cc875c2eSYuval Mintz /* Last seen running index */ 823cc875c2eSYuval Mintz u16 index; 824cc875c2eSYuval Mintz 8250d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 8260d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 8270d956e8aSYuval Mintz 8280d956e8aSYuval Mintz /* A pointer to the attention description structure */ 8290d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 8300d956e8aSYuval Mintz 831cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 832cc875c2eSYuval Mintz u16 known_attn; 833cc875c2eSYuval Mintz 834cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 835cc875c2eSYuval Mintz u32 mfw_attn_addr; 836cc875c2eSYuval Mintz }; 837cc875c2eSYuval Mintz 838cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 839cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 840cc875c2eSYuval Mintz { 8411a635e48SYuval Mintz u16 rc = 0, index; 842cc875c2eSYuval Mintz 843cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 844cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 845cc875c2eSYuval Mintz p_sb_desc->index = index; 846cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 847cc875c2eSYuval Mintz } 848cc875c2eSYuval Mintz 849cc875c2eSYuval Mintz return rc; 850cc875c2eSYuval Mintz } 851cc875c2eSYuval Mintz 852cc875c2eSYuval Mintz /** 853cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 854cc875c2eSYuval Mintz * 855cc875c2eSYuval Mintz * @param p_hwfn 856cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 857cc875c2eSYuval Mintz * @return int 858cc875c2eSYuval Mintz */ 8591a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 860cc875c2eSYuval Mintz { 861cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 862cc875c2eSYuval Mintz u32 igu_mask; 863cc875c2eSYuval Mintz 864cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 8651a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 866cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 867cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 868cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 869cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 870cc875c2eSYuval Mintz 871cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 872cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 873cc875c2eSYuval Mintz sb_attn_sw->known_attn, 874cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 875cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 876cc875c2eSYuval Mintz 877cc875c2eSYuval Mintz /* Handle MCP events */ 878cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 879cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 880cc875c2eSYuval Mintz /* Clean the MCP attention */ 881cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 882cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 883cc875c2eSYuval Mintz } 884cc875c2eSYuval Mintz 885cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 886cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 887cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 888cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 889cc875c2eSYuval Mintz (u32)asserted_bits); 890cc875c2eSYuval Mintz 891cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 892cc875c2eSYuval Mintz asserted_bits); 893cc875c2eSYuval Mintz 894cc875c2eSYuval Mintz return 0; 895cc875c2eSYuval Mintz } 896cc875c2eSYuval Mintz 8970ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 8980ebbd1c8SMintz, Yuval enum block_id id, 8990ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 900ff38577aSYuval Mintz { 9010ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 9020ebbd1c8SMintz, Yuval enum dbg_status status; 903ff38577aSYuval Mintz 9040ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 905ff38577aSYuval Mintz 9060ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 9070ebbd1c8SMintz, Yuval b_clear, &attn_results); 9080ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 909ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 9100ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 9110ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 9120ebbd1c8SMintz, Yuval else 9130ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 914ff38577aSYuval Mintz } 915ff38577aSYuval Mintz 916cc875c2eSYuval Mintz /** 9170d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 9180d956e8aSYuval Mintz * cause of the attention 9190d956e8aSYuval Mintz * 9200d956e8aSYuval Mintz * @param p_hwfn 9210d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 9220d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 9230d956e8aSYuval Mintz * this bit to this group. 9240d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 9250d956e8aSYuval Mintz * 9260d956e8aSYuval Mintz * @return int 9270d956e8aSYuval Mintz */ 9280d956e8aSYuval Mintz static int 9290d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 9300d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9310d956e8aSYuval Mintz u32 aeu_en_reg, 9326010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 9330d956e8aSYuval Mintz { 9340ebbd1c8SMintz, Yuval bool b_fatal = false; 9350d956e8aSYuval Mintz int rc = -EINVAL; 936b4149dc7SYuval Mintz u32 val; 9370d956e8aSYuval Mintz 9380d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 9396010179dSMintz, Yuval p_bit_name, bitmask); 9400d956e8aSYuval Mintz 941b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 942b4149dc7SYuval Mintz if (p_aeu->cb) { 943b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 9446010179dSMintz, Yuval p_bit_name); 945b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 946b4149dc7SYuval Mintz } 947b4149dc7SYuval Mintz 9480ebbd1c8SMintz, Yuval if (rc) 9490ebbd1c8SMintz, Yuval b_fatal = true; 950ff38577aSYuval Mintz 9510ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 9520ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 9530ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 9540ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 955ff38577aSYuval Mintz 9562ec276d5SIgor Russkikh /* Reach assertion if attention is fatal */ 9572ec276d5SIgor Russkikh if (b_fatal) 9582ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN, 9592ec276d5SIgor Russkikh "`%s': Fatal attention\n", 9602ec276d5SIgor Russkikh p_bit_name); 9612ec276d5SIgor Russkikh else /* If the attention is benign, no need to prevent it */ 962b4149dc7SYuval Mintz goto out; 963b4149dc7SYuval Mintz 9640d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 9650d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 966b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 9670d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 9686010179dSMintz, Yuval p_bit_name); 9690d956e8aSYuval Mintz 970b4149dc7SYuval Mintz out: 9710d956e8aSYuval Mintz return rc; 9720d956e8aSYuval Mintz } 9730d956e8aSYuval Mintz 974ff38577aSYuval Mintz /** 975ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 976ff38577aSYuval Mintz * 977ff38577aSYuval Mintz * @param p_hwfn 978ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 9799790c35eSMintz, Yuval * @param aeu_en_reg - address of the AEU enable register 980ff38577aSYuval Mintz * @param bit_index 981ff38577aSYuval Mintz */ 982ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 983ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9849790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 985ff38577aSYuval Mintz { 9869790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 987ff38577aSYuval Mintz 9889790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 9899790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 9909790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 991ff38577aSYuval Mintz 992ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 9930ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 994ff38577aSYuval Mintz 995ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 996ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 9970ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 9980ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 9990ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 10000ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 1001ff38577aSYuval Mintz } 1002ff38577aSYuval Mintz } 10039790c35eSMintz, Yuval 10049790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 10059790c35eSMintz, Yuval mask = ~BIT(bit_index); 10069790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 10079790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 10089790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 10099790c35eSMintz, Yuval p_aeu->bit_name); 1010ff38577aSYuval Mintz } 1011ff38577aSYuval Mintz 10120d956e8aSYuval Mintz /** 1013cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 1014cc875c2eSYuval Mintz * 1015cc875c2eSYuval Mintz * @param p_hwfn 1016cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 1017cc875c2eSYuval Mintz * @return int 1018cc875c2eSYuval Mintz * 1019cc875c2eSYuval Mintz */ 1020cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 1021cc875c2eSYuval Mintz u16 deasserted_bits) 1022cc875c2eSYuval Mintz { 1023cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 10249790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 10250d956e8aSYuval Mintz u8 i, j, k, bit_idx; 10260d956e8aSYuval Mintz int rc = 0; 1027cc875c2eSYuval Mintz 10280d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 10290d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10300d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 10310d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 10320d956e8aSYuval Mintz i * 0x4); 10330d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 10340d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 10350d956e8aSYuval Mintz i, aeu_inv_arr[i]); 10360d956e8aSYuval Mintz } 10370d956e8aSYuval Mintz 10380d956e8aSYuval Mintz /* Find parity attentions first */ 10390d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10400d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 10410d956e8aSYuval Mintz u32 parities; 10420d956e8aSYuval Mintz 10439790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 10449790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10459790c35eSMintz, Yuval 10460d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 10470d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 10480d956e8aSYuval Mintz if (!parities) 10490d956e8aSYuval Mintz continue; 10500d956e8aSYuval Mintz 10510d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10520d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 10530d956e8aSYuval Mintz 1054ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 10551a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 1056ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 10579790c35eSMintz, Yuval aeu_en, bit_idx); 10580d956e8aSYuval Mintz 10590d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 10600d956e8aSYuval Mintz } 10610d956e8aSYuval Mintz } 10620d956e8aSYuval Mintz 10630d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 10640d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 10650d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 10660d956e8aSYuval Mintz 10670d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 10680d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 10690d956e8aSYuval Mintz continue; 10700d956e8aSYuval Mintz 10710d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10729790c35eSMintz, Yuval u32 bits; 10739790c35eSMintz, Yuval 10749790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 10750d956e8aSYuval Mintz i * sizeof(u32) + 10760d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 10770d956e8aSYuval Mintz 10780d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10790d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 10800d956e8aSYuval Mintz 10810d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 10820d956e8aSYuval Mintz if (!bits) 10830d956e8aSYuval Mintz continue; 10840d956e8aSYuval Mintz 10850d956e8aSYuval Mintz /* Find all set bits from current register which belong 10860d956e8aSYuval Mintz * to current group, making them responsible for the 10870d956e8aSYuval Mintz * previous assertion. 10880d956e8aSYuval Mintz */ 10890d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10906010179dSMintz, Yuval long unsigned int bitmask; 10910d956e8aSYuval Mintz u8 bit, bit_len; 10920d956e8aSYuval Mintz 10930d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1094ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 10950d956e8aSYuval Mintz 10960d956e8aSYuval Mintz bit = bit_idx; 10970d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 1098ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 10990d956e8aSYuval Mintz /* Skip Parity */ 11000d956e8aSYuval Mintz bit++; 11010d956e8aSYuval Mintz bit_len--; 11020d956e8aSYuval Mintz } 11030d956e8aSYuval Mintz 11040d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 11056010179dSMintz, Yuval bitmask >>= bit; 11066010179dSMintz, Yuval 11070d956e8aSYuval Mintz if (bitmask) { 11086010179dSMintz, Yuval u32 flags = p_aeu->flags; 11096010179dSMintz, Yuval char bit_name[30]; 11106010179dSMintz, Yuval u8 num; 11116010179dSMintz, Yuval 11126010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 11136010179dSMintz, Yuval bit_len); 11146010179dSMintz, Yuval 11156010179dSMintz, Yuval /* Some bits represent more than a 11166010179dSMintz, Yuval * a single interrupt. Correctly print 11176010179dSMintz, Yuval * their name. 11186010179dSMintz, Yuval */ 11196010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 11206010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 11216010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 11226010179dSMintz, Yuval snprintf(bit_name, 30, 11236010179dSMintz, Yuval p_aeu->bit_name, num); 11246010179dSMintz, Yuval else 11253690c8c9SWang Xiayang strlcpy(bit_name, 11266010179dSMintz, Yuval p_aeu->bit_name, 30); 11276010179dSMintz, Yuval 11286010179dSMintz, Yuval /* We now need to pass bitmask in its 11296010179dSMintz, Yuval * correct position. 11306010179dSMintz, Yuval */ 11316010179dSMintz, Yuval bitmask <<= bit; 11326010179dSMintz, Yuval 11330d956e8aSYuval Mintz /* Handle source of the attention */ 11340d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 11350d956e8aSYuval Mintz p_aeu, 11360d956e8aSYuval Mintz aeu_en, 11376010179dSMintz, Yuval bit_name, 11380d956e8aSYuval Mintz bitmask); 11390d956e8aSYuval Mintz } 11400d956e8aSYuval Mintz 11410d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 11420d956e8aSYuval Mintz } 11430d956e8aSYuval Mintz } 11440d956e8aSYuval Mintz } 1145cc875c2eSYuval Mintz 1146d4476b8aSDenis Bolotin /* Handle missed DORQ attention */ 1147d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn); 1148d4476b8aSDenis Bolotin 1149cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 1150cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1151cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1152cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1153cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1154cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 1155cc875c2eSYuval Mintz 1156cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 11571a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1158cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1159cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1160cc875c2eSYuval Mintz 1161cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 1162cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 1163cc875c2eSYuval Mintz 11640d956e8aSYuval Mintz return rc; 1165cc875c2eSYuval Mintz } 1166cc875c2eSYuval Mintz 1167cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1168cc875c2eSYuval Mintz { 1169cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1170cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1171cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 1172cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 1173cc875c2eSYuval Mintz __le16 index; 1174cc875c2eSYuval Mintz int rc = 0; 1175cc875c2eSYuval Mintz 1176cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 1177cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 1178cc875c2eSYuval Mintz */ 1179cc875c2eSYuval Mintz do { 1180cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 1181ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 1182ed4eac20SDenis Bolotin dma_rmb(); 1183cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1184cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1185cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1186cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1187cc875c2eSYuval Mintz 1188cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1189cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1190cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1191cc875c2eSYuval Mintz * attention with no previous attention 1192cc875c2eSYuval Mintz */ 1193cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1194cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1195cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1196cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1197cc875c2eSYuval Mintz 1198cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1199cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1200cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1201cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1202cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1203cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 12041d61e218SLaurence Oberman DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 12051d61e218SLaurence Oberman "MFW indication via attention\n"); 1206cc875c2eSYuval Mintz } else { 1207cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1208cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1209cc875c2eSYuval Mintz } 1210cc875c2eSYuval Mintz 1211cc875c2eSYuval Mintz if (asserted_bits) { 1212cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1213cc875c2eSYuval Mintz if (rc) 1214cc875c2eSYuval Mintz return rc; 1215cc875c2eSYuval Mintz } 1216cc875c2eSYuval Mintz 12171a635e48SYuval Mintz if (deasserted_bits) 1218cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1219cc875c2eSYuval Mintz 1220cc875c2eSYuval Mintz return rc; 1221cc875c2eSYuval Mintz } 1222cc875c2eSYuval Mintz 1223cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 12241a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1225cc875c2eSYuval Mintz { 1226cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1227cc875c2eSYuval Mintz 1228cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 1229cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1230cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1231cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1232cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1233cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1234cc875c2eSYuval Mintz 1235cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1236cc875c2eSYuval Mintz 1237cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1238cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1239cc875c2eSYuval Mintz */ 1240cc875c2eSYuval Mintz barrier(); 1241cc875c2eSYuval Mintz } 1242cc875c2eSYuval Mintz 1243fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 1244fe56b9e6SYuval Mintz { 1245fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1246fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1247cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1248fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1249fe56b9e6SYuval Mintz int arr_size; 1250fe56b9e6SYuval Mintz u16 rc = 0; 1251fe56b9e6SYuval Mintz 1252fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1253fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1254fe56b9e6SYuval Mintz return; 1255fe56b9e6SYuval Mintz } 1256fe56b9e6SYuval Mintz 1257fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1258fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1259fe56b9e6SYuval Mintz if (!sb_info) { 1260fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1261fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1262fe56b9e6SYuval Mintz return; 1263fe56b9e6SYuval Mintz } 1264fe56b9e6SYuval Mintz 1265cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1266cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1267cc875c2eSYuval Mintz return; 1268cc875c2eSYuval Mintz } 1269cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1270cc875c2eSYuval Mintz 1271fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1272fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1273fe56b9e6SYuval Mintz 1274fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1275fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1276fe56b9e6SYuval Mintz */ 1277fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1278fe56b9e6SYuval Mintz 1279fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1280fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 12811a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1282fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1283fe56b9e6SYuval Mintz } else { 1284fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1285fe56b9e6SYuval Mintz 1286fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1287fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1288fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1289fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1290fe56b9e6SYuval Mintz } 1291fe56b9e6SYuval Mintz 1292cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 12931a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1294cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1295cc875c2eSYuval Mintz } else { 1296cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1297cc875c2eSYuval Mintz 1298cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1299cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1300cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1301cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1302cc875c2eSYuval Mintz } 1303cc875c2eSYuval Mintz 1304fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1305fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1306fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1307fe56b9e6SYuval Mintz return; 1308fe56b9e6SYuval Mintz } 1309fe56b9e6SYuval Mintz 1310fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1311fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1312fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1313fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1314fe56b9e6SYuval Mintz return; 1315fe56b9e6SYuval Mintz } 1316fe56b9e6SYuval Mintz 1317cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1318cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1319cc875c2eSYuval Mintz 1320fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1321fe56b9e6SYuval Mintz int pi; 1322fe56b9e6SYuval Mintz 1323fe56b9e6SYuval Mintz /* Look for a free index */ 1324fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1325fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1326fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1327fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1328fe56b9e6SYuval Mintz } 1329fe56b9e6SYuval Mintz } 1330fe56b9e6SYuval Mintz 1331cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1332cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1333cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1334cc875c2eSYuval Mintz */ 1335cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1336cc875c2eSYuval Mintz 1337fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1338fe56b9e6SYuval Mintz } 1339fe56b9e6SYuval Mintz 1340cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1341cc875c2eSYuval Mintz { 1342cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1343cc875c2eSYuval Mintz 13444ac801b7SYuval Mintz if (!p_sb) 13454ac801b7SYuval Mintz return; 13464ac801b7SYuval Mintz 1347cc875c2eSYuval Mintz if (p_sb->sb_attn) 13484ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1349cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 13501a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1351cc875c2eSYuval Mintz kfree(p_sb); 13523587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1353cc875c2eSYuval Mintz } 1354cc875c2eSYuval Mintz 1355cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1356cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1357cc875c2eSYuval Mintz { 1358cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1359cc875c2eSYuval Mintz 1360cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1361cc875c2eSYuval Mintz 1362cc875c2eSYuval Mintz sb_info->index = 0; 1363cc875c2eSYuval Mintz sb_info->known_attn = 0; 1364cc875c2eSYuval Mintz 1365cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1366cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1367cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1368cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1369cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1370cc875c2eSYuval Mintz } 1371cc875c2eSYuval Mintz 1372cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1373cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 13741a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1375cc875c2eSYuval Mintz { 1376cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 13770d956e8aSYuval Mintz int i, j, k; 1378cc875c2eSYuval Mintz 1379cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1380cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1381cc875c2eSYuval Mintz 13820d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 13830d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 13840d956e8aSYuval Mintz 13850d956e8aSYuval Mintz /* Calculate Parity Masks */ 13860d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 13870d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 13880d956e8aSYuval Mintz /* j is array index, k is bit index */ 13890d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1390ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 13910d956e8aSYuval Mintz 1392ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1393ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 13940d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 13950d956e8aSYuval Mintz 1396ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 13970d956e8aSYuval Mintz } 13980d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 13990d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 14000d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 14010d956e8aSYuval Mintz } 14020d956e8aSYuval Mintz 1403cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1404cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1405cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1406cc875c2eSYuval Mintz 1407cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1408cc875c2eSYuval Mintz } 1409cc875c2eSYuval Mintz 1410cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1411cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1412cc875c2eSYuval Mintz { 1413cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1414cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1415cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 14161a635e48SYuval Mintz void *p_virt; 1417cc875c2eSYuval Mintz 1418cc875c2eSYuval Mintz /* SB struct */ 141960fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 14202591c280SJoe Perches if (!p_sb) 1421cc875c2eSYuval Mintz return -ENOMEM; 1422cc875c2eSYuval Mintz 1423cc875c2eSYuval Mintz /* SB ring */ 1424cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1425cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1426cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1427cc875c2eSYuval Mintz 1428cc875c2eSYuval Mintz if (!p_virt) { 1429cc875c2eSYuval Mintz kfree(p_sb); 1430cc875c2eSYuval Mintz return -ENOMEM; 1431cc875c2eSYuval Mintz } 1432cc875c2eSYuval Mintz 1433cc875c2eSYuval Mintz /* Attention setup */ 1434cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1435cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1436cc875c2eSYuval Mintz 1437cc875c2eSYuval Mintz return 0; 1438cc875c2eSYuval Mintz } 1439cc875c2eSYuval Mintz 1440fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1441fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1442fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1443fe56b9e6SYuval Mintz 1444fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1445fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 14461a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1447fe56b9e6SYuval Mintz { 14484ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1449fe56b9e6SYuval Mintz u32 cau_state; 1450722003acSSudarsana Reddy Kalluru u8 timer_res; 1451fe56b9e6SYuval Mintz 1452fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1453fe56b9e6SYuval Mintz 1454fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1455fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1456fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1457fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1458fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1459fe56b9e6SYuval Mintz 1460fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1461fe56b9e6SYuval Mintz 14624ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1463fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 14644ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 14654ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 14664ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 14674ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1468fe56b9e6SYuval Mintz } 1469fe56b9e6SYuval Mintz 1470722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1471722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1472722003acSSudarsana Reddy Kalluru timer_res = 0; 1473722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1474722003acSSudarsana Reddy Kalluru timer_res = 1; 1475722003acSSudarsana Reddy Kalluru else 1476722003acSSudarsana Reddy Kalluru timer_res = 2; 1477722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1478722003acSSudarsana Reddy Kalluru 1479722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1480722003acSSudarsana Reddy Kalluru timer_res = 0; 1481722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1482722003acSSudarsana Reddy Kalluru timer_res = 1; 1483722003acSSudarsana Reddy Kalluru else 1484722003acSSudarsana Reddy Kalluru timer_res = 2; 1485722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1486722003acSSudarsana Reddy Kalluru 1487fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1488fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1489fe56b9e6SYuval Mintz } 1490fe56b9e6SYuval Mintz 14918befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 14928befd73cSMintz, Yuval struct qed_ptt *p_ptt, 14938befd73cSMintz, Yuval u16 igu_sb_id, 14948befd73cSMintz, Yuval u32 pi_index, 14958befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 14968befd73cSMintz, Yuval u8 timeset) 14978befd73cSMintz, Yuval { 14988befd73cSMintz, Yuval struct cau_pi_entry pi_entry; 14998befd73cSMintz, Yuval u32 sb_offset, pi_offset; 15008befd73cSMintz, Yuval 15018befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 15028befd73cSMintz, Yuval return; 15038befd73cSMintz, Yuval 150421dd79e8STomer Tayar sb_offset = igu_sb_id * PIS_PER_SB_E4; 15058befd73cSMintz, Yuval memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 15068befd73cSMintz, Yuval 15078befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 15088befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 15098befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 15108befd73cSMintz, Yuval else 15118befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 15128befd73cSMintz, Yuval 15138befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 15148befd73cSMintz, Yuval if (p_hwfn->hw_init_done) { 15158befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 15168befd73cSMintz, Yuval CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 15178befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 15188befd73cSMintz, Yuval } else { 15198befd73cSMintz, Yuval STORE_RT_REG(p_hwfn, 15208befd73cSMintz, Yuval CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 15218befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 15228befd73cSMintz, Yuval } 15238befd73cSMintz, Yuval } 15248befd73cSMintz, Yuval 1525fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1526fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1527fe56b9e6SYuval Mintz dma_addr_t sb_phys, 15281a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1529fe56b9e6SYuval Mintz { 1530fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1531fe56b9e6SYuval Mintz 1532fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1533fe56b9e6SYuval Mintz vf_number, vf_valid); 1534fe56b9e6SYuval Mintz 1535fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 15360a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 15370a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1538fe56b9e6SYuval Mintz 15390a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 15400a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 154183bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 15420a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 15430a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 154483bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 1545fe56b9e6SYuval Mintz } else { 1546fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1547fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1548fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1549fe56b9e6SYuval Mintz igu_sb_id * 2, 1550fe56b9e6SYuval Mintz sb_phys); 1551fe56b9e6SYuval Mintz 1552fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1553fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1554fe56b9e6SYuval Mintz igu_sb_id * 2, 1555fe56b9e6SYuval Mintz sb_entry); 1556fe56b9e6SYuval Mintz } 1557fe56b9e6SYuval Mintz 1558fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1559fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1560b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1561722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1562b5a9ee7cSAriel Elior u8 i; 1563fe56b9e6SYuval Mintz 1564722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1565722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1566722003acSSudarsana Reddy Kalluru timer_res = 0; 1567722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1568722003acSSudarsana Reddy Kalluru timer_res = 1; 1569722003acSSudarsana Reddy Kalluru else 1570722003acSSudarsana Reddy Kalluru timer_res = 2; 1571722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1572fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 15731a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1574fe56b9e6SYuval Mintz 1575722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1576722003acSSudarsana Reddy Kalluru timer_res = 0; 1577722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1578722003acSSudarsana Reddy Kalluru timer_res = 1; 1579722003acSSudarsana Reddy Kalluru else 1580722003acSSudarsana Reddy Kalluru timer_res = 2; 1581722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1582fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1583fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1584fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1585fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1586fe56b9e6SYuval Mintz timeset); 1587fe56b9e6SYuval Mintz } 1588fe56b9e6SYuval Mintz } 1589fe56b9e6SYuval Mintz } 1590fe56b9e6SYuval Mintz 1591fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 15921a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1593fe56b9e6SYuval Mintz { 1594fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1595fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1596fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1597fe56b9e6SYuval Mintz 15981408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1599fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1600fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1601fe56b9e6SYuval Mintz } 1602fe56b9e6SYuval Mintz 160309b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 160409b6b147SMintz, Yuval { 160509b6b147SMintz, Yuval struct qed_igu_block *p_block; 160609b6b147SMintz, Yuval u16 igu_id; 160709b6b147SMintz, Yuval 160809b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 160909b6b147SMintz, Yuval igu_id++) { 161009b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 161109b6b147SMintz, Yuval 161209b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 161309b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 161409b6b147SMintz, Yuval continue; 161509b6b147SMintz, Yuval 161609b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 161709b6b147SMintz, Yuval return p_block; 161809b6b147SMintz, Yuval } 161909b6b147SMintz, Yuval 162009b6b147SMintz, Yuval return NULL; 162109b6b147SMintz, Yuval } 162209b6b147SMintz, Yuval 1623a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1624a333f7f3SMintz, Yuval { 1625a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1626a333f7f3SMintz, Yuval u16 igu_id; 1627a333f7f3SMintz, Yuval 1628a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1629a333f7f3SMintz, Yuval igu_id++) { 1630a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1631a333f7f3SMintz, Yuval 1632a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1633a333f7f3SMintz, Yuval !p_block->is_pf || 1634a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1635a333f7f3SMintz, Yuval continue; 1636a333f7f3SMintz, Yuval 1637a333f7f3SMintz, Yuval return igu_id; 1638a333f7f3SMintz, Yuval } 1639a333f7f3SMintz, Yuval 1640a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1641a333f7f3SMintz, Yuval } 1642a333f7f3SMintz, Yuval 164350a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1644fe56b9e6SYuval Mintz { 1645fe56b9e6SYuval Mintz u16 igu_sb_id; 1646fe56b9e6SYuval Mintz 1647fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1648fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1649fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 16501408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1651a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 16521408cc1fSYuval Mintz else 16531408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1654fe56b9e6SYuval Mintz 1655525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1656525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1657525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1658525ef5c0SYuval Mintz else 1659525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1660525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1661fe56b9e6SYuval Mintz 1662fe56b9e6SYuval Mintz return igu_sb_id; 1663fe56b9e6SYuval Mintz } 1664fe56b9e6SYuval Mintz 1665fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1666fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1667fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 16681a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1669fe56b9e6SYuval Mintz { 1670fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1671fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1672fe56b9e6SYuval Mintz 1673fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1674fe56b9e6SYuval Mintz 1675fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 167650a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 167750a20714SMintz, Yuval struct qed_igu_info *p_info; 167850a20714SMintz, Yuval struct qed_igu_block *p_block; 167950a20714SMintz, Yuval 168050a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 168150a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 168250a20714SMintz, Yuval 168350a20714SMintz, Yuval p_block->sb_info = sb_info; 168450a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 168550a20714SMintz, Yuval p_info->usage.free_cnt--; 168650a20714SMintz, Yuval } else { 168750a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 168850a20714SMintz, Yuval } 1689fe56b9e6SYuval Mintz } 1690fe56b9e6SYuval Mintz 1691fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1692fe56b9e6SYuval Mintz 1693fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1694fe56b9e6SYuval Mintz * written to for a specific status block 1695fe56b9e6SYuval Mintz */ 16961408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1697fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1698fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1699fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 17001408cc1fSYuval Mintz } else { 17011408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 17021408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 17031408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 17041408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 17051408cc1fSYuval Mintz } 1706fe56b9e6SYuval Mintz 1707fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1708fe56b9e6SYuval Mintz 1709fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1710fe56b9e6SYuval Mintz 1711fe56b9e6SYuval Mintz return 0; 1712fe56b9e6SYuval Mintz } 1713fe56b9e6SYuval Mintz 1714fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 17151a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1716fe56b9e6SYuval Mintz { 171750a20714SMintz, Yuval struct qed_igu_block *p_block; 171850a20714SMintz, Yuval struct qed_igu_info *p_info; 171950a20714SMintz, Yuval 172050a20714SMintz, Yuval if (!sb_info) 172150a20714SMintz, Yuval return 0; 1722fe56b9e6SYuval Mintz 1723fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1724fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1725fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1726fe56b9e6SYuval Mintz 172750a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 172850a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 172950a20714SMintz, Yuval return 0; 17304ac801b7SYuval Mintz } 1731fe56b9e6SYuval Mintz 173250a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 173350a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 173450a20714SMintz, Yuval 173550a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 173650a20714SMintz, Yuval if (!p_block->vector_number) { 173750a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 173850a20714SMintz, Yuval return -EINVAL; 173950a20714SMintz, Yuval } 174050a20714SMintz, Yuval 174150a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 174250a20714SMintz, Yuval p_block->sb_info = NULL; 174350a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 174450a20714SMintz, Yuval p_info->usage.free_cnt++; 174550a20714SMintz, Yuval 1746fe56b9e6SYuval Mintz return 0; 1747fe56b9e6SYuval Mintz } 1748fe56b9e6SYuval Mintz 1749fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1750fe56b9e6SYuval Mintz { 1751fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1752fe56b9e6SYuval Mintz 17534ac801b7SYuval Mintz if (!p_sb) 17544ac801b7SYuval Mintz return; 17554ac801b7SYuval Mintz 1756fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1757fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1758fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1759fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1760fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1761fe56b9e6SYuval Mintz kfree(p_sb); 17623587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1763fe56b9e6SYuval Mintz } 1764fe56b9e6SYuval Mintz 17651a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1766fe56b9e6SYuval Mintz { 1767fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1768fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1769fe56b9e6SYuval Mintz void *p_virt; 1770fe56b9e6SYuval Mintz 1771fe56b9e6SYuval Mintz /* SB struct */ 177260fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 17732591c280SJoe Perches if (!p_sb) 1774fe56b9e6SYuval Mintz return -ENOMEM; 1775fe56b9e6SYuval Mintz 1776fe56b9e6SYuval Mintz /* SB ring */ 1777fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1778fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1779fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1780fe56b9e6SYuval Mintz if (!p_virt) { 1781fe56b9e6SYuval Mintz kfree(p_sb); 1782fe56b9e6SYuval Mintz return -ENOMEM; 1783fe56b9e6SYuval Mintz } 1784fe56b9e6SYuval Mintz 1785fe56b9e6SYuval Mintz /* Status Block setup */ 1786fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1787fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1788fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1789fe56b9e6SYuval Mintz 1790fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1791fe56b9e6SYuval Mintz 1792fe56b9e6SYuval Mintz return 0; 1793fe56b9e6SYuval Mintz } 1794fe56b9e6SYuval Mintz 1795fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1796fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 17971a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1798fe56b9e6SYuval Mintz { 1799fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 18004ac801b7SYuval Mintz int rc = -ENOMEM; 1801fe56b9e6SYuval Mintz u8 pi; 1802fe56b9e6SYuval Mintz 1803fe56b9e6SYuval Mintz /* Look for a free index */ 1804fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 18054ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 18064ac801b7SYuval Mintz continue; 18074ac801b7SYuval Mintz 1808fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1809fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1810fe56b9e6SYuval Mintz *sb_idx = pi; 1811fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 18124ac801b7SYuval Mintz rc = 0; 1813fe56b9e6SYuval Mintz break; 1814fe56b9e6SYuval Mintz } 1815fe56b9e6SYuval Mintz 18164ac801b7SYuval Mintz return rc; 1817fe56b9e6SYuval Mintz } 1818fe56b9e6SYuval Mintz 1819fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1820fe56b9e6SYuval Mintz { 1821fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1822fe56b9e6SYuval Mintz 18234ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 18244ac801b7SYuval Mintz return -ENOMEM; 18254ac801b7SYuval Mintz 1826fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1827fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1828fe56b9e6SYuval Mintz 18294ac801b7SYuval Mintz return 0; 1830fe56b9e6SYuval Mintz } 1831fe56b9e6SYuval Mintz 1832fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1833fe56b9e6SYuval Mintz { 1834fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1835fe56b9e6SYuval Mintz } 1836fe56b9e6SYuval Mintz 1837fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 18381a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1839fe56b9e6SYuval Mintz { 1840cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1841fe56b9e6SYuval Mintz 1842fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1843fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1844fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1845fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1846fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1847fe56b9e6SYuval Mintz break; 1848fe56b9e6SYuval Mintz 1849fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1850fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1851fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1852fe56b9e6SYuval Mintz break; 1853fe56b9e6SYuval Mintz 1854fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1855fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1856fe56b9e6SYuval Mintz break; 1857fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1858fe56b9e6SYuval Mintz break; 1859fe56b9e6SYuval Mintz } 1860fe56b9e6SYuval Mintz 1861fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1862fe56b9e6SYuval Mintz } 1863fe56b9e6SYuval Mintz 1864979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1865979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1866fe56b9e6SYuval Mintz { 1867fe56b9e6SYuval Mintz 18680d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 18690d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1870cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1871cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 18720d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1873cc875c2eSYuval Mintz 1874cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1875cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1876979cead3SMintz, Yuval } 1877979cead3SMintz, Yuval 1878979cead3SMintz, Yuval int 1879979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1880979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1881979cead3SMintz, Yuval { 1882979cead3SMintz, Yuval int rc = 0; 1883979cead3SMintz, Yuval 1884979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1885979cead3SMintz, Yuval 18868f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 18878f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 18881a635e48SYuval Mintz if (rc) { 18898f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 18908f16bc97SSudarsana Kalluru return -EINVAL; 18918f16bc97SSudarsana Kalluru } 18928f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 18938f16bc97SSudarsana Kalluru } 18948f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 18958f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 18968f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 18978f16bc97SSudarsana Kalluru 18988f16bc97SSudarsana Kalluru return rc; 1899fe56b9e6SYuval Mintz } 1900fe56b9e6SYuval Mintz 19011a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1902fe56b9e6SYuval Mintz { 1903fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1904fe56b9e6SYuval Mintz 19051408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 19061408cc1fSYuval Mintz return; 19071408cc1fSYuval Mintz 1908fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1909fe56b9e6SYuval Mintz } 1910fe56b9e6SYuval Mintz 1911fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1912b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1913fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1914d031548eSMintz, Yuval u16 igu_sb_id, 1915d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1916fe56b9e6SYuval Mintz { 1917b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1918d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1919fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1920fe56b9e6SYuval Mintz 1921fe56b9e6SYuval Mintz /* Set the data field */ 1922fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1923fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1924fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1925fe56b9e6SYuval Mintz 1926fe56b9e6SYuval Mintz /* Set the control register */ 1927fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1928fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1929fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1930fe56b9e6SYuval Mintz 1931fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1932fe56b9e6SYuval Mintz 1933fe56b9e6SYuval Mintz barrier(); 1934fe56b9e6SYuval Mintz 1935fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1936fe56b9e6SYuval Mintz 1937fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1938d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1939d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1940fe56b9e6SYuval Mintz 1941fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1942fe56b9e6SYuval Mintz 1943fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1944fe56b9e6SYuval Mintz do { 1945fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1946fe56b9e6SYuval Mintz 1947fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1948fe56b9e6SYuval Mintz break; 1949fe56b9e6SYuval Mintz 1950fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1951fe56b9e6SYuval Mintz } while (--sleep_cnt); 1952fe56b9e6SYuval Mintz 1953fe56b9e6SYuval Mintz if (!sleep_cnt) 1954fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1955fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1956d031548eSMintz, Yuval val, igu_sb_id); 1957fe56b9e6SYuval Mintz } 1958fe56b9e6SYuval Mintz 1959fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1960fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1961d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1962fe56b9e6SYuval Mintz { 19631ac72433SMintz, Yuval struct qed_igu_block *p_block; 1964b2b897ebSYuval Mintz int pi, i; 1965fe56b9e6SYuval Mintz 19661ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 19671ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 19681ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 19691ac72433SMintz, Yuval igu_sb_id, 19701ac72433SMintz, Yuval p_block->function_id, 19711ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 19721ac72433SMintz, Yuval 1973fe56b9e6SYuval Mintz /* Set */ 1974fe56b9e6SYuval Mintz if (b_set) 1975d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1976fe56b9e6SYuval Mintz 1977fe56b9e6SYuval Mintz /* Clear */ 1978d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1979fe56b9e6SYuval Mintz 1980b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1981b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1982b2b897ebSYuval Mintz u32 val; 1983b2b897ebSYuval Mintz 1984b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1985d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1986d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1987d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1988b2b897ebSYuval Mintz usleep_range(10, 20); 1989b2b897ebSYuval Mintz else 1990b2b897ebSYuval Mintz break; 1991b2b897ebSYuval Mintz } 1992b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1993b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1994b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1995d031548eSMintz, Yuval igu_sb_id); 1996b2b897ebSYuval Mintz 1997fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1998fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1999fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 2000d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 2001fe56b9e6SYuval Mintz } 2002fe56b9e6SYuval Mintz 2003fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 2004fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2005b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 2006fe56b9e6SYuval Mintz { 20071ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 20081ac72433SMintz, Yuval struct qed_igu_block *p_block; 20091ac72433SMintz, Yuval u16 igu_sb_id = 0; 20101ac72433SMintz, Yuval u32 val = 0; 2011fe56b9e6SYuval Mintz 2012fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 2013fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 2014fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 2015fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 2016fe56b9e6SYuval Mintz 20171ac72433SMintz, Yuval for (igu_sb_id = 0; 20181ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 20191ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2020fe56b9e6SYuval Mintz 20211ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 20221ac72433SMintz, Yuval !p_block->is_pf || 20231ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 20241ac72433SMintz, Yuval continue; 20251ac72433SMintz, Yuval 2026d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 2027fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 2028fe56b9e6SYuval Mintz b_set); 20291ac72433SMintz, Yuval } 2030fe56b9e6SYuval Mintz 20311ac72433SMintz, Yuval if (b_slowpath) 20321ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 20331ac72433SMintz, Yuval p_info->igu_dsb_id, 20341ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 20351ac72433SMintz, Yuval b_set); 2036fe56b9e6SYuval Mintz } 2037fe56b9e6SYuval Mintz 2038ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2039ebbdcc66SMintz, Yuval { 2040ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2041ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 2042ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 2043ebbdcc66SMintz, Yuval u16 igu_sb_id; 2044ebbdcc66SMintz, Yuval u32 val, rval; 2045ebbdcc66SMintz, Yuval 2046ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 2047ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 2048ebbdcc66SMintz, Yuval } else { 2049ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 2050ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 2051ebbdcc66SMintz, Yuval */ 2052ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 2053ebbdcc66SMintz, Yuval 2054ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2055ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 2056ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2057ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 2058ebbdcc66SMintz, Yuval p_info->usage.cnt); 2059ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2060ebbdcc66SMintz, Yuval } 2061ebbdcc66SMintz, Yuval 2062ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 2063ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2064ebbdcc66SMintz, Yuval 2065ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 2066ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2067ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2068ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2069ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 2070ebbdcc66SMintz, Yuval 2071ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 2072ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 2073ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 2074ebbdcc66SMintz, Yuval */ 2075ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 2076ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2077ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 2078ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2079ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 2080ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 2081ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 2082ebbdcc66SMintz, Yuval return -EINVAL; 2083ebbdcc66SMintz, Yuval } 2084ebbdcc66SMintz, Yuval 2085ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 2086ebbdcc66SMintz, Yuval * number of VFs. 2087ebbdcc66SMintz, Yuval */ 2088ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 2089ebbdcc66SMintz, Yuval } 2090ebbdcc66SMintz, Yuval } 2091ebbdcc66SMintz, Yuval 2092ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 2093ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 2094ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2095ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 2096ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 2097ebbdcc66SMintz, Yuval 2098ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 2099ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 2100ebbdcc66SMintz, Yuval */ 2101ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 2102ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 2103ebbdcc66SMintz, Yuval 2104ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 2105ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2106ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2107ebbdcc66SMintz, Yuval val = 0; 2108ebbdcc66SMintz, Yuval 2109ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 2110ebbdcc66SMintz, Yuval continue; 2111ebbdcc66SMintz, Yuval 2112ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 2113ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2114ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2115ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2116ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2117ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2118ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 2119ebbdcc66SMintz, Yuval } else if (pf_sbs) { 2120ebbdcc66SMintz, Yuval pf_sbs--; 2121ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2122ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2123ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 2124ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2125ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2126ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2127ebbdcc66SMintz, Yuval } else if (vf_sbs) { 2128ebbdcc66SMintz, Yuval p_block->function_id = 2129ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2130ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 2131ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2132ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2133ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2134ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2135ebbdcc66SMintz, Yuval vf_sbs--; 2136ebbdcc66SMintz, Yuval } else { 2137ebbdcc66SMintz, Yuval p_block->function_id = 0; 2138ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2139ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2140ebbdcc66SMintz, Yuval } 2141ebbdcc66SMintz, Yuval 2142ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2143ebbdcc66SMintz, Yuval p_block->function_id); 2144ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2145ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2146ebbdcc66SMintz, Yuval p_block->vector_number); 2147ebbdcc66SMintz, Yuval 2148ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 2149ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2150ebbdcc66SMintz, Yuval 2151ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 2152ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2153ebbdcc66SMintz, Yuval 2154ebbdcc66SMintz, Yuval if (rval != val) { 2155ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 2156ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 2157ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 2158ebbdcc66SMintz, Yuval 2159ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2160ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2161ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2162ebbdcc66SMintz, Yuval igu_sb_id, 2163ebbdcc66SMintz, Yuval p_block->function_id, 2164ebbdcc66SMintz, Yuval p_block->is_pf, 2165ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 2166ebbdcc66SMintz, Yuval } 2167ebbdcc66SMintz, Yuval } 2168ebbdcc66SMintz, Yuval 2169ebbdcc66SMintz, Yuval return 0; 2170ebbdcc66SMintz, Yuval } 2171ebbdcc66SMintz, Yuval 2172d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2173d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 21744ac801b7SYuval Mintz { 21754ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 2176d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 21774ac801b7SYuval Mintz struct qed_igu_block *p_block; 21784ac801b7SYuval Mintz 2179d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 21804ac801b7SYuval Mintz 21814ac801b7SYuval Mintz /* Fill the block information */ 2182d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 21834ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2184d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 21851ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 21864ac801b7SYuval Mintz } 21874ac801b7SYuval Mintz 21881a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2189fe56b9e6SYuval Mintz { 2190fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2191d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2192d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2193d749dd0dSMintz, Yuval u16 igu_sb_id; 2194fe56b9e6SYuval Mintz 219560fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2196fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2197fe56b9e6SYuval Mintz return -ENOMEM; 2198fe56b9e6SYuval Mintz 2199fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2200fe56b9e6SYuval Mintz 2201d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2202d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2203d749dd0dSMintz, Yuval 2204d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 22051408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 22061408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 22071408cc1fSYuval Mintz 22081408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 22091408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 22101408cc1fSYuval Mintz } 22111408cc1fSYuval Mintz 2212d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2213d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2214d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2215d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2216d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2217fe56b9e6SYuval Mintz 2218d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2219d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2220d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2221d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2222d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2223fe56b9e6SYuval Mintz 22241ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2225726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2226d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2227d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2228d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 22291408cc1fSYuval Mintz /* Available for VFs of this PF */ 2230d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2231d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2232d749dd0dSMintz, Yuval 22331ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2234726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 22351408cc1fSYuval Mintz } 22365a1f965aSMintz, Yuval 2237d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2238ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 22395a1f965aSMintz, Yuval */ 2240d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2241d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2242d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2243d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2244d749dd0dSMintz, Yuval } 22455a1f965aSMintz, Yuval 2246d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2247d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2248d749dd0dSMintz, Yuval * everything. 2249d749dd0dSMintz, Yuval */ 2250d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2251d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2252d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2253d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2254d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2255d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2256d749dd0dSMintz, Yuval } 2257d749dd0dSMintz, Yuval } 2258d749dd0dSMintz, Yuval 2259d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 22605a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2261d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2262d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 22635a1f965aSMintz, Yuval return -EINVAL; 22645a1f965aSMintz, Yuval } 2265d749dd0dSMintz, Yuval 2266d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2267726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2268726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2269fe56b9e6SYuval Mintz 2270d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2271ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2272d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2273726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2274fe56b9e6SYuval Mintz 2275fe56b9e6SYuval Mintz return 0; 2276fe56b9e6SYuval Mintz } 2277fe56b9e6SYuval Mintz 2278fe56b9e6SYuval Mintz /** 2279fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 2280fe56b9e6SYuval Mintz * 2281fe56b9e6SYuval Mintz * @param p_hwfn 2282fe56b9e6SYuval Mintz */ 2283fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2284fe56b9e6SYuval Mintz { 22851a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2286fe56b9e6SYuval Mintz 2287fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2288fe56b9e6SYuval Mintz } 2289fe56b9e6SYuval Mintz 2290fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2291fe56b9e6SYuval Mintz { 2292fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2293fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2294fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2295fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 22961a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 22971a635e48SYuval Mintz u64 intr_status = 0; 2298fe56b9e6SYuval Mintz 2299fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2300fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2301fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2302fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2303fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2304fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2305fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2306fe56b9e6SYuval Mintz 2307fe56b9e6SYuval Mintz return intr_status; 2308fe56b9e6SYuval Mintz } 2309fe56b9e6SYuval Mintz 2310fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2311fe56b9e6SYuval Mintz { 2312fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 2313fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 2314fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2315fe56b9e6SYuval Mintz } 2316fe56b9e6SYuval Mintz 2317fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2318fe56b9e6SYuval Mintz { 231960fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2320fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 2321fe56b9e6SYuval Mintz return -ENOMEM; 2322fe56b9e6SYuval Mintz 2323fe56b9e6SYuval Mintz return 0; 2324fe56b9e6SYuval Mintz } 2325fe56b9e6SYuval Mintz 2326fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2327fe56b9e6SYuval Mintz { 2328fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 23293587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 2330fe56b9e6SYuval Mintz } 2331fe56b9e6SYuval Mintz 23321a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2333fe56b9e6SYuval Mintz { 2334fe56b9e6SYuval Mintz int rc = 0; 2335fe56b9e6SYuval Mintz 2336fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 233783aeb933SYuval Mintz if (rc) 23382591c280SJoe Perches return rc; 23392591c280SJoe Perches 23402591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 23412591c280SJoe Perches if (rc) 23422591c280SJoe Perches return rc; 23432591c280SJoe Perches 23442591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 234583aeb933SYuval Mintz 2346fe56b9e6SYuval Mintz return rc; 2347fe56b9e6SYuval Mintz } 2348fe56b9e6SYuval Mintz 2349fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2350fe56b9e6SYuval Mintz { 2351fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2352cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2353fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 2354fe56b9e6SYuval Mintz } 2355fe56b9e6SYuval Mintz 23561a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2357fe56b9e6SYuval Mintz { 23580d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 23590d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2360fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2361fe56b9e6SYuval Mintz } 2362fe56b9e6SYuval Mintz 23634ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 23644ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2365fe56b9e6SYuval Mintz { 2366fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2367fe56b9e6SYuval Mintz 23684ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 23694ac801b7SYuval Mintz return; 2370fe56b9e6SYuval Mintz 2371726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2372fe56b9e6SYuval Mintz } 23738f16bc97SSudarsana Kalluru 23748f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 23758f16bc97SSudarsana Kalluru { 23768f16bc97SSudarsana Kalluru int i; 23778f16bc97SSudarsana Kalluru 23788f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 23798f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 23808f16bc97SSudarsana Kalluru } 2381722003acSSudarsana Reddy Kalluru 2382936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable) 2383936c7ba4SIgor Russkikh { 2384936c7ba4SIgor Russkikh cdev->attn_clr_en = clr_enable; 2385936c7ba4SIgor Russkikh } 2386936c7ba4SIgor Russkikh 2387722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2388722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2389722003acSSudarsana Reddy Kalluru { 2390722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 2391722003acSSudarsana Reddy Kalluru int rc; 2392722003acSSudarsana Reddy Kalluru 2393722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2394722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2395722003acSSudarsana Reddy Kalluru return -EINVAL; 2396722003acSSudarsana Reddy Kalluru } 2397722003acSSudarsana Reddy Kalluru 2398722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2399722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 240083bf76e3SMichal Kalderon (u64)(uintptr_t)&sb_entry, 2, NULL); 2401722003acSSudarsana Reddy Kalluru if (rc) { 2402722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2403722003acSSudarsana Reddy Kalluru return rc; 2404722003acSSudarsana Reddy Kalluru } 2405722003acSSudarsana Reddy Kalluru 2406722003acSSudarsana Reddy Kalluru if (tx) 2407722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2408722003acSSudarsana Reddy Kalluru else 2409722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2410722003acSSudarsana Reddy Kalluru 2411722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2412722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2413722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 241483bf76e3SMichal Kalderon sb_id * sizeof(u64), 2, NULL); 2415722003acSSudarsana Reddy Kalluru if (rc) { 2416722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2417722003acSSudarsana Reddy Kalluru return rc; 2418722003acSSudarsana Reddy Kalluru } 2419722003acSSudarsana Reddy Kalluru 2420722003acSSudarsana Reddy Kalluru return rc; 2421722003acSSudarsana Reddy Kalluru } 2422