1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/bitops.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 39fe56b9e6SYuval Mintz #include <linux/errno.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/kernel.h> 42fe56b9e6SYuval Mintz #include <linux/pci.h> 43fe56b9e6SYuval Mintz #include <linux/slab.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include "qed.h" 46fe56b9e6SYuval Mintz #include "qed_hsi.h" 47fe56b9e6SYuval Mintz #include "qed_hw.h" 48fe56b9e6SYuval Mintz #include "qed_init_ops.h" 49fe56b9e6SYuval Mintz #include "qed_int.h" 50fe56b9e6SYuval Mintz #include "qed_mcp.h" 51fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 52fe56b9e6SYuval Mintz #include "qed_sp.h" 531408cc1fSYuval Mintz #include "qed_sriov.h" 541408cc1fSYuval Mintz #include "qed_vf.h" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz struct qed_pi_info { 57fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 58fe56b9e6SYuval Mintz void *cookie; 59fe56b9e6SYuval Mintz }; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz struct qed_sb_sp_info { 62fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz /* per protocol index data */ 6521dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 66fe56b9e6SYuval Mintz }; 67fe56b9e6SYuval Mintz 68ff38577aSYuval Mintz enum qed_attention_type { 69ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 70ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 71ff38577aSYuval Mintz }; 72ff38577aSYuval Mintz 73cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75cc875c2eSYuval Mintz 760d956e8aSYuval Mintz struct aeu_invert_reg_bit { 770d956e8aSYuval Mintz char bit_name[30]; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 820d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 830d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 840d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 85a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 860d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 870d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 880d956e8aSYuval Mintz ATTENTION_PARITY) 890d956e8aSYuval Mintz 900d956e8aSYuval Mintz /* Multiple bits start with this offset */ 910d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 920d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 93ba36f718SMintz, Yuval 94ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 95ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 96ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 97ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 98ba36f718SMintz, Yuval 990d956e8aSYuval Mintz unsigned int flags; 100ff38577aSYuval Mintz 101b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 102b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 103b4149dc7SYuval Mintz 104ff38577aSYuval Mintz enum block_id block_index; 1050d956e8aSYuval Mintz }; 1060d956e8aSYuval Mintz 1070d956e8aSYuval Mintz struct aeu_invert_reg { 1080d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 1090d956e8aSYuval Mintz }; 1100d956e8aSYuval Mintz 1110d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 1120d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 1130d956e8aSYuval Mintz 114b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 115b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 116b4149dc7SYuval Mintz { 117b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 118b4149dc7SYuval Mintz 119b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 120b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 121b4149dc7SYuval Mintz tmp); 122b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 123b4149dc7SYuval Mintz 0xffffffff); 124b4149dc7SYuval Mintz 125b4149dc7SYuval Mintz return 0; 126b4149dc7SYuval Mintz } 127b4149dc7SYuval Mintz 128b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 129b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 130b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 131b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 132b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 133b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 134b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 135b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 136b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 137b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 138b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 139b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 140b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 141b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 142b4149dc7SYuval Mintz { 143b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 144b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 145b4149dc7SYuval Mintz 146b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 147b4149dc7SYuval Mintz u32 addr, data, length; 148b4149dc7SYuval Mintz 149b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 150b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 151b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 152b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 153b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 154b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 155b4149dc7SYuval Mintz 156b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 157b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 158b4149dc7SYuval Mintz addr, length, 159b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 160b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 161b4149dc7SYuval Mintz (u8) GET_FIELD(data, 162b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 163b4149dc7SYuval Mintz (u8) GET_FIELD(data, 164b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 165b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 166b4149dc7SYuval Mintz (u8) GET_FIELD(data, 167b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 168b4149dc7SYuval Mintz data); 169b4149dc7SYuval Mintz } 170b4149dc7SYuval Mintz 171b4149dc7SYuval Mintz return 0; 172b4149dc7SYuval Mintz } 173b4149dc7SYuval Mintz 174b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 175b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 176b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 177b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 178b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 179b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 180b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 181b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 182b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 183b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 184b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 185b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 186b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 187b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 188b4149dc7SYuval Mintz { 189b4149dc7SYuval Mintz switch (master) { 190b4149dc7SYuval Mintz case 1: return "PXP"; 191b4149dc7SYuval Mintz case 2: return "MCP"; 192b4149dc7SYuval Mintz case 3: return "MSDM"; 193b4149dc7SYuval Mintz case 4: return "PSDM"; 194b4149dc7SYuval Mintz case 5: return "YSDM"; 195b4149dc7SYuval Mintz case 6: return "USDM"; 196b4149dc7SYuval Mintz case 7: return "TSDM"; 197b4149dc7SYuval Mintz case 8: return "XSDM"; 198b4149dc7SYuval Mintz case 9: return "DBU"; 199b4149dc7SYuval Mintz case 10: return "DMAE"; 200b4149dc7SYuval Mintz default: 2019165dabbSMasanari Iida return "Unknown"; 202b4149dc7SYuval Mintz } 203b4149dc7SYuval Mintz } 204b4149dc7SYuval Mintz 205b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 206b4149dc7SYuval Mintz { 207b4149dc7SYuval Mintz u32 tmp, tmp2; 208b4149dc7SYuval Mintz 209b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 210b4149dc7SYuval Mintz * of interrupts via the validity register 211b4149dc7SYuval Mintz */ 212b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 213b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 214b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 215b4149dc7SYuval Mintz goto out; 216b4149dc7SYuval Mintz 217b4149dc7SYuval Mintz /* Read the GRC timeout information */ 218b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 219b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 220b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 221b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 222b4149dc7SYuval Mintz 223b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 224b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 225b4149dc7SYuval Mintz tmp2, tmp, 226b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 227b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 228b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 229b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 230b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 231fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 232b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 233b4149dc7SYuval Mintz 234b4149dc7SYuval Mintz out: 235b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 236b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 237b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 238b4149dc7SYuval Mintz return 0; 239b4149dc7SYuval Mintz } 240b4149dc7SYuval Mintz 241b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 242b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 243b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 244b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 245b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 246b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 247b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 248b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 249b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 250b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 251b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 252b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 253b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 254b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 255b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 256b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 257b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 258666db486STomer Tayar 259666db486STomer Tayar int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, 260666db486STomer Tayar struct qed_ptt *p_ptt) 261b4149dc7SYuval Mintz { 262b4149dc7SYuval Mintz u32 tmp; 263b4149dc7SYuval Mintz 264666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 265b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 266b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 267b4149dc7SYuval Mintz 268666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 269b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 270666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 271b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 272666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 273b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 274b4149dc7SYuval Mintz 275666db486STomer Tayar DP_NOTICE(p_hwfn, 276b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 277b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 278b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 279b4149dc7SYuval Mintz addr_hi, addr_lo, details, 280b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 281b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 282b4149dc7SYuval Mintz GET_FIELD(details, 283b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 284b4149dc7SYuval Mintz tmp, 285b4149dc7SYuval Mintz GET_FIELD(tmp, 286b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 287b4149dc7SYuval Mintz GET_FIELD(tmp, 288b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 289b4149dc7SYuval Mintz GET_FIELD(tmp, 290b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 291b4149dc7SYuval Mintz } 292b4149dc7SYuval Mintz 293666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 294b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 295b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 296b4149dc7SYuval Mintz 297666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 298b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 299666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 300b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 301666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 302b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 303b4149dc7SYuval Mintz 304666db486STomer Tayar DP_NOTICE(p_hwfn, 305b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 306b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 307b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 308b4149dc7SYuval Mintz addr_hi, addr_lo, details, 309b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 310b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 311b4149dc7SYuval Mintz GET_FIELD(details, 312b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 313b4149dc7SYuval Mintz tmp, 314666db486STomer Tayar GET_FIELD(tmp, 315666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 316666db486STomer Tayar GET_FIELD(tmp, 317666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 318666db486STomer Tayar GET_FIELD(tmp, 319666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 320b4149dc7SYuval Mintz } 321b4149dc7SYuval Mintz 322666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 323b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 324666db486STomer Tayar DP_NOTICE(p_hwfn, "ICPL error - %08x\n", tmp); 325b4149dc7SYuval Mintz 326666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 327b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 328b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 329b4149dc7SYuval Mintz 330666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 331b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 332666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 333b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 334b4149dc7SYuval Mintz 335666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 336b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 337b4149dc7SYuval Mintz } 338b4149dc7SYuval Mintz 339666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 340b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 341b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 342b4149dc7SYuval Mintz 343666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 344b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 345666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 346b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 347666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 348b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 349b4149dc7SYuval Mintz 350666db486STomer Tayar DP_NOTICE(p_hwfn, 351b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 352b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 353b4149dc7SYuval Mintz } 354b4149dc7SYuval Mintz 355b4149dc7SYuval Mintz /* Clear the indications */ 356666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 357b4149dc7SYuval Mintz 358b4149dc7SYuval Mintz return 0; 359b4149dc7SYuval Mintz } 360b4149dc7SYuval Mintz 361666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 362666db486STomer Tayar { 363666db486STomer Tayar return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt); 364666db486STomer Tayar } 365666db486STomer Tayar 366b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 367b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 368a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 369b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 370b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 371a1b469b8SAriel Elior 372a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000 373a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100 374a1b469b8SAriel Elior 375a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 376a1b469b8SAriel Elior struct qed_ptt *p_ptt) 377a1b469b8SAriel Elior { 378a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT; 379a1b469b8SAriel Elior u32 usage = 1; 380a1b469b8SAriel Elior 381a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since 382a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such 383a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with 384a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM 385a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or 386a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second 387a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such 388a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before 389a1b469b8SAriel Elior * releasing the overflow sticky indication. 390a1b469b8SAriel Elior */ 391a1b469b8SAriel Elior while (count-- && usage) { 392a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 393a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL); 394a1b469b8SAriel Elior } 395a1b469b8SAriel Elior 396a1b469b8SAriel Elior /* should have been depleted by now */ 397a1b469b8SAriel Elior if (usage) { 398a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 399a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 400a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 401a1b469b8SAriel Elior return -EBUSY; 402a1b469b8SAriel Elior } 403a1b469b8SAriel Elior 404a1b469b8SAriel Elior return 0; 405a1b469b8SAriel Elior } 406a1b469b8SAriel Elior 407a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 408a1b469b8SAriel Elior { 409a1b469b8SAriel Elior u32 overflow; 410a1b469b8SAriel Elior int rc; 411a1b469b8SAriel Elior 412a1b469b8SAriel Elior overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 413a1b469b8SAriel Elior DP_NOTICE(p_hwfn, "PF Overflow sticky 0x%x\n", overflow); 4149ac6bb14SDenis Bolotin if (!overflow) 415a1b469b8SAriel Elior return 0; 416a1b469b8SAriel Elior 417a1b469b8SAriel Elior if (qed_edpm_enabled(p_hwfn)) { 418a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 419a1b469b8SAriel Elior if (rc) 420a1b469b8SAriel Elior return rc; 421a1b469b8SAriel Elior } 422a1b469b8SAriel Elior 423a1b469b8SAriel Elior /* Flush any pending (e)dpm as they may never arrive */ 424a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 425a1b469b8SAriel Elior 426a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */ 427a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 428a1b469b8SAriel Elior 429a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */ 4309ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn); 431a1b469b8SAriel Elior 432a1b469b8SAriel Elior return 0; 433a1b469b8SAriel Elior } 434a1b469b8SAriel Elior 435b4149dc7SYuval Mintz static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 436b4149dc7SYuval Mintz { 437a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason; 438a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 439a1b469b8SAriel Elior int rc; 440b4149dc7SYuval Mintz 441d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true; 442a1b469b8SAriel Elior 443a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell 444a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If 445a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again. 446a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring. 447a1b469b8SAriel Elior */ 448d4476b8aSDenis Bolotin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 449a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 450a1b469b8SAriel Elior return 0; 451a1b469b8SAriel Elior 452d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 453d4476b8aSDenis Bolotin 454a1b469b8SAriel Elior /* check if db_drop or overflow happened */ 455a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 456a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 457a1b469b8SAriel Elior /* Obtain data about db drop/overflow */ 458a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt, 459a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) & 460b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 461a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 462a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt, 463a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS); 464a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt, 465a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON); 466b4149dc7SYuval Mintz 467a1b469b8SAriel Elior /* Log info */ 468a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 469a1b469b8SAriel Elior "Doorbell drop occurred\n" 470a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n" 471a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n" 472a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n" 473a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 474a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 475a1b469b8SAriel Elior address, 476a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 477b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 478a1b469b8SAriel Elior first_drop_reason, all_drops_reason); 479a1b469b8SAriel Elior 480a1b469b8SAriel Elior rc = qed_db_rec_handler(p_hwfn, p_ptt); 481a1b469b8SAriel Elior qed_periodic_db_rec_start(p_hwfn); 482a1b469b8SAriel Elior if (rc) 483a1b469b8SAriel Elior return rc; 484a1b469b8SAriel Elior 485a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */ 486a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 487a1b469b8SAriel Elior 488a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different 489a1b469b8SAriel Elior * reason than overflow we mark as handled) 490a1b469b8SAriel Elior */ 491a1b469b8SAriel Elior qed_wr(p_hwfn, 492a1b469b8SAriel Elior p_ptt, 493a1b469b8SAriel Elior DORQ_REG_INT_STS_WR, 494a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP | 495a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 496a1b469b8SAriel Elior 497a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */ 498a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 499a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 500a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 501a1b469b8SAriel Elior return 0; 502b4149dc7SYuval Mintz } 503b4149dc7SYuval Mintz 504a1b469b8SAriel Elior /* Some other indication was present - non recoverable */ 505a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n"); 506a1b469b8SAriel Elior 507b4149dc7SYuval Mintz return -EINVAL; 508b4149dc7SYuval Mintz } 509b4149dc7SYuval Mintz 510d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 511d4476b8aSDenis Bolotin { 512d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn) 513d4476b8aSDenis Bolotin goto out; 514d4476b8aSDenis Bolotin 515d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */ 516d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn); 517d4476b8aSDenis Bolotin out: 518d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false; 519d4476b8aSDenis Bolotin } 520d4476b8aSDenis Bolotin 521ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 522ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 523ba36f718SMintz, Yuval */ 524ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 525ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 526ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 527ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 528ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 529ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 530ba36f718SMintz, Yuval }; 531ba36f718SMintz, Yuval 532ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 533ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 534ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 535ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 536ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 537ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 538ba36f718SMintz, Yuval }; 539ba36f718SMintz, Yuval 5400d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 5410d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 5420d956e8aSYuval Mintz { 5430d956e8aSYuval Mintz { /* After Invert 1 */ 5440d956e8aSYuval Mintz {"GPIO0 function%d", 545b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5460d956e8aSYuval Mintz } 5470d956e8aSYuval Mintz }, 5480d956e8aSYuval Mintz 5490d956e8aSYuval Mintz { 5500d956e8aSYuval Mintz { /* After Invert 2 */ 551b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 552b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 553b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 554b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 555b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 556666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 557b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 558b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 559b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 560b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 561b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 5620d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 563ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 564b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5650d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 566b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 5670d956e8aSYuval Mintz } 5680d956e8aSYuval Mintz }, 5690d956e8aSYuval Mintz 5700d956e8aSYuval Mintz { 5710d956e8aSYuval Mintz { /* After Invert 3 */ 5720d956e8aSYuval Mintz {"General Attention %d", 573b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5740d956e8aSYuval Mintz } 5750d956e8aSYuval Mintz }, 5760d956e8aSYuval Mintz 5770d956e8aSYuval Mintz { 5780d956e8aSYuval Mintz { /* After Invert 4 */ 579ff38577aSYuval Mintz {"General Attention 32", ATTENTION_SINGLE, 580b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5810d956e8aSYuval Mintz {"General Attention %d", 5820d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 583b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 584ff38577aSYuval Mintz {"General Attention 35", ATTENTION_SINGLE, 585b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 586ba36f718SMintz, Yuval {"NWS Parity", 587ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 588ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 589ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 590ba36f718SMintz, Yuval {"NWS Interrupt", 591ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 592ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 593ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 594ba36f718SMintz, Yuval {"NWM Parity", 595ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 596ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 597ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 598ba36f718SMintz, Yuval {"NWM Interrupt", 599ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 600ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 601ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 602b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 603b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 604b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 605b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 606b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 607ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 608b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 609b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 610b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 611b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 612ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 613b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 614b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 615b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 616b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 617b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 618b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 6190d956e8aSYuval Mintz } 6200d956e8aSYuval Mintz }, 6210d956e8aSYuval Mintz 6220d956e8aSYuval Mintz { 6230d956e8aSYuval Mintz { /* After Invert 5 */ 624b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 625b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 626b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 627b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 628b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 629b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 630b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 631b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 632b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 633b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 634b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 635b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 636b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 637b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 638b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 639b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 6400d956e8aSYuval Mintz } 6410d956e8aSYuval Mintz }, 6420d956e8aSYuval Mintz 6430d956e8aSYuval Mintz { 6440d956e8aSYuval Mintz { /* After Invert 6 */ 645b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 646b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 647b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 648b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 649b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 650b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 651b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 652b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 653b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 654b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 655b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 656b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 657b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 658b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 659b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 660b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 661b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 6620d956e8aSYuval Mintz } 6630d956e8aSYuval Mintz }, 6640d956e8aSYuval Mintz 6650d956e8aSYuval Mintz { 6660d956e8aSYuval Mintz { /* After Invert 7 */ 667b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 668b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 669b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 670b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 671b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 672b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 673b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 674b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 675b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 676b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 677b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 678b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 679b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 680b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 681b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 682b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 683b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 6840d956e8aSYuval Mintz } 6850d956e8aSYuval Mintz }, 6860d956e8aSYuval Mintz 6870d956e8aSYuval Mintz { 6880d956e8aSYuval Mintz { /* After Invert 8 */ 689b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 690b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 691b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 692b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 693b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 694b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 695b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 696b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 697b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 698b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 699b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 700b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 701b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 702b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 703b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 704b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 705b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 706b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 707b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 708b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 709b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 710b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 711b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 712ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 713b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 714b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 715b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 716ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 717b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 718ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 719b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7200d956e8aSYuval Mintz } 7210d956e8aSYuval Mintz }, 7220d956e8aSYuval Mintz 7230d956e8aSYuval Mintz { 7240d956e8aSYuval Mintz { /* After Invert 9 */ 725b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 726b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 727ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 728b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 729b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 730b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 731ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 732b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 733ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 734b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7350d956e8aSYuval Mintz } 7360d956e8aSYuval Mintz }, 7370d956e8aSYuval Mintz }; 7380d956e8aSYuval Mintz 739ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 740ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 741ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 742ba36f718SMintz, Yuval { 743ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 744ba36f718SMintz, Yuval return p_bit; 745ba36f718SMintz, Yuval 746ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 747ba36f718SMintz, Yuval return p_bit; 748ba36f718SMintz, Yuval 749ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 750ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 751ba36f718SMintz, Yuval } 752ba36f718SMintz, Yuval 753ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 754ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 755ba36f718SMintz, Yuval { 756ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 757ba36f718SMintz, Yuval ATTENTION_PARITY); 758ba36f718SMintz, Yuval } 759ba36f718SMintz, Yuval 760cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 761cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 762cc875c2eSYuval Mintz struct qed_sb_attn_info { 763cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 764cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 765cc875c2eSYuval Mintz dma_addr_t sb_phys; 766cc875c2eSYuval Mintz 767cc875c2eSYuval Mintz /* Last seen running index */ 768cc875c2eSYuval Mintz u16 index; 769cc875c2eSYuval Mintz 7700d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 7710d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 7720d956e8aSYuval Mintz 7730d956e8aSYuval Mintz /* A pointer to the attention description structure */ 7740d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 7750d956e8aSYuval Mintz 776cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 777cc875c2eSYuval Mintz u16 known_attn; 778cc875c2eSYuval Mintz 779cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 780cc875c2eSYuval Mintz u32 mfw_attn_addr; 781cc875c2eSYuval Mintz }; 782cc875c2eSYuval Mintz 783cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 784cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 785cc875c2eSYuval Mintz { 7861a635e48SYuval Mintz u16 rc = 0, index; 787cc875c2eSYuval Mintz 788cc875c2eSYuval Mintz /* Make certain HW write took affect */ 789cc875c2eSYuval Mintz mmiowb(); 790cc875c2eSYuval Mintz 791cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 792cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 793cc875c2eSYuval Mintz p_sb_desc->index = index; 794cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 795cc875c2eSYuval Mintz } 796cc875c2eSYuval Mintz 797cc875c2eSYuval Mintz /* Make certain we got a consistent view with HW */ 798cc875c2eSYuval Mintz mmiowb(); 799cc875c2eSYuval Mintz 800cc875c2eSYuval Mintz return rc; 801cc875c2eSYuval Mintz } 802cc875c2eSYuval Mintz 803cc875c2eSYuval Mintz /** 804cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 805cc875c2eSYuval Mintz * 806cc875c2eSYuval Mintz * @param p_hwfn 807cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 808cc875c2eSYuval Mintz * @return int 809cc875c2eSYuval Mintz */ 8101a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 811cc875c2eSYuval Mintz { 812cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 813cc875c2eSYuval Mintz u32 igu_mask; 814cc875c2eSYuval Mintz 815cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 8161a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 817cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 818cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 819cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 820cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 821cc875c2eSYuval Mintz 822cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 823cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 824cc875c2eSYuval Mintz sb_attn_sw->known_attn, 825cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 826cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 827cc875c2eSYuval Mintz 828cc875c2eSYuval Mintz /* Handle MCP events */ 829cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 830cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 831cc875c2eSYuval Mintz /* Clean the MCP attention */ 832cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 833cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 834cc875c2eSYuval Mintz } 835cc875c2eSYuval Mintz 836cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 837cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 838cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 839cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 840cc875c2eSYuval Mintz (u32)asserted_bits); 841cc875c2eSYuval Mintz 842cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 843cc875c2eSYuval Mintz asserted_bits); 844cc875c2eSYuval Mintz 845cc875c2eSYuval Mintz return 0; 846cc875c2eSYuval Mintz } 847cc875c2eSYuval Mintz 8480ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 8490ebbd1c8SMintz, Yuval enum block_id id, 8500ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 851ff38577aSYuval Mintz { 8520ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 8530ebbd1c8SMintz, Yuval enum dbg_status status; 854ff38577aSYuval Mintz 8550ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 856ff38577aSYuval Mintz 8570ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 8580ebbd1c8SMintz, Yuval b_clear, &attn_results); 8590ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 860ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 8610ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 8620ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 8630ebbd1c8SMintz, Yuval else 8640ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 865ff38577aSYuval Mintz } 866ff38577aSYuval Mintz 867cc875c2eSYuval Mintz /** 8680d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 8690d956e8aSYuval Mintz * cause of the attention 8700d956e8aSYuval Mintz * 8710d956e8aSYuval Mintz * @param p_hwfn 8720d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 8730d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 8740d956e8aSYuval Mintz * this bit to this group. 8750d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 8760d956e8aSYuval Mintz * 8770d956e8aSYuval Mintz * @return int 8780d956e8aSYuval Mintz */ 8790d956e8aSYuval Mintz static int 8800d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 8810d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 8820d956e8aSYuval Mintz u32 aeu_en_reg, 8836010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 8840d956e8aSYuval Mintz { 8850ebbd1c8SMintz, Yuval bool b_fatal = false; 8860d956e8aSYuval Mintz int rc = -EINVAL; 887b4149dc7SYuval Mintz u32 val; 8880d956e8aSYuval Mintz 8890d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 8906010179dSMintz, Yuval p_bit_name, bitmask); 8910d956e8aSYuval Mintz 892b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 893b4149dc7SYuval Mintz if (p_aeu->cb) { 894b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 8956010179dSMintz, Yuval p_bit_name); 896b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 897b4149dc7SYuval Mintz } 898b4149dc7SYuval Mintz 8990ebbd1c8SMintz, Yuval if (rc) 9000ebbd1c8SMintz, Yuval b_fatal = true; 901ff38577aSYuval Mintz 9020ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 9030ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 9040ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 9050ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 906ff38577aSYuval Mintz 907ff38577aSYuval Mintz 908b4149dc7SYuval Mintz /* If the attention is benign, no need to prevent it */ 909b4149dc7SYuval Mintz if (!rc) 910b4149dc7SYuval Mintz goto out; 911b4149dc7SYuval Mintz 9120d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 9130d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 914b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 9150d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 9166010179dSMintz, Yuval p_bit_name); 9170d956e8aSYuval Mintz 918b4149dc7SYuval Mintz out: 9190d956e8aSYuval Mintz return rc; 9200d956e8aSYuval Mintz } 9210d956e8aSYuval Mintz 922ff38577aSYuval Mintz /** 923ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 924ff38577aSYuval Mintz * 925ff38577aSYuval Mintz * @param p_hwfn 926ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 9279790c35eSMintz, Yuval * @param aeu_en_reg - address of the AEU enable register 928ff38577aSYuval Mintz * @param bit_index 929ff38577aSYuval Mintz */ 930ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 931ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9329790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 933ff38577aSYuval Mintz { 9349790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 935ff38577aSYuval Mintz 9369790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 9379790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 9389790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 939ff38577aSYuval Mintz 940ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 9410ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 942ff38577aSYuval Mintz 943ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 944ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 9450ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 9460ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 9470ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 9480ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 949ff38577aSYuval Mintz } 950ff38577aSYuval Mintz } 9519790c35eSMintz, Yuval 9529790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 9539790c35eSMintz, Yuval mask = ~BIT(bit_index); 9549790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 9559790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 9569790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 9579790c35eSMintz, Yuval p_aeu->bit_name); 958ff38577aSYuval Mintz } 959ff38577aSYuval Mintz 9600d956e8aSYuval Mintz /** 961cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 962cc875c2eSYuval Mintz * 963cc875c2eSYuval Mintz * @param p_hwfn 964cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 965cc875c2eSYuval Mintz * @return int 966cc875c2eSYuval Mintz * 967cc875c2eSYuval Mintz */ 968cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 969cc875c2eSYuval Mintz u16 deasserted_bits) 970cc875c2eSYuval Mintz { 971cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 9729790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 9730d956e8aSYuval Mintz u8 i, j, k, bit_idx; 9740d956e8aSYuval Mintz int rc = 0; 975cc875c2eSYuval Mintz 9760d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 9770d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 9780d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 9790d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 9800d956e8aSYuval Mintz i * 0x4); 9810d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 9820d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 9830d956e8aSYuval Mintz i, aeu_inv_arr[i]); 9840d956e8aSYuval Mintz } 9850d956e8aSYuval Mintz 9860d956e8aSYuval Mintz /* Find parity attentions first */ 9870d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 9880d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 9890d956e8aSYuval Mintz u32 parities; 9900d956e8aSYuval Mintz 9919790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 9929790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 9939790c35eSMintz, Yuval 9940d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 9950d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 9960d956e8aSYuval Mintz if (!parities) 9970d956e8aSYuval Mintz continue; 9980d956e8aSYuval Mintz 9990d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10000d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 10010d956e8aSYuval Mintz 1002ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 10031a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 1004ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 10059790c35eSMintz, Yuval aeu_en, bit_idx); 10060d956e8aSYuval Mintz 10070d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 10080d956e8aSYuval Mintz } 10090d956e8aSYuval Mintz } 10100d956e8aSYuval Mintz 10110d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 10120d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 10130d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 10140d956e8aSYuval Mintz 10150d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 10160d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 10170d956e8aSYuval Mintz continue; 10180d956e8aSYuval Mintz 10190d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10209790c35eSMintz, Yuval u32 bits; 10219790c35eSMintz, Yuval 10229790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 10230d956e8aSYuval Mintz i * sizeof(u32) + 10240d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 10250d956e8aSYuval Mintz 10260d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10270d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 10280d956e8aSYuval Mintz 10290d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 10300d956e8aSYuval Mintz if (!bits) 10310d956e8aSYuval Mintz continue; 10320d956e8aSYuval Mintz 10330d956e8aSYuval Mintz /* Find all set bits from current register which belong 10340d956e8aSYuval Mintz * to current group, making them responsible for the 10350d956e8aSYuval Mintz * previous assertion. 10360d956e8aSYuval Mintz */ 10370d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10386010179dSMintz, Yuval long unsigned int bitmask; 10390d956e8aSYuval Mintz u8 bit, bit_len; 10400d956e8aSYuval Mintz 10410d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1042ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 10430d956e8aSYuval Mintz 10440d956e8aSYuval Mintz bit = bit_idx; 10450d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 1046ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 10470d956e8aSYuval Mintz /* Skip Parity */ 10480d956e8aSYuval Mintz bit++; 10490d956e8aSYuval Mintz bit_len--; 10500d956e8aSYuval Mintz } 10510d956e8aSYuval Mintz 10520d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 10536010179dSMintz, Yuval bitmask >>= bit; 10546010179dSMintz, Yuval 10550d956e8aSYuval Mintz if (bitmask) { 10566010179dSMintz, Yuval u32 flags = p_aeu->flags; 10576010179dSMintz, Yuval char bit_name[30]; 10586010179dSMintz, Yuval u8 num; 10596010179dSMintz, Yuval 10606010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 10616010179dSMintz, Yuval bit_len); 10626010179dSMintz, Yuval 10636010179dSMintz, Yuval /* Some bits represent more than a 10646010179dSMintz, Yuval * a single interrupt. Correctly print 10656010179dSMintz, Yuval * their name. 10666010179dSMintz, Yuval */ 10676010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 10686010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 10696010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 10706010179dSMintz, Yuval snprintf(bit_name, 30, 10716010179dSMintz, Yuval p_aeu->bit_name, num); 10726010179dSMintz, Yuval else 10736010179dSMintz, Yuval strncpy(bit_name, 10746010179dSMintz, Yuval p_aeu->bit_name, 30); 10756010179dSMintz, Yuval 10766010179dSMintz, Yuval /* We now need to pass bitmask in its 10776010179dSMintz, Yuval * correct position. 10786010179dSMintz, Yuval */ 10796010179dSMintz, Yuval bitmask <<= bit; 10806010179dSMintz, Yuval 10810d956e8aSYuval Mintz /* Handle source of the attention */ 10820d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 10830d956e8aSYuval Mintz p_aeu, 10840d956e8aSYuval Mintz aeu_en, 10856010179dSMintz, Yuval bit_name, 10860d956e8aSYuval Mintz bitmask); 10870d956e8aSYuval Mintz } 10880d956e8aSYuval Mintz 10890d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 10900d956e8aSYuval Mintz } 10910d956e8aSYuval Mintz } 10920d956e8aSYuval Mintz } 1093cc875c2eSYuval Mintz 1094d4476b8aSDenis Bolotin /* Handle missed DORQ attention */ 1095d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn); 1096d4476b8aSDenis Bolotin 1097cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 1098cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1099cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1100cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1101cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1102cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 1103cc875c2eSYuval Mintz 1104cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 11051a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1106cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1107cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1108cc875c2eSYuval Mintz 1109cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 1110cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 1111cc875c2eSYuval Mintz 11120d956e8aSYuval Mintz return rc; 1113cc875c2eSYuval Mintz } 1114cc875c2eSYuval Mintz 1115cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1116cc875c2eSYuval Mintz { 1117cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1118cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1119cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 1120cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 1121cc875c2eSYuval Mintz __le16 index; 1122cc875c2eSYuval Mintz int rc = 0; 1123cc875c2eSYuval Mintz 1124cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 1125cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 1126cc875c2eSYuval Mintz */ 1127cc875c2eSYuval Mintz do { 1128cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 1129ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 1130ed4eac20SDenis Bolotin dma_rmb(); 1131cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1132cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1133cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1134cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1135cc875c2eSYuval Mintz 1136cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1137cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1138cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1139cc875c2eSYuval Mintz * attention with no previous attention 1140cc875c2eSYuval Mintz */ 1141cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1142cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1143cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1144cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1145cc875c2eSYuval Mintz 1146cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1147cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1148cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1149cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1150cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1151cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 11521a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 1153cc875c2eSYuval Mintz } else { 1154cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1155cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1156cc875c2eSYuval Mintz } 1157cc875c2eSYuval Mintz 1158cc875c2eSYuval Mintz if (asserted_bits) { 1159cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1160cc875c2eSYuval Mintz if (rc) 1161cc875c2eSYuval Mintz return rc; 1162cc875c2eSYuval Mintz } 1163cc875c2eSYuval Mintz 11641a635e48SYuval Mintz if (deasserted_bits) 1165cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1166cc875c2eSYuval Mintz 1167cc875c2eSYuval Mintz return rc; 1168cc875c2eSYuval Mintz } 1169cc875c2eSYuval Mintz 1170cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 11711a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1172cc875c2eSYuval Mintz { 1173cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1174cc875c2eSYuval Mintz 1175cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 1176cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1177cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1178cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1179cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1180cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1181cc875c2eSYuval Mintz 1182cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1183cc875c2eSYuval Mintz 1184cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1185cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1186cc875c2eSYuval Mintz */ 1187cc875c2eSYuval Mintz mmiowb(); 1188cc875c2eSYuval Mintz barrier(); 1189cc875c2eSYuval Mintz } 1190cc875c2eSYuval Mintz 1191fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 1192fe56b9e6SYuval Mintz { 1193fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1194fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1195cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1196fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1197fe56b9e6SYuval Mintz int arr_size; 1198fe56b9e6SYuval Mintz u16 rc = 0; 1199fe56b9e6SYuval Mintz 1200fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1201fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1202fe56b9e6SYuval Mintz return; 1203fe56b9e6SYuval Mintz } 1204fe56b9e6SYuval Mintz 1205fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1206fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1207fe56b9e6SYuval Mintz if (!sb_info) { 1208fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1209fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1210fe56b9e6SYuval Mintz return; 1211fe56b9e6SYuval Mintz } 1212fe56b9e6SYuval Mintz 1213cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1214cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1215cc875c2eSYuval Mintz return; 1216cc875c2eSYuval Mintz } 1217cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1218cc875c2eSYuval Mintz 1219fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1220fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1221fe56b9e6SYuval Mintz 1222fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1223fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1224fe56b9e6SYuval Mintz */ 1225fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1226fe56b9e6SYuval Mintz 1227fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1228fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 12291a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1230fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1231fe56b9e6SYuval Mintz } else { 1232fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1233fe56b9e6SYuval Mintz 1234fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1235fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1236fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1237fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1238fe56b9e6SYuval Mintz } 1239fe56b9e6SYuval Mintz 1240cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 12411a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1242cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1243cc875c2eSYuval Mintz } else { 1244cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1245cc875c2eSYuval Mintz 1246cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1247cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1248cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1249cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1250cc875c2eSYuval Mintz } 1251cc875c2eSYuval Mintz 1252fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1253fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1254fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1255fe56b9e6SYuval Mintz return; 1256fe56b9e6SYuval Mintz } 1257fe56b9e6SYuval Mintz 1258fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1259fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1260fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1261fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1262fe56b9e6SYuval Mintz return; 1263fe56b9e6SYuval Mintz } 1264fe56b9e6SYuval Mintz 1265cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1266cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1267cc875c2eSYuval Mintz 1268fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1269fe56b9e6SYuval Mintz int pi; 1270fe56b9e6SYuval Mintz 1271fe56b9e6SYuval Mintz /* Look for a free index */ 1272fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1273fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1274fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1275fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1276fe56b9e6SYuval Mintz } 1277fe56b9e6SYuval Mintz } 1278fe56b9e6SYuval Mintz 1279cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1280cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1281cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1282cc875c2eSYuval Mintz */ 1283cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1284cc875c2eSYuval Mintz 1285fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1286fe56b9e6SYuval Mintz } 1287fe56b9e6SYuval Mintz 1288cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1289cc875c2eSYuval Mintz { 1290cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1291cc875c2eSYuval Mintz 12924ac801b7SYuval Mintz if (!p_sb) 12934ac801b7SYuval Mintz return; 12944ac801b7SYuval Mintz 1295cc875c2eSYuval Mintz if (p_sb->sb_attn) 12964ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1297cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 12981a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1299cc875c2eSYuval Mintz kfree(p_sb); 13003587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1301cc875c2eSYuval Mintz } 1302cc875c2eSYuval Mintz 1303cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1304cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1305cc875c2eSYuval Mintz { 1306cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1307cc875c2eSYuval Mintz 1308cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1309cc875c2eSYuval Mintz 1310cc875c2eSYuval Mintz sb_info->index = 0; 1311cc875c2eSYuval Mintz sb_info->known_attn = 0; 1312cc875c2eSYuval Mintz 1313cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1314cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1315cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1316cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1317cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1318cc875c2eSYuval Mintz } 1319cc875c2eSYuval Mintz 1320cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1321cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 13221a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1323cc875c2eSYuval Mintz { 1324cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 13250d956e8aSYuval Mintz int i, j, k; 1326cc875c2eSYuval Mintz 1327cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1328cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1329cc875c2eSYuval Mintz 13300d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 13310d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 13320d956e8aSYuval Mintz 13330d956e8aSYuval Mintz /* Calculate Parity Masks */ 13340d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 13350d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 13360d956e8aSYuval Mintz /* j is array index, k is bit index */ 13370d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1338ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 13390d956e8aSYuval Mintz 1340ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1341ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 13420d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 13430d956e8aSYuval Mintz 1344ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 13450d956e8aSYuval Mintz } 13460d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 13470d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 13480d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 13490d956e8aSYuval Mintz } 13500d956e8aSYuval Mintz 1351cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1352cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1353cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1354cc875c2eSYuval Mintz 1355cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1356cc875c2eSYuval Mintz } 1357cc875c2eSYuval Mintz 1358cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1359cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1360cc875c2eSYuval Mintz { 1361cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1362cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1363cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 13641a635e48SYuval Mintz void *p_virt; 1365cc875c2eSYuval Mintz 1366cc875c2eSYuval Mintz /* SB struct */ 136760fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 13682591c280SJoe Perches if (!p_sb) 1369cc875c2eSYuval Mintz return -ENOMEM; 1370cc875c2eSYuval Mintz 1371cc875c2eSYuval Mintz /* SB ring */ 1372cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1373cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1374cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1375cc875c2eSYuval Mintz 1376cc875c2eSYuval Mintz if (!p_virt) { 1377cc875c2eSYuval Mintz kfree(p_sb); 1378cc875c2eSYuval Mintz return -ENOMEM; 1379cc875c2eSYuval Mintz } 1380cc875c2eSYuval Mintz 1381cc875c2eSYuval Mintz /* Attention setup */ 1382cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1383cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1384cc875c2eSYuval Mintz 1385cc875c2eSYuval Mintz return 0; 1386cc875c2eSYuval Mintz } 1387cc875c2eSYuval Mintz 1388fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1389fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1390fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1391fe56b9e6SYuval Mintz 1392fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1393fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 13941a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1395fe56b9e6SYuval Mintz { 13964ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1397fe56b9e6SYuval Mintz u32 cau_state; 1398722003acSSudarsana Reddy Kalluru u8 timer_res; 1399fe56b9e6SYuval Mintz 1400fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1401fe56b9e6SYuval Mintz 1402fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1403fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1404fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1405fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1406fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1407fe56b9e6SYuval Mintz 1408fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1409fe56b9e6SYuval Mintz 14104ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1411fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 14124ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 14134ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 14144ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 14154ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1416fe56b9e6SYuval Mintz } 1417fe56b9e6SYuval Mintz 1418722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1419722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1420722003acSSudarsana Reddy Kalluru timer_res = 0; 1421722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1422722003acSSudarsana Reddy Kalluru timer_res = 1; 1423722003acSSudarsana Reddy Kalluru else 1424722003acSSudarsana Reddy Kalluru timer_res = 2; 1425722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1426722003acSSudarsana Reddy Kalluru 1427722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1428722003acSSudarsana Reddy Kalluru timer_res = 0; 1429722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1430722003acSSudarsana Reddy Kalluru timer_res = 1; 1431722003acSSudarsana Reddy Kalluru else 1432722003acSSudarsana Reddy Kalluru timer_res = 2; 1433722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1434722003acSSudarsana Reddy Kalluru 1435fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1436fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1437fe56b9e6SYuval Mintz } 1438fe56b9e6SYuval Mintz 14398befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 14408befd73cSMintz, Yuval struct qed_ptt *p_ptt, 14418befd73cSMintz, Yuval u16 igu_sb_id, 14428befd73cSMintz, Yuval u32 pi_index, 14438befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 14448befd73cSMintz, Yuval u8 timeset) 14458befd73cSMintz, Yuval { 14468befd73cSMintz, Yuval struct cau_pi_entry pi_entry; 14478befd73cSMintz, Yuval u32 sb_offset, pi_offset; 14488befd73cSMintz, Yuval 14498befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 14508befd73cSMintz, Yuval return; 14518befd73cSMintz, Yuval 145221dd79e8STomer Tayar sb_offset = igu_sb_id * PIS_PER_SB_E4; 14538befd73cSMintz, Yuval memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 14548befd73cSMintz, Yuval 14558befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 14568befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 14578befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 14588befd73cSMintz, Yuval else 14598befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 14608befd73cSMintz, Yuval 14618befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 14628befd73cSMintz, Yuval if (p_hwfn->hw_init_done) { 14638befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 14648befd73cSMintz, Yuval CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 14658befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14668befd73cSMintz, Yuval } else { 14678befd73cSMintz, Yuval STORE_RT_REG(p_hwfn, 14688befd73cSMintz, Yuval CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 14698befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14708befd73cSMintz, Yuval } 14718befd73cSMintz, Yuval } 14728befd73cSMintz, Yuval 1473fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1474fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1475fe56b9e6SYuval Mintz dma_addr_t sb_phys, 14761a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1477fe56b9e6SYuval Mintz { 1478fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1479fe56b9e6SYuval Mintz 1480fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1481fe56b9e6SYuval Mintz vf_number, vf_valid); 1482fe56b9e6SYuval Mintz 1483fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 14840a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 14850a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1486fe56b9e6SYuval Mintz 14870a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 14880a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 14890a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 14900a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 14910a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 14920a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 1493fe56b9e6SYuval Mintz } else { 1494fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1495fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1496fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1497fe56b9e6SYuval Mintz igu_sb_id * 2, 1498fe56b9e6SYuval Mintz sb_phys); 1499fe56b9e6SYuval Mintz 1500fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1501fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1502fe56b9e6SYuval Mintz igu_sb_id * 2, 1503fe56b9e6SYuval Mintz sb_entry); 1504fe56b9e6SYuval Mintz } 1505fe56b9e6SYuval Mintz 1506fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1507fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1508b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1509722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1510b5a9ee7cSAriel Elior u8 i; 1511fe56b9e6SYuval Mintz 1512722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1513722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1514722003acSSudarsana Reddy Kalluru timer_res = 0; 1515722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1516722003acSSudarsana Reddy Kalluru timer_res = 1; 1517722003acSSudarsana Reddy Kalluru else 1518722003acSSudarsana Reddy Kalluru timer_res = 2; 1519722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1520fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 15211a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1522fe56b9e6SYuval Mintz 1523722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1524722003acSSudarsana Reddy Kalluru timer_res = 0; 1525722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1526722003acSSudarsana Reddy Kalluru timer_res = 1; 1527722003acSSudarsana Reddy Kalluru else 1528722003acSSudarsana Reddy Kalluru timer_res = 2; 1529722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1530fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1531fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1532fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1533fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1534fe56b9e6SYuval Mintz timeset); 1535fe56b9e6SYuval Mintz } 1536fe56b9e6SYuval Mintz } 1537fe56b9e6SYuval Mintz } 1538fe56b9e6SYuval Mintz 1539fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 15401a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1541fe56b9e6SYuval Mintz { 1542fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1543fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1544fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1545fe56b9e6SYuval Mintz 15461408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1547fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1548fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1549fe56b9e6SYuval Mintz } 1550fe56b9e6SYuval Mintz 155109b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 155209b6b147SMintz, Yuval { 155309b6b147SMintz, Yuval struct qed_igu_block *p_block; 155409b6b147SMintz, Yuval u16 igu_id; 155509b6b147SMintz, Yuval 155609b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 155709b6b147SMintz, Yuval igu_id++) { 155809b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 155909b6b147SMintz, Yuval 156009b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 156109b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 156209b6b147SMintz, Yuval continue; 156309b6b147SMintz, Yuval 156409b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 156509b6b147SMintz, Yuval return p_block; 156609b6b147SMintz, Yuval } 156709b6b147SMintz, Yuval 156809b6b147SMintz, Yuval return NULL; 156909b6b147SMintz, Yuval } 157009b6b147SMintz, Yuval 1571a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1572a333f7f3SMintz, Yuval { 1573a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1574a333f7f3SMintz, Yuval u16 igu_id; 1575a333f7f3SMintz, Yuval 1576a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1577a333f7f3SMintz, Yuval igu_id++) { 1578a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1579a333f7f3SMintz, Yuval 1580a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1581a333f7f3SMintz, Yuval !p_block->is_pf || 1582a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1583a333f7f3SMintz, Yuval continue; 1584a333f7f3SMintz, Yuval 1585a333f7f3SMintz, Yuval return igu_id; 1586a333f7f3SMintz, Yuval } 1587a333f7f3SMintz, Yuval 1588a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1589a333f7f3SMintz, Yuval } 1590a333f7f3SMintz, Yuval 159150a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1592fe56b9e6SYuval Mintz { 1593fe56b9e6SYuval Mintz u16 igu_sb_id; 1594fe56b9e6SYuval Mintz 1595fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1596fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1597fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 15981408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1599a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 16001408cc1fSYuval Mintz else 16011408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1602fe56b9e6SYuval Mintz 1603525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1604525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1605525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1606525ef5c0SYuval Mintz else 1607525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1608525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1609fe56b9e6SYuval Mintz 1610fe56b9e6SYuval Mintz return igu_sb_id; 1611fe56b9e6SYuval Mintz } 1612fe56b9e6SYuval Mintz 1613fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1614fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1615fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 16161a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1617fe56b9e6SYuval Mintz { 1618fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1619fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1620fe56b9e6SYuval Mintz 1621fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1622fe56b9e6SYuval Mintz 1623fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 162450a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 162550a20714SMintz, Yuval struct qed_igu_info *p_info; 162650a20714SMintz, Yuval struct qed_igu_block *p_block; 162750a20714SMintz, Yuval 162850a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 162950a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 163050a20714SMintz, Yuval 163150a20714SMintz, Yuval p_block->sb_info = sb_info; 163250a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 163350a20714SMintz, Yuval p_info->usage.free_cnt--; 163450a20714SMintz, Yuval } else { 163550a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 163650a20714SMintz, Yuval } 1637fe56b9e6SYuval Mintz } 1638fe56b9e6SYuval Mintz 1639fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1640fe56b9e6SYuval Mintz 1641fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1642fe56b9e6SYuval Mintz * written to for a specific status block 1643fe56b9e6SYuval Mintz */ 16441408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1645fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1646fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1647fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 16481408cc1fSYuval Mintz } else { 16491408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 16501408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 16511408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 16521408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 16531408cc1fSYuval Mintz } 1654fe56b9e6SYuval Mintz 1655fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1656fe56b9e6SYuval Mintz 1657fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1658fe56b9e6SYuval Mintz 1659fe56b9e6SYuval Mintz return 0; 1660fe56b9e6SYuval Mintz } 1661fe56b9e6SYuval Mintz 1662fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 16631a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1664fe56b9e6SYuval Mintz { 166550a20714SMintz, Yuval struct qed_igu_block *p_block; 166650a20714SMintz, Yuval struct qed_igu_info *p_info; 166750a20714SMintz, Yuval 166850a20714SMintz, Yuval if (!sb_info) 166950a20714SMintz, Yuval return 0; 1670fe56b9e6SYuval Mintz 1671fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1672fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1673fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1674fe56b9e6SYuval Mintz 167550a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 167650a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 167750a20714SMintz, Yuval return 0; 16784ac801b7SYuval Mintz } 1679fe56b9e6SYuval Mintz 168050a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 168150a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 168250a20714SMintz, Yuval 168350a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 168450a20714SMintz, Yuval if (!p_block->vector_number) { 168550a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 168650a20714SMintz, Yuval return -EINVAL; 168750a20714SMintz, Yuval } 168850a20714SMintz, Yuval 168950a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 169050a20714SMintz, Yuval p_block->sb_info = NULL; 169150a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 169250a20714SMintz, Yuval p_info->usage.free_cnt++; 169350a20714SMintz, Yuval 1694fe56b9e6SYuval Mintz return 0; 1695fe56b9e6SYuval Mintz } 1696fe56b9e6SYuval Mintz 1697fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1698fe56b9e6SYuval Mintz { 1699fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1700fe56b9e6SYuval Mintz 17014ac801b7SYuval Mintz if (!p_sb) 17024ac801b7SYuval Mintz return; 17034ac801b7SYuval Mintz 1704fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1705fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1706fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1707fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1708fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1709fe56b9e6SYuval Mintz kfree(p_sb); 17103587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1711fe56b9e6SYuval Mintz } 1712fe56b9e6SYuval Mintz 17131a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1714fe56b9e6SYuval Mintz { 1715fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1716fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1717fe56b9e6SYuval Mintz void *p_virt; 1718fe56b9e6SYuval Mintz 1719fe56b9e6SYuval Mintz /* SB struct */ 172060fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 17212591c280SJoe Perches if (!p_sb) 1722fe56b9e6SYuval Mintz return -ENOMEM; 1723fe56b9e6SYuval Mintz 1724fe56b9e6SYuval Mintz /* SB ring */ 1725fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1726fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1727fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1728fe56b9e6SYuval Mintz if (!p_virt) { 1729fe56b9e6SYuval Mintz kfree(p_sb); 1730fe56b9e6SYuval Mintz return -ENOMEM; 1731fe56b9e6SYuval Mintz } 1732fe56b9e6SYuval Mintz 1733fe56b9e6SYuval Mintz /* Status Block setup */ 1734fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1735fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1736fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1737fe56b9e6SYuval Mintz 1738fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1739fe56b9e6SYuval Mintz 1740fe56b9e6SYuval Mintz return 0; 1741fe56b9e6SYuval Mintz } 1742fe56b9e6SYuval Mintz 1743fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1744fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 17451a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1746fe56b9e6SYuval Mintz { 1747fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 17484ac801b7SYuval Mintz int rc = -ENOMEM; 1749fe56b9e6SYuval Mintz u8 pi; 1750fe56b9e6SYuval Mintz 1751fe56b9e6SYuval Mintz /* Look for a free index */ 1752fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 17534ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 17544ac801b7SYuval Mintz continue; 17554ac801b7SYuval Mintz 1756fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1757fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1758fe56b9e6SYuval Mintz *sb_idx = pi; 1759fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 17604ac801b7SYuval Mintz rc = 0; 1761fe56b9e6SYuval Mintz break; 1762fe56b9e6SYuval Mintz } 1763fe56b9e6SYuval Mintz 17644ac801b7SYuval Mintz return rc; 1765fe56b9e6SYuval Mintz } 1766fe56b9e6SYuval Mintz 1767fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1768fe56b9e6SYuval Mintz { 1769fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1770fe56b9e6SYuval Mintz 17714ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 17724ac801b7SYuval Mintz return -ENOMEM; 17734ac801b7SYuval Mintz 1774fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1775fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1776fe56b9e6SYuval Mintz 17774ac801b7SYuval Mintz return 0; 1778fe56b9e6SYuval Mintz } 1779fe56b9e6SYuval Mintz 1780fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1781fe56b9e6SYuval Mintz { 1782fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1783fe56b9e6SYuval Mintz } 1784fe56b9e6SYuval Mintz 1785fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 17861a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1787fe56b9e6SYuval Mintz { 1788cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1789fe56b9e6SYuval Mintz 1790fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1791fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1792fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1793fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1794fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1795fe56b9e6SYuval Mintz break; 1796fe56b9e6SYuval Mintz 1797fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1798fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1799fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1800fe56b9e6SYuval Mintz break; 1801fe56b9e6SYuval Mintz 1802fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1803fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1804fe56b9e6SYuval Mintz break; 1805fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1806fe56b9e6SYuval Mintz break; 1807fe56b9e6SYuval Mintz } 1808fe56b9e6SYuval Mintz 1809fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1810fe56b9e6SYuval Mintz } 1811fe56b9e6SYuval Mintz 1812979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1813979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1814fe56b9e6SYuval Mintz { 1815fe56b9e6SYuval Mintz 18160d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 18170d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1818cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1819cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 18200d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1821cc875c2eSYuval Mintz 1822fe56b9e6SYuval Mintz /* Flush the writes to IGU */ 1823fe56b9e6SYuval Mintz mmiowb(); 1824cc875c2eSYuval Mintz 1825cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1826cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1827979cead3SMintz, Yuval } 1828979cead3SMintz, Yuval 1829979cead3SMintz, Yuval int 1830979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1831979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1832979cead3SMintz, Yuval { 1833979cead3SMintz, Yuval int rc = 0; 1834979cead3SMintz, Yuval 1835979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1836979cead3SMintz, Yuval 18378f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 18388f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 18391a635e48SYuval Mintz if (rc) { 18408f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 18418f16bc97SSudarsana Kalluru return -EINVAL; 18428f16bc97SSudarsana Kalluru } 18438f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 18448f16bc97SSudarsana Kalluru } 18458f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 18468f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 18478f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 18488f16bc97SSudarsana Kalluru 18498f16bc97SSudarsana Kalluru return rc; 1850fe56b9e6SYuval Mintz } 1851fe56b9e6SYuval Mintz 18521a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1853fe56b9e6SYuval Mintz { 1854fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1855fe56b9e6SYuval Mintz 18561408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 18571408cc1fSYuval Mintz return; 18581408cc1fSYuval Mintz 1859fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1860fe56b9e6SYuval Mintz } 1861fe56b9e6SYuval Mintz 1862fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1863b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1864fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1865d031548eSMintz, Yuval u16 igu_sb_id, 1866d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1867fe56b9e6SYuval Mintz { 1868b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1869d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1870fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1871fe56b9e6SYuval Mintz 1872fe56b9e6SYuval Mintz /* Set the data field */ 1873fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1874fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1875fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1876fe56b9e6SYuval Mintz 1877fe56b9e6SYuval Mintz /* Set the control register */ 1878fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1879fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1880fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1881fe56b9e6SYuval Mintz 1882fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1883fe56b9e6SYuval Mintz 1884fe56b9e6SYuval Mintz barrier(); 1885fe56b9e6SYuval Mintz 1886fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1887fe56b9e6SYuval Mintz 1888fe56b9e6SYuval Mintz /* Flush the write to IGU */ 1889fe56b9e6SYuval Mintz mmiowb(); 1890fe56b9e6SYuval Mintz 1891fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1892d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1893d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1894fe56b9e6SYuval Mintz 1895fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1896fe56b9e6SYuval Mintz 1897fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1898fe56b9e6SYuval Mintz do { 1899fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1900fe56b9e6SYuval Mintz 1901fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1902fe56b9e6SYuval Mintz break; 1903fe56b9e6SYuval Mintz 1904fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1905fe56b9e6SYuval Mintz } while (--sleep_cnt); 1906fe56b9e6SYuval Mintz 1907fe56b9e6SYuval Mintz if (!sleep_cnt) 1908fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1909fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1910d031548eSMintz, Yuval val, igu_sb_id); 1911fe56b9e6SYuval Mintz } 1912fe56b9e6SYuval Mintz 1913fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1914fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1915d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1916fe56b9e6SYuval Mintz { 19171ac72433SMintz, Yuval struct qed_igu_block *p_block; 1918b2b897ebSYuval Mintz int pi, i; 1919fe56b9e6SYuval Mintz 19201ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 19211ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 19221ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 19231ac72433SMintz, Yuval igu_sb_id, 19241ac72433SMintz, Yuval p_block->function_id, 19251ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 19261ac72433SMintz, Yuval 1927fe56b9e6SYuval Mintz /* Set */ 1928fe56b9e6SYuval Mintz if (b_set) 1929d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1930fe56b9e6SYuval Mintz 1931fe56b9e6SYuval Mintz /* Clear */ 1932d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1933fe56b9e6SYuval Mintz 1934b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1935b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1936b2b897ebSYuval Mintz u32 val; 1937b2b897ebSYuval Mintz 1938b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1939d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1940d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1941d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1942b2b897ebSYuval Mintz usleep_range(10, 20); 1943b2b897ebSYuval Mintz else 1944b2b897ebSYuval Mintz break; 1945b2b897ebSYuval Mintz } 1946b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1947b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1948b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1949d031548eSMintz, Yuval igu_sb_id); 1950b2b897ebSYuval Mintz 1951fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1952fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1953fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1954d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1955fe56b9e6SYuval Mintz } 1956fe56b9e6SYuval Mintz 1957fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1958fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1959b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1960fe56b9e6SYuval Mintz { 19611ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 19621ac72433SMintz, Yuval struct qed_igu_block *p_block; 19631ac72433SMintz, Yuval u16 igu_sb_id = 0; 19641ac72433SMintz, Yuval u32 val = 0; 1965fe56b9e6SYuval Mintz 1966fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1967fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1968fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1969fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1970fe56b9e6SYuval Mintz 19711ac72433SMintz, Yuval for (igu_sb_id = 0; 19721ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 19731ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 1974fe56b9e6SYuval Mintz 19751ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 19761ac72433SMintz, Yuval !p_block->is_pf || 19771ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 19781ac72433SMintz, Yuval continue; 19791ac72433SMintz, Yuval 1980d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 1981fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 1982fe56b9e6SYuval Mintz b_set); 19831ac72433SMintz, Yuval } 1984fe56b9e6SYuval Mintz 19851ac72433SMintz, Yuval if (b_slowpath) 19861ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 19871ac72433SMintz, Yuval p_info->igu_dsb_id, 19881ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 19891ac72433SMintz, Yuval b_set); 1990fe56b9e6SYuval Mintz } 1991fe56b9e6SYuval Mintz 1992ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1993ebbdcc66SMintz, Yuval { 1994ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 1995ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 1996ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 1997ebbdcc66SMintz, Yuval u16 igu_sb_id; 1998ebbdcc66SMintz, Yuval u32 val, rval; 1999ebbdcc66SMintz, Yuval 2000ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 2001ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 2002ebbdcc66SMintz, Yuval } else { 2003ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 2004ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 2005ebbdcc66SMintz, Yuval */ 2006ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 2007ebbdcc66SMintz, Yuval 2008ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2009ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 2010ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2011ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 2012ebbdcc66SMintz, Yuval p_info->usage.cnt); 2013ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2014ebbdcc66SMintz, Yuval } 2015ebbdcc66SMintz, Yuval 2016ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 2017ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2018ebbdcc66SMintz, Yuval 2019ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 2020ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2021ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2022ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2023ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 2024ebbdcc66SMintz, Yuval 2025ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 2026ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 2027ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 2028ebbdcc66SMintz, Yuval */ 2029ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 2030ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2031ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 2032ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2033ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 2034ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 2035ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 2036ebbdcc66SMintz, Yuval return -EINVAL; 2037ebbdcc66SMintz, Yuval } 2038ebbdcc66SMintz, Yuval 2039ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 2040ebbdcc66SMintz, Yuval * number of VFs. 2041ebbdcc66SMintz, Yuval */ 2042ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 2043ebbdcc66SMintz, Yuval } 2044ebbdcc66SMintz, Yuval } 2045ebbdcc66SMintz, Yuval 2046ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 2047ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 2048ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2049ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 2050ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 2051ebbdcc66SMintz, Yuval 2052ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 2053ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 2054ebbdcc66SMintz, Yuval */ 2055ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 2056ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 2057ebbdcc66SMintz, Yuval 2058ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 2059ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2060ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2061ebbdcc66SMintz, Yuval val = 0; 2062ebbdcc66SMintz, Yuval 2063ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 2064ebbdcc66SMintz, Yuval continue; 2065ebbdcc66SMintz, Yuval 2066ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 2067ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2068ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2069ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2070ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2071ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2072ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 2073ebbdcc66SMintz, Yuval } else if (pf_sbs) { 2074ebbdcc66SMintz, Yuval pf_sbs--; 2075ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2076ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2077ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 2078ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2079ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2080ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2081ebbdcc66SMintz, Yuval } else if (vf_sbs) { 2082ebbdcc66SMintz, Yuval p_block->function_id = 2083ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2084ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 2085ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2086ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2087ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2088ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2089ebbdcc66SMintz, Yuval vf_sbs--; 2090ebbdcc66SMintz, Yuval } else { 2091ebbdcc66SMintz, Yuval p_block->function_id = 0; 2092ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2093ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2094ebbdcc66SMintz, Yuval } 2095ebbdcc66SMintz, Yuval 2096ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2097ebbdcc66SMintz, Yuval p_block->function_id); 2098ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2099ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2100ebbdcc66SMintz, Yuval p_block->vector_number); 2101ebbdcc66SMintz, Yuval 2102ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 2103ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2104ebbdcc66SMintz, Yuval 2105ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 2106ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2107ebbdcc66SMintz, Yuval 2108ebbdcc66SMintz, Yuval if (rval != val) { 2109ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 2110ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 2111ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 2112ebbdcc66SMintz, Yuval 2113ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2114ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2115ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2116ebbdcc66SMintz, Yuval igu_sb_id, 2117ebbdcc66SMintz, Yuval p_block->function_id, 2118ebbdcc66SMintz, Yuval p_block->is_pf, 2119ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 2120ebbdcc66SMintz, Yuval } 2121ebbdcc66SMintz, Yuval } 2122ebbdcc66SMintz, Yuval 2123ebbdcc66SMintz, Yuval return 0; 2124ebbdcc66SMintz, Yuval } 2125ebbdcc66SMintz, Yuval 2126d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2127d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 21284ac801b7SYuval Mintz { 21294ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 2130d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 21314ac801b7SYuval Mintz struct qed_igu_block *p_block; 21324ac801b7SYuval Mintz 2133d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 21344ac801b7SYuval Mintz 21354ac801b7SYuval Mintz /* Fill the block information */ 2136d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 21374ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2138d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 21391ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 21404ac801b7SYuval Mintz } 21414ac801b7SYuval Mintz 21421a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2143fe56b9e6SYuval Mintz { 2144fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2145d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2146d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2147d749dd0dSMintz, Yuval u16 igu_sb_id; 2148fe56b9e6SYuval Mintz 214960fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2150fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2151fe56b9e6SYuval Mintz return -ENOMEM; 2152fe56b9e6SYuval Mintz 2153fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2154fe56b9e6SYuval Mintz 2155d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2156d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2157d749dd0dSMintz, Yuval 2158d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 21591408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 21601408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 21611408cc1fSYuval Mintz 21621408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 21631408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 21641408cc1fSYuval Mintz } 21651408cc1fSYuval Mintz 2166d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2167d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2168d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2169d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2170d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2171fe56b9e6SYuval Mintz 2172d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2173d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2174d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2175d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2176d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2177fe56b9e6SYuval Mintz 21781ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2179726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2180d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2181d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2182d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 21831408cc1fSYuval Mintz /* Available for VFs of this PF */ 2184d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2185d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2186d749dd0dSMintz, Yuval 21871ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2188726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 21891408cc1fSYuval Mintz } 21905a1f965aSMintz, Yuval 2191d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2192ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 21935a1f965aSMintz, Yuval */ 2194d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2195d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2196d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2197d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2198d749dd0dSMintz, Yuval } 21995a1f965aSMintz, Yuval 2200d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2201d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2202d749dd0dSMintz, Yuval * everything. 2203d749dd0dSMintz, Yuval */ 2204d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2205d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2206d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2207d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2208d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2209d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2210d749dd0dSMintz, Yuval } 2211d749dd0dSMintz, Yuval } 2212d749dd0dSMintz, Yuval 2213d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 22145a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2215d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2216d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 22175a1f965aSMintz, Yuval return -EINVAL; 22185a1f965aSMintz, Yuval } 2219d749dd0dSMintz, Yuval 2220d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2221726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2222726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2223fe56b9e6SYuval Mintz 2224d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2225ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2226d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2227726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2228fe56b9e6SYuval Mintz 2229fe56b9e6SYuval Mintz return 0; 2230fe56b9e6SYuval Mintz } 2231fe56b9e6SYuval Mintz 2232fe56b9e6SYuval Mintz /** 2233fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 2234fe56b9e6SYuval Mintz * 2235fe56b9e6SYuval Mintz * @param p_hwfn 2236fe56b9e6SYuval Mintz */ 2237fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2238fe56b9e6SYuval Mintz { 22391a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2240fe56b9e6SYuval Mintz 2241fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2242fe56b9e6SYuval Mintz } 2243fe56b9e6SYuval Mintz 2244fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2245fe56b9e6SYuval Mintz { 2246fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2247fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2248fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2249fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 22501a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 22511a635e48SYuval Mintz u64 intr_status = 0; 2252fe56b9e6SYuval Mintz 2253fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2254fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2255fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2256fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2257fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2258fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2259fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2260fe56b9e6SYuval Mintz 2261fe56b9e6SYuval Mintz return intr_status; 2262fe56b9e6SYuval Mintz } 2263fe56b9e6SYuval Mintz 2264fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2265fe56b9e6SYuval Mintz { 2266fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 2267fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 2268fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2269fe56b9e6SYuval Mintz } 2270fe56b9e6SYuval Mintz 2271fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2272fe56b9e6SYuval Mintz { 227360fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2274fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 2275fe56b9e6SYuval Mintz return -ENOMEM; 2276fe56b9e6SYuval Mintz 2277fe56b9e6SYuval Mintz return 0; 2278fe56b9e6SYuval Mintz } 2279fe56b9e6SYuval Mintz 2280fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2281fe56b9e6SYuval Mintz { 2282fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 22833587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 2284fe56b9e6SYuval Mintz } 2285fe56b9e6SYuval Mintz 22861a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2287fe56b9e6SYuval Mintz { 2288fe56b9e6SYuval Mintz int rc = 0; 2289fe56b9e6SYuval Mintz 2290fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 229183aeb933SYuval Mintz if (rc) 22922591c280SJoe Perches return rc; 22932591c280SJoe Perches 22942591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 22952591c280SJoe Perches if (rc) 22962591c280SJoe Perches return rc; 22972591c280SJoe Perches 22982591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 229983aeb933SYuval Mintz 2300fe56b9e6SYuval Mintz return rc; 2301fe56b9e6SYuval Mintz } 2302fe56b9e6SYuval Mintz 2303fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2304fe56b9e6SYuval Mintz { 2305fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2306cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2307fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 2308fe56b9e6SYuval Mintz } 2309fe56b9e6SYuval Mintz 23101a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2311fe56b9e6SYuval Mintz { 23120d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 23130d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2314fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2315fe56b9e6SYuval Mintz } 2316fe56b9e6SYuval Mintz 23174ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 23184ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2319fe56b9e6SYuval Mintz { 2320fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2321fe56b9e6SYuval Mintz 23224ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 23234ac801b7SYuval Mintz return; 2324fe56b9e6SYuval Mintz 2325726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2326fe56b9e6SYuval Mintz } 23278f16bc97SSudarsana Kalluru 23288f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 23298f16bc97SSudarsana Kalluru { 23308f16bc97SSudarsana Kalluru int i; 23318f16bc97SSudarsana Kalluru 23328f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 23338f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 23348f16bc97SSudarsana Kalluru } 2335722003acSSudarsana Reddy Kalluru 2336722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2337722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2338722003acSSudarsana Reddy Kalluru { 2339722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 2340722003acSSudarsana Reddy Kalluru int rc; 2341722003acSSudarsana Reddy Kalluru 2342722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2343722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2344722003acSSudarsana Reddy Kalluru return -EINVAL; 2345722003acSSudarsana Reddy Kalluru } 2346722003acSSudarsana Reddy Kalluru 2347722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2348722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2349722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2, 0); 2350722003acSSudarsana Reddy Kalluru if (rc) { 2351722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2352722003acSSudarsana Reddy Kalluru return rc; 2353722003acSSudarsana Reddy Kalluru } 2354722003acSSudarsana Reddy Kalluru 2355722003acSSudarsana Reddy Kalluru if (tx) 2356722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2357722003acSSudarsana Reddy Kalluru else 2358722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2359722003acSSudarsana Reddy Kalluru 2360722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2361722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2362722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 2363722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2, 0); 2364722003acSSudarsana Reddy Kalluru if (rc) { 2365722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2366722003acSSudarsana Reddy Kalluru return rc; 2367722003acSSudarsana Reddy Kalluru } 2368722003acSSudarsana Reddy Kalluru 2369722003acSSudarsana Reddy Kalluru return rc; 2370722003acSSudarsana Reddy Kalluru } 2371